Programmable resistive-switch nanowire transistor logic circuits.

PubMed

Shim, Wooyoung; Yao, Jun; Lieber, Charles M

2014-09-10

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

2000-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing: Digital Timing Analysis Tools and Techniques. Articles in this issue include: SX and SX-A Series Devices Power Sequencing; JTAG and SXISX-AISX-S Series Devices; Analysis Techniques (i.e., notes on digital timing analysis tools and techniques); Status of the Radiation Hard reconfigurable Field Programmable Gate Array Program, Input Transition Times; Apollo Guidance Computer Logic Study; RT54SX32S Prototype Data Sets; A54SX32A - 0.22 micron/UMC Test Results; Ramtron FM1608 FRAM; and Analysis of VHDL Code and Synthesizer Output.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

NASA Astrophysics Data System (ADS)

Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

2012-01-01

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

Logic operations based on magnetic-vortex-state networks.

PubMed

Jung, Hyunsung; Choi, Youn-Seok; Lee, Ki-Suk; Han, Dong-Soo; Yu, Young-Sang; Im, Mi-Young; Fischer, Peter; Kim, Sang-Koog

2012-05-22

Logic operations based on coupled magnetic vortices were experimentally demonstrated. We utilized a simple chain structure consisting of three physically separated but dipolar-coupled vortex-state Permalloy disks as well as two electrodes for application of the logical inputs. We directly monitored the vortex gyrations in the middle disk, as the logical output, by time-resolved full-field soft X-ray microscopy measurements. By manipulating the relative polarization configurations of both end disks, two different logic operations are programmable: the XOR operation for the parallel polarization and the OR operation for the antiparallel polarization. This work paves the way for new-type programmable logic gates based on the coupled vortex-gyration dynamics achievable in vortex-state networks. The advantages are as follows: a low-power input signal by means of resonant vortex excitation, low-energy dissipation during signal transportation by selection of low-damping materials, and a simple patterned-array structure.

Memristor-based programmable logic array (PLA) and analysis as Memristive networks.

PubMed

Lee, Kwan-Hee; Lee, Sang-Jin; Kim, Seok-Man; Cho, Kyoungrok

2013-05-01

A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors.

Programmable logic construction kits for hyper-real-time neuronal modeling.

PubMed

Guerrero-Rivera, Ruben; Morrison, Abigail; Diesmann, Markus; Pearce, Tim C

2006-11-01

Programmable logic designs are presented that achieve exact integration of leaky integrate-and-fire soma and dynamical synapse neuronal models and incorporate spike-time dependent plasticity and axonal delays. Highly accurate numerical performance has been achieved by modifying simpler forward-Euler-based circuitry requiring minimal circuit allocation, which, as we show, behaves equivalently to exact integration. These designs have been implemented and simulated at the behavioral and physical device levels, demonstrating close agreement with both numerical and analytical results. By exploiting finely grained parallelism and single clock cycle numerical iteration, these designs achieve simulation speeds at least five orders of magnitude faster than the nervous system, termed here hyper-real-time operation, when deployed on commercially available field-programmable gate array (FPGA) devices. Taken together, our designs form a programmable logic construction kit of commonly used neuronal model elements that supports the building of large and complex architectures of spiking neuron networks for real-time neuromorphic implementation, neurophysiological interfacing, or efficient parameter space investigations.

Interface For Dual-Channel MIL-STD-1553 Data Bus

NASA Technical Reports Server (NTRS)

Davies, Bryan L.; Heaps, Timothy L.

1992-01-01

Digital electronic subsystem made of commercially available programmable logic arrays and discrete logic devices serves as interface between microprocessor and dual-channel MIL-STD-1553 data bus. Subsystem consumes only 800 mW of power. Provides flexibility in that it is controllable via firmware. Includes only two reading-and-writing ports: one for status and control signals, other for transmission and reception of data.

An acceleration framework for synthetic aperture radar algorithms

NASA Astrophysics Data System (ADS)

Kim, Youngsoo; Gloster, Clay S.; Alexander, Winser E.

2017-04-01

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.

Design and Implementation of an MC68020-Based Educational Computer Board

DTIC Science & Technology

1989-12-01

device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to initialize...MHz. It includes four * Static Random Access Memory (SRAM) chips which provide a storage of 32K bytes. Two Programmable Array Logic (PAL) chips...device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to

A programmable computational image sensor for high-speed vision

NASA Astrophysics Data System (ADS)

Yang, Jie; Shi, Cong; Long, Xitian; Wu, Nanjian

2013-08-01

In this paper we present a programmable computational image sensor for high-speed vision. This computational image sensor contains four main blocks: an image pixel array, a massively parallel processing element (PE) array, a row processor (RP) array and a RISC core. The pixel-parallel PE is responsible for transferring, storing and processing image raw data in a SIMD fashion with its own programming language. The RPs are one dimensional array of simplified RISC cores, it can carry out complex arithmetic and logic operations. The PE array and RP array can finish great amount of computation with few instruction cycles and therefore satisfy the low- and middle-level high-speed image processing requirement. The RISC core controls the whole system operation and finishes some high-level image processing algorithms. We utilize a simplified AHB bus as the system bus to connect our major components. Programming language and corresponding tool chain for this computational image sensor are also developed.

Architecture and data processing alternatives for the TSE computer. Volume 3: Execution of a parallel counting algorithm using array logic (Tse) devices

NASA Technical Reports Server (NTRS)

Metcalfe, A. G.; Bodenheimer, R. E.

1976-01-01

A parallel algorithm for counting the number of logic-l elements in a binary array or image developed during preliminary investigation of the Tse concept is described. The counting algorithm is implemented using a basic combinational structure. Modifications which improve the efficiency of the basic structure are also presented. A programmable Tse computer structure is proposed, along with a hardware control unit, Tse instruction set, and software program for execution of the counting algorithm. Finally, a comparison is made between the different structures in terms of their more important characteristics.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Implementation of a Configurable Fault Tolerant Processor (CFTP) Using Internal Triple Modular Redundancy (TMR)

DTIC Science & Technology

2005-12-01

Upsets in SRAM FPGAs,” Military and Aerospace Applications of Programmable Logic Devices, September 2002. 8. Wakerly , John F,. “Microcomputer...change. The goal of the Configurable Fault Tolerant Processor (CFTP) Project is to explore, develop and demonstrate the applicability of using off-the...develop and demonstrate the applicability of using commercial-of-the-shelf (COTS) Field Programmable Gate Arrays (FPGA) in the design of

FPGA-based multiprocessor system for injection molding control.

PubMed

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

2012-10-18

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

A Modular Approach to Arithmetic and Logic Unit Design on a Reconfigurable Hardware Platform for Educational Purpose

NASA Astrophysics Data System (ADS)

Oztekin, Halit; Temurtas, Feyzullah; Gulbag, Ali

The Arithmetic and Logic Unit (ALU) design is one of the important topics in Computer Architecture and Organization course in Computer and Electrical Engineering departments. There are ALU designs that have non-modular nature to be used as an educational tool. As the programmable logic technology has developed rapidly, it is feasible that ALU design based on Field Programmable Gate Array (FPGA) is implemented in this course. In this paper, we have adopted the modular approach to ALU design based on FPGA. All the modules in the ALU design are realized using schematic structure on Altera's Cyclone II Development board. Under this model, the ALU content is divided into four distinct modules. These are arithmetic unit except for multiplication and division operations, logic unit, multiplication unit and division unit. User can easily design any size of ALU unit since this approach has the modular nature. Then, this approach was applied to microcomputer architecture design named BZK.SAU.FPGA10.0 instead of the current ALU unit.

Electrokinetic Microactuator Arrays for Control of Vehicles

DTIC Science & Technology

2002-08-01

programmable logic array (PLA) content in each unit cell....................46 Chapter 4 4.1 Schematic showing electroosmotic flow induced by an...control situations involved in propulsion systems, spanning from con- trol of mixing in advanced gas turbine combustors, to active control of surge and... electroosmotic flow, shown schematically in Fig. 4.1, results when an electric field is applied to a liquid electrolyte in contact with a charged solid

Automated ILA design for synchronous sequential circuits

NASA Technical Reports Server (NTRS)

Liu, M. N.; Liu, K. Z.; Maki, G. K.; Whitaker, S. R.

1991-01-01

An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This technique utilizes linear algebra to produce the design equations. The ILA realization of synchronous sequential logic can be fully automated with a computer program. A programmable design procedure is proposed to fullfill the design task and layout generation. A software algorithm in the C language has been developed and tested to generate 1 micron CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.

A programmable CCD driver circuit for multiphase CCD operation

NASA Technical Reports Server (NTRS)

Ewin, Audrey J.; Reed, Kenneth V.

1989-01-01

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

Field-programmable logic devices with optical input-output.

PubMed

Szymanski, T H; Saint-Laurent, M; Tyan, V; Au, A; Supmonchai, B

2000-02-10

A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA's) on a 2 mm x 2 mm die. The devices were fabricated through the Lucent Technologies-Advanced Research Projects Agency-Consortium for Optical and Optoelectronic Technologies in Computing (Lucent/ARPA/COOP) workshop by use of 0.5-microm complementary metal-oxide semiconductor-self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 x 4 crossbar switches, which can realize more than 190 x 10(6) unique programmable input-output permutations. The same device scaled to a 2 cm x 2 cm substrate could support as many as 4000 optical I/O and 1 Tbit/s of optical I/O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms.

PubMed

Pruttivarasin, Thaned; Katori, Hidetoshi

2015-11-01

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp; Katori, Hidetoshi; Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Assurance of Complex Electronics. What Path Do We Take?

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

Nanowire nanocomputer as a finite-state machine.

PubMed

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2014-02-18

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.

Nanowire nanocomputer as a finite-state machine

PubMed Central

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F.; Ellenbogen, James C.; Lieber, Charles M.

2014-01-01

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom–up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future. PMID:24469812

A novel productivity-driven logic element for field-programmable devices

NASA Astrophysics Data System (ADS)

Marconi, Thomas; Bertels, Koen; Gaydadjiev, Georgi

2014-06-01

Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.

Experimental demonstration of programmable multi-functional spin logic cell based on spin Hall effect

NASA Astrophysics Data System (ADS)

Zhang, X.; Wan, C. H.; Yuan, Z. H.; Fang, C.; Kong, W. J.; Wu, H.; Zhang, Q. T.; Tao, B. S.; Han, X. F.

2017-04-01

Confronting with the gigantic volume of data produced every day, raising integration density by reducing the size of devices becomes harder and harder to meet the ever-increasing demand for high-performance computers. One feasible path is to actualize more logic functions in one cell. In this respect, we experimentally demonstrate a prototype spin-orbit torque based spin logic cell integrated with five frequently used logic functions (AND, OR, NOT, NAND and NOR). The cell can be easily programmed and reprogrammed to perform desired function. Furthermore, the information stored in cells is symmetry-protected, making it possible to expand into logic gate array where the cell can be manipulated one by one without changing the information of other undesired cells. This work provides a prospective example of multi-functional spin logic cell with reprogrammability and nonvolatility, which will advance the application of spin logic devices.

FPGA-Based Multiprocessor System for Injection Molding Control

PubMed Central

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J.; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P.; Osornio-Rios, Roque A.

2012-01-01

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

A synchronous serial bus for multidimensional array acoustic logging tool

NASA Astrophysics Data System (ADS)

Men, Baiyong; Ju, Xiaodong; Lu, Junqiang; Qiao, Wenxiao

2016-12-01

In high-temperature and spatial borehole applications, a distributed structure is employed in a multidimensional array acoustic logging tool (MDALT) based on a phased array technique for electronic systems. However, new challenges, such as synchronous multichannel data acquisition, multinode real-time control and bulk data transmission in a limited interval, have emerged. To address these challenges, we developed a synchronous serial bus (SSB) in this study. SSB works in a half-duplex mode via a master-slave architecture. It also consists of a single master, several slaves, a differential clock line and a differential data line. The clock line is simplex, whereas the data line is half-duplex and synchronous to the clock line. A reliable communication between the master and the slaves with real-time adjustment of synchronisation is achieved by rationally designing the frame format and protocol of communication and by introducing a scramble code and a Hamming error-correcting code. The control logic of the master and the slaves is realized in field programmable gate array (FPGA) or complex programmable logic device (CPLD). The clock speed of SSB is 10 MHz, the effective data rate of the bulk data transmission is over 99%, and the synchronous errors amongst the slaves are less than 10 ns. Room-temperature test, high-temperature test (175 °C) and field test demonstrate that the proposed SSB is qualified for MDALT.

A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

PubMed

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2013-12-20

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

PubMed Central

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2014-01-01

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

Programmable logic controller performance enhancement by field programmable gate array based design.

PubMed

Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

2015-01-01

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

Filling the Assurance Gap on Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Software Process Assurance for Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

High-performance reconfigurable coincidence counting unit based on a field programmable gate array.

PubMed

Park, Byung Kwon; Kim, Yong-Su; Kwon, Osung; Han, Sang-Wook; Moon, Sung

2015-05-20

We present a high-performance reconfigurable coincidence counting unit (CCU) using a low-end field programmable gate array (FPGA) and peripheral circuits. Because of the flexibility guaranteed by the FPGA program, we can easily change system parameters, such as internal input delays, coincidence configurations, and the coincidence time window. In spite of a low-cost implementation, the proposed CCU architecture outperforms previous ones in many aspects: it has 8 logic inputs and 4 coincidence outputs that can measure up to eight-fold coincidences. The minimum coincidence time window and the maximum input frequency are 0.47 ns and 163 MHz, respectively. The CCU will be useful in various experimental research areas, including the field of quantum optics and quantum information.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

NASA Astrophysics Data System (ADS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-03-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

NASA Astrophysics Data System (ADS)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

FPGA-based gating and logic for multichannel single photon counting

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G

2012-01-01

We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidencemore » measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)« less

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Software Process Assurance for Complex Electronics (SPACE)

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Compton suppression and event triggering in a commercial data acquisition system

NASA Astrophysics Data System (ADS)

Tabor, Samuel; Caussyn, D. D.; Tripathi, Vandana; Vonmoss, J.; Liddick, S. N.

2012-10-01

A number of groups are starting to use flash digitizer systems to directly convert the preamplifier signals of high-resolution Ge detectors to a stream of digital data. Some digitizers are also equipped with software constant fraction discriminator algorithms capable of operating on the resulting digital data stream to provide timing information. Because of the dropping cost per channel of these systems, it should now be possible to also connect outputs of the Bismuth Germanate (BGO) scintillators used for Compton suppression to other digitizer inputs so that BGO logic signals can also be available in the same system. This provides the possibility to perform all the Compton suppression and multiplicity trigger logic within the digital system, thus eliminating the need for separate timing filter amplifiers (TFA), constant fraction discriminators (CFD), logic units, and lots of cables. This talk will describe the performance of such a system based on Pixie16 modules from XIA LLC with custom field programmable gate array (FPGA) programming for an array of Compton suppressed single Ge crystal and 4-crystal ``Clover'' detector array along with optional particle detectors. Initial tests of the system have produced results comparable with the current traditional system of individual electronics and peak sensing analog to digital converters. The advantages of the all digital system will be discussed.

Application of SEU imaging for analysis of device architecture using a 25 MeV/u 86Kr ion microbeam at HIRFL

NASA Astrophysics Data System (ADS)

Liu, Tianqi; Yang, Zhenlei; Guo, Jinlong; Du, Guanghua; Tong, Teng; Wang, Xiaohui; Su, Hong; Liu, Wenjing; Liu, Jiande; Wang, Bin; Ye, Bing; Liu, Jie

2017-08-01

The heavy-ion imaging of single event upset (SEU) in a flash-based field programmable gate array (FPGA) device was carried out for the first time at Heavy Ion Research Facility in Lanzhou (HIRFL). The three shift register chains with separated input and output configurations in device under test (DUT) were used to identify the corresponding logical area rapidly once an upset occurred. The logic units in DUT were partly configured in order to distinguish the registers in SEU images. Based on the above settings, the partial architecture of shift register chains in DUT was imaged by employing the microbeam of 86Kr ion with energy of 25 MeV/u in air. The results showed that the physical distribution of registers in DUT had a high consistency with its logical arrangement by comparing SEU image with logic configuration in scanned area.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Test Bus Evaluation

DTIC Science & Technology

1998-04-01

selected is statistically based on the total number of faults and the failure rate distribution in the system under test. The fault set is also...implemented the BPM and system level emulation consolidation logic as well as statistics counters for cache misses and various bus transactions. These...instruction F22 Advanced Tactical Fighter FET Field Effect Transitor FF Flip-Flop FM Failures/Milhon hours C-3 FPGA Field Programmable Gate Array GET

Standard Transistor Array (Star): SIMLOG/TESTGN programmer's guide, volume 2, addendum 2

NASA Technical Reports Server (NTRS)

Carroll, B. D.

1979-01-01

A brief introduction to the SIMLOG/TESTGN system of programs is given. SIMLOG is a logic simulation program, whereas TESTGN is a program for generating test sequences from output produced by SIMLOG. The structures of the two programs are described. Data base, main program, and subprogram details are also given. Guidelines for program modifications are discussed. Commented program listings are included.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

PubMed

Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

2007-06-01

A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

Programmable Logic Controllers.

ERIC Educational Resources Information Center

Insolia, Gerard; Anderson, Kathleen

This document contains a 40-hour course in programmable logic controllers (PLC), developed for a business-industry technology resource center for firms in eastern Pennsylvania by Northampton Community College. The 10 units of the course cover the following: (1) introduction to programmable logic controllers; (2) DOS primer; (3) prerequisite…

Statistical Validation of a New Python-based Military Workforce Simulation Model

DTIC Science & Technology

2014-12-30

also having a straightforward syntax that is accessible to non-programmers. Furthermore, it is supported by an impressive variety of scientific... accessed by a given element of model logic or line of code. For example, in Arena, data arrays, queues and the simulation clock are part of the...global scope and are therefore accessible anywhere in the model. The disadvantage of scopes is that all names in a scope must be unique. If more than

Multiple-Valued Programmable Logic Array Minimization by Simulated Annealing

DTIC Science & Technology

1992-02-10

time is controllable, allowing one to tradeoff time for minimalit ’. It has been incorporated in the HAMLET PLA minimization tool. AcOSSIOn P? DTTC TAB C...specified along the horizontal axis. Each slice represents one temperature. The slice in the very front represents the highest and starting ...rectangle with a pair of adjacent 2’s in between. This func- tion can yield five product terms by a sequence of reshape moves starting from four

CORDIC-based digital signal processing (DSP) element for adaptive signal processing

NASA Astrophysics Data System (ADS)

Bolstad, Gregory D.; Neeld, Kenneth B.

1995-04-01

The High Performance Adaptive Weight Computation (HAWC) processing element is a CORDIC based application specific DSP element that, when connected in a linear array, can perform extremely high throughput (100s of GFLOPS) matrix arithmetic operations on linear systems of equations in real time. In particular, it very efficiently performs the numerically intense computation of optimal least squares solutions for large, over-determined linear systems. Most techniques for computing solutions to these types of problems have used either a hard-wired, non-programmable systolic array approach, or more commonly, programmable DSP or microprocessor approaches. The custom logic methods can be efficient, but are generally inflexible. Approaches using multiple programmable generic DSP devices are very flexible, but suffer from poor efficiency and high computation latencies, primarily due to the large number of DSP devices that must be utilized to achieve the necessary arithmetic throughput. The HAWC processor is implemented as a highly optimized systolic array, yet retains some of the flexibility of a programmable data-flow system, allowing efficient implementation of algorithm variations. This provides flexible matrix processing capabilities that are one to three orders of magnitude less expensive and more dense than the current state of the art, and more importantly, allows a realizable solution to matrix processing problems that were previously considered impractical to physically implement. HAWC has direct applications in RADAR, SONAR, communications, and image processing, as well as in many other types of systems.

Programmable Logic Controllers. Teacher Edition.

ERIC Educational Resources Information Center

Rauh, Bob; Kaltwasser, Stan

These materials were developed for a seven-unit secondary or postsecondary education course on programmable logic controllers (PLCs) that treats most of the skills needed to work effectively with PLCs as programming skills. The seven units of the course cover the following topics: fundamentals of programmable logic controllers; contracts, timers,…

General purpose programmable accelerator board

DOEpatents

Robertson, Perry J.; Witzke, Edward L.

2001-01-01

A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

Optimized smith waterman processor design for breast cancer early diagnosis

NASA Astrophysics Data System (ADS)

Nurdin, D. S.; Isa, M. N.; Ismail, R. C.; Ahmad, M. I.

2017-09-01

This paper presents an optimized design of Processing Element (PE) of Systolic Array (SA) which implements affine gap penalty Smith Waterman (SW) algorithm on the Xilinx Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) for Deoxyribonucleic Acid (DNA) sequence alignment. The PE optimization aims to reduce PE logic resources to increase number of PEs in FPGA for higher degree of parallelism during alignment matrix computations. This is useful for aligning long DNA-based disease sequence such as Breast Cancer (BC) for early diagnosis. The optimized PE architecture has the smallest PE area with 15 slices in a PE and 776 PEs implemented in the Virtex - 6 FPGA.

Software Safety Assurance of Programmable Logic

NASA Technical Reports Server (NTRS)

Berens, Kalynnda

2002-01-01

Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

Note: a 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy.

PubMed

Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A M

2012-09-01

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Note: A 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy

NASA Astrophysics Data System (ADS)

Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A. M.

2012-09-01

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Programmable pulse generator based on programmable logic and direct digital synthesis.

PubMed

Suchenek, M; Starecki, T

2012-12-01

The paper presents a new approach of pulse generation which results in both wide range tunability and high accuracy of the output pulses. The concept is based on the use of programmable logic and direct digital synthesis. The programmable logic works as a set of programmable counters, while direct digital synthesis (DDS) as the clock source. Use of DDS as the clock source results in stability of the output pulses comparable to the stability of crystal oscillators and quasi-continuous tuning of the output frequency.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

NASA Astrophysics Data System (ADS)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

2014-02-01

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of datamore » acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.« less

Implementing neural nets with programmable logic

NASA Technical Reports Server (NTRS)

Vidal, Jacques J.

1988-01-01

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

Fast and robust control of nanopositioning systems: Performance limits enabled by field programmable analog arrays.

PubMed

Baranwal, Mayank; Gorugantu, Ram S; Salapaka, Srinivasa M

2015-08-01

This paper aims at control design and its implementation for robust high-bandwidth precision (nanoscale) positioning systems. Even though modern model-based control theoretic designs for robust broadband high-resolution positioning have enabled orders of magnitude improvement in performance over existing model independent designs, their scope is severely limited by the inefficacies of digital implementation of the control designs. High-order control laws that result from model-based designs typically have to be approximated with reduced-order systems to facilitate digital implementation. Digital systems, even those that have very high sampling frequencies, provide low effective control bandwidth when implementing high-order systems. In this context, field programmable analog arrays (FPAAs) provide a good alternative to the use of digital-logic based processors since they enable very high implementation speeds, moreover with cheaper resources. The superior flexibility of digital systems in terms of the implementable mathematical and logical functions does not give significant edge over FPAAs when implementing linear dynamic control laws. In this paper, we pose the control design objectives for positioning systems in different configurations as optimal control problems and demonstrate significant improvements in performance when the resulting control laws are applied using FPAAs as opposed to their digital counterparts. An improvement of over 200% in positioning bandwidth is achieved over an earlier digital signal processor (DSP) based implementation for the same system and same control design, even when for the DSP-based system, the sampling frequency is about 100 times the desired positioning bandwidth.

KM3NeT Digital Optical Module electronics

NASA Astrophysics Data System (ADS)

Real, Diego

2016-04-01

The KM3NeT collaboration is currently building of a neutrino telescope with a volume of several cubic kilometres at the bottom of the Mediterranean Sea. The telescope consists of a matrix of Digital Optical Modules that will detect the Cherenkov light originated by the interaction of the neutrinos in the proximity of the detector. This contribution describes the main components of the read-out electronics of the Digital Optical Module: the Power Board, which delivers all the power supply required by the Digital Optical Molule electronics; the Central Logic Board, the main core of the read-out system, hosting 31 Time to Digital Converters with 1 ns resolution and the White Rabbit protocol embedded in the Central Logic Board Field Programmable Gate Array; the Octopus boards, that transfer the Low Voltage Digital Signals from the PMT bases to the Central Logic Board and finally the PMT bases, in charge of converting the analogue signal produced in the 31 3" PMTs into a Low Voltage Digital Signal.

Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lashin, A. V., E-mail: LashinAV@lhp.ru; Kozyrev, A. V.

One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

A three-sided rearrangeable switching network for a binary fat tree

NASA Astrophysics Data System (ADS)

Yen, Mao-Hsu; Yu, Chu; Shin, Haw-Yun; Chen, Sao-Jie

2011-06-01

A binary fat tree needs an internal node to interconnect the left-children, right-children and parent terminals to each other. In this article, we first propose a three-stage, 3-sided rearrangeable switching network for the implementation of a binary fat tree. The main component of this 3-sided switching network (3SSN) consists of a polygonal switch block (PSB) interconnected by crossbars. With the same size and the same number of switches as our 3SSN, a three-stage, 3-sided clique-based switching network is shown to be not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters has been determined to minimise the number of switches. We derive that a rearrangeable 3-sided switching network with switches proportional to N 3/2 is most suitable to interconnect N terminals. Moreover, we propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of logic blocks interconnected by our 3SSN, such that the logic blocks in this PFPGA can be grouped into clusters to implement different logic functions. Since the programmable switches usually have high resistance and capacitance and occupy a large area, we have to consider the effect of the 3SSN structure and the granularity of its cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that the switch and speed performances are significantly improved. Based on the experimental results, we can determine the parameters of PFPGA for the VLSI implementation.

Telescope Array Control System Based on Wireless Touch Screen Platform

NASA Astrophysics Data System (ADS)

Fu, X. N.; Huang, L.; Wei, J. Y.

2016-07-01

GWAC (Ground-based Wide Angle Cameras) are the ground-based observational instruments of the Sino-French cooperation SVOM (Space Variable Objects Monitor) astronomical satellite, and Mini-GWAC is a pathfinder and supplement of GWAC. In the context of the Mini-GWAC telescope array, this paper introduces the design and implementation of a kind of telescope array control system, which is based on wireless serial interface module to communicate. We describe the development and implementation of the system in detail in terms of control system principle, system hardware structure, software design, experiment, and test. The system uses the touch-control PC which is based on the Windows CE system as the upper-computer, the wireless transceiver module and PLC (Programmable Logic Controller) as the core. It has the advantages of low cost, reliable data transmission, and simple operation. So far, the control system has been applied to Mini-GWAC successfully.

Telescope Array Control System Based on Wireless Touch Screen Platform

NASA Astrophysics Data System (ADS)

Fu, Xia-nan; Huang, Lei; Wei, Jian-yan

2017-10-01

Ground-based Wide Angle Cameras (GMAC) are the ground-based observational facility for the SVOM (Space Variable Object Monitor) astronomical satellite of Sino-French cooperation, and Mini-GWAC is the pathfinder and supplement of GWAC. In the context of the Mini-GWAC telescope array, this paper introduces the design and implementation of a kind of telescope array control system based on the wireless touch screen platform. We describe the development and implementation of the system in detail in terms of control system principle, system hardware structure, software design, experiment, and test etc. The system uses a touch-control PC which is based on the Windows CE system as the upper computer, while the wireless transceiver module and PLC (Programmable Logic Controller) are taken as the system kernel. It has the advantages of low cost, reliable data transmission, and simple operation. And the control system has been applied to the Mini-GWAC successfully.

Optical reversible programmable Boolean logic unit.

PubMed

Chattopadhyay, Tanay

2012-07-20

Computing with reversibility is the only way to avoid dissipation of energy associated with bit erase. So, a reversible microprocessor is required for future computing. In this paper, a design of a simple all-optical reversible programmable processor is proposed using a polarizing beam splitter, liquid crystal-phase spatial light modulators, a half-wave plate, and plane mirrors. This circuit can perform 16 logical operations according to three programming inputs. Also, inputs can be easily recovered from the outputs. It is named the "reversible programmable Boolean logic unit (RPBLU)." The logic unit is the basic building block of many complex computational operations. Hence the design is important in sense. Two orthogonally polarized lights are defined here as two logical states, respectively.

Circuit for high resolution decoding of multi-anode microchannel array detectors

NASA Technical Reports Server (NTRS)

Kasle, David B. (Inventor)

1995-01-01

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Programmable hardware for reconfigurable computing systems

NASA Astrophysics Data System (ADS)

Smith, Stephen

1996-10-01

In 1945 the work of J. von Neumann and H. Goldstein created the principal architecture for electronic computation that has now lasted fifty years. Nevertheless alternative architectures have been created that have computational capability, for special tasks, far beyond that feasible with von Neumann machines. The emergence of high capacity programmable logic devices has made the realization of these architectures practical. The original ENIAC and EDVAC machines were conceived to solve special mathematical problems that were far from today's concept of 'killer applications.' In a similar vein programmable hardware computation is being used today to solve unique mathematical problems. Our programmable hardware activity is focused on the research and development of novel computational systems based upon the reconfigurability of our programmable logic devices. We explore our programmable logic architectures and their implications for programmable hardware. One programmable hardware board implementation is detailed.

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

Field-Free Programmable Spin Logics via Chirality-Reversible Spin-Orbit Torque Switching.

PubMed

Wang, Xiao; Wan, Caihua; Kong, Wenjie; Zhang, Xuan; Xing, Yaowen; Fang, Chi; Tao, Bingshan; Yang, Wenlong; Huang, Li; Wu, Hao; Irfan, Muhammad; Han, Xiufeng

2018-06-21

Spin-orbit torque (SOT)-induced magnetization switching exhibits chirality (clockwise or counterclockwise), which offers the prospect of programmable spin-logic devices integrating nonvolatile spintronic memory cells with logic functions. Chirality is usually fixed by an applied or effective magnetic field in reported studies. Herein, utilizing an in-plane magnetic layer that is also switchable by SOT, the chirality of a perpendicular magnetic layer that is exchange-coupled with the in-plane layer can be reversed in a purely electrical way. In a single Hall bar device designed from this multilayer structure, three logic gates including AND, NAND, and NOT are reconfigured, which opens a gateway toward practical programmable spin-logic devices. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Synchronized operation by field programmable gate array based signal controller for the Thomson scattering diagnostic system in KSTAR.

PubMed

Lee, W R; Kim, H S; Park, M K; Lee, J H; Kim, K H

2012-09-01

The Thomson scattering diagnostic system is successfully installed in the Korea Superconducting Tokamak Advanced Research (KSTAR) facility. We got the electron temperature and electron density data for the first time in 2011, 4th campaign using a field programmable gate array (FPGA) based signal control board. It operates as a signal generator, a detector, a controller, and a time measuring device. This board produces two configurable trigger pulses to operate Nd:YAG laser system and receives a laser beam detection signal from a photodiode detector. It allows a trigger pulse to be delivered to a time delay module to make a scattered signal measurement, measuring an asynchronous time value between the KSTAR timing board and the laser system injection signal. All functions are controlled by the embedded processor running on operating system within a single FPGA. It provides Ethernet communication interface and is configured with standard middleware to integrate with KSTAR. This controller has operated for two experimental campaigns including commissioning and performed the reconfiguration of logic designs to accommodate varying experimental situation without hardware rebuilding.

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

Reprogrammable logic in memristive crossbar for in-memory computing

NASA Astrophysics Data System (ADS)

Cheng, Long; Zhang, Mei-Yun; Li, Yi; Zhou, Ya-Xiong; Wang, Zhuo-Rui; Hu, Si-Yu; Long, Shi-Bing; Liu, Ming; Miao, Xiang-Shui

2017-12-01

Memristive stateful logic has emerged as a promising next-generation in-memory computing paradigm to address escalating computing-performance pressures in traditional von Neumann architecture. Here, we present a nonvolatile reprogrammable logic method that can process data between different rows and columns in a memristive crossbar array based on material implication (IMP) logic. Arbitrary Boolean logic can be executed with a reprogrammable cell containing four memristors in a crossbar array. In the fabricated Ti/HfO2/W memristive array, some fundamental functions, such as universal NAND logic and data transfer, were experimentally implemented. Moreover, using eight memristors in a 2  ×  4 array, a one-bit full adder was theoretically designed and verified by simulation to exhibit the feasibility of our method to accomplish complex computing tasks. In addition, some critical logic-related performances were further discussed, such as the flexibility of data processing, cascading problem and bit error rate. Such a method could be a step forward in developing IMP-based memristive nonvolatile logic for large-scale in-memory computing architecture.

Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

ERIC Educational Resources Information Center

Debiec, P.; Byczuk, M.

2011-01-01

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

Using Spare Logic Resources To Create Dynamic Test Points

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.

Directed evolution of a synthetic phylogeny of programmable Trp repressors.

PubMed

Ellefson, Jared W; Ledbetter, Michael P; Ellington, Andrew D

2018-04-01

As synthetic regulatory programs expand in sophistication, an ever increasing number of biological components with predictable phenotypes is required. Regulators are often 'part mined' from a diverse, but uncharacterized, array of genomic sequences, often leading to idiosyncratic behavior. Here, we generate an entire synthetic phylogeny from the canonical allosteric transcription factor TrpR. Iterative rounds of positive and negative compartmentalized partnered replication (CPR) led to the exponential amplification of variants that responded with high affinity and specificity to halogenated tryptophan analogs and novel operator sites. Fourteen repressor variants were evolved with unique regulatory profiles across five operators and three ligands. The logic of individual repressors can be modularly programmed by creating heterodimeric fusions, resulting in single proteins that display logic functions, such as 'NAND'. Despite the evolutionarily limited regulatory role of TrpR, vast functional spaces exist around this highly conserved protein scaffold and can be harnessed to create synthetic regulatory programs.

A Pipelined Non-Deterministic Finite Automaton-Based String Matching Scheme Using Merged State Transitions in an FPGA

PubMed Central

Choi, Kang-Il

2016-01-01

This paper proposes a pipelined non-deterministic finite automaton (NFA)-based string matching scheme using field programmable gate array (FPGA) implementation. The characteristics of the NFA such as shared common prefixes and no failure transitions are considered in the proposed scheme. In the implementation of the automaton-based string matching using an FPGA, each state transition is implemented with a look-up table (LUT) for the combinational logic circuit between registers. In addition, multiple state transitions between stages can be performed in a pipelined fashion. In this paper, it is proposed that multiple one-to-one state transitions, called merged state transitions, can be performed with an LUT. By cutting down the number of used LUTs for implementing state transitions, the hardware overhead of combinational logic circuits is greatly reduced in the proposed pipelined NFA-based string matching scheme. PMID:27695114

A Pipelined Non-Deterministic Finite Automaton-Based String Matching Scheme Using Merged State Transitions in an FPGA.

PubMed

Kim, HyunJin; Choi, Kang-Il

2016-01-01

This paper proposes a pipelined non-deterministic finite automaton (NFA)-based string matching scheme using field programmable gate array (FPGA) implementation. The characteristics of the NFA such as shared common prefixes and no failure transitions are considered in the proposed scheme. In the implementation of the automaton-based string matching using an FPGA, each state transition is implemented with a look-up table (LUT) for the combinational logic circuit between registers. In addition, multiple state transitions between stages can be performed in a pipelined fashion. In this paper, it is proposed that multiple one-to-one state transitions, called merged state transitions, can be performed with an LUT. By cutting down the number of used LUTs for implementing state transitions, the hardware overhead of combinational logic circuits is greatly reduced in the proposed pipelined NFA-based string matching scheme.

The trigger system for the external target experiment in the HIRFL cooling storage ring

NASA Astrophysics Data System (ADS)

Li, Min; Zhao, Lei; Liu, Jin-Xin; Lu, Yi-Ming; Liu, Shu-Bin; An, Qi

2016-08-01

A trigger system was designed for the external target experiment in the Cooling Storage Ring (CSR) of the Heavy Ion Research Facility in Lanzhou (HIRFL). Considering that different detectors are scattered over a large area, the trigger system is designed based on a master-slave structure and fiber-based serial data transmission technique. The trigger logic is organized in hierarchies, and flexible reconfiguration of the trigger function is achieved based on command register access or overall field-programmable gate array (FPGA) logic on-line reconfiguration controlled by remote computers. We also conducted tests to confirm the function of the trigger electronics, and the results indicate that this trigger system works well. Supported by the National Natural Science Foundation of China (11079003), the Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27), and the CAS Center for Excellence in Particle Physics (CCEPP).

PLA realizations for VLSI state machines

NASA Technical Reports Server (NTRS)

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

NASA Astrophysics Data System (ADS)

Li, Huiyun; Du, Guanghua; Shao, Cuiping; Dai, Liang; Xu, Guoqing; Guo, Jinlong

2015-06-01

Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations.

Stego on FPGA: An IWT Approach

PubMed Central

Ramalingam, Balakrishnan

2014-01-01

A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8 × 8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk's verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA). PMID:24723794

77 FR 33243 - Applications and Amendments to Facility Operating Licenses and Combined Licenses Involving...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-05

... Operations Management Tricon Programmable Logic Controller (PLC), Version 10, and the CS Innovations, LLC... process protection system that is based on the Invensys Operations Management Tricon Programmable Logic...

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

NASA Astrophysics Data System (ADS)

Hamada, Tsuyoshi; Fukushige, Toshiyuki; Kawai, Atsushi; Makino, Junichiro

2000-10-01

We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and ``traditional'' GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydro\\-dynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ben-Zvi, I.

Various authors have previously studied the theory and practice of cavity testing, notably an extensive treatment by Powers [1] and Padamsee [2]. The advent of the digital Low Level RF (LLRF) electronics based on Field Programmable Logic Arrays (FPGA) provides various improvements over the rather complex systems used in the past as well as enabling new measurement techniques.In this document we reintroduce a technique that seems to have fallen out of practice in recent times, that is obtaining the coupling constant β through measurements from just one port, the reflected power port, of the directional coupler placed in front ofmore » the cavity.« less

Method and apparatus for optical encoding with compressible imaging

NASA Technical Reports Server (NTRS)

Leviton, Douglas B. (Inventor)

2006-01-01

The present invention presents an optical encoder with increased conversion rates. Improvement in the conversion rate is a result of combining changes in the pattern recognition encoder's scale pattern with an image sensor readout technique which takes full advantage of those changes, and lends itself to operation by modern, high-speed, ultra-compact microprocessors and digital signal processors (DSP) or field programmable gate array (FPGA) logic elements which can process encoder scale images at the highest speeds. Through these improvements, all three components of conversion time (reciprocal conversion rate)--namely exposure time, image readout time, and image processing time--are minimized.

Industrial Control System Process-Oriented Intrusion Detection (iPoid) Algorithm

DTIC Science & Technology

2016-08-01

inspection rules using an intrusion-detection system (IDS) sensor, a simulated Programmable Logic Controller (PLC), and a Modbus client operating...operating system PLC Programmable Logic Controller SCADA supervisory control and data acquisition SIGHUP signal hangup SPAN Switched Port Analyzer

Cellular logic array for computation of squares

NASA Technical Reports Server (NTRS)

Shamanna, M.; Whitaker, S.; Canaris, J.

1991-01-01

A cellular logic array is described for squaring binary numbers. This array offers a significant increase in speed, with a relatively small hardware overhead. This improvement is a result of novel implementation of the formula (x + y)exp 2 = x(exp 2) + y(exp 2) + 2(x)(y). These results can also be incorporated in the existing arrays achieving considerable hardware reduction.

A reconfigurable cryogenic platform for the classical control of quantum processors

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

A reconfigurable cryogenic platform for the classical control of quantum processors.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

A binary link tracker for the BaBar level 1 trigger system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berenyi, A.; Chen, H.K.; Dao, K.

1999-08-01

The BaBar detector at PEP-II will operate in a high-luminosity e{sup +}e{sup {minus}} collider environment near the {Upsilon}(4S) resonance with the primary goal of studying CP violation in the B meson system. In this environment, typical physics events of interest involve multiple charged particles. These events are identified by counting these tracks in a fast first level (Level 1) trigger system, by reconstructing the tracks in real time. For this purpose, a Binary Link Tracker Module (BLTM) was designed and fabricated for the BaBar Level 1 Drift Chamber trigger system. The BLTM is responsible for linking track segments, constructed bymore » the Track Segment Finder Modules (TSFM), into complete tracks. A single BLTM module processes a 360 MBytes/s stream of segment hit data, corresponding to information from the entire Drift Chamber, and implements a fast and robust algorithm that tolerates high hit occupancies as well as local inefficiencies of the Drift Chamber. The algorithms and the necessary control logic of the BLTM were implemented in Field Programmable Gate Arrays (FPGAs), using the VHDL hardware description language. The finished 9U x 400 mm Euro-format board contains roughly 75,000 gates of programmable logic or about 10,000 lines of VHDL code synthesized into five FPGAs.« less

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

2000-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will start a series of notes concentrating on analysis techniques with this issues section discussing worst-case analysis requirements.

A hybrid nanomemristor/transistor logic circuit capable of self-programming

PubMed Central

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

PubMed

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Optical programmable Boolean logic unit.

PubMed

Chattopadhyay, Tanay

2011-11-10

Logic units are the building blocks of many important computational operations likes arithmetic, multiplexer-demultiplexer, radix conversion, parity checker cum generator, etc. Multifunctional logic operation is very much essential in this respect. Here a programmable Boolean logic unit is proposed that can perform 16 Boolean logical operations from a single optical input according to the programming input without changing the circuit design. This circuit has two outputs. One output is complementary to the other. Hence no loss of data can occur. The circuit is basically designed by a 2×2 polarization independent optical cross bar switch. Performance of the proposed circuit has been achieved by doing numerical simulations. The binary logical states (0,1) are represented by the absence of light (null) and presence of light, respectively.

A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment

NASA Astrophysics Data System (ADS)

Stefan Devlin, Benjamin; Nakura, Toru; Ikeda, Makoto; Asada, Kunihiro

We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2Mλ2 area with 35bits of SRAM, and the prototype SSFPGA with 34 × 30 (1020) blocks is designed and fabricated using 65nm CMOS. Measured results show at 1.2V 430MHz and 647MHz operation for a 3bit ripple carry adder, without and with throughput optimization, respectively. We find that using the proposed pipeline alignment techniques we can perform at maximum throughput of 647MHz in various benchmarks on the SSFPGA. We demonstrate up to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

NASA Astrophysics Data System (ADS)

Mar, Jeich; Kuo, Chi-Cheng; Wu, Shin-Ru; Lin, You-Rong

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard; Day, John H. (Technical Monitor)

2001-01-01

This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.

Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

ERIC Educational Resources Information Center

Todorovich, E.; Marone, J. A.; Vazquez, M.

2012-01-01

Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

Programming Programmable Logic Controller. High-Technology Training Module.

ERIC Educational Resources Information Center

Lipsky, Kevin

This training module on programming programmable logic controllers (PLC) is part of the memory structure and programming unit used in a packaging systems equipment control course. In the course, students assemble, install, maintain, and repair industrial machinery used in industry. The module contains description, objectives, content outline,…

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

1998-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, and some total dose results.

Spacecube: A Family of Reconfigurable Hybrid On-Board Science Data Processors

NASA Technical Reports Server (NTRS)

Flatley, Thomas P.

2015-01-01

SpaceCube is a family of Field Programmable Gate Array (FPGA) based on-board science data processing systems developed at the NASA Goddard Space Flight Center (GSFC). The goal of the SpaceCube program is to provide 10x to 100x improvements in on-board computing power while lowering relative power consumption and cost. SpaceCube is based on the Xilinx Virtex family of FPGAs, which include processor, FPGA logic and digital signal processing (DSP) resources. These processing elements are leveraged to produce a hybrid science data processing platform that accelerates the execution of algorithms by distributing computational functions to the most suitable elements. This approach enables the implementation of complex on-board functions that were previously limited to ground based systems, such as on-board product generation, data reduction, calibration, classification, eventfeature detection, data mining and real-time autonomous operations. The system is fully reconfigurable in flight, including data parameters, software and FPGA logic, through either ground commanding or autonomously in response to detected eventsfeatures in the instrument data stream.

Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

NASA Technical Reports Server (NTRS)

Le, Martin; Zheng, Xin; Katanyoutant, Sunant

2008-01-01

Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state-transition rules.

Universal programmable logic gate and routing method

NASA Technical Reports Server (NTRS)

Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Mojarradi, Mohammad M. (Inventor); Fijany, Amir (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Phased Arrays 1985 Symposium - Proceedings

DTIC Science & Technology

1985-08-01

have served the logic industry well, and appropriate versions can do the same for micruwdve drid millimeter * wave technology, An aspect of phased...continuing revolutions of the logic industry and the microwave monolithic integrated circuit community are bringing relevant technology closer to the array...monolithic phased array antennas, and discuss their relative advantages and disadvantages . Considerations such as bandwidth, maxianiru scan range, feed

Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews.

PubMed

Kneale, Dylan; Thomas, James; Harris, Katherine

2015-01-01

Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to 'think' conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions.

Improving excellence in scoliosis rehabilitation: a controlled study of matched pairs.

PubMed

Weiss, H-R; Klein, R

2006-01-01

Physiotherapy programmes so far mainly address the lateral deformity of scoliosis, a few aim at the correction of rotation and only very few address the sagittal profile. Meanwhile, there is evidence that correction forces applied in the sagittal plane are also able to correct the scoliotic deformity in the coronal and frontal planes. So it should be possible to improve excellence in scoliosis rehabilitation by the implementation of exercises to correct the sagittal deformity in scoliosis patients. An exercise programme (physio-logic exercises) aiming at a physiologic sagittal profile was developed to add to the programme applied at the centre or to replace certain exercises or exercising positions. To test the hypothesis that physio-logic exercises improve the outcome of Scoliosis Intensive Rehabilitation (SIR), the following study design was chosen: Prospective controlled trial of pairs of patients with idiopathic scoliosis matched by sex, age, Cobb angle and curve pattern. There were 18 patients in the treatment group (SIR + physio-logic exercises) and 18 patients in the control group (SIR only), all in matched pairs. Average Cobb angle in the treatment group was 34.5 degrees (SD 7.8) Cobb angle in the control group was 31.6 degrees (SD 5.8). Age in the treatment group was at average 15.3 years (SD 1.1) and in the control group 14.7 years (SD 1.3). Thirteen of the 18 patients in either group had a brace. Outcome parameter: average lateral deviation (mm), average surface rotation ( degrees ) and maximum Kyphosis angle ( degrees ) as evaluated with the help of surface topography (Formetric-system). Lateral deviation (mm) decreased significantly after the performance of the physio-logic programme and highly significantly in the physio-logic ADL posture; however, it was not significant after completion of the whole rehabilitation programme (2.3 vs 0.3 mm in the controls). Surface rotation improved at average 1.2 degrees in the treatment group and 0.8 degrees in the controls while Kyphosis angle did not improve in both groups. The physio-logic programme has to be regarded as a useful 'add on' to Scoliosis Rehabilitation with regards to the lateral deviation of the scoliotic trunk. A longitudinal controlled study is necessary to evaluate the long-term effect of the the physio-logic programme also with the help of X-rays.

Enhanced Control for Local Helicity Injection on the Pegasus ST

NASA Astrophysics Data System (ADS)

Pierren, C.; Bongard, M. W.; Fonck, R. J.; Lewicki, B. T.; Perry, J. M.

2017-10-01

Local helicity injection (LHI) experiments on Pegasus rely upon programmable control of a 250 MVA modular power supply system that drives the electromagnets and helicity injection systems. Precise control of the central solenoid is critical to experimental campaigns that test the LHI Taylor relaxation limit and the coupling efficiency of LHI-produced plasmas to Ohmic current drive. Enhancement and expansion of the present control system is underway using field programmable gate array (FPGA) technology for digital logic and control, coupled to new 10 MHz optical-to-digital transceivers for semiconductor level device communication. The system accepts optical command signals from existing analog feedback controllers, transmits them to multiple devices in parallel H-bridges, and aggregates their status signals for fault detection. Present device-level multiplexing/de-multiplexing and protection logic is extended to include bridge-level protections with the FPGA. An input command filter protects against erroneous and/or spurious noise generated commands that could otherwise cause device failures. Fault registration and response times with the FPGA system are 25 ns. Initial system testing indicates an increased immunity to power supply induced noise, enabling plasma operations at higher working capacitor bank voltage. This can increase the applied helicity injection drive voltage, enable longer pulse lengths and improve Ohmic loop voltage control. Work supported by US DOE Grant DE-FG02-96ER54375.

Two-dimensional radiant energy array computers and computing devices

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1976-01-01

Two dimensional digital computers and computer devices operate in parallel on rectangular arrays of digital radiant energy optical signal elements which are arranged in ordered rows and columns. Logic gate devices receive two input arrays and provide an output array having digital states dependent only on the digital states of the signal elements of the two input arrays at corresponding row and column positions. The logic devices include an array of photoconductors responsive to at least one of the input arrays for either selectively accelerating electrons to a phosphor output surface, applying potentials to an electroluminescent output layer, exciting an array of discrete radiant energy sources, or exciting a liquid crystal to influence crystal transparency or reflectivity.

An Ultrasonic Multiple-Access Ranging Core Based on Frequency Shift Keying Towards Indoor Localization

PubMed Central

Segers, Laurent; Van Bavegem, David; De Winne, Sam; Braeken, An; Touhafi, Abdellah; Steenhaut, Kris

2015-01-01

This paper describes a new approach and implementation methodology for indoor ranging based on the time difference of arrival using code division multiple access with ultrasound signals. A novel implementation based on a field programmable gate array using finite impulse response filters and an optimized correlation demodulator implementation for ultrasound orthogonal signals is developed. Orthogonal codes are modulated onto ultrasound signals using frequency shift keying with carrier frequencies of 24.5 kHz and 26 kHz. This implementation enhances the possibilities for real-time, embedded and low-power tracking of several simultaneous transmitters. Due to the high degree of parallelism offered by field programmable gate arrays, up to four transmitters can be tracked simultaneously. The implementation requires at most 30% of the available logic gates of a Spartan-6 XC6SLX45 device and is evaluated on accuracy and precision through several ranging topologies. In the first topology, the distance between one transmitter and one receiver is evaluated. Afterwards, ranging analyses are applied between two simultaneous transmitters and one receiver. Ultimately, the position of the receiver against four transmitters using trilateration is also demonstrated. Results show enhanced distance measurements with distances ranging from a few centimeters up to 17 m, while keeping a centimeter-level accuracy. PMID:26263986

A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

ERIC Educational Resources Information Center

Kellett, C. M.

2012-01-01

This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is…

"Modeling" Youth Work: Logic Models, Neoliberalism, and Community Praxis

ERIC Educational Resources Information Center

Carpenter, Sara

2016-01-01

This paper examines the use of logic models in the development of community initiatives within the AmeriCorps program. AmeriCorps is the civilian national service programme in the U.S., operating as a grants programme to local governments and not-for-profit organisations and providing low-cost labour to address pressing issues of social…

A novel approach to Hough Transform for implementation in fast triggers

NASA Astrophysics Data System (ADS)

Pozzobon, Nicola; Montecassiano, Fabio; Zotto, Pierluigi

2016-10-01

Telescopes of position sensitive detectors are common layouts in charged particles tracking, and programmable logic devices, such as FPGAs, represent a viable choice for the real-time reconstruction of track segments in such detector arrays. A compact implementation of the Hough Transform for fast triggers in High Energy Physics, exploiting a parameter reduction method, is proposed, targeting the reduction of the needed storage or computing resources in current, or next future, state-of-the-art FPGA devices, while retaining high resolution over a wide range of track parameters. The proposed approach is compared to a Standard Hough Transform with particular emphasis on their application to muon detectors. In both cases, an original readout implementation is modeled.

Mutation Testing for Effective Verification of Digital Components of Physical Systems

NASA Astrophysics Data System (ADS)

Kushik, N. G.; Evtushenko, N. V.; Torgaev, S. N.

2015-12-01

Digital components of modern physical systems are often designed applying circuitry solutions based on the field programmable gate array technology (FPGA). Such (embedded) digital components should be carefully tested. In this paper, an approach for the verification of digital physical system components based on mutation testing is proposed. The reference description of the behavior of a digital component in the hardware description language (HDL) is mutated by introducing into it the most probable errors and, unlike mutants in high-level programming languages, the corresponding test case is effectively derived based on a comparison of special scalable representations of the specification and the constructed mutant using various logic synthesis and verification systems.

EEE Links, Volume 9, No. 1, January 2003 Focus on Plastic Parts

NASA Technical Reports Server (NTRS)

2003-01-01

The January 2003 issue of Electronic, Electromechanical, Electric (EEE) Links is presented. The Programmable Logic Application Notes column has been reinstated in this newsletter. Written by Rich Katz of NASA's Office of Logic Design (OLD), the application notes offer technical tips intended to prevent flight design errors and enhance research, development, and use of programmable logic and elements for space flight applications. An archive of these notes columns from previous issues of EEE Links is available at http://www.klabs.org/richcontent/eeelink s/EEE Links.htm.

Development and use of the generic WHO/CDC logic model for vitamin and mineral interventions in public health programmes

PubMed Central

De-Regil, Luz Maria; Peña-Rosas, Juan Pablo; Flores-Ayala, Rafael; del Socorro Jefferds, Maria Elena

2015-01-01

Objective Nutrition interventions are critical to achieve the Millennium Development Goals; among them, micronutrient interventions are considered cost-effective and programmatically feasible to scale up, but there are limited tools to communicate the programme components and their relationships. The WHO/CDC (Centers for Disease Control and Prevention) logic model for micronutrient interventions in public health programmes is a useful resource for planning, implementation, monitoring and evaluation of these interventions, which depicts the programme theory and expected relationships between inputs and expected Millennium Development Goals. Design The model was developed by applying principles of programme evaluation, public health nutrition theory and programmatic expertise. The multifaceted and iterative structure validation included feedback from potential users and adaptation by national stakeholders involved in public health programmes' design and implementation. Results In addition to the inputs, main activity domains identified as essential for programme development, implementation and performance include: (i) policy; (ii) products and supply; (iii) delivery systems; (iv) quality control; and (v) behaviour change communication. Outputs encompass the access to and coverage of interventions. Outcomes include knowledge and appropriate use of the intervention, as well as effects on micronutrient intake, nutritional status and health of target populations, for ultimate achievement of the Millennium Development Goals. Conclusions The WHO/CDC logic model simplifies the process of developing a logic model by providing a tool that has identified high-priority areas and concepts that apply to virtually all public health micronutrient interventions. Countries can adapt it to their context in order to support programme design, implementation, monitoring and evaluation for the successful scale-up of nutrition interventions in public health. PMID:23507463

Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews

PubMed Central

Kneale, Dylan; Thomas, James; Harris, Katherine

2015-01-01

Background Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to ‘think’ conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. Methods and Findings In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Conclusions Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions. PMID:26575182

FPGA implementation of bit controller in double-tick architecture

NASA Astrophysics Data System (ADS)

Kobylecki, Michał; Kania, Dariusz

2017-11-01

This paper presents a comparison of the two original architectures of programmable bit controllers built on FPGAs. Programmable Logic Controllers (which include, among other things programmable bit controllers) built on FPGAs provide a efficient alternative to the controllers based on microprocessors which are expensive and often too slow. The presented and compared methods allow for the efficient implementation of any bit control algorithm written in Ladder Diagram language into the programmable logic system in accordance with IEC61131-3. In both cases, we have compared the effect of the applied architecture on the performance of executing the same bit control program in relation to its own size.

Versatile logic devices based on programmable DNA-regulated silver-nanocluster signal transducers.

PubMed

Huang, Zhenzhen; Tao, Yu; Pu, Fang; Ren, Jinsong; Qu, Xiaogang

2012-05-21

A DNA-encoding strategy is reported for the programmable regulation of the fluorescence properties of silver nanoclusters (AgNCs). By taking advantage of the DNA-encoding strategy, aqueous AgNCs were used as signal transducers to convert DNA inputs into fluorescence outputs for the construction of various DNA-based logic gates (AND, OR, INHIBIT, XOR, NOR, XNOR, NAND, and a sequential logic gate). Moreover, a biomolecular keypad that was capable of constructing crossword puzzles was also fabricated. These AgNC-based logic systems showed several advantages, including a simple transducer-introduction strategy, universal design, and biocompatible operation. In addition, this proof of concept opens the door to a new generation of signal transducer materials and provides a general route to versatile biomolecular logic devices for practical applications. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Array processor architecture connection network

NASA Technical Reports Server (NTRS)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1982-01-01

A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.

A Versatile Planetary Radio Science Microreceiver

NASA Technical Reports Server (NTRS)

Fry, Craig D.; Rosenberg, T. J.

1999-01-01

We have developed a low-power. programmable radio "microreceiver" that combines the functionality of two science instruments: a Relative Ionospheric Opacity Meter (riometer) and a swept-frequency, VTF/HF radio spectrometer. The radio receiver, calibration noise source, data acquisition and processing, and command and control functions are all contained on a single circuit board. This design is suitable for miniaturizing as a complete flight instrument. Several of the subsystems were implemented in a field-programmable gate array (FPGA), including the receiver detector, the control logic, and the data acquisition and processing blocks. Considerable efforts were made to reduce the power consumption of the instrument, and eliminate or minimize RF noise and spurious emissions generated by the receiver's digital circuitry. A prototype instrument was deployed at McMurdo Station, Antarctica, and operated in parallel with a traditional riometer instrument for approximately three weeks. The attached paper (accepted for publication by Radio Science) describes in detail the microreceiver theory of operation, performance specifications and test results.

Reconfigurable electro-optical directed-logic circuit using carrier-depletion micro-ring resonators.

PubMed

Qiu, Ciyuan; Gao, Weilu; Soref, Richard; Robinson, Jacob T; Xu, Qianfan

2014-12-15

Here we demonstrate a reconfigurable electro-optical directed-logic circuit based on a regular array of integrated optical switches. Each 1×1 optical switch consists of a micro-ring resonator with an embedded lateral p-n junction and a micro-heater. We achieve high-speed on-off switching by applying electrical logic signals to the p-n junction. We can configure the operation mode of each switch by thermal tuning the resonance wavelength. The result is an integrated optical circuit that can be reconfigured to perform any combinational logic operation. As a proof-of-principle, we fabricated a multi-spectral directed-logic circuit based on a fourfold array of switches and showed that this circuit can be reconfigured to perform arbitrary two-input logic functions with speeds up to 3  GB/s.

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Compact universal logic gates realized using quantization of current in nanodevices.

PubMed

Zhang, Wancheng; Wu, Nan-Jian; Yang, Fuhua

2007-12-12

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Compact FPGA-based beamformer using oversampled 1-bit A/D converters.

PubMed

Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

2005-05-01

A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.

Programmer's guide to the fuzzy logic ramp metering algorithm : software design, integration, testing, and evaluation

DOT National Transportation Integrated Search

2000-02-01

A Fuzzy Logic Ramp Metering Algorithm was implemented on 126 ramps in the greater Seattle area. This report documents the implementation of the Fuzzy Logic Ramp Metering Algorithm at the Northwest District of the Washington State Department of Transp...

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Na; Wu, Yu-Ping; Min, Hao

A radio-frequency (RF) source designed for cold atom experiments is presented. The source uses AD9858, a direct digital synthesizer, to generate the sine wave directly, up to 400 MHz, with sub-Hz resolution. An amplitude control circuit consisting of wideband variable gain amplifier and high speed digital to analog converter is integrated into the source, capable of 70 dB off isolation and 4 ns on-off keying. A field programmable gate array is used to implement a versatile frequency and amplitude co-sweep logic. Owing to modular design, the RF sources have been used on many cold atom experiments to generate various complicatedmore » RF sequences, enriching the operation schemes of cold atoms, which cannot be done by standard RF source instruments.« less

Efficient Digital Implementation of The Sigmoidal Function For Artificial Neural Network

NASA Astrophysics Data System (ADS)

Pratap, Rana; Subadra, M.

2011-10-01

An efficient piecewise linear approximation of a nonlinear function (PLAN) is proposed. This uses simulink environment design to perform a direct transformation from X to Y, where X is the input and Y is the approximated sigmoidal output. This PLAN is then used within the outputs of an artificial neural network to perform the nonlinear approximation. In This paper, is proposed a method to implement in FPGA (Field Programmable Gate Array) circuits different approximation of the sigmoid function.. The major benefit of the proposed method resides in the possibility to design neural networks by means of predefined block systems created in System Generator environment and the possibility to create a higher level design tools used to implement neural networks in logical circuits.

Novel processor architecture for onboard infrared sensors

NASA Astrophysics Data System (ADS)

Hihara, Hiroki; Iwasaki, Akira; Tamagawa, Nobuo; Kuribayashi, Mitsunobu; Hashimoto, Masanori; Mitsuyama, Yukio; Ochi, Hiroyuki; Onodera, Hidetoshi; Kanbara, Hiroyuki; Wakabayashi, Kazutoshi; Tada, Munehiro

2016-09-01

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

Programmable Pulser

NASA Technical Reports Server (NTRS)

Baumann, Eric; Merolla, Anthony

1988-01-01

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

Design structure for in-system redundant array repair in integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Field Programmable Gate Array Control of Power Systems in Graduate Student Laboratories

DTIC Science & Technology

2008-03-01

NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS Approved for public release; distribution is unlimited FIELD PROGRAMMABLE...REPORT TYPE AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Field Programmable Gate Array Control of Power Systems in Graduate Student...Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA) control of power electronics

Programmable bioelectronics in a stimuli-encoded 3D graphene interface

NASA Astrophysics Data System (ADS)

Parlak, Onur; Beyazit, Selim; Tse-Sum-Bui, Bernadette; Haupt, Karsten; Turner, Anthony P. F.; Tiwari, Ashutosh

2016-05-01

The ability to program and mimic the dynamic microenvironment of living organisms is a crucial step towards the engineering of advanced bioelectronics. Here, we report for the first time a design for programmable bioelectronics, with `built-in' switchable and tunable bio-catalytic performance that responds simultaneously to appropriate stimuli. The designed bio-electrodes comprise light and temperature responsive compartments, which allow the building of Boolean logic gates (i.e. ``OR'' and ``AND'') based on enzymatic communications to deliver logic operations.The ability to program and mimic the dynamic microenvironment of living organisms is a crucial step towards the engineering of advanced bioelectronics. Here, we report for the first time a design for programmable bioelectronics, with `built-in' switchable and tunable bio-catalytic performance that responds simultaneously to appropriate stimuli. The designed bio-electrodes comprise light and temperature responsive compartments, which allow the building of Boolean logic gates (i.e. ``OR'' and ``AND'') based on enzymatic communications to deliver logic operations. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02355j

System and method for programmable bank selection for banked memory subsystems

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Programmable logic devices

NASA Astrophysics Data System (ADS)

Jacobs, J. L.

1993-04-01

Erasable programmable logic devices (EPLD's) were investigated to determine their advantages and/or disadvantages in Test Equipment Engineering applications. It was found that EPLD's performed as well as or better than identical circuits using standard transistor transistor logic (TTL). The chip count in these circuits was reduced, saving printed circuit board space and shortening fabrication and prove-in time. Troubleshooting circuits of EPLD's was also easier with 10 to 100 times fewer wires needed. The reduced number of integrated circuits (IC's) contributed to faster system speeds and an overall lower power consumption. In some cases changes to the circuit became software changes using EPLD's instead of hardware changes for standard logic. Using EPLD's was fairly easy; however, as with any new technology, a learning curve must be overcome before EPLD's can be used efficiently. The many benefits of EPLD's outweighed this initial inconvenience.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-29

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-08

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

2007-12-18

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Interface Supports Multiple Broadcast Transceivers for Flight Applications

NASA Technical Reports Server (NTRS)

Block, Gary L.; Whitaker, William D.; Dillon, James W.; Lux, James P.; Ahmad, Mohammad

2011-01-01

A wireless avionics interface provides a mechanism for managing multiple broadcast transceivers. This interface isolates the control logic required to support multiple transceivers so that the flight application does not have to manage wireless transceivers. All of the logic to select transceivers, detect transmitter and receiver faults, and take autonomous recovery action is contained in the interface, which is not restricted to using wireless transceivers. Wired, wireless, and mixed transceiver technologies are supported. This design s use of broadcast data technology provides inherent cross strapping of data links. This greatly simplifies the design of redundant flight subsystems. The interface fully exploits the broadcast data link to determine the health of other transceivers used to detect and isolate faults for fault recovery. The interface uses simplified control logic, which can be implemented as an intellectual-property (IP) core in a field-programmable gate array (FPGA). The interface arbitrates the reception of inbound data traffic appearing on multiple receivers. It arbitrates the transmission of outbound traffic. This system also monitors broadcast data traffic to determine the health of transmitters in the network, and then uses this health information to make autonomous decisions for routing traffic through transceivers. Multiple selection strategies are supported, like having an active transceiver with the secondary transceiver powered off except to send periodic health status reports. Transceivers can operate in round-robin for load-sharing and graceful degradation.

Aptamer-Binding Directed DNA Origami Pattern for Logic Gates.

PubMed

Yang, Jing; Jiang, Shuoxing; Liu, Xiangrong; Pan, Linqiang; Zhang, Cheng

2016-12-14

In this study, an aptamer-substrate strategy is introduced to control programmable DNA origami pattern. Combined with DNA aptamer-substrate binding and DNAzyme-cutting, small DNA tiles were specifically controlled to fill into the predesigned DNA origami frame. Here, a set of DNA logic gates (OR, YES, and AND) are performed in response to the stimuli of adenosine triphosphate (ATP) and cocaine. The experimental results are confirmed by AFM imaging and time-dependent fluorescence changes, demonstrating that the geometric patterns are regulated in a controllable and programmable manner. Our approach provides a new platform for engineering programmable origami nanopatterns and constructing complex DNA nanodevices.

Programmable Logic Controllers for Research on the Cyber Security of Industrial Power Plants

DTIC Science & Technology

2017-02-12

group . 15. SUBJECT TERMS Industrial control systems, cyber security 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF a. REPORT b. ABSTRACT c. THIS...currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. 1. REPORT DATE (00-MM-YYYY) ,2. REPORT TYPE 3. DATES COVERED...From- To) 12/02/2017 Final 15 August 2015 - 12 February 2017 4. TITLE AND SUBTITLE Sa. CONTRACT NUMBER Programmable Logic Controllers for Research

46 CFR 62.25-25 - Programmable systems and devices.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 46 Shipping 2 2014-10-01 2014-10-01 false Programmable systems and devices. 62.25-25 Section 62.25... AUTOMATION General Requirements for All Automated Vital Systems § 62.25-25 Programmable systems and devices. (a) Programmable control or alarm system logic must not be altered after Design Verification testing...

Design and simulation of programmable relational optoelectronic time-pulse coded processors as base elements for sorting neural networks

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Lazareva, Maria V.

2010-05-01

In the paper we show that the biologically motivated conception of time-pulse encoding usage gives a set of advantages (single methodological basis, universality, tuning simplicity, learning and programming et al) at creation and design of sensor systems with parallel input-output and processing for 2D structures hybrid and next generations neuro-fuzzy neurocomputers. We show design principles of programmable relational optoelectronic time-pulse encoded processors on the base of continuous logic, order logic and temporal waves processes. We consider a structure that execute analog signal extraction, analog and time-pulse coded variables sorting. We offer optoelectronic realization of such base relational order logic element, that consists of time-pulse coded photoconverters (pulse-width and pulse-phase modulators) with direct and complementary outputs, sorting network on logical elements and programmable commutation blocks. We make technical parameters estimations of devices and processors on such base elements by simulation and experimental research: optical input signals power 0.2 - 20 uW, processing time 1 - 10 us, supply voltage 1 - 3 V, consumption power 10 - 100 uW, extended functional possibilities, learning possibilities. We discuss some aspects of possible rules and principles of learning and programmable tuning on required function, relational operation and realization of hardware blocks for modifications of such processors. We show that it is possible to create sorting machines, neural networks and hybrid data-processing systems with untraditional numerical systems and pictures operands on the basis of such quasiuniversal hardware simple blocks with flexible programmable tuning.

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

DOEpatents

Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A

2014-01-28

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

High density, multi-range analog output Versa Module Europa board for control system applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, Kundan, E-mail: kundan@iuac.res.in; Das, Ajit Lal

2014-01-15

A new VMEDAC64, 12-bit 64 channel digital-to-analog converter, a Versa Module Europa (VME) module, features 64 analog voltage outputs with user selectable multiple ranges, has been developed for control system applications at Inter University Accelerator Centre. The FPGA (Field Programmable Gate Array) is the module's core, i.e., it implements the DAC control logic and complexity of VMEbus slave interface logic. The VMEbus slave interface and DAC control logic are completely designed and implemented on a single FPGA chip to achieve high density of 64 channels in a single width VME module and will reduce the module count in the controlmore » system applications, and hence will reduce the power consumption and cost of overall system. One of our early design goals was to develop the VME interface such that it can be easily integrated with the peripheral devices and satisfy the timing specifications of VME standard. The modular design of this module reduces the amount of time required to develop other custom modules for control system. The VME slave interface is written as a single component inside FPGA which will be used as a basic building block for any VMEbus interface project. The module offers multiple output voltage ranges depending upon the requirement. The output voltage range can be reduced or expanded by writing range selection bits in the control register. The module has programmable refresh rate and by default hold capacitors in the sample and hold circuit for each channel are charged periodically every 7.040 ms (i.e., update frequency 284 Hz). Each channel has software controlled output switch which disconnects analog output from the field. The modularity in the firmware design on FPGA makes the debugging very easy. On-board DC/DC converters are incorporated for isolated power supply for the analog section of the board.« less

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

NASA Astrophysics Data System (ADS)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Bit-systolic arithmetic arrays using dynamic differential gallium arsenide circuits

NASA Technical Reports Server (NTRS)

Beagles, Grant; Winters, Kel; Eldin, A. G.

1992-01-01

A new family of gallium arsenide circuits for fine grained bit-systolic arithmetic arrays is introduced. This scheme combines features of two recent techniques of dynamic gallium arsenide FET logic and differential dynamic single-clock CMOS logic. The resulting circuits are fast and compact, with tightly constrained series FET propagation paths, low fanout, no dc power dissipation, and depletion FET implementation without level shifting diodes.

A Star Image Extractor for Small Satellites

NASA Astrophysics Data System (ADS)

Yamada, Yoshiyuki; Yamauchi, Masahiro; Gouda, Naoteru; Kobayashi, Yukiyasu; Tsujimoto, Takuji; Yano, Taihei; Suganuma, Masahiro; Nakasuka, Shinichi; Sako, Nobutada; Inamori, Takaya

We have developed a Star Image Extractor (SIE) which works as an on-board real-time image processor. It is a logic circuit written on an FPGA(Field Programmable Gate Array) device. It detects and extracts only an object data from raw image data. SIE will be required with the Nano-JASMINE 1) satellite. Nano-JASMINE is the small astrometry satellite that observes objects in our galaxy. It will be launched in 2010 and needs two years mission period. Nano-JASMINE observes an object with the TDI (Time Delayed Integration) observation mode. TDI is one of operation modes of CCD detector. Data is obtained, by rotating the imaging system including CCD at a rated synchronized with a vertical charge transfer of CCD. Obtained image data is sent through SIE to the Mission-controller.

Programmable bioelectronics in a stimuli-encoded 3D graphene interface.

PubMed

Parlak, Onur; Beyazit, Selim; Tse-Sum-Bui, Bernadette; Haupt, Karsten; Turner, Anthony P F; Tiwari, Ashutosh

2016-05-21

The ability to program and mimic the dynamic microenvironment of living organisms is a crucial step towards the engineering of advanced bioelectronics. Here, we report for the first time a design for programmable bioelectronics, with 'built-in' switchable and tunable bio-catalytic performance that responds simultaneously to appropriate stimuli. The designed bio-electrodes comprise light and temperature responsive compartments, which allow the building of Boolean logic gates (i.e."OR" and "AND") based on enzymatic communications to deliver logic operations.

Starting Circuit For Erasable Programmable Logic Device

NASA Technical Reports Server (NTRS)

Cole, Steven W.

1990-01-01

Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.

Flexible programmable logic module

DOEpatents

Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

2001-01-01

The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

Molecular implementation of simple logic programs.

PubMed

Ran, Tom; Kaplan, Shai; Shapiro, Ehud

2009-10-01

Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) <-- Man(X) (Every Man is Mortal), the system can answer molecular queries such as Mortal(Socrates)? (Is Socrates Mortal?) and Mortal(X)? (Who is Mortal?). This biomolecular computing system compares favourably with previous approaches in terms of expressive power, performance and precision. A compiler translates facts, rules and queries into their molecular representations and subsequently operates a robotic system that assembles the logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

Layout and cabling considerations for a large communications antenna array

NASA Technical Reports Server (NTRS)

Logan, R. T., Jr.

1993-01-01

Layout considerations for a large deep space communications antenna array are discussed. A fractal geometry for the antenna layout is described that provides optimal packing of antenna elements, efficient cable routing, and logical division of the array into identical sub-arrays.

Diagnosable structured logic array

NASA Technical Reports Server (NTRS)

Whitaker, Sterling (Inventor); Miles, Lowell (Inventor); Gambles, Jody (Inventor); Maki, Gary K. (Inventor)

2009-01-01

A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

NASA Astrophysics Data System (ADS)

Rosky, David S.; Coy, Bruce H.; Friedmann, Marc D.

1992-03-01

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

Design techniques for a stable operation of cryogenic field-programmable gate arrays.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Design techniques for a stable operation of cryogenic field-programmable gate arrays

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Runtime verification of embedded real-time systems.

PubMed

Reinbacher, Thomas; Függer, Matthias; Brauer, Jörg

We present a runtime verification framework that allows on-line monitoring of past-time Metric Temporal Logic (ptMTL) specifications in a discrete time setting. We design observer algorithms for the time-bounded modalities of ptMTL, which take advantage of the highly parallel nature of hardware designs. The algorithms can be translated into efficient hardware blocks, which are designed for reconfigurability, thus, facilitate applications of the framework in both a prototyping and a post-deployment phase of embedded real-time systems. We provide formal correctness proofs for all presented observer algorithms and analyze their time and space complexity. For example, for the most general operator considered, the time-bounded Since operator, we obtain a time complexity that is doubly logarithmic both in the point in time the operator is executed and the operator's time bounds. This result is promising with respect to a self-contained, non-interfering monitoring approach that evaluates real-time specifications in parallel to the system-under-test. We implement our framework on a Field Programmable Gate Array platform and use extensive simulation and logic synthesis runs to assess the benefits of the approach in terms of resource usage and operating frequency.

Digital Device Architecture and the Safe Use of Flash Devices in Munitions

NASA Technical Reports Server (NTRS)

Katz, Richard B.; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

Wide Tuning Capability for Spacecraft Transponders

NASA Technical Reports Server (NTRS)

Lux, James; Mysoor, Narayan; Shah, Biren; Cook, Brian; Smith, Scott

2007-01-01

A document presents additional information on the means of implementing a capability for wide tuning of microwave receiver and transmitter frequencies in the development reported in the immediately preceding article, VCO PLL Frequency Synthesizers for Spacecraft Transponders (NPO- 42909). The reference frequency for a PLL-based frequency synthesizer is derived from a numerically controlled oscillator (NCO) implemented in digital logic, such that almost any reference frequency can be derived from a fixed crystal reference oscillator with microhertz precision. The frequency of the NCO is adjusted to track the received signal, then used to create another NCO frequency used to synthesize the transmitted signal coherent with, and at a specified frequency ratio to, the received signal. The frequencies can be changed, even during operation, through suitable digital programming. The NCOs and the related tracking loops and coherent turnaround logic are implemented in a field-programmable gate array (FPGA). The interface between the analog microwave receiver and transmitter circuits and the FPGA includes analog-to-digital and digital-toanalog converters, the sampling rates of which are chosen to minimize spurious signals and otherwise optimize performance. Several mixers and filters are used to properly route various signals.

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

NASA Astrophysics Data System (ADS)

Kleinfelder, Stuart A.; Chiang, Shiuh-hua Wood; Huang, Wei

2013-10-01

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.

RHrFPGA Radiation-Hardened Re-programmable Field-Programmable Gate Array

NASA Technical Reports Server (NTRS)

Sanders, A. B.; LaBel, K. A.; McCabe, J. F.; Gardner, G. A.; Lintz, J.; Ross, C.; Golke, K.; Burns, B.; Carts, M. A.; Kim, H. S.

2004-01-01

Viewgraphs on the development of the Radiation-Hardened Re-programmable Field-Programmable Gate Array (RHrFPGA) are presented. The topics include: 1) Radiation Test Suite; 2) Testing Interface; 3) Test Configuration; 4) Facilities; 5) Test Programs; 6) Test Procedure; and 7) Test Results. A summary of heavy ion and proton testing is also included.

Using a Commercial Ethernet PHY Device in a Radiation Environment

NASA Technical Reports Server (NTRS)

Parks, Jeremy; Arani, Michael; Arroyo, Roberto

2014-01-01

This work involved placing a commercial Ethernet PHY on its own power boundary, with limited current supply, and providing detection methods to determine when the device is not operating and when it needs either a reset or power-cycle. The device must be radiation-tested and free of destructive latchup errors. The commercial Ethernet PHY's own power boundary must be supplied by a current-limited power regulator that must have an enable (for power cycling), and its maximum power output must not exceed the PHY's input requirements, thus preventing damage to the device. A regulator with configurable output limits and short-circuit protection (such as the RHFL4913, rad hard positive voltage regulator family) is ideal. This will prevent a catastrophic failure due to radiation (such as a short between the commercial device's power and ground) from taking down the board's main power. Logic provided on the board will detect errors in the PHY. An FPGA (field-programmable gate array) with embedded Ethernet MAC (Media Access Control) will work well. The error detection includes monitoring the PHY's interrupt line, and the status of the Ethernet's switched power. When the PHY is determined to be non-functional, the logic device resets the PHY, which will often clear radiation induced errors. If this doesn't work, the logic device power-cycles the FPGA by toggling the regulator's enable input. This should clear almost all radiation induced errors provided the device is not latched up.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Logical Reasoning in Middle Childhood: A Study of Piagetian Concrete Operations Stage.

ERIC Educational Resources Information Center

Hooper, Frank H.; And Others

This 4-year longitudinal study of logical reasoning found complex interrelationships among different cognitive processes of children ages 6 to 15. Piaget's stage theory is discussed in the introduction, with a focus on the concrete operational stage in middle childhood. In the study, a representative array of logical concept tasks and short-term…

Programmable and multiparameter DNA-based logic platform for cancer recognition and targeted therapy.

PubMed

You, Mingxu; Zhu, Guizhi; Chen, Tao; Donovan, Michael J; Tan, Weihong

2015-01-21

The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy.

FAST TRACK COMMUNICATION: Reversible arithmetic logic unit for quantum arithmetic

NASA Astrophysics Data System (ADS)

Kirkedal Thomsen, Michael; Glück, Robert; Axelsen, Holger Bock

2010-09-01

This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic-logical operations on two n-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible ALU for a programmable computing device is possible and that the V-shape design is a very versatile approach to the design of quantum networks.

Design of multi-mode compatible image acquisition system for HD area array CCD

NASA Astrophysics Data System (ADS)

Wang, Chen; Sui, Xiubao

2014-11-01

Combining with the current development trend in video surveillance-digitization and high-definition, a multimode-compatible image acquisition system for HD area array CCD is designed. The hardware and software designs of the color video capture system of HD area array CCD KAI-02150 presented by Truesense Imaging company are analyzed, and the structure parameters of the HD area array CCD and the color video gathering principle of the acquisition system are introduced. Then, the CCD control sequence and the timing logic of the whole capture system are realized. The noises of the video signal (KTC noise and 1/f noise) are filtered by using the Correlated Double Sampling (CDS) technique to enhance the signal-to-noise ratio of the system. The compatible designs in both software and hardware for the two other image sensors of the same series: KAI-04050 and KAI-08050 are put forward; the effective pixels of these two HD image sensors are respectively as many as four million and eight million. A Field Programmable Gate Array (FPGA) is adopted as the key controller of the system to perform the modularization design from top to bottom, which realizes the hardware design by software and improves development efficiency. At last, the required time sequence driving is simulated accurately by the use of development platform of Quartus II 12.1 combining with VHDL. The result of the simulation indicates that the driving circuit is characterized by simple framework, low power consumption, and strong anti-interference ability, which meet the demand of miniaturization and high-definition for the current tendency.

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Quantum cellular automata

NASA Astrophysics Data System (ADS)

Porod, Wolfgang; Lent, Craig S.; Bernstein, Gary H.

1994-06-01

The Notre Dame group has developed a new paradigm for ultra-dense and ultra-fast information processing in nanoelectronic systems. These Quantum Cellular Automata (QCA's) are the first concrete proposal for a technology based on arrays of coupled quantum dots. The basic building block of these cellular arrays is the Notre Dame Logic Cell, as it has been called in the literature. The phenomenon of Coulomb exclusion, which is a synergistic interplay of quantum confinement and Coulomb interaction, leads to a bistable behavior of each cell which makes possible their use in large-scale cellular arrays. The physical interaction between neighboring cells has been exploited to implement logic functions. New functionality may be achieved in this fashion, and the Notre Dame group invented a versatile majority logic gate. In a series of papers, the feasibility of QCA wires, wire crossing, inverters, and Boolean logic gates was demonstrated. A major finding is that all logic functions may be integrated in a hierarchial fashion which allows the design of complicated QCA structures. The most complicated system which was simulated to date is a one-bit full adder consisting of some 200 cells. In addition to exploring these new concepts, efforts are under way to physically realize such structures both in semiconductor and metal systems. Extensive modeling work of semiconductor quantum dot structures has helped identify optimum design parameters for QCA experimental implementations.

Boolean logic tree of graphene-based chemical system for molecular computation and intelligent molecular search query.

PubMed

Huang, Wei Tao; Luo, Hong Qun; Li, Nian Bing

2014-05-06

The most serious, and yet unsolved, problem of constructing molecular computing devices consists in connecting all of these molecular events into a usable device. This report demonstrates the use of Boolean logic tree for analyzing the chemical event network based on graphene, organic dye, thrombin aptamer, and Fenton reaction, organizing and connecting these basic chemical events. And this chemical event network can be utilized to implement fluorescent combinatorial logic (including basic logic gates and complex integrated logic circuits) and fuzzy logic computing. On the basis of the Boolean logic tree analysis and logic computing, these basic chemical events can be considered as programmable "words" and chemical interactions as "syntax" logic rules to construct molecular search engine for performing intelligent molecular search query. Our approach is helpful in developing the advanced logic program based on molecules for application in biosensing, nanotechnology, and drug delivery.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Flight dynamics analysis and simulation of heavy lift airships. Volume 5: Programmer's manual

NASA Technical Reports Server (NTRS)

Ringland, R. F.; Tischler, M. B.; Jex, H. R.; Emmen, R. D.; Ashkenas, I. L.

1982-01-01

The Programmer's Manual contains explanations of the logic embodied in the various program modules, a dictionary of program variables, a subroutine listing, subroutine/common block/cross reference listing, and a calling/called subroutine cross reference listing.

The Art of Electronics

NASA Astrophysics Data System (ADS)

Horowitz, Paul; Hill, Winfield

2015-04-01

1. Foundations; 2. Bipolar transistors; 3. Field effect transistors; 4. Operational amplifiers; 5. Precision circuits; 6. Filters; 7. Oscillators and timers; 8. Low noise techniques and transimpedance; 9. Power regulation; 10. Digital electronics; 11. Programmable logic devices; 12. Logical interfacing; 13. Digital meets analog; 14. Computers, controllers, and data links; 15. Microcontrollers.

Optical triple-in digital logic using nonlinear optical four-wave mixing

NASA Astrophysics Data System (ADS)

Widjaja, Joewono; Tomita, Yasuo

1995-08-01

A new programmable optical processor is proposed for implementing triple-in combinatorial digital logic that uses four-wave mixing. Binary-coded decimal-to-octal decoding is experimentally demonstrated by use of a photorefractive BaTiO 3 crystal. The result confirms the feasibility of the proposed system.

A String Search Marketing Application Using Visual Programming

ERIC Educational Resources Information Center

Chin, Jerry M.; Chin, Mary H.; Van Landuyt, Cathryn

2013-01-01

This paper demonstrates the use of programing software that provides the student programmer visual cues to construct the code to a student programming assignment. This method does not disregard or minimize the syntax or required logical constructs. The student can concentrate more on the logic and less on the language itself.

V&V Plan for FPGA-based ESF-CCS Using System Engineering Approach.

NASA Astrophysics Data System (ADS)

Maerani, Restu; Mayaka, Joyce; El Akrat, Mohamed; Cheon, Jung Jae

2018-02-01

Instrumentation and Control (I&C) systems play an important role in maintaining the safety of Nuclear Power Plant (NPP) operation. However, most current I&C safety systems are based on Programmable Logic Controller (PLC) hardware, which is difficult to verify and validate, and is susceptible to software common cause failure. Therefore, a plan for the replacement of the PLC-based safety systems, such as the Engineered Safety Feature - Component Control System (ESF-CCS), with Field Programmable Gate Arrays (FPGA) is needed. By using a systems engineering approach, which ensures traceability in every phase of the life cycle, from system requirements, design implementation to verification and validation, the system development is guaranteed to be in line with the regulatory requirements. The Verification process will ensure that the customer and stakeholder’s needs are satisfied in a high quality, trustworthy, cost efficient and schedule compliant manner throughout a system’s entire life cycle. The benefit of the V&V plan is to ensure that the FPGA based ESF-CCS is correctly built, and to ensure that the measurement of performance indicators has positive feedback that “do we do the right thing” during the re-engineering process of the FPGA based ESF-CCS.

Design and FPGA implementation for MAC layer of Ethernet PON

NASA Astrophysics Data System (ADS)

Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

2004-04-01

Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

Training a molecular automaton to play a game

NASA Astrophysics Data System (ADS)

Pei, Renjun; Matamoros, Elizabeth; Liu, Manhong; Stefanovic, Darko; Stojanovic, Milan N.

2010-11-01

Research at the interface between chemistry and cybernetics has led to reports of `programmable molecules', but what does it mean to say `we programmed a set of solution-phase molecules to do X'? A survey of recently implemented solution-phase circuitry indicates that this statement could be replaced with `we pre-mixed a set of molecules to do X and functional subsets of X'. These hard-wired mixtures are then exposed to a set of molecular inputs, which can be interpreted as being keyed to human moves in a game, or as assertions of logical propositions. In nucleic acids-based systems, stemming from DNA computation, these inputs can be seen as generic oligonucleotides. Here, we report using reconfigurable nucleic acid catalyst-based units to build a multipurpose reprogrammable molecular automaton that goes beyond single-purpose `hard-wired' molecular automata. The automaton covers all possible responses to two consecutive sets of four inputs (such as four first and four second moves for a generic set of trivial two-player two-move games). This is a model system for more general molecular field programmable gate array (FPGA)-like devices that can be programmed by example, which means that the operator need not have any knowledge of molecular computing methods.

Training a molecular automaton to play a game.

PubMed

Pei, Renjun; Matamoros, Elizabeth; Liu, Manhong; Stefanovic, Darko; Stojanovic, Milan N

2010-11-01

Research at the interface between chemistry and cybernetics has led to reports of 'programmable molecules', but what does it mean to say 'we programmed a set of solution-phase molecules to do X'? A survey of recently implemented solution-phase circuitry indicates that this statement could be replaced with 'we pre-mixed a set of molecules to do X and functional subsets of X'. These hard-wired mixtures are then exposed to a set of molecular inputs, which can be interpreted as being keyed to human moves in a game, or as assertions of logical propositions. In nucleic acids-based systems, stemming from DNA computation, these inputs can be seen as generic oligonucleotides. Here, we report using reconfigurable nucleic acid catalyst-based units to build a multipurpose reprogrammable molecular automaton that goes beyond single-purpose 'hard-wired' molecular automata. The automaton covers all possible responses to two consecutive sets of four inputs (such as four first and four second moves for a generic set of trivial two-player two-move games). This is a model system for more general molecular field programmable gate array (FPGA)-like devices that can be programmed by example, which means that the operator need not have any knowledge of molecular computing methods.

Design automation techniques for custom LSI arrays

NASA Technical Reports Server (NTRS)

Feller, A.

1975-01-01

The standard cell design automation technique is described as an approach for generating random logic PMOS, CMOS or CMOS/SOS custom large scale integration arrays with low initial nonrecurring costs and quick turnaround time or design cycle. The system is composed of predesigned circuit functions or cells and computer programs capable of automatic placement and interconnection of the cells in accordance with an input data net list. The program generates a set of instructions to drive an automatic precision artwork generator. A series of support design automation and simulation programs are described, including programs for verifying correctness of the logic on the arrays, performing dc and dynamic analysis of MOS devices, and generating test sequences.

C-MOS bulk metal design handbook. [LSI standard cell (circuits)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The LSI standard cell array technique was used in the fabrication of more than 20 CMOS custom arrays. This technique consists of a series of computer programs and design automation techniques referred to as the Computer Aided Design And Test (CADAT) system that automatically translate a partitioned logic diagram into a set of instructions for driving an automatic plotter which generates precision mask artwork for complex LSI arrays of CMOS standard cells. The standard cell concept for producing LSI arrays begins with the design, layout, and validation of a group of custom circuits called standard cells. Once validated, these cells are given identification or pattern numbers and are permanently stored. To use one of these cells in a logic design, the user calls for the desired cell by pattern number. The Place, Route in Two Dimension (PR2D) computer program is then used to automatically generate the metalization and/or tunnels to interconnect the standard cells into the required function. Data sheets that describe the function, artwork, and performance of each of the standard cells, the general procedure for implementation of logic in CMOS standard cells, and additional detailed design information are presented.

Design of an FPGA-based electronic flow regulator (EFR) for spacecraft propulsion system

NASA Astrophysics Data System (ADS)

Manikandan, J.; Jayaraman, M.; Jayachandran, M.

2011-02-01

This paper describes a scheme for electronically regulating the flow of propellant to the thruster from a high-pressure storage tank used in spacecraft application. Precise flow delivery of propellant to thrusters ensures propulsion system operation at best efficiency by maximizing the propellant and power utilization for the mission. The proposed field programmable gate array (FPGA) based electronic flow regulator (EFR) is used to ensure precise flow of propellant to the thrusters from a high-pressure storage tank used in spacecraft application. This paper presents hardware and software design of electronic flow regulator and implementation of the regulation logic onto an FPGA.Motivation for proposed FPGA-based electronic flow regulation is on the disadvantages of conventional approach of using analog circuits. Digital flow regulation overcomes the analog equivalent as digital circuits are highly flexible, are not much affected due to noise, accurate performance is repeatable, interface is easier to computers, storing facilities are possible and finally failure rate of digital circuits is less. FPGA has certain advantages over ASIC and microprocessor/micro-controller that motivated us to opt for FPGA-based electronic flow regulator. Also the control algorithm being software, it is well modifiable without changing the hardware. This scheme is simple enough to adopt for a wide range of applications, where the flow is to be regulated for efficient operation.The proposed scheme is based on a space-qualified re-configurable field programmable gate arrays (FPGA) and hybrid micro circuit (HMC). A graphical user interface (GUI) based application software is also developed for debugging, monitoring and controlling the electronic flow regulator from PC COM port.

A Field-Programmable Gate Array (FPGA) TDC for the Fermilab SeaQuest (E906) Experiment and Its Test with a Novel External Wave Union Launcher

NASA Astrophysics Data System (ADS)

Wang, Su-Yin; Wu, Jinyuan; Yao, Shi-Hong; Chang, Wen-Chen

2014-12-01

We developed a field-programmable gate array (FPGA) TDC module for the tracking detectors of the Fermilab SeaQuest (E906) experiment, including drift chambers, proportional tubes, and hodoscopes. This 64-channel TDC module had a 6U VMEbus form factor and was equipped with a low-power, radiation-hardened Microsemi ProASIC3 Flash-based FPGA. The design of the new FPGA firmware (Run2-TDC) aimed to reduce the data volume and data acquisition (DAQ) deadtime. The firmware digitized multiple input hits of both polarities while allowing users to turn on a multiple-hit elimination logic to remove after-pulses in the wire chambers and proportional tubes. A scaler was implemented in the firmware to allow for recording the number of hits in each channel. The TDC resolution was determined by an internal cell delay of 450 ps. A measurement precision of 200 ps was achieved. We used five kinds of tests to ensure the qualification of 93 TDCs in mass production. We utilized the external wave union launcher in our test to improve the TDC's measurement precision and also to illustrate how to construct the Wave Union TDC using an existing multi-hit TDC without modifying its firmware. Measurement precision was improved by a factor of about two (108 ps) based on the four-edge wave union. Better measurement precision (69 ps) was achieved by combining the approaches of Wave Union TDC and multiple-channel ganging.

Implementation of a Loosely-Coupled Lockstep Approach in the Xilinx Zynq-7000 All Programmable SoC for High Consequence Applications

DTIC Science & Technology

2017-03-01

Implementation of a Loosely-Coupled Lockstep Approach in the Xilinx Zynq-7000 All Programmable SoC™ for High Consequence Applications Ryan D...sandia.gov Abstract: For high consequence applications requiring information assurance, the architecture of the Xilinx Zynq- 7000 All Programmable ...transaction checker residing in the Programmable Logic portion of the Zynq device will be discussed along with implementation results and latency

Maskless, reticle-free, lithography

DOEpatents

Ceglio, N.M.; Markle, D.A.

1997-11-25

A lithography system in which the mask or reticle, which usually carries the pattern to be printed onto a substrate, is replaced by a programmable array of binary (i.e. on/off) light valves or switches which can be programmed to replicate a portion of the pattern each time an illuminating light source is flashed. The pattern of light produced by the programmable array is imaged onto a lithographic substrate which is mounted on a scanning stage as is common in optical lithography. The stage motion and the pattern of light displayed by the programmable array are precisely synchronized with the flashing illumination system so that each flash accurately positions the image of the pattern on the substrate. This is achieved by advancing the pattern held in the programmable array by an amount which corresponds to the travel of the substrate stage each time the light source flashes. In this manner the image is built up of multiple flashes and an isolated defect in the array will only have a small effect on the printed pattern. The method includes projection lithographies using radiation other than optical or ultraviolet light. The programmable array of binary switches would be used to control extreme ultraviolet (EUV), x-ray, or electron, illumination systems, obviating the need for stable, defect free masks for projection EUV, x-ray, or electron, lithographies. 7 figs.

Maskless, reticle-free, lithography

DOEpatents

Ceglio, Natale M.; Markle, David A.

1997-11-25

A lithography system in which the mask or reticle, which usually carries the pattern to be printed onto a substrate, is replaced by a programmable array of binary (i.e. on/off) light valves or switches which can be programmed to replicate a portion of the pattern each time an illuminating light source is flashed. The pattern of light produced by the programmable array is imaged onto a lithographic substrate which is mounted on a scanning stage as is common in optical lithography. The stage motion and the pattern of light displayed by the programmable array are precisely synchronized with the flashing illumination system so that each flash accurately positions the image of the pattern on the substrate. This is achieved by advancing the pattern held in the programmable array by an amount which corresponds to the travel of the substrate stage each time the light source flashes. In this manner the image is built up of multiple flashes and an isolated defect in the array will only have a small effect on the printed pattern. The method includes projection lithographies using radiation other than optical or ultraviolet light. The programmable array of binary switches would be used to control extreme ultraviolet (EUV), x-ray, or electron, illumination systems, obviating the need for stable, defect free masks for projection EUV, x-ray, or electron, lithographies.

Programmed optoelectronic time-pulse coded relational processor as base element for sorting neural networks

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Bardachenko, Vitaliy F.; Nikolsky, Alexander I.; Lazarev, Alexander A.

2007-04-01

In the paper we show that the biologically motivated conception of the use of time-pulse encoding gives the row of advantages (single methodological basis, universality, simplicity of tuning, training and programming et al) at creation and designing of sensor systems with parallel input-output and processing, 2D-structures of hybrid and neuro-fuzzy neurocomputers of next generations. We show principles of construction of programmable relational optoelectronic time-pulse coded processors, continuous logic, order logic and temporal waves processes, that lie in basis of the creation. We consider structure that executes extraction of analog signal of the set grade (order), sorting of analog and time-pulse coded variables. We offer optoelectronic realization of such base relational elements of order logic, which consists of time-pulse coded phototransformers (pulse-width and pulse-phase modulators) with direct and complementary outputs, sorting network on logical elements and programmable commutations blocks. We make estimations of basic technical parameters of such base devices and processors on their basis by simulation and experimental research: power of optical input signals - 0.200-20 μW, processing time - microseconds, supply voltage - 1.5-10 V, consumption power - hundreds of microwatts per element, extended functional possibilities, training possibilities. We discuss some aspects of possible rules and principles of training and programmable tuning on the required function, relational operation and realization of hardware blocks for modifications of such processors. We show as on the basis of such quasiuniversal hardware simple block and flexible programmable tuning it is possible to create sorting machines, neural networks and hybrid data-processing systems with the untraditional numerical systems and pictures operands.

A preliminary study of molecular dynamics on reconfigurable computers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wolinski, C.; Trouw, F. R.; Gokhale, M.

2003-01-01

In this paper we investigate the performance of platform FPGAs on a compute-intensive, floating-point-intensive supercomputing application, Molecular Dynamics (MD). MD is a popular simulation technique to track interacting particles through time by integrating their equations of motion. One part of the MD algorithm was implemented using the Fabric Generator (FG)[l I ] and mapped onto several reconfigurable logic arrays. FG is a Java-based toolset that greatly accelerates construction of the fabrics from an abstract technology independent representation. Our experiments used technology-independent IEEE 32-bit floating point operators so that the design could be easily re-targeted. Experiments were performed using both non-pipelinedmore » and pipelined floating point modules. We present results for the Altera Excalibur ARM System on a Programmable Chip (SoPC), the Altera Strath EPlS80, and the Xilinx Virtex-N Pro 2VP.50. The best results obtained were 5.69 GFlops at 8OMHz(Altera Strath EPlS80), and 4.47 GFlops at 82 MHz (Xilinx Virtex-II Pro 2VF50). Assuming a lOWpower budget, these results compare very favorably to a 4Gjlop/40Wprocessing/power rate for a modern Pentium, suggesting that reconfigurable logic can achieve high performance at low power on jloating-point-intensivea pplications.« less

Program to Optimize Simulated Trajectories (POST). Volume 3: Programmer's manual

NASA Technical Reports Server (NTRS)

Brauer, G. L.; Cornick, D. E.; Habeger, A. R.; Petersen, F. M.; Stevenson, R.

1975-01-01

Information pertinent to the programmer and relating to the program to optimize simulated trajectories (POST) is presented. Topics discussed include: program structure and logic, subroutine listings and flow charts, and internal FORTRAN symbols. The POST core requirements are summarized along with program macrologic.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brusati, M.; Camplani, A.; Cannon, M.

SRAM-ba8ed Field Programmable Gate Array (FPGA) logic devices arc very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which ismore » a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. :!\\litigation techniques such as Triple Modular Redundancy (T:t\\IR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

D'Huys, Otti, E-mail: otti.dhuys@phy.duke.edu; Haynes, Nicholas D.; Lohmann, Johannes

Autonomous Boolean networks are commonly used to model the dynamics of gene regulatory networks and allow for the prediction of stable dynamical attractors. However, most models do not account for time delays along the network links and noise, which are crucial features of real biological systems. Concentrating on two paradigmatic motifs, the toggle switch and the repressilator, we develop an experimental testbed that explicitly includes both inter-node time delays and noise using digital logic elements on field-programmable gate arrays. We observe transients that last millions to billions of characteristic time scales and scale exponentially with the amount of time delaysmore » between nodes, a phenomenon known as super-transient scaling. We develop a hybrid model that includes time delays along network links and allows for stochastic variation in the delays. Using this model, we explain the observed super-transient scaling of both motifs and recreate the experimentally measured transient distributions.« less

A Practical, Hardware Friendly MMSE Detector for MIMO-OFDM-Based Systems

NASA Astrophysics Data System (ADS)

Kim, Hun Seok; Zhu, Weijun; Bhatia, Jatin; Mohammed, Karim; Shah, Anish; Daneshrad, Babak

2008-12-01

Design and implementation of a highly optimized MIMO (multiple-input multiple-output) detector requires cooptimization of the algorithm with the underlying hardware architecture. Special attention must be paid to application requirements such as throughput, latency, and resource constraints. In this work, we focus on a highly optimized matrix inversion free [InlineEquation not available: see fulltext.] MMSE (minimum mean square error) MIMO detector implementation. The work has resulted in a real-time field-programmable gate array-based implementation (FPGA-) on a Xilinx Virtex-2 6000 using only 9003 logic slices, 66 multipliers, and 24 Block RAMs (less than 33% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput with a small 2.77-microsecond latency. The designed [InlineEquation not available: see fulltext.] linear MMSE MIMO detector is capable of complying with the proposed IEEE 802.11n standard.

Hardware Architecture Study for NASA's Space Software Defined Radios

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

2008-01-01

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Feasibility study for future implantable neural-silicon interface devices.

PubMed

Al-Armaghany, Allann; Yu, Bo; Mak, Terrence; Tong, Kin-Fai; Sun, Yihe

2011-01-01

The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and transmission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. Field programmable logic arrays (FPGAs) are used to evaluate various structures.

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

2008-01-01

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

SAD-Based Stereo Matching Using FPGAs

NASA Astrophysics Data System (ADS)

Ambrosch, Kristian; Humenberger, Martin; Kubinger, Wilfried; Steininger, Andreas

In this chapter we present a field-programmable gate array (FPGA) based stereo matching architecture. This architecture uses the sum of absolute differences (SAD) algorithm and is targeted at automotive and robotics applications. The disparity maps are calculated using 450×375 input images and a disparity range of up to 150 pixels. We discuss two different implementation approaches for the SAD and analyze their resource usage. Furthermore, block sizes ranging from 3×3 up to 11×11 and their impact on the consumed logic elements as well as on the disparity map quality are discussed. The stereo matching architecture enables a frame rate of up to 600 fps by calculating the data in a highly parallel and pipelined fashion. This way, a software solution optimized by using Intel's Open Source Computer Vision Library running on an Intel Pentium 4 with 3 GHz clock frequency is outperformed by a factor of 400.

High-Speed Current dq PI Controller for Vector Controlled PMSM Drive

PubMed Central

Reaz, Mamun Bin Ibne; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era. PMID:24574913

Design of a ``Digital Atlas Vme Electronics'' (DAVE) module

NASA Astrophysics Data System (ADS)

Goodrick, M.; Robinson, D.; Shaw, R.; Postranecky, M.; Warren, M.

2012-01-01

ATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' (``DAVE''). The unit is designed to provide a versatile array of interface and logic resources, including a large FPGA. It interfaces to both VME bus and USB hosts. DAVE aims to provide exact ATLAS CTP (ATLAS Central Trigger Processor) functionality, with random trigger, simple and complex deadtime, ECR (Event Counter Reset), BCR (Bunch Counter Reset) etc. being generated to give exactly the same conditions in standalone running as experienced in combined runs. DAVE provides additional hardware and a large amount of free firmware resource to allow users to add or change functionality. The combination of the large number of individually programmable inputs and outputs in various formats, with very large external RAM and other components all connected to the FPGA, also makes DAVE a powerful and versatile FPGA utility card.

Method and apparatus for detecting and determining event characteristics with reduced data collection

NASA Technical Reports Server (NTRS)

Totman, Peter D. (Inventor); Everton, Randy L. (Inventor); Egget, Mark R. (Inventor); Macon, David J. (Inventor)

2007-01-01

A method and apparatus for detecting and determining event characteristics such as, for example, the material failure of a component, in a manner which significantly reduces the amount of data collected. A sensor array, including a plurality of individual sensor elements, is coupled to a programmable logic device (PLD) configured to operate in a passive state and an active state. A triggering event is established such that the PLD records information only upon detection of the occurrence of the triggering event which causes a change in state within one or more of the plurality of sensor elements. Upon the occurrence of the triggering event, the change in state of the one or more sensor elements causes the PLD to record in memory which sensor element detected the event and at what time the event was detected. The PLD may be coupled with a computer for subsequent downloading and analysis of the acquired data.

A DNAzyme-mediated logic gate for programming molecular capture and release on DNA origami.

PubMed

Li, Feiran; Chen, Haorong; Pan, Jing; Cha, Tae-Gon; Medintz, Igor L; Choi, Jong Hyun

2016-06-28

Here we design a DNA origami-based site-specific molecular capture and release platform operated by a DNAzyme-mediated logic gate process. We show the programmability and versatility of this platform with small molecules, proteins, and nanoparticles, which may also be controlled by external light signals.

Programmable and Multiparameter DNA-Based Logic Platform For Cancer Recognition and Targeted Therapy

PubMed Central

2014-01-01

The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy. PMID:25361164

Programmable Regulation of DNA Conjugation to Gold Nanoparticles via Strand Displacement.

PubMed

Zhang, Cheng; Wu, Ranfeng; Li, Yifan; Zhang, Qiang; Yang, Jing

2017-10-31

Methods for conjugating DNA to gold nanoparticles (AuNPs) have recently attracted considerable attention. The ability to control such conjugation in a programmable way is of great interest. Here, we have developed a logic-based method for manipulating the conjugation of thiolated DNA species to AuNPs via cascading DNA strand displacement. Using this method, several logic-based operation systems are established and up to three kinds of DNA signals are introduced at the same time. In addition, a more sensitive catalytic logic-based operation is also achieved based on an entropy-driven process. In the experiment, all of the DNA/AuNPs conjugation results are verified by agrose gel. This strategy promises great potential for automatically conjugating DNA stands onto label-free gold nanoparticles and can be extended to constructing DNA/nanoparticle devices for applications in diagnostics, biosensing, and molecular robotics.

Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays

NASA Technical Reports Server (NTRS)

Edwards, R. Timothy; Strohbehn, Kim; Jaskulek, Steven E.; Katz, Richard

1999-01-01

Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.

Design and implementation of projects with Xilinx Zynq FPGA: a practical case

NASA Astrophysics Data System (ADS)

Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

Mount control system of the ASTRI SST-2M prototype for the Cherenkov Telescope Array

NASA Astrophysics Data System (ADS)

Antolini, Elisa; Tosti, Gino; Tanci, Claudio; Bagaglia, Marco; Canestrari, Rodolfo; Cascone, Enrico; Gambini, Giorgio; Nucciarelli, Giuliano; Pareschi, Giovanni; Scuderi, Salvo; Stringhetti, Luca; Busatta, Andrea; Giacomel, Stefano; Marchiori, Gianpietro; Manfrin, Cristiana; Marcuzzi, Enrico; Di Michele, Daniele; Grigolon, Carlo; Guarise, Paolo

2016-08-01

The ASTRI SST-2M telescope is an end-to-end prototype proposed for the Small Size class of Telescopes (SST) of the future Cherenkov Telescope Array (CTA). The prototype is installed in Italy at the INAF observing station located at Serra La Nave on Mount Etna (Sicily) and it was inaugurated in September 2014. This paper presents the software and hardware architecture and development of the system dedicated to the control of the mount, health, safety and monitoring systems of the ASTRI SST-2M telescope prototype. The mount control system installed on the ASTRI SST-2M telescope prototype makes use of standard and widely deployed industrial hardware and software. State of the art of the control and automation industries was selected in order to fulfill the mount related functional and safety requirements with assembly compactness, high reliability, and reduced maintenance. The software package was implemented with the Beckhoff TwinCAT version 3 environment for the software Programmable Logical Controller (PLC), while the control electronics have been chosen in order to maximize the homogeneity and the real time performance of the system. The integration with the high level controller (Telescope Control System) has been carried out by choosing the open platform communications Unified Architecture (UA) protocol, supporting rich data model while offering compatibility with the PLC platform. In this contribution we show how the ASTRI approach for the design and implementation of the mount control system has made the ASTRI SST-2M prototype a standalone intelligent machine, able to fulfill requirements and easy to be integrated in an array configuration such as the future ASTRI mini-array proposed to be installed at the southern site of the Cherenkov Telescope Array (CTA).

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

1999-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter the focus is on some experimental data on low voltage drop out regulators to support mixed 5 and 3.3 volt systems. A discussion of the Small Explorer WIRE spacecraft will also be given. Lastly, we show take a first look at robust state machines in Hardware Description Languages (VHDL) and their use in critical systems. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or e-mail.

Coupling Photonics and Coherent Spintronics for Low-Loss Flexible Optical Logic

DTIC Science & Technology

2015-12-02

AFRL-AFOSR-VA-TR-2016-0055 Coupling photonics and coherent spintronics for low-loss flexible optical logic Jesse Berezovsky CASE WESTERN RESERVE UNIV...2012 - 14/06/2015 4. TITLE AND SUBTITLE Coupling photonics and coherent spintronics for low-loss flexible optical logic 5a. CONTRACT NUMBER 5b...into devices, ranging from macroscopic optical cavities, to arrays of microlens cavities, to quantum dot-impregnated integrated polymer waveguides

Programmer's guide for the GNAT computer program (numerical analysis of stratification in supercritical oxygen)

NASA Technical Reports Server (NTRS)

Heinmiller, J. P.

1971-01-01

This document is the programmer's guide for the GNAT computer program developed under MSC/TRW Task 705-2, Apollo cryogenic storage system analysis, subtask 2, is reported. Detailed logic flow charts and compiled program listings are provided for all program elements.

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

PubMed

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Wire like link for cycle reproducible and cycle accurate hardware accelerator

DOEpatents

Asaad, Sameh; Kapur, Mohit; Parker, Benjamin D

2015-04-07

First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

Microwave scanning beam approach and landing system phased array antenna.

DOT National Transportation Integrated Search

1971-09-01

The design, operating instructions, detailed logic circuitry, and antenna test range results for the electronic circular scanning phased array developed at TSC (DOTSCAN) are described. Components developed for this effort are also described, and test...

Binary logic based purely on Fresnel diffraction

NASA Astrophysics Data System (ADS)

Hamam, H.; de Bougrenet de La Tocnaye, J. L.

1995-09-01

Binary logic operations on two-dimensional data arrays are achieved by use of the self-imaging properties of Fresnel diffraction. The fields diffracted by periodic objects can be considered as the superimposition of weighted and shifted replicas of original objects. We show that a particular spatial organization of the input data can result in logical operations being performed on these data in the considered diffraction planes. Among various advantages, this approach is shown to allow the implementation of dual-track, nondissipative logical operators. Image algebra is presented as an experimental illustration of this principle.

Time-space modal logic for verification of bit-slice circuits

NASA Astrophysics Data System (ADS)

Hiraishi, Hiromi

1996-03-01

The major goal of this paper is to propose a new modal logic aiming at formal verification of bit-slice circuits. The new logic is called as time-space modal logic and its major feature is that it can handle two transition relations: one for time transition and the other for space transition. As for a verification algorithm, a symbolic model checking algorithm of the new logic is shown. This could be applicable to verification of bit-slice microprocessor of infinite bit width and 1D systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

Addition of flexible body option to the TOLA computer program. Part 2: User and programmer documentation

NASA Technical Reports Server (NTRS)

Dick, J. W.; Benda, B. J.

1975-01-01

User and programmer oriented documentation for the flexible body option of the Takeoff and Landing Analysis (TOLA) computer program are provided. The user information provides sufficient knowledge of the development and use of the option to enable the engineering user to successfully operate the modified program and understand the results. The programmer's information describes the option structure and logic enabling a programmer to make major revisions to this part of the TOLA computer program.

Programme Costing - A Logical Step Toward Improved Management.

ERIC Educational Resources Information Center

McDougall, Ronald N.

The analysis of costs of university activities from a functional or program point of view, rather than an organizational unit basis, is not only an imperative for the planning and management of universities, but also a logical method of examing the costs of university operations. A task force of the Committee of Finance Officers-Universities of…

An iLab for Teaching Advanced Logic Concepts with Hardware Descriptive Languages

ERIC Educational Resources Information Center

Ayodele, Kayode P.; Inyang, Isaac A.; Kehinde, Lawrence O.

2015-01-01

One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on…

R-189 (C-620) air compressor control logic software documentation. Revision 1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Walter, K.E.

1995-06-08

This relates to FFTF plant air compressors. Purpose of this document is to provide an updated Computer Software Description for the software to be used on R-189 (C-620-C) air compressor programmable controllers. Logic software design changes were required to allow automatic starting of a compressor that had not been previously started.

EHWPACK: An evolvable hardware environment using the SPICE simulator and the Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Keymeulen, D.; Klimeck, G.; Zebulum, R.; Stoica, A.; Jin, Y.; Lazaro, C.

2000-01-01

This paper describes the EHW development system, a tool that performs the evolutionary synthesis of electronic circuits, using the SPICE simulator and the Field Programmable Transistor Array hardware (FPTA) developed at JPL.

Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.

PubMed

Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou

2017-11-20

A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Studies in optical parallel processing. [All optical and electro-optic approaches

NASA Technical Reports Server (NTRS)

Lee, S. H.

1978-01-01

Threshold and A/D devices for converting a gray scale image into a binary one were investigated for all-optical and opto-electronic approaches to parallel processing. Integrated optical logic circuits (IOC) and optical parallel logic devices (OPA) were studied as an approach to processing optical binary signals. In the IOC logic scheme, a single row of an optical image is coupled into the IOC substrate at a time through an array of optical fibers. Parallel processing is carried out out, on each image element of these rows, in the IOC substrate and the resulting output exits via a second array of optical fibers. The OPAL system for parallel processing which uses a Fabry-Perot interferometer for image thresholding and analog-to-digital conversion, achieves a higher degree of parallel processing than is possible with IOC.

Generalized look-ahead number conversion from signed digit to complement representation with optical logic operations

NASA Astrophysics Data System (ADS)

Qian, Feng; Li, Guoqiang

2001-12-01

In this paper a generalized look-ahead logic algorithm for number conversion from signed-digit to its complement representation is developed. By properly encoding the signed digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quaternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using electron-trapping device is employed, which is suitable for realizing complex logic functions in the form of sum-of-product. The proposed algorithm and architecture are compatible with a general-purpose optoelectronic computing system.

Catalytic nucleic acids (DNAzymes) as functional units for logic gates and computing circuits: from basic principles to practical applications.

PubMed

Orbach, Ron; Willner, Bilha; Willner, Itamar

2015-03-11

This feature article addresses the implementation of catalytic nucleic acids as functional units for the construction of logic gates and computing circuits, and discusses the future applications of these systems. The assembly of computational modules composed of DNAzymes has led to the operation of a universal set of logic gates, to field programmable logic gates and computing circuits, to the development of multiplexers/demultiplexers, and to full-adder systems. Also, DNAzyme cascades operating as logic gates and computing circuits were demonstrated. DNAzyme logic systems find important practical applications. These include the use of DNAzyme-based systems for sensing and multiplexed analyses, for the development of controlled release and drug delivery systems, for regulating intracellular biosynthetic pathways, and for the programmed synthesis and operation of cascades.

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

NASA Astrophysics Data System (ADS)

Ayyoub, Slimani; Achour, Benslama

2017-08-01

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Raising a Programmer: Teaching Saudi Children How to Code

ERIC Educational Resources Information Center

Meccawy, Maram

2017-01-01

Teaching computer coding to children from a young age provides with them a competitive advantage for the future in a continually changing workplace. Programming strengthens logical and critical thinking as well as problem-solving skills, which lead to creative solutions for today's problems. The Little Programmer is an application for mobile…

Multiprog Virtual Laboratory Applied to PLC Programming Learning

ERIC Educational Resources Information Center

Shyr, Wen-Jye

2010-01-01

This study develops a Multiprog virtual laboratory for a mechatronics education designed to teach how to programme a programmable logic controller (PLC). The study was carried out with 34 students in the Department of Industry Education and Technology at National Changhua University of Education in Taiwan. In total, 17 students were assigned to…

Rapid geodesic mapping of brain functional connectivity: implementation of a dedicated co-processor in a field-programmable gate array (FPGA) and application to resting state functional MRI.

PubMed

Minati, Ludovico; Cercignani, Mara; Chan, Dennis

2013-10-01

Graph theory-based analyses of brain network topology can be used to model the spatiotemporal correlations in neural activity detected through fMRI, and such approaches have wide-ranging potential, from detection of alterations in preclinical Alzheimer's disease through to command identification in brain-machine interfaces. However, due to prohibitive computational costs, graph-based analyses to date have principally focused on measuring connection density rather than mapping the topological architecture in full by exhaustive shortest-path determination. This paper outlines a solution to this problem through parallel implementation of Dijkstra's algorithm in programmable logic. The processor design is optimized for large, sparse graphs and provided in full as synthesizable VHDL code. An acceleration factor between 15 and 18 is obtained on a representative resting-state fMRI dataset, and maps of Euclidean path length reveal the anticipated heterogeneous cortical involvement in long-range integrative processing. These results enable high-resolution geodesic connectivity mapping for resting-state fMRI in patient populations and real-time geodesic mapping to support identification of imagined actions for fMRI-based brain-machine interfaces. Copyright © 2013 IPEM. Published by Elsevier Ltd. All rights reserved.

Real-time plasma control based on the ISTTOK tomography diagnostica)

NASA Astrophysics Data System (ADS)

Carvalho, P. J.; Carvalho, B. B.; Neto, A.; Coelho, R.; Fernandes, H.; Sousa, J.; Varandas, C.; Chávez-Alarcón, E.; Herrera-Velázquez, J. J. E.

2008-10-01

The presently available processing power in generic processing units (GPUs) combined with state-of-the-art programmable logic devices benefits the implementation of complex, real-time driven, data processing algorithms for plasma diagnostics. A tomographic reconstruction diagnostic has been developed for the ISTTOK tokamak, based on three linear pinhole cameras each with ten lines of sight. The plasma emissivity in a poloidal cross section is computed locally on a submillisecond time scale, using a Fourier-Bessel algorithm, allowing the use of the output signals for active plasma position control. The data acquisition and reconstruction (DAR) system is based on ATCA technology and consists of one acquisition board with integrated field programmable gate array (FPGA) capabilities and a dual-core Pentium module running real-time application interface (RTAI) Linux. In this paper, the DAR real-time firmware/software implementation is presented, based on (i) front-end digital processing in the FPGA; (ii) a device driver specially developed for the board which enables streaming data acquisition to the host GPU; and (iii) a fast reconstruction algorithm running in Linux RTAI. This system behaves as a module of the central ISTTOK control and data acquisition system (FIRESIGNAL). Preliminary results of the above experimental setup are presented and a performance benchmarking against the magnetic coil diagnostic is shown.

Code conversion from signed-digit to complement representation based on look-ahead optical logic operations

NASA Astrophysics Data System (ADS)

Li, Guoqiang; Qian, Feng

2001-11-01

We present, for the first time to our knowledge, a generalized lookahead logic algorithm for number conversion from signed-digit to complement representation. By properly encoding the signed-digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed- digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quarternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using an electron-trapping device is employed and experimental results are shown. This optical module is suitable for implementing complex logic functions in the form of the sum of the product. The algorithm and architecture are compatible with a general-purpose optoelectronic computing system.

Logic Design Pathology and Space Flight Electronics

NASA Technical Reports Server (NTRS)

Katz, Richard; Barto, Rod L.; Erickson, K.

1997-01-01

Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

Performance of the Versatile Array of Neutron Detectors at Low Energy (VANDLE)

DOE PAGES

Peters, W. A.; Ilyushkin, S.; Madurga, M.; ...

2016-08-26

The Versatile Array of Neutron Detectors at Low Energy (VANDLE) is a new, highly efficient plastic-scintillator array constructed for decay and transfer reaction experimental setups that require neutron detection. The versatile and modular design allows for customizable experimental setups including beta-delayed neutron spectroscopy and (d,n) transfer reactions in normal and inverse kinematics. The neutron energy and prompt-photon discrimination is determined through the time of flight technique. Fully digital data acquisition electronics and integrated triggering logic enables some VANDLE modules to achieve an intrinsic efficiency over 70% for 300-keV neutrons, measured through two different methods. A custom Geant4 simulation models aspectsmore » of the detector array and the experimental setups to determine efficiency and detector response. Lastly, a low detection threshold, due to the trigger logic and digitizing data acquisition, allowed us to measure the light-yield response curve from elastically scattered carbon nuclei inside the scintillating plastic from incident neutrons with kinetic energies below 2 MeV.« less

Remote Control Laboratory Using EJS Applets and TwinCAT Programmable Logic Controllers

ERIC Educational Resources Information Center

Besada-Portas, E.; Lopez-Orozco, J. A.; de la Torre, L.; de la Cruz, J. M.

2013-01-01

This paper presents a new methodology to develop remote laboratories for systems engineering and automation control courses, based on the combined use of TwinCAT, a laboratory Java server application, and Easy Java Simulations (EJS). The TwinCAT system is used to close the control loop for the selected plants by means of programmable logic…

Toward Automating Web Protocol Configuration for a Programmable Logic Controller Emulator

DTIC Science & Technology

2014-06-19

Security Risks for Industrial Control Systems ,” VDE 2004 Congress, Berlin, Germany, October 2004, pp. 1-7. [Cis12] Cisco, NetFlow Configuration Guide...Date 29 May 2014 Date AFIT-ENG-T-14-J-4 Abstract Industrial Control Systems (ICS) remain vulnerable through attack vectors that exist within programmable...5 2.2 Industrial Control Systems

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

PubMed Central

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

Solar array stepping problems in satellites and solutions

NASA Astrophysics Data System (ADS)

Maharana, P. K.; Goel, P. S.

1992-01-01

The dynamics problems arising due to stepping motion of the solar arrays of spacecraft are studied. To overcome these problems, design improvements in the drive logic based on the phase plane analysis are suggested. The improved designs are applied to the Solar Array Drive Assembly (SADA) of IRS-1B and INSAT-2A satellites. In addition, an alternate torquing strategy for very successful slewing of the arrays, and with minimum excitation of flexible modes, is proposed.

Relevancies of multiple-interaction events and signal-to-noise ratio for Anger-logic based PET detector designs

NASA Astrophysics Data System (ADS)

Peng, Hao

2015-10-01

A fundamental challenge for PET block detector designs is to deploy finer crystal elements while limiting the number of readout channels. The standard Anger-logic scheme including light sharing (an 8 by 8 crystal array coupled to a 2×2 photodetector array with an optical diffuser, multiplexing ratio: 16:1) has been widely used to address such a challenge. Our work proposes a generalized model to study the impacts of two critical parameters on spatial resolution performance of a PET block detector: multiple interaction events and signal-to-noise ratio (SNR). The study consists of the following three parts: (1) studying light output profile and multiple interactions of 511 keV photons within crystal arrays of different crystal widths (from 4 mm down to 1 mm, constant height: 20 mm); (2) applying the Anger-logic positioning algorithm to investigate positioning/decoding uncertainties (i.e., "block effect") in terms of peak-to-valley ratio (PVR), with light sharing, multiple interactions and photodetector SNR taken into account; and (3) studying the dependency of spatial resolution on SNR in the context of modulation transfer function (MTF). The proposed model can be used to guide the development and evaluation of a standard Anger-logic based PET block detector including: (1) selecting/optimizing the configuration of crystal elements for a given photodetector SNR; and (2) predicting to what extent additional electronic multiplexing may be implemented to further reduce the number of readout channels.

Control of Turing patterns and their usage as sensors, memory arrays, and logic gates

NASA Astrophysics Data System (ADS)

Muzika, František; Schreiber, Igor

2013-10-01

We study a model system of three diffusively coupled reaction cells arranged in a linear array that display Turing patterns with special focus on the case of equal coupling strength for all components. As a suitable model reaction we consider a two-variable core model of glycolysis. Using numerical continuation and bifurcation techniques we analyze the dependence of the system's steady states on varying rate coefficient of the recycling step while the coupling coefficients of the inhibitor and activator are fixed and set at the ratios 100:1, 1:1, and 4:5. We show that stable Turing patterns occur at all three ratios but, as expected, spontaneous transition from the spatially uniform steady state to the spatially nonuniform Turing patterns occurs only in the first case. The other two cases possess multiple Turing patterns, which are stabilized by secondary bifurcations and coexist with stable uniform periodic oscillations. For the 1:1 ratio we examine modular spatiotemporal perturbations, which allow for controllable switching between the uniform oscillations and various Turing patterns. Such modular perturbations are then used to construct chemical computing devices utilizing the multiple Turing patterns. By classifying various responses we propose: (a) a single-input resettable sensor capable of reading certain value of concentration, (b) two-input and three-input memory arrays capable of storing logic information, (c) three-input, three-output logic gates performing combinations of logical functions OR, XOR, AND, and NAND.

MSEA--The Department's Microcomputer. The Illinois Series on Educational Applications of Computer. Report No. 27.

ERIC Educational Resources Information Center

Muiznieks, Viktors

This report provides a technical description and operating guidelines for the IMSAI 8080 microcomputer in the Department of Secondary Education at the University of Illinois. An overview of the microcomputer highlights the register array, address logic, arithmetic and logical unit, instruction register and control section, and the data bus buffer.…

Submicron Systems Architecture Project

DTIC Science & Technology

1981-11-01

This project is concerned with the architecture , design , and testing of VLSI Systems. The principal activities in this report period include: The Tree Machine; COPE, The Homogeneous Machine; Computational Arrays; Switch-Level Model for MOS Logic Design; Testing; Local Network and Designer Workstations; Self-timed Systems; Characterization of Deadlock Free Resource Contention; Concurrency Algebra; Language Design and Logic for Program Verification.

Semantically Aware Foundation Environment (SAFE) for Clean-Slate Design of Resilient, Adaptive Secure Hosts (CRASH)

DTIC Science & Technology

2016-02-01

system consists of a high-fidelity hardware simulation using field programmable gate arrays (FPGAs), with a set of runtime services (ConcreteWare...perimeter protection, patch, and pray” is not aligned with the threat. Programmers will not bail us out of this situation (by writing defect free code...hosted on a Field Programmable Gate Array (FPGA), with a set of runtime services (concreteware) running on the hardware. Secure applications can be

Two-dimensional non-volatile programmable p-n junctions

NASA Astrophysics Data System (ADS)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

PubMed

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-03-28

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

Designed cell consortia as fragrance-programmable analog-to-digital converters.

PubMed

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study

PubMed Central

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-01-01

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation. PMID:28350358

Two-dimensional non-volatile programmable p-n junctions.

PubMed

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe 2 /hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 10 4 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Catalytic molecular logic devices by DNAzyme displacement.

PubMed

Brown, Carl W; Lakin, Matthew R; Stefanovic, Darko; Graves, Steven W

2014-05-05

Chemical reactions catalyzed by DNAzymes offer a route to programmable modification of biomolecules for therapeutic purposes. To this end, we have developed a new type of catalytic DNA-based logic gates in which DNAzyme catalysis is controlled via toehold-mediated strand displacement reactions. We refer to these as DNAzyme displacement gates. The use of toeholds to guide input binding provides a favorable pathway for input recognition, and the innate catalytic activity of DNAzymes allows amplification of nanomolar input concentrations. We demonstrate detection of arbitrary input sequences by rational introduction of mismatched bases into inhibitor strands. Furthermore, we illustrate the applicability of DNAzyme displacement to compute logic functions involving multiple logic gates. This work will enable sophisticated logical control of a range of biochemical modifications, with applications in pathogen detection and autonomous theranostics. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Programmable full-adder computations in communicating three-dimensional cell cultures.

PubMed

Ausländer, David; Ausländer, Simon; Pierrat, Xavier; Hellmann, Leon; Rachid, Leila; Fussenegger, Martin

2018-01-01

Synthetic biologists have advanced the design of trigger-inducible gene switches and their assembly into input-programmable circuits that enable engineered human cells to perform arithmetic calculations reminiscent of electronic circuits. By designing a versatile plug-and-play molecular-computation platform, we have engineered nine different cell populations with genetic programs, each of which encodes a defined computational instruction. When assembled into 3D cultures, these engineered cell consortia execute programmable multicellular full-adder logics in response to three trigger compounds.

Development of a Low-Cost and High-speed Single Event Effects Testers based on Reconfigurable Field Programmable Gate Arrays (FPGA)

NASA Technical Reports Server (NTRS)

Howard, J. W.; Kim, H.; Berg, M.; LaBel, K. A.; Stansberry, S.; Friendlich, M.; Irwin, T.

2006-01-01

A viewgraph presentation on the development of a low cost, high speed tester reconfigurable Field Programmable Gata Array (FPGA) is shown. The topics include: 1) Introduction; 2) Objectives; 3) Tester Descriptions; 4) Tester Validations and Demonstrations; 5) Future Work; and 6) Summary.

A simple laser locking system based on a field-programmable gate array.

PubMed

Jørgensen, N B; Birkmose, D; Trelborg, K; Wacker, L; Winter, N; Hilliard, A J; Bason, M G; Arlt, J J

2016-07-01

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The locking system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.

A simple laser locking system based on a field-programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jørgensen, N. B.; Birkmose, D.; Trelborg, K.

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The lockingmore » system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.« less

Water-based and biocompatible 2D crystal inks for all-inkjet-printed heterostructures

NASA Astrophysics Data System (ADS)

McManus, Daryl; Vranic, Sandra; Withers, Freddie; Sanchez-Romaguera, Veronica; Macucci, Massimo; Yang, Huafeng; Sorrentino, Roberto; Parvez, Khaled; Son, Seok-Kyun; Iannaccone, Giuseppe; Kostarelos, Kostas; Fiori, Gianluca; Casiraghi, Cinzia

2017-05-01

Exploiting the properties of two-dimensional crystals requires a mass production method able to produce heterostructures of arbitrary complexity on any substrate. Solution processing of graphene allows simple and low-cost techniques such as inkjet printing to be used for device fabrication. However, the available printable formulations are still far from ideal as they are either based on toxic solvents, have low concentration, or require time-consuming and expensive processing. In addition, none is suitable for thin-film heterostructure fabrication due to the re-mixing of different two-dimensional crystals leading to uncontrolled interfaces and poor device performance. Here, we show a general approach to achieve inkjet-printable, water-based, two-dimensional crystal formulations, which also provide optimal film formation for multi-stack fabrication. We show examples of all-inkjet-printed heterostructures, such as large-area arrays of photosensors on plastic and paper and programmable logic memory devices. Finally, in vitro dose-escalation cytotoxicity assays confirm the biocompatibility of the inks, extending their possible use to biomedical applications.

Investigation of High-Level Synthesis tools’ applicability to data acquisition systems design based on the CMS ECAL Data Concentrator Card example

NASA Astrophysics Data System (ADS)

HUSEJKO, Michal; EVANS, John; RASTEIRO DA SILVA, Jose Carlos

2015-12-01

High-Level Synthesis (HLS) for Field-Programmable Logic Array (FPGA) programming is becoming a practical alternative to well-established VHDL and Verilog languages. This paper describes a case study in the use of HLS tools to design FPGA-based data acquisition systems (DAQ). We will present the implementation of the CERN CMS detector ECAL Data Concentrator Card (DCC) functionality in HLS and lessons learned from using HLS design flow. The DCC functionality and a definition of the initial system-level performance requirements (latency, bandwidth, and throughput) will be presented. We will describe how its packet processing control centric algorithm was implemented with VHDL and Verilog languages. We will then show how the HLS flow could speed up design-space exploration by providing loose coupling between functions interface design and functions algorithm implementation. We conclude with results of real-life hardware tests performed with the HLS flow-generated design with a DCC Tester system.

Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

NASA Astrophysics Data System (ADS)

Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

2018-02-01

In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments

DOE PAGES

Brusati, M.; Camplani, A.; Cannon, M.; ...

2017-02-20

SRAM-ba8ed Field Programmable Gate Array (FPGA) logic devices arc very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which ismore » a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. :!\\litigation techniques such as Triple Modular Redundancy (T:t\\IR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).« less

Design and implementation of an optical Gaussian noise generator

NASA Astrophysics Data System (ADS)

Za~O, Leonardo; Loss, Gustavo; Coelho, Rosângela

2009-08-01

A design of a fast and accurate optical Gaussian noise generator is proposed and demonstrated. The noise sample generation is based on the Box-Muller algorithm. The functions implementation was performed on a high-speed Altera Stratix EP1S25 field-programmable gate array (FPGA) development kit. It enabled the generation of 150 million 16-bit noise samples per second. The Gaussian noise generator required only 7.4% of the FPGA logic elements, 1.2% of the RAM memory, 0.04% of the ROM memory, and a laser source. The optical pulses were generated by a laser source externally modulated by the data bit samples using the frequency-shift keying technique. The accuracy of the noise samples was evaluated for different sequences size and confidence intervals. The noise sample pattern was validated by the Bhattacharyya distance (Bd) and the autocorrelation function. The results showed that the proposed design of the optical Gaussian noise generator is very promising to evaluate the performance of optical communications channels with very low bit-error-rate values.

Carbon Nanotube-Based Digital Vacuum Electronics and Miniature Instrumentation for Space Exploration

NASA Technical Reports Server (NTRS)

Manohara, H.; Toda, R.; Lin, R. H.; Liao, A.; Mojarradi, M.

2010-01-01

JPL has developed high performance cold cathodes using arrays of carbon nanotube bundles that produce > 15 A/sq cm at applied fields of 5 to 8 V/micron without any beam focusing. They have exhibited robust operation in poor vacuums of 10(exp -6) to 10(exp -4) Torr- a typically achievable range inside hermetically sealed microcavities. Using these CNT cathodes JPL has developed miniature X-ray tubes capable of delivering sufficient photon flux at acceleration voltages of <20kV to perform definitive mineralogy on planetary surfaces; mass ionizers that offer two orders of magnitude power savings, and S/N ratio better by a factor of five over conventional ionizers. JPL has also developed a new class of programmable logic gates using CNT vacuum electronics potentially for Venus in situ missions and defense applications. These digital vacuum electronic devices are inherently high-temperature tolerant and radiation insensitive. Device design, fabrication and DC switching operation at temperatures up to 700 C are presented in this paper.

A Survey of Memristive Threshold Logic Circuits.

PubMed

Maan, Akshay Kumar; Jayadevi, Deepthi Anirudhan; James, Alex Pappachen

2017-08-01

In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore's law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO 2 , ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.

All-spin logic operations: Memory device and reconfigurable computing

NASA Astrophysics Data System (ADS)

Patra, Moumita; Maiti, Santanu K.

2018-02-01

Exploiting spin degree of freedom of electron a new proposal is given to characterize spin-based logical operations using a quantum interferometer that can be utilized as a programmable spin logic device (PSLD). The ON and OFF states of both inputs and outputs are described by spin state only, circumventing spin-to-charge conversion at every stage as often used in conventional devices with the inclusion of extra hardware that can eventually diminish the efficiency. All possible logic functions can be engineered from a single device without redesigning the circuit which certainly offers the opportunities of designing new generation spintronic devices. Moreover, we also discuss the utilization of the present model as a memory device and suitable computing operations with proposed experimental setups.

Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Darrin, Ann Garrison; Conde, Richard; Chern, Bobbie; Luers, Phil; Jurczyk, Steve; Mills, Carl; Day, John H. (Technical Monitor)

2001-01-01

The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of radiation tolerant RAM-based field programmable gate array (FPGA) technology to develop a reconfigurable processor that combines the flexibility of a general purpose processor running software with the performance of application specific processing hardware for a variety of high performance computing applications.

The IMPACT Common Module - A Low Cost, Reconfigurable Building Block for Next Generation Phased Arrays

DTIC Science & Technology

2016-03-31

The SiGe receiver has two stages of programmable RF filtering and one stage of IF filtering. Each filter can be tuned in center frequency and...distribution unlimited. transmit, with an IF to RF upconversion chain that is split to programmable phase shifters and VGAs at each output port. Figure 2...These are optimized to run on medium grade Field Programmable Gate Arrays (FPGAs), such as the Altera Arria 10, and represent a few of the many

OpenFlow Extensions for Programmable Quantum Networks

DTIC Science & Technology

2017-06-19

Extensions for Programmable Quantum Networks by Venkat Dasari, Nikolai Snow, and Billy Geerhart Computational and Information Sciences Directorate...distribution is unlimited. 1 1. Introduction Quantum networks and quantum computing have been receiving a surge of interest recently.1–3 However, there has...communicate using entangled particles and perform calculations using quantum logic gates. Additionally, quantum computing uses a quantum bit (qubit

Single array of magnetic vortex disks uses in-plane anisotropy to create different logic gates

NASA Astrophysics Data System (ADS)

Vigo-Cotrina, H.; Guimarães, A. P.

2017-11-01

Using micromagnetic simulation, we show that in-plane uniaxial magnetic anisotropy (IPUA) can be used to obtain FAN-OUT, AND and OR gates in an array of coupled disks with magnetic vortex configuration. First, we studied the influence of the direction of application of the IPUA on the energy transfer time (τ) between two identical coupled nanodisks. We found that when the direction of the IPUA is along the x axis the magnetic interaction increases, allowing shorter values of τ , while the IPUA along the y direction has the opposite effect. The magnetic interactions between the nanodisks along x and y directions (the coupling integrals) as a function of the uniaxial anisotropy constant (Kσ) were obtained using a simple dipolar model. Next, we demonstrated that choosing a suitable direction of application of the IPUA, it is possible to create several different logic gates with a single array of coupled nanodisks.

A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

PubMed

Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

2015-08-01

A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

Nonvolatile programmable neural network synaptic array

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1994-01-01

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Failure detection in high-performance clusters and computers using chaotic map computations

DOEpatents

Rao, Nageswara S.

2015-09-01

A programmable media includes a processing unit capable of independent operation in a machine that is capable of executing 10.sup.18 floating point operations per second. The processing unit is in communication with a memory element and an interconnect that couples computing nodes. The programmable media includes a logical unit configured to execute arithmetic functions, comparative functions, and/or logical functions. The processing unit is configured to detect computing component failures, memory element failures and/or interconnect failures by executing programming threads that generate one or more chaotic map trajectories. The central processing unit or graphical processing unit is configured to detect a computing component failure, memory element failure and/or an interconnect failure through an automated comparison of signal trajectories generated by the chaotic maps.

System and method for cognitive processing for data fusion

NASA Technical Reports Server (NTRS)

Duong, Tuan A. (Inventor); Duong, Vu A. (Inventor)

2012-01-01

A system and method for cognitive processing of sensor data. A processor array receiving analog sensor data and having programmable interconnects, multiplication weights, and filters provides for adaptive learning in real-time. A static random access memory contains the programmable data for the processor array and the stored data is modified to provide for adaptive learning.

An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays

ERIC Educational Resources Information Center

Meyer-Base, U.; Vera, A.; Meyer-Base, A.; Pattichis, M. S.; Perry, R. J.

2010-01-01

In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the…

Programmable computing with a single magnetoresistive element

NASA Astrophysics Data System (ADS)

Ney, A.; Pampuch, C.; Koch, R.; Ploog, K. H.

2003-10-01

The development of transistor-based integrated circuits for modern computing is a story of great success. However, the proved concept for enhancing computational power by continuous miniaturization is approaching its fundamental limits. Alternative approaches consider logic elements that are reconfigurable at run-time to overcome the rigid architecture of the present hardware systems. Implementation of parallel algorithms on such `chameleon' processors has the potential to yield a dramatic increase of computational speed, competitive with that of supercomputers. Owing to their functional flexibility, `chameleon' processors can be readily optimized with respect to any computer application. In conventional microprocessors, information must be transferred to a memory to prevent it from getting lost, because electrically processed information is volatile. Therefore the computational performance can be improved if the logic gate is additionally capable of storing the output. Here we describe a simple hardware concept for a programmable logic element that is based on a single magnetic random access memory (MRAM) cell. It combines the inherent advantage of a non-volatile output with flexible functionality which can be selected at run-time to operate as an AND, OR, NAND or NOR gate.

Non-volatile logic gates based on planar Hall effect in magnetic films with two in-plane easy axes.

PubMed

Lee, Sangyeop; Bac, Seul-Ki; Choi, Seonghoon; Lee, Hakjoon; Yoo, Taehee; Lee, Sanghoon; Liu, Xinyu; Dobrowolska, M; Furdyna, Jacek K

2017-04-25

We discuss the use of planar Hall effect (PHE) in a ferromagnetic GaMnAs film with two in-plane easy axes as a means for achieving novel logic functionalities. We show that the switching of magnetization between the easy axes in a GaMnAs film depends strongly on the magnitude of the current flowing through the film due to thermal effects that modify its magnetic anisotropy. Planar Hall resistance in a GaMnAs film with two in-plane easy axes shows well-defined maxima and minima that can serve as two binary logic states. By choosing appropriate magnitudes of the input current for the GaMnAs Hall device, magnetic logic functions can then be achieved. Specifically, non-volatile logic functionalities such as AND, OR, NAND, and NOR gates can be obtained in such a device by selecting appropriate initial conditions. These results, involving a simple PHE device, hold promise for realizing programmable logic elements in magnetic electronics.

Simultaneous G-Quadruplex DNA Logic.

PubMed

Bader, Antoine; Cockroft, Scott L

2018-04-03

A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

46 CFR 62.20-1 - Plans for approval.

Code of Federal Regulations, 2014 CFR

2014-10-01

... console, panel, and enclosure layouts. (3) Schematic or logic diagrams including functional relationships... programmable features. (6) A description of built-in test features and diagnostics. (7) Design Verification and...

Implementation of cascade logic gates and majority logic gate on a simple and universal molecular platform.

PubMed

Gao, Jinting; Liu, Yaqing; Lin, Xiaodong; Deng, Jiankang; Yin, Jinjin; Wang, Shuo

2017-10-25

Wiring a series of simple logic gates to process complex data is significantly important and a large challenge for untraditional molecular computing systems. The programmable property of DNA endows its powerful application in molecular computing. In our investigation, it was found that DNA exhibits excellent peroxidase-like activity in a colorimetric system of TMB/H 2 O 2 /Hemin (TMB, 3,3', 5,5'-Tetramethylbenzidine) in the presence of K + and Cu 2+ , which is significantly inhibited by the addition of an antioxidant. According to the modulated catalytic activity of this DNA-based catalyst, three cascade logic gates including AND-OR-INH (INHIBIT), AND-INH and OR-INH were successfully constructed. Interestingly, by only modulating the concentration of Cu 2+ , a majority logic gate with a single-vote veto function was realized following the same threshold value as that of the cascade logic gates. The strategy is quite straightforward and versatile and provides an instructive method for constructing multiple logic gates on a simple platform to implement complex molecular computing.

Graphene-based aptamer logic gates and their application to multiplex detection.

PubMed

Wang, Li; Zhu, Jinbo; Han, Lei; Jin, Lihua; Zhu, Chengzhou; Wang, Erkang; Dong, Shaojun

2012-08-28

In this work, a GO/aptamer system was constructed to create multiplex logic operations and enable sensing of multiplex targets. 6-Carboxyfluorescein (FAM)-labeled adenosine triphosphate binding aptamer (ABA) and FAM-labeled thrombin binding aptamer (TBA) were first adsorbed onto graphene oxide (GO) to form a GO/aptamer complex, leading to the quenching of the fluorescence of FAM. We demonstrated that the unique GO/aptamer interaction and the specific aptamer-target recognition in the target/GO/aptamer system were programmable and could be utilized to regulate the fluorescence of FAM via OR and INHIBIT logic gates. The fluorescence changed according to different input combinations, and the integration of OR and INHIBIT logic gates provided an interesting approach for logic sensing applications where multiple target molecules were present. High-throughput fluorescence imagings that enabled the simultaneous processing of many samples by using the combinatorial logic gates were realized. The developed logic gates may find applications in further development of DNA circuits and advanced sensors for the identification of multiple targets in complex chemical environments.

Fuzz Testing of Industrial Network Protocols in Programmable Logic Controllers

DTIC Science & Technology

2017-12-01

PLCs) are vital components in these cyber-physical systems. The industrial network protocols used to communicate between nodes in a control network...AB/RA) MicroLogix 1100 PLC through its implementation of EtherNet/IP, Common Industrial Protocol (CIP), and Programmable Controller Communication ...Commands (PCCC) communication protocols. This research also examines whether cross-generational vulnerabilities exist in the more advanced AB/RA

Nonlinear dynamics based digital logic and circuits.

PubMed

Kia, Behnam; Lindner, John F; Ditto, William L

2015-01-01

We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

2000-01-01

The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

SRAM Based Re-programmable FPGA for Space Applications

NASA Technical Reports Server (NTRS)

Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

1999-01-01

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Bayesian Inference for Source Reconstruction: A Real-World Application

DTIC Science & Technology

2014-09-25

deliberately or acci- dentally . Two examples of operational monitoring sensor networks are the deployment of biological sensor arrays by the Department of...remarkable paper, Cox [16] demonstrated that proba- bility theory, when interpreted as logic, is the only calculus that conforms to a consistent theory...of inference. This demonstration provides the firm logical basis for asserting that probability calculus is the unique quantitative theory of

DOE Office of Scientific and Technical Information (OSTI.GOV)

Braiman, Yehuda; Neschke, Brendan; Nair, Niketh S.

Here, we study memory states of a circuit consisting of a small inductively coupled Josephson junction array and introduce basic (write, read, and reset) memory operations logics of the circuit. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics. We calculate stability diagrams of the zero-voltage states and outline memory states of the circuit. We also calculate access times and access energies for basic memory operations.

Feedforward, high density, programmable read only neural network based memory system

NASA Technical Reports Server (NTRS)

Daud, Taher; Moopenn, Alex; Lamb, James; Thakoor, Anil; Khanna, Satish

1988-01-01

Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Current Radiation Issues for Programmable Elements and Devices

NASA Technical Reports Server (NTRS)

Katz, R.; Wang, J. J.; Koga, R.; LaBel, A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.;

Parent education interventions designed to support the transition to parenthood: A realist review.

PubMed

Gilmer, Cyndi; Buchan, Judy L; Letourneau, Nicole; Bennett, Claudine T; Shanker, Stuart G; Fenwick, Anne; Smith-Chant, Brenda

2016-07-01

Public health nurses use parent education programmes to support individuals' transition to parenthood. A wide array of these programmes exists; however, the approach must be accommodated by resources available in a publicly funded system. For example, some new-parent education approaches use 1:1 home visiting (with a nurse or trained lay-home visitor) but the costs of this intensive approach can be prohibitive. Because of this limitation there is an interest in identifying effective and efficient new parent educational approaches that can realistically be provided at a universal level. Unfortunately, there is a lack of high-quality evaluation identifying programmes or educational processes that meet these criteria. To identify potentially effective new-parenting education interventions that could be implemented at a population level during the transition to parenthood period. Realist synthesis. Medline, CINAHL, ERIC, PsycINFO, Sociological Abstracts, grey literature. A realist review method generated a total of 72 papers that were used to inform the results. A three-pronged approach was used incorporating an initial search (6), a database search using applicable keywords and MeSH headings (58), and review of literature identified by advisory group (8 grey literature). An 'implementation chain' was developed to outline the overall logic and process behind parent education interventions and to guide the analysis. Seventy-two papers informed this review: 13 systematic reviews/meta-analyses, 34 intervention studies, 9 opinion papers, 8 programme reviews, and 8 grey literature reports. There was no compelling evidence to suggest that a single educational programme or delivery format was effective at a universal level. Some inherent issues were identified. For example, adult learning principles were overlooked and theories of parent-child interaction were not in evidence. No direct links between universal new-parent education programmes and child development outcomes were established. Programme reach and attrition were key challenges. Programme evaluation criteria were inconsistent, with an over-reliance on parent satisfaction or self-reported intention to change behaviour. There was evidence that effective facilitators helped increase parents' perceived satisfaction with programmes. It is unlikely that a single standardized format or programme will meet all the specific learning needs of parents. Multiple approaches that will allow people to access information or education at a time and in a format that suits them may be of value. The importance of the transition to parenthood and its impact on parent and child wellbeing warrant careful consideration of current programming and careful evaluation of future initiatives. Copyright © 2016 Elsevier Ltd. All rights reserved.

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

A programmable microfluidic static droplet array for droplet generation, transportation, fusion, storage, and retrieval.

PubMed

Jin, Si Hyung; Jeong, Heon-Ho; Lee, Byungjin; Lee, Sung Sik; Lee, Chang-Soo

2015-01-01

We present a programmable microfluidic static droplet array (SDA) device that can perform user-defined multistep combinatorial protocols. It combines the passive storage of aqueous droplets without any external control with integrated microvalves for discrete sample dispensing and dispersion-free unit operation. The addressable picoliter-volume reaction is systematically achieved by consecutively merging programmable sequences of reagent droplets. The SDA device is remarkably reusable and able to perform identical enzyme kinetic experiments at least 30 times via automated cross-contamination-free removal of droplets from individual hydrodynamic traps. Taking all these features together, this programmable and reusable universal SDA device will be a general microfluidic platform that can be reprogrammed for multiple applications.

Integrally regulated solar array demonstration using an Intel 8080 microprocessor

NASA Technical Reports Server (NTRS)

Petrik, E. J.

1977-01-01

A concept for regulating the voltage of a solar array by using a microprocessor to effect discrete voltage changes was demonstrated. Eight shorting switches were employed to regulate a simulated array at set-point voltages between 10,000 and 15,000 volts. The demonstration showed that the microprocessor easily regulated the solar array output voltage independently of whether or not the switched cell groups were binary sized in voltage. In addition, the microprocessor provided logic memory capability to perform additional tasks such as locating and insolating a faulty switch.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Detecting Payload Attacks on Programmable Logic Controllers (PLCs)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Huan

Programmable logic controllers (PLCs) play critical roles in industrial control systems (ICS). Providing hardware peripherals and firmware support for control programs (i.e., a PLC’s “payload”) written in languages such as ladder logic, PLCs directly receive sensor readings and control ICS physical processes. An attacker with access to PLC development software (e.g., by compromising an engineering workstation) can modify the payload program and cause severe physical damages to the ICS. To protect critical ICS infrastructure, we propose to model runtime behaviors of legitimate PLC payload program and use runtime behavior monitoring in PLC firmware to detect payload attacks. By monitoring themore » I/O access patterns, network access patterns, as well as payload program timing characteristics, our proposed firmware-level detection mechanism can detect abnormal runtime behaviors of malicious PLC payload. Using our proof-of-concept implementation, we evaluate the memory and execution time overhead of implementing our proposed method and find that it is feasible to incorporate our method into existing PLC firmware. In addition, our evaluation results show that a wide variety of payload attacks can be effectively detected by our proposed approach. The proposed firmware-level payload attack detection scheme complements existing bumpin- the-wire solutions (e.g., external temporal-logic-based model checkers) in that it can detect payload attacks that violate realtime requirements of ICS operations and does not require any additional apparatus.« less

Efficient processing of two-dimensional arrays with C or C++

USGS Publications Warehouse

Donato, David I.

2017-07-20

Because fast and efficient serial processing of raster-graphic images and other two-dimensional arrays is a requirement in land-change modeling and other applications, the effects of 10 factors on the runtimes for processing two-dimensional arrays with C and C++ are evaluated in a comparative factorial study. This study’s factors include the choice among three C or C++ source-code techniques for array processing; the choice of Microsoft Windows 7 or a Linux operating system; the choice of 4-byte or 8-byte array elements and indexes; and the choice of 32-bit or 64-bit memory addressing. This study demonstrates how programmer choices can reduce runtimes by 75 percent or more, even after compiler optimizations. Ten points of practical advice for faster processing of two-dimensional arrays are offered to C and C++ programmers. Further study and the development of a C and C++ software test suite are recommended.Key words: array processing, C, C++, compiler, computational speed, land-change modeling, raster-graphic image, two-dimensional array, software efficiency

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Video rate morphological processor based on a redundant number representation

NASA Astrophysics Data System (ADS)

Kuczborski, Wojciech; Attikiouzel, Yianni; Crebbin, Gregory A.

1992-03-01

This paper presents a video rate morphological processor for automated visual inspection of printed circuit boards, integrated circuit masks, and other complex objects. Inspection algorithms are based on gray-scale mathematical morphology. Hardware complexity of the known methods of real-time implementation of gray-scale morphology--the umbra transform and the threshold decomposition--has prompted us to propose a novel technique which applied an arithmetic system without carrying propagation. After considering several arithmetic systems, a redundant number representation has been selected for implementation. Two options are analyzed here. The first is a pure signed digit number representation (SDNR) with the base of 4. The second option is a combination of the base-2 SDNR (to represent gray levels of images) and the conventional twos complement code (to represent gray levels of structuring elements). Operation principle of the morphological processor is based on the concept of the digit level systolic array. Individual processing units and small memory elements create a pipeline. The memory elements store current image windows (kernels). All operation primitives of processing units apply a unified direction of digit processing: most significant digit first (MSDF). The implementation technology is based on the field programmable gate arrays by Xilinx. This paper justified the rationality of a new approach to logic design, which is the decomposition of Boolean functions instead of Boolean minimization.

Multisensory architectures for action-oriented perception

NASA Astrophysics Data System (ADS)

Alba, L.; Arena, P.; De Fiore, S.; Listán, J.; Patané, L.; Salem, A.; Scordino, G.; Webb, B.

2007-05-01

In order to solve the navigation problem of a mobile robot in an unstructured environment a versatile sensory system and efficient locomotion control algorithms are necessary. In this paper an innovative sensory system for action-oriented perception applied to a legged robot is presented. An important problem we address is how to utilize a large variety and number of sensors, while having systems that can operate in real time. Our solution is to use sensory systems that incorporate analog and parallel processing, inspired by biological systems, to reduce the required data exchange with the motor control layer. In particular, as concerns the visual system, we use the Eye-RIS v1.1 board made by Anafocus, which is based on a fully parallel mixed-signal array sensor-processor chip. The hearing sensor is inspired by the cricket hearing system and allows efficient localization of a specific sound source with a very simple analog circuit. Our robot utilizes additional sensors for touch, posture, load, distance, and heading, and thus requires customized and parallel processing for concurrent acquisition. Therefore a Field Programmable Gate Array (FPGA) based hardware was used to manage the multi-sensory acquisition and processing. This choice was made because FPGAs permit the implementation of customized digital logic blocks that can operate in parallel allowing the sensors to be driven simultaneously. With this approach the multi-sensory architecture proposed can achieve real time capabilities.

Reflectance confocal microscope for imaging oral tissues in vivo, potentially with line scanning as a low-cost approach for clinical use

NASA Astrophysics Data System (ADS)

Peterson, Gary; Abeytunge, Sanjeewa; Eastman, Zachary; Rajadhyaksha, Milind

2012-02-01

Reflectance confocal microscopy with a line scanning approach potentially offers a smaller, simpler and less expensive approach than traditional methods of point scanning for imaging in living tissues. With one moving mechanical element (galvanometric scanner), a linear array detector and off-the-shelf optics, we designed a compact (102x102x76mm) line scanning confocal reflectance microscope (LSCRM) for imaging human tissues in vivo in a clinical setting. Custom-designed electronics, based on field programmable gate array (FPGA) logic has been developed. With 405 nm illumination and a custom objective lens of numerical aperture 0.5, lateral resolution was measured to be 0.8 um (calculated 0.64 um). The calculated optical sectioning is 3.2 um. Preliminary imaging shows nuclear and cellular detail in human skin and oral epithelium in vivo. Blood flow is also visualized in the deeper connective tissue (lamina propria) in oral mucosa. Since a line is confocal only in one dimension (parallel) but not in the other, the detection is more sensitive to multiply scattered out of focus background noise than in the traditional point scanning configuration. Based on the results of our translational studies thus far, a simpler, smaller and lower-cost approach based on a LSCRM appears to be promising for clinical imaging.

Trigger design for a gamma ray detector of HIRFL-ETF

NASA Astrophysics Data System (ADS)

Du, Zhong-Wei; Su, Hong; Qian, Yi; Kong, Jie

2013-10-01

The Gamma Ray Array Detector (GRAD) is one subsystem of HIRFL-ETF (the External Target Facility (ETF) of the Heavy Ion Research Facility in Lanzhou (HIRFL)). It is capable of measuring the energy of gamma-rays with 1024 CsI scintillators in in-beam nuclear experiments. The GRAD trigger should select the valid events and reject the data from the scintillators which are not hit by the gamma-ray. The GRAD trigger has been developed based on the Field Programmable Gate Array (FPGAs) and PXI interface. It makes prompt trigger decisions to select valid events by processing the hit signals from the 1024 CsI scintillators. According to the physical requirements, the GRAD trigger module supplies 12-bit trigger information for the global trigger system of ETF and supplies a trigger signal for data acquisition (DAQ) system of GRAD. In addition, the GRAD trigger generates trigger data that are packed and transmitted to the host computer via PXI bus to be saved for off-line analysis. The trigger processing is implemented in the front-end electronics of GRAD and one FPGA of the GRAD trigger module. The logic of PXI transmission and reconfiguration is implemented in another FPGA of the GRAD trigger module. During the gamma-ray experiments, the GRAD trigger performs reliably and efficiently. The function of GRAD trigger is capable of satisfying the physical requirements.

Field-programmable beam reconfiguring based on digitally-controlled coding metasurface

NASA Astrophysics Data System (ADS)

Wan, Xiang; Qi, Mei Qing; Chen, Tian Yi; Cui, Tie Jun

2016-02-01

Digital phase shifters have been applied in traditional phased array antennas to realize beam steering. However, the phase shifter deals with the phase of the induced current; hence, it has to be in the path of each element of the antenna array, making the phased array antennas very expensive. Metamaterials and/or metasurfaces enable the direct modulation of electromagnetic waves by designing subwavelength structures, which opens a new way to control the beam scanning. Here, we present a direct digital mechanism to control the scattered electromagnetic waves using coding metasurface, in which each unit cell loads a pin diode to produce binary coding states of “1” and “0”. Through data lines, the instant communications are established between the coding metasurface and the internal memory of field-programmable gate arrays (FPGA). Thus, we realize the digital modulation of electromagnetic waves, from which we present the field-programmable reflective antenna with good measurement performance. The proposed mechanism and functional device have great application potential in new-concept radar and communication systems.

Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth; Kim, Hak

2014-01-01

An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

NASA Astrophysics Data System (ADS)

Hu, Wei; Choi, Yong; Hong, Key Jo; Kang, Jihoon; Jung, Jin Ho; Huh, Youn Suk; Lim, Hyun Keong; Kim, Sang Su; Kim, Byung-Tae; Chung, Yonghyun

2012-02-01

Currently, for most photomultiplier tube (PMT)-based PET systems, constant fraction discriminators (CFD) and time to digital converters (TDC) have been employed to detect gamma ray signal arrival time, whereas anger logic circuits and peak detection analog-to-digital converters (ADCs) have been implemented to acquire position and energy information of detected events. As compared to PMT the Geiger-mode avalanche photodiodes (GAPDs) have a variety of advantages, such as compactness, low bias voltage requirement and MRI compatibility. Furthermore, the individual read-out method using a GAPD array coupled 1:1 with an array scintillator can provide better image uniformity than can be achieved using PMT and anger logic circuits. Recently, a brain PET using 72 GAPD arrays (4×4 array, pixel size: 3 mm×3 mm) coupled 1:1 with LYSO scintillators (4×4 array, pixel size: 3 mm×3 mm×20 mm) has been developed for simultaneous PET/MRI imaging in our laboratory. Eighteen 64:1 position decoder circuits (PDCs) were used to reduce GAPD channel number and three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards were used for data acquisition and processing. In this study, a free-running ADC- and FPGA-based signal processing method was developed for the detection of gamma ray signal arrival time, energy and position information all together for each GAPD channel. For the method developed herein, three DAQ cards continuously acquired 18 channels of pre-amplified analog gamma ray signals and 108-bit digital addresses from 18 PDCs. In the FPGA, the digitized gamma ray pulses and digital addresses were processed to generate data packages containing pulse arrival time, baseline value, energy value and GAPD channel ID. Finally, these data packages were saved to a 128 Mbyte on-board synchronous dynamic random access memory (SDRAM) and then transferred to a host computer for coincidence sorting and image reconstruction. In order to evaluate the functionality of the developed signal processing method, energy and timing resolutions for brain PET were measured via the placement of a 6 μCi 22Na point source at the center of the PET scanner. Furthermore the PET image of the hot rod phantom (rod diameter: from 2.5 mm to 6.5 mm) with activity of 1 mCi was simulated, and then image acquisition experiment was performed using the brain PET. Measured average energy resolution for 1152 GAPD channels and system timing resolution were 19.5% (FWHM%) and 2.7 ns (FWHM), respectively. With regard to the acquisition of the hot rod phantom image, rods could be resolved down to a diameter of 2.5 mm, which was similar to simulated results. The experimental results demonstrated that the signal processing method developed herein was successfully implemented for brain PET. This reduced the complexity, cost and developing duration for PET system relative to normal PET electronics, and it will obviously be useful for the development of high-performance investigational PET systems.

Memory device for two-dimensional radiant energy array computers

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1977-01-01

A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also included

Nanopore Logic Operation with DNA to RNA Transcription in a Droplet System.

PubMed

Ohara, Masayuki; Takinoue, Masahiro; Kawano, Ryuji

2017-07-21

This paper describes an AND logic operation with amplification and transcription from DNA to RNA, using T7 RNA polymerase. All four operations, (0 0) to (1 1), with an enzyme reaction can be performed simultaneously, using four-droplet devices that are directly connected to a patch-clamp amplifier. The output RNA molecule is detected using a biological nanopore with single-molecule translocation. Channel current recordings can be obtained using the enzyme solution. The integration of DNA logic gates into electrochemical devices is necessary to obtain output information in a human-recognizable form. Our method will be useful for rapid and confined DNA computing applications, including the development of programmable diagnostic devices.

Mechanical logic switches based on DNA-inspired acoustic metamaterials with ultrabroad low-frequency band gaps

NASA Astrophysics Data System (ADS)

Zheng, Bowen; Xu, Jun

2017-11-01

Mechanical information processing and control has attracted great attention in recent years. A challenging pursuit is to achieve broad functioning frequency ranges, especially at low-frequency domain. Here, we propose a design of mechanical logic switches based on DNA-inspired chiral acoustic metamaterials, which are capable of having ultrabroad band gaps at low-frequency domain. Logic operations can be easily performed by applying constraints at different locations and the functioning frequency ranges are able to be low, broad and tunable. This work may have an impact on the development of mechanical information processing, programmable materials, stress wave manipulation, as well as the isolation of noise and harmful vibration.

Adiabatic quantum-flux-parametron cell library adopting minimalist design

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takeuchi, Naoki, E-mail: takeuchi-naoki-kx@ynu.jp; Yamanashi, Yuki; Yoshikawa, Nobuyuki

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells inmore » the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.« less

Adiabatic quantum-flux-parametron cell library adopting minimalist design

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2015-05-01

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells in the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.

Field-Programmable Gate Array Computer in Structural Analysis: An Initial Exploration

NASA Technical Reports Server (NTRS)

Singleterry, Robert C., Jr.; Sobieszczanski-Sobieski, Jaroslaw; Brown, Samuel

2002-01-01

This paper reports on an initial assessment of using a Field-Programmable Gate Array (FPGA) computational device as a new tool for solving structural mechanics problems. A FPGA is an assemblage of binary gates arranged in logical blocks that are interconnected via software in a manner dependent on the algorithm being implemented and can be reprogrammed thousands of times per second. In effect, this creates a computer specialized for the problem that automatically exploits all the potential for parallel computing intrinsic in an algorithm. This inherent parallelism is the most important feature of the FPGA computational environment. It is therefore important that if a problem offers a choice of different solution algorithms, an algorithm of a higher degree of inherent parallelism should be selected. It is found that in structural analysis, an 'analog computer' style of programming, which solves problems by direct simulation of the terms in the governing differential equations, yields a more favorable solution algorithm than current solution methods. This style of programming is facilitated by a 'drag-and-drop' graphic programming language that is supplied with the particular type of FPGA computer reported in this paper. Simple examples in structural dynamics and statics illustrate the solution approach used. The FPGA system also allows linear scalability in computing capability. As the problem grows, the number of FPGA chips can be increased with no loss of computing efficiency due to data flow or algorithmic latency that occurs when a single problem is distributed among many conventional processors that operate in parallel. This initial assessment finds the FPGA hardware and software to be in their infancy in regard to the user conveniences; however, they have enormous potential for shrinking the elapsed time of structural analysis solutions if programmed with algorithms that exhibit inherent parallelism and linear scalability. This potential warrants further development of FPGA-tailored algorithms for structural analysis.

Implementation of digital equality comparator circuit on memristive memory crossbar array using material implication logic

NASA Astrophysics Data System (ADS)

Haron, Adib; Mahdzair, Fazren; Luqman, Anas; Osman, Nazmie; Junid, Syed Abdul Mutalib Al

2018-03-01

One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.

Programmable single-cell mammalian biocomputers.

PubMed

Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

2012-07-05

Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

Optically programmable encoder based on light propagation in two-dimensional regular nanoplates.

PubMed

Li, Ya; Zhao, Fangyin; Guo, Shuai; Zhang, Yongyou; Niu, Chunhui; Zeng, Ruosheng; Zou, Bingsuo; Zhang, Wensheng; Ding, Kang; Bukhtiar, Arfan; Liu, Ruibin

2017-04-07

We design an efficient optically controlled microdevice based on CdSe nanoplates. Two-dimensional CdSe nanoplates exhibit lighting patterns around the edges and can be realized as a new type of optically controlled programmable encoder. The light source is used to excite the nanoplates and control the logical position under vertical pumping mode by the objective lens. At each excitation point in the nanoplates, the preferred light-propagation routes are along the normal direction and perpendicular to the edges, which then emit out from the edges to form a localized lighting section. The intensity distribution around the edges of different nanoplates demonstrates that the lighting part with a small scale is much stronger, defined as '1', than the dark section, defined as '0', along the edge. These '0' and '1' are the basic logic elements needed to compose logically functional devices. The observed propagation rules are consistent with theoretical simulations, meaning that the guided-light route in two-dimensional semiconductor nanoplates is regular and predictable. The same situation was also observed in regular CdS nanoplates. Basic theoretical analysis and experiments prove that the guided light and exit position follow rules mainly originating from the shape rather than material itself.

Programmable Potentials: Approximate N-body potentials from coarse-level logic.

PubMed

Thakur, Gunjan S; Mohr, Ryan; Mezić, Igor

2016-09-27

This paper gives a systematic method for constructing an N-body potential, approximating the true potential, that accurately captures meso-scale behavior of the chemical or biological system using pairwise potentials coming from experimental data or ab initio methods. The meso-scale behavior is translated into logic rules for the dynamics. Each pairwise potential has an associated logic function that is constructed using the logic rules, a class of elementary logic functions, and AND, OR, and NOT gates. The effect of each logic function is to turn its associated potential on and off. The N-body potential is constructed as linear combination of the pairwise potentials, where the "coefficients" of the potentials are smoothed versions of the associated logic functions. These potentials allow a potentially low-dimensional description of complex processes while still accurately capturing the relevant physics at the meso-scale. We present the proposed formalism to construct coarse-grained potential models for three examples: an inhibitor molecular system, bond breaking in chemical reactions, and DNA transcription from biology. The method can potentially be used in reverse for design of molecular processes by specifying properties of molecules that can carry them out.

Programmable Potentials: Approximate N-body potentials from coarse-level logic

NASA Astrophysics Data System (ADS)

Thakur, Gunjan S.; Mohr, Ryan; Mezić, Igor

2016-09-01

This paper gives a systematic method for constructing an N-body potential, approximating the true potential, that accurately captures meso-scale behavior of the chemical or biological system using pairwise potentials coming from experimental data or ab initio methods. The meso-scale behavior is translated into logic rules for the dynamics. Each pairwise potential has an associated logic function that is constructed using the logic rules, a class of elementary logic functions, and AND, OR, and NOT gates. The effect of each logic function is to turn its associated potential on and off. The N-body potential is constructed as linear combination of the pairwise potentials, where the “coefficients” of the potentials are smoothed versions of the associated logic functions. These potentials allow a potentially low-dimensional description of complex processes while still accurately capturing the relevant physics at the meso-scale. We present the proposed formalism to construct coarse-grained potential models for three examples: an inhibitor molecular system, bond breaking in chemical reactions, and DNA transcription from biology. The method can potentially be used in reverse for design of molecular processes by specifying properties of molecules that can carry them out.

Programmable Potentials: Approximate N-body potentials from coarse-level logic

PubMed Central

Thakur, Gunjan S.; Mohr, Ryan; Mezić, Igor

2016-01-01

This paper gives a systematic method for constructing an N-body potential, approximating the true potential, that accurately captures meso-scale behavior of the chemical or biological system using pairwise potentials coming from experimental data or ab initio methods. The meso-scale behavior is translated into logic rules for the dynamics. Each pairwise potential has an associated logic function that is constructed using the logic rules, a class of elementary logic functions, and AND, OR, and NOT gates. The effect of each logic function is to turn its associated potential on and off. The N-body potential is constructed as linear combination of the pairwise potentials, where the “coefficients” of the potentials are smoothed versions of the associated logic functions. These potentials allow a potentially low-dimensional description of complex processes while still accurately capturing the relevant physics at the meso-scale. We present the proposed formalism to construct coarse-grained potential models for three examples: an inhibitor molecular system, bond breaking in chemical reactions, and DNA transcription from biology. The method can potentially be used in reverse for design of molecular processes by specifying properties of molecules that can carry them out. PMID:27671683

Automatic Digital Hardware Synthesis

DTIC Science & Technology

1990-09-01

VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGAI using...process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate...allows the engineer to use VHDL to create and validate a design, and then to implement it in a gate array. The development of software o translate VHDL

Roll Angle Estimation Using Thermopiles for a Flight Controlled Mortar

DTIC Science & Technology

2012-06-01

Using Xilinx’s System generator, the entire design was implemented at a relatively high level within Malab’s Simulink. This allowed VHDL code to...thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA). These results demonstrate the...accurately estimated by processing the thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA

Interlocked DNA nanostructures controlled by a reversible logic circuit.

PubMed

Li, Tao; Lohmann, Finn; Famulok, Michael

2014-09-17

DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems.

Interlocked DNA nanostructures controlled by a reversible logic circuit

PubMed Central

Li, Tao; Lohmann, Finn; Famulok, Michael

2014-01-01

DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

The fabrication of a programmable via using phase-change material in CMOS-compatible technology.

PubMed

Chen, Kuan-Neng; Krusin-Elbaum, Lia

2010-04-02

We demonstrate an energy-efficient programmable via concept using indirectly heated phase-change material. This via structure has maximum phase-change volume to achieve a minimum on resistance for high performance logic applications. Process development and material investigations for this device structure are reported. The device concept is successfully demonstrated in a standard CMOS-compatible technology capable of multiple cycles between on/off states for reconfigurable applications.

Evaluation of automated decisionmaking methodologies and development of an integrated robotic system simulation. Appendix B: ROBSIM programmer's guide

NASA Technical Reports Server (NTRS)

Haley, D. C.; Almand, B. J.; Thomas, M. M.; Krauze, L. D.; Gremban, K. D.; Sanborn, J. C.; Kelly, J. H.; Depkovich, T. M.; Wolfe, W. J.; Nguyen, T.

1986-01-01

The purpose of the Robotic Simulation (ROBSIM) program is to provide a broad range of computer capabilities to assist in the design, verification, simulation, and study of robotic systems. ROBSIM is programmed in FORTRAM 77 and implemented on a VAX 11/750 computer using the VMS operating system. The programmer's guide describes the ROBSIM implementation and program logic flow, and the functions and structures of the different subroutines. With the manual and the in-code documentation, an experienced programmer can incorporate additional routines and modify existing ones to add desired capabilities.

Strategic Control Algorithm Development : Volume 4A. Computer Program Report.

DOT National Transportation Integrated Search

1974-08-01

A description of the strategic algorithm evaluation model is presented, both at the user and programmer levels. The model representation of an airport configuration, environmental considerations, the strategic control algorithm logic, and the airplan...

Strategic Control Algorithm Development : Volume 4B. Computer Program Report (Concluded)

DOT National Transportation Integrated Search

1974-08-01

A description of the strategic algorithm evaluation model is presented, both at the user and programmer levels. The model representation of an airport configuration, environmental considerations, the strategic control algorithm logic, and the airplan...

Improving immunization of programmable logic controllers using weighted median filters.

PubMed

Paredes, José L; Díaz, Dhionel

2005-04-01

This paper addresses the problem of improving immunization of programmable logic controllers (PLC's) to electromagnetic interference with impulsive characteristics. A filtering structure, based on weighted median filters, that does not require additional hardware and can be implemented in legacy PLC's is proposed. The filtering operation is implemented in the binary domain and removes the impulsive noise presented in the discrete input adding thus robustness to PLC's. By modifying the sampling clock structure, two variants of the filter are obtained. Both structures exploit the cyclic nature of the PLC to form an N-sample observation window of the discrete input, hence a status change on it is determined by the filter output taking into account all the N samples avoiding thus that a single impulse affects the PLC functionality. A comparative study, based on a statistical analysis, of the different filters' performances is presented.

Programmable logic controller implementation of an auto-tuned predictive control based on minimal plant information.

PubMed

Valencia-Palomo, G; Rossiter, J A

2011-01-01

This paper makes two key contributions. First, it tackles the issue of the availability of constrained predictive control for low-level control loops. Hence, it describes how the constrained control algorithm is embedded in an industrial programmable logic controller (PLC) using the IEC 61131-3 programming standard. Second, there is a definition and implementation of a novel auto-tuned predictive controller; the key novelty is that the modelling is based on relatively crude but pragmatic plant information. Laboratory experiment tests were carried out in two bench-scale laboratory systems to prove the effectiveness of the combined algorithm and hardware solution. For completeness, the results are compared with a commercial proportional-integral-derivative (PID) controller (also embedded in the PLC) using the most up to date auto-tuning rules. Copyright © 2010 ISA. Published by Elsevier Ltd. All rights reserved.

Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

NASA Astrophysics Data System (ADS)

Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

2015-02-01

A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer，a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

The need for theory evaluation in global citizenship programmes: The case of the GCSA programme.

PubMed

Goodier, Sarah; Field, Carren; Goodman, Suki

2018-02-01

Many education programmes lack a documented programme theory. This is a problem for programme planners and evaluators as the ability to measure programme success is grounded in the plausibility of the programme's underlying causal logic. Where the programme theory has not been documented, conducting a theory evaluation offers a foundational evaluation step as it gives an indication of whether the theory behind a programme is sound. This paper presents a case of a theory evaluation of a Global Citizenship programme at a top-ranking university in South Africa, subsequently called the GCSA Programme. This evaluation highlights the need for documented programme theory in global citizenship-type programmes for future programme development. An articulated programme theory produced for the GCSA Programme, analysed against the available social science literature, indicated it is comparable to other such programmes in terms of its overarching framework. What the research found is that most other global citizenship programmes do not have an articulated programme theory. These programmes also do not explicitly link their specific activities to their intended outcomes, making demonstrating impact impossible. In conclusion, we argue that taking a theory-based approach can strengthen and enable outcome evaluations in global citizenship programmes. Copyright © 2017. Published by Elsevier Ltd.

Fabrication of heterogeneous nanomaterial array by programmable heating and chemical supply within microfluidic platform towards multiplexed gas sensing application

PubMed Central

Yang, Daejong; Kang, Kyungnam; Kim, Donghwan; Li, Zhiyong; Park, Inkyu

2015-01-01

A facile top-down/bottom-up hybrid nanofabrication process based on programmable temperature control and parallel chemical supply within microfluidic platform has been developed for the all liquid-phase synthesis of heterogeneous nanomaterial arrays. The synthesized materials and locations can be controlled by local heating with integrated microheaters and guided liquid chemical flow within microfluidic platform. As proofs-of-concept, we have demonstrated the synthesis of two types of nanomaterial arrays: (i) parallel array of TiO2 nanotubes, CuO nanospikes and ZnO nanowires, and (ii) parallel array of ZnO nanowire/CuO nanospike hybrid nanostructures, CuO nanospikes and ZnO nanowires. The laminar flow with negligible ionic diffusion between different precursor solutions as well as localized heating was verified by numerical calculation and experimental result of nanomaterial array synthesis. The devices made of heterogeneous nanomaterial array were utilized as a multiplexed sensor for toxic gases such as NO2 and CO. This method would be very useful for the facile fabrication of functional nanodevices based on highly integrated arrays of heterogeneous nanomaterials. PMID:25634814

The evolvability of programmable hardware.

PubMed

Raman, Karthik; Wagner, Andreas

2011-02-06

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected 'neutral networks' in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10(45) logic circuits ('genotypes') and 10(19) logic functions ('phenotypes'). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.

The evolvability of programmable hardware

PubMed Central

Raman, Karthik; Wagner, Andreas

2011-01-01

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 1045 logic circuits (‘genotypes’) and 1019 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry. PMID:20534598

Ferritin-Templated Quantum-Dots for Quantum Logic Gates

NASA Technical Reports Server (NTRS)

Choi, Sang H.; Kim, Jae-Woo; Chu, Sang-Hyon; Park, Yeonjoon; King, Glen C.; Lillehei, Peter T.; Kim, Seon-Jeong; Elliott, James R.

2005-01-01

Quantum logic gates (QLGs) or other logic systems are based on quantum-dots (QD) with a stringent requirement of size uniformity. The QD are widely known building units for QLGs. The size control of QD is a critical issue in quantum-dot fabrication. The work presented here offers a new method to develop quantum-dots using a bio-template, called ferritin, that ensures QD production in uniform size of nano-scale proportion. The bio-template for uniform yield of QD is based on a ferritin protein that allows reconstitution of core material through the reduction and chelation processes. One of the biggest challenges for developing QLG is the requirement of ordered and uniform size of QD for arrays on a substrate with nanometer precision. The QD development by bio-template includes the electrochemical/chemical reconsitution of ferritins with different core materials, such as iron, cobalt, manganese, platinum, and nickel. The other bio-template method used in our laboratory is dendrimers, precisely defined chemical structures. With ferritin-templated QD, we fabricated the heptagonshaped patterned array via direct nano manipulation of the ferritin molecules with a tip of atomic force microscope (AFM). We also designed various nanofabrication methods of QD arrays using a wide range manipulation techniques. The precise control of the ferritin-templated QD for a patterned arrangement are offered by various methods, such as a site-specific immobilization of thiolated ferritins through local oxidation using the AFM tip, ferritin arrays induced by gold nanoparticle manipulation, thiolated ferritin positioning by shaving method, etc. In the signal measurements, the current-voltage curve is obtained by measuring the current through the ferritin, between the tip and the substrate for potential sweeping or at constant potential. The measured resistance near zero bias was 1.8 teraohm for single holoferritin and 5.7 teraohm for single apoferritin, respectively.

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

2017-01-01

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.; Carmichael, C.; Tseng, C.

2007-01-01

We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.

Digitally programmable signal generator and method

DOEpatents

Priatko, G.J.; Kaskey, J.A.

1989-11-14

Disclosed is a digitally programmable waveform generator for generating completely arbitrary digital or analog waveforms from very low frequencies to frequencies in the gigasample per second range. A memory array with multiple parallel outputs is addressed; then the parallel output data is latched into buffer storage from which it is serially multiplexed out at a data rate many times faster than the access time of the memory array itself. While data is being multiplexed out serially, the memory array is accessed with the next required address and presents its data to the buffer storage before the serial multiplexing of the last group of data is completed, allowing this new data to then be latched into the buffer storage for smooth continuous serial data output. In a preferred implementation, a plurality of these serial data outputs are paralleled to form the input to a digital to analog converter, providing a programmable analog output. 6 figs.

Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Zebulum, Ricardo; Rajeshuni, Ramesham; Stoica, Adrian; Katkoori, Srinivas; Graves, Sharon; Novak, Frank; Antill, Charles

2006-01-01

In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.

Digitally programmable signal generator and method

DOEpatents

Priatko, Gordon J.; Kaskey, Jeffrey A.

1989-01-01

A digitally programmable waveform generator for generating completely arbitrary digital or analog waveforms from very low frequencies to frequencies in the gigasample per second range. A memory array with multiple parallel outputs is addressed; then the parallel output data is latched into buffer storage from which it is serially multiplexed out at a data rate many times faster than the access time of the memory array itself. While data is being multiplexed out serially, the memory array is accessed with the next required address and presents its data to the buffer storage before the serial multiplexing of the last group of data is completed, allowing this new data to then be latched into the buffer storage for smooth continuous serial data output. In a preferred implementation, a plurality of these serial data outputs are paralleled to form the input to a digital to analog converter, providing a programmable analog output.

MIRIADS: miniature infrared imaging applications development system description and operation

NASA Astrophysics Data System (ADS)

Baxter, Christopher R.; Massie, Mark A.; McCarley, Paul L.; Couture, Michael E.

2001-10-01

A cooperative effort between the U.S. Air Force Research Laboratory, Nova Research, Inc., the Raytheon Infrared Operations (RIO) and Optics 1, Inc. has successfully produced a miniature infrared camera system that offers significant real-time signal and image processing capabilities by virtue of its modular design. This paper will present an operational overview of the system as well as results from initial testing of the 'Modular Infrared Imaging Applications Development System' (MIRIADS) configured as a missile early-warning detection system. The MIRIADS device can operate virtually any infrared focal plane array (FPA) that currently exists. Programmable on-board logic applies user-defined processing functions to the real-time digital image data for a variety of functions. Daughterboards may be plugged onto the system to expand the digital and analog processing capabilities of the system. A unique full hemispherical infrared fisheye optical system designed and produced by Optics 1, Inc. is utilized by the MIRIADS in a missile warning application to demonstrate the flexibility of the overall system to be applied to a variety of current and future AFRL missions.

Implementation of a high precision multi-measurement time-to-digital convertor on a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Kuang, Jie; Wang, Yonggang; Cao, Qiang; Liu, Chong

2018-05-01

Time-to-digital convertors (TDCs) based on field programmable gate array (FPGA) are becoming more and more popular. Multi-measurement is an effective method to improve TDC precision beyond the cell delay limitation. However, the implementation of TDC with multi-measurement on FPGAs manufactured with 28 nm and more advanced process is facing new challenges. Benefiting from the ones-counter encoding scheme, which was developed in our previous work, we implement a ring oscillator multi-measurement TDC on a Xilinx Kintex-7 FPGA. Using the two TDC channels to measure time-intervals in the range (0 ns-30 ns), the average RMS precision can be improved to 5.76 ps, meanwhile the logic resource usage remains the same with the one-measurement TDC, and the TDC dead time is only 22 ns. The investigation demonstrates that the multi-measurement methods are still available for current main-stream FPGAs. Furthermore, the new implementation in this paper could make the trade-off among the time precision, resource usage and TDC dead time better than ever before.

A Component-Based FPGA Design Framework for Neuronal Ion Channel Dynamics Simulations

PubMed Central

Mak, Terrence S. T.; Rachmuth, Guy; Lam, Kai-Pui; Poon, Chi-Sang

2008-01-01

Neuron-machine interfaces such as dynamic clamp and brain-implantable neuroprosthetic devices require real-time simulations of neuronal ion channel dynamics. Field Programmable Gate Array (FPGA) has emerged as a high-speed digital platform ideal for such application-specific computations. We propose an efficient and flexible component-based FPGA design framework for neuronal ion channel dynamics simulations, which overcomes certain limitations of the recently proposed memory-based approach. A parallel processing strategy is used to minimize computational delay, and a hardware-efficient factoring approach for calculating exponential and division functions in neuronal ion channel models is used to conserve resource consumption. Performances of the various FPGA design approaches are compared theoretically and experimentally in corresponding implementations of the AMPA and NMDA synaptic ion channel models. Our results suggest that the component-based design framework provides a more memory economic solution as well as more efficient logic utilization for large word lengths, whereas the memory-based approach may be suitable for time-critical applications where a higher throughput rate is desired. PMID:17190033

Environmental Effects on Data Retention in Flash Cells

NASA Technical Reports Server (NTRS)

Katz, Rich; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.

An Asynchronous Recurrent Network of Cellular Automaton-Based Neurons and Its Reproduction of Spiking Neural Network Activities.

PubMed

Matsubara, Takashi; Torikai, Hiroyuki

2016-04-01

Modeling and implementation approaches for the reproduction of input-output relationships in biological nervous tissues contribute to the development of engineering and clinical applications. However, because of high nonlinearity, the traditional modeling and implementation approaches encounter difficulties in terms of generalization ability (i.e., performance when reproducing an unknown data set) and computational resources (i.e., computation time and circuit elements). To overcome these difficulties, asynchronous cellular automaton-based neuron (ACAN) models, which are described as special kinds of cellular automata that can be implemented as small asynchronous sequential logic circuits have been proposed. This paper presents a novel type of such ACAN and a theoretical analysis of its excitability. This paper also presents a novel network of such neurons, which can mimic input-output relationships of biological and nonlinear ordinary differential equation model neural networks. Numerical analyses confirm that the presented network has a higher generalization ability than other major modeling and implementation approaches. In addition, Field-Programmable Gate Array-implementations confirm that the presented network requires lower computational resources.

Magnetoelectric domain wall dynamics and its implications for magnetoelectric memory

DOE PAGES

Belashchenko, K. D.; Tchernyshyov, O.; Kovalev, Alexey A.; ...

2016-03-30

Domain wall dynamics in a magnetoelectric antiferromagnet is analyzed, and its implications for magnetoelectric memory applications are discussed. Cr 2O 3 is used in the estimates of the materials parameters. It is found that the domain wall mobility has a maximum as a function of the electric field due to the gyrotropic coupling induced by it. In Cr 2O 3, the maximal mobility of 0.1 m/(s Oe) is reached at E≈0.06 V/nm. Fields of this order may be too weak to overcome the intrinsic depinning field, which is estimated for B-doped Cr 2O 3. These major drawbacks for device implementationmore » can be overcome by applying a small in-plane shear strain, which blocks the domain wall precession. Domain wall mobility of about 0.7 m/(s Oe) can then be achieved at E = 0.2 V/nm. Furthermore, a split-gate scheme is proposed for the domain-wall controlled bit element; its extension to multiple-gate linear arrays can offer advantages in memory density, programmability, and logic functionality.« less

A high-resolution and intelligent dead pixel detection scheme for an electrowetting display screen

NASA Astrophysics Data System (ADS)

Luo, ZhiJie; Luo, JianKun; Zhao, WenWen; Cao, Yang; Lin, WeiJie; Zhou, GuoFu

2018-02-01

Electrowetting display technology is realized by tuning the surface energy of a hydrophobic surface by applying a voltage based on electrowetting mechanism. With the rapid development of the electrowetting industry, how to analyze efficiently the quality of an electrowetting display screen has a very important significance. There are two kinds of dead pixels on the electrowetting display screen. One is that the oil of pixel cannot completely cover the display area. The other is that indium tin oxide semiconductor wire connecting pixel and foil was burned. In this paper, we propose a high-resolution and intelligent dead pixel detection scheme for an electrowetting display screen. First, we built an aperture ratio-capacitance model based on the electrical characteristics of electrowetting display. A field-programmable gate array is used as the integrated logic hub of the system for a highly reliable and efficient control of the circuit. Dead pixels can be detected and displayed on a PC-based 2D graphical interface in real time. The proposed dead pixel detection scheme reported in this work has promise in automating electrowetting display experiments.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Binary information propagation in circular magnetic nanodot arrays using strain induced magnetic anisotropy

NASA Astrophysics Data System (ADS)

Salehi-Fashami, M.; Al-Rashid, M.; Sun, Wei-Yang; Nordeen, P.; Bandyopadhyay, S.; Chavez, A. C.; Carman, G. P.; Atulasimha, J.

2016-10-01

Nanomagnetic logic has emerged as a potential replacement for traditional Complementary Metal Oxide Semiconductor (CMOS) based logic because of superior energy-efficiency (Salahuddin and Datta 2007 Appl. Phys. Lett. 90 093503, Cowburn and Welland 2000 Science 287 1466-68). One implementation of nanomagnetic logic employs shape-anisotropic (e.g. elliptical) ferromagnets (with two stable magnetization orientations) as binary switches that rely on dipole-dipole interaction to communicate binary information (Cowburn and Welland 2000 Science 287 1466-8, Csaba et al 2002 IEEE Trans. Nanotechnol. 1 209-13, Carlton et al 2008 Nano Lett. 8 4173-8, Atulasimha and Bandyopadhyay 2010 Appl. Phys. Lett. 97 173105, Roy et al 2011 Appl. Phys. Lett. 99 063108, Fashami et al 2011 Nanotechnology 22 155201, Tiercelin et al 2011 Appl. Phys. Lett. 99 , Alam et al 2010 IEEE Trans. Nanotechnol. 9 348-51 and Bhowmik et al 2013 Nat. Nanotechnol. 9 59-63). Normally, circular nanomagnets are incompatible with this approach since they lack distinct stable in-plane magnetization orientations to encode bits. However, circular magnetoelastic nanomagnets can be made bi-stable with a voltage induced anisotropic strain, which provides two significant advantages for nanomagnetic logic applications. First, the shape-anisotropy energy barrier is eliminated which reduces the amount of energy required to reorient the magnetization. Second, the in-plane size can be reduced (˜20 nm) which was previously not possible due to thermal stability issues. In circular magnetoelastic nanomagnets, a voltage induced strain stabilizes the magnetization even at this size overcoming the thermal stability issue. In this paper, we analytically demonstrate the feasibility of a binary ‘logic wire’ implemented with an array of circular nanomagnets that are clocked with voltage-induced strain applied by an underlying piezoelectric substrate. This leads to an energy-efficient logic paradigm orders of magnitude superior to existing CMOS-based logic that is scalable to dimensions substantially smaller than those for existing nanomagnetic logic approaches. The analytical approach is validated with experimental measurements conducted on dipole coupled Nickel (Ni) nanodots fabricated on a PMN-PT (Lead Magnesium Niobate-Lead Titanate) sample.

78 FR 13747 - Safety Advisory 2013-01; Passing Stop Signals Protecting Movable Bridges

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-28

... 82 freight cars, including 51 hazardous materials tank cars, derailed seven cars while crossing a... bridge to close using the key pad on the locomotive radio. Through the use of a programmable logic...

C-MOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.

1978-01-01

The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.

Bill Calculator V1.0

DOE Office of Scientific and Technical Information (OSTI.GOV)

2002-08-19

Utitlity tariffs vary significantly from utility to utility. Each utility has its own rates and sets of rules by which bills are calculated. The Bill Calculator reconstructs the tariff based on these rules, stored in data tables, and access the appropriate charges for a given energy consumption and demand. The software reconstructs the tariff logic from the rules stored in data tables. Changes are tallied as the logic is reconstructed. This is essentially an accounting program. The main limitation is on the time to search for each tariff element. It is currently on O(N) search. Also, since the Bill calculatormore » first stores all tariffs in an array and then reads the array to reconstruct a specific tariff, the memory limitatins of a particular system would limit the number of tariffs that could be handled. This tool allows a user to calculate a bill from any sampled utility without prior knowledge of the tariff logic or structure. The peculiarities of the tariff logic are stored in data tables and manged by the Bill Calculator software. This version of the software is implemented as a VB module that operates within Microsoft Excel. Input data tables are stored in Excel worksheets. In this version the Bill Calculator functions can be assessed through Excel as user defined worksheet functions. Bill Calculator can calculate approximately 50,000 bills in less than 30 minutes.« less

The Integration of DCS I/O to an Existing PLC

NASA Technical Reports Server (NTRS)

Sadhukhan, Debashis; Mihevic, John

2013-01-01

At the NASA Glenn Research Center (GRC), Existing Programmable Logic Controller (PLC) I/O was replaced with Distributed Control System (DCS) I/O, while keeping the existing PLC sequence Logic. The reason for integration of the PLC logic and DCS I/O, along with the evaluation of the resulting system is the subject of this paper. The pros and cons of the old system and new upgrade are described, including operator workstation screen update times. Detail of the physical layout and the communication between the PLC, the DCS I/O and the operator workstations are illustrated. The complex characteristics of a central process control system and the plan to remove the PLC processors in future upgrades is also discussed.

Programming Cell Adhesion for On-Chip Sequential Boolean Logic Functions.

PubMed

Qu, Xiangmeng; Wang, Shaopeng; Ge, Zhilei; Wang, Jianbang; Yao, Guangbao; Li, Jiang; Zuo, Xiaolei; Shi, Jiye; Song, Shiping; Wang, Lihua; Li, Li; Pei, Hao; Fan, Chunhai

2017-08-02

Programmable remodelling of cell surfaces enables high-precision regulation of cell behavior. In this work, we developed in vitro constructed DNA-based chemical reaction networks (CRNs) to program on-chip cell adhesion. We found that the RGD-functionalized DNA CRNs are entirely noninvasive when interfaced with the fluidic mosaic membrane of living cells. DNA toehold with different lengths could tunably alter the release kinetics of cells, which shows rapid release in minutes with the use of a 6-base toehold. We further demonstrated the realization of Boolean logic functions by using DNA strand displacement reactions, which include multi-input and sequential cell logic gates (AND, OR, XOR, and AND-OR). This study provides a highly generic tool for self-organization of biological systems.

Multilevel Resistance Programming in Conductive Bridge Resistive Memory

NASA Astrophysics Data System (ADS)

Mahalanabis, Debayan

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.

Test Capability Enhancements to the NASA Langley 8-Foot High Temperature Tunnel

NASA Technical Reports Server (NTRS)

Harvin, S. F.; Cabell, K. F.; Gallimore, S. D.; Mekkes, G. L.

2006-01-01

The NASA Langley 8-Foot High Temperature Tunnel produces true enthalpy environments simulating flight from Mach 4 to Mach 7, primarily for airbreathing propulsion and aerothermal/thermo-structural testing. Flow conditions are achieved through a methane-air heater and nozzles producing aerodynamic Mach numbers of 4, 5 or 7 and have exit diameters of 8 feet or 4.5 feet. The 12-ft long free-jet test section, housed inside a 26-ft vacuum sphere, accommodates large test articles. Recently, the facility underwent significant upgrades to support hydrocarbon fueled scramjet engine testing and to expand flight simulation capability. The upgrades were required to meet engine system development and flight clearance verification requirements originally defined by the joint NASA-Air Force X-43C Hypersonic Flight Demonstrator Project and now the Air Force X-51A Program. Enhancements to the 8-Ft. HTT were made in four areas: 1) hydrocarbon fuel delivery; 2) flight simulation capability; 3) controls and communication; and 4) data acquisition/processing. The upgrades include the addition of systems to supply ethylene and liquid JP-7 to test articles; a Mach 5 nozzle with dynamic pressure simulation capability up to 3200 psf, the addition of a real-time model angle-of-attack system; a new programmable logic controller sub-system to improve process controls and communication with model controls; the addition of MIL-STD-1553B and high speed data acquisition systems and a classified data processing environment. These additions represent a significant increase to the already unique test capability and flexibility of the facility, and complement the existing array of test support hardware such as a model injection system, radiant heaters, six-component force measurement system, and optical flow field visualization hardware. The new systems support complex test programs that require sophisticated test sequences and precise management of process fluids. Furthermore, the new systems, such as the real-time angle of attack system and the new programmable logic controller enhance the test efficiency of the facility. The motivation for the upgrades and the expanded capabilities is described here.

Upgrade of Tile Calorimeter of the ATLAS Detector for the High Luminosity LHC.

NASA Astrophysics Data System (ADS)

Valdes Santurio, Eduardo; Tile Calorimeter System, ATLAS

2017-11-01

The Tile Calorimeter (TileCal) is the hadronic calorimeter of ATLAS covering the central region of the ATLAS experiment. TileCal is a sampling calorimeter with steel as absorber and scintillators as active medium. The scintillators are read out by wavelength shifting fibers coupled to photomultiplier tubes (PMT). The analogue signals from the PMTs are amplified, shaped and digitized by sampling the signal every 25 ns. The High Luminosity Large Hadron Collider (HL-LHC) will have a peak luminosity of 5 × 1034 cm -2 s -1, five times higher than the design luminosity of the LHC. TileCal will undergo a major replacement of its on- and off-detector electronics for the high luminosity programme of the LHC in 2026. The calorimeter signals will be digitized and sent directly to the off-detector electronics, where the signals are reconstructed and shipped to the first level of trigger at a rate of 40 MHz. This will provide a better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. Field Programmable Gate Arrays (FPGAs) are extensively used for the logic functions of the off- and on-detector electronics. One hybrid demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, may be inserted in ATLAS at the end of 2016.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Efficient Graph Based Assembly of Short-Read Sequences on Hybrid Core Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sczyrba, Alex; Pratap, Abhishek; Canon, Shane

2011-03-22

Advanced architectures can deliver dramatically increased throughput for genomics and proteomics applications, reducing time-to-completion in some cases from days to minutes. One such architecture, hybrid-core computing, marries a traditional x86 environment with a reconfigurable coprocessor, based on field programmable gate array (FPGA) technology. In addition to higher throughput, increased performance can fundamentally improve research quality by allowing more accurate, previously impractical approaches. We will discuss the approach used by Convey?s de Bruijn graph constructor for short-read, de-novo assembly. Bioinformatics applications that have random access patterns to large memory spaces, such as graph-based algorithms, experience memory performance limitations on cache-based x86more » servers. Convey?s highly parallel memory subsystem allows application-specific logic to simultaneously access 8192 individual words in memory, significantly increasing effective memory bandwidth over cache-based memory systems. Many algorithms, such as Velvet and other de Bruijn graph based, short-read, de-novo assemblers, can greatly benefit from this type of memory architecture. Furthermore, small data type operations (four nucleotides can be represented in two bits) make more efficient use of logic gates than the data types dictated by conventional programming models.JGI is comparing the performance of Convey?s graph constructor and Velvet on both synthetic and real data. We will present preliminary results on memory usage and run time metrics for various data sets with different sizes, from small microbial and fungal genomes to very large cow rumen metagenome. For genomes with references we will also present assembly quality comparisons between the two assemblers.« less

Single-Event Effect (SEE) Survey of Advanced Reconfigurable Field Programmable Gate Arrays: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

Allen, Gregory

2011-01-01

The NEPP Reconfigurable Field-Programmable Gate Array (FPGA) task has been charged to evaluate reconfigurable FPGA technologies for use in space. Under this task, the Xilinx single-event-immune, reconfigurable FPGA (SIRF) XQR5VFX130 device was evaluated for SEE. Additionally, the Altera Stratix-IV and SiliconBlue iCE65 were screened for single-event latchup (SEL).

Excitonic AND Logic Gates on DNA Brick Nanobreadboards.

PubMed

Cannon, Brittany L; Kellis, Donald L; Davis, Paul H; Lee, Jeunghoon; Kuang, Wan; Hughes, William L; Graugnard, Elton; Yurke, Bernard; Knowlton, William B

2015-03-18

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems.

Excitonic AND Logic Gates on DNA Brick Nanobreadboards

PubMed Central

2015-01-01

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

Instantaneous relationship between solar inertial and local vertical local horizontal attitudes

NASA Technical Reports Server (NTRS)

Vickery, S. A.

1977-01-01

The instantaneous relationship between the Solar Inertial (SI) and Local Vertical Local Horizontal (LVLH) coordinate systems is derived. A method is presented for computation of the LVLH to SI rotational transformation matrix as a function of an input LVLH attitude and the corresponding look angles to the sun. Logic is provided for conversion between LVLH and SI attitudes expressed in terms of a pitch, yaw, roll Euler sequence. Documentation is included for a program which implements the logic on the Hewlett-Packard 97 programmable calculator.

High Contrast Programmable Field Masks for JWST NIRSpec

NASA Technical Reports Server (NTRS)

Kutyrev, Alexander S.

2008-01-01

Microshutter arrays are one of the novel technologies developed for the James Webb Space Telescope (JWST). It will allow Near Infrared Spectrometer (NIRSpec) to acquire spectra of hundreds of objects simultaneously therefore increasing its efficiency tremendously. We have developed these programmable arrays that are based on Micro-Electro Mechanical Structures (MEMS) technology. The arrays are 2D addressable masks that can operate in cryogenic environment of JWST. Since the primary JWST science requires acquisition of spectra of extremely faint objects, it is important to provide very high contrast of the open to closed shutters. This high contrast is necessary to eliminate any possible contamination and confusion in the acquired spectra by unwanted objects. We have developed and built a test system for the microshutter array functional and optical characterization. This system is capable of measuring the contrast of the microshutter array both in visible and infrared light of the NIRSpec wavelength range while the arrays are in their working cryogenic environment. We have measured contrast ratio of several microshutter arrays and demonstrated that they satisfy and in many cases far exceed the NIRSpec contrast requirement value of 2000.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

PubMed

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Information Retrieval Research and ESPRIT.

ERIC Educational Resources Information Center

Smeaton, Alan F.

1987-01-01

Describes the European Strategic Programme of Research and Development in Information Technology (ESPRIT), and its five programs: advanced microelectronics, software technology, advanced information processing, office systems, and computer integrated manufacturing. The emphasis on logic programming and ESPRIT as the European response to the…

The World Starts With Me: using intervention mapping for the systematic adaptation and transfer of school-based sexuality education from Uganda to Indonesia.

PubMed

Leerlooijer, Joanne N; Ruiter, Robert A C; Reinders, Jo; Darwisyah, Wati; Kok, Gerjo; Bartholomew, L Kay

2011-06-01

Evidence-based health promotion programmes, including HIV/AIDS prevention and sexuality education programmes, are often transferred to other cultures, priority groups and implementation settings. Challenges in this process include the identification of retaining core elements that relate to the programme's effectiveness while making changes that enhances acceptance in the new context and for the new priority group. This paper describes the use of a systematic approach to programme adaptation using a case study as an example. Intervention Mapping, a protocol for the development of evidence-based behaviour change interventions, was used to adapt the comprehensive school-based sexuality education programme 'The World Starts With Me'. The programme was developed for a priority population in Uganda and adapted to a programme for Indonesian secondary school students. The approach helped to systematically address the complexity and challenges of programme adaptation and to find a balance between preservation of essential programme elements (i.e. logic models) that may be crucial to the programme's effectiveness, including key objectives and theoretical behaviour change methods, and the adaptation of the programme to be acceptable to the new priority group and the programme implementers.

Banning standard cell engineering notebook

NASA Technical Reports Server (NTRS)

1976-01-01

A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The information is presented in a form useful for systems designs, logic design, and the preparation of inputs to both sets of Design Automation programs for array design and analysis. A data sheet is provided for each cell and gives the cell name, the cell number, its logic symbol, Boolean equation, truth table, circuit schematic circuit composite, input-output capacitances, and revision date. The circuit type file, also given for each cell, together with the logic drawing contained on the data sheet provides all the information required to prepare input data files for the Design Automation Systems. A detailed description of the electrical design procedure is included.

Design of a system based on DSP and FPGA for video recording and replaying

NASA Astrophysics Data System (ADS)

Kang, Yan; Wang, Heng

2013-08-01

This paper brings forward a video recording and replaying system with the architecture of Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The system achieved encoding, recording, decoding and replaying of Video Graphics Array (VGA) signals which are displayed on a monitor during airplanes and ships' navigating. In the architecture, the DSP is a main processor which is used for a large amount of complicated calculation during digital signal processing. The FPGA is a coprocessor for preprocessing video signals and implementing logic control in the system. In the hardware design of the system, Peripheral Device Transfer (PDT) function of the External Memory Interface (EMIF) is utilized to implement seamless interface among the DSP, the synchronous dynamic RAM (SDRAM) and the First-In-First-Out (FIFO) in the system. This transfer mode can avoid the bottle-neck of the data transfer and simplify the circuit between the DSP and its peripheral chips. The DSP's EMIF and two level matching chips are used to implement Advanced Technology Attachment (ATA) protocol on physical layer of the interface of an Integrated Drive Electronics (IDE) Hard Disk (HD), which has a high speed in data access and does not rely on a computer. Main functions of the logic on the FPGA are described and the screenshots of the behavioral simulation are provided in this paper. In the design of program on the DSP, Enhanced Direct Memory Access (EDMA) channels are used to transfer data between the FIFO and the SDRAM to exert the CPU's high performance on computing without intervention by the CPU and save its time spending. JPEG2000 is implemented to obtain high fidelity in video recording and replaying. Ways and means of acquiring high performance for code are briefly present. The ability of data processing of the system is desirable. And smoothness of the replayed video is acceptable. By right of its design flexibility and reliable operation, the system based on DSP and FPGA for video recording and replaying has a considerable perspective in analysis after the event, simulated exercitation and so forth.

Stability of Programmable Shunt Valve Settings with Simultaneous Use of the Optune Transducer Array: A Case Report.

PubMed

Chan, Andrew K; Birk, Harjus S; Winkler, Ethan A; Viner, Jennifer A; Taylor, Jennie W; McDermott, Michael W

2016-07-07

The Optune® transducer array (Novocure Ltd., Haifa, Israel) is an FDA-approved noninvasive regional therapy that aims to inhibit the growth of glioblastoma multiforme (GBM) cells via utilization of alternating electric fields. Some patients with GBM may develop hydrocephalus and benefit from subsequent shunt placement, but special attention must be paid to patients in whom programmable valves are utilized, given the potential effect of the magnetic fields on valve settings. We present the first case report illustrating the stability of programmable shunt valve settings in a neurosurgical patient undergoing therapy with the Optune device. In this study, shunt valve settings were stable over a period of five days despite Optune therapy. This is reassuring for patients with GBM who require simultaneous treatment with both the Optune device and a programmable shunt system.

Magnetic-field-controlled reconfigurable semiconductor logic.

PubMed

Joo, Sungjung; Kim, Taeyueb; Shin, Sang Hoon; Lim, Ju Young; Hong, Jinki; Song, Jin Dong; Chang, Joonyeon; Lee, Hyun-Woo; Rhie, Kungwon; Han, Suk Hee; Shin, Kyung-Ho; Johnson, Mark

2013-02-07

Logic devices based on magnetism show promise for increasing computational efficiency while decreasing consumed power. They offer zero quiescent power and yet combine novel functions such as programmable logic operation and non-volatile built-in memory. However, practical efforts to adapt a magnetic device to logic suffer from a low signal-to-noise ratio and other performance attributes that are not adequate for logic gates. Rather than exploiting magnetoresistive effects that result from spin-dependent transport of carriers, we have approached the development of a magnetic logic device in a different way: we use the phenomenon of large magnetoresistance found in non-magnetic semiconductors in high electric fields. Here we report a device showing a strong diode characteristic that is highly sensitive to both the sign and the magnitude of an external magnetic field, offering a reversible change between two different characteristic states by the application of a magnetic field. This feature results from magnetic control of carrier generation and recombination in an InSb p-n bilayer channel. Simple circuits combining such elementary devices are fabricated and tested, and Boolean logic functions including AND, OR, NAND and NOR are performed. They are programmed dynamically by external electric or magnetic signals, demonstrating magnetic-field-controlled semiconductor reconfigurable logic at room temperature. This magnetic technology permits a new kind of spintronic device, characterized as a current switch rather than a voltage switch, and provides a simple and compact platform for non-volatile reconfigurable logic devices.

An autonomous molecular computer for logical control of gene expression.

PubMed

Benenson, Yaakov; Gil, Binyamin; Ben-Dor, Uri; Adar, Rivka; Shapiro, Ehud

2004-05-27

Early biomolecular computer research focused on laboratory-scale, human-operated computers for complex computational problems. Recently, simple molecular-scale autonomous programmable computers were demonstrated allowing both input and output information to be in molecular form. Such computers, using biological molecules as input data and biologically active molecules as outputs, could produce a system for 'logical' control of biological processes. Here we describe an autonomous biomolecular computer that, at least in vitro, logically analyses the levels of messenger RNA species, and in response produces a molecule capable of affecting levels of gene expression. The computer operates at a concentration of close to a trillion computers per microlitre and consists of three programmable modules: a computation module, that is, a stochastic molecular automaton; an input module, by which specific mRNA levels or point mutations regulate software molecule concentrations, and hence automaton transition probabilities; and an output module, capable of controlled release of a short single-stranded DNA molecule. This approach might be applied in vivo to biochemical sensing, genetic engineering and even medical diagnosis and treatment. As a proof of principle we programmed the computer to identify and analyse mRNA of disease-related genes associated with models of small-cell lung cancer and prostate cancer, and to produce a single-stranded DNA molecule modelled after an anticancer drug.

Towards a DNA Nanoprocessor: Reusable Tile-Integrated DNA Circuits.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2016-08-22

Modern electronic microprocessors use semiconductor logic gates organized on a silicon chip to enable efficient inter-gate communication. Here, arrays of communicating DNA logic gates integrated on a single DNA tile were designed and used to process nucleic acid inputs in a reusable format. Our results lay the foundation for the development of a DNA nanoprocessor, a small and biocompatible device capable of performing complex analyses of DNA and RNA inputs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Numerical aerodynamic simulation facility preliminary study, volume 2 and appendices

NASA Technical Reports Server (NTRS)

1977-01-01

Data to support results obtained in technology assessment studies are presented. Objectives, starting points, and future study tasks are outlined. Key design issues discussed in appendices include: data allocation, transposition network design, fault tolerance and trustworthiness, logic design, processing element of existing components, number of processors, the host system, alternate data base memory designs, number representation, fast div 521 instruction, architectures, and lockstep array versus synchronizable array machine comparison.

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory; Edmonds, Larry D.; Swift, Gary; Carmichael, Carl; Tseng, Chen Wei; Heldt, Kevin; Anderson, Scott Arlo; Coe, Michael

2010-01-01

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

Fuzzy logic control of stand-alone photovoltaic system with battery storage

NASA Astrophysics Data System (ADS)

Lalouni, S.; Rekioua, D.; Rekioua, T.; Matagne, E.

Photovoltaic energy has nowadays an increased importance in electrical power applications, since it is considered as an essentially inexhaustible and broadly available energy resource. However, the output power provided via the photovoltaic conversion process depends on solar irradiation and temperature. Therefore, to maximize the efficiency of the photovoltaic energy system, it is necessary to track the maximum power point of the PV array. The present paper proposes a maximum power point tracker (MPPT) method, based on fuzzy logic controller (FLC), applied to a stand-alone photovoltaic system. It uses a sampling measure of the PV array power and voltage then determines an optimal increment required to have the optimal operating voltage which permits maximum power tracking. This method carries high accuracy around the optimum point when compared to the conventional one. The stand-alone photovoltaic system used in this paper includes two bi-directional DC/DC converters and a lead-acid battery bank to overcome the scare periods. One converter works as an MPP tracker, while the other regulates the batteries state of charge and compensates the power deficit to provide a continuous delivery of energy to the load. The Obtained simulation results show the effectiveness of the proposed fuzzy logic controller.

Electromechanical Componentry. High-Technology Training Module.

ERIC Educational Resources Information Center

Lindemann, Don

This training module on electromechanical components contains 10 units for a two-year vocational program packaging system equipment control course at Wisconsin Indianhead Technical College. This module describes the functions of electromechanical devices essential for understanding input/output devices for Programmable Logic Control (PLC)…

Dynamically reconfigurable photovoltaic system

DOEpatents

Okandan, Murat; Nielson, Gregory N.

2016-05-31

A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

Dynamically reconfigurable photovoltaic system

DOEpatents

Okandan, Murat; Nielson, Gregory N.

2016-12-27

A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

Logical enzyme triggered (LET) layer-by-layer nanocapsules for drug delivery system

NASA Astrophysics Data System (ADS)

Kelley, Marie-Michelle

Breast cancer is the second leading cause of morbidity and mortality among women in the United States. Early detection and treatment methods have resulted in 100% 5-year survival rates for stage 0-I breast cancer. Unfortunately, the 5-year survival rate of metastatic breast cancer (stage IV) is reduced fivefold. The most challenging issues of metastatic breast cancer treatment are the ability to selectively target the adenoma and adenocarcinoma cells both in their location of origin and as they metastasize following initial treatment. Multilayer/Layer-by-Layer (LbL) nanocapsules have garnered vast interest as anticancer drug delivery systems due to their ability to be easily modified, their capacity to encapsulate a wide range of chemicals and proteins, and their improved pharmacokinetics. Multilayer nanocapsule formation requires the layering of opposing charged polyelectrolytic polymers over a removable core nanoparticle. Our goal is to have a programmable nanocapsules degrade only after receiving and validating specific breast cancer biomarkers. The overall objective is to fabricate a novel programmable LbL nanocapsule with a specific logical system that will enhance functions pertinent to drug delivery systems. Our central hypothesis is that LbL technology coupled with extracellular matrix (ECM) protein substrates will result in a logical enzyme triggered LbL nanocapsule drug delivery system. This platform represents a novel approach toward a logically regulated nano-encapsulated cancer therapy that can selectively follow and deliver chemotherapeutics to cancer cells. The rationale for this project is to overcome a crucial limitation of existing drug delivery systems where chemotherapeutic can be erroneously delivered to non-carcinogenic cells.

Summary of Proton Test on the Quick Logic QL3025 at Indiana University

NASA Technical Reports Server (NTRS)

Katz, Richard

1998-01-01

This issue of the Programmable Logic Application Notes is a compilation of topics: (1) Proton irradiation tests were performed on the Quick Logic QL3025 at the Indian University Cyclotron facility. The devices, tests, and results are discussed; (2) The functional failure of EEPROM's in heavy ion environment is presented; (3) the Act 1 architecture is summarized; (4) Antifuse hardness and hardness testing is updated; the single even upset (SEU) response of hardwired flip-flops is also presented; (4) Total dose results of the ACT 2 and ACT 3 circuits is presented in a chart; (5) Recent sub-micron devices testing of total dose is presented in a chart along with brief discussion; and (6) a reference to the WWW site for more articles of interest.

A Programmable and Configurable Mixed-Mode FPAA SoC

DTIC Science & Technology

2016-03-17

A Programmable and Configurable Mixed-Mode FPAA SoC Sahil Shah, Sihwan Kim, Farhan Adil, Jennifer Hasler, Suma George, Michelle Collins, Richard...Abstract: The authors present a Floating-Gate based, System-On-Chip large-scale Field- Programmable Analog Array IC that integrates divergent concepts...Floating-Gate, SoC, Command Word Classification This paper presents a Floating-Gate (FG) based, System- On-Chip (SoC) large-scale Field- Programmable

Realworld maximum power point tracking simulation of PV system based on Fuzzy Logic control

NASA Astrophysics Data System (ADS)

Othman, Ahmed M.; El-arini, Mahdi M. M.; Ghitas, Ahmed; Fathy, Ahmed

2012-12-01

In the recent years, the solar energy becomes one of the most important alternative sources of electric energy, so it is important to improve the efficiency and reliability of the photovoltaic (PV) systems. Maximum power point tracking (MPPT) plays an important role in photovoltaic power systems because it maximize the power output from a PV system for a given set of conditions, and therefore maximize their array efficiency. This paper presents a maximum power point tracker (MPPT) using Fuzzy Logic theory for a PV system. The work is focused on the well known Perturb and Observe (P&O) algorithm and is compared to a designed fuzzy logic controller (FLC). The simulation work dealing with MPPT controller; a DC/DC Ćuk converter feeding a load is achieved. The results showed that the proposed Fuzzy Logic MPPT in the PV system is valid.

Fuzzy logic particle tracking velocimetry

NASA Technical Reports Server (NTRS)

Wernet, Mark P.

1993-01-01

Fuzzy logic has proven to be a simple and robust method for process control. Instead of requiring a complex model of the system, a user defined rule base is used to control the process. In this paper the principles of fuzzy logic control are applied to Particle Tracking Velocimetry (PTV). Two frames of digitally recorded, single exposure particle imagery are used as input. The fuzzy processor uses the local particle displacement information to determine the correct particle tracks. Fuzzy PTV is an improvement over traditional PTV techniques which typically require a sequence (greater than 2) of image frames for accurately tracking particles. The fuzzy processor executes in software on a PC without the use of specialized array or fuzzy logic processors. A pair of sample input images with roughly 300 particle images each, results in more than 200 velocity vectors in under 8 seconds of processing time.

Implementation of fuzzy-sliding mode based control of a grid connected photovoltaic system.

PubMed

Menadi, Abdelkrim; Abdeddaim, Sabrina; Ghamri, Ahmed; Betka, Achour

2015-09-01

The present work describes an optimal operation of a small scale photovoltaic system connected to a micro-grid, based on both sliding mode and fuzzy logic control. Real time implementation is done through a dSPACE 1104 single board, controlling a boost chopper on the PV array side and a voltage source inverter (VSI) on the grid side. The sliding mode controller tracks permanently the maximum power of the PV array regardless of atmospheric condition variations, while The fuzzy logic controller (FLC) regulates the DC-link voltage, and ensures via current control of the VSI a quasi-total transit of the extracted PV power to the grid under a unity power factor operation. Simulation results, carried out via Matlab-Simulink package were approved through experiment, showing the effectiveness of the proposed control techniques. Copyright © 2015. Published by Elsevier Ltd.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Palomar, J.; Wyman, R.

This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create anmore » unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out.« less

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Détermination assistée par ordinateur de la structure des molécules organiques

NASA Astrophysics Data System (ADS)

Nuzillard, J.-M.

1998-02-01

Nuclear Magnetic Resonance spectroscopy offers the unique possibility of accessing proximity relationships between atoms by means of chemical shift correlation experiments. Structure determination of small molecules has become thus much simpler. Computer programs can use directly correlation information for structure analysis. The use and operation mechanism of such a program, LSD (Logic for Structure Determination) are presented. The example compound is gibberellic acid, a natural product. La spectroscopie de Résonance Magnétique Nucléaire offre un moyen unique de déterminer des relations de proximité entre atomes par le biais des expériences de corrélation. L'analyse structurale de petites molécules organiques s'en trouve extrêmement facilitée. Des programmes informatiques peuvent utiliser directement les informations de corrélation pour déduire des structures. Le fonctionnement et l'usage d'un tel programme, LSD (Logic for Structure Determination), sont détaillés sur un exemple, l'acide gibberellique.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations.

PubMed

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-27

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

NASA Astrophysics Data System (ADS)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Rebounding droplet-droplet collisions on superhydrophobic surfaces: from the phenomenon to droplet logic.

PubMed

Mertaniemi, Henrikki; Forchheimer, Robert; Ikkala, Olli; Ras, Robin H A

2012-11-08

When water droplets impact each other while traveling on a superhydrophobic surface, we demonstrate that they are able to rebound like billiard balls. We present elementary Boolean logic operations and a flip-flop memory based on these rebounding water droplet collisions. Furthermore, bouncing or coalescence can be easily controlled by process parameters. Thus by the controlled coalescence of reactive droplets, here using the quenching of fluorescent metal nanoclusters as a model reaction, we also demonstrate an elementary operation for programmable chemistry. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Light-driven OR and XOR programmable chemical logic gates.

PubMed

Szaciłowski, Konrad; Macyk, Wojciech; Stochel, Grazyna

2006-04-12

Photoelectrodes made of nanocrystalline titanium dioxide modified with various pentacyanoferrates exhibit unique photoelectrochemical properties; photocurrent direction can be switched from anodic to cathodic and vice versa upon changes in photoelectrode potential and incident light wavelength (PhotoElectrochemical Photocurrent Switching, PEPS effect). At certain potentials, anodic photocurrent generated upon UV irradiation has the same intensity as the cathodic photocurrent generated upon visible irradiation. Under these conditions, simultaneous irradiation with UV and visible light results in compensation of anodic and cathodic photocurrents, and zero net photocurrent is observed. This process can be used for construction of unique light-driven chemical logic gates.

An innovative approach for modeling and simulation of an automated industrial robotic arm operated electro-pneumatically

NASA Astrophysics Data System (ADS)

Popa, L.; Popa, V.

2017-08-01

The article is focused on modeling an automated industrial robotic arm operated electro-pneumatically and to simulate the robotic arm operation. It is used the graphic language FBD (Function Block Diagram) to program the robotic arm on Zelio Logic automation. The innovative modeling and simulation procedures are considered specific problems regarding the development of a new type of technical products in the field of robotics. Thus, were identified new applications of a Programmable Logic Controller (PLC) as a specialized computer performing control functions with a variety of high levels of complexit.

Development of components for an S-band phased array antenna subsystem

NASA Technical Reports Server (NTRS)

1975-01-01

The system requirements, module test data, and S-band phased array subsystem test data are discussed. Of the two approaches to achieving antenna gain (mechanically steered reflector or electronically steered phased array), the phased array approach offers the greatest simplicity and lowest cost (size, weight, power, and dollars) for this medium gain. A competitive system design is described as well as hardware evaluation which will lead to timely availability of this technology for implementing such a system. The objectives of the study were: to fabricate and test six engineering model transmit/receive microelectronics modules; to design, fabricate, and test one dc and logic multilayer manifold; and to integrate and test an S-band phased array antenna subsystem composed of antenna elements, seven T/R modules, RF manifolds and dc manifold.

Radio Frequency Based Programmable Logic Controller Anomaly Detection

DTIC Science & Technology

2013-09-01

include wireless radios, IEEE 802.15 Blue- tooth devices, cellular phones, and IEEE 802.11 WiFi networking devices. While wireless communication...MacKenzie, H. Shamoon Malware and SCADA Security What are the Im- pacts? . Technical Report, Tofino Security, Sep 2012. 61. Mateti,P. Hacking Techniques

Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application

NASA Technical Reports Server (NTRS)

Sheldon, Douglas; Schone, Harald

2005-01-01

This viewgraph document reviews the issue of using Field Programmable Gate Arrays (FPGAs) in Space Application, and the some of the strategies for qualifying the FPGA. Qualification and risk management of such complex systems requires new approaches. The paper presents a matrix approach to qualification has been presented that: - Complements historical specifications - Highlights the importance of device physics as a cornerstone to qualification. - Provides levels of risk management that expressly document trade offs. - Stresses the role of the FPGA vendor as team member in the development of modern spacecraft.

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

NASA Astrophysics Data System (ADS)

Kim, J. B.; Won, E.

2018-03-01

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

OSA Proceedings of the International Topical Meeting on Photonic Switching, Held in Salt Lake City, Utah on 6 - 8 March, 1992. Volume 8

DTIC Science & Technology

1992-05-22

Frobenius Theory : Why Hilberts Metric ?," Mathematics of Operations Research 7 (1982) pp.198-210. 11. H. S. M. Cnxeter, Regular Complex Poly- topes...can be made to perform logic functions by pre-setting the device to a given state. We can, in theory , achieve arbitrary logical functionality by using...then extrapolating on the basis of this theory , is about 2000 two diffracted spots appear in the focal plane of the channels. output lenslet array

Development of multiple user AMTRAN on the Datacraft DC6024

NASA Technical Reports Server (NTRS)

Austin, S. L.

1973-01-01

A multiple user version of AMTRAn was implemented on the Datacraft DC6024 computer is reported. The major portion of the multiple user logic is incorporated in the main program which remains in core during all AMTRAN processes. A detailed flowchart of the main program is provided as documentation of the multiple user capability. Activities are directed toward perfecting its capability, providing new features in response to user needs and requests, providing a two-dimensional array AMTRAN containing multiple user logic, and providing documentation as the tasks progress.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

PubMed

Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Javascript Library for Developing Interactive Micro-Level Animations for Teaching and Learning Algorithms on One-Dimensional Arrays

ERIC Educational Resources Information Center

Végh, Ladislav

2016-01-01

The first data structure that first-year undergraduate students learn during the programming and algorithms courses is the one-dimensional array. For novice programmers, it might be hard to understand different algorithms on arrays (e.g. searching, mirroring, sorting algorithms), because the algorithms dynamically change the values of elements. In…

European Seminar on Neural Computing

DTIC Science & Technology

1988-08-31

elements can be fabricated on a single chip . Two specific oriented language (for example, SMALLTALK or cellular arrays, namely, the programmable systolic... chip POOL) the basic concepts are: objects are viewed as (Fisher, 1983) and the connection machine (Treleaven, active, they may contain state, and...flow computer the availability of 1. Programmable Systolic Chip . Programmable Sys- input operands triggers the execution of the instruction tolic Chips

Programmable DNA switches and their applications.

PubMed

Harroun, Scott G; Prévost-Tremblay, Carl; Lauzon, Dominic; Desrosiers, Arnaud; Wang, Xiaomeng; Pedro, Liliana; Vallée-Bélisle, Alexis

2018-03-08

DNA switches are ideally suited for numerous nanotechnological applications, and increasing efforts are being directed toward their engineering. In this review, we discuss how to engineer these switches starting from the selection of a specific DNA-based recognition element, to its adaptation and optimisation into a switch, with applications ranging from sensing to drug delivery, smart materials, molecular transporters, logic gates and others. We provide many examples showcasing their high programmability and recent advances towards their real life applications. We conclude with a short perspective on this exciting emerging field.

ANOPP programmer's reference manual for the executive System. [aircraft noise prediction program

NASA Technical Reports Server (NTRS)

Gillian, R. E.; Brown, C. G.; Bartlett, R. W.; Baucom, P. H.

1977-01-01

Documentation for the Aircraft Noise Prediction Program as of release level 01/00/00 is presented in a manual designed for programmers having a need for understanding the internal design and logical concepts of the executive system software. Emphasis is placed on providing sufficient information to modify the system for enhancements or error correction. The ANOPP executive system includes software related to operating system interface, executive control, and data base management for the Aircraft Noise Prediction Program. It is written in Fortran IV for use on CDC Cyber series of computers.

Recognizing and engineering digital-like logic gates and switches in gene regulatory networks.

PubMed

Bradley, Robert W; Buck, Martin; Wang, Baojun

2016-10-01

A central aim of synthetic biology is to build organisms that can perform useful activities in response to specified conditions. The digital computing paradigm which has proved so successful in electrical engineering is being mapped to synthetic biological systems to allow them to make such decisions. However, stochastic molecular processes have graded input-output functions, thus, bioengineers must select those with desirable characteristics and refine their transfer functions to build logic gates with digital-like switching behaviour. Recent efforts in genome mining and the development of programmable RNA-based switches, especially CRISPRi, have greatly increased the number of parts available to synthetic biologists. Improvements to the digital characteristics of these parts are required to enable robust predictable design of deeply layered logic circuits. Copyright © 2016 The Author(s). Published by Elsevier Ltd.. All rights reserved.

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Transformations of software design and code may lead to reduced errors

NASA Technical Reports Server (NTRS)

Connelly, E. M.

1983-01-01

The capability of programmers and non-programmers to specify problem solutions by developing example-solutions and also for the programmers by writing computer programs was investigated; each method of specification was accomplished at various levels of problem complexity. The level of difficulty of each problem was reflected by the number of steps needed by the user to develop a solution. Machine processing of the user inputs permitted inferences to be developed about the algorithms required to solve a particular problem. The interactive feedback of processing results led users to a more precise definition of the desired solution. Two participant groups (programmers and bookkeepers/accountants) working with three levels of problem complexity and three levels of processor complexity were used. The experimental task employed required specification of a logic for solution of a Navy task force problem.

On Representative Spaceflight Instrument and Associated Instrument Sensor Web Framework

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Patel, Umeshkumar; Vootukuru, Meg

2007-01-01

Sensor Web-based adaptation and sharing of space flight mission resources, including those of the Space-Ground and Control-User communication segment, could greatly benefit from utilization of heritage Internet Protocols and devices applied for Spaceflight (SpaceIP). This had been successfully demonstrated by a few recent spaceflight experiments. However, while terrestrial applications of Internet protocols are well developed and understood (mostly due to billions of dollars in investments by the military and industry), the spaceflight application of Internet protocols is still in its infancy. Progress in the developments of SpaceIP-enabled instrument components will largely determine the SpaceIP utilization of those investments and acceptance in years to come. Likewise SpaceIP, the development of commercial real-time and instrument colocated computational resources, data compression and storage, can be enabled on-board a spacecraft and, in turn, support a powerful application to Sensor Web-based design of a spaceflight instrument. Sensor Web-enabled reconfiguration and adaptation of structures for hardware resources and information systems will commence application of Field Programmable Arrays (FPGA) and other aerospace programmable logic devices for what this technology was intended. These are a few obvious potential benefits of Sensor Web technologies for spaceflight applications. However, they are still waiting to be explored. This is because there is a need for a new approach to spaceflight instrumentation in order to make these mature sensor web technologies applicable for spaceflight. In this paper we present an approach in developing related and enabling spaceflight instrument-level technologies based on the new concept of a representative spaceflight Instrument Sensor Web (ISW).

Fast BPM data distribution for global orbit feedback using commercial gigabit ethernet technology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hulsart, R.; Cerniglia, P.; Michnoff, R.

2011-03-28

In order to correct beam perturbations in RHIC around 10Hz, a new fast data distribution network was required to deliver BPM position data at rates several orders of magnitude above the capability of the existing system. The urgency of the project limited the amount of custom hardware that could be developed, which dictated the use of as much commercially available equipment as possible. The selected architecture uses a custom hardware interface to the existing RHIC BPM electronics together with commercially available Gigabit Ethernet switches to distribute position data to devices located around the collider ring. Using the minimum Ethernet packetmore » size and a field programmable gate array (FPGA) based state machine logic instead of a software based driver, real-time and deterministic data delivery is possible using Ethernet. The method of adapting this protocol for low latency data delivery, bench testing of Ethernet hardware, and the logic to construct Ethernet packets using FPGA hardware will be discussed. A robust communications system using almost all commercial off-the-shelf equipment was developed in under a year which enabled retrofitting of the existing RHIC BPM system to provide 10 KHz data delivery for a global orbit feedback scheme using 72 BPMs. Total latencies from data acquisition at the BPMs to delivery at the controller modules, including very long transmission distances, were kept under 100 {micro}s, which provide very little phase error in correcting the 10 Hz oscillations. Leveraging off of the speed of Gigabit Ethernet and wide availability of Ethernet products enabled this solution to be fully implemented in a much shorter time and at lower cost than if a similar network was developed using a proprietary method.« less

The Central Logic Board for the KM3NeT detector: Design and production

NASA Astrophysics Data System (ADS)

Musico, P.; KM3NeT Collaboration

2016-07-01

The KM3NeT deep sea neutrino observatory will include a very large number of multi-Photomultiplier (PMT) optical modules (DOM) to detect the Cherenkov light generated by secondary particles produced in neutrino interactions. The Central Logic Board (CLB) has been developed to acquire timing and amplitude information from the PMT signals, implementing time-to-digital conversion (TDC) with time over threshold (TOT) technique. The board is also used to configure all the DOM subsystems, to assist in the DOM position and orientation, calibration and to monitor temperature and humidity in the DOM itself. All the collected data are transmitted to shore using a wide-bandwidth optical network. Moreover, through the optical network, all the DOMs are kept synchronized in time within 1 ns precision using the White Rabbit (WR) Precision Time Protocol (PTP) over an Ethernet connection. A large Field Programmable Gate Array (FPGA) has been adopted to implement all the specifications witht the requested performances. The CLB will be also used in the base container of the detection unit (DU) to set-up and monitor all the requested functionalities: in this scenario a dedicated firmware and software will be deployed on board. The design has been started in early 2013 and several prototypes have been developed. After deep test carried on in different EU laboratories, the final mass production batch of 600 boards has been ordered and built: all the CLB are now ready for integration in the DOMs and base containers. The first two KM3NeT DU will be deployed in summer 2015 and all other units are in advanced stage of integration.

Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Snider, Gregory

2000-03-01

Quantum-dot Cellular Automata (QCA) [1] is a promising architecture which employs quantum dots for digital computation. It is a revolutionary approach that holds the promise of high device density and low power dissipation. A basic QCA cell consists of four quantum dots coupled capacitively and by tunnel barriers. The cell is biased to contain two excess electrons within the four dots, which are forced to opposite "corners" of the four-dot cell by mutual Coulomb repulsion. These two possible polarization states of the cell will represent logic "0" and "1". Properly arranged, arrays of these basic cells can implement Boolean logic functions. Experimental results from functional QCA devices built of nanoscale metal dots defined by tunnel barriers will be presented. The experimental devices to be presented consist of Al islands, which we will call quantum dots, interconnected by tunnel junctions and lithographically defined capacitors. Aluminum/ aluminum-oxide/aluminum tunnel junctions were fabricated using a standard e-beam lithography and shadow evaporation technique. The experiments were performed in a dilution refrigerator at a temperature of 70 mK. The operation of a cell is evaluated by direct measurements of the charge state of dots within a cell as the input voltage is changed. The experimental demonstration of a functioning cell will be presented. A line of three cells demonstrates that there are no metastable switching states in a line of cells. A QCA majority gate will also be presented, which is a programmable AND/OR gate and represents the basic building block of QCA systems. The results of recent experiments will be presented. 1. C.S. Lent, P.D. Tougaw, W. Porod, and G.H. Bernstein, Nanotechnology, 4, 49 (1993).

Development of signal processing system of avalanche photo diode for space observations by Astro-H

NASA Astrophysics Data System (ADS)

Ohno, M.; Goto, K.; Hanabata, Y.; Takahashi, H.; Fukazawa, Y.; Yoshino, M.; Saito, T.; Nakamori, T.; Kataoka, J.; Sasano, M.; Torii, S.; Uchiyama, H.; Nakazawa, K.; Watanabe, S.; Kokubun, M.; Ohta, M.; Sato, T.; Takahashi, T.; Tajima, H.

2013-01-01

Astro-H is the sixth Japanese X-ray space observatory which will be launched in 2014. Two of onboard instruments of Astro-H, Hard X-ray Imager and Soft Gamma-ray Detector are surrounded by many number of large Bismuth Germanate (Bi4Ge3O12; BGO) scintillators. Optimum readout system of scintillation lights from these BGOs are essential to reduce the background signals and achieve high performance for main detectors because most of gamma-rays from out of field-of-view of main detectors or radio-isotopes produced inside them due to activation can be eliminated by anti-coincidence technique using BGO signals. We apply Avalanche Photo Diode (APD) for light sensor of these BGO detectors since their compactness and high quantum efficiency make it easy to design such large number of BGO detector system. For signal processing from APDs, digital filter and other trigger logics on the Field-Programmable Gate Array (FPGA) is used instead of discrete analog circuits due to limitation of circuit implementation area on spacecraft. For efficient observations, we have to achieve as low threshold of anti-coincidence signal as possible by utilizing the digital filtering. In addition, such anti-coincident signals should be sent to the main detector within 5 μs to make it in time to veto the A-D conversion. Considering this requirement and constraint from logic size of FPGA, we adopt two types of filter, 8 delay taps filter with only 2 bit precision coefficient and 16 delay taps filter with 8 bit precision coefficient. The data after former simple filter provides anti-coincidence signal quickly in orbit, and the latter filter is used for detail analysis after the data is down-linked.

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

NASA Astrophysics Data System (ADS)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology. Electronic supplementary information (ESI) available: Additional figures (Table S1, Fig. S1-S5). See DOI: 10.1039/c4nr01676a

Logical optical line terminal technologies towards flexible and highly reliable metro- and access-integrated networks

NASA Astrophysics Data System (ADS)

Okamoto, Satoru; Sato, Takehiro; Yamanaka, Naoaki

2017-01-01

In this paper, flexible and highly reliable metro and access integrated networks with network virtualization and software defined networking technologies will be presented. Logical optical line terminal (L-OLT) technologies and active optical distribution networks (ODNs) are the key to introduce flexibility and high reliability into the metro and access integrated networks. In the Elastic Lambda Aggregation Network (EλAN) project which was started in 2012, a concept of the programmable optical line terminal (P-OLT) has been proposed. A role of the P-OLT is providing multiple network services that have different protocols and quality of service requirements by single OLT box. Accommodated services will be Internet access, mobile front-haul/back-haul, data-center access, and leased line. L-OLTs are configured within the P-OLT box to support the functions required for each network service. Multiple P-OLTs and programmable optical network units (P-ONUs) are connected by the active ODN. Optical access paths which have flexible capacity are set on the ODN to provide network services from L-OLT to logical ONUs (L-ONUs). The L-OLT to L-ONU path on the active ODN provides a logical connection. Therefore, introducing virtualization technologies becomes possible. One example is moving an L-OLT from one P-OLT to another P-OLT like a virtual machine. This movement is called L-OLT migration. The L-OLT migration provides flexible and reliable network functions such as energy saving by aggregating L-OLTs to a limited number of P-OLTs, and network wide optical access path restoration. Other L-OLT virtualization technologies and experimental results will be also discussed in the paper.

Research on NC motion controller based on SOPC technology

NASA Astrophysics Data System (ADS)

Jiang, Tingbiao; Meng, Biao

2006-11-01

With the rapid development of the digitization and informationization, the application of numerical control technology in the manufacturing industry becomes more and more important. However, the conventional numerical control system usually has some shortcomings such as the poor in system openness, character of real-time, cutability and reconfiguration. In order to solve these problems, this paper investigates the development prospect and advantage of the application in numerical control area with system-on-a-Programmable-Chip (SOPC) technology, and puts forward to a research program approach to the NC controller based on SOPC technology. Utilizing the characteristic of SOPC technology, we integrate high density logic device FPGA, memory SRAM, and embedded processor ARM into a single programmable logic device. We also combine the 32-bit RISC processor with high computing capability of the complicated algorithm with the FPGA device with strong motivable reconfiguration logic control ability. With these steps, we can greatly resolve the defect described in above existing numerical control systems. For the concrete implementation method, we use FPGA chip embedded with ARM hard nuclear processor to construct the control core of the motion controller. We also design the peripheral circuit of the controller according to the requirements of actual control functions, transplant real-time operating system into ARM, design the driver of the peripheral assisted chip, develop the application program to control and configuration of FPGA, design IP core of logic algorithm for various NC motion control to configured it into FPGA. The whole control system uses the concept of modular and structured design to develop hardware and software system. Thus the NC motion controller with the advantage of easily tailoring, highly opening, reconfigurable, and expandable can be implemented.

Heuristics for Scientific Experimentation: A Developmental Study.

ERIC Educational Resources Information Center

Klahr, David; And Others

1993-01-01

Studied developmental differences in the search constraint heuristics used in scientific reasoning using 12 undergraduates, 20 community college students, 17 fifth to seventh graders (grade 6), and 15 third graders taught to use a programmable robot. Adults use domain-general skills that go beyond the logic of confirmation and disconfirmation.…

Security Enhancement of Littoral Combat Ship Class Utilizing an Autonomous Mustering and Pier Monitoring System

DTIC Science & Technology

2010-03-01

allows the programmer to use the English language in an expressive manor while still maintaining the logical structure of a programming language ( Pressman ...and Choudhury Tanzeem. 2000. Face Recognition for Smart Environments, IEEE Computer, pp. 50–55. Pressman , Roger. 2010. Software Engineering A

[The improved design of table operating box of digital subtraction angiography device].

PubMed

Qi, Xianying; Zhang, Minghai; Han, Fengtan; Tang, Feng; He, Lemin

2009-12-01

In this paper are analyzed the disadvantages of CGO-3000 digital subtraction angiography table Operating Box. The authors put forward a communication control scheme between single-chip microcomputer(SCM) and programmable logic controller(PLC). The details of hardware and software of communication are given.

Electromechanical Devices and Controllers. Electronics Module 10. Instructor's Guide.

ERIC Educational Resources Information Center

Carter, Ed

This module is the tenth of 10 modules in the competency-based electronics series. Introductory materials include a listing of competencies addressed in the module, a parts/equipment list, and a cross-reference table of instructional materials. Six instructional units cover: electromechanical control devices; programmable logic controllers (PLC);…

The Programmable Calculator in the Classroom.

ERIC Educational Resources Information Center

Stolarz, Theodore J.

The uses of programable calculators in the mathematics classroom are presented. A discussion of the "microelectronics revolution" that has brought programable calculators into our society is also included. Pointed out is that the logical or mental processes used to program the programable calculator are identical to those used to program…

Towards Quantifying Programmable Logic Controller Resilience Against Intentional Exploits

DTIC Science & Technology

2012-03-22

may improve the SCADA system’s resilience against DoS and man-in-the-middle ( MITM ) attacks. DoS attacks may be mitigated by using the redundant...paths available on the network links. MITM attacks may be mitigated by the data integrity checks associated with the middleware. Figure 4 illustrates

Three In-Course Assessment Reforms to Improve Higher Education Learning Outcomes

ERIC Educational Resources Information Center

Sadler, D. Royce

2016-01-01

A current international concern is that, for too large a proportion of graduates, their higher order cognitive and practical capabilities are below acceptable levels. The constituent courses of academic programmes are the most logical sites for developing these capabilities. Contributing to patchy attainment are deficiencies in three particular…

Digital Architecture for a Trace Gas Sensor Platform

NASA Technical Reports Server (NTRS)

Gonzales, Paula; Casias, Miguel; Vakhtin, Andrei; Pilgrim, Jeffrey

2012-01-01

A digital architecture has been implemented for a trace gas sensor platform, as a companion to standard analog control electronics, which accommodates optical absorption whose fractional absorbance equivalent would result in excess error if assumed to be linear. In cases where the absorption (1-transmission) is not equivalent to the fractional absorbance within a few percent error, it is necessary to accommodate the actual measured absorption while reporting the measured concentration of a target analyte with reasonable accuracy. This requires incorporation of programmable intelligence into the sensor platform so that flexible interpretation of the acquired data may be accomplished. Several different digital component architectures were tested and implemented. Commercial off-the-shelf digital electronics including data acquisition cards (DAQs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), and microcontrollers have been used to achieve the desired outcome. The most completely integrated architecture achieved during the project used the CPLD along with a microcontroller. The CPLD provides the initial digital demodulation of the raw sensor signal, and then communicates over a parallel communications interface with a microcontroller. The microcontroller analyzes the digital signal from the CPLD, and applies a non-linear correction obtained through extensive data analysis at the various relevant EVA operating pressures. The microcontroller then presents the quantitatively accurate carbon dioxide partial pressure regardless of optical density. This technique could extend the linear dynamic range of typical absorption spectrometers, particularly those whose low end noise equivalent absorbance is below one-part-in-100,000. In the EVA application, it allows introduction of a path-length-enhancing architecture whose optical interference effects are well understood and quantified without sacrificing the dynamic range that allows quantitative detection at the higher carbon dioxide partial pressures. The digital components are compact and allow reasonably complete integration with separately developed analog control electronics without sacrificing size, mass, or power draw.

Event management for large scale event-driven digital hardware spiking neural networks.

PubMed

Caron, Louis-Charles; D'Haene, Michiel; Mailhot, Frédéric; Schrauwen, Benjamin; Rouat, Jean

2013-09-01

The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65,536 neurons and 513,184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel image is segmented in 200 ms. Copyright © 2013 Elsevier Ltd. All rights reserved.

Logic design and implementation of FPGA for a high frame rate ultrasound imaging system

NASA Astrophysics Data System (ADS)

Liu, Anjun; Wang, Jing; Lu, Jian-Yu

2002-05-01

Recently, a method has been developed for high frame rate medical imaging [Jian-yu Lu, ``2D and 3D high frame rate imaging with limited diffraction beams,'' IEEE Trans. Ultrason. Ferroelectr. Freq. Control 44(4), 839-856 (1997)]. To realize this method, a complicated system [multiple-channel simultaneous data acquisition, large memory in each channel for storing up to 16 seconds of data at 40 MHz and 12-bit resolution, time-variable-gain (TGC) control, Doppler imaging, harmonic imaging, as well as coded transmissions] is designed. Due to the complexity of the system, field programmable gate array (FPGA) (Xilinx Spartn II) is used. In this presentation, the design and implementation of the FPGA for the system will be reported. This includes the synchronous dynamic random access memory (SDRAM) controller and other system controllers, time sharing for auto-refresh of SDRAMs to reduce peak power, transmission and imaging modality selections, ECG data acquisition and synchronization, 160 MHz delay locked loop (DLL) for accurate timing, and data transfer via either a parallel port or a PCI bus for post image processing. [Work supported in part by Grant 5RO1 HL60301 from NIH.

Single phase dynamic CMOS PLA using charge sharing technique

NASA Technical Reports Server (NTRS)

Dhong, Y. B.; Tsang, C. P.

1991-01-01

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Sano, Y.; Horii, Y.; Ikeno, M.; Sasaki, O.; Tomoto, M.; Uchida, T.

2017-12-01

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.

A Timing Synchronizer System for Beam Test Setups Requiring Galvanic Isolation

NASA Astrophysics Data System (ADS)

Meder, Lukas Dominik; Emschermann, David; Frühauf, Jochen; Müller, Walter F. J.; Becker, Jürgen

2017-07-01

In beam test setups detector elements together with a readout composed of frontend electronics (FEE) and usually a layer of field-programmable gate arrays (FPGAs) are being analyzed. The FEE is in this scenario often directly connected to both the detector and the FPGA layer what in many cases requires sharing the ground potentials of these layers. This setup can become problematic if parts of the detector need to be operated at different high-voltage potentials, since all of the FPGA boards need to receive a common clock and timing reference for getting the readout synchronized. Thus, for the context of the compressed baryonic matter experiment a versatile timing synchronizer (TS) system was designed providing galvanically isolated timing distribution links over twisted-pair cables. As an electrical interface the so-called timing data processing board FPGA mezzanine card was created for being mounted onto FPGA-based advanced mezzanine cards for mTCA.4 crates. The FPGA logic of the TS system connects to this card and can be monitored and controlled through IPBus slow-control links. Evaluations show that the system is capable of stably synchronizing the FPGA boards of a beam test setup being integrated into a hierarchical TS network.

Towards Real-time, On-board, Hardware-Supported Sensor and Software Health Management for Unmanned Aerial Systems

NASA Technical Reports Server (NTRS)

Schumann, Johann; Rozier, Kristin Y.; Reinbacher, Thomas; Mengshoel, Ole J.; Mbaya, Timmy; Ippolito, Corey

2013-01-01

Unmanned aerial systems (UASs) can only be deployed if they can effectively complete their missions and respond to failures and uncertain environmental conditions while maintaining safety with respect to other aircraft as well as humans and property on the ground. In this paper, we design a real-time, on-board system health management (SHM) capability to continuously monitor sensors, software, and hardware components for detection and diagnosis of failures and violations of safety or performance rules during the flight of a UAS. Our approach to SHM is three-pronged, providing: (1) real-time monitoring of sensor and/or software signals; (2) signal analysis, preprocessing, and advanced on the- fly temporal and Bayesian probabilistic fault diagnosis; (3) an unobtrusive, lightweight, read-only, low-power realization using Field Programmable Gate Arrays (FPGAs) that avoids overburdening limited computing resources or costly re-certification of flight software due to instrumentation. Our implementation provides a novel approach of combining modular building blocks, integrating responsive runtime monitoring of temporal logic system safety requirements with model-based diagnosis and Bayesian network-based probabilistic analysis. We demonstrate this approach using actual data from the NASA Swift UAS, an experimental all-electric aircraft.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Prospects for Future Synergies Between SKA and AtLAST

NASA Astrophysics Data System (ADS)

Wagg, Jeff

2018-01-01

The Square Kilometre Array will be the next major global radio astronomy observatory. Being built in two phases, the first phase will consist of a low frequency array in Australia and a mid to high frequency array of dishes in the Karoo of South Africa. The design of SKA1 is nearly complete with the expectation that construction should begin within the next two years. A significant fraction of the observing time on both SKA1-MID and SKA1-LOW will likely be devoted to large survey programmes covering a broad range of science objectives. Given the timeline for these SKA1 programmes to be completed, it is anticipated that they could naturally complement future high frequency surveys using AtLAST. I will highlight a few areas where such synergies should exist.

The Design and Development of the SMEX-Lite Power System

NASA Technical Reports Server (NTRS)

Rakow, Glenn P.; Schnurr, Richard G., Jr.; Solly, Michael A.

1998-01-01

This paper describes the design and development of a 250W orbit average electrical power system electronic Power Node and software for use in Low Earth Orbit missions. The mass of the Power Node is 3.6 Kg (8 lb.). The dimensions of the Power Node are 30cm x 26cm x 7.9cm (11 in. x 10.25 in x 3.1 in.) The design was realized using software, Field Programmable Gate Array (FPGA) digital logic and surface mount technology. The design is generic enough to reduce the non-recurring engineering for different mission configurations. The Power Node charges one to five, low cost, 22-cell 4 AH D-cell battery packs independently. The battery charging algorithms are executed in the power software to reduce the mass and size of the power electronic. The Power Node implements a peak-power tracking algorithm using an innovative hardware/software approach. The power software task is hosted on the spacecraft processor. The power software task generates a MIL-STD-1553 command packet to update the Power Node control settings. The settings for the battery voltage and current limits, as well as minimum solar array voltage used to implement peak power tracking are contained in this packet. Several advanced topologies are used in the Power Node. These include synchronous rectification in the bus regulators, average current control in the battery chargers and quasi-resonant converters for the Field Effect Transistor (FET) transistor drive electronics. Lastly, the main bus regulator uses a feed-forward topology with the PWM implemented in an FPGA.

FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harold D. Anderson, John T. Williams

2009-07-01

The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Basedmore » on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results in an abort situation immediately executes a shutdown, with only a tens-of-nanoseconds delay to propagate across the FPGA. This paper discusses the design, installation, and testing of the proposed system upgrade, including failure statistics and modifications to the original design.« less

Introducing a new monitoring manual for home fortification and strengthening capacity to monitor nutrition interventions.

PubMed

Jefferds, Maria Elena D; Flores-Ayala, Rafael

2015-12-01

Lack of monitoring capacity is a key barrier for nutrition interventions and limits programme management, decision making and programme effectiveness in many low-income and middle-income countries. A 2011 global assessment reported lack of monitoring capacity was the top barrier for home fortification interventions, such as micronutrient powders or lipid-based nutrient supplements. A Manual for Developing and Implementing Monitoring Systems for Home Fortification Interventions was recently disseminated. It is comprehensive and describes monitoring concepts and frameworks and includes monitoring tools and worksheets. The monitoring manual describes the steps of developing and implementing a monitoring system for home fortification interventions, including identifying and engaging stakeholders; developing a programme description including logic model and logical framework; refining the purpose of the monitoring system, identifying users and their monitoring needs; describing the design of the monitoring system; developing indicators; describing the core components of a comprehensive monitoring plan; and considering factors related to stage of programme development, sustainability and scale up. A fictional home fortification example is used throughout the monitoring manual to illustrate these steps. The monitoring manual is a useful tool to support the development and implementation of home fortification intervention monitoring systems. In the context of systematic capacity gaps to design, implement and monitor nutrition interventions in many low-income and middle-income countries, the dissemination of new tools, such as monitoring manuals may have limited impact without additional attention to strengthening other individual, organisational and systems levels capacities. Published 2014. This article is a U.S. Government work and is in the public domain in the USA.

Design of a K-Band Transmit Phased Array For Low Earth Orbit Satellite Communications

NASA Technical Reports Server (NTRS)

Watson, Thomas; Miller, Stephen; Kershner, Dennis; Anzic, Godfrey

2000-01-01

The design of a light weight, low cost phased array antenna is presented. Multilayer printed wiring board (PWB) technology is utilized for Radio Frequencies (RF) and DC/Logic manifold distribution. Transmit modules are soldered on one side and patch antenna elements are on the other, allowing the use of automated assembly processes. The 19 GHz antenna has two independently steerable beams, each capable of transferring data at 622 Mbps. A passive, self-contained phase change thermal management system is also presented.

Versatile and Programmable DNA Logic Gates on Universal and Label-Free Homogeneous Electrochemical Platform.

PubMed

Ge, Lei; Wang, Wenxiao; Sun, Ximei; Hou, Ting; Li, Feng

2016-10-04

Herein, a novel universal and label-free homogeneous electrochemical platform is demonstrated, on which a complete set of DNA-based two-input Boolean logic gates (OR, NAND, AND, NOR, INHIBIT, IMPLICATION, XOR, and XNOR) is constructed by simply and rationally deploying the designed DNA polymerization/nicking machines without complicated sequence modulation. Single-stranded DNA is employed as the proof-of-concept target/input to initiate or prevent the DNA polymerization/nicking cyclic reactions on these DNA machines to synthesize numerous intact G-quadruplex sequences or binary G-quadruplex subunits as the output. The generated output strands then self-assemble into G-quadruplexes that render remarkable decrease to the diffusion current response of methylene blue and, thus, provide the amplified homogeneous electrochemical readout signal not only for the logic gate operations but also for the ultrasensitive detection of the target/input. This system represents the first example of homogeneous electrochemical logic operation. Importantly, the proposed homogeneous electrochemical logic gates possess the input/output homogeneity and share a constant output threshold value. Moreover, the modular design of DNA polymerization/nicking machines enables the adaptation of these homogeneous electrochemical logic gates to various input and output sequences. The results of this study demonstrate the versatility and universality of the label-free homogeneous electrochemical platform in the design of biomolecular logic gates and provide a potential platform for the further development of large-scale DNA-based biocomputing circuits and advanced biosensors for multiple molecular targets.

Sequence invariant state machines

NASA Technical Reports Server (NTRS)

Whitaker, S.; Manjunath, S.

1990-01-01

A synthesis method and new VLSI architecture are introduced to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. A design method is proposed that utilizes BTS logic to implement regular and dense circuits. A given state sequence can be programmed with power supply connections or dynamically reallocated if stored in a register. Arbitrary flow table sequences can be modified or programmed to dynamically alter the function of the machine. This allows VLSI controllers to be designed with the programmability of a general purpose processor but with the compact size and performance of dedicated logic.

Sequence-invariant state machines

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R.; Manjunath, Shamanna K.; Maki, Gary K.

1991-01-01

A synthesis method and an MOS VLSI architecture are presented to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. The design method utilizes binary tree structured (BTS) logic to implement regular and dense circuits. The desired state sequence can be hardwired with power supply connections or can be dynamically reallocated if stored in a register. This allows programmable VLSI controllers to be designed with a compact size and performance approaching that of dedicated logic. Results of ICV implementations are reported and an example sequence-invariant state machine is contrasted with implementations based on traditional methods.

Toward active-matrix lab-on-a-chip: programmable electrofluidic control enabled by arrayed oxide thin film transistors.

PubMed

Noh, Joo Hyon; Noh, Jiyong; Kreit, Eric; Heikenfeld, Jason; Rack, Philip D

2012-01-21

Agile micro- and nano-fluidic control is critical to numerous life science and chemical science synthesis as well as kinetic and thermodynamic studies. To this end, we have demonstrated the use of thin film transistor arrays as an active matrix addressing method to control an electrofluidic array. Because the active matrix method minimizes the number of control lines necessary (m + n lines for the m×n element array), the active matrix addressing method integrated with an electrofluidic platform can be a significant breakthrough for complex electrofluidic arrays (increased size or resolution) with enhanced function, agility and programmability. An amorphous indium gallium zinc oxide (a-IGZO) semiconductor active layer is used because of its high mobility of 1-15 cm(2) V(-1) s(-1), low-temperature processing and transparency for potential spectroscopy and imaging. Several electrofluidic functionalities are demonstrated using a simple 2 × 5 electrode array connected to a 2 × 5 IGZO thin film transistor array with the semiconductor channel width of 50 μm and mobility of 6.3 cm(2) V(-1) s(-1). Additionally, using the TFT device characteristics, active matrix addressing schemes are discussed as the geometry of the electrode array can be tailored to act as a storage capacitor element. Finally, requisite material and device parameters are discussed in context with a VGA scale active matrix addressed electrofluidic platform.

TID Effects of High-Z Material Spot Shields on FPGA Using MPTB Data

NASA Technical Reports Server (NTRS)

Hardage, Donna (Technical Monitor); Crain, S. H.; Mazur, J. E.; Looper, M. D.

2003-01-01

An experiment on the Microelectronics and Photonics Test Bed (MPTB) was testing lield programmable gate arrays using spot shields to extend the life of some of the devices being tested. It was expected that the unshielded parts would fail from a total ionizing dose (TID) and yet the opposite occurred. The data show that the devices failing from the TID effects are those with the spot shields attached. This effort is to determine the mechanism by which the environment is interacting with the high-Z material to enhance the TID in these field programmable gate arrays.

Banning PRF programmer's manual. [considering MOS integrated circuits

NASA Technical Reports Server (NTRS)

Kuelthau, R. L.

1970-01-01

This manual describes a modification of the Banning placement routing folding program. The modifications to this program have been made to implement it on a Sigma 5 computer. Flow charts of various levels, beginning with high level functional diagrams and working down to the level of detail deemed necessary to understand the operations of the various sections of the program are included. Along with the flow charts of each subroutine is a narrative description of its functional operation and definitions of its arrays and key variables, and a section to assist the programmer in dimensioning the program's arrays.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array.

PubMed

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Liang, Futian; Jin, Ge

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Kun; Wang, Xu; Li, Feng

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Field programmable gate array-assigned complex-valued computation and its limits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernard-Schwarz, Maria, E-mail: maria.bernardschwarz@ni.com; Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien; Zwick, Wolfgang

We discuss how leveraging Field Programmable Gate Array (FPGA) technology as part of a high performance computing platform reduces latency to meet the demanding real time constraints of a quantum optics simulation. Implementations of complex-valued operations using fixed point numeric on a Virtex-5 FPGA compare favorably to more conventional solutions on a central processing unit. Our investigation explores the performance of multiple fixed point options along with a traditional 64 bits floating point version. With this information, the lowest execution times can be estimated. Relative error is examined to ensure simulation accuracy is maintained.

A control system based on field programmable gate array for papermaking sewage treatment

NASA Astrophysics Data System (ADS)

Zhang, Zi Sheng; Xie, Chang; Qing Xiong, Yan; Liu, Zhi Qiang; Li, Qing

2013-03-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

High throughput reconfigurable data analysis system

NASA Technical Reports Server (NTRS)

Bearman, Greg (Inventor); Pelletier, Michael J. (Inventor); Seshadri, Suresh (Inventor); Pain, Bedabrata (Inventor)

2008-01-01

The present invention relates to a system and method for performing rapid and programmable analysis of data. The present invention relates to a reconfigurable detector comprising at least one array of a plurality of pixels, where each of the plurality of pixels can be selected to receive and read-out an input. The pixel array is divided into at least one pixel group for conducting a common predefined analysis. Each of the pixels has a programmable circuitry programmed with a dynamically configurable user-defined function to modify the input. The present detector also comprises a summing circuit designed to sum the modified input.

Radiation Hardened Electronics for Extreme Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches.

Process development for automated solar cell and module production. Task 4: Automated array assembly

NASA Technical Reports Server (NTRS)

1980-01-01

A process sequence which can be used in conjunction with automated equipment for the mass production of solar cell modules for terrestrial use was developed. The process sequence was then critically analyzed from a technical and economic standpoint to determine the technological readiness of certain process steps for implementation. The steps receiving analysis were: back contact metallization, automated cell array layup/interconnect, and module edge sealing. For automated layup/interconnect, both hard automation and programmable automation (using an industrial robot) were studied. The programmable automation system was then selected for actual hardware development.

[National health resources for highly specialised medicine].

PubMed

Bratlid, Dag; Rasmussen, Knut

2005-11-03

In order to monitor quality and efficiency in the use of health resources for highly specialised medicine, a National Professional Council has since 1990 advised the Norwegian health authorities on the establishing and localisation of such services. A comprehensive review of both the quality, economy and the geographical distribution of patients in each specialised service has been carried out. 33 defined national programmes were centralised to one hospital only and distributed among seven university hospitals. Eight multiregional programmes were centralised to two hospitals only and included four university hospitals. In 2001, a total of 2711 new patients were treated in these programmes. The system seems to have secured a sufficient patient flow to each programme so as to maintain quality. However, a geographically skewed distribution of patients was noted, particularly in some of the national programmes. In a small country like Norway, with 4.5 million inhabitants, a centralised monitoring of highly specialised medicine seems both rational and successful. By the same logic, however, international cooperation should probably be sought for the smallest patient groups.

Logic Gate Operation by DNA Translocation through Biological Nanopores.

PubMed

Yasuga, Hiroki; Kawano, Ryuji; Takinoue, Masahiro; Tsuji, Yutaro; Osaki, Toshihisa; Kamiya, Koki; Miki, Norihisa; Takeuchi, Shoji

2016-01-01

Logical operations using biological molecules, such as DNA computing or programmable diagnosis using DNA, have recently received attention. Challenges remain with respect to the development of such systems, including label-free output detection and the rapidity of operation. Here, we propose integration of biological nanopores with DNA molecules for development of a logical operating system. We configured outputs "1" and "0" as single-stranded DNA (ssDNA) that is or is not translocated through a nanopore; unlabeled DNA was detected electrically. A negative-AND (NAND) operation was successfully conducted within approximately 10 min, which is rapid compared with previous studies using unlabeled DNA. In addition, this operation was executed in a four-droplet network. DNA molecules and associated information were transferred among droplets via biological nanopores. This system would facilitate linking of molecules and electronic interfaces. Thus, it could be applied to molecular robotics, genetic engineering, and even medical diagnosis and treatment.

Hyperbranched Hybridization Chain Reaction for Triggered Signal Amplification and Concatenated Logic Circuits.

PubMed

Bi, Sai; Chen, Min; Jia, Xiaoqiang; Dong, Ying; Wang, Zonghua

2015-07-06

A hyper-branched hybridization chain reaction (HB-HCR) is presented herein, which consists of only six species that can metastably coexist until the introduction of an initiator DNA to trigger a cascade of hybridization events, leading to the self-sustained assembly of hyper-branched and nicked double-stranded DNA structures. The system can readily achieve ultrasensitive detection of target DNA. Moreover, the HB-HCR principle is successfully applied to construct three-input concatenated logic circuits with excellent specificity and extended to design a security-mimicking keypad lock system. Significantly, the HB-HCR-based keypad lock can alarm immediately if the "password" is incorrect. Overall, the proposed HB-HCR with high amplification efficiency is simple, homogeneous, fast, robust, and low-cost, and holds great promise in the development of biosensing, in the programmable assembly of DNA architectures, and in molecular logic operations. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Logical NAND and NOR Operations Using Algorithmic Self-assembly of DNA Molecules

NASA Astrophysics Data System (ADS)

Wang, Yanfeng; Cui, Guangzhao; Zhang, Xuncai; Zheng, Yan

DNA self-assembly is the most advanced and versatile system that has been experimentally demonstrated for programmable construction of patterned systems on the molecular scale. It has been demonstrated that the simple binary arithmetic and logical operations can be computed by the process of self assembly of DNA tiles. Here we report a one-dimensional algorithmic self-assembly of DNA triple-crossover molecules that can be used to execute five steps of a logical NAND and NOR operations on a string of binary bits. To achieve this, abstract tiles were translated into DNA tiles based on triple-crossover motifs. Serving as input for the computation, long single stranded DNA molecules were used to nucleate growth of tiles into algorithmic crystals. Our method shows that engineered DNA self-assembly can be treated as a bottom-up design techniques, and can be capable of designing DNA computer organization and architecture.

Three challenges to the complementarity of the logic and the pragmatics of science.

PubMed

Uebel, Thomas

2015-10-01

The bipartite metatheory thesis attributes to Rudolf Carnap, Philipp Frank and Otto Neurath a conception of the nature of post-metaphysical philosophy of science that sees the purely formal-logical analyses of the logic of science as complemented by empirical inquiries into the psychology, sociology and history of science. Three challenges to this thesis are considered in this paper: that Carnap did not share this conception of the nature of philosophy of science even on a programmatic level, that Carnap's detailed analysis of the language of science is incompatible with one developed by Neurath for the pursuit of empirical studies of science, and, finally, that Neurath himself was confused about the programme of which the bipartite metatheory thesis makes him a representative. I argue that all three challenges can be met and refuted. Copyright © 2015 Elsevier Ltd. All rights reserved.

Logic Gate Operation by DNA Translocation through Biological Nanopores

PubMed Central

Takinoue, Masahiro; Tsuji, Yutaro; Osaki, Toshihisa; Kamiya, Koki; Miki, Norihisa; Takeuchi, Shoji

2016-01-01

Logical operations using biological molecules, such as DNA computing or programmable diagnosis using DNA, have recently received attention. Challenges remain with respect to the development of such systems, including label-free output detection and the rapidity of operation. Here, we propose integration of biological nanopores with DNA molecules for development of a logical operating system. We configured outputs “1” and “0” as single-stranded DNA (ssDNA) that is or is not translocated through a nanopore; unlabeled DNA was detected electrically. A negative-AND (NAND) operation was successfully conducted within approximately 10 min, which is rapid compared with previous studies using unlabeled DNA. In addition, this operation was executed in a four-droplet network. DNA molecules and associated information were transferred among droplets via biological nanopores. This system would facilitate linking of molecules and electronic interfaces. Thus, it could be applied to molecular robotics, genetic engineering, and even medical diagnosis and treatment. PMID:26890568

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nishimura, Takahiro, E-mail: t-nishimura@ist.osaka-u.ac.jp; Fujii, Ryo; Ogura, Yusuke

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on themore » DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.« less

Adaptive array antenna for satellite cellular and direct broadcast communications

NASA Technical Reports Server (NTRS)

Horton, Charles R.; Abend, Kenneth

1993-01-01

Adaptive phased-array antennas provide cost-effective implementation of large, light weight apertures with high directivity and precise beamshape control. Adaptive self-calibration allows for relaxation of all mechanical tolerances across the aperture and electrical component tolerances, providing high performance with a low-cost, lightweight array, even in the presence of large physical distortions. Beam-shape is programmable and adaptable to changes in technical and operational requirements. Adaptive digital beam-forming eliminates uplink contention by allowing a single electronically steerable antenna to service a large number of receivers with beams which adaptively focus on one source while eliminating interference from others. A large, adaptively calibrated and fully programmable aperture can also provide precise beam shape control for power-efficient direct broadcast from space. Advanced adaptive digital beamforming technologies are described for: (1) electronic compensation of aperture distortion, (2) multiple receiver adaptive space-time processing, and (3) downlink beam-shape control. Cost considerations for space-based array applications are also discussed.

A Remote Laboratory Platform for Electrical Drive Control Using Programmable Logic Controllers

ERIC Educational Resources Information Center

Ferrater-Simon, C.; Molas-Balada, L.; Gomis-Bellmunt, O.; Lorenzo-Martinez, N.; Bayo-Puxan, O.; Villafafila-Robles, R.

2009-01-01

Many teaching institutions worldwide are working on distance learning applications. In this field, remote laboratories are enabling intensive use of university facilities, while aiding the work of professors and students. The present paper introduces a platform designed to be used in industrial automation practical work. The platform is…

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation

DTIC Science & Technology

2007-08-01

with a Design Specification de- scribed by Scilab [26], a MATLAB-like software applica- tion, and ends up with HDL code. The Design Specifica- tion...Conf. on Field Programmable Logic and Applications (FPL’05), Tampere, Finland, pp. 118–123, Aug. 2005. [26] Scilab 3.0, INRIA-ENPC, France, http

An evaluation of a micro programmable logic controller for oxygen monitoring and control in tanks of a recirculating aquaculture system

USDA-ARS?s Scientific Manuscript database

Control of dissolved gases, especially oxygen is an essential component of recirculating aquaculture systems. The use of pure oxygen in a recirculating aquaculture system creates supersaturated concentrations of dissolved oxygen and can reduce fish production costs by supporting greater fish and fee...

Bias-free spin-wave phase shifter for magnonic logic

DOE Office of Scientific and Technical Information (OSTI.GOV)

Louis, Steven; Tyberkevych, Vasyl; Slavin, Andrei

2016-06-15

A design of a magnonic phase shifter operating without an external bias magnetic field is proposed. The phase shifter uses a localized collective spin wave mode propagating along a domain wall “waveguide” in a dipolarly-coupled magnetic dot array with a chessboard antiferromagnetic (CAFM) ground state. It is demonstrated numerically that the remagnetization of a single magnetic dot adjacent to the domain wall waveguide introduces a controllable phase shift in the propagating spin wave mode without significant change to the mode amplitude. It is also demonstrated that a logic XOR gate can be realized in the same system.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

PubMed Central

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

Quantum-classical interface based on single flux quantum digital logic

NASA Astrophysics Data System (ADS)

McDermott, R.; Vavilov, M. G.; Plourde, B. L. T.; Wilhelm, F. K.; Liebermann, P. J.; Mukhanov, O. A.; Ohki, T. A.

2018-04-01

We describe an approach to the integrated control and measurement of a large-scale superconducting multiqubit array comprising up to 108 physical qubits using a proximal coprocessor based on the Single Flux Quantum (SFQ) digital logic family. Coherent control is realized by irradiating the qubits directly with classical bitstreams derived from optimal control theory. Qubit measurement is performed by a Josephson photon counter, which provides access to the classical result of projective quantum measurement at the millikelvin stage. We analyze the power budget and physical footprint of the SFQ coprocessor and discuss challenges and opportunities associated with this approach.

Programmable logic controller optical fibre sensor interface module

NASA Astrophysics Data System (ADS)

Allwood, Gary; Wild, Graham; Hinckley, Steven

2011-12-01

Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

A distributed control system for the lower-hybrid current drive system on the Tokamak de Varennes

NASA Astrophysics Data System (ADS)

Bagdoo, J.; Guay, J. M.; Chaudron, G.-A.; Decoste, R.; Demers, Y.; Hubbard, A.

1990-08-01

An rf current drive system with an output power of 1 MW at 3.7 GHz is under development for the Tokamak de Varennes. The control system is based on an Ethernet local-area network of programmable logic controllers as front end, personal computers as consoles, and CAMAC-based DSP processors. The DSP processors ensure the PID control of the phase and rf power of each klystron, and the fast protection of high-power rf hardware, all within a 40 μs loop. Slower control and protection, event sequencing and the run-time database are provided by the programmable logic controllers, which communicate, via the LAN, with the consoles. The latter run a commercial process-control console software. The LAN protocol respects the first four layers of the ISO/OSI 802.3 standard. Synchronization with the tokamak control system is provided by commercially available CAMAC timing modules which trigger shot-related events and reference waveform generators. A detailed description of each subsystem and a performance evaluation of the system will be presented.

Photonic Programmable Tele-Cloning Network.

PubMed

Li, Wei; Chen, Ming-Cheng

2016-06-29

The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling.

Evaluation of automated decisionmaking methodologies and development of an integrated robotic system simulation, appendix B

NASA Technical Reports Server (NTRS)

Haley, D. C.; Almand, B. J.; Thomas, M. M.; Krauze, L. D.; Gremban, K. D.; Sanborn, J. C.; Kelly, J. H.; Depkovich, T. M.

1984-01-01

The purpose of the Robotics Simulation (ROBSIM) program is to provide a broad range of computer capabilities to assist in the design, verification, simulation, and study of robotic systems. ROBSIM is programmed in FORTRAN 77 and implemented on a VAX 11/750 computer using the VMS operating system. This programmer's guide describes the ROBSIM implementation and program logic flow, and the functions and structures of the different subroutines. With this manual and the in-code documentation, and experienced programmer can incorporate additional routines and modify existing ones to add desired capabilities.

Multiprog virtual laboratory applied to PLC programming learning

NASA Astrophysics Data System (ADS)

Shyr, Wen-Jye

2010-10-01

This study develops a Multiprog virtual laboratory for a mechatronics education designed to teach how to programme a programmable logic controller (PLC). The study was carried out with 34 students in the Department of Industry Education and Technology at National Changhua University of Education in Taiwan. In total, 17 students were assigned to each group, experimental and control. Two laboratory exercises were designed to provide students with experience in PLC programming. The results show that the experiments supported by Multiprog virtual laboratory user-friendly control interfaces generate positive meaningful results in regard to students' knowledge and understanding of the material.

Integrated electronics for time-resolved array of single-photon avalanche diodes

NASA Astrophysics Data System (ADS)

Acconcia, G.; Crotti, M.; Rech, I.; Ghioni, M.

2013-12-01

The Time Correlated Single Photon Counting (TCSPC) technique has reached a prominent position among analytical methods employed in a great variety of fields, from medicine and biology (fluorescence spectroscopy) to telemetry (laser ranging) and communication (quantum cryptography). Nevertheless the development of TCSPC acquisition systems featuring both a high number of parallel channels and very high performance is still an open challenge: to satisfy the tight requirements set by the applications, a fully parallel acquisition system requires not only high efficiency single photon detectors but also a read-out electronics specifically designed to obtain the highest performance in conjunction with these sensors. To this aim three main blocks have been designed: a gigahertz bandwidth front-end stage to directly read the custom technology SPAD array avalanche current, a reconfigurable logic to route the detectors output signals to the acquisition chain and an array of time measurement circuits capable of recording the photon arrival times with picoseconds time resolution and a very high linearity. An innovative architecture based on these three circuits will feature a very high number of detectors to perform a truly parallel spatial or spectral analysis and a smaller number of high performance time-to-amplitude converter offering very high performance and a very high conversion frequency while limiting the area occupation and power dissipation. The routing logic will make the dynamic connection between the two arrays possible in order to guarantee that no information gets lost.

Programmable assembly of nanoarchitectures using genetically engineered viruses.

PubMed

Huang, Yu; Chiang, Chung-Yi; Lee, Soo Kwan; Gao, Yan; Hu, Evelyn L; De Yoreo, James; Belcher, Angela M

2005-07-01

Biological systems possess inherent molecular recognition and self-assembly capabilities and are attractive templates for constructing complex material structures with molecular precision. Here we report the assembly of various nanoachitectures including nanoparticle arrays, hetero-nanoparticle architectures, and nanowires utilizing highly engineered M13 bacteriophage as templates. The genome of M13 phage can be rationally engineered to produce viral particles with distinct substrate-specific peptides expressed on the filamentous capsid and the ends, providing a generic template for programmable assembly of complex nanostructures. Phage clones with gold-binding motifs on the capsid and streptavidin-binding motifs at one end are created and used to assemble Au and CdSe nanocrytals into ordered one-dimensional arrays and more complex geometries. Initial studies show such nanoparticle arrays can further function as templates to nucleate highly conductive nanowires that are important for addressing/interconnecting individual nanostructures.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications.

PubMed

Linn, E; Menzel, S; Ferch, S; Waser, R

2013-09-27

Dynamic physics-based models of resistive switching devices are of great interest for the realization of complex circuits required for memory, logic and neuromorphic applications. Here, we apply such a model of an electrochemical metallization (ECM) cell to complementary resistive switches (CRSs), which are favorable devices to realize ultra-dense passive crossbar arrays. Since a CRS consists of two resistive switching devices, it is straightforward to apply the dynamic ECM model for CRS simulation with MATLAB and SPICE, enabling study of the device behavior in terms of sweep rate and series resistance variations. Furthermore, typical memory access operations as well as basic implication logic operations can be analyzed, revealing requirements for proper spike and level read operations. This basic understanding facilitates applications of massively parallel computing paradigms required for neuromorphic applications.

A Hardware-in-the-Loop Simulation Platform for the Verification and Validation of Safety Control Systems

NASA Astrophysics Data System (ADS)

Rankin, Drew J.; Jiang, Jin

2011-04-01

Verification and validation (V&V) of safety control system quality and performance is required prior to installing control system hardware within nuclear power plants (NPPs). Thus, the objective of the hardware-in-the-loop (HIL) platform introduced in this paper is to verify the functionality of these safety control systems. The developed platform provides a flexible simulated testing environment which enables synchronized coupling between the real and simulated world. Within the platform, National Instruments (NI) data acquisition (DAQ) hardware provides an interface between a programmable electronic system under test (SUT) and a simulation computer. Further, NI LabVIEW resides on this remote DAQ workstation for signal conversion and routing between Ethernet and standard industrial signals as well as for user interface. The platform is applied to the testing of a simplified implementation of Canadian Deuterium Uranium (CANDU) shutdown system no. 1 (SDS1) which monitors only the steam generator level of the simulated NPP. CANDU NPP simulation is performed on a Darlington NPP desktop training simulator provided by Ontario Power Generation (OPG). Simplified SDS1 logic is implemented on an Invensys Tricon v9 programmable logic controller (PLC) to test the performance of both the safety controller and the implemented logic. Prior to HIL simulation, platform availability of over 95% is achieved for the configuration used during the V&V of the PLC. Comparison of HIL simulation results to benchmark simulations shows good operational performance of the PLC following a postulated initiating event (PIE).

Intelligent layered nanoflare: "lab-on-a-nanoparticle" for multiple DNA logic gate operations and efficient intracellular delivery.

PubMed

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-08-07

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a "lab-on-a-nanoparticle", the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.

Forest Fertilization Symposium Proceedings

Treesearch

Albert L. Leaf; Raymond E. Leonard

1973-01-01

Forest fertilization is a cultural practice becoming available to forest land managers for use in meeting management objectives. Like other cultural practices, it involves an investment in the site, it may result in an array of side effects in the ecosystem, and it must fit logically into long-range management plans.

A programmable time alignment scheme for detector signals from the upgraded muon spectrometer at the ATLAS experiment

NASA Astrophysics Data System (ADS)

Wang, Jinhong; Guan, Liang; Chapman, J.; Zhou, Bing; Zhu, Junjie

2017-11-01

We present a programmable time alignment scheme used in an ASIC for the ATLAS forward muon trigger development. The scheme utilizes regenerated clocks with programmable phases to compensate for the timing offsets introduced by different detector trace lengths. Each ASIC used in the design has 104 input channels with delay compensation circuitry providing steps of ∼3 ns and a full range of 25 ns for each channel. Detailed implementation of the scheme including majority logic to suppress single-event effects is presented. The scheme is flexible and fully synthesizable. The approach is adaptable to other applications with similar phase shifting requirements. In addition, the design is resource efficient and is suitable for cost-effective digital implementation with a large number of channels.

Integrating IR detector imaging systems

NASA Technical Reports Server (NTRS)

Bailey, G. C. (Inventor)

1984-01-01

An integrating IR detector array for imaging is provided in a hybrid circuit with InSb mesa diodes in a linear array, a single J-FET preamplifier for readout, and a silicon integrated circuit multiplexer. Thin film conductors in a fan out pattern deposited on an Al2O3 substrate connect the diodes to the multiplexer, and thick film conductors also connect the reset switch and preamplifier to the multiplexer. Two phase clock pulses are applied with a logic return signal to the multiplexer through triax comprised of three thin film conductors deposited between layers. A lens focuses a scanned image onto the diode array for horizontal read out while a scanning mirror provides vertical scan.

Evolutionary Multiobjective Design Targeting a Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Aguirre, Arturo Hernandez; Zebulum, Ricardo S.; Coello, Carlos Coello

2004-01-01

This paper introduces the ISPAES algorithm for circuit design targeting a Field Programmable Transistor Array (FPTA). The use of evolutionary algorithms is common in circuit design problems, where a single fitness function drives the evolution process. Frequently, the design problem is subject to several goals or operating constraints, thus, designing a suitable fitness function catching all requirements becomes an issue. Such a problem is amenable for multi-objective optimization, however, evolutionary algorithms lack an inherent mechanism for constraint handling. This paper introduces ISPAES, an evolutionary optimization algorithm enhanced with a constraint handling technique. Several design problems targeting a FPTA show the potential of our approach.

Programmable optical microshutter arrays for large aspect ratio microslits

NASA Astrophysics Data System (ADS)

Ilias, S.; Picard, F.; Larouche, C.; Kruzelecky, R.; Jamroz, W.; Le Noc, L.; Topart, P.

2008-06-01

Design, fabrication and characterization of a 16x1 programmable microshutter array are described. Each shutter controls the light transmitted through a microslit defined on the transparent substrate supporting the array. Two approaches were considered for the shutter array implementation: sweeping blades and zipping actuators. Simulation results and fabrication constraints led to the selection of the zipping actuators. The device was fabricated using a surface micromachining process. Each microshutter is basically an electrostatic zipping actuator having a curved shape induced by a stress gradient throughout the actuator thickness. When a sufficient voltage is applied between the microshutter and an actuation electrode surrounding the microslit area, the generated electrostatic force pulls the actuator down to the substrate which closes the microslit. Opening the slit relies on the restoring force due to the actuator deformation. Microshutter arrays were fabricated successfully. High light transmission through the slit area is obtained with the actuator in the open position and excellent light blocking is observed when the shutter is closed. Static and dynamic responses of the device were determined. A pull-in voltage of about 110 V closes the microslit and the response times to close and open the microslit are about 2 and 7 ms, respectively.

DNA "nano-claw": logic-based autonomous cancer targeting and therapy.

PubMed

You, Mingxu; Peng, Lu; Shao, Na; Zhang, Liqin; Qiu, Liping; Cui, Cheng; Tan, Weihong

2014-01-29

Cell types, both healthy and diseased, can be classified by inventories of their cell-surface markers. Programmable analysis of multiple markers would enable clinicians to develop a comprehensive disease profile, leading to more accurate diagnosis and intervention. As a first step to accomplish this, we have designed a DNA-based device, called "Nano-Claw". Combining the special structure-switching properties of DNA aptamers with toehold-mediated strand displacement reactions, this claw is capable of performing autonomous logic-based analysis of multiple cancer cell-surface markers and, in response, producing a diagnostic signal and/or targeted photodynamic therapy. We anticipate that this design can be widely applied in facilitating basic biomedical research, accurate disease diagnosis, and effective therapy.

The political economy of rationing health care in England and the US: the 'accidental logics' of political settlements.

PubMed

Bevan, Gwyn; Brown, Lawrence D

2014-07-01

This article considers how the 'accidental logics' of political settlements for the English National Health Service (NHS) and the Medicare and Medicaid programmes in the United States have resulted in different institutional arrangements and different implicit social contracts for rationing, which we define to be the denial of health care that is beneficial but is deemed to be too costly. This article argues that rationing is designed into the English NHS and designed out of US Medicare; and compares rationing for the elderly in the United States and in England for acute care, care at the end of life, and chronic care.