Science.gov

Sample records for programmable logic devices

  1. Fuzzy logic and coarse coding using programmable logic devices

    NASA Astrophysics Data System (ADS)

    Brooks, Geoffrey

    2009-05-01

    Naturally-occurring sensory signal processing algorithms, such as those that inspired fuzzy-logic control, can be integrated into non-naturally-occurring high-performance technology, such as programmable logic devices, to realize novel bio-inspired designs. Research is underway concerning an investigation into using field programmable logic devices (FPLD's) to implement fuzzy logic sensory processing. A discussion is provided concerning the commonality between bio-inspired fuzzy logic algorithms and coarse coding that is prevalent in naturally-occurring sensory systems. Undergraduate design projects using fuzzy logic for an obstacle-avoidance robot has been accomplished at our institution and other places; numerous other successful fuzzy logic applications can be found as well. The long-term goal is to leverage such biomimetic algorithms for future applications. This paper outlines a design approach for implementing fuzzy-logic algorithms into reconfigurable computing devices. This paper is presented in an effort to connect with others who may be interested in collaboration as well as to establish a starting point for future research.

  2. Starting Circuit For Erasable Programmable Logic Device

    NASA Technical Reports Server (NTRS)

    Cole, Steven W.

    1990-01-01

    Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.

  3. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm

  4. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment

  5. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

  6. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, and some total dose results.

  7. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, heavy ion test results, and some total dose results.

  8. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    2000-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will start a series of notes concentrating on analysis techniques with this issues section discussing worst-case analysis requirements.

  9. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Day, John H. (Technical Monitor)

    2001-01-01

    This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.

  10. Flexible programmable logic module

    DOEpatents

    Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

    2001-01-01

    The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

  11. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1999-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter the focus is on some experimental data on low voltage drop out regulators to support mixed 5 and 3.3 volt systems. A discussion of the Small Explorer WIRE spacecraft will also be given. Lastly, we show take a first look at robust state machines in Hardware Description Languages (VHDL) and their use in critical systems. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or e-mail.

  12. Programmable Logic Controllers.

    ERIC Educational Resources Information Center

    Insolia, Gerard; Anderson, Kathleen

    This document contains a 40-hour course in programmable logic controllers (PLC), developed for a business-industry technology resource center for firms in eastern Pennsylvania by Northampton Community College. The 10 units of the course cover the following: (1) introduction to programmable logic controllers; (2) DOS primer; (3) prerequisite…

  13. A complex programmable logic device-based high-precision electrical capacitance tomography system

    NASA Astrophysics Data System (ADS)

    Zhou, Haili; Xu, Lijun; Cao, Zhang; Liu, XiaoLei; Liu, Shi

    2013-07-01

    In this paper, a high-precision measurement system for electrical capacitance tomography (ECT) is presented. A low-cost complex programmable logic device (CPLD) is employed to accomplish logic control, signal generation, data acquisition, digital demodulation and communication with the aid of external components. By adopting a simple digital demodulator recently developed by the authors, the demodulation to ac signals becomes rather simple and resource-saving. A double-T-switches configuration is developed to improve the precision and lower the limit of multi-channel capacitance measurement. A capacitance network is constructed for system calibration. A square ECT sensor with 16 electrodes is constructed to test the practical performance of the measurement system. With a data acquisition rate of 185 frame s-1, the signal-to-noise ratio and standard deviation of capacitance measurement can reach up to 70 dB and 0.09 fF, respectively. Image reconstruction experiment has validated the CPLD-based ECT system.

  14. Software Safety Assurance of Programmable Logic

    NASA Technical Reports Server (NTRS)

    Berens, Kalynnda

    2002-01-01

    Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

  15. Programmable Logic Controllers. Teacher Edition.

    ERIC Educational Resources Information Center

    Rauh, Bob; Kaltwasser, Stan

    These materials were developed for a seven-unit secondary or postsecondary education course on programmable logic controllers (PLCs) that treats most of the skills needed to work effectively with PLCs as programming skills. The seven units of the course cover the following topics: fundamentals of programmable logic controllers; contracts, timers,…

  16. Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Darrin, Ann Garrison; Conde, Richard; Chern, Bobbie; Luers, Phil; Jurczyk, Steve; Mills, Carl; Day, John H. (Technical Monitor)

    2001-01-01

    The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of

  17. Microelectromechanical reprogrammable logic device

    NASA Astrophysics Data System (ADS)

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-03-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

  18. Microelectromechanical reprogrammable logic device

    PubMed Central

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-01-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

  19. Universal programmable logic gate and routing method

    NASA Technical Reports Server (NTRS)

    Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

    2009-01-01

    An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

  20. Design of a Ferroelectric Programmable Logic Gate Array

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Ho, Fat Duen

    2003-01-01

    A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

  1. Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

    ERIC Educational Resources Information Center

    Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

    2009-01-01

    Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

  2. Firmware Modification Analysis in Programmable Logic Controllers

    DTIC Science & Technology

    2014-03-27

    MODIFICATION ANALYSIS IN PROGRAMMABLE LOGIC CONTROLLERS Arturo M. Garcia Jr., B.S.S.E.C.A. Captain, USA Approved: //signed// Robert F. Mills , PhD...Matthew 5:37 v Acknowledgments My sincere gratitude to my committee for their guidance and teamwork which made this thesis possible. Dr. Mills ...2012. 2012. [5] Bolton, William. Programmable logic controllers. Newnes, 2009. [6] Boyer, Stuart . SCADA: Supervisory Control and Data Aquisition 4th

  3. Implementing neural nets with programmable logic

    NASA Technical Reports Server (NTRS)

    Vidal, Jacques J.

    1988-01-01

    Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

  4. G4-FETs as Universal and Programmable Logic Gates

    NASA Technical Reports Server (NTRS)

    Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

    2007-01-01

    An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

  5. PLAFST Programmable Logic Array from State Table.

    DTIC Science & Technology

    1983-12-01

    HD -i8 466 PL AFST PROGRAMMABLE LOGIC ARRAY FROM STATE T ABLE(U) AIR /2 FORC INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF UNCLSSIIED...INSTITUTE OF TECHNOLOGY Wright-Patterson Air Force Base, Ohio ) A ’J[. .:’,,- oved iot public T.,-].:.,’ 8 4 7 x -;..- APIT/GE/EE/83D-57 Accession For...number of rows with y - 1. Don’t care symbols are denoted by a " x ". The l’s and x’s are grouped together like Karnaugh maps with two exceptions. The

  6. Reactivity measurement using a programmable logic controller

    SciTech Connect

    Bobek, L.M.; Miraglia, P.Q.

    1995-12-31

    The application of digital systems for measuring reactor dynamics has been used at experimental and research reactors for almost 30 yr. At the Worcester Polytechnic Institute (WPI) nuclear reactor facility (NRF), a recent modernization effort included the installation of a programmable logic controller (PLC) and an operator interface terminal (OIT). The PLC systems are increasingly being used to replace relay-based monitoring and control systems at nuclear power plants. At WPI, the PLC and OIT provide a digital reactor monitoring system that is remote from the reactor`s analog control instrumentation. The NRF staff has programmed the monitoring system for several reactor-related applications, including reactivity measurement.

  7. Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

    ERIC Educational Resources Information Center

    Debiec, P.; Byczuk, M.

    2011-01-01

    Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

  8. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    SciTech Connect

    Lashin, A. V. Kozyrev, A. V.

    2015-09-15

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

  9. Multilevel programmable logic array schemes for microprogrammed automata

    SciTech Connect

    Barkalov, A.A.

    1995-03-01

    Programmable logic arrays (PLAs) provide an efficient tool for implementation of logic schemes of microprogrammed automata (MPA). The number of PLAs in the MPA logic scheme can be minimized by increasing the number of levels. In this paper, we analyze the structures of multilevel schemes of Mealy automata, propose a number of new structures, consider the corresponding correctness conditions, and examine some problems that must be solved in order to satisfy these conditions.

  10. A Device for Logic Information Processing.

    ERIC Educational Resources Information Center

    Levinskiy, L. S.; Vissonova, I. A.

    Two essential components of the information-logic problem are: (1) choosing some known part of the total information block for parallel review of the entire block and (2) parallel logic processing of a sequence of codes. The described device fulfills these essential components thereby improving information processing and increasing the speed of…

  11. Optical design of programmable logic arrays

    NASA Astrophysics Data System (ADS)

    Murdocca, Miles J.; Huang, Alan; Jahns, Jurgen; Streibl, Norbert

    1988-05-01

    Regular free-space interconnects such as the perfect shuffle and banyan provided by beam splitters, lenses, and mirrors connect optical logic gates arranged in two-dimensional arrays. An algorithmic design technique transforms arbitrary logic equations into a near-optimal depth circuit. Analysis shows that an arbitrary interconnect makes little or no improvement in circuit depth and can even reduce throughput. Gate count is normally higher with a regular interconnect, and cost bounds are shown. It is concluded that regularly interconnected circuits will have a higher gate count compared with arbitrarily interconnected circuits using the design techniques presented here and that regular free-space interconnects are comparable with arbitrary interconnects in terms of circuit depth and are preferred to arbitrary interconnects for maximizing throughput.

  12. Programming Programmable Logic Controller. High-Technology Training Module.

    ERIC Educational Resources Information Center

    Lipsky, Kevin

    This training module on programming programmable logic controllers (PLC) is part of the memory structure and programming unit used in a packaging systems equipment control course. In the course, students assemble, install, maintain, and repair industrial machinery used in industry. The module contains description, objectives, content outline,…

  13. Current Radiation Issues for Programmable Elements and Devices

    NASA Technical Reports Server (NTRS)

    Katz, R.; Wang, J. J.; Koga, R.; LaBel, A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.; Paolini, W.; Sin, B.

    1998-01-01

    State of the an programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.

  14. Spin wave nonreciprocity for logic device applications

    PubMed Central

    Jamali, Mahdi; Kwon, Jae Hyun; Seo, Soo-Man; Lee, Kyung-Jin; Yang, Hyunsoo

    2013-01-01

    The utilization of spin waves as eigenmodes of the magnetization dynamics for information processing and communication has been widely explored recently due to its high operational speed with low power consumption and possible applications for quantum computations. Previous proposals of spin wave Mach-Zehnder devices were based on the spin wave phase, a delicate entity which can be easily disrupted. Here, we propose a complete logic system based on the spin wave amplitude utilizing the nonreciprocal spin wave behavior excited by microstrip antennas. The experimental data reveal that the nonreciprocity of magnetostatic surface spin wave can be tuned by the bias magnetic field. Furthermore, engineering of the device structure could result in a high nonreciprocity factor for spin wave logic applications. PMID:24196318

  15. Fuzzy Petri net-based programmable logic controller.

    PubMed

    Andreu, D; Pascal, J C; Valette, R

    1997-01-01

    Programmable logic controllers (PLCs) are able to directly implement control sequences specified by means of standard languages such as Grafcet or formal models such as Petri nets. In the case of simple regulation problems between two steps it could be of great interest to introduce a notion of "fuzzy events" in order to denote a continuous evolution from one state to another. This could result from a linear interpolation between the commands attached to two control steps represented by two Petri net (PN) places. This paper is an attempt to develop fuzzy PN-based PLCs in a similar way as fuzzy controllers (regulators). Our approach is based on a combination of Petri nets with possibility theory (Petri nets with fuzzy markings).

  16. The programmable (logic) controller: Adapting in an environment of change

    SciTech Connect

    Levine, P.S.

    1995-03-01

    Reports of the imminent death of the PLC (programmable logic controller) were greatly exaggerated, to paraphrase Mark Twain. In fact, the PLC is not only alive and working worldwide in thousands of applications, but it is also integrating well with related technologies. Long-term survival is a larger question - probably unanswerable given the pace of technological change. However, a few questions arise about the PLC today and in the immediate future: (1) What`s happening with programming languages? (2) Will there continue to be a {open_quotes}blurring of the lines{close_quotes} between the PLC and other technologies, and what role will software play in this integration? (3) How will the PLC`s cost and size affect the market?

  17. Development of ferrite logic devices for an arithmetic processor

    NASA Technical Reports Server (NTRS)

    Heckler, C. H., Jr.

    1972-01-01

    A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.

  18. Sandia ATM SONET Interface Logic

    SciTech Connect

    Kitta, Joseph P.

    1994-07-21

    SASIL is used to program the EPLD's (Erasable Programmable Logic Devices) and PAL's (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.

  19. Designing a Beamline Equipment Protection System Using a Programmable Logic Controller

    NASA Astrophysics Data System (ADS)

    Minich, James M.

    1996-09-01

    As part of the Synchrotron Radiation Instrumentation Collaborative Access Team (SRI-CAT), a new beamline equipment protection system was designed, implemented and installed. The beamline equipment protection system is designed to assure the safe operation of bending magnet and insertion device beamline components, such as white-beam slits, user filters, shutters and stops, mirrors and monochromators. Design goals of the equipment protection system were to improve equipment safety performance, reduce nuisance trips and incorporate additional system functions with minimal cost. To meet the requirements of such a safety system, it was configured to use a programmable controller, remote block input/output (I/O), local interfaces and a serial communication link known as remote I/O (RIO). Aspects about the design requirements, functionality and constraints are presented, as well as specifics on programmable ladder logic design, hardware selection, testing and interfacing requirements.

  20. Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits

    NASA Astrophysics Data System (ADS)

    Ogawa, Taichi; Hirose, Tetsuya; Asai, Tetsuya; Amemiya, Yoshihito

    A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.

  1. Processing device with self-scrubbing logic

    SciTech Connect

    Wojahn, Christopher K.

    2016-03-01

    An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.

  2. Programmable logic controller optical fibre sensor interface module

    NASA Astrophysics Data System (ADS)

    Allwood, Gary; Wild, Graham; Hinckley, Steven

    2011-12-01

    Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

  3. Partial reconfiguration of concurrent logic controllers implemented in FPGA devices

    NASA Astrophysics Data System (ADS)

    Wiśniewski, Remigiusz; Grobelna, Iwona; Stefanowicz, Łukasz

    2016-12-01

    Reconfigurable systems are recently used in many domains. Although the concept of multi-context logic controllers is relatively new, it may be noticed that the subject is receiving a lot of attention, especially in the industry. The work constitutes a stepping stone in design of reconfigurable logic controllers implemented in an FPGA device. An approach of designing of logic controllers oriented for further partial reconfiguration is proposed. A case study of a milling machine is used for an illustration.

  4. Compact programmable photonic variable delay devices

    NASA Technical Reports Server (NTRS)

    Yao, X. Steve (Inventor)

    1999-01-01

    Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm.sup.2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.

  5. SASIL. Sandia ATM SONET Interface Logic

    SciTech Connect

    Kitta, J P

    1994-07-01

    SASIL is used to program the EPLD`s (Erasable Programmable Logic Devices) and PAL`s (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.

  6. Voltage controlled spintronic devices for logic applications

    DOEpatents

    You, Chun-Yeol; Bader, Samuel D.

    2001-01-01

    A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

  7. General purpose programmable accelerator board

    DOEpatents

    Robertson, Perry J.; Witzke, Edward L.

    2001-01-01

    A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

  8. Ultrafast phase-change logic device driven by melting processes.

    PubMed

    Loke, Desmond; Skelton, Jonathan M; Wang, Wei-Jie; Lee, Tae-Hoon; Zhao, Rong; Chong, Tow-Chong; Elliott, Stephen R

    2014-09-16

    The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change-based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change-based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change-based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates.

  9. Ultrafast phase-change logic device driven by melting processes

    PubMed Central

    Loke, Desmond; Skelton, Jonathan M.; Wang, Wei-Jie; Lee, Tae-Hoon; Zhao, Rong; Chong, Tow-Chong; Elliott, Stephen R.

    2014-01-01

    The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change–based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change–based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change–based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates. PMID:25197044

  10. Memristor-based programmable logic array (PLA) and analysis as Memristive networks.

    PubMed

    Lee, Kwan-Hee; Lee, Sang-Jin; Kim, Seok-Man; Cho, Kyoungrok

    2013-05-01

    A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors.

  11. pH-programmable DNA logic arrays powered by modular DNAzyme libraries.

    PubMed

    Elbaz, Johann; Wang, Fuan; Remacle, Francoise; Willner, Itamar

    2012-12-12

    Nature performs complex information processing circuits, such the programmed transformations of versatile stem cells into targeted functional cells. Man-made molecular circuits are, however, unable to mimic such sophisticated biomachineries. To reach these goals, it is essential to construct programmable modular components that can be triggered by environmental stimuli to perform different logic circuits. We report on the unprecedented design of artificial pH-programmable DNA logic arrays, constructed by modular libraries of Mg(2+)- and UO(2)(2+)-dependent DNAzyme subunits and their substrates. By the appropriate modular design of the DNA computation units, pH-programmable logic arrays of various complexities are realized, and the arrays can be erased, reused, and/or reprogrammed. Such systems may be implemented in the near future for nanomedical applications by pH-controlled regulation of cellular functions or may be used to control biotransformations stimulated by bacteria.

  12. Programmable Metallization Cell Devices for Flexible Electronics

    NASA Astrophysics Data System (ADS)

    Baliga, Sunil

    Programmable metallization cell (PMC) technology is based on an electrochemical phenomenon in which a metallic electrodeposit can be grown or dissolved between two electrodes depending on the voltage applied between them. Devices based on this phenomenon exhibit a unique, self-healing property, as a broken metallic structure can be healed by applying an appropriate voltage between the two broken ends. This work explores methods of fabricating interconnects and switches based on PMC technology on flexible substrates. The objective was the evaluation of the feasibility of using this technology in flexible electronics applications in which reliability is a primary concern. The re-healable property of the interconnect is characterized for the silver doped germanium selenide (Ag-Ge-Se) solid electrolyte system. This property was evaluated by measuring the resistances of the healed interconnect structures and comparing these to the resistances of the unbroken structures. The reliability of the interconnects in both unbroken and healed states is studied by investigating the resistances of the structures to DC voltages, AC voltages and different temperatures as a function of time. This work also explores replacing silver with copper for these interconnects to enhance their reliability. A model for PMC-based switches on flexible substrates is proposed and compared to the observed device behavior with the objective of developing a formal design methodology for these devices. The switches were subjected to voltage sweeps and their resistance was investigated as a function of sweep voltage. The resistance of the switches as a function of voltage pulse magnitude when placed in series with a resistance was also investigated. A model was then developed to explain the behavior of these devices. All observations were based on statistical measurements to account for random errors. The results of this work demonstrate that solid electrolyte based interconnects display self

  13. Experimental demonstration of programmable multi-functional spin logic cell based on spin Hall effect

    NASA Astrophysics Data System (ADS)

    Zhang, X.; Wan, C. H.; Yuan, Z. H.; Fang, C.; Kong, W. J.; Wu, H.; Zhang, Q. T.; Tao, B. S.; Han, X. F.

    2017-04-01

    Confronting with the gigantic volume of data produced every day, raising integration density by reducing the size of devices becomes harder and harder to meet the ever-increasing demand for high-performance computers. One feasible path is to actualize more logic functions in one cell. In this respect, we experimentally demonstrate a prototype spin-orbit torque based spin logic cell integrated with five frequently used logic functions (AND, OR, NOT, NAND and NOR). The cell can be easily programmed and reprogrammed to perform desired function. Furthermore, the information stored in cells is symmetry-protected, making it possible to expand into logic gate array where the cell can be manipulated one by one without changing the information of other undesired cells. This work provides a prospective example of multi-functional spin logic cell with reprogrammability and nonvolatility, which will advance the application of spin logic devices.

  14. Towards Quantifying Programmable Logic Controller Resilience Against Intentional Exploits

    DTIC Science & Technology

    2012-03-22

    the metric applicable. The data used for this research is derived from PLC simulations executed on LogixPro ® 500 software. The definition for...applied to the SUT are primarily fixed attributes of the PLC emulation provided by LogixPro ® 500; the varying parameter during experimentation is the...programmed in ladder logic from a laptop with the accompanying LogixPro ® 500 software package associated with the PLC. The program is loaded to the

  15. Motor imaginary-based brain-machine interface design using programmable logic controllers for the disabled.

    PubMed

    Jeyabalan, Vickneswaran; Samraj, Andrews; Loo, Chu Kiong

    2010-10-01

    Aiming at the implementation of brain-machine interfaces (BMI) for the aid of disabled people, this paper presents a system design for real-time communication between the BMI and programmable logic controllers (PLCs) to control an electrical actuator that could be used in devices to help the disabled. Motor imaginary signals extracted from the brain’s motor cortex using an electroencephalogram (EEG) were used as a control signal. The EEG signals were pre-processed by means of adaptive recursive band-pass filtrations (ARBF) and classified using simplified fuzzy adaptive resonance theory mapping (ARTMAP) in which the classified signals are then translated into control signals used for machine control via the PLC. A real-time test system was designed using MATLAB for signal processing, KEP-Ware V4 OLE for process control (OPC), a wireless local area network router, an Omron Sysmac CPM1 PLC and a 5 V/0.3A motor. This paper explains the signal processing techniques, the PLC's hardware configuration, OPC configuration and real-time data exchange between MATLAB and PLC using the MATLAB OPC toolbox. The test results indicate that the function of exchanging real-time data can be attained between the BMI and PLC through OPC server and proves that it is an effective and feasible method to be applied to devices such as wheelchairs or electronic equipment.

  16. Radio Frequency Based Programmable Logic Controller Anomaly Detection

    DTIC Science & Technology

    2013-09-01

    RF- DNA Transform . . . . . . . . . . . . . . . . . . . . 49 3.7 Region of Interest Selection . . . . . . . . . . . . . . . . . . . . 52 3.8 CBAD...Device, NB=60, NOp=5 . . . . . . . . . . . . . . . 71 4.4 Software Anomaly Detection: RF- DNA Sequences . . . . . . . . 74 vii Page 4.4.1 Single Device...Waveforms . . . . . . . . . . . . . . 50 3.11 RF- DNA Fingerprint Diagram . . . . . . . . . . . . . . . . . 53 3.12 Representative Collected Scan Waveform

  17. Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

    ERIC Educational Resources Information Center

    Todorovich, E.; Marone, J. A.; Vazquez, M.

    2012-01-01

    Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

  18. A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

    ERIC Educational Resources Information Center

    Kellett, C. M.

    2012-01-01

    This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is…

  19. Energy Efficient Digital Logic Using Nanoscale Magnetic Devices

    NASA Astrophysics Data System (ADS)

    Lambson, Brian James

    Increasing demand for information processing in the last 50 years has been largely satisfied by the steadily declining price and improving performance of microelectronic devices. Much of this progress has been made by aggressively scaling the size of semiconductor transistors and metal interconnects that microprocessors are built from. As devices shrink to the size regime in which quantum effects pose significant challenges, new physics may be required in order to continue historical scaling trends. A variety of new devices and physics are currently under investigation throughout the scientific and engineering community to meet these challenges. One of the more drastic proposals on the table is to replace the electronic components of information processors with magnetic components. Magnetic components are already commonplace in computers for their information storage capability. Unlike most electronic devices, magnetic materials can store data in the absence of a power supply. Today's magnetic hard disk drives can routinely hold billions of bits of information and are in widespread commercial use. Their ability to function without a constant power source hints at an intrinsic energy efficiency. The question we investigate in this dissertation is whether or not this advantage can be extended from information storage to the notoriously energy intensive task of information processing. Several proof-of-concept magnetic logic devices were proposed and tested in the past decade. In this dissertation, we build on the prior work by answering fundamental questions about how magnetic devices achieve such high energy efficiency and how they can best function in digital logic applications. The results of this analysis are used to suggest and test improvements to nanomagnetic computing devices. Two of our results are seen as especially important to the field of nanomagnetic computing: (1) we show that it is possible to operate nanomagnetic computers at the fundamental

  20. 242-A/LERF programmable Logic Controller Ladder. Revision 1

    SciTech Connect

    Teats, M.C.

    1995-05-23

    This document defines and describes the user-generated application software written to transmit digital and analog signals from the Liquid Effluent Retention Facility (LERF) to the 242-A Evaporator Distributed Control System (DCS). PLCs and modems were installed in the 242-A Evaporator by Project W-105 (LERF) to transmit 6 analog liquid level signals, 6 range alarms based on the analog signals, and 6 leak detection and pump status signals to the 242-A Distributive Control System (DCS) from LERF. Communications between the two facilities are also monitored and alarm on the DCS. Following the Project W-105 completion, the communications and signal mix were modified by Project C-018H (ETF). The current PLC software (including ladder logic and data tables), PLC hardware settings, and modern option settings to transmit the signals and monitor communications are documented and described in this document.

  1. Preliminary surface-emitting laser logic device evaluation

    NASA Astrophysics Data System (ADS)

    Libby, S. I.; Parker, M. A.; Olbright, G. R.; Swanson, P. D.

    1993-03-01

    This report discusses the evaluation of a monolithically integrated heterojunction phototransistor and vertical-cavity surface-emitting laser, designated the surface-Emitting Laser Logic device (CELL). Included is a discussion of the device structure and theory of operation, test procedures, results, and conclusions. Also presented is the CELL's opto-electronic input/output characteristics which includes spectral analysis, characteristic emitted light versus current and current versus voltage curves, input wavelength tolerance, output wavelength sensitivity to bias current, and insensitivity to input wavelength and power within a specified range.

  2. 46 CFR 62.25-25 - Programmable systems and devices.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 46 Shipping 2 2014-10-01 2014-10-01 false Programmable systems and devices. 62.25-25 Section 62.25-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM AUTOMATION General Requirements for All Automated Vital Systems § 62.25-25 Programmable systems and...

  3. Binary Arithmetic Using Optical Symbolic Substitution and Cascadable Surface-Emitting Laser Logic Devices,

    DTIC Science & Technology

    LOGIC DEVICES, *OPTICAL CIRCUITS, *OPTICAL SWITCHING, HETEROJUNCTIONS, PHOTOTRANSISTORS, ELECTROOPTICS, LASER CAVITIES, OPTICAL PROCESSING, PARALLEL PROCESSING, BISTABLE DEVICES, GATES(CIRCUITS), VOLTAGE, BINARY ARITHMETIC .

  4. Firmware Counterfeiting and Modification Attacks on Programmable Logic Controllers

    DTIC Science & Technology

    2013-03-01

    RTUs ) are field devices designed to control physical aspects of the system . SCADA systems branch out over various communication channels to assorted... RTUs that control and monitor actual physical objects in the system such as valves and sensors. Another type of ICS, called a distributed control system ...DISTRIBUTION UNLIMITED. AFIT-ENG-13-M-06 Abstract Recent attacks on industrial control systems (ICSs), like the highly publicized Stuxnet malware, have

  5. Current-limiting challenges for all-spin logic devices

    PubMed Central

    Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

    2015-01-01

    All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications. PMID:26449410

  6. 242-A Control System device logic software documentation. Revision 2

    SciTech Connect

    Berger, J.F.

    1995-05-19

    A Distributive Process Control system was purchased by Project B-534. This computer-based control system, called the Monitor and Control System (MCS), was installed in the 242-A Evaporator located in the 200 East Area. The purpose of the MCS is to monitor and control the Evaporator and Monitor a number of alarms and other signals from various Tank Farm facilities. Applications software for the MCS was developed by the Waste Treatment System Engineering Group of Westinghouse. This document describes the Device Logic for this system.

  7. D0 General Support: The Use of Programmable Logic Controllers (PLCS) at D0

    SciTech Connect

    Hance, R.; /Fermilab

    2000-05-05

    With the exception of control of heating, ventilation, and air conditioning (HVAC) ventilation fans, and their shutdown in the case of smoke in the ducts, all implementations of Programmable Logic Controllers (PLCs) in Dzero have been made within the fundamental premise that no uncertified PLC apparatus shall be entrusted with the safety of equipment or personnel. Thus although PLCs are used to control and monitor all manner of intricate equipment, simple hardware interlocks and relief devices provide basic protection against component failure, control failure, or inappropriate control operation. Nevertheless, this report includes two observations as follows: (1) It may be prudent to reconfigure the link between the Pyrotronics system and the HVAC system such that the Pyrotronics system provides interlocks to the ventilation fans instead of control inputs to the uncertified HVAC PLCs. Although the Pyrotronics system is certified and maintained to life safety standards, the HVAC system is not. A hardware or software failure of the HVAC system probably should not be allowed to result in the situation where the ventilation fans in a smoke filled duct continue to operate. Dan Markley is investigating this matter. (2) It may also be prudent to examine the network security of those systems connected to the Fermilab WAN (HVAC, Cryo, and Solenoid Controls). Even though the impact of a successful hack might only be to operations, it might nevertheless be disruptive and could be expensive. The risks should perhaps be analyzed. One of the most attractive features of these systems, from a user's viewpoint, is their unlimited networking. The unlimited networking that makes the systems so convenient to legitimate access also makes them vulnerable to illegitimate access.

  8. A power-efficient and non-volatile programmable logic array based on phase change memory

    NASA Astrophysics Data System (ADS)

    Du, Yuan; Ye, Yong; Kang, Yong; Xia, Yangyang; Song, Zhitang; Chen, Bomy

    2016-10-01

    Recently, numerous efforts have been made on NVM-based Field Programmable Gate Arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can't be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, Programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of Programmable Element is OFF.

  9. Programmable logic controller performance enhancement by field programmable gate array based design.

    PubMed

    Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

    2015-01-01

    PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported.

  10. Application of programmable logic controller to pump regulation system for supplying water

    NASA Astrophysics Data System (ADS)

    Ye, Dao-Yi; Yang, Yong-Bin; Lu, Zong-Qi

    This paper describes a pump regulation system for supplying-water. The controlled variable is the output water pressure for supplying-water pumps. The reference input signal is given in PLC. The water pressure for supplying-water pump output is fed back by a A/D converter to CPU in PLC. The output of Programmable Logic Controller Controls a frequency converter. The frequency converter controls three groups of motor-pump. The water from the three pumps enters the same pipe. Programmable Logic Controller (PLC) uses Ladder-shaped diagram software to implement logical control and proportional-plus-integral control. The method for automatic tuning of regulator of the PID type is based on a simple identification method which gives one point on the Nyquist curve of the open loop transfer function. The key idea is a scheme which provides automatic excitation of the process which is nearly optimal for estimating the desired process characteristics. Only a frequency converter controls several groups of motor pumps, therefore, the cost of the system is decreased. This system has electrically breaking off protection function and automatically restoring software. Through a long time operation, the system can work well.

  11. Programmable synaptic devices for electronic neural nets

    NASA Technical Reports Server (NTRS)

    Moopenn, A.; Thakoor, A. P.

    1990-01-01

    The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

  12. A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell

    NASA Astrophysics Data System (ADS)

    Tsai, Yi-Hung; Yang, Hsiao-Lan; Lin, Wun-Jie; Lin, Chrong Jung; King, Ya-Chin

    2010-04-01

    This work presents a novel differential n-channel logic-compatible multiple-time programmable (MTP) memory cell. This cell features double sensing window by a differential pair of floating gates, and therefore increases the retention lifetime of the nonvolatile memory effectively. Also, a self-selective programming (SSP) method is innovated in writing one pair differential data by a single cell without increasing any design or process complexity in peripheral circuit. The differential cell is a promising MTP solution to challenge thin floating gate oxide below 70 Å for 90 nm complementary metal-oxide-semiconductor (CMOS) node and beyond.

  13. Improvement of photovoltaic pumping systems based on standard frequency converters by means of programmable logic controllers

    SciTech Connect

    Fernandez-Ramos, Jose; Narvarte-Fernandez, Luis; Poza-Saura, Fernando

    2010-01-15

    Photovoltaic pumping systems (PVPS) based on standard frequency converters (SFCs) are currently experiencing a growing interest in pumping programmes implemented in remote areas because of their high performance in terms of component reliability, low cost, high power range and good availability of components virtually anywhere in the world. However, in practical applications there have appeared a number of problems related to the adaptation of the SFCs to the requirements of the photovoltaic pumping systems (PVPS). Another disadvantage of dedicated PVPS is the difficulty in implementing maximum power point tracking (MPPT). This paper shows that these problems can be solved through the addition of a basic industrial programmable logic controller (PLC) to the system. This PLC does not increase the cost and complexity of the system, but improves the adaptation of the SFC to the photovoltaic pumping system, and increases the overall performance of the system. (author)

  14. Toward Automating Web Protocol Configuration for a Programmable Logic Controller Emulator

    DTIC Science & Technology

    2014-06-19

    logic controllers ( PLC ). PLC emulators used as honeypots can provide insight into these vulnerabilities. Honeypots can sometimes deter attackers from...real devices and log activity. A variety of PLC emulators exist, but require manual configuration to change their PLC profile. This limits their...flexibility for deployment. An automated process for configuring PLC emulators can open the door for emulation of many types of PLCs . This study

  15. The Programmable Logic Controller and its application in nuclear reactor systems

    SciTech Connect

    Palomar, J.; Wyman, R.

    1993-09-01

    This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out.

  16. A logical molecular circuit for programmable and autonomous regulation of protein activity using DNA aptamer-protein interactions.

    PubMed

    Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R; Tan, Weihong

    2012-12-26

    Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo. (1) As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here, we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy.

  17. Novel nano materials for high performance logic and memory devices

    NASA Astrophysics Data System (ADS)

    Das, Saptarshi

    After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

  18. Model-based pattern dummy generation for logic devices

    NASA Astrophysics Data System (ADS)

    Jang, Jongwon; Kim, Cheolkyun; Ko, Sungwoo; Byun, Seokyoung; Yang, Hyunjo; Yim, Donggyu

    2014-03-01

    The insertion of SRAF(Sub-Resolution Assist Feature) is one of the most frequently used method to enlarge the process window area. In most cases, the size of SRAF is proportional to the focus margin of drawn patterns. However, there is a trade-off between the SRAF size and SRAF printing, because SRAF is not supposed to be patterned on a wafer. For this reason, a lot of OPC engineers have been tried to put bigger and more SRAFs within the limits of the possible. The fact that many papers about predicting SRAF printability have been published recent years reflects this circumstance. Pattern dummy is inserted to enhance the lithographic process margin and CD uniformity unlike CMP dummy for uniform metal line height. It is ordinary to put pattern dummy at the designated location under consideration of the pitch of real patterns at design step. However, it is not always desirable to generate pattern dummies based on rules at the lithographic point of view. In this paper, we introduce the model based pattern dummy insertion method, which is putting pattern dummies at the location that model based SRAF is located. We applied the model based pattern dummy to the layers in logic devices, and studied which layer is more efficient for the insertion of dummies.

  19. Implementation of motor speed control using PID control in programmable logic controller

    NASA Astrophysics Data System (ADS)

    Samin, R. E.; Azmi, N. A.; Ahmad, M. A.; Ghazali, M. R.; Zawawi, M. A.

    2012-11-01

    This paper presents the implementation of motor speed control using Proportional Integral Derrivative (PID) controller using Programmable Logic Controller (PLC). Proportional Integral Derrivative (PID) controller is the technique used to actively control the speed of the motor. An AC motor is used in the research together with the PLC, encoder and Proface touch screen. The model of the PLC that has been used in this project is OMRON CJIG-CPU42P where this PLC has a build in loop control that can be made the ladder diagram quite simple using function block in CX-process tools. A complete experimental analysis of the technique in terms of system response is presented. Comparative assessment of the impact of Proportional, Integral and Derivative in the controller on the system performance is presented and discussed.

  20. Programmable logic controller implementation of an auto-tuned predictive control based on minimal plant information.

    PubMed

    Valencia-Palomo, G; Rossiter, J A

    2011-01-01

    This paper makes two key contributions. First, it tackles the issue of the availability of constrained predictive control for low-level control loops. Hence, it describes how the constrained control algorithm is embedded in an industrial programmable logic controller (PLC) using the IEC 61131-3 programming standard. Second, there is a definition and implementation of a novel auto-tuned predictive controller; the key novelty is that the modelling is based on relatively crude but pragmatic plant information. Laboratory experiment tests were carried out in two bench-scale laboratory systems to prove the effectiveness of the combined algorithm and hardware solution. For completeness, the results are compared with a commercial proportional-integral-derivative (PID) controller (also embedded in the PLC) using the most up to date auto-tuning rules.

  1. Saltwell Leak Detector Station Programmable Logic Controller (PLC) Software Configuration Management Plan (SCMP)

    SciTech Connect

    WHITE, K.A.

    2000-11-28

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell Leak Detector Stations as required by HNF-PRO-309, Rev. 1, Computer Software Quality Assurance, Section 2.4, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell Leak Detector Station Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell Leak Detector Station PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis.

  2. Saltwell PIC Skid Programmable Logic Controller (PLC) Software Configuration Management Plan

    SciTech Connect

    KOCH, M.R.

    1999-11-16

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell PIC Skids as required by LMH-PRO-309, Rev. 0, Computer Software Quality Assurance, Section 2.6, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell PIC Skid Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell PIC Skid PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis.

  3. All optical logic operations using semiconductor optical amplifier based devices

    NASA Astrophysics Data System (ADS)

    Wang, Qiang

    High-speed optical processing technologies are essential for the construction of all-optical networks in the information era. In this Ph. D. thesis dissertation, essential mechanisms related to the semiconductor optical amplifier (SOA) based device such as the gain and phase dynamics when a short pulse in propagating inside SOA, and, all-optical Boolean function, XOR, AND and OR have been studied. In order to realize the all-optical logic using SOA, the nonlinear gain and phase dynamics in SOA need to be studied first. The experimental results of 10--90% gain recovery curve have been presented. The recovery time is related to the carrier lifetime of the SOA and it varies with gain compression and bias current. For pulse width of a few picosecond, intraband effects need to be considered. In the SOA, phase change is also induced when a short pulse is propagating inside SOA. Unlike the conventional way of estimating the phase shift using alpha factor, the maximum phase shift is obtained first, then the effective alpha factor is calculated. The experimental results of all optical Boolean function XOR and OR at 80 Gb/s are presented using SOA-MZI-DI and SOA-DI respectively. These are the highest operating speed that has been reported. The all optical AND operation at 40 Gb/s using SOA-MZI have also been reported here. The numerical simulation shows that the performance of these all-optical Boolean operations is limited by the carrier lifetime of the SOA. The Boolean functions are the first step towards all optical circuits. The designs of a parity checker and a pseudo-random binary sequence (PRBS) generator are demonstrated. The error analysis using quality factor and eye-diagram is also presented.

  4. Evaluation of commercial programmable floating gate devices as radiation dosimeters

    NASA Astrophysics Data System (ADS)

    Edgecock, R.; Matheson, J.; Weber, M.; Giulio Villani, E.; Bose, R.; Khan, A.; Smith, D. R.; Adil-Smith, I.; Gabrielli, A.

    2009-02-01

    Programmable floating gate MOSFET transistors were tested with gamma radiation with doses up to approximately 100Gy (air equivalent), to evaluate their suitability as dosimeters in radiotherapy. After characterization and programming at different threshold voltages, the devices were irradiated and their Vgs shift with dose monitored in real time. Post-irradiation analysis was carried out to evaluate sensitivity, linearity, reproducibility and voltage threshold annealing. A subsequent re-programming phase followed by characterization was performed to asses their post-irradiation charge restoring capabilities. It was found that up to 73% of the initial maximum threshold voltage could be recovered. A sensitivity of up to 9 mV/Gy with an uncertainty of less than 1%, an excellent linearity up to the maximum programmable threshold voltage and low noise suggest the use of this technology for in vivo dosimetry applications.

  5. Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design.

    DTIC Science & Technology

    2014-09-26

    microns %H*SIC dimensions. Part 2: Various Programmable Logic Array (PLA) implementations with clocked CMOS technology are explored inthis project...Previous research at MSU has dealt with clocked CMOS circuit styles with some application to gate array and microprocessor applications. Work under this...in this report deals with structured logic schemes based on Programmable Logic Arrays (PLAs). Three different PLA design methods are reported with a

  6. Controlling High Power Devices with Computers or TTL Logic Circuits

    ERIC Educational Resources Information Center

    Carlton, Kevin

    2002-01-01

    Computers are routinely used to control experiments in modern science laboratories. This should be reflected in laboratories in an educational setting. There is a mismatch between the power that can be delivered by a computer interfacing card or a TTL logic circuit and that required by many practical pieces of laboratory equipment. One common way…

  7. Designing the Expanded Programme on Immunisation (EPI) as a service: Prioritising patients over administrative logic.

    PubMed

    McKnight, Jacob; Holt, Douglas B

    2014-01-01

    Expanded Programme on Immunisation (EPI) vaccination rates remain well below herd immunity in regions of many countries despite huge international resources devoted to both financing and access. We draw upon service marketing theory, organisational sociology, development anthropology and cultural consumer research to conduct an ethnographic study of vaccination delivery in Jimma Zone, Ethiopia - one such region. We find that Western public health sector policies are dominated by an administrative logic. Critical failures in delivery are produced by a system that obfuscates the on-the-ground problems that mothers face in trying to vaccinate their children, while instead prioritising administrative processes. Our ethnographic analysis of 83 mothers who had not vaccinated their children reveals key barriers to vaccination from a 'customer' perspective. While mothers value vaccination, it is a 'low involvement' good compared to the acute daily needs of a subsistence life. The costs imposed by poor service - such as uncaring staff with class hostilities, unpredictable and missed schedules and long waits - are too much and so they forego the service. Our service design framework illuminates specific service problems from the mother's perspective and points towards simple service innovations that could improve vaccination rates in regions that have poor uptake.

  8. Ion-tuned DNA/Ag fluorescent nanoclusters as versatile logic device.

    PubMed

    Li, Tao; Zhang, Libing; Ai, Jun; Dong, Shaojun; Wang, Erkang

    2011-08-23

    A novel kind of versatile logic device has been constructed utilizing ion-tuned DNA/Ag fluorescent nanoclusters, with K(+) and H(+) as two inputs. A well-chosen hairpin DNA with a poly-C loop serves as the template for synthesizing two species of Ag nanoclusters. Several G-tracts and C-tracts on its two terminals enable the hairpin DNA to convert into the G-quadruplex and/or i-motif structures upon input of K(+) and H(+). Such a structural change remarkably influences the spectral behaviors of Ag nanoclusters. In particular, different species of Ag nanoclusters have distinct fluorescence responses to the input of K(+) and H(+). These unique features of DNA/Ag nanoclusters enable multiple logic operations via multichannel fluorescence output, indicating the versatility as a molecular logic device. By altering the specific sequence of the hairpin DNA, more logic gates can be constructed utilizing Ag nanoclusters.

  9. RSFQ logic devices; non-linear properties and experimental investigations

    NASA Astrophysics Data System (ADS)

    Mygind, Jesper

    1998-05-01

    Rapid Single Flux Quantum (RSFQ) logic has a great potential as fast digital and high frequency analog electronics. Several Logic/Memory base elements and integrated sub-systems in the RSFQ family have been devised and tested since the pioneering work in the mid 1980s by K. K. Likharev's group at Moscow State University [1,2]. It is argumented why the RSFQ digital circuits are superior to the voltage state family circuits, which were utilised in the first development of Josephson logic. Also the parameter space for operation of the 1-D RSFQ transmission line is discussed. Presently most RSFQ circuits are made with low-Tc superconductors using the now mature whole-wafer NbAlOxNb technology, which allows for large and densely packed integrated circuits. Recently, a few operational high-Tc RSFQ circuits have been reported. An important development within the last two years is the advent of general-purpose on-chip bit-by-bit verification test systems. Timing of RSFQ circuits and a few recent RSFQ "highlights" are briefly mentioned. Basically the RSFQ technology appears "ready" for widespread industrial use. One of the key components is the RSFQ transmission line, which can both generate and transmit SFQ pulses. In order to demonstrate the importance of the fluxon dynamics we discuss a new phenomenon observed in a parallel array of identical junctions. Steps with extremely low differential resistance in the I-V characteristic are found to be due to the self-induced magnetic field produced by the edge current fed to the array. The underlying mechanism is that the nonuniform field divides the moving fluxon into "domains" covering several (unit) cells. The experimental/numerical results illustrate practical and may be more fundamental limits to RSFQ electronics.

  10. A programmable nanoreplica molding for the fabrication of nanophotonic devices

    NASA Astrophysics Data System (ADS)

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-Min; Lu, Meng

    2016-03-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively.

  11. A programmable nanoreplica molding for the fabrication of nanophotonic devices

    PubMed Central

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-min; Lu, Meng

    2016-01-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively. PMID:26925828

  12. The spatial and logical organization of devices in an advanced industrial robot system

    NASA Technical Reports Server (NTRS)

    Ruoff, C. F.

    1980-01-01

    This paper describes the geometrical and device organization of a robot system which is based in part upon transformations of Cartesian frames and exchangeable device tree structures. It discusses coordinate frame transformations, geometrical device representation and solution degeneracy along with the data structures which support the exchangeable logical-physical device assignments. The system, which has been implemented in a minicomputer, supports vision, force, and other sensors. It allows tasks to be instantiated with logically equivalent devices and it allows tasks to be defined relative to appropriate frames. Since these frames are, in turn, defined relative other frames this organization provides a significant simplification in task specification and a high degree of system modularity.

  13. Cellular Signaling Circuits Interfaced with Synthetic, Post-Translational, Negating Boolean Logic Devices

    PubMed Central

    2014-01-01

    A negating functionality is fundamental to information processing of logic circuits within cells and computers. Aiming to adapt unutilized electronic concepts to the interrogation of signaling circuits in cells, we first took a bottom-up strategy whereby we created protein-based devices that perform negating Boolean logic operations such as NOT, NOR, NAND, and N-IMPLY. These devices function in living cells within a minute by precisely commanding the localization of an activator molecule among three subcellular spaces. We networked these synthetic gates to an endogenous signaling circuit and devised a physiological output. In search of logic functions in signal transduction, we next took a top–down approach and computationally screened 108 signaling pathways to identify commonalities and differences between these biological pathways and electronic circuits. This combination of synthetic and systems approaches will guide us in developing foundations for deconstruction of intricate cell signaling, as well as construction of biomolecular computers. PMID:25000210

  14. CAMAC modular programmable function generator

    SciTech Connect

    Turner, G.W.; Suehiro, S.; Hendricks, R.W.

    1980-12-01

    A CAMAC modular programmable function generator has been developed. The device contains a 1024 word by 12-bit memory, a 12-bit digital-to-analog converter with a 600 ns settling time, an 18-bit programmable frequency register, and two programmable trigger output registers. The trigger registers can produce programmed output logic transitions at various (binary) points in the output function curve, and are used to synchronize various other data acquisition devices with the function curve.

  15. Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic.

    PubMed

    Shim, Jaewoo; Oh, Seyong; Kang, Dong-Ho; Jo, Seo-Hyeon; Ali, Muhammad Hasnain; Choi, Woo-Young; Heo, Keun; Jeon, Jaeho; Lee, Sungjoo; Kim, Minwoo; Song, Young Jae; Park, Jin-Hong

    2016-11-07

    Recently, negative differential resistance devices have attracted considerable attention due to their folded current-voltage characteristic, which presents multiple threshold voltage values. Because of this remarkable property, studies associated with the negative differential resistance devices have been explored for realizing multi-valued logic applications. Here we demonstrate a negative differential resistance device based on a phosphorene/rhenium disulfide (BP/ReS2) heterojunction that is formed by type-III broken-gap band alignment, showing high peak-to-valley current ratio values of 4.2 and 6.9 at room temperature and 180 K, respectively. Also, the carrier transport mechanism of the BP/ReS2 negative differential resistance device is investigated in detail by analysing the tunnelling and diffusion currents at various temperatures with the proposed analytic negative differential resistance device model. Finally, we demonstrate a ternary inverter as a multi-valued logic application. This study of a two-dimensional material heterojunction is a step forward toward future multi-valued logic device research.

  16. Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic

    PubMed Central

    Shim, Jaewoo; Oh, Seyong; Kang, Dong-Ho; Jo, Seo-Hyeon; Ali, Muhammad Hasnain; Choi, Woo-Young; Heo, Keun; Jeon, Jaeho; Lee, Sungjoo; Kim, Minwoo; Song, Young Jae; Park, Jin-Hong

    2016-01-01

    Recently, negative differential resistance devices have attracted considerable attention due to their folded current–voltage characteristic, which presents multiple threshold voltage values. Because of this remarkable property, studies associated with the negative differential resistance devices have been explored for realizing multi-valued logic applications. Here we demonstrate a negative differential resistance device based on a phosphorene/rhenium disulfide (BP/ReS2) heterojunction that is formed by type-III broken-gap band alignment, showing high peak-to-valley current ratio values of 4.2 and 6.9 at room temperature and 180 K, respectively. Also, the carrier transport mechanism of the BP/ReS2 negative differential resistance device is investigated in detail by analysing the tunnelling and diffusion currents at various temperatures with the proposed analytic negative differential resistance device model. Finally, we demonstrate a ternary inverter as a multi-valued logic application. This study of a two-dimensional material heterojunction is a step forward toward future multi-valued logic device research. PMID:27819264

  17. SLS complementary logic devices with increase carrier mobility

    DOEpatents

    Chaffin, Roger J.; Osbourn, Gordon C.; Zipperian, Thomas E.

    1991-01-01

    In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.

  18. SLS complementary logic devices with increase carrier mobility

    DOEpatents

    Chaffin, R.J.; Osbourn, G.C.; Zipperian, T.E.

    1991-07-09

    In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated. 5 figures.

  19. Programmable Potentials: Approximate N-body potentials from coarse-level logic

    PubMed Central

    Thakur, Gunjan S.; Mohr, Ryan; Mezić, Igor

    2016-01-01

    This paper gives a systematic method for constructing an N-body potential, approximating the true potential, that accurately captures meso-scale behavior of the chemical or biological system using pairwise potentials coming from experimental data or ab initio methods. The meso-scale behavior is translated into logic rules for the dynamics. Each pairwise potential has an associated logic function that is constructed using the logic rules, a class of elementary logic functions, and AND, OR, and NOT gates. The effect of each logic function is to turn its associated potential on and off. The N-body potential is constructed as linear combination of the pairwise potentials, where the “coefficients” of the potentials are smoothed versions of the associated logic functions. These potentials allow a potentially low-dimensional description of complex processes while still accurately capturing the relevant physics at the meso-scale. We present the proposed formalism to construct coarse-grained potential models for three examples: an inhibitor molecular system, bond breaking in chemical reactions, and DNA transcription from biology. The method can potentially be used in reverse for design of molecular processes by specifying properties of molecules that can carry them out. PMID:27671683

  20. Programmable Potentials: Approximate N-body potentials from coarse-level logic

    NASA Astrophysics Data System (ADS)

    Thakur, Gunjan S.; Mohr, Ryan; Mezić, Igor

    2016-09-01

    This paper gives a systematic method for constructing an N-body potential, approximating the true potential, that accurately captures meso-scale behavior of the chemical or biological system using pairwise potentials coming from experimental data or ab initio methods. The meso-scale behavior is translated into logic rules for the dynamics. Each pairwise potential has an associated logic function that is constructed using the logic rules, a class of elementary logic functions, and AND, OR, and NOT gates. The effect of each logic function is to turn its associated potential on and off. The N-body potential is constructed as linear combination of the pairwise potentials, where the “coefficients” of the potentials are smoothed versions of the associated logic functions. These potentials allow a potentially low-dimensional description of complex processes while still accurately capturing the relevant physics at the meso-scale. We present the proposed formalism to construct coarse-grained potential models for three examples: an inhibitor molecular system, bond breaking in chemical reactions, and DNA transcription from biology. The method can potentially be used in reverse for design of molecular processes by specifying properties of molecules that can carry them out.

  1. Structured approach in PLC (programmable logic controller) programming for water/wastewater applications.

    PubMed

    Keskar, P Y

    1990-01-01

    This paper describes a methodology for efficient implementation of PLC programming for water/wastewater applications. The PLC was interfaced with a supervisory host computer which used touch screen equipped color monitors as operator interfaces. PLC ladder logic had to be designed to process real-world hardwired I/O as well as the I/O received from the host computer and/or touch screens, via a communications link. Standard "templates" of PLC networks were developed for (a) pump controls including provision for touch screen I/O; (b) PID control; (c) alarms; (d) motor run times; (e) square root extraction; (f) signal conversion, and (g) flow totalization. All logic was implemented using the standard templates. This structured approach led to efficient implementation, easy debugging/start-up, and easy to read uniform ladder logic.

  2. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    NASA Technical Reports Server (NTRS)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  3. Biofuel cell controlled by enzyme logic network--approaching physiologically regulated devices.

    PubMed

    Tam, Tsz Kin; Pita, Marcos; Ornatska, Maryna; Katz, Evgeny

    2009-09-01

    A "smart" biofuel cell switchable ON and OFF upon application of several chemical signals processed by an enzyme logic network was designed. The biocomputing system performing logic operations on the input signals was composed of four enzymes: alcohol dehydrogenase (ADH), amyloglucosidase (AGS), invertase (INV) and glucose dehydrogenase (GDH). These enzymes were activated by different combinations of chemical input signals: NADH, acetaldehyde, maltose and sucrose. The sequence of biochemical reactions catalyzed by the enzymes models a logic network composed of concatenated AND/OR gates. Upon application of specific "successful" patterns of the chemical input signals, the cascade of biochemical reactions resulted in the formation of gluconic acid, thus producing acidic pH in the solution. This resulted in the activation of a pH-sensitive redox-polymer-modified cathode in the biofuel cell, thus, switching ON the entire cell and dramatically increasing its power output. Application of another chemical signal (urea in the presence of urease) resulted in the return to the initial neutral pH value, when the O(2)-reducing cathode and the entire cell are in the mute state. The reversible activation-inactivation of the biofuel cell was controlled by the enzymatic reactions logically processing a number of chemical input signals applied in different combinations. The studied biofuel cell exemplifies a new kind of bioelectronic device where the bioelectronic function is controlled by a biocomputing system. Such devices will provide a new dimension in bioelectronics and biocomputing benefiting from the integration of both concepts.

  4. All-optical compact surface plasmonic two-mode interference device for optical logic gate operation.

    PubMed

    Gogoi, Nilima; Sahu, Partha Pratim

    2015-02-10

    In this paper, we have proposed an ultra-compact surface plasmonic two-mode interference (SPTMI) coupler having a silicon core, silver upper and lower cladding, and GaAsInP left and right cladding for basic logic gate operations. By modulating the refractive index of the GaAsInP cladding with incidence of optical pulse energy, we have shown coupling characteristics depending on additional phase change ΔΦ(E) between the excited surface plasmon polariton modes propagating through the silicon core. By using applied optical pulse dependent coupling behavior of the proposed SPTMI device, the operations of NOT, AND, and OR logic gates are shown. It is also seen that the coupling length of the proposed device is 32.3 times more compact than that of a multimode interference-directional coupler.

  5. Remote Control Laboratory Using EJS Applets and TwinCAT Programmable Logic Controllers

    ERIC Educational Resources Information Center

    Besada-Portas, E.; Lopez-Orozco, J. A.; de la Torre, L.; de la Cruz, J. M.

    2013-01-01

    This paper presents a new methodology to develop remote laboratories for systems engineering and automation control courses, based on the combined use of TwinCAT, a laboratory Java server application, and Easy Java Simulations (EJS). The TwinCAT system is used to close the control loop for the selected plants by means of programmable logic…

  6. Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

    NASA Astrophysics Data System (ADS)

    Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

    2015-02-01

    A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer,a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

  7. A novel design-based global CDU metrology for 1X nm node logic devices

    NASA Astrophysics Data System (ADS)

    Yoon, Young-Keun; Chung, Dong H.; Kim, Min-Ho; Seo, Jung-Uk; Kim, Byung-Gook; Jeon, Chan-Uk; Hur, JiUk; Cho, Wonil; Yamamoto, Tetsuya

    2013-09-01

    As dimension of device shrinks to 1X nm node, an extreme control of critical dimension uniformity (CDU) of masks becomes one of key techniques for mask and wafer fabrication. For memory devices, a large number of optical techniques have been studied and applied to mask production so far. The advantages of these methods are to eliminate the sampling dependency due to their high throughput, to minimize the local CD errors due to their large field of view (FOV) and to improve the correlation with wafer infield uniformity if they have scanner-like optics. For logic devices, however, CD-SEM has been a single solution to characterize CD performance of logic masks for a long time and simple monitoring patterns, instead of the cell patterns, have been measured to monitor the CD quality of masks. Therefore a global CDU of the mask tends to show its ambiguity because of the limited number of measurement sites and large local CD errors. An application of optical metrology for logic mask is a challenging task because patterns are more complex and random in shape and because there is no guarantee of finding patterns for CDU everywhere on the mask. CDU map still consists of the results from the indirect measurements and the traditional definition of uniformity, a statistical deviation of a typical pattern, seems to be unsuitable for logic CDU. A new definition of CDU is required in order to maximize the coverage area on a mask. In this study, we have focused of the possibility of measuring cell patterns and of using an inspection tool with data base handling capability, KLA Teron617, to find the areas and positions where the repeating patterns exist and the patterns which satisfy a certain set of condition and we have devised a new definition of CDU, which can handle multiple target CDs. Then we have checked the feasibility and validity of our new methodology through evaluation its fundamental performance such as accuracy, repeatability, and correlation with other CD metrology

  8. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    SciTech Connect

    Mitra, Kalyan Yoti E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-17

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  9. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    NASA Astrophysics Data System (ADS)

    Mitra, Kalyan Yoti; Sowade, Enrico; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-01

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  10. Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews

    PubMed Central

    Kneale, Dylan; Thomas, James; Harris, Katherine

    2015-01-01

    Background Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to ‘think’ conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. Methods and Findings In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Conclusions Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions. PMID:26575182

  11. Quantum logical gates with four-level superconducting quantum interference devices coupled to a superconducting resonator

    SciTech Connect

    He Xiaoling; Luo Junyan; Yang Chuiping; Li Sheng; Han Siyuan

    2010-08-15

    We propose a way for realizing a two-qubit controlled phase gate with superconducting quantum interference devices (SQUIDs) coupled to a superconducting resonator. In this proposal, the two lowest levels of each SQUID serve as the logical states and two intermediate levels of each SQUID are used for the gate realization. We show that neither adjustment of SQUID level spacings during the gate operation nor uniformity in SQUID parameters is required by this proposal. In addition, this proposal does not require the adiabatic passage or a second-order detuning and thus the gate is much faster.

  12. [Left ventricle assist device: rehabilitation and management programmes].

    PubMed

    D'agrosa-Boiteux, M-C; Geoffroy, E; Dauphin, N; Camilleri, L; Eschalier, R; Cuenin, C; Moisa, A

    2014-09-01

    Progress in the medical management of patients with heart failure with systolic dysfunction has been accompanied by a significant improvement in survival and quality of life. These strategies have also resulted in changes in the clinical profile as well as an increase in the number of patients with advanced heart failure. The technological developments in left ventricular assist devices provide real hope for these patients. This article related our experience of management and the rehabilitation program realized.

  13. Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

    PubMed

    Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

    2015-05-26

    Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

  14. Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes

    NASA Astrophysics Data System (ADS)

    Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Patil, Nishant; Lin, Albert; Mitra, Subhasish; Wong, H.-S. Philip; Zhou, Chongwu

    2008-07-01

    In this paper, high-performance back-gated carbon nanotube field-effect transistors based on transferred aligned carbon nanotubes were fabricated and studies found that the on/off ratio can reach 107 and the current density can reach 1.6μA/μm after electrical breakdown. In addition, chemical doping with hydrazine was used to convert the p-type aligned nanotube devices into n-type. These devices were further utilized to demonstrate various logic circuits, including p-type metal-oxide-semiconductor inverters, diode-loaded inverters, complementary metal-oxide-semiconductor inverters, NAND, and NOR gates. This approach could work as the platform for future nanotube-based nanoelectronics.

  15. Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

    NASA Technical Reports Server (NTRS)

    Taylor, B.

    1990-01-01

    The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

  16. High-frequency programmable acoustic wave device realized through ferroelectric domain engineering

    NASA Astrophysics Data System (ADS)

    Ivry, Yachin; Wang, Nan; Durkan, Colm

    2014-03-01

    Surface acoustic wave devices are extensively used in contemporary wireless communication devices. We used atomic force microscopy to form periodic macroscopic ferroelectric domains in sol-gel deposited lead zirconate titanate, where each ferroelectric domain is composed of many crystallites, each of which contains many microscopic ferroelastic domains. We examined the electro-acoustic characteristics of the apparatus and found a resonator behavior similar to that of an equivalent surface or bulk acoustic wave device. We show that the operational frequency of the device can be tailored by altering the periodicity of the engineered domains and demonstrate high-frequency filter behavior (>8 GHz), allowing low-cost programmable high-frequency resonators.

  17. The use of programmable logic controllers (PLC) for rocket engine component testing

    NASA Technical Reports Server (NTRS)

    Nail, William; Scheuermann, Patrick; Witcher, Kern

    1991-01-01

    Application of PLCs to the rocket engine component testing at a new Stennis Space Center Component Test Facility is suggested as an alternative to dedicated specialized computers. The PLC systems are characterized by rugged design, intuitive software, fault tolerance, flexibility, multiple end device options, networking capability, and built-in diagnostics. A distributed PLC-based system is projected to be used for testing LH2/LOx turbopumps required for the ALS/NLS rocket engines.

  18. A programmable and portable NMES device for drop foot correction and blood flow assist applications.

    PubMed

    Breen, Paul P; Corley, Gavin J; O'Keeffe, Derek T; Conway, Richard; Olaighin, Gearóid

    2009-04-01

    The Duo-STIM, a new, programmable and portable neuromuscular stimulation system for drop foot correction and blood flow assist applications is presented. The system consists of a programmer unit and a portable, programmable stimulator unit. The portable stimulator features fully programmable, sensor-controlled, constant-voltage, dual-channel stimulation and accommodates a range of customized stimulation profiles. Trapezoidal and free-form adaptive stimulation intensity envelope algorithms are provided for drop foot correction applications, while time dependent and activity dependent algorithms are provided for blood flow assist applications. A variety of sensor types can be used with the portable unit, including force sensitive resistor-based foot switches and MEMS-based accelerometer and gyroscope devices. The paper provides a detailed description of the hardware and block-level system design for both units. The programming and operating procedures for the system are also presented. Finally, functional bench test results for the system are presented.

  19. On the Spot: Using Mobile Devices for Listening and Speaking Practice on a French Language Programme

    ERIC Educational Resources Information Center

    Demouy, Valerie; Kukulska-Hulme, Agnes

    2010-01-01

    This paper presents and discusses the initial findings of a mobile language learning project undertaken in the context of an undergraduate distance-learning French language programme at The Open University (UK). The overall objective of the project was to investigate students' experiences when using their own portable devices for additional…

  20. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    DOE PAGES

    Gao, X.; Mamaluy, D.; Cyr, E. C.; ...

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

  1. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    SciTech Connect

    Gao, X.; Mamaluy, D.; Cyr, E. C.; Marinella, M. J.

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device is determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.

  2. Design and theoretical investigation of a silicon-on-insulator based electro-optical logic gate device

    NASA Astrophysics Data System (ADS)

    Li, Lei; Qi, Zhipeng; Hu, Guohua; Yun, Binfeng; Zhong, Yuan; Cui, Yiping

    2016-10-01

    A compact electro-optical "NOR" logic gate device based on silicon-on-insulator (SOI) platform is proposed and investigated theoretically. By introducing a hook-type waveguide, the signal could be coupled between the bus and hook-type waveguide to form an optical circuit and realize NOR logic gate. We can easily realize the NOR logical function by the voltage applied on the coupling components. The numerical simulation shows that a high coupling efficiency of more than 99% is obtained at the wavelength of 1550 nm, and the footprint of our device is smaller than 90 μm2. In addition, the response time of the proposed NOR logic gate is 3 ns with a switching voltage of 1.8 V. Moreover, it is demonstrated that such NOR logic gate device could obtain an extinction ratio of 21.8 dB. Thus, it has great potential to achieve high speed response, low power consumption, and small footprint, which fulfill the demands of next-generation on-chip computer multiplex processors.

  3. Automated hotspot analysis with aerial image CD metrology for advanced logic devices

    NASA Astrophysics Data System (ADS)

    Buttgereit, Ute; Trautzsch, Thomas; Kim, Min-ho; Seo, Jung-Uk; Yoon, Young-Keun; Han, Hak-Seung; Chung, Dong Hoon; Jeon, Chan-Uk; Meyers, Gary

    2014-09-01

    Continuously shrinking designs by further extension of 193nm technology lead to a much higher probability of hotspots especially for the manufacturing of advanced logic devices. The CD of these potential hotspots needs to be precisely controlled and measured on the mask. On top of that, the feature complexity increases due to high OPC load in the logic mask design which is an additional challenge for CD metrology. Therefore the hotspot measurements have been performed on WLCD from ZEISS, which provides the benefit of reduced complexity by measuring the CD in the aerial image and qualifying the printing relevant CD. This is especially of advantage for complex 2D feature measurements. Additionally, the data preparation for CD measurement becomes more critical due to the larger amount of CD measurements and the increasing feature diversity. For the data preparation this means to identify these hotspots and mark them automatically with the correct marker required to make the feature specific CD measurement successful. Currently available methods can address generic pattern but cannot deal with the pattern diversity of the hotspots. The paper will explore a method how to overcome those limitations and to enhance the time-to-result in the marking process dramatically. For the marking process the Synopsys WLCD Output Module was utilized, which is an interface between the CATS mask data prep software and the WLCD metrology tool. It translates the CATS marking directly into an executable WLCD measurement job including CD analysis. The paper will describe the utilized method and flow for the hotspot measurement. Additionally, the achieved results on hotspot measurements utilizing this method will be presented.

  4. Development and Validation of a Miniature Programmable tDCS Device.

    PubMed

    Kouzani, Abbas Z; Jaberzadeh, Shapour; Zoghi, Maryam; Usma, Clara; Parastarfeizabadi, Mahboubeh

    2016-01-01

    Research is being conducted on the use of transcranial direct current stimulation (tDCS) for therapeutic effects, and also on the mechanisms through which such therapeutic effects are mediated. A bottleneck in the progress of the research has been the large size of the existing tDCS systems which prevents subjects from performing their daily activities. To help research into the principles, mechanisms, and benefits of tDCS, reduction of size and weight, improvement in simplicity and user friendliness, portability, and programmability of tDCS systems are vital. This paper presents a design for a low-cost, light-weight, programmable, and portable tDCS device. The device is head-mountable and can be concealed in a hat and worn on the head by the subject while receiving the stimulation. The strength of the direct current stimulation can be selected through a simple user interface. The device is constructed and its performance evaluated through bench and in vivo tests. The tests validated the operation of the device in inducing neuromodulatory changes in primary motor cortex, M1, through measuring excitability of dominant M1 of resting right first dorsal interosseus muscle by transcranial magnetic stimulation induced motor evoked potentials. It was observed that the tDCS device induced comparable neuromodulatory effects in M1 as the existing bulky tDCS systems.

  5. High-frequency programmable acoustic wave device realized through ferroelectric domain engineering

    SciTech Connect

    Ivry, Yachin E-mail: cd229@eng.cam.ac.uk; Wang, Nan; Durkan, Colm E-mail: cd229@eng.cam.ac.uk

    2014-03-31

    Surface acoustic wave devices are extensively used in contemporary wireless communication devices. We used atomic force microscopy to form periodic macroscopic ferroelectric domains in sol-gel deposited lead zirconate titanate, where each ferroelectric domain is composed of many crystallites, each of which contains many microscopic ferroelastic domains. We examined the electro-acoustic characteristics of the apparatus and found a resonator behavior similar to that of an equivalent surface or bulk acoustic wave device. We show that the operational frequency of the device can be tailored by altering the periodicity of the engineered domains and demonstrate high-frequency filter behavior (>8 GHz), allowing low-cost programmable high-frequency resonators.

  6. Automated hot-spot fixing system applied for metal layers of 65 nm logic devices

    NASA Astrophysics Data System (ADS)

    Kobayashi, Sachiko; Kyoh, Suigen; Kotani, Toshiya; Tanaka, Satoshi; Inoue, Soichi

    2006-05-01

    Hot spot clearance using process simulation is indispensable under low-k1 lithography process for logic devices of 65 nm and below. Hot spots such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Appropriate calibration of design rule (DR), mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of design at hot spot will be effective, but it takes too much time to determine how to modify layout to be consistent with DR, MDP/OPC rule, and the process often needs to be iterative. Therefore, there is a need for an automated hot spot fixing system is capable of fixing design layout so as to avoid fatal hot spot occurrence, with sufficient process margin and short turn around time (TAT). We developed an automated hot-spot fixing system, Hot Spot Fixer (HSF). The basic system flow in the developed system is as follows; Design data is processed with the conventional mask data preparation process. Then, process simulation is performed to extract hot spots. The hot spots are categorized by lithography error mode, critical level, and surrounding context. An intelligent hot-spot modification instructor, taking the surrounding situation into consideration, generates modification guide for the every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. If necessary, several modification candidates are indicated and the user can choose the most adequate one from them. The design modification process is verified from every aspect, using Design Rule Checker (DRC) and process simulation. The modified design data, with reduced potential hot spot compared with pre

  7. Shot number analysis on character projection e-beam lithography for random logic device fabrication at 70-nm node

    NASA Astrophysics Data System (ADS)

    Tomo, Yoichi; Shimizu, Isao; Kojima, Yoshinori; Yoshida, Akira; Takenaka, Hiroshi; Yamabe, Masaki

    2001-08-01

    A reduction efficiency of shot numbers in character projection (CP) electron-beam (EB) lithography with memory device application depends on a design rule (cell size) and a pattern complexity within a memory cell. Many researchers reported that it was approximately 1/10 to 1/100 compared with conventional variable-shaped beam (VSB) method. The reduction of shot numbers in memory devices mainly comes from allowance to place multiple cells in one CP-cell area and simplicity of the cell's placement (regular pitch with adjacent allocation). On the other hand, there are few reports concerning reduction efficiency of shot numbers with logic specific application in CP EB lithography due to the complexity of logic cell's allocation to CP-cell area. To analyze this, logic device layout data in 70nm node was prepared by shringking actual functional device data of 350 nm node in the ratio of 1/5 and extracting random logic region. The size of this region was 1,094 x 283 micrometers . The height of logic cell was 2.64micrometers and it was smaller than typical one CP-cell size in second aperture (5 x 5micrometers ). The pattern data in GDS-II stream format was converted into EB exposure data: divided figures (rectangles). By this procedure, numbers of figures and cells were obtained. The total number of referred logic cell was 26,812. Among 26,812 cells, only 111 common (unique) logic cells were used for the logic region. The sum of figures in gate layer was 412,251 and this value was assumed to be equal to a total number of shots in conventional VSB method. Among the 111 common cells, only 6 cells in the gate layer showed width more than 5micrometers (maximum CP-cell size). Most frequently referred cell was an inverter and the number of reference was 5,395. The referred frequency of each cell exponentially decreased when the cells were arranged in descending order of reference. Among the total figures, top cell showed 66,120 accumulated number of figures (referred number=2

  8. The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

    SciTech Connect

    Hu, Jiaxi; Haratipour, Nazila; Koester, Steven J.

    2015-05-07

    All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare the effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau–Lifshitz–Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.

  9. Reliability concerns with logical constants in Xilinx FPGA designs

    SciTech Connect

    Quinn, Heather M; Graham, Paul; Morgan, Keith; Ostler, Patrick; Allen, Greg; Swift, Gary; Tseng, Chen W

    2009-01-01

    In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.

  10. Generation-3 programmable array microscope (PAM) with digital micro-mirror device (DMD)

    NASA Astrophysics Data System (ADS)

    De Beule, Pieter A. A.; de Vries, Anthony H. B.; Arndt-Jovin, Donna J.; Jovin, Thomas M.

    2011-03-01

    We report progress on the construction of an optical sectioning programmable array microscope (PAM) implemented with a digital micro-mirror device (DMD) spatial light modulator (SLM) utilized for both fluorescence illumination and detection. The introduction of binary intensity modulation at the focal plane of a microscope objective in a computer controlled pixilated mode allows the recovery of an optically sectioned image. Illumination patterns can be changed very quickly, in contrast to static Nipkow disk or aperture correlation implementations, thereby creating an optical system that can be optimized to the optical specimen in a convenient manner, e.g. for patterned photobleaching, photobleaching reduction, or spatial superresolution. We present a third generation (Gen-3) dual path PAM module incorporating the 25 kHz binary frame rate TI 1080p DMD and a newly developed optical system that offers diffraction limited imaging with compensation of tilt angle distortion.

  11. Programmable immersive peripheral environmental system (PIPES): a prototype control system for environmental feedback devices

    NASA Astrophysics Data System (ADS)

    Frend, Chauncey; Boyles, Michael

    2015-03-01

    This paper describes an environmental feedback device (EFD) control system aimed at simplifying the VR development cycle. Programmable Immersive Peripheral Environmental System (PIPES) affords VR developers a custom approach to programming and controlling EFD behaviors while relaxing the required knowledge and expertise of electronic systems. PIPES has been implemented for the Unity engine and features EFD control using the Arduino integrated development environment. PIPES was installed and tested on two VR systems, a large format CAVE system and an Oculus Rift HMD system. A photocell based end-to-end latency experiment was conducted to measure latency within the system. This work extends previously unpublished prototypes of a similar design. Development and experiments described in this paper are part of the VR community goal to understand and apply environment effects to VEs that ultimately add to users' perceived presence.

  12. Optical logic and signal processing using a semiconductor laser diode-based optical bistability device

    NASA Astrophysics Data System (ADS)

    Zhang, Yuancheng; Song, Qian; He, Shaowei

    1995-02-01

    Using an optical fibre-coupled semiconductor laser diode OBD with output feedback pumping operation in 5 modes (differential gain, bistability, zero-bias, inverted differential gain, and inverted bistability) has been realized respectively, and 5 elementary optical logic functions (AND, OR, NOT, NAND, and NOR) and some optical signal processing such as limiting, reshaping, and triggering have been implemented.

  13. THRESHOLD LOGIC IN ARTIFICIAL INTELLIGENCE

    DTIC Science & Technology

    COMPUTER LOGIC, ARTIFICIAL INTELLIGENCE , BIONICS, GEOMETRY, INPUT OUTPUT DEVICES, LINEAR PROGRAMMING, MATHEMATICAL LOGIC, MATHEMATICAL PREDICTION, NETWORKS, PATTERN RECOGNITION, PROBABILITY, SWITCHING CIRCUITS, SYNTHESIS

  14. Customizable 3D Printed ‘Plug and Play’ Millifluidic Devices for Programmable Fluidics

    PubMed Central

    Tsuda, Soichiro; Jaffery, Hussain; Doran, David; Hezwani, Mohammad; Robbins, Phillip J.; Yoshida, Mari; Cronin, Leroy

    2015-01-01

    Three dimensional (3D) printing is actively sought after in recent years as a promising novel technology to construct complex objects, which scope spans from nano- to over millimeter scale. Previously we utilized Fused deposition modeling (FDM)-based 3D printer to construct complex 3D chemical fluidic systems, and here we demonstrate the construction of 3D milli-fluidic structures for programmable liquid handling and control of biological samples. Basic fluidic operation devices, such as water-in-oil (W/O) droplet generators for producing compartmentalized mono-disperse droplets, sensor-integrated chamber for online monitoring of cellular growth, are presented. In addition, chemical surface treatment techniques are used to construct valve-based flow selector for liquid flow control and inter-connectable modular devices for networking fluidic parts. As such this work paves the way for complex operations, such as mixing, flow control, and monitoring of reaction / cell culture progress can be carried out by constructing both passive and active components in 3D printed structures, which designs can be shared online so that anyone with 3D printers can reproduce them by themselves. PMID:26558389

  15. Customizable 3D Printed 'Plug and Play' Millifluidic Devices for Programmable Fluidics.

    PubMed

    Tsuda, Soichiro; Jaffery, Hussain; Doran, David; Hezwani, Mohammad; Robbins, Phillip J; Yoshida, Mari; Cronin, Leroy

    2015-01-01

    Three dimensional (3D) printing is actively sought after in recent years as a promising novel technology to construct complex objects, which scope spans from nano- to over millimeter scale. Previously we utilized Fused deposition modeling (FDM)-based 3D printer to construct complex 3D chemical fluidic systems, and here we demonstrate the construction of 3D milli-fluidic structures for programmable liquid handling and control of biological samples. Basic fluidic operation devices, such as water-in-oil (W/O) droplet generators for producing compartmentalized mono-disperse droplets, sensor-integrated chamber for online monitoring of cellular growth, are presented. In addition, chemical surface treatment techniques are used to construct valve-based flow selector for liquid flow control and inter-connectable modular devices for networking fluidic parts. As such this work paves the way for complex operations, such as mixing, flow control, and monitoring of reaction / cell culture progress can be carried out by constructing both passive and active components in 3D printed structures, which designs can be shared online so that anyone with 3D printers can reproduce them by themselves.

  16. Molecular implementation of simple logic programs

    NASA Astrophysics Data System (ADS)

    Ran, Tom; Kaplan, Shai; Shapiro, Ehud

    2009-11-01

    Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) <-- Man(X) (Every Man is Mortal), the system can answer molecular queries such as Mortal(Socrates)? (Is Socrates Mortal?) and Mortal(X)? (Who is Mortal?). This biomolecular computing system compares favourably with previous approaches in terms of expressive power, performance and precision. A compiler translates facts, rules and queries into their molecular representations and subsequently operates a robotic system that assembles the logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

  17. Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

    NASA Astrophysics Data System (ADS)

    Roy, Debapriya; Biswas, Abhijit

    2016-09-01

    Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4-0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of ION by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.

  18. Sensor sentinel computing device

    DOEpatents

    Damico, Joseph P.

    2016-08-02

    Technologies pertaining to authenticating data output by sensors in an industrial environment are described herein. A sensor sentinel computing device receives time-series data from a sensor by way of a wireline connection. The sensor sentinel computing device generates a validation signal that is a function of the time-series signal. The sensor sentinel computing device then transmits the validation signal to a programmable logic controller in the industrial environment.

  19. Polymer-based electrochemical devices for logic functions and paper displays

    NASA Astrophysics Data System (ADS)

    Berggren, Magnus; Nilsson, David; Chen, Miaoxiang; Andersson, Peter; Kugler, Thomas; Malmstroem, Anna; Haell, Jessica; Remonen, Tommi; Robinson, Nathaniel D.

    2003-07-01

    Here, we report on devices based on patterned thin films of the conducting polymer system poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulphonic acid) (PEDOT:PSS) combined with patterns of solid electrolyte. The key device functionalities base on the updating of the RedOx state of PEDOT. This results in control of the electronic properties of this conjugated polymer, i.e. the conductivity and optical properties are updated. Based on this we have achieved electric current rectifiers, transistors and display cells. Also, matrix addressed displays will be presented. Electrochemical switching is taking place when the oxidation and reduction potentials are overcome respectively. Therefore, these devices operate at voltage levels less then 2 Volts. Low voltage operation is achieved in devices not requiring any extremely narrow dimensions, as is the case for field effect driven devices. All devices reported can or has been made using standard printing techniques on flexible carriers.

  20. Nonvolatile, electrically erasable programmable ROM

    NASA Astrophysics Data System (ADS)

    El-Dessouky, A.

    1984-01-01

    The processing technology for integration of MNOS-EEPROMs and NMOS Logic was investigated as p-well isolation. Memory characteristics of both Si gate and metal gate MNOS devices are investigated for nitride constitution which aims for lower programming voltages and good memory performance. The complete fabrication process for 128 byte SNOS-EEPROM chip is described by using high voltage depletion MOS devices in p-well technology. Another test vehicle uses 4 x 4 metal gate MNOS array to demonstrate possible fabrication of 12 V programmable scaled MNOS devices with 10 years retention after 10 to the 5th power endurance.

  1. Programmable Pulser

    NASA Technical Reports Server (NTRS)

    Baumann, Eric; Merolla, Anthony

    1988-01-01

    User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

  2. A water pumping control system with a programmable logic controller (PLC) and industrial wireless modules for industrial plants--an experimental setup.

    PubMed

    Bayindir, Ramazan; Cetinceviz, Yucel

    2011-04-01

    This paper describes a water pumping control system that is designed for production plants and implemented in an experimental setup in a laboratory. These plants contain harsh environments in which chemicals, vibrations or moving parts exist that could potentially damage the cabling or wires that are part of the control system. Furthermore, the data has to be transferred over paths that are accessible to the public. The control systems that it uses are a programmable logic controller (PLC) and industrial wireless local area network (IWLAN) technologies. It is implemented by a PLC, an communication processor (CP), two IWLAN modules, and a distributed input/output (I/O) module, as well as the water pump and sensors. Our system communication is based on an Industrial Ethernet and uses the standard Transport Control Protocol/Internet Protocol for parameterisation, configuration and diagnostics. The main function of the PLC is to send a digital signal to the water pump to turn it on or off, based on the tank level, using a pressure transmitter and inputs from limit switches that indicate the level of the water in the tank. This paper aims to provide a convenient solution in process plants where cabling is not possible. It also has lower installation and maintenance cost, provides reliable operation, and robust and flexible construction, suitable for industrial applications.

  3. System and method for programmable bank selection for banked memory subsystems

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  4. Ferrite logic reliability study

    NASA Technical Reports Server (NTRS)

    Baer, J. A.; Clark, C. B.

    1973-01-01

    Development and use of digital circuits called all-magnetic logic are reported. In these circuits the magnetic elements and their windings comprise the active circuit devices in the logic portion of a system. The ferrite logic device belongs to the all-magnetic class of logic circuits. The FLO device is novel in that it makes use of a dual or bimaterial ferrite composition in one physical ceramic body. This bimaterial feature, coupled with its potential for relatively high speed operation, makes it attractive for high reliability applications. (Maximum speed of operation approximately 50 kHz.)

  5. Field Programmable Gate Array Hysteresis Control of Parallel Connected Inverters

    DTIC Science & Technology

    2006-06-01

    voltage with respect to time FPGA Field Programmable Gate Array GIC Generalized Impedance Converter GTO Gate-Turn-Off Transistors HDL...C. Figure 12 SEMIKRON PEBB [After Ref 13] G. FIELD PROGRAMMABLE GATE ARRAYS An FPGA is a generic semiconductor device containing a large... generate reference voltage and current waves for each of the three phases. The time to complete one logical operation inside the FPGA is a function of how

  6. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process

    PubMed Central

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-01-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency −70 cd A−1 under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices. PMID:27187936

  7. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process.

    PubMed

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-05-17

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency -70 cd A(-1) under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices.

  8. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process

    NASA Astrophysics Data System (ADS)

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-05-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency -70 cd A-1 under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices.

  9. Integrated all-optical logic and arithmetic operations with the help of a TOAD-based interferometer device--alternative approach.

    PubMed

    Roy, Jitendra Nath; Gayen, Dilip Kumar

    2007-08-01

    Interferometric devices have drawn a great interest in all-optical signal processing for their high-speed photonic activity. The nonlinear optical loop mirror provides a major support to optical switching based all-optical logic and algebraic operations. The gate based on the terahertz optical asymmetric demultiplexer (TOAD) has added new momentum in this field. Optical tree architecture (OTA) plays a significant role in the optical interconnecting network. We have tried to exploit the advantages of both OTA- and TOAD-based switches. We have proposed a TOAD-based tree architecture, a new and alternative scheme, for integrated all-optical logic and arithmetic operations.

  10. Integrated all-optical logic and arithmetic operations with the help of a TOAD-based interferometer device--alternative approach

    NASA Astrophysics Data System (ADS)

    Nath Roy, Jitendra; Gayen, Dilip Kumar

    2007-08-01

    Interferometric devices have drawn a great interest in all-optical signal processing for their high-speed photonic activity. The nonlinear optical loop mirror provides a major support to optical switching based all-optical logic and algebraic operations. The gate based on the terahertz optical asymmetric demultiplexer (TOAD) has added new momentum in this field. Optical tree architecture (OTA) plays a significant role in the optical interconnecting network. We have tried to exploit the advantages of both OTA- and TOAD-based switches. We have proposed a TOAD-based tree architecture, a new and alternative scheme, for integrated all-optical logic and arithmetic operations.

  11. Architecture and data processing alternatives for the TSE computer. Volume 3: Execution of a parallel counting algorithm using array logic (Tse) devices

    NASA Technical Reports Server (NTRS)

    Metcalfe, A. G.; Bodenheimer, R. E.

    1976-01-01

    A parallel algorithm for counting the number of logic-l elements in a binary array or image developed during preliminary investigation of the Tse concept is described. The counting algorithm is implemented using a basic combinational structure. Modifications which improve the efficiency of the basic structure are also presented. A programmable Tse computer structure is proposed, along with a hardware control unit, Tse instruction set, and software program for execution of the counting algorithm. Finally, a comparison is made between the different structures in terms of their more important characteristics.

  12. Field programmable gate arrays: Evaluation report for space-flight application

    NASA Technical Reports Server (NTRS)

    Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

    1992-01-01

    Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

  13. Label-free and enzyme-free platform for the construction of advanced DNA logic devices based on the assembly of graphene oxide and DNA-templated AgNCs

    NASA Astrophysics Data System (ADS)

    Fan, Daoqing; Zhu, Jinbo; Liu, Yaqing; Wang, Erkang; Dong, Shaojun

    2016-02-01

    DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator.DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator. Electronic supplementary information (ESI) available: Optimization experiments, Table S1, Fig. S1-S5 in ESI. See DOI: 10.1039/c6nr00032k

  14. Logic Programming in LISP.

    DTIC Science & Technology

    1981-01-01

    79/7, Imperial College, University of London. [Colmerauer 1973] Colmerauer, A., Un Systeme de Communication Homme - machine Kanoui, H., en Francais...any of the LOGIC interface functions (,-, THE, ALL, ANY, etc.) can be obtained by invoking the command (DOC fn), where "fn" is the name of the function...well as for output) illustrates one more way in which the LOGLISP programmer can fruitfully exploit the interface between LOGIC and LISP. GIVE is just a

  15. Digital Holographic Logic

    NASA Technical Reports Server (NTRS)

    Preston, K., Jr.

    1972-01-01

    The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.

  16. Distributed Logics

    DTIC Science & Technology

    2014-10-03

    introduce distributed logics. Distributed logics lift the distribution structure of a distributed system directly into the logic, thereby parameterizing...the logic by the distribution structure itself. Each domain supports a “local modal logic.” The connections between domains are realized as...There are also multi- agent logic systems [12]. What distinguishes distributed logics from these are that the morphisms, i.e., the nbd maps, have

  17. A programmable and configurable multi-port System-on-Chip for stimulating electrokinetically-driven microfluidic devices.

    PubMed

    Lopez, Martha Salome; Gerstlauer, Andreas; Avila, Alfonso; Martinez-Chapa, Sergio O

    2011-01-01

    Recent research has demonstrated the use of microfluidic devices and electro-kinetics in areas such as medicine, genetics, embryology, epidemiology and pollution analysis, where manipulation of particles suspended in liquid media is required. Micro-fabrication technology has made it possible to increase system complexity and functionality by allowing integration of different processing and analysis stages in a single chip. However, fully integrated and autonomous microfluidic systems supporting ad-hoc stimulation have yet to be developed. This paper presents a flexible, configurable and programmable stimulator for electro-kinetically driven microfluidic devices. The stimulator is a dedicated System-on-Chip (SoC) architecture that generates sine, triangle, and sawtooth signals within a frequency range of 1 Hz to 20 MHz, capable of delivering single, dual, and superimposed waveforms, in a user defined test sequence for a selected time period. The system is designed to be integrated into complete, autonomous Lab-on-Chip, portable or implantable devices. As such, it is expected to help significantly advance current and future research on particle manipulation.

  18. flexTMS--a novel repetitive transcranial magnetic stimulation device with freely programmable stimulus currents.

    PubMed

    Gattinger, Norbert; Moessnang, Georg; Gleich, Bernhard

    2012-07-01

    Transcranial magnetic stimulation (TMS) is able to noninvasively excite neuronal populations due to brief magnetic field pulses. The efficiency and the characteristics of stimulation pulse shapes influence the physiological effect of TMS. However, commercial devices allow only a minimum of control of different pulse shapes. Basically, just sinusoidal and monophasic pulse shapes with fixed pulse widths are available. Only few research groups work on TMS devices with controllable pulse parameters such as pulse shape or pulse width. We describe a novel TMS device with a full-bridge circuit topology incorporating four insulated-gate bipolar transistor (IGBT) modules and one energy storage capacitor to generate arbitrary waveforms. This flexible TMS (flexTMS ) device can generate magnetic pulses which can be adjusted with respect to pulse width, polarity, and intensity. Furthermore, the equipment allows us to set paired pulses with a variable interstimulus interval (ISI) from 0 to 20 ms with a step size of 10  μs. All user-defined pulses can be applied continually with repetition rates up to 30 pulses per second (pps) or, respectively, up to 100 pps in theta burst mode. Offering this variety of flexibility, flexTMS will allow the enhancement of existing TMS paradigms and novel research applications.

  19. Excitonic AND Logic Gates on DNA Brick Nanobreadboards

    PubMed Central

    2015-01-01

    A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

  20. Excitonic AND Logic Gates on DNA Brick Nanobreadboards.

    PubMed

    Cannon, Brittany L; Kellis, Donald L; Davis, Paul H; Lee, Jeunghoon; Kuang, Wan; Hughes, William L; Graugnard, Elton; Yurke, Bernard; Knowlton, William B

    2015-03-18

    A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems.

  1. Development of bioMEMS device and package for a spatially programmable biomolecule assembly

    NASA Astrophysics Data System (ADS)

    Park, Jung Jin

    We report facile in situ biomolecule assembly at readily addressable sites in microfluidic channels after complete fabrication and packaging of the microfluidic device. Aminopolysaccharide chitosan's pH responsive and chemically reactive properties allow electric signal-guided biomolecule assembly onto conductive inorganic surfaces from the aqueous environment, preserving the activity of the biomolecules. Photoimageable SU8 is used on a Pyrex bottom substrate to create microfluidic channels and a PDMS layer is sealed to the SU8 microchannel by compression of their respective substrates between additional top and bottom Plexiglas plates at the package level. Transparent and non-permanently packaged device allows consistently leak-free sealing, simple in situ and ex situ examination of the assembly procedures, fluidic input/outputs for transport of aqueous solutions, and electrical ports to guide the assembly onto the patterned gold electrode sites within the channel. Facile post-fabrication in-situ biomolecule assembly of internal electrodes is demonstrated using electrodeposition of a chitosan film on a patterned gold electrode. Both in situ fluorescence and ex situ profilometer results confirm chitosan-mediated in situ biomolecule assembly, demonstrating a simple approach to direct the assembly of biological components into a completely fabricated device. We believe that this strategy holds significant potential as a simple and generic biomolecule assembly approach for future applications in complex biomolecular or biosensing analyses as well as in sophisticated microfluidic networks as anticipated for future lab-on-a chip.

  2. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    NASA Astrophysics Data System (ADS)

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-02-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated.

  3. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure.

    PubMed

    Murapaka, C; Sethi, P; Goolaup, S; Lew, W S

    2016-02-03

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated.

  4. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    PubMed Central

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-01-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

  5. Origami-inspired active graphene-based paper for programmable instant self-folding walking devices

    PubMed Central

    Mu, Jiuke; Hou, Chengyi; Wang, Hongzhi; Li, Yaogang; Zhang, Qinghong; Zhu, Meifang

    2015-01-01

    Origami-inspired active graphene-based paper with programmed gradients in vertical and lateral directions is developed to address many of the limitations of polymer active materials including slow response and violent operation methods. Specifically, we used function-designed graphene oxide as nanoscale building blocks to fabricate an all-graphene self-folding paper that has a single-component gradient structure. A functional device composed of this graphene paper can (i) adopt predesigned shapes, (ii) walk, and (iii) turn a corner. These processes can be remote-controlled by gentle light or heating. We believe that this self-folding material holds potential for a wide range of applications such as sensing, artificial muscles, and robotics. PMID:26601135

  6. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion

    PubMed Central

    Lam, Brian; Zhou, Wendi; Kelley, Shana O.; Sargent, Edward H.

    2015-01-01

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1–3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top–down template definition with bottom–up three-dimensional nanoscale features. PMID:25914024

  7. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion

    NASA Astrophysics Data System (ADS)

    Lam, Brian; Zhou, Wendi; Kelley, Shana O.; Sargent, Edward H.

    2015-04-01

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1-3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top-down template definition with bottom-up three-dimensional nanoscale features.

  8. Interference of GSM mobile phones with communication between Cardiac Rhythm Management devices and programmers: A combined in vivo and in vitro study.

    PubMed

    Huang, Dong; Dong, Zhi-Feng; Chen, Yan; Wang, Fa-Bin; Wei, Zhi; Zhao, Wen-Bin; Li, Shuai; Liu, Ming-Ya; Zhu, Wei; Wei, Meng; Li, Jing-Bo

    2015-07-01

    To investigate interference, and how to avoid it, by high-frequency electromagnetic fields (EMFs) of Global System for Mobile Communications (GSM) mobile phone with communication between cardiac rhythm management devices (CRMs) and programmers, a combined in vivo and in vitro testing was conducted. During in vivo testing, GSM mobile phones interfered with CRM-programmer communication in 33 of 65 subjects tested (50.8%). Losing ventricle sensing was representative in this study. In terms of clinical symptoms, only 4 subjects (0.6%) felt dizzy during testing. CRM-programmer communication recovered upon termination of mobile phone communication. During in vitro testing, electromagnetic interference by high-frequency (700-950 MHz) EMFs reproducibly occurred in duplicate testing in 18 of 20 CRMs (90%). During each interference, the pacing pulse signal on the programmer would suddenly disappear while the synchronous signal was normal on the amplifier-oscilloscope. Simulation analysis showed that interference by radiofrequency emitting devices with CRM-programmer communication may be attributed to factors including materials, excitation source distance, and implant depth. Results suggested that patients implanted with CRMs should not be restricted from using GSM mobile phones; however, CRMs should be kept away from high-frequency EMFs of GSM mobile phone during programming.

  9. Smart time-pulse coding photoconverters as basic components 2D-array logic devices for advanced neural networks and optical computers

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Michalnichenko, Nikolay N.

    2004-04-01

    The article deals with a conception of building arithmetic-logic devices (ALD) with a 2D-structure and optical 2D-array inputs-outputs as advanced high-productivity parallel basic operational training modules for realization of basic operation of continuous, neuro-fuzzy, multilevel, threshold and others logics and vector-matrix, vector-tensor procedures in neural networks, that consists in use of time-pulse coding (TPC) architecture and 2D-array smart optoelectronic pulse-width (or pulse-phase) modulators (PWM or PPM) for transformation of input pictures. The input grayscale image is transformed into a group of corresponding short optical pulses or time positions of optical two-level signal swing. We consider optoelectronic implementations of universal (quasi-universal) picture element of two-valued ALD, multi-valued ALD, analog-to-digital converters, multilevel threshold discriminators and we show that 2D-array time-pulse photoconverters are the base elements for these devices. We show simulation results of the time-pulse photoconverters as base components. Considered devices have technical parameters: input optical signals power is 200nW_200μW (if photodiode responsivity is 0.5A/W), conversion time is from tens of microseconds to a millisecond, supply voltage is 1.5_15V, consumption power is from tens of microwatts to a milliwatt, conversion nonlinearity is less than 1%. One cell consists of 2-3 photodiodes and about ten CMOS transistors. This simplicity of the cells allows to carry out their integration in arrays of 32x32, 64x64 elements and more.

  10. Tribotronic Logic Circuits and Basic Operations.

    PubMed

    Zhang, Chi; Zhang, Li Min; Tang, Wei; Han, Chang Bao; Wang, Zhong Lin

    2015-06-17

    A tribotronic logic device is fabricated to convert external mechanical stimuli into logic level signals, and tribotronic logic circuits such as NOT, AND, OR, NAND, NOR, XOR, and XNOR gates are demonstrated for performing mechanical-electrical coupled tribotronic logic operations, which realize the direct interaction between the external environment and the current silicon integrated circuits.

  11. LSI/VLSI (Large Scale Integration/Very Large Scale Integration) ion implanted GaAs (Gallium Arsenide) IC processing. Appendix A: Feasibility analysis of Gallium-Arsenide mask programmable functions and logic arrays for high performance communications systems

    NASA Astrophysics Data System (ADS)

    Zucca, R. R.; Kirkpatrick, C. G.; Asbeck, P. M.; Eisen, F. H.; Lee, C. P.

    1984-01-01

    Circuits critical to the performance of advanced radio, radar and spread spectrum communications systems require advances in the state-of-the-art in semiconductor technology to meet the demands of advanced systems. As these systems increase in complexity, extensive digital circuitry is required in addition to the typical linear signal processing circuits. The power, size and weight of advanced systems also becomes unacceptable without continuous advances in semiconductor technology. Moreover an increasing trend is seen in the use of metal mask selectable functions, programmable logic arrays and gate arrays to implement system specific circuitry in an attempt to lower non-recurring costs, minimize risk and shorten development times. GaAs and other technologies with very high speed power-performance figures-of-merit are critical ingredients in systems implementations which satisfy these needs. To meet these advanced system requirements this project was initiated as a multi-phase/year program to develop a group of mask programmable gallium arsenide (GaAs) circuit elements applicable to high speed/performance communications systems.

  12. Programmable Pacemaker

    NASA Technical Reports Server (NTRS)

    1980-01-01

    St. Jude Medical's Cardiac Rhythm Management Division, formerly known as Pacesetter Systems, Inc., incorporated Apollo technology into the development of the programmable pacemaker system. This consists of the implantable pacemaker together with a physician's console containing the programmer and a data printer. Physician can communicate with patient's pacemaker by means of wireless telemetry signals transmitted through the communicating head held over the patient's chest. Where earlier pacemakers deliver a fixed type of stimulus once implanted, Programalith enables surgery free "fine tuning" of device to best suit the patient's changing needs.

  13. Radiation tolerant combinational logic cell

    NASA Technical Reports Server (NTRS)

    Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

    2009-01-01

    A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

  14. G(sup 4)FET Implementations of Some Logic Circuits

    NASA Technical Reports Server (NTRS)

    Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

    2009-01-01

    Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

  15. Electromechanical Devices and Controllers. Electronics Module 10. Instructor's Guide.

    ERIC Educational Resources Information Center

    Carter, Ed

    This module is the tenth of 10 modules in the competency-based electronics series. Introductory materials include a listing of competencies addressed in the module, a parts/equipment list, and a cross-reference table of instructional materials. Six instructional units cover: electromechanical control devices; programmable logic controllers (PLC);…

  16. Are the UK systems of innovation and evaluation of medical devices compatible? The role of NICE's Medical Technologies Evaluation Programme (MTEP).

    PubMed

    Chapman, A M; Taylor, C A; Girling, A J

    2014-08-01

    The economic evaluation of medical products and services is increasingly prioritised by healthcare decision makers and plays a key role in informing funding allocation decisions. It is well known that there are a number of methodological difficulties in the health technology assessment of medical devices, particularly in the provision of efficacy evidence. By contrasting devices with pharmaceuticals, the way in which the differing systems of innovation mould the UK's industry landscape is described and substantiated with market statistics. In recognition of the challenges faced by industry, as well as the growing need for cost-effective allocation of National Health Service (NHS) resources, the National Institute for Health and Care Excellence (NICE) led the development of the Medical Technologies Evaluation Programme (MTEP), which launched in 2009/2010. The review of the UK's medical devices market supports the programme's three principal aims: to simplify access to evaluation, speed up the process, and increase evaluative capacity for devices within NICE. However, an analysis of the output of MTEP's first 3 years suggests that it has some way to go to meet each of these aims.

  17. Dispositional logic

    NASA Technical Reports Server (NTRS)

    Le Balleur, J. C.

    1988-01-01

    The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.

  18. New Polysilicon-Oxide-Nitride-Oxide-Silicon Electrically Erasable Programmable Read-only Memory Device Approach for Eliminating Off-Cell Leakage Current

    NASA Astrophysics Data System (ADS)

    Lin, Jyh-Kuang; Chang, Chun-Yen; Huang, Heng-Sheng; Chen, Kun-Luh; Kuo, Dah-Chih

    1994-05-01

    A new polysilicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory (EEPROM) device, which eliminated off-cell leakage current, has been described and fabricated. The leakage current is easily encountered in metal-nitride-oxide-silicon (MNOS)-type EEPROMs. Two parasitic transistors, which are in parallel with the desired variable V t cell, are responsible for the leakage current. We demonstrated that the parasitic transistors are caused either by the nearly constant-threshold-voltage parasitic transistors surrounding the active region or by the “fringing effect” in poly-Si gate edges. The on-state and off-state I-V curves of the cell are shown and compared with those of two other different devices. The results reveal that the off-cell leakage current, which is observed in the other two devices, is completely eliminated in the proposed cell.

  19. Logic digital fluidic in miniaturized functional devices: Perspective to the next generation of microfluidic lab-on-chips.

    PubMed

    Zhang, Qiongdi; Zhang, Ming; Djeghlaf, Lyas; Bataille, Jeanne; Gamby, Jean; Haghiri-Gosnet, Anne-Marie; Pallandre, Antoine

    2017-04-01

    Microfluidics has emerged following the quest for scale reduction inherent to micro- and nanotechnologies. By definition, microfluidics manipulates fluids in small channels with dimensions of tens to hundreds of micrometers. Recently, microfluidics has been greatly developed and its influence extends not only the domains of chemical synthesis, bioanalysis, and medical researches but also optics and information technology. In this review article, we will shortly discuss an enlightening analogy between electrons transport in electronics and fluids transport in microfluidic channels. This analogy helps to master transport and sorting. We will present some complex microfluidic devices showing that the analogy is going a long way off toward more complex components with impressive similarities between electronics and microfluidics. We will in particular explore the vast manifold of fluidic operations with passive and active fluidic components, respectively, as well as the associated mechanisms and corresponding applications. Finally, some relevant applications and an outlook will be cited and presented.

  20. Logic programming

    SciTech Connect

    Lusk, E.L.; Overbeek, R.A.

    1989-01-01

    This book contains the proceedings of the 1989 North American Conference on Logic Programming. Included are the following papers: Expanding query power in constrain logic programming languages, Investigating the linguistics of DNA with definite clause grammars, An intermediate language to support prolog's unification.

  1. Experience with an external quality assessment programme for point-of-care-testing (POCT) devices for the determination of blood glucose.

    PubMed

    Wood, William Graham; Hanke, Rainer; Meissner, Dieane; Reinauer, Hans

    2003-01-01

    This article describes the preparation and internal and external evaluation of materials, critical issues in the external quality assessment (EQA) of point-of-care testing (POCT) devices for measuring blood glucose. A comparison was made between different materials, both of natural and synthetic origin and with and without stabilisers. The aims were to produce a material which was compatible with as many POCT-devices as possible and so reduce the number of materials sent out in each campaign as well as to optimise the precision and comparability of results between methods and devices. Although the use of near natural material--sterile-filtered plasma spiked with glucose--survived internal testing, this material proved to be unsuitable for EQA surveys. The study resulted in the reduction of materials for each survey to stabilised whole blood for one device, stabilised plasma for two devices and a synthetic material based on a polyethylene glycol matrix for all other devices. Samples were sent as pairs six times annually. The POCT-devices tested measured precisely but inaccurately in the synthetic material, when compared with the reference method (gas-chromatography coupled with isotope-dilution mass-spectrometry; GC-IDMS), so that the devices could only be evaluated for precision. The construction of ratios between the concentrations measured on the two samples distributed allowed an indirect assessment of accuracy. The need for surveillance of POCT devices is stressed in this publication, which combines theory and practice in setting up and running an EQA programme for blood glucose.

  2. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  3. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  4. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  5. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to noninvasively change one or more...

  6. Nucleic acid based logical systems.

    PubMed

    Han, Da; Kang, Huaizhi; Zhang, Tao; Wu, Cuichen; Zhou, Cuisong; You, Mingxu; Chen, Zhuo; Zhang, Xiaobing; Tan, Weihong

    2014-05-12

    Researchers increasingly visualize a significant role for artificial biochemical logical systems in biological engineering, much like digital logic circuits in electrical engineering. Those logical systems could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expression in vivo. Nucleic acids (NA), as carriers of genetic information with well-regulated and predictable structures, are promising materials for the design and engineering of biochemical circuits. A number of logical devices based on nucleic acids (NA) have been designed to handle various processes for technological or biotechnological purposes. This article focuses on the most recent and important developments in NA-based logical devices and their evolution from in vitro, through cellular, even towards in vivo biological applications.

  7. PROGRAMMABLE DISPLAY PUSHBUTTON LEGEND EDITOR

    NASA Technical Reports Server (NTRS)

    Busquets, A. M.

    1994-01-01

    The Programmable Display Pushbutton (PDP) is a pushbutton device available from Micro Switch which has a programmable 16 x 35 matrix of LEDs on the pushbutton surface. Any desired legends can be displayed on the PDPs, producing user-friendly applications which greatly reduce the need for dedicated manual controls. Because the PDP can interact with the operator, it can call for the correct response before transmitting its next message. It is both a simple manual control and a sophisticated programmable link between the operator and the host system. The Programmable Display Pushbutton Legend Editor, PDPE, is used to create the LED displays for the pushbuttons. PDPE encodes PDP control commands and legend data into message byte strings sent to a Logic Refresh and Control Unit (LRCU). The LRCU serves as the driver for a set of four PDPs. The legend editor (PDPE) transmits to the LRCU user specified commands that control what is displayed on the LED face of the individual pushbuttons. Upon receiving a command, the LRCU transmits an acknowledgement that the message was received and executed successfully. The user then observes the effect of the command on the PDP displays and decides whether or not to send the byte code of the message to a data file so that it may be called by an applications program. The PDPE program is written in FORTRAN for interactive execution. It was developed on a DEC VAX 11/780 under VMS. It has a central memory requirement of approximately 12800 bytes. It requires four Micro Switch PDPs and two RS-232 VAX 11/780 terminal ports. The PDPE program was developed in 1985.

  8. The universal magnetic tunnel junction logic gates representing 16 binary Boolean logic operations

    NASA Astrophysics Data System (ADS)

    Lee, Junwoo; Suh, Dong Ik; Park, Wanjun

    2015-05-01

    The novel devices are expected to shift the paradigm of a logic operation by their own nature, replacing the conventional devices. In this study, the nature of our fabricated magnetic tunnel junction (MTJ) that responds to the two external inputs, magnetic field and voltage bias, demonstrated seven basic logic operations. The seven operations were obtained by the electric-field-assisted switching characteristics, where the surface magnetoelectric effect occurs due to a sufficiently thin free layer. The MTJ was transformed as a universal logic gate combined with three supplementary circuits: A multiplexer (MUX), a Wheatstone bridge, and a comparator. With these circuits, the universal logic gates demonstrated 16 binary Boolean logic operations in one logic stage. A possible further approach is parallel computations through a complimentary of MUX and comparator, capable of driving multiple logic gates. A reconfigurable property can also be realized when different logic operations are produced from different level of voltages applying to the same configuration of the logic gate.

  9. Effects of gamma-ray irradiation on electronic and non-electronic equipment of Large Helical Device

    NASA Astrophysics Data System (ADS)

    K, Ogawa; T, Nishitani; M, Isobe; M, Sato; M, Yokota; H, Hayashi; T, Kobuchi; T, Nishimura

    2017-02-01

    In a deuterium operation on the Large Helical Device, the measurement and control equipment placed in the torus hall must survive under an environment of radiation. To study the effects of gamma-ray irradiation on the equipment, an irradiation experiment is performed at the Cobalt-60 irradiation facility of Nagoya University. Transient and permanent effects on a personal computer, media converters, programmable logic controllers, isolation amplifiers, a web camera, optical flow meters, and water sealing gaskets are experimentally surveyed. Transient noise appears on the web camera. Offset of the signal increases with an increase of the integrated dose on the programmable logic controller. The DeviceNet module on the programmable logic controller is broken at the integrated dose of 72 Gy, which is the expected range of the integrated dose of the torus hall. The other equipment can survive under the gamma-ray field in the torus hall.

  10. A label-free and enzyme-free system for operating various logic devices using poly(thymine)-templated CuNPs and SYBR Green I as signal transducers

    NASA Astrophysics Data System (ADS)

    Wu, Changtong; Zhou, Chunyang; Wang, Erkang; Dong, Shaojun

    2016-07-01

    For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations.For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr04069a

  11. Automatic Configuration of Programmable Logic Controller Emulators

    DTIC Science & Technology

    2015-03-01

    techniques used in reverse engineering protocols in order to automatically configure PLC emula- tors using network traces. The accuracy, flexibility, and...Reference traffic is captured and used to build protocol state machines, and then the resultant emulators’ experimental traffic is captured. Variability...thank my advisor, Dr. Barry Mullins, for providing my first formal introduction to network protocols and all of the wondrous things they can do. Thank

  12. Interlocked DNA nanostructures controlled by a reversible logic circuit

    PubMed Central

    Li, Tao; Lohmann, Finn; Famulok, Michael

    2014-01-01

    DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207

  13. Fuzzy logic

    NASA Technical Reports Server (NTRS)

    Zadeh, Lofti A.

    1988-01-01

    The author presents a condensed exposition of some basic ideas underlying fuzzy logic and describes some representative applications. The discussion covers basic principles; meaning representation and inference; basic rules of inference; and the linguistic variable and its application to fuzzy control.

  14. Synthesizing Biomolecule-based Boolean Logic Gates

    PubMed Central

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2012-01-01

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

  15. A portable microfluidic device for the rapid diagnosis of cancer metastatic potential which is programmable for temperature and CO2.

    PubMed

    Yu, I F; Yu, Y H; Chen, L Y; Fan, S K; Chou, H Y E; Yang, J T

    2014-09-21

    If metastasis of lung cancer can be found and treated early, a victim might have an improved chance to prevail over it, but routine examinations such as chest radiography, computed tomography and biopsy cannot characterize the metastatic potential of lung cancer cells; critical diagnoses to define optimal therapeutic strategies are thus lost. We designed a portable microfluidic device for the rapid diagnosis of cancer metastatic potential. Featuring a micro system to control temperature and a bicarbonate buffered environment, our device discriminates a rate of surface detachment as an index of the migratory ability of cells cultured on pH-responsive chitosan. We labeled metastatic subpopulations of lung cancer cell lines, and verified that our device is capable of separating cells according to their metastatic ability. As only few cells are needed, a patient's specimen from biopsies, e.g. from fine-needle aspiration, can be processed on site to offer immediate information to physicians. We expect that our design will provide valuable information in pre-operative evaluations to assist the definition of therapeutic plans for lung cancer, as well as for metastatic tumors of other types.

  16. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

    PubMed

    Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

    2014-12-01

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  17. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

    SciTech Connect

    Berger, Andrew J. Page, Michael R.; Young, Justin R.; Bhallamudi, Vidya P.; Johnston-Halperin, Ezekiel; Pelekhov, Denis V.; Hammel, P. Chris; Jacob, Jan; Lewis, Jim; Wenzel, Lothar

    2014-12-15

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  18. Optically controllable molecular logic circuits

    SciTech Connect

    Nishimura, Takahiro Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-07-06

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.

  19. Programmable scan/read circuitry for charge coupled device imaging detectors. [spcecraft attitude control and star trackers

    NASA Technical Reports Server (NTRS)

    Salomon, P. M.; Smilowitz, K.

    1984-01-01

    A circuit for scanning and outputting the induced charges in a solid state charge coupled device (CCD) image detector is disclosed in an image detection system for use in a spacecraft attitude control system. The image detection system includes timing control circuitry for selectively controlling the output of the CCD detector so that video outputs are provided only with respect to induced charges corresponding to predetermined sensing element lines of the CCD detector. The timing control circuit and the analog to digital converter are controlled by a programmed microprocessor which defines the video outputs to be converted and further controls the timing control circuit so that no video outputs are provided during the delay associated with analog to digital conversion.

  20. Low delay and area efficient soft error correction in arbitration logic

    DOEpatents

    Sugawara, Yutaka

    2013-09-10

    There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.

  1. Efficient G(sup 4)FET-Based Logic Circuits

    NASA Technical Reports Server (NTRS)

    Vatan, Farrokh

    2008-01-01

    A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

  2. Adaptive parallel logic networks

    NASA Technical Reports Server (NTRS)

    Martinez, Tony R.; Vidal, Jacques J.

    1988-01-01

    Adaptive, self-organizing concurrent systems (ASOCS) that combine self-organization with massive parallelism for such applications as adaptive logic devices, robotics, process control, and system malfunction management, are presently discussed. In ASOCS, an adaptive network composed of many simple computing elements operating in combinational and asynchronous fashion is used and problems are specified by presenting if-then rules to the system in the form of Boolean conjunctions. During data processing, which is a different operational phase from adaptation, the network acts as a parallel hardware circuit.

  3. Queuing register uses fluid logic elements

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Queuing register /a multistage bit-shifting device/ uses a series of pure fluid elements to perform the required logic operations. The register has several stages of three-state pure fluid elements combined with two-input NOR gates.

  4. A new laterally conductive bridge random access memory by fully CMOS logic compatible process

    NASA Astrophysics Data System (ADS)

    Hsieh, Min-Che; Chin, Yung-Wen; Lin, Yu-Cheng; Chih, Yu-Der; Tsai, Kan-Hsueh; Tsai, Ming-Jinn; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

  5. Bilayer avalanche spin-diode logic

    SciTech Connect

    Friedman, Joseph S. Querlioz, Damien; Fadel, Eric R.; Wessels, Bruce W.; Sahakian, Alan V.

    2015-11-15

    A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.

  6. Using a Commercial Ethernet PHY Device in a Radiation Environment

    NASA Technical Reports Server (NTRS)

    Parks, Jeremy; Arani, Michael; Arroyo, Roberto

    2014-01-01

    This work involved placing a commercial Ethernet PHY on its own power boundary, with limited current supply, and providing detection methods to determine when the device is not operating and when it needs either a reset or power-cycle. The device must be radiation-tested and free of destructive latchup errors. The commercial Ethernet PHY's own power boundary must be supplied by a current-limited power regulator that must have an enable (for power cycling), and its maximum power output must not exceed the PHY's input requirements, thus preventing damage to the device. A regulator with configurable output limits and short-circuit protection (such as the RHFL4913, rad hard positive voltage regulator family) is ideal. This will prevent a catastrophic failure due to radiation (such as a short between the commercial device's power and ground) from taking down the board's main power. Logic provided on the board will detect errors in the PHY. An FPGA (field-programmable gate array) with embedded Ethernet MAC (Media Access Control) will work well. The error detection includes monitoring the PHY's interrupt line, and the status of the Ethernet's switched power. When the PHY is determined to be non-functional, the logic device resets the PHY, which will often clear radiation induced errors. If this doesn't work, the logic device power-cycles the FPGA by toggling the regulator's enable input. This should clear almost all radiation induced errors provided the device is not latched up.

  7. Programmable physiological infusion

    NASA Technical Reports Server (NTRS)

    Howard, W. H.; Young, D. R.; Adachi, R. R. (Inventor)

    1974-01-01

    A programmable physiological infusion device and method are provided wherein a program source, such as a paper tape, is used to actuate an infusion pump in accordance with a desired program. The system is particularly applicable for dispensing calcium in a variety of waveforms.

  8. Assembly For Moving a Robotic Device Along Selected Axes

    NASA Technical Reports Server (NTRS)

    Nowlin, Brentley Craig (Inventor); Koch, Lisa Danielle (Inventor)

    2001-01-01

    An assembly for moving a robotic device along selected axes includes a programmable logic controller (PLC) for controlling movement of the device along selected axes to effect movement of the device to a selected disposition. The PLC includes a plurality of single axis motion control modules, and a central processing unit (CPU) in communication with the motion control modules. A human-machine interface is provided for operator selection of configurations of device movements and is in communication with the CPU. A motor drive is in communication with each of the motion control modules and is operable to effect movement of the device along the selected axes to obtain movement of the device to the selected disposition.

  9. Oscillatory Threshold Logic

    PubMed Central

    Borresen, Jon; Lynch, Stephen

    2012-01-01

    In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

  10. Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs

    NASA Astrophysics Data System (ADS)

    Fang, Wu; Huowen, Zhang; Jinmei, Lai; Yuan, Wang; Liguang, Chen; Lei, Duan; Jiarong, Tong

    2009-06-01

    This paper presents a universal field programmable gate array (FPGA) programmable routing circuit, focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.

  11. Fluid logic control circuit operates nutator actuator motor

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.

  12. LOGIC CIRCUIT

    DOEpatents

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  13. Nonlinear dynamics based digital logic and circuits.

    PubMed

    Kia, Behnam; Lindner, John F; Ditto, William L

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

  14. Nonlinear dynamics based digital logic and circuits

    PubMed Central

    Kia, Behnam; Lindner, John. F.; Ditto, William L.

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096

  15. Fuzzy logic controller optimization

    DOEpatents

    Sepe, Jr., Raymond B; Miller, John Michael

    2004-03-23

    A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.

  16. A programmable heater control circuit for spacecraft

    NASA Technical Reports Server (NTRS)

    Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

    1994-01-01

    Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

  17. Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; LaBel, Kenneth; Kim, Hak

    2014-01-01

    An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

  18. Probabilistic and fuzzy logic in clinical diagnosis.

    PubMed

    Licata, G

    2007-06-01

    In this study I have compared classic and fuzzy logic and their usefulness in clinical diagnosis. The theory of probability is often considered a device to protect the classical two-valued logic from the evidence of its inadequacy to understand and show the complexity of world [1]. This can be true, but it is not possible to discard the theory of probability. I will argue that the problems and the application fields of the theory of probability are very different from those of fuzzy logic. After the introduction on the theoretical bases of fuzzy approach to logic, I have reported some diagnostic argumentations employing fuzzy logic. The state of normality and the state of disease often fight their battle on scalar quantities of biological values and it is not hard to establish a correspondence between the biological values and the percent values of fuzzy logic. Accordingly, I have suggested some applications of fuzzy logic in clinical diagnosis and in particular I have utilised a fuzzy curve to recognise subjects with diabetes mellitus, renal failure and liver disease. The comparison between classic and fuzzy logic findings seems to indicate that fuzzy logic is more adequate to study the development of biological events. In fact, fuzzy logic is useful when we have a lot of pieces of information and when we dispose to scalar quantities. In conclusion, increasingly the development of technology offers new instruments to measure pathological parameters through scalar quantities, thus it is reasonable to think that in the future fuzzy logic will be employed more in clinical diagnosis.

  19. DNA logic gates.

    PubMed

    Okamoto, Akimitsu; Tanaka, Kazuo; Saito, Isao

    2004-08-04

    A conceptually new logic gate based on DNA has been devised. Methoxybenzodeazaadenine ((MD)A), an artificial nucleobase which we recently developed for efficient hole transport through DNA, formed stable base pairs with T and C. However, a reasonable hole-transport efficiency was observed in the reaction for the duplex containing an (MD)A/T base pair, whereas the hole transport was strongly suppressed in the reaction using a duplex where the base opposite (MD)A was replaced by C. The influence of complementary pyrimidines on the efficiency of hole transport through (MD)A was quite contrary to the selectivity observed for hole transport through G. The orthogonality of the modulation of these hole-transport properties by complementary pyrimidine bases is promising for the design of a new molecular logic gate. The logic gate system was executed by hole transport through short DNA duplexes, which consisted of the "logic gate strand", containing hole-transporting nucleobases, and the "input strand", containing pyrimidines which modulate the hole-transport efficiency of logic bases. A logic gate strand containing multiple (MD)A bases in series provided the basis for a sharp AND logic action. On the other hand, for OR logic and combinational logic, conversion of Boolean expressions to standard sum-of-product (SOP) expressions was indispensable. Three logic gate strands were designed for OR logic according to each product term in the standard SOP expression of OR logic. The hole-transport efficiency observed for the mixed sample of logic gate strands exhibited an OR logic behavior. This approach is generally applicable to the design of other complicated combinational logic circuits such as the full-adder.

  20. Fuzzy Logic Particle Tracking

    NASA Technical Reports Server (NTRS)

    2005-01-01

    A new all-electronic Particle Image Velocimetry technique that can efficiently map high speed gas flows has been developed in-house at the NASA Lewis Research Center. Particle Image Velocimetry is an optical technique for measuring the instantaneous two component velocity field across a planar region of a seeded flow field. A pulsed laser light sheet is used to illuminate the seed particles entrained in the flow field at two instances in time. One or more charged coupled device (CCD) cameras can be used to record the instantaneous positions of particles. Using the time between light sheet pulses and determining either the individual particle displacements or the average displacement of particles over a small subregion of the recorded image enables the calculation of the fluid velocity. Fuzzy logic minimizes the required operator intervention in identifying particles and computing velocity. Using two cameras that have the same view of the illumination plane yields two single exposure image frames. Two competing techniques that yield unambiguous velocity vector direction information have been widely used for reducing the single-exposure, multiple image frame data: (1) cross-correlation and (2) particle tracking. Correlation techniques yield averaged velocity estimates over subregions of the flow, whereas particle tracking techniques give individual particle velocity estimates. For the correlation technique, the correlation peak corresponding to the average displacement of particles across the subregion must be identified. Noise on the images and particle dropout result in misidentification of the true correlation peak. The subsequent velocity vector maps contain spurious vectors where the displacement peaks have been improperly identified. Typically these spurious vectors are replaced by a weighted average of the neighboring vectors, thereby decreasing the independence of the measurements. In this work, fuzzy logic techniques are used to determine the true

  1. SRAM Based Re-programmable FPGA for Space Applications

    NASA Technical Reports Server (NTRS)

    Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

    1999-01-01

    An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

  2. Programmability of Co-antidot lattices of optimized geometry

    PubMed Central

    Schneider, Tobias; Langer, Manuel; Alekhina, Julia; Kowalska, Ewa; Oelschlägel, Antje; Semisalova, Anna; Neudert, Andreas; Lenz, Kilian; Potzger, Kay; Kostylev, Mikhail P.; Fassbender, Jürgen; Adeyeye, Adekunle O.; Lindner, Jürgen; Bali, Rantej

    2017-01-01

    Programmability of stable magnetization configurations in a magnetic device is a highly desirable feature for a variety of applications, such as in magneto-transport and spin-wave logic. Periodic systems such as antidot lattices may exhibit programmability; however, to achieve multiple stable magnetization configurations the lattice geometry must be optimized. We consider the magnetization states in Co-antidot lattices of ≈50 nm thickness and ≈150 nm inter-antidot distance. Micromagnetic simulations were applied to investigate the magnetization states around individual antidots during the reversal process. The reversal processes predicted by micromagnetics were confirmed by experimental observations. Magnetization reversal in these antidots occurs via field driven transition between 3 elementary magnetization states – termed G, C and Q. These magnetization states can be described by vectors, and the reversal process proceeds via step-wise linear operations on these vector states. Rules governing the co-existence of the three magnetization states were empirically observed. It is shown that in an n × n antidot lattice, a variety of field switchable combinations of G, C and Q can occur, indicating programmability of the antidot lattices. PMID:28145463

  3. Programmability of Co-antidot lattices of optimized geometry

    NASA Astrophysics Data System (ADS)

    Schneider, Tobias; Langer, Manuel; Alekhina, Julia; Kowalska, Ewa; Oelschlägel, Antje; Semisalova, Anna; Neudert, Andreas; Lenz, Kilian; Potzger, Kay; Kostylev, Mikhail P.; Fassbender, Jürgen; Adeyeye, Adekunle O.; Lindner, Jürgen; Bali, Rantej

    2017-02-01

    Programmability of stable magnetization configurations in a magnetic device is a highly desirable feature for a variety of applications, such as in magneto-transport and spin-wave logic. Periodic systems such as antidot lattices may exhibit programmability; however, to achieve multiple stable magnetization configurations the lattice geometry must be optimized. We consider the magnetization states in Co-antidot lattices of ≈50 nm thickness and ≈150 nm inter-antidot distance. Micromagnetic simulations were applied to investigate the magnetization states around individual antidots during the reversal process. The reversal processes predicted by micromagnetics were confirmed by experimental observations. Magnetization reversal in these antidots occurs via field driven transition between 3 elementary magnetization states – termed G, C and Q. These magnetization states can be described by vectors, and the reversal process proceeds via step-wise linear operations on these vector states. Rules governing the co-existence of the three magnetization states were empirically observed. It is shown that in an n × n antidot lattice, a variety of field switchable combinations of G, C and Q can occur, indicating programmability of the antidot lattices.

  4. Reversible logic for supercomputing.

    SciTech Connect

    DeBenedictis, Erik P.

    2005-05-01

    This paper is about making reversible logic a reality for supercomputing. Reversible logic offers a way to exceed certain basic limits on the performance of computers, yet a powerful case will have to be made to justify its substantial development expense. This paper explores the limits of current, irreversible logic for supercomputers, thus forming a threshold above which reversible logic is the only solution. Problems above this threshold are discussed, with the science and mitigation of global warming being discussed in detail. To further develop the idea of using reversible logic in supercomputing, a design for a 1 Zettaflops supercomputer as required for addressing global climate warming is presented. However, to create such a design requires deviations from the mainstream of both the software for climate simulation and research directions of reversible logic. These deviations provide direction on how to make reversible logic practical.

  5. Logic Design Pathology and Space Flight Electronics

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Barto, Rod L.; Erickson, K.

    1997-01-01

    Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

  6. Nonvolatile ``AND,'' ``OR,'' and ``NOT'' Boolean logic gates based on phase-change memory

    NASA Astrophysics Data System (ADS)

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-01

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  7. Complete all-optical processing polarization-based binary logic gates and optical processors.

    PubMed

    Zaghloul, Y A; Zaghloul, A R M

    2006-10-16

    We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple

  8. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.

    PubMed

    Sun, Li; Savory, Joshua J; Warncke, Kurt

    2013-08-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range.

  9. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications

    PubMed Central

    Sun, Li; Savory, Joshua J.; Warncke, Kurt

    2014-01-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range. PMID:25076864

  10. Optical Logic Gates

    NASA Technical Reports Server (NTRS)

    Du Fresne, E. R.; Dowler, W. L.

    1985-01-01

    Logic gates for light signals constructed from combinations of prisms, polarizing plates, and quarterwave plates. Optical logic gate performs elementary logic operation on light signals received along two optical fibers. Whether gate performs OR function or exclusive-OR function depends on orientation of analyzer. Nonbinary truth tables also obtained by rotating polarizer or analyzer to other positions or inserting other quarter-wave plates.

  11. Fuzzy Logic Engine

    NASA Technical Reports Server (NTRS)

    Howard, Ayanna

    2005-01-01

    The Fuzzy Logic Engine is a software package that enables users to embed fuzzy-logic modules into their application programs. Fuzzy logic is useful as a means of formulating human expert knowledge and translating it into software to solve problems. Fuzzy logic provides flexibility for modeling relationships between input and output information and is distinguished by its robustness with respect to noise and variations in system parameters. In addition, linguistic fuzzy sets and conditional statements allow systems to make decisions based on imprecise and incomplete information. The user of the Fuzzy Logic Engine need not be an expert in fuzzy logic: it suffices to have a basic understanding of how linguistic rules can be applied to the user's problem. The Fuzzy Logic Engine is divided into two modules: (1) a graphical-interface software tool for creating linguistic fuzzy sets and conditional statements and (2) a fuzzy-logic software library for embedding fuzzy processing capability into current application programs. The graphical- interface tool was developed using the Tcl/Tk programming language. The fuzzy-logic software library was written in the C programming language.

  12. Fundamentals of Digital Logic.

    ERIC Educational Resources Information Center

    Noell, Monica L.

    This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…

  13. Promoting Logical Ability

    ERIC Educational Resources Information Center

    Osborne, Alan R.

    1973-01-01

    This article reports one search for factors or conditions shaping the child's growth in logical ability. The search indicated the existence of a relationship between the quantity of teacher talk that contains the language of logic and the change exhibited by students. Implications for classroom practice are discussed. (JA)

  14. Logic via Computer Programming.

    ERIC Educational Resources Information Center

    Wieschenberg, Agnes A.

    This paper proposed the question "How do we teach logical thinking and sophisticated mathematics to unsophisticated college students?" One answer among many is through the writing of computer programs. The writing of computer algorithms is mathematical problem solving and logic in disguise and it may attract students who would otherwise stop…

  15. Logic Programming: PROLOG.

    ERIC Educational Resources Information Center

    Lopez, Antonio M., Jr.

    1989-01-01

    Provides background material on logic programing and presents PROLOG as a high-level artificial intelligence programing language that borrows its basic constructs from logic. Suggests the language is one which will help the educator to achieve various goals, particularly the promotion of problem solving ability. (MVL)

  16. Regulatory Conformance Checking: Logic and Logical Form

    ERIC Educational Resources Information Center

    Dinesh, Nikhil

    2010-01-01

    We consider the problem of checking whether an organization conforms to a body of regulation. Conformance is studied in a runtime verification setting. The regulation is translated to a logic, from which we synthesize monitors. The monitors are evaluated as the state of an organization evolves over time, raising an alarm if a violation is…

  17. Aptamer-Binding Directed DNA Origami Pattern for Logic Gates.

    PubMed

    Yang, Jing; Jiang, Shuoxing; Liu, Xiangrong; Pan, Linqiang; Zhang, Cheng

    2016-12-14

    In this study, an aptamer-substrate strategy is introduced to control programmable DNA origami pattern. Combined with DNA aptamer-substrate binding and DNAzyme-cutting, small DNA tiles were specifically controlled to fill into the predesigned DNA origami frame. Here, a set of DNA logic gates (OR, YES, and AND) are performed in response to the stimuli of adenosine triphosphate (ATP) and cocaine. The experimental results are confirmed by AFM imaging and time-dependent fluorescence changes, demonstrating that the geometric patterns are regulated in a controllable and programmable manner. Our approach provides a new platform for engineering programmable origami nanopatterns and constructing complex DNA nanodevices.

  18. Smart programmable wireless microaccelerometers

    NASA Astrophysics Data System (ADS)

    Varadan, Vijay K.; Subramanian, Hareesh; Varadan, Vasundara V.

    1998-07-01

    The integration of MEMS, SAW devices and required microelectronics and conformal antenna to realize a programmable wireless accelerometer is presented in this paper. This unique combination of technologies results in a novel accelerometer that can be remotely sensed by a microwave system with the advantage of no power requirements at the sensor site. The microaccelerometer presented is simple in construction and easy to manufacture with existing silicon micromachining techniques. Programmable accelerometers can be achieved with splitfinger interdigital transducers (IDTs) as reflecting structures. If IDTs are short circuited or capacitively loaded, the wave propagates without any reflection whereas in an open circuit configuration, the IDTs reflect the incoming SAW signal. The programmable accelerometers can thus be achieved by using an external circuitry on a semiconductor chip using hybrid technology. The relatively small size of the sensor makes it an ideal conformal sensor. The accelerometer finds application as air bag deployment sensors, vibration sensors for noise control, deflection and strain sensors, inertial and dimensional positioning systems, ABS/traction control, smart suspension, active roll stabilization and four wheel steering. The wireless accelerometer is very attractive to study the response of a `dummy' in automobile crash test.

  19. Valve system incorporating single failure protection logic

    DOEpatents

    Ryan, Rodger; Timmerman, Walter J. H.

    1980-01-01

    A valve system incorporating single failure protective logic. The system consists of a valve combination or composite valve which allows actuation or de-actuation of a device such as a hydraulic cylinder or other mechanism, integral with or separate from the valve assembly, by means of three independent input signals combined in a function commonly known as two-out-of-three logic. Using the input signals as independent and redundant actuation/de-actuation signals, a single signal failure, or failure of the corresponding valve or valve set, will neither prevent the desired action, nor cause the undesired action of the mechanism.

  20. Feasibility study for future implantable neural-silicon interface devices.

    PubMed

    Al-Armaghany, Allann; Yu, Bo; Mak, Terrence; Tong, Kin-Fai; Sun, Yihe

    2011-01-01

    The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and transmission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. Field programmable logic arrays (FPGAs) are used to evaluate various structures.

  1. A digital magnetic resonance imaging spectrometer using digital signal processor and field programmable gate array

    NASA Astrophysics Data System (ADS)

    Liang, Xiao; Binghe, Sun; Yueping, Ma; Ruyan, Zhao

    2013-05-01

    A digital spectrometer for low-field magnetic resonance imaging is described. A digital signal processor (DSP) is utilized as the pulse programmer on which a pulse sequence is executed as a subroutine. Field programmable gate array (FPGA) devices that are logically mapped into the external addressing space of the DSP work as auxiliary controllers of gradient control, radio frequency (rf) generation, and rf receiving separately. The pulse programmer triggers an event by setting the 32-bit control register of the corresponding FPGA, and then the FPGA automatically carries out the event function according to preset configurations in cooperation with other devices; accordingly, event control of the spectrometer is flexible and efficient. Digital techniques are in widespread use: gradient control is implemented in real-time by a FPGA; rf source is constructed using direct digital synthesis technique, and rf receiver is constructed using digital quadrature detection technique. Well-designed performance is achieved, including 1 μs time resolution of the gradient waveform, 1 μs time resolution of the soft pulse, and 2 MHz signal receiving bandwidth. Both rf synthesis and rf digitalization operate at the same 60 MHz clock, therefore, the frequency range of transmitting and receiving is from DC to ˜27 MHz. A majority of pulse sequences have been developed, and the imaging performance of the spectrometer has been validated through a large number of experiments. Furthermore, the spectrometer is also suitable for relaxation measurement in nuclear magnetic resonance field.

  2. Photonic encryption using all optical logic.

    SciTech Connect

    Blansett, Ethan L.; Schroeppel, Richard Crabtree; Tang, Jason D.; Robertson, Perry J.; Vawter, Gregory Allen; Tarman, Thomas David; Pierson, Lyndon George

    2003-12-01

    With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an

  3. Fuzzy logic based on-line fault detection and classification in transmission line.

    PubMed

    Adhikari, Shuma; Sinha, Nidul; Dorendrajit, Thingam

    2016-01-01

    This study presents fuzzy logic based online fault detection and classification of transmission line using Programmable Automation and Control technology based National Instrument Compact Reconfigurable i/o (CRIO) devices. The LabVIEW software combined with CRIO can perform real time data acquisition of transmission line. When fault occurs in the system current waveforms are distorted due to transients and their pattern changes according to the type of fault in the system. The three phase alternating current, zero sequence and positive sequence current data generated by LabVIEW through CRIO-9067 are processed directly for relaying. The result shows that proposed technique is capable of right tripping action and classification of type of fault at high speed therefore can be employed in practical application.

  4. DNA “Nano-Claw”: Logic-based Autonomous Cancer Targeting and Therapy

    PubMed Central

    You, Mingxu; Peng, Lu; Shao, Na; Zhang, Liqin; Qiu, Liping; Cui, Cheng; Tan, Weihong

    2014-01-01

    Cell types, both healthy and diseased, can be classified by inventories of their cell-surface markers. Programmable analysis of multiple markers would enable clinicians to develop a comprehensive disease profile, leading to more accurate diagnosis and intervention. As a first step to accomplish this, we have designed a DNA-based device, called “Nano-Claw”. Combining the special structure-switching properties of DNA aptamers with toehold-mediated strand displacement reactions, this claw is capable of performing autonomous logic-based analysis of multiple cancer cell-surface markers and, in response, producing a diagnostic signal and/or targeted photodynamic therapy. We anticipate that this design can be widely applied in facilitating basic biomedical research, accurate disease diagnosis and effective therapy. PMID:24367989

  5. Nanoeletromechanical switch and logic circuits formed therefrom

    DOEpatents

    Nordquist, Christopher D.; Czaplewski, David A.

    2010-05-18

    A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

  6. The Lick Observatory charge-coupled device /CCD/ and controller

    NASA Technical Reports Server (NTRS)

    Robinson, L. B.

    1981-01-01

    A description is given of a flexible microprocessor-based controller for charge-coupled device two-dimensional detectors. It is noted that the controller can operate under manual control or as a slave to a remote computer linked by coaxial cable. The system is discussed, together with data taken at the telescope and in the laboratory. The flexibility of the controller derives from its modular form and from the use of a programmable 8-bit microprocessor to control and sequence the electronic logic. The electronic circuits for such functions as signal processing, clock sequencing, voltage level adjustment, and temperature control are on small individual plug-in cards, making future improvements and changes simple. The software of the microprocessor is stored in erasable, programmable, read-only memory. Among the limitations of the controller is a scan speed of roughly 35 microsec per pixel.

  7. Event Logic Assistant (Elan)

    DTIC Science & Technology

    2008-07-14

    as a basis for Phase II research. 2 Background 2.1 Event logic 2.1.1 Event structures Intuitively, an event structure is an abstract algebraic ...Theoretical Computer Science, 149:257–298, 1995. [2] Uri Abraham. Models for Concurrency, volume 11 of Algebra , Logic and Applications Series. Gordon...the ordering of events in a distributed system. Comms. ACM, 21(7):558–65, 1978. [28] Leslie Lamport. Hybrid systems in TLA+. In Grossman , Nerode, Ravn

  8. Systems, Devices, and Materials for Digital Optical Processing.

    NASA Astrophysics Data System (ADS)

    Title, Mark Alan

    The massive parallelism and flexibility of three -dimensional optical communication may allow the development of new parallel computers free from the constraints of planar electronic technology. To bring the optical computer from possibility to reality, however, requires technological and scientific development in new optical systems, devices, and materials. We present here research results in each of these areas. First described is a prototype optical information processing system using CdS/liquid crystal spatial light modulators for optical logic and memory. This system has been developed as the first step in the implementation of a fine-grained, globally-interconnected optical processing element array. Notable system features include the implementation of programmable electronic control and the analysis of the optical power distribution within the processor, both directly applicable to the design of new and more advanced optical information processing systems. Next presented is the design and initial performance data for a new spatial light modulator combining an array of silicon phototransistors with the electro-optic material (Pb,La)(Zr,Ti)O _3, opening new possibilities for "intelligent" optical logic, memory, and switching devices. Important to the optimal performance of this Si/PLZT device is the fabrication of embedded electrodes in the electro-optic material, reducing the device operating voltage and switching energy while improving the uniformity of the optical modulation. An extensive computer model of embedded electrode performance and details of the electrode fabrication by reactive ion beam etching and electroless Ni deposition are presented. Finally, in the area of optical materials development we present initial results in the RF magnetron deposition of electro -optic PLZT on r-plane sapphire. This work is important to the fabrication of a monolithic, Si/PLZT-on-sapphire spatial light modulator, promising superior performance to devices using

  9. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  10. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  11. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  12. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  13. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  14. Towards bioelectronic logic (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Meredith, Paul; Mostert, Bernard; Sheliakina, Margarita; Carrad, Damon J.; Micolich, Adam P.

    2016-09-01

    One of the critical tasks in realising a bioelectronic interface is the transduction of ion and electron signals at high fidelity, and with appropriate speed, bandwidth and signal-to-noise ratio [1]. This is a challenging task considering ions and electrons (or holes) have drastically different physics. For example, even the lightest ions (protons) have mobilities much smaller than electrons in the best semiconductors, effective masses are quite different, and at the most basic level, ions are `classical' entities and electrons `quantum mechanical'. These considerations dictate materials and device strategies for bioelectronic interfaces alongside practical aspects such as integration and biocompatibility [2]. In my talk I will detail these `differences in physics' that are pertinent to the ion-electron transduction challenge. From this analysis, I will summarise the basic categories of device architecture that are possibilities for transducing elements and give recent examples of their realisation. Ultimately, transducing elements need to be combined to create `bioelectronic logic' capable of signal processing at the interface level. In this regard, I will extend the discussion past the single element concept, and discuss our recent progress in delivering all-solids-state logic circuits based upon transducing interfaces. [1] "Ion bipolar junction transistors", K. Tybrandt, K.C. Larsson, A. Richter-Dahlfors and M. Berggren, Proc. Natl Acad. Sci., 107, 9929 (2010). [2] "Electronic and optoelectronic materials and devices inspired by nature", P Meredith, C.J. Bettinger, M. Irimia-Vladu, A.B. Mostert and P.E. Schwenn, Reports on Progress in Physics, 76, 034501 (2013).

  15. Analysis of an innovative user threshold programmable photoreceiver monolithically integrated in a multitechnology field programmable gate array (MT-FPGA)

    NASA Astrophysics Data System (ADS)

    Mal, Prosenjit; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-10-01

    In the past decade, Field Programmable Gate Arrays (FPGA) has significantly influenced the landscape of the electronic industry. In particular, in the areas of semiconductor manufacturing, CAD tool designs and a wide range of digital logic applications. Primarily, research efforts in the FPGA community have concentrated on improving the reconfigurability or programmability of present day architecture for digital applications. However, the digital nature of FPGA technologies limits their applicability to a wide range of applications that depend on analog circuitry, photonic and RF based technologies. As with any ASIC design, the turn-around time between design iterations may be several months which is prohibitively long for multi-technology test-bed systems where the system designer depends on a rapid prototyping/experimentation environment that allows for optimization of processing algorithms and system architecture. Therefore, we developed innovative FPGA architecture that merges conventional FPGA technology with mixed signal and other multi-technology device. In this paper we discuss the Multi-Technology-FPGA (MT-FPGA) architecture that allows the user to have flexible rapid prototyping environment and provides him or her with the benefits of a conventional FPGA in a mixed signal domain. We substantiate this concept by implementing this architecture in TSMC 0.35 μm process and discussing the results of a variable threshold optical receiver circuit suitable for photonic information processing.

  16. A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

    NASA Astrophysics Data System (ADS)

    Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

    2017-03-01

    A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

  17. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  18. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  19. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  20. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  1. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  2. Advanced logic gates for ultrafast network interchanges

    NASA Astrophysics Data System (ADS)

    Islam, Mohammed N.

    1995-08-01

    By overcoming speed bottlenecks from electronic switching as well as optical/electronic conversions, all-optical logic gates can permit further exploitation of the nearly 40 THz of bandwidth available from optical fibers. We focus on the use of optical solitons and all-optical logic gates to implement ultrafast ``interchanges'' or switching nodes on packet networks with speeds of 100 Gbit/s or greater. For example, all-optical logic gates have been demonstrated with speeds up to 200 Gbit/s, and they may be used to decide whether to add or drop a data packet. The overall goal of our effort is to demonstrate the key enabling technologies and their combination for header processing in 100 Gbit/s, time-division-multiplexed, packed switched networks. Soliton-based fiber logic gates are studied with the goal of combining attractive features of soliton-dragging logic gates, nonlinear loop mirrors, and erbium-doped fiber amplifiers to design logic gates with optimum switching energy, contrast ratio, and timing sensitivity. First, the experimental and numerical work studies low-latency soliton logic gates based on frequency shifts associated with cross-phase modulation. In preliminary experiments, switching in 15 m long low-birefringent fibers has been demonstrated with a contrast ratio of 2.73:1. Using dispersion-shifted fiber in the gate should lower the switching energy and improve the contrast ratio. Next, the low-birefringent fiber can be cross-spliced and wrapped into a nonlinear optical loop mirror to take advantage of mechanisms from both soliton dragging and loop mirrors. The resulting device can have low switching energy and a timing window that results from a combination of soliton dragging and the loop mirror mechanisms.

  3. Programmable Logic Controller Modification Attacks for use in Detection Analysis

    DTIC Science & Technology

    2014-03-27

    Control System IDS Intrusion Detection System IP Internet Protocol IT Information Technology JTAG Joint Test Action Group LAN Local Area Network PLC...firewalls or Intrusion Detection System (IDS), implementing cryptography, and improving protocol security. There are few vendors, however, that include...Mode Setting Register Values. Mode r0 Value r3 Value PRGM 0x11 0x1 RUN 0x11 0x2 REM PRGM 0x12 0x1 REM RUN 0x12 0x2 cpmode 1 contains two

  4. Application of programmable logic controllers to space simulation

    NASA Technical Reports Server (NTRS)

    Sushon, Janet

    1992-01-01

    Incorporating a state-of-the-art process control and instrumentation system into a complex system for thermal vacuum testing is discussed. The challenge was to connect several independent control systems provided by various vendors to a supervisory computer. This combination will sequentially control and monitor the process, collect the data, and transmit it to color a graphic system for subsequent manipulation. The vacuum system upgrade included: replacement of seventeen diffusion pumps with eight cryogenic pumps and one turbomolecular pump, replacing a relay based control system, replacing vacuum instrumentation, and upgrading the data acquisition system.

  5. Distributed solid state programmable thermostat/power controller

    NASA Technical Reports Server (NTRS)

    Alexander, Jane C. (Inventor); Howard, David E. (Inventor); Smith, Dennis A. (Inventor)

    2008-01-01

    A self-contained power controller having a power driver switch, programmable controller, communication port, and environmental parameter measuring device coupled to a controllable device. The self-contained power controller needs only a single voltage source to power discrete devices, analog devices, and the controlled device. The programmable controller has a run mode which, when selected, upon the occurrence of a trigger event changes the state of a power driver switch and wherein the power driver switch is maintained by the programmable controller at the same state until the occurrence of a second event.

  6. The JOSHUA (J80) system programmer`s manual

    SciTech Connect

    Smetana, A.O.; McCort, J.T.; Westmoreland, B.W.

    1993-08-01

    The JOSHUA system routines (JS routines) can be used to manage a JOSHUA data base and execute JOSHUA modules on VAX/VMS and IBM/MVS computer systems. This manual provides instructions for using the JS routines and information about the internal data structures and logic used by the routines. It is intended for use primarily by JOSHUA systems programmers, however, advanced applications programmers may also find it useful. The JS routines are, as far as possible, written in ANSI FORTRAN 77 so that they are easily maintainable and easily portable to different computer systems. Nevertheless, the JOSHUA system provides features that are not available in ANSI FORTRAN 77, notably dynamic module execution and a data base of named, variable length, unformatted records, so some parts of the routines are coded in nonstandard FORTRAN or assembler (as a last resort). In most cases, the nonstandard sections of code are different for each computer system. To make it easy for programmers using the JS routines to avoid naming conflicts, the JS routines and common block all have six character names that begin with the characters {open_quotes}JS.{close_quotes} Before using this manual, one should be familiar with the JOSHUA system as described in {open_quotes}The JOSHUA Users` Manual,{close_quotes} ANSI FORTRAN 77, and at least one of the computer systems for which the JS routines have been implemented.

  7. Optically programmable encoder based on light propagation in two-dimensional regular nanoplates.

    PubMed

    Li, Ya; Zhao, Fangyin; Guo, Shuai; Zhang, Yongyou; Niu, Chunhui; Zeng, Ruosheng; Zou, Bingsuo; Zhang, Wensheng; Ding, Kang; Bukhtiar, Arfan; Liu, Ruibin

    2017-04-07

    We design an efficient optically controlled microdevice based on CdSe nanoplates. Two-dimensional CdSe nanoplates exhibit lighting patterns around the edges and can be realized as a new type of optically controlled programmable encoder. The light source is used to excite the nanoplates and control the logical position under vertical pumping mode by the objective lens. At each excitation point in the nanoplates, the preferred light-propagation routes are along the normal direction and perpendicular to the edges, which then emit out from the edges to form a localized lighting section. The intensity distribution around the edges of different nanoplates demonstrates that the lighting part with a small scale is much stronger, defined as '1', than the dark section, defined as '0', along the edge. These '0' and '1' are the basic logic elements needed to compose logically functional devices. The observed propagation rules are consistent with theoretical simulations, meaning that the guided-light route in two-dimensional semiconductor nanoplates is regular and predictable. The same situation was also observed in regular CdS nanoplates. Basic theoretical analysis and experiments prove that the guided light and exit position follow rules mainly originating from the shape rather than material itself.

  8. Optically programmable encoder based on light propagation in two-dimensional regular nanoplates

    NASA Astrophysics Data System (ADS)

    Li, Ya; Zhao, Fangyin; Guo, Shuai; Zhang, Yongyou; Niu, Chunhui; Zeng, Ruosheng; Zou, Bingsuo; Zhang, Wensheng; Ding, Kang; Bukhtiar, Arfan; Liu, Ruibin

    2017-04-01

    We design an efficient optically controlled microdevice based on CdSe nanoplates. Two-dimensional CdSe nanoplates exhibit lighting patterns around the edges and can be realized as a new type of optically controlled programmable encoder. The light source is used to excite the nanoplates and control the logical position under vertical pumping mode by the objective lens. At each excitation point in the nanoplates, the preferred light-propagation routes are along the normal direction and perpendicular to the edges, which then emit out from the edges to form a localized lighting section. The intensity distribution around the edges of different nanoplates demonstrates that the lighting part with a small scale is much stronger, defined as ‘1’, than the dark section, defined as ‘0’, along the edge. These ‘0’ and ‘1’ are the basic logic elements needed to compose logically functional devices. The observed propagation rules are consistent with theoretical simulations, meaning that the guided-light route in two-dimensional semiconductor nanoplates is regular and predictable. The same situation was also observed in regular CdS nanoplates. Basic theoretical analysis and experiments prove that the guided light and exit position follow rules mainly originating from the shape rather than material itself.

  9. Flight dynamics analysis and simulation of heavy lift airships. Volume 5: Programmer's manual

    NASA Technical Reports Server (NTRS)

    Ringland, R. F.; Tischler, M. B.; Jex, H. R.; Emmen, R. D.; Ashkenas, I. L.

    1982-01-01

    The Programmer's Manual contains explanations of the logic embodied in the various program modules, a dictionary of program variables, a subroutine listing, subroutine/common block/cross reference listing, and a calling/called subroutine cross reference listing.

  10. Diagnosable structured logic array

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling (Inventor); Miles, Lowell (Inventor); Gambles, Jody (Inventor); Maki, Gary K. (Inventor)

    2009-01-01

    A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.

  11. Extremely large magnetoresistance and magnetic logic by coupling semiconductor nonlinear transport effect and anomalous Hall Effect

    NASA Astrophysics Data System (ADS)

    Zhang, Xiaozhong; Luo, Zhaochu

    Size limitation of silicon FET hinders the further scaling down of silicon based CPU. To solve this problem, spin based magnetic logic devices were proposed but almost all of them could not be realized experimentally except for NOT logic operation. A magnetic field controlled reconfigurable semiconductor logic using InSb was reported. However, InSb is very expensive and not compatible with the silicon technology. Based on our Si based magnetoresistance (MR) device, we developed a Si based reconfigurable magnetic logic device, which could do all four Boolean logic operations including AND, OR, NOR and NAND. By coupling nonlinear transport effect of semiconductor and anomalous Hall effect of magnetic material, we propose a PMA material based MR device with a remarkable non local MR of >20000 % at ~1 mT. Based on this MR device, we further developed a PMA material based magnetic logic device which could do all four Boolean logic operations. This makes it possible that magnetic material does both memory and logic. This may result in a memory-logic integrated system leading to a non von Neumann computer

  12. Reconfigurable magnetic logic combined with non-volatile memory in silicon

    NASA Astrophysics Data System (ADS)

    Luo, Zhaochu; Zhang, Xiaozhong

    Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.

  13. Reconfigurable Boolean Logic Using Magnetic Single-Electron Transistors

    PubMed Central

    Gonzalez-Zalba, M. Fernando; Ciccarelli, Chiara; Zarbo, Liviu P.; Irvine, Andrew C.; Campion, Richard C.; Gallagher, Bryan L.; Jungwirth, Tomas; Ferguson, Andrew J.; Wunderlich, Joerg

    2015-01-01

    We propose a novel hybrid single-electron device for reprogrammable low-power logic operations, the magnetic single-electron transistor (MSET). The device consists of an aluminium single-electron transistor with a GaMnAs magnetic back-gate. Changing between different logic gate functions is realized by reorienting the magnetic moments of the magnetic layer, which induces a voltage shift on the Coulomb blockade oscillations of the MSET. We show that we can arbitrarily reprogram the function of the device from an n-type SET for in-plane magnetization of the GaMnAs layer to p-type SET for out-of-plane magnetization orientation. Moreover, we demonstrate a set of reprogrammable Boolean gates and its logical complement at the single device level. Finally, we propose two sets of reconfigurable binary gates using combinations of two MSETs in a pull-down network. PMID:25923789

  14. Fuzzy logic controller to improve powerline communication

    NASA Astrophysics Data System (ADS)

    Tirrito, Salvatore

    2015-12-01

    The Power Line Communications (PLC) technology allows the use of the power grid in order to ensure the exchange of data information among devices. This work proposes an approach, based on Fuzzy Logic, that dynamically manages the amplitude of the signal, with which each node transmits, by processing the master-slave link quality measured and the master-slave distance. The main objective of this is to reduce both the impact of communication interferences induced and power consumption.

  15. Synthetic circuits integrating logic and memory in living cells.

    PubMed

    Siuti, Piro; Yazbek, John; Lu, Timothy K

    2013-05-01

    Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications.

  16. Anion Sensors as Logic Gates: A Close Encounter?

    PubMed

    Madhuprasad; Bhat, Mahesh P; Jung, Ho-Young; Losic, Dusan; Kurkuri, Mahaveer D

    2016-04-25

    Computers have become smarter, smaller, and more efficient due to the downscaling of silicon-based components. Top-down miniaturisation of silicon-based computer components is fast reaching its limitations because of physical constraints and economical non-feasibility. Therefore, the possibility of a bottom-up approach that uses molecules to build nano-sized devices has been initiated. As a result, molecular logic gates based on chemical inputs and measurable optical outputs have captured significant attention very recently. In addition, it would be interesting if such molecular logic gates could be developed by making use of ion sensors, which can give significantly sensitive output information. This review provides a brief introduction to anion receptors, molecular logic gates, a comprehensive review on describing recent advances and progress on development of ion receptors for molecular logic gates, and a brief idea about the application of molecular logic gates.

  17. Stacked resistive switches for AND/OR logic gates

    NASA Astrophysics Data System (ADS)

    Kim, Myung Ju; Son, Kyung Rock; Park, Ju Hyun; Kim, Tae Geun

    2017-06-01

    This paper reports the use of stacked resistive switches as logic gates for implementing the ;AND; and ;OR; operations. These stacked resistive switches consist of two resistive switches that share a middle electrode, and they operate based on the difference in resistance between the low and high resistance states indicating the logical states of ;0; and ;1;, respectively. The stacked resistive switches can perform either AND or OR operation, using two read schemes in one device. To perform the AND (or OR) operation, two resistive switches are arranged in a serial (or parallel) connection. AND and OR operations have been successfully demonstrated using the stacked resistive switches. The use of stacked resistive switches as logic gates that utilize the advantages of memristive devices shows the possibility of stateful logic circuits.

  18. The Logic of Evaluation.

    ERIC Educational Resources Information Center

    Welty, Gordon A.

    The logic of the evaluation of educational and other action programs is discussed from a methodological viewpoint. However, no attempt is made to develop methods of evaluating programs. In Part I, the structure of an educational program is viewed as a system with three components--inputs, transformation of inputs into outputs, and outputs. Part II…

  19. Metacomputation and logic programming

    SciTech Connect

    Abramov, S.M.

    1992-03-01

    This paper presents an approach to logic programming based on implementing reverse semantics of programming languages. The interpreter that implements reverse semantics is called a Universal Resolving Algorithm (URA). Implementation and methods for application of a URA are based on methods of metacomputation. 12 refs., 2 figs.

  20. Temporal logics meet telerobotics

    NASA Technical Reports Server (NTRS)

    Rutten, Eric; Marce, Lionel

    1989-01-01

    The specificity of telerobotics being the presence of a human operator, decision assistance tools are necessary for the operator, especially in hostile environments. In order to reduce execution hazards due to a degraded ability for quick and efficient recovery of unexpected dangerous situations, it is of importance to have the opportunity, amongst others, to simulate the possible consequences of a plan before its actual execution, in order to detect these problematic situations. Hence the idea of providing the operator with a simulator enabling him to verify the temporal and logical coherence of his plans. Therefore, the power of logical formalisms is used for representation and deduction purposes. Starting from the class of situations that are represented, a STRIPS (the STanford Research Institute Problem Solver)-like formalism and its underlying logic are adapted to the simulation of plans of actions in time. The choice of a temporal logic enables to build a world representation, on which the effects of plans, grouping actions into control structures, will be transcribed by the simulation, resulting in a verdict and information about the plan's coherence.

  1. Quantum probabilistic logic programming

    NASA Astrophysics Data System (ADS)

    Balu, Radhakrishnan

    2015-05-01

    We describe a quantum mechanics based logic programming language that supports Horn clauses, random variables, and covariance matrices to express and solve problems in probabilistic logic. The Horn clauses of the language wrap random variables, including infinite valued, to express probability distributions and statistical correlations, a powerful feature to capture relationship between distributions that are not independent. The expressive power of the language is based on a mechanism to implement statistical ensembles and to solve the underlying SAT instances using quantum mechanical machinery. We exploit the fact that classical random variables have quantum decompositions to build the Horn clauses. We establish the semantics of the language in a rigorous fashion by considering an existing probabilistic logic language called PRISM with classical probability measures defined on the Herbrand base and extending it to the quantum context. In the classical case H-interpretations form the sample space and probability measures defined on them lead to consistent definition of probabilities for well formed formulae. In the quantum counterpart, we define probability amplitudes on Hinterpretations facilitating the model generations and verifications via quantum mechanical superpositions and entanglements. We cast the well formed formulae of the language as quantum mechanical observables thus providing an elegant interpretation for their probabilities. We discuss several examples to combine statistical ensembles and predicates of first order logic to reason with situations involving uncertainty.

  2. Making programmable BMS safe and reliable

    SciTech Connect

    Cusimano, J.A.

    1995-12-01

    Burner management systems ensure safe admission of fuel to the furnace and prevent explosions. This article describes how programmable control systems can be every bit as safe and reliable as hardwired or standard programmable logic controller-based designs. High-pressure boilers are required by regulatory agencies and insurance companies alike to be equipped with a burner management system (BMS) to ensure safe admission of fuel to the furnace and to prevent explosions. These systems work in parallel with, but independently of, the combustion and feedwater control systems that start up, monitor, and shut down burners and furnaces. Safety and reliability are the fundamental requirements of a BMS. Programmable control system for BMS applications are now available that incorporate high safety and reliability into traditional microprocessor-based designs. With one of these control systems, a qualified systems engineer applying relevant standards, such as the National Fire Protection Assn (NFPA) 85 series, can design and implement a superior BMS.

  3. Behavior of faulty double BJT BiCMOS logic gates

    NASA Technical Reports Server (NTRS)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  4. Boolean logic gates that use enzymes as input signals.

    PubMed

    Strack, Guinevere; Pita, Marcos; Ornatska, Maryna; Katz, Evgeny

    2008-05-23

    Biochemical systems that demonstrate the Boolean logic operations AND, OR, XOR, and InhibA were developed by using soluble compounds, which represent the chemical "devices", and the enzymes glucose oxidase (GOx), glucose dehydrogenase (GDH), alcohol dehydrogenase (AlcDH), and microperoxidase-11 (MP-11), which operated as the input signals that activated the logic gates. The enzymes were used as soluble materials and as immobilized biocatalysts. The studied systems are proposed to be a step towards the construction of "smart" signal-responsive materials with built-in Boolean logic.

  5. Logical and pseudo-logical optical fibre networks based on two-state (binary) optical fibre sensors for industrial monitoring and control systems

    NASA Astrophysics Data System (ADS)

    Szczot, Feliks

    2005-09-01

    The possibilities of development of logical and pseudo-logical optical fibre networks for monitoring and control of equipment and industrial sites are presented. Such networks composed of simple binary attenuation and optical fibre communication lines may also be used as fast and reliable systems developing a final command signal - logical and/or pseudo-logical, depending or the architecture of network and the type of located sensors. They realise the process similar to standard electronic logical sets but use the optical signal directly on the monitored or controlled device. The analysis of serial and parallel networks was carried out in the "dark" mode detection. The examples of networks in power industry were presented where technical and economical merits of logical and pseudo-logical monitoring and controlling networks are clearly visible.

  6. Logical stochastic resonance with correlated internal and external noises in a synthetic biological logic block

    NASA Astrophysics Data System (ADS)

    Dari, Anna; Kia, Behnam; Bulsara, Adi R.; Ditto, William L.

    2011-12-01

    Following the advent of synthetic biology, several gene networks have been engineered to emulate digital devices, with the ability to program cells for different applications. In this work, we adapt the concept of logical stochastic resonance to a synthetic gene network derived from a bacteriophage λ. The intriguing results of this study show that it is possible to build a biological logic block that can emulate or switch from the AND to the OR gate functionalities through externally tuning the system parameters. Moreover, this behavior and the robustness of the logic gate are underpinned by the presence of an optimal amount of random fluctuations. We extend our earlier work in this field, by taking into account the effects of correlated external (additive) and internal (multiplicative or state-dependent) noise. Results obtained through analytical calculations as well as numerical simulations are presented.

  7. Conceptual Modeling via Logic Programming

    DTIC Science & Technology

    1990-01-01

    31 2.7 Approaches Other Than Logic Programming ............................. 33 2.7.1 L isp...Development Environment Needs ................................ 84 5.1.4 Alternative Logic Programming Implementation Approaches ......... 85 5.1.5 User... APPROACH and logic programming techniques. Section 2 The CMLP project consisted of three describes the task outputs. interrelated investi ations: 3

  8. Conditional Logic and Primary Children.

    ERIC Educational Resources Information Center

    Ennis, Robert H.

    Conditional logic, as interpreted in this paper, means deductive logic characterized by "if-then" statements. This study sought to investigate the knowledge of conditional logic possessed by primary children and to test their readiness to learn such concepts. Ninety students were designated the experimental group and participated in a…

  9. Fuzzy logic program at SGS-Thomson

    NASA Astrophysics Data System (ADS)

    Pagni, Andrea; Poluzzi, Rinaldo; Rizzotto, GianGuido

    1993-12-01

    From its conception by Professor Lotfi A. Zadeh in the early '60s, Fuzzy Logic has slowly won acceptance, first in the academic world, then in industry. Its success is mainly due to the different perspective with which problems are tackled. Thanks to Fuzzy Logic we have moved from a numerical/analytical description to a quantitative/qualitative one. It is important to stress that this different perspective not only allows us to solve analysis/control problems at lower costs but can also allow otherwise insoluble problems to be solved at acceptable costs. Of course, it must be stressed that Fuzzy Systems cannot match the computational precision of traditional techniques but seek, instead, to find acceptable solutions in shorter times. Recognizing the enormous importance of fuzzy logic in the markets of the future, SGS-THOMSON intends to produce devices belonging to a new class of machines: Fuzzy Computational Machines. For this purpose a major research project has been established considering the architectural aspects and system implications of fuzzy logic, the development of dedicated VLSI components and supporting software.

  10. Fluidic-thermochromic display device

    NASA Technical Reports Server (NTRS)

    Grafstein, D.; Hilborn, E. H.

    1968-01-01

    Fluidic decoder and display device has low-power requirements for temperature control of thermochromic materials. An electro-to-fluid converter translates incoming electrical signals into pneumatics signal of sufficient power to operate the fluidic logic elements.

  11. The Logic of Life.

    PubMed

    Pascal, Robert; Pross, Addy

    2016-11-01

    In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the 'regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both 'regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.

  12. The Logic of Life

    NASA Astrophysics Data System (ADS)

    Pascal, Robert; Pross, Addy

    2016-11-01

    In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the `regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both `regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.

  13. Program to Optimize Simulated Trajectories (POST). Volume 3: Programmer's manual

    NASA Technical Reports Server (NTRS)

    Brauer, G. L.; Cornick, D. E.; Habeger, A. R.; Petersen, F. M.; Stevenson, R.

    1975-01-01

    Information pertinent to the programmer and relating to the program to optimize simulated trajectories (POST) is presented. Topics discussed include: program structure and logic, subroutine listings and flow charts, and internal FORTRAN symbols. The POST core requirements are summarized along with program macrologic.

  14. Radiation Effects on Current Field Programmable Technologies

    NASA Technical Reports Server (NTRS)

    Katz, R.; LaBel, K.; Wang, J. J.; Cronquist, B.; Koga, R.; Penzin, S.; Swift, G.

    1997-01-01

    Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

  15. Mathematical logic in the human brain: semantics.

    PubMed

    Friedrich, Roland M; Friederici, Angela D

    2013-01-01

    As a higher cognitive function in humans, mathematics is supported by parietal and prefrontal brain regions. Here, we give an integrative account of the role of the different brain systems in processing the semantics of mathematical logic from the perspective of macroscopic polysynaptic networks. By comparing algebraic and arithmetic expressions of identical underlying structure, we show how the different subparts of a fronto-parietal network are modulated by the semantic domain, over which the mathematical formulae are interpreted. Within this network, the prefrontal cortex represents a system that hosts three major components, namely, control, arithmetic-logic, and short-term memory. This prefrontal system operates on data fed to it by two other systems: a premotor-parietal top-down system that updates and transforms (external) data into an internal format, and a hippocampal bottom-up system that either detects novel information or serves as an access device to memory for previously acquired knowledge.

  16. Logic gates based on ion transistors.

    PubMed

    Tybrandt, Klas; Forchheimer, Robert; Berggren, Magnus

    2012-05-29

    Precise control over processing, transport and delivery of ionic and molecular signals is of great importance in numerous fields of life sciences. Integrated circuits based on ion transistors would be one approach to route and dispense complex chemical signal patterns to achieve such control. To date several types of ion transistors have been reported; however, only individual devices have so far been presented and most of them are not functional at physiological salt concentrations. Here we report integrated chemical logic gates based on ion bipolar junction transistors. Inverters and NAND gates of both npn type and complementary type are demonstrated. We find that complementary ion gates have higher gain and lower power consumption, as compared with the single transistor-type gates, which imitates the advantages of complementary logics found in conventional electronics. Ion inverters and NAND gates lay the groundwork for further development of solid-state chemical delivery circuits.

  17. Mathematical Logic in the Human Brain: Semantics

    PubMed Central

    Friedrich, Roland M.; Friederici, Angela D.

    2013-01-01

    As a higher cognitive function in humans, mathematics is supported by parietal and prefrontal brain regions. Here, we give an integrative account of the role of the different brain systems in processing the semantics of mathematical logic from the perspective of macroscopic polysynaptic networks. By comparing algebraic and arithmetic expressions of identical underlying structure, we show how the different subparts of a fronto-parietal network are modulated by the semantic domain, over which the mathematical formulae are interpreted. Within this network, the prefrontal cortex represents a system that hosts three major components, namely, control, arithmetic-logic, and short-term memory. This prefrontal system operates on data fed to it by two other systems: a premotor-parietal top-down system that updates and transforms (external) data into an internal format, and a hippocampal bottom-up system that either detects novel information or serves as an access device to memory for previously acquired knowledge. PMID:23301101

  18. The connection between logical and thermodynamic irreversibility

    NASA Astrophysics Data System (ADS)

    Ladyman, James; Presnell, Stuart; Short, Anthony J.; Groisman, Berry

    There has recently been a good deal of controversy about Landauer's Principle, which is often stated as follows: the erasure of one bit of information in a computational device is necessarily accompanied by a generation of kT ln 2 heat. This is often generalised to the claim that any logically irreversible operation cannot be implemented in a thermodynamically reversible way. Norton [2005. Eaters of the lotus: Landauer's principle and the return of Maxwell's demon. Studies in History and Philosophy of Modern Physics, 36, 375-411] and Maroney [2005. The (absence of a) relationship between thermodynamic and logical reversibility. Studies in History and Philosophy of Modern Physics, 36, 355-374] both argue that Landauer's Principle has not been shown to hold in general, and Maroney offers a method that he claims instantiates the operation Reset in a thermodynamically reversible way. In this paper we defend the qualitative form of Landauer's Principle, and clarify its quantitative consequences (assuming the second law of thermodynamics). We analyse in detail what it means for a physical system to implement a logical transformation L, and we make this precise by defining the notion of an L-machine. Then we show that logical irreversibility of L implies thermodynamic irreversibility of every corresponding L-machine. We do this in two ways. First, by assuming the phenomenological validity of the Kelvin statement of the second law, and second, by using information-theoretic reasoning. We illustrate our results with the example of the logical transformation 'Reset', and thereby recover the quantitative form of Landauer's Principle.

  19. Addition of flexible body option to the TOLA computer program. Part 2: User and programmer documentation

    NASA Technical Reports Server (NTRS)

    Dick, J. W.; Benda, B. J.

    1975-01-01

    User and programmer oriented documentation for the flexible body option of the Takeoff and Landing Analysis (TOLA) computer program are provided. The user information provides sufficient knowledge of the development and use of the option to enable the engineering user to successfully operate the modified program and understand the results. The programmer's information describes the option structure and logic enabling a programmer to make major revisions to this part of the TOLA computer program.

  20. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    SciTech Connect

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-21

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  1. A reconfigurable NAND/NOR genetic logic gate

    PubMed Central

    2012-01-01

    Background Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. Results We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. Conclusions We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications. PMID:22989145

  2. Novel Ferroelectric CMOS Circuits as a Nonvolatile Logic

    NASA Astrophysics Data System (ADS)

    Takahashi, M.; Horiuchi, T.; Li, Q.-H.; Wang, S.; Yun, K. Y.; Sakai, S.

    2008-03-01

    We propose a novel and promising nonvolatile-logic circuit constructed by p channel type (Pch) and n channel type (Nch) ferroelectric gate field effect transistors (FeFETs), which we named a ferroelectric CMOS (FeCMOS) circuit. The circuit works as both logic and memory. We fabricated a NOT logic FeCMOS device which have Pt metal gates and gate oxides of ferroelectric SrBi2Ta2O9 (SBT) and high-k HfAlO on Si. Key technology was adjusting threshold voltages of the FeFETs as well as preparing those of high quality. We demonstrate basic operations of the NOT-logic response, memory writing, holding and non-destructive reading. The memory writing is done by amplifying the input node voltage to a higher level when the node was logically high and to a lower one when it was logically low just before the writing operation. The data retention was also measured. The retained high and low voltages were almost unchanged for 1.2 days. The idea of this FeCMOS will enhance flexibility of circuit designing by merging logic and memory functions. This work was partially supported by NEDO.

  3. Substructural Logical Specifications

    DTIC Science & Technology

    2012-11-14

    a more natural correspondence with our physical intuitions about consumable resources. Linear conjunction A ⊗ B (“A tensor B”) represents the...sketch a radically different, vaguely Feynman - diagram-inspired, way of presenting traces in Figure 4.14. Resources are the edges in the DAG and steps or...70th Birthday, volume 17 of Studies in Logic. College Publications, 2008. 3.3.3, 4.1.2, 4.7.3 [Pfe12a] Frank Pfenning. Lecture notes on backtracking

  4. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  5. Gallium arsenide processing for gate array logic

    NASA Astrophysics Data System (ADS)

    Cole, Eric D.

    1989-09-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  6. Application of digital pulse delay device in range-gated control for range-gated imaging lidar

    NASA Astrophysics Data System (ADS)

    Yuan, Chaokai; Chen, Siying; Zhang, Yinchao; Qiu, Zongjia; Ni, Guoqiang

    2009-11-01

    Digital pulse delay device is one of the key techniques of range-gated imaging lidar. At present, Digital method and analog method are the two main implementations of pulse delay device. Digital method is mainly achieved by counter or FIFO memory. With the development of Complex Programmable Logic Device (CPLD), the digital delay device can be achieved with a single chip of CPLD. With this method, the digital delay device enjoys the advantages of high integration, high reliability and strong ability of anti-electromagnetic interference. However, since the maximum clock frequency of CPLD is limited, the improvement of temporal resolution is restricted. Analog method is mainly realized by the delay-line, which is one of the dedicated integrated circuit. Using this method, a higher time resolution can be arrived. In this paper, the timing characteristics of the delay signal are analyzed. Three design options are presented and the advantages and deficiencies are discussed. Based on the theoretical analysis and numerical simulation, the digital delay device combined with the delay chip AD9501 and Field Programmable Gate Array (FPGA) is chosen because of its large dynamic range and high accuracy. Besides, the output pulse width can be adjusted conveniently. The digital delay device is simulated and the result shows that the delay control for range-gated imaging lidar is feasible.

  7. Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control.

    PubMed

    Geier, Michael L; Prabhumirashi, Pradyumna L; McMorrow, Julian J; Xu, Weichao; Seo, Jung-Woo T; Everaerts, Ken; Kim, Chris H; Marks, Tobin J; Hersam, Mark C

    2013-10-09

    In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

  8. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

    NASA Astrophysics Data System (ADS)

    Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.

    2016-01-01

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.

  9. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

    PubMed Central

    Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.

    2016-01-01

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412

  10. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls.

    PubMed

    Currivan-Incorvia, J A; Siddiqui, S; Dutta, S; Evarts, E R; Zhang, J; Bono, D; Ross, C A; Baldo, M A

    2016-01-12

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.

  11. A single nano cantilever as a reprogrammable universal logic gate

    NASA Astrophysics Data System (ADS)

    Chappanda, K. N.; Ilyas, S.; Kazmi, S. N. R.; Holguin-Lerma, J.; Batra, N. M.; Costa, P. M. F. J.; Younis, M. I.

    2017-04-01

    The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.

  12. Rapidly Reconfigurable All-Optical Universal Logic Gates

    SciTech Connect

    Goddard, L L; Kallman, J S; Bond, T C

    2006-06-21

    We present designs and simulations for a highly cascadable, rapidly reconfigurable, all-optical, universal logic gate. We will discuss the gate's expected performance, e.g. speed, fanout, and contrast ratio, as a function of the device layout and biasing conditions. The gate is a three terminal on-chip device that consists of: (1) the input optical port, (2) the gate selection port, and (3) the output optical port. The device can be built monolithically using a standard multiple quantum well graded index separate confinement heterostructure laser configuration. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog electrical or optical signal at the gate selection port. Specifically, the same gate can be selected to execute one of the 2 basic unary operations (NOT or COPY), or one of the 6 binary operations (OR, XOR, AND, NOR, XNOR, or NAND), or one of the many logic operations involving more than two inputs. The speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal modulation speed of a laser, which can be on the order of tens of GHz. The reprogrammable nature of the universal gate offers maximum flexibility and interchangeability for the end user since the entire application of a photonic integrated circuit built from cascaded universal logic gates can be changed simply by adjusting the gate selection port signals.

  13. A Very Small Logical Qubit

    NASA Astrophysics Data System (ADS)

    Kapit, Eliot

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven SQUID couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multi-qubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of forty or more compared to the individual qubit T1 and T2 using this technique.

  14. Programmable multi-node quantum network design and simulation

    NASA Astrophysics Data System (ADS)

    Dasari, Venkat R.; Sadlier, Ronald J.; Prout, Ryan; Williams, Brian P.; Humble, Travis S.

    2016-05-01

    Software-defined networking offers a device-agnostic programmable framework to encode new network functions. Externally centralized control plane intelligence allows programmers to write network applications and to build functional network designs. OpenFlow is a key protocol widely adopted to build programmable networks because of its programmability, flexibility and ability to interconnect heterogeneous network devices. We simulate the functional topology of a multi-node quantum network that uses programmable network principles to manage quantum metadata for protocols such as teleportation, superdense coding, and quantum key distribution. We first show how the OpenFlow protocol can manage the quantum metadata needed to control the quantum channel. We then use numerical simulation to demonstrate robust programmability of a quantum switch via the OpenFlow network controller while executing an application of superdense coding. We describe the software framework implemented to carry out these simulations and we discuss near-term efforts to realize these applications.

  15. An SEU immune logic family

    NASA Technical Reports Server (NTRS)

    Canaris, J.

    1991-01-01

    A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.

  16. Reduced Precision Redundancy Applied to Arithmetic Operations in Field Programmable Gate Arrays for Satellite Control and Sensor Systems

    DTIC Science & Technology

    2008-12-01

    three times the programmable logic space on an FPGA as that required by the unprotected circuit . This thesis addresses the theory that Reduced...software.” Many software radio designers use SRAM-based FPGAs for digital data processing because they can handle more complex circuits than programmable...evident when designers take advantage of parallel processing architectures allowed by FPGA logic block configurations. FPGAs also offer great

  17. Surface-confined assemblies and polymers for molecular logic.

    PubMed

    de Ruiter, Graham; van der Boom, Milko E

    2011-08-16

    Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the

  18. Construction of a fuzzy and Boolean logic gates based on DNA.

    PubMed

    Zadegan, Reza M; Jepsen, Mette D E; Hildebrandt, Lasse L; Birkedal, Victoria; Kjems, Jørgen

    2015-04-17

    Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics.

  19. Shape-programmable macromolecules.

    PubMed

    Schafmeister, Christian E; Brown, Zachary Z; Gupta, Sharad

    2008-10-01

    Proteins catalyze specific chemical reactions and carry out highly selective molecular recognition because they adopt well-defined three-dimensional structures and position chemically reactive functional groups in specific constellations. Proteins attain these well-defined structures through the complex process of protein folding. We seek to emulate these protein functions by constructing macromolecules that are easier to engineer by avoiding folding altogether. Toward that goal, we have developed an approach for the synthesis of macromolecules with programmable shapes. As described in this Account, we have constructed synthetic building blocks called bis-amino acids that we then couple through pairs of amide bonds to create water-soluble, spiroladder oligomers (bis-peptides) with well-defined three-dimensional structures. Bis-peptides use the conformational preferences of fused rings, stereochemistry, and strong covalent bonds to define their shape, unlike natural proteins and synthetic foldamers, which depend on noncovalent interactions and an unpredictable folding process to attain structure. Using these bis-amino acid monomers, we have built and characterized a number of bis-peptide nanostructures. We also constructed a molecular actuator that undergoes a large change in conformation under the control of metal exchange; the first application of bis-peptides. We are currently developing further approaches to functionalize bis-peptides as scaffolds to present well-defined constellations of functional groups. Such macromolecules could facilitate multifunctional catalysis and molecular recognition and lead to nanoscale molecular devices.

  20. Parsing with logical variables (logic-based programming systems)

    SciTech Connect

    Finin, T.W.; Stone Palmer, M.

    1983-01-01

    Logic based programming systems have enjoyed an increasing popularity in applied AI work in the last few years. One of the contributions to computational linguistics made by the logic programming paradigm has been the definite clause grammar. In comparing DCGS with previous parsing mechanisms such as ATNS, certain clear advantages are seen. The authors feel that the most important of these advantages are due to the use of logical variables with unification as the fundamental operation on them. To illustrate the power of the logical variable, they have implemented an experimental atn system which treats atn registers as logical variables and provides a unification operation over them. They aim to simultaneously encourage the use of the powerful mechanisms available in DCGS and demonstrate that some of these techniques can be captured without reference to a resolution theorem prover. 14 references.

  1. Photonic Programmable Tele-Cloning Network

    PubMed Central

    Li, Wei; Chen, Ming-Cheng

    2016-01-01

    The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling. PMID:27353838

  2. Photonic Programmable Tele-Cloning Network

    NASA Astrophysics Data System (ADS)

    Li, Wei; Chen, Ming-Cheng

    2016-06-01

    The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling.

  3. Photonic Programmable Tele-Cloning Network.

    PubMed

    Li, Wei; Chen, Ming-Cheng

    2016-06-29

    The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling.

  4. Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures

    NASA Technical Reports Server (NTRS)

    Rickard, D. A.; Bodenheimer, R. E.

    1976-01-01

    Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.

  5. Auto-programmable impulse neural circuits

    NASA Technical Reports Server (NTRS)

    Watula, D.; Meador, J.

    1990-01-01

    Impulse neural networks use pulse trains to communicate neuron activation levels. Impulse neural circuits emulate natural neurons at a more detailed level than that typically employed by contemporary neural network implementation methods. An impulse neural circuit which realizes short term memory dynamics is presented. The operation of that circuit is then characterized in terms of pulse frequency modulated signals. Both fixed and programmable synapse circuits for realizing long term memory are also described. The implementation of a simple and useful unsupervised learning law is then presented. The implementation of a differential Hebbian learning rule for a specific mean-frequency signal interpretation is shown to have a straightforward implementation using digital combinational logic with a variation of a previously developed programmable synapse circuit. This circuit is expected to be exploited for simple and straightforward implementation of future auto-adaptive neural circuits.

  6. The cognitive bases for the design of a new class of fuzzy logic controllers: The clearness transformation fuzzy logic controller

    NASA Technical Reports Server (NTRS)

    Sultan, Labib; Janabi, Talib

    1992-01-01

    This paper analyses the internal operation of fuzzy logic controllers as referenced to the human cognitive tasks of control and decision making. Two goals are targeted. The first goal focuses on the cognitive interpretation of the mechanisms employed in the current design of fuzzy logic controllers. This analysis helps to create a ground to explore the potential of enhancing the functional intelligence of fuzzy controllers. The second goal is to outline the features of a new class of fuzzy controllers, the Clearness Transformation Fuzzy Logic Controller (CT-FLC), whereby some new concepts are advanced to qualify fuzzy controllers as 'cognitive devices' rather than 'expert system devices'. The operation of the CT-FLC, as a fuzzy pattern processing controller, is explored, simulated, and evaluated.

  7. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  8. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  9. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  10. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  11. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  12. Mechanically Flexible and High-Performance CMOS Logic Circuits

    PubMed Central

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  13. Mechanically Flexible and High-Performance CMOS Logic Circuits.

    PubMed

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-10-13

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

  14. A Logical Process Calculus

    NASA Technical Reports Server (NTRS)

    Cleaveland, Rance; Luettgen, Gerald; Bushnell, Dennis M. (Technical Monitor)

    2002-01-01

    This paper presents the Logical Process Calculus (LPC), a formalism that supports heterogeneous system specifications containing both operational and declarative subspecifications. Syntactically, LPC extends Milner's Calculus of Communicating Systems with operators from the alternation-free linear-time mu-calculus (LT(mu)). Semantically, LPC is equipped with a behavioral preorder that generalizes Hennessy's and DeNicola's must-testing preorder as well as LT(mu's) satisfaction relation, while being compositional for all LPC operators. From a technical point of view, the new calculus is distinguished by the inclusion of: (1) both minimal and maximal fixed-point operators and (2) an unimple-mentability predicate on process terms, which tags inconsistent specifications. The utility of LPC is demonstrated by means of an example highlighting the benefits of heterogeneous system specification.

  15. The Early Development of Programmable Machinery.

    ERIC Educational Resources Information Center

    Collins, Martin D.

    1985-01-01

    Programmable equipment innovations, precursors of today's technology, are examined, including the development of the binary code and feedback control systems, such as temperature sensing devices, interchangeable parts, punched cards carrying instructions, continuous flow oil refining process, assembly lines for mass production, and the…

  16. Logic, reasoning, and verbal behavior

    PubMed Central

    Terrell, Dudley J.; Johnston, J. M.

    1989-01-01

    This paper analyzes the traditional concepts of logic and reasoning from the perspective of radical behaviorism and in the terms of Skinner's treatment of verbal behavior. The topics covered in this analysis include the proposition, premises and conclusions, logicality and rules, and deductive and inductive reasoning. PMID:22478015

  17. Simulated Laboratory in Digital Logic.

    ERIC Educational Resources Information Center

    Cleaver, Thomas G.

    Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

  18. Binary logic is rich enough

    SciTech Connect

    Zapatrin, R.R.

    1992-02-01

    Given a finite ortholattice L, the *-semigroup is explicitly built whose annihilator ortholattice is isomorphic to L. Thus, it is shown that any finite quantum logic is the additive part of a binary logic. Some areas of possible applications are outlined. 7 refs.

  19. Logic and the National Curriculum.

    ERIC Educational Resources Information Center

    Nelson, David

    2000-01-01

    Reviews the historic relationship between logic and the mathematics curriculum. Proposes a list of logical elements for modern school mathematics. Checks the current national curriculum against this list and finds it to be deficient, especially in relation to the development of ideas of proof. Presents arguments for reform. (Contains 29…

  20. Programmable convolution via the chirp Z-transform with CCD's

    NASA Technical Reports Server (NTRS)

    Buss, D. D.

    1977-01-01

    Technique filtering by convolution in frequency domain rather than in time domain presents possible solution to problem of programmable transversal filters. Process is accomplished through utilization of chip z-transform (CZT) with charge-coupled devices

  1. Weighted Automata and Weighted Logics

    NASA Astrophysics Data System (ADS)

    Droste, Manfred; Gastin, Paul

    In automata theory, a fundamental result of Büchi and Elgot states that the recognizable languages are precisely the ones definable by sentences of monadic second order logic. We will present a generalization of this result to the context of weighted automata. We develop syntax and semantics of a quantitative logic; like the behaviors of weighted automata, the semantics of sentences of our logic are formal power series describing ‘how often’ the sentence is true for a given word. Our main result shows that if the weights are taken in an arbitrary semiring, then the behaviors of weighted automata are precisely the series definable by sentences of our quantitative logic. We achieve a similar characterization for weighted Büchi automata acting on infinite words, if the underlying semiring satisfies suitable completeness assumptions. Moreover, if the semiring is additively locally finite or locally finite, then natural extensions of our weighted logic still have the same expressive power as weighted automata.

  2. Power optimization in logic isomers

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.

  3. MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic

    PubMed Central

    Jaiswal, Akhilesh; Roy, Kaushik

    2017-01-01

    In the quest for novel, scalable and energy-efficient computing technologies, many non-charge based logic devices are being explored. Recent advances in multi-ferroic materials have paved the way for electric field induced low energy and fast switching of nano-magnets using the magneto-electric (ME) effect. In this paper, we propose a voltage driven logic-device based on the ME induced switching of nano-magnets. We further demonstrate that the proposed logic-device, which exhibits decoupled read and write paths, can be used to construct a complete logic family including XNOR, NAND and NOR gates. The proposed logic family shows good scalability with a quadratic dependence of switching energy with respect to the switching voltage. Further, the proposed logic-device has better robustness against the effect of thermal noise as compared to the conventional current driven switching of nano-magnets. A device-to-circuit level coupled simulation framework, including magnetization dynamics and electron transport model, has been developed for analyzing the present proposal. Using our simulation framework, we present energy and delay results for the proposed Magneto-Electric Spin Logic (MESL) gates. PMID:28045074

  4. MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic

    NASA Astrophysics Data System (ADS)

    Jaiswal, Akhilesh; Roy, Kaushik

    2017-01-01

    In the quest for novel, scalable and energy-efficient computing technologies, many non-charge based logic devices are being explored. Recent advances in multi-ferroic materials have paved the way for electric field induced low energy and fast switching of nano-magnets using the magneto-electric (ME) effect. In this paper, we propose a voltage driven logic-device based on the ME induced switching of nano-magnets. We further demonstrate that the proposed logic-device, which exhibits decoupled read and write paths, can be used to construct a complete logic family including XNOR, NAND and NOR gates. The proposed logic family shows good scalability with a quadratic dependence of switching energy with respect to the switching voltage. Further, the proposed logic-device has better robustness against the effect of thermal noise as compared to the conventional current driven switching of nano-magnets. A device-to-circuit level coupled simulation framework, including magnetization dynamics and electron transport model, has been developed for analyzing the present proposal. Using our simulation framework, we present energy and delay results for the proposed Magneto-Electric Spin Logic (MESL) gates.

  5. LSI/VLSI (Large Scale Integration/Very Large Scale Integration) ion implanted GaAs (Gallium Arsenide) IC processing. Appendix B: Two-dimensional modeling of GaAs MESFET devices for integrated high-speed logic circuits

    NASA Astrophysics Data System (ADS)

    Zucca, R. R.; Kirkpatrick, C. G.; Asbeck, P. M.; Eisen, F. H.; Lee, C. P.

    1984-01-01

    This report summarizes the research carried out at North Carolina State University in support of the Rockwell International Program on LSI-VLSI Ion Implanted Planar GaAs IC Processing. The major thrust of the program at NCSU was to develop accurate computer models for analyzing the performance of short-channel GaAs MESFET devices as used in the Rockwell VLSI circuits. The modeling research is divided into three parts: (1) Two-dimensional finite difference simulation, (2) Two-dimensional Monte Carlo analysis, and (3) Analytical modeling. The intent was to use the two-dimensional analyses to give exact solutions to the device operation and to serve as a guide for developing a simpler, and less expensive, analytical model of sufficient accuracy to be valuable as a design aid and to study effects of parameter changes.

  6. Realization of morphing logic gates in a repressilator with quorum sensing feedback

    NASA Astrophysics Data System (ADS)

    Agrawal, Vidit; Kang, Shivpal Singh; Sinha, Sudeshna

    2014-03-01

    We demonstrate how a genetic ring oscillator network with quorum sensing feedback can operate as a robust logic gate. Specifically we show how a range of logic functions, namely AND/NAND, OR/NOR and XOR/XNOR, can be realized by the system, thus yielding a versatile unit that can morph between different logic operations. We further demonstrate the capacity of this system to yield complementary logic operations in parallel. Our results then indicate the computing potential of this biological system, and may lead to bio-inspired computing devices.

  7. N channel JFET based digital logic gate structure

    NASA Technical Reports Server (NTRS)

    Krasowski, Michael J. (Inventor)

    2010-01-01

    A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

  8. Computerized logic design of digital circuits

    NASA Technical Reports Server (NTRS)

    Gussow, S.; Oglesby, R.

    1974-01-01

    Procedure performs all work required for logic design of digital counters or sequential circuits and simplification of Boolean expressions. Program provides simple, accurate, and comprehensive logic design capability to users both experienced and totally inexperienced in logic design

  9. Note: a 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy.

    PubMed

    Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A M

    2012-09-01

    We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

  10. Note: A 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy

    NASA Astrophysics Data System (ADS)

    Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A. M.

    2012-09-01

    We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

  11. Photonic encryption : modeling and functional analysis of all optical logic.

    SciTech Connect

    Tang, Jason D.; Schroeppel, Richard Crabtree; Robertson, Perry J.

    2004-10-01

    With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. This paper documents the innovations and advances of work first detailed in 'Photonic Encryption using All Optical Logic,' [1]. A discussion of underlying concepts can be found in SAND2003-4474. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines S-SEED devices and how discrete logic elements can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of S-SEED devices in an optical circuit was modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay

  12. R-189 (C-620) air compressor control logic software documentation. Revision 1

    SciTech Connect

    Walter, K.E.

    1995-06-08

    This relates to FFTF plant air compressors. Purpose of this document is to provide an updated Computer Software Description for the software to be used on R-189 (C-620-C) air compressor programmable controllers. Logic software design changes were required to allow automatic starting of a compressor that had not been previously started.

  13. A DNAzyme-mediated logic gate for programming molecular capture and release on DNA origami.

    PubMed

    Li, Feiran; Chen, Haorong; Pan, Jing; Cha, Tae-Gon; Medintz, Igor L; Choi, Jong Hyun

    2016-06-28

    Here we design a DNA origami-based site-specific molecular capture and release platform operated by a DNAzyme-mediated logic gate process. We show the programmability and versatility of this platform with small molecules, proteins, and nanoparticles, which may also be controlled by external light signals.

  14. School Inclusion Programmes (SIPS)

    ERIC Educational Resources Information Center

    Drossinou-Korea, Maria; Matousi, Dimitra; Panopoulos, Nikolaos; Paraskevopoulou, Aikaterini

    2016-01-01

    The purpose of this work was to understand the school inclusion programmes (SIPs) for students with special educational needs (SEN). The methodology was conducted in the field of special education (SE) and focuses on three case studies of students who was supported by SIPs. The Targeted, Individual, Structured, Inclusion Programme for students…

  15. Using LogicWorks to Teach Logic Design.

    ERIC Educational Resources Information Center

    Spoerri, Peter

    1988-01-01

    Discusses a computer simulation to teach logic design using a Macintosh computer which allows circuits to be built piece by piece. Describes features of the simulation and presents several schematics drawn by the software. (MVL)

  16. Suicide as social logic.

    PubMed

    Kral, M J

    1994-01-01

    Although suicide is not viewed as a mental disorder per se, it is viewed by many if not most clinicians, researchers, and lay people as a real or natural symptom of depression. It is at least most typically seen as the unfortunate, severe, yet logical end result of a chain of negative self-appraisals, negative events, and hopelessness. Extending an approach articulated by the early French sociologist Gabriel Tarde, in this paper I argue that suicide is merely an idea, albeit a very bad one, having more in common with societal beliefs and norms regarding such things as divorce, abortion, sex, politics, consumer behavior, and fashion. I make a sharp contrast between perturbation and lethality, concepts central to Edwin S. Shneidman's theory of suicide. Evidence supportive of suicide as an idea is discussed based on what we are learning from the study of history and culture, and about contagion/cluster phenomena, media/communication, and choice of method. It is suggested that certain individuals are more vulnerable to incorporate the idea and act of suicide into their concepts of self, based on the same principles by which ideas are spread throughout society. Just as suicide impacts on society, so does society impact on suicide.

  17. The Logic of Reachability

    NASA Technical Reports Server (NTRS)

    Smith, David E.; Jonsson, Ari K.; Clancy, Daniel (Technical Monitor)

    2001-01-01

    In recent years, Graphplan style reachability analysis and mutual exclusion reasoning have been used in many high performance planning systems. While numerous refinements and extensions have been developed, the basic plan graph structure and reasoning mechanisms used in these systems are tied to the very simple STRIPS model of action. In 1999, Smith and Weld generalized the Graphplan methods for reachability and mutex reasoning to allow actions to have differing durations. However, the representation of actions still has some severe limitations that prevent the use of these techniques for many real-world planning systems. In this paper, we 1) separate the logic of reachability from the particular representation and inference methods used in Graphplan, and 2) extend the notions of reachability and mutual exclusion to more general notions of time and action. As it turns out, the general rules for mutual exclusion reasoning take on a remarkably clean and simple form. However, practical instantiations of them turn out to be messy, and require that we make representation and reasoning choices.

  18. Integrated all-optical logic discriminators based on plasmonic bandgap engineering

    PubMed Central

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2013-01-01

    Optical computing uses photons as information carriers, opening up the possibility for ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic devices are indispensible core components of optical computing systems. However, up to now, little experimental progress has been made in nanoscale all-optical logic discriminators, which have the function of discriminating and encoding incident light signals according to wavelength. Here, we report a strategy to realize a nanoscale all-optical logic discriminator based on plasmonic bandgap engineering in a planar plasmonic microstructure. Light signals falling within different operating wavelength ranges are differentiated and endowed with different logic state encodings. Compared with values previously reported, the operating bandwidth is enlarged by one order of magnitude. Also the SPP light source is integrated with the logic device while retaining its ultracompact size. This opens up a way to construct on-chip all-optical information processors and artificial intelligence systems. PMID:24071647

  19. Formalized Epistemology, Logic, and Grammar

    NASA Astrophysics Data System (ADS)

    Bitbol, Michel

    The task of a formal epistemology is defined. It appears that a formal epistemology must be a generalization of "logic" in the sense of Wittgenstein's Tractatus. The generalization is required because, whereas logic presupposes a strict relation between activity and language, this relation may be broken in some domains of experimental enquiry (e.g., in microscopic physics). However, a formal epistemology should also retain a major feature of Wittgenstein's "logic": It must not be a discourse about scientific knowledge, but rather a way of making manifest the structures usually implicit in knowledge-gaining activity. This strategy is applied to the formalism of quantum mechanics.

  20. Early monitoring results of two voltage sag ride-through devices at a plastics extrusion plant

    SciTech Connect

    Ray, L.A.; Lamoree, J.; Peele, G.S.; Samotyj, M.

    1995-06-01

    Voltage sag mitigation techniques command attention in the power quality arena today due to the increasing numbers of sensitive process loads connected to the utility distribution system. This paper presents monitoring results related to the performance of two such devices applied in different levels of voltage sag coverage. The superconducting storage device is designed to protect sensitive loads without the normal segregation of large-power loads (drives, motors) from low-power/high sensitivity machines (computers, programmable logic controllers). The magnetic synthesizer in this case study protects control circuits and requires separation of these circuits from other loads within the sensitive machine. Both methods are effective in reducing process shutdowns due to voltage sags. Their relative economy depends on the type of disturbances affecting the process and the amount of the customer`s economic losses.

  1. Programmable computing with a single magnetoresistive element

    NASA Astrophysics Data System (ADS)

    Ney, A.; Pampuch, C.; Koch, R.; Ploog, K. H.

    2003-10-01

    The development of transistor-based integrated circuits for modern computing is a story of great success. However, the proved concept for enhancing computational power by continuous miniaturization is approaching its fundamental limits. Alternative approaches consider logic elements that are reconfigurable at run-time to overcome the rigid architecture of the present hardware systems. Implementation of parallel algorithms on such `chameleon' processors has the potential to yield a dramatic increase of computational speed, competitive with that of supercomputers. Owing to their functional flexibility, `chameleon' processors can be readily optimized with respect to any computer application. In conventional microprocessors, information must be transferred to a memory to prevent it from getting lost, because electrically processed information is volatile. Therefore the computational performance can be improved if the logic gate is additionally capable of storing the output. Here we describe a simple hardware concept for a programmable logic element that is based on a single magnetic random access memory (MRAM) cell. It combines the inherent advantage of a non-volatile output with flexible functionality which can be selected at run-time to operate as an AND, OR, NAND or NOR gate.

  2. Digital logic testing and testability

    NASA Astrophysics Data System (ADS)

    Debany, Warren H., Jr.

    1991-02-01

    Electronic hardware is subject to defects that are introduced at the time of manufacture and failures that occur in the field. Because of the complexity of digital logic circuits, they are difficult to test. This report provides an overview of digital logic testing. It provides access to the literature and unifies terminology and concepts that have evolved in this field. It discusses the types and causes of failures in digital logic. This report presents the topics of logic and fault simulation, fault grading, test generation algorithms, and fault isolation. The discussion of testability measurement is useful for understanding testability requirements and analysis techniques. Design-for-testability and built in test techniques are presented.

  3. Knowledge representation in fuzzy logic

    NASA Technical Reports Server (NTRS)

    Zadeh, Lotfi A.

    1989-01-01

    The author presents a summary of the basic concepts and techniques underlying the application of fuzzy logic to knowledge representation. He then describes a number of examples relating to its use as a computational system for dealing with uncertainty and imprecision in the context of knowledge, meaning, and inference. It is noted that one of the basic aims of fuzzy logic is to provide a computational framework for knowledge representation and inference in an environment of uncertainty and imprecision. In such environments, fuzzy logic is effective when the solutions need not be precise and/or it is acceptable for a conclusion to have a dispositional rather than categorical validity. The importance of fuzzy logic derives from the fact that there are many real-world applications which fit these conditions, especially in the realm of knowledge-based systems for decision-making and control.

  4. Emerging Standards for Medical Logic

    PubMed Central

    Clayton, Paul D.; Hripcsak, George; Pryor, T. Allan

    1990-01-01

    Sharing medical logic has traditionally occurred in the form of lectures, conversations, books and journals. As knowledge based computer systems have demonstrated their utility in the health care arena, individuals have pondered the best way to transfer knowledge in a computer based representation (1). A simple representation which allows the knowledge to be shared can be constructed when the knowledge base is modular. Within this representation, units have been named Medical Logic Modules (MLM's) and a syntax has emerged which would allow multiple users to create, criticize, and share those types of medical logic which can be represented in this format. In this paper we talk about why standards exist and why they emerge in some areas and not in others. The appropriateness of using the proposed standards for medical logic modules is then examined against this broader context.

  5. Logic, Probability, and Human Reasoning

    DTIC Science & Technology

    2015-01-01

    logics developed in artificial intelligence, which allow conclusions to be withdrawn [38–42]. Second, conditional assertions (e.g., ‘If she insulted him...N. (2014) Probabilistic single function dual process theory and logic programming as approaches to non- monotonicity in human vs artificial reasoning...How can we solve this crisis? Leibniz dreamed of a calculus that settles any argument. Can cognitive scientists devise such a system? Feature

  6. Heat exchanger expert system logic

    NASA Technical Reports Server (NTRS)

    Cormier, R.

    1988-01-01

    The reduction is described of the operation and fault diagnostics of a Deep Space Network heat exchanger to a rule base by the application of propositional calculus to a set of logic statements. The value of this approach lies in the ease of converting the logic and subsequently implementing it on a computer as an expert system. The rule base was written in Process Intelligent Control software.

  7. Multichannel optical sensing device

    DOEpatents

    Selkowitz, S.E.

    1985-08-16

    A multichannel optical sensing device is disclosed, for measuring the outdoor sky luminance or illuminance or the luminance or illuminance distribution in a room, comprising a plurality of light receptors, an optical shutter matrix including a plurality of liquid crystal optical shutter elements operable by electrical control signals between light transmitting and light stopping conditions, fiber optical elements connected between the receptors and the shutter elements, a microprocessor based programmable control unit for selectively supplying control signals to the optical shutter elements in a programmable sequence, a photodetector including an optical integrating spherical chamber having an input port for receiving the light from the shutter matrix and at least one detector element in the spherical chamber for producing output signals corresponding to the light, and output units for utilizing the output signals including a storage unit having a control connection to the microprocessor based programmable control unit for storing the output signals under the sequence control of the programmable control unit.

  8. Multichannel optical sensing device

    DOEpatents

    Selkowitz, Stephen E.

    1990-01-01

    A multichannel optical sensing device is disclosed, for measuring the outr sky luminance or illuminance or the luminance or illuminance distribution in a room, comprising a plurality of light receptors, an optical shutter matrix including a plurality of liquid crystal optical shutter elements operable by electrical control signals between light transmitting and light stopping conditions, fiber optic elements connected between the receptors and the shutter elements, a microprocessor based programmable control unit for selectively supplying control signals to the optical shutter elements in a programmable sequence, a photodetector including an optical integrating spherical chamber having an input port for receiving the light from the shutter matrix and at least one detector element in the spherical chamber for producing output signals corresponding to the light, and output units for utilizing the output signals including a storage unit having a control connection to the microprocessor based programmable control unit for storing the output signals under the sequence control of the programmable control unit.

  9. Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

    NASA Technical Reports Server (NTRS)

    Straka, Bartholomew

    2013-01-01

    Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

  10. Magnon-based logic in a multi-terminal YIG/Pt nanostructure

    NASA Astrophysics Data System (ADS)

    Ganzhorn, Kathrin; Klingler, Stefan; Wimmer, Tobias; Geprägs, Stephan; Gross, Rudolf; Huebl, Hans; Goennenwein, Sebastian T. B.

    2016-07-01

    Boolean logic is the foundation of modern digital information processing. Recently, there has been a growing interest in phenomena based on pure spin currents, which allows to move from charge to spin based logic gates. We study a proof-of-principle logic device based on the ferrimagnetic insulator Yttrium Iron Garnet, with Pt strips acting as injectors and detectors for non-equilibrium magnons. We experimentally observe incoherent superposition of magnons generated by different injectors. This allows to implement a fully functional majority gate, enabling multiple logic operations (AND and OR) in one and the same device. Clocking frequencies of the order of several GHz and straightforward down-scaling make our device promising for applications.

  11. Transverse Domain Wall Profile for Spin Logic Applications

    PubMed Central

    Goolaup, S.; Ramu, M.; Murapaka, C.; Lew, W. S.

    2015-01-01

    Domain wall (DW) based logic and memory devices require precise control and manipulation of DW in nanowire conduits. The topological defects of Transverse DWs (TDW) are of paramount importance as regards to the deterministic pinning and movement of DW within complex networks of conduits. In-situ control of the DW topological defects in nanowire conduits may pave the way for novel DW logic applications. In this work, we present a geometrical modulation along a nanowire conduit, which allows for the topological rectification/inversion of TDW in nanowires. This is achieved by exploiting the controlled relaxation of the TDW within an angled rectangle. Direct evidence of the logical operation is obtained via magnetic force microscopy measurement. PMID:25900455

  12. Programmable DNA-Mediated Multitasking Processor.

    PubMed

    Shu, Jian-Jun; Wang, Qi-Wen; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

    2015-04-30

    Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

  13. FPGA-based gating and logic for multichannel single photon counting

    SciTech Connect

    Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G; Williams, Brian P; Schaake, Jason; Humble, Travis S

    2012-01-01

    We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidence measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)

  14. SOTANCP3 Scientific Programme

    NASA Astrophysics Data System (ADS)

    2014-12-01

    The programme for the 3rd International Workshop on "State of the Art in Nuclear Cluster Physics" which was held at the KGU (Kanto Gakuin University) Kannai Media Center (8th floor of Yokohoma Media Business Center (YMBC))

  15. FAST joins Breakthrough programme

    NASA Astrophysics Data System (ADS)

    Banks, Michael

    2016-11-01

    The 180m Five-hundred-meter Aperture Spherical radio Telescope (FAST) - the world's largest single-aperture radio receiver - has become part of the Breakthrough Listen programme, which launched in July 2015 to look for intelligent life beyond Earth.

  16. Programmes in Continuing Education

    ERIC Educational Resources Information Center

    Shah, L. R.

    1976-01-01

    The various types and forms of credit and non-credit university continuing education programmes are described in these extracts from a paper presented at the Hyderabad conference on university continuing education. (ABM)

  17. IFLA's Programme of ISBDs

    ERIC Educational Resources Information Center

    Anderson, Dorothy

    1978-01-01

    The article outlines the evolution, development, and current operational programme of the ISBD's (International Standard Bibliographic Description) within the framework of IFLA (International Federation of Library Associations). (Author/JAB)

  18. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

    PubMed Central

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-01

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

  19. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

    NASA Astrophysics Data System (ADS)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-01

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  20. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

    PubMed

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-27

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  1. Optical interference logic in silicon-on-insulator waveguides

    NASA Astrophysics Data System (ADS)

    Wheeler, Dana C.; Hall, Douglas C.

    2006-02-01

    A novel means of realizing optical logic with passive silicon-on-insulator (SOI) waveguide elements is proposed and modeled. Using what we call interference logic (IL), information is encoded and manipulated in the complex domain by properly setting the amplitude and phase of information inputs through specially designed waveguide structures, with the resulting wave interference used to compute the desired function output. We demonstrate that any arbitrary Boolean logic function can be realized in any physical system in which interference occurs. In this work, optical interference logic utilizing constructive and destructive interference of 1.55 micron light waves in multi-mode interference (MMI) couplers fabricated with SOI rib waveguides is described. Defining a vector representation of the complex information, a numerical function minimization algorithm is employed to compute the optimum input vector manipulations needed to realize a given operation's truth table. As such, with the definition of an output amplitude detection threshold separating "0" and "1" results, logic operations can be performed. A digital 2 x 1 multiplexer (MUX) is implemented in a single 4 x 1 MMI coupler where 1 of the 4 inputs serves as a reference input beam. With an input spacing of 40 micron, the 2 x 1 multiplexer has an overall dimension of 160 micron x 2.25 cm. Simple varied-dimension waveguide elements are used to adjust input wave amplitude and phase. To confirm and optimize the designs, device operation is simulated using 2D beam propagation method (BPM).

  2. Control of electrochemical signals from quantum dots conjugated to organic materials by using DNA structure in an analog logic gate.

    PubMed

    Chen, Qi; Yoo, Si-Youl; Chung, Yong-Ho; Lee, Ji-Young; Min, Junhong; Choi, Jeong-Woo

    2016-10-01

    Various bio-logic gates have been studied intensively to overcome the rigidity of single-function silicon-based logic devices arising from combinations of various gates. Here, a simple control tool using electrochemical signals from quantum dots (QDs) was constructed using DNA and organic materials for multiple logic functions. The electrochemical redox current generated from QDs was controlled by the DNA structure. DNA structure, in turn, was dependent on the components (organic materials) and the input signal (pH). Independent electrochemical signals from two different logic units containing QDs were merged into a single analog-type logic gate, which was controlled by two inputs. We applied this electrochemical biodevice to a simple logic system and achieved various logic functions from the controlled pH input sets. This could be further improved by choosing QDs, ionic conditions, or DNA sequences. This research provides a feasible method for fabricating an artificial intelligence system.

  3. Experimental signature of programmable quantum annealing.

    PubMed

    Boixo, Sergio; Albash, Tameem; Spedalieri, Federico M; Chancellor, Nicholas; Lidar, Daniel A

    2013-01-01

    Quantum annealing is a general strategy for solving difficult optimization problems with the aid of quantum adiabatic evolution. Both analytical and numerical evidence suggests that under idealized, closed system conditions, quantum annealing can outperform classical thermalization-based algorithms such as simulated annealing. Current engineered quantum annealing devices have a decoherence timescale which is orders of magnitude shorter than the adiabatic evolution time. Do they effectively perform classical thermalization when coupled to a decohering thermal environment? Here we present an experimental signature which is consistent with quantum annealing, and at the same time inconsistent with classical thermalization. Our experiment uses groups of eight superconducting flux qubits with programmable spin-spin couplings, embedded on a commercially available chip with >100 functional qubits. This suggests that programmable quantum devices, scalable with current superconducting technology, implement quantum annealing with a surprising robustness against noise and imperfections.

  4. Nanomagnet Logic: Architectures, design, and benchmarking

    NASA Astrophysics Data System (ADS)

    Kurtz, Steven J.

    Nanomagnet Logic (NML) is an emerging technology being studied as a possible replacement or supplementary device for Complimentary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FET) by the year 2020. NML devices offer numerous potential advantages including: low energy operation, steady state non-volatility, radiation hardness and a clear path to fabrication and integration with CMOS. However, maintaining both low-energy operation and non-volatility while scaling from the device to the architectural level is non-trivial as (i) nearest neighbor interactions within NML circuits complicate the modeling of ensemble nanomagnet behavior and (ii) the energy intensive clock structures required for re-evaluation and NML's relatively high latency challenge its ability to offer system-level performance wins against other emerging nanotechnologies. Thus, further research efforts are required to model more complex circuits while also identifying circuit design techniques that balance low-energy operation with steady state non-volatility. In addition, further work is needed to design and model low-power on-chip clocks while simultaneously identifying application spaces where NML systems (including clock overhead) offer sufficient energy savings to merit their inclusion in future processors. This dissertation presents research advancing the understanding and modeling of NML at all levels including devices, circuits, and line clock structures while also benchmarking NML against both scaled CMOS and tunneling FETs (TFET) devices. This is accomplished through the development of design tools and methodologies for (i) quantifying both energy and stability in NML circuits and (ii) evaluating line-clocked NML system performance. The application of these newly developed tools improves the understanding of ideal design criteria (i.e., magnet size, clock wire geometry, etc.) for NML architectures. Finally, the system-level performance evaluation tool offers the ability to

  5. Logic, probability, and human reasoning.

    PubMed

    Johnson-Laird, P N; Khemlani, Sangeet S; Goodwin, Geoffrey P

    2015-04-01

    This review addresses the long-standing puzzle of how logic and probability fit together in human reasoning. Many cognitive scientists argue that conventional logic cannot underlie deductions, because it never requires valid conclusions to be withdrawn - not even if they are false; it treats conditional assertions implausibly; and it yields many vapid, although valid, conclusions. A new paradigm of probability logic allows conclusions to be withdrawn and treats conditionals more plausibly, although it does not address the problem of vapidity. The theory of mental models solves all of these problems. It explains how people reason about probabilities and postulates that the machinery for reasoning is itself probabilistic. Recent investigations accordingly suggest a way to integrate probability and deduction.

  6. Fuzzy logic particle tracking velocimetry

    NASA Technical Reports Server (NTRS)

    Wernet, Mark P.

    1993-01-01

    Fuzzy logic has proven to be a simple and robust method for process control. Instead of requiring a complex model of the system, a user defined rule base is used to control the process. In this paper the principles of fuzzy logic control are applied to Particle Tracking Velocimetry (PTV). Two frames of digitally recorded, single exposure particle imagery are used as input. The fuzzy processor uses the local particle displacement information to determine the correct particle tracks. Fuzzy PTV is an improvement over traditional PTV techniques which typically require a sequence (greater than 2) of image frames for accurately tracking particles. The fuzzy processor executes in software on a PC without the use of specialized array or fuzzy logic processors. A pair of sample input images with roughly 300 particle images each, results in more than 200 velocity vectors in under 8 seconds of processing time.

  7. MoS2 based dual input logic AND gate

    NASA Astrophysics Data System (ADS)

    Martinez, Luis M.; Pinto, Nicholas J.; Naylor, Carl H.; Johnson, A. T. Charlie

    2016-12-01

    Crystalline monolayers of CVD MoS2 are used as the active semiconducting channel in a split-gate field effect transistor. The device demonstrates logic AND functionality that is controlled by independently addressing each gate terminal with ±10V. When +10V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The ON/OFF ratio of the device was ˜ 35 and the charge mobility using silicon nitride as the gate dielectric was 1.2cm2/V-s and 0.1cm2/V-s in the ON and OFF states respectively. Clear discrimination between the two states was observed when a simple circuit containing a load resistor was used to test the device logic AND functionality at 10Hz. One advantage is that split gate technology can reduce the number of devices required in complex circuits, leading to compact electronics and large scale integration based on intrinsic 2-D semiconducting materials.

  8. Use of Fuzzy Logic Systems for Assessment of Primary Faults

    NASA Astrophysics Data System (ADS)

    Petrović, Ivica; Jozsa, Lajos; Baus, Zoran

    2015-09-01

    In electric power systems, grid elements are often subjected to very complex and demanding disturbances or dangerous operating conditions. Determining initial fault or cause of those states is a difficult task. When fault occurs, often it is an imperative to disconnect affected grid element from the grid. This paper contains an overview of possibilities for using fuzzy logic in an assessment of primary faults in the transmission grid. The tool for this task is SCADA system, which is based on information of currents, voltages, events of protection devices and status of circuit breakers in the grid. The function model described with the membership function and fuzzy logic systems will be presented in the paper. For input data, diagnostics system uses information of protection devices tripping, states of circuit breakers and measurements of currents and voltages before and after faults.

  9. Orthogonally modulated molecular transport junctions for resettable electronic logic gates

    PubMed Central

    Meng, Fanben; Hervault, Yves-Marie; Shao, Qi; Hu, Benhui; Norel, Lucie; Rigaut, Stéphane; Chen, Xiaodong

    2014-01-01

    Individual molecules have been demonstrated to exhibit promising applications as functional components in the fabrication of computing nanocircuits. Based on their advantage in chemical tailorability, many molecular devices with advanced electronic functions have been developed, which can be further modulated by the introduction of external stimuli. Here, orthogonally modulated molecular transport junctions are achieved via chemically fabricated nanogaps functionalized with dithienylethene units bearing organometallic ruthenium fragments. The addressable and stepwise control of molecular isomerization can be repeatedly and reversibly completed with a judicious use of the orthogonal optical and electrochemical stimuli to reach the controllable switching of conductivity between two distinct states. These photo-/electro-cooperative nanodevices can be applied as resettable electronic logic gates for Boolean computing, such as a two-input OR and a three-input AND-OR. The proof-of-concept of such logic gates demonstrates the possibility to develop multifunctional molecular devices by rational chemical design. PMID:24394717

  10. On schemes of combinatorial transcription logic.

    PubMed

    Buchler, Nicolas E; Gerland, Ulrich; Hwa, Terence

    2003-04-29

    Cells receive a wide variety of cellular and environmental signals, which are often processed combinatorially to generate specific genetic responses. Here we explore theoretically the potentials and limitations of combinatorial signal integration at the level of cis-regulatory transcription control. Our analysis suggests that many complex transcription-control functions of the type encountered in higher eukaryotes are already implementable within the much simpler bacterial transcription system. Using a quantitative model of bacterial transcription and invoking only specific protein-DNA interaction and weak glue-like interaction between regulatory proteins, we show explicit schemes to implement regulatory logic functions of increasing complexity by appropriately selecting the strengths and arranging the relative positions of the relevant protein-binding DNA sequences in the cis-regulatory region. The architectures that emerge are naturally modular and evolvable. Our results suggest that the transcription regulatory apparatus is a "programmable" computing machine, belonging formally to the class of Boltzmann machines. Crucial to our results is the ability to regulate gene expression at a distance. In bacteria, this can be achieved for isolated genes via DNA looping controlled by the dimerization of DNA-bound proteins. However, if adopted extensively in the genome, long-distance interaction can cause unintentional intergenic cross talk, a detrimental side effect difficult to overcome by the known bacterial transcription-regulation systems. This may be a key factor limiting the genome-wide adoption of complex transcription control in bacteria. Implications of our findings for combinatorial transcription control in eukaryotes are discussed.

  11. The semantics of fuzzy logic

    NASA Technical Reports Server (NTRS)

    Ruspini, Enrique H.

    1991-01-01

    Summarized here are the results of recent research on the conceptual foundations of fuzzy logic. The focus is primarily on the principle characteristics of a model that quantifies resemblance between possible worlds by means of a similarity function that assigns a number between 0 and 1 to every pair of possible worlds. Introduction of such a function permits one to interpret the major constructs and methods of fuzzy logic: conditional and unconditional possibility and necessity distributions and the generalized modus ponens of Zadeh on the basis of related metric relationships between subsets of possible worlds.

  12. Logic programming and metadata specifications

    NASA Technical Reports Server (NTRS)

    Lopez, Antonio M., Jr.; Saacks, Marguerite E.

    1992-01-01

    Artificial intelligence (AI) ideas and techniques are critical to the development of intelligent information systems that will be used to collect, manipulate, and retrieve the vast amounts of space data produced by 'Missions to Planet Earth.' Natural language processing, inference, and expert systems are at the core of this space application of AI. This paper presents logic programming as an AI tool that can support inference (the ability to draw conclusions from a set of complicated and interrelated facts). It reports on the use of logic programming in the study of metadata specifications for a small problem domain of airborne sensors, and the dataset characteristics and pointers that are needed for data access.

  13. Superconducting gates with fluxon logics

    NASA Astrophysics Data System (ADS)

    Nacak, H.; Kusmartsev, F. V.

    2010-10-01

    We have developed several logic gates (OR, XOR, AND and NAND) made of superconducting Josephson junctions. The gates based of the flux cloning phenomenon and high speed of fluxons moving in Josephson junctions of different shapes. In a contrast with previous design the gates operates extremely fast since fluxons are moving with the speed close to the speed of light. We have demonstrated their operations and indicated several ways to made a more complicated logic elements which have at the same time a compact form.

  14. Dynamic Logic Assigned to Automata

    NASA Astrophysics Data System (ADS)

    Chajda, Ivan; Paseka, Jan

    2017-02-01

    A dynamic logic B can be assigned to every automaton [InlineMediaObject not available: see fulltext.] without regard if [InlineMediaObject not available: see fulltext.] is deterministic or nondeterministic. This logic enables us to formulate observations on [InlineMediaObject not available: see fulltext.] in the form of composed propositions and, due to a transition functor T, it captures the dynamic behaviour of [InlineMediaObject not available: see fulltext.]. There are formulated conditions under which the automaton [InlineMediaObject not available: see fulltext.] can be recovered by means of B and T.

  15. A Logical Approach to Entanglement

    NASA Astrophysics Data System (ADS)

    Das, Abhishek

    2016-10-01

    In this paper we innovate a logical approach to develop an intuition regarding the phenomenon of quantum entanglement. In the vein of the logic introduced we substantiate that particles that were entangled in the past will be entangled in perpetuity and thereby abide a rule that restricts them to act otherwise. We also introduce a game and by virtue of the concept of Nash equilibrium we have been able to show that entangled particles will mutually correspond to an experiment that is performed on any one of the particle.

  16. JPRS Report, Science & Technology, Japan. Goto Quantum Magneto-Flux Logic Project.

    DTIC Science & Technology

    2007-11-02

    Overseas Publications ...................................................................................................... 17 (1) P atent L ist...When a quantum flux is used as a logic unit, the device keeps expanding, and supercomputers are now essential must always be operated in a...speed supercomputer device by .104CMOS developing appropriate evaluation techniques . This includes measuring the basic operational characteristics

  17. 21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  18. 21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  19. 21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  20. 21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  1. 21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  2. 21 CFR 866.5400 - Alpha-globulin immuno-logical test system.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Alpha-globulin immuno-logical test system. 866.5400 Section 866.5400 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  3. 21 CFR 866.5350 - Fibrinopeptide A immuno-logical test system.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Fibrinopeptide A immuno-logical test system. 866.5350 Section 866.5350 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  4. 21 CFR 866.5350 - Fibrinopeptide A immuno-logical test system.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Fibrinopeptide A immuno-logical test system. 866.5350 Section 866.5350 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  5. 21 CFR 866.5270 - C-reactive protein immuno-logical test system.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false C-reactive protein immuno-logical test system. 866.5270 Section 866.5270 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  6. 21 CFR 866.5270 - C-reactive protein immuno-logical test system.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false C-reactive protein immuno-logical test system. 866.5270 Section 866.5270 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  7. 21 CFR 866.5270 - C-reactive protein immuno-logical test system.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false C-reactive protein immuno-logical test system. 866.5270 Section 866.5270 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  8. 21 CFR 866.5350 - Fibrinopeptide A immuno-logical test system.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Fibrinopeptide A immuno-logical test system. 866.5350 Section 866.5350 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  9. 21 CFR 866.5380 - Free secretory component immuno-logical test system.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... system. 866.5380 Section 866.5380 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5380 Free secretory component immuno-logical test system. (a) Identification. A...

  10. 21 CFR 866.5380 - Free secretory component immuno-logical test system.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... system. 866.5380 Section 866.5380 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5380 Free secretory component immuno-logical test system. (a) Identification. A...

  11. 21 CFR 866.5350 - Fibrinopeptide A immuno-logical test system.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Fibrinopeptide A immuno-logical test system. 866.5350 Section 866.5350 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  12. 21 CFR 866.5270 - C-reactive protein immuno-logical test system.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false C-reactive protein immuno-logical test system. 866.5270 Section 866.5270 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  13. 21 CFR 866.5400 - Alpha-globulin immuno-logical test system.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Alpha-globulin immuno-logical test system. 866.5400 Section 866.5400 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems §...

  14. Enzyme-based logic gates switchable between OR, NXOR and NAND Boolean operations realized in a flow system.

    PubMed

    Fratto, Brian E; Roby, Lucas J; Guz, Nataliia; Katz, Evgeny

    2014-10-18

    The enzyme-based system performing a biocatalytic cascade reaction was realized in a flow device and was used to mimic Boolean logic operations. Chemical inputs applied to the system resulted in the activation of additional reaction steps, allowing the reversible switch of the logic operations between OR, NXOR and NAND gates for processing of two other biomolecular inputs.

  15. Control system devices : architectures and supply channels overview.

    SciTech Connect

    Trent, Jason; Atkins, William Dee; Schwartz, Moses Daniel; Mulder, John C.

    2010-08-01

    This report describes a research project to examine the hardware used in automated control systems like those that control the electric grid. This report provides an overview of the vendors, architectures, and supply channels for a number of control system devices. The research itself represents an attempt to probe more deeply into the area of programmable logic controllers (PLCs) - the specialized digital computers that control individual processes within supervisory control and data acquisition (SCADA) systems. The report (1) provides an overview of control system networks and PLC architecture, (2) furnishes profiles for the top eight vendors in the PLC industry, (3) discusses the communications protocols used in different industries, and (4) analyzes the hardware used in several PLC devices. As part of the project, several PLCs were disassembled to identify constituent components. That information will direct the next step of the research, which will greatly increase our understanding of PLC security in both the hardware and software areas. Such an understanding is vital for discerning the potential national security impact of security flaws in these devices, as well as for developing proactive countermeasures.

  16. Biosensors with Built-In Biomolecular Logic Gates for Practical Applications

    PubMed Central

    Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh

    2014-01-01

    Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating “sense and act” schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423

  17. Sensor activity and logic behaviour of PET based dihydroimidazonaphthalimide diester

    NASA Astrophysics Data System (ADS)

    Georgiev, Nikolai I.; Lyulev, Mihail P.; Bojinov, Vladimir B.

    2012-11-01

    An ester terminated dihydroimidazonaphthalimide as multi-functional logic device is presented. Due to the optical changes as a function of pH this simple molecule is able to act as a molecular pH metre, a digital comparator and a half-adder. It was demonstrated that the dihydroimidazonaphthalimide comparator could be used as a fundamental element of an optical device for control of pH windows. Also, the ability of the device to detect metal ions in DMF and in water/DMF (3:1, v/v) at different pHs has been evaluated by monitoring the changes of its fluorescence intensity. Among the tested metal ions (Cd2+, Co2+, Cu2+, Fe3+, Ni2+, Pb2+, Zn2+, Bi3+, Hg2+ and Ag+) only Fe3+ and Bi3+ were efficiently detected. In water/DMF (3:1, v/v) XOR and XNOR logic gates are presented using pH and Fe3+ as chemical inputs based on encoding binary digits of logical conventions.

  18. Sensor activity and logic behaviour of PET based dihydroimidazonaphthalimide diester.

    PubMed

    Georgiev, Nikolai I; Lyulev, Mihail P; Bojinov, Vladimir B

    2012-11-01

    An ester terminated dihydroimidazonaphthalimide as multi-functional logic device is presented. Due to the optical changes as a function of pH this simple molecule is able to act as a molecular pH metre, a digital comparator and a half-adder. It was demonstrated that the dihydroimidazonaphthalimide comparator could be used as a fundamental element of an optical device for control of pH windows. Also, the ability of the device to detect metal ions in DMF and in water/DMF (3:1, v/v) at different pHs has been evaluated by monitoring the changes of its fluorescence intensity. Among the tested metal ions (Cd(2+), Co(2+), Cu(2+), Fe(3+), Ni(2+), Pb(2+), Zn(2+), Bi(3+), Hg(2+) and Ag(+)) only Fe(3+) and Bi(3+) were efficiently detected. In water/DMF (3:1, v/v) XOR and XNOR logic gates are presented using pH and Fe(3+) as chemical inputs based on encoding binary digits of logical conventions.

  19. Application System Architecture for Cellular Phones by Dividing Interaction Logics

    NASA Astrophysics Data System (ADS)

    Kitamura, Misayo; Todoroki, Nobutoshi; Akiyoshi, Masanori; Kojima, Taizo

    This paper describes application system architecture using cellular phones as user interface devices, which enables users to interact with the system by graphic symbols on a client screen. Our approach has the following features: (i) divided interaction logics running on a server and a Java phone client; both interaction logics cooperate to accomplish a user's operation using a simplified script, (ii) local interaction which enables users to handle figures on a client screen without connecting to a server, and (iii) device-independent script which hides the differences of API sets among various cellular phones. By using this architecture, complicated figures including lots of graphic symbols can be displayed in spite of program-size limitation on a client device, and application programs including same interaction logics are just described once for various cellular phones. Our experiments show the advantage of the local interaction. A client program can respond immediately when handling complicated figures. The ratio of requests to the server is reduced to 23%. It takes less than 9 seconds to display typical contents, which is good enough for practical use. This method also reduces development costs at the second development or later.

  20. Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

    2000-01-01

    The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

  1. Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

    SciTech Connect

    Lee, Youngmin; Lee, Sejoon Im, Hyunsik; Hiramoto, Toshiro

    2015-02-14

    We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

  2. Guide on Logical Database Design.

    ERIC Educational Resources Information Center

    Fong, Elizabeth N.; And Others

    This report discusses an iterative methodology for logical database design (LDD). The methodology includes four phases: local information-flow modeling, global information-flow modeling, conceptual schema design, and external schema modeling. These phases are intended to make maximum use of available information and user expertise, including the…

  3. Mathematical Induction: Deductive Logic Perspective

    ERIC Educational Resources Information Center

    Dogan, Hamide

    2016-01-01

    Many studies mentioned the deductive nature of Mathematical Induction (MI) proofs but almost all fell short in explaining its potential role in the formation of the misconceptions reported in the literature. This paper is the first of its kind looking at the misconceptions from the perspective of the abstract of the deductive logic from one's…

  4. Gateways to Writing Logical Arguments

    ERIC Educational Resources Information Center

    McCann, Thomas M.

    2010-01-01

    Middle school and high school students have a conception of what the basic demands of logic are, and they draw on this understanding in anticipating certain demands of parents and teachers when the adolescents have to defend positions. At the same time, many adolescents struggle to "write" highly elaborated arguments. Teaching students lessons in…

  5. Logical Empiricism, Politics, and Professionalism

    ERIC Educational Resources Information Center

    Edgar, Scott

    2009-01-01

    This paper considers George A. Reisch's account of the role of Cold War political forces in shaping the apolitical stance that came to dominate philosophy of science in the late 1940s and 1950s. It argues that at least as early as the 1930s, Logical Empiricists such as Rudolf Carnap already held that philosophy of science could not properly have…

  6. Program Theory Evaluation: Logic Analysis

    ERIC Educational Resources Information Center

    Brousselle, Astrid; Champagne, Francois

    2011-01-01

    Program theory evaluation, which has grown in use over the past 10 years, assesses whether a program is designed in such a way that it can achieve its intended outcomes. This article describes a particular type of program theory evaluation--logic analysis--that allows us to test the plausibility of a program's theory using scientific knowledge.…

  7. Generic physical protection logic trees

    SciTech Connect

    Paulus, W.K.

    1981-10-01

    Generic physical protection logic trees, designed for application to nuclear facilities and materials, are presented together with a method of qualitative evaluation of the trees for design and analysis of physical protection systems. One or more defense zones are defined where adversaries interact with the physical protection system. Logic trees that are needed to describe the possible scenarios within a defense zone are selected. Elements of a postulated or existing physical protection system are tagged to the primary events of the logic tree. The likelihood of adversary success in overcoming these elements is evaluated on a binary, yes/no basis. The effect of these evaluations is propagated through the logic of each tree to determine whether the adversary is likely to accomplish the end event of the tree. The physical protection system must be highly likely to overcome the adversary before he accomplishes his objective. The evaluation must be conducted for all significant states of the site. Deficiencies uncovered become inputs to redesign and further analysis, closing the loop on the design/analysis cycle.

  8. Logic synthesis from DDL description

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.

    1980-01-01

    The implementation of DDLTRN and DDLSIM programs on SEL-2 computer system is reported. These programs were tested with DDL descriptions of various complexity. An algorithm to synthesize the combinational logic using the cells available in the standard IC cell library was formulated. The algorithm is implemented as a FORTRAN program and a description of the program is given.

  9. Logic Programming and Knowledge Maintenance.

    DTIC Science & Technology

    1987-08-13

    the literature , and became convinced that many of the advantages of frames and semantic nets can be captured in logic programming systems by a...consists of: needs(john,money). married_to(john,mary). loves(john,mary). (mary is the dead victim in this thriller .) The victim’s sister sara consists of

  10. Learning fuzzy logic control system

    NASA Technical Reports Server (NTRS)

    Lung, Leung Kam

    1994-01-01

    The performance of the Learning Fuzzy Logic Control System (LFLCS), developed in this thesis, has been evaluated. The Learning Fuzzy Logic Controller (LFLC) learns to control the motor by learning the set of teaching values that are generated by a classical PI controller. It is assumed that the classical PI controller is tuned to minimize the error of a position control system of the D.C. motor. The Learning Fuzzy Logic Controller developed in this thesis is a multi-input single-output network. Training of the Learning Fuzzy Logic Controller is implemented off-line. Upon completion of the training process (using Supervised Learning, and Unsupervised Learning), the LFLC replaces the classical PI controller. In this thesis, a closed loop position control system of a D.C. motor using the LFLC is implemented. The primary focus is on the learning capabilities of the Learning Fuzzy Logic Controller. The learning includes symbolic representation of the Input Linguistic Nodes set and Output Linguistic Notes set. In addition, we investigate the knowledge-based representation for the network. As part of the design process, we implement a digital computer simulation of the LFLCS. The computer simulation program is written in 'C' computer language, and it is implemented in DOS platform. The LFLCS, designed in this thesis, has been developed on a IBM compatible 486-DX2 66 computer. First, the performance of the Learning Fuzzy Logic Controller is evaluated by comparing the angular shaft position of the D.C. motor controlled by a conventional PI controller and that controlled by the LFLC. Second, the symbolic representation of the LFLC and the knowledge-based representation for the network are investigated by observing the parameters of the Fuzzy Logic membership functions and the links at each layer of the LFLC. While there are some limitations of application with this approach, the result of the simulation shows that the LFLC is able to control the angular shaft position of the

  11. Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

    SciTech Connect

    Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

    2014-02-12

    Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.

  12. Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

    NASA Astrophysics Data System (ADS)

    Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

    2014-02-01

    Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.

  13. National Radiobiology Archives distributed access programmer's guide

    SciTech Connect

    Prather, J. C.; Smith, S. K.; Watson, C. R.

    1991-12-01

    The National Radiobiology Archives is a comprehensive effort to gather, organize, and catalog original data, representative specimens, and supporting materials related to significant radiobiology studies. This provides researchers with information for analyses which compare or combine results of these and other studies and with materials for analysis by advanced molecular biology techniques. This Programmer's Guide document describes the database access software, NRADEMO, and the subset loading script NRADEMO/MAINT/MAINTAIN, which comprise the National Laboratory Archives Distributed Access Package. The guide is intended for use by an experienced database management specialist. It contains information about the physical and logical organization of the software and data files. It also contains printouts of all the scripts and associated batch processing files. It is part of a suite of documents published by the National Radiobiology Archives.

  14. Spintronic logic design methodology based on spin Hall effect-driven magnetic tunnel junctions

    NASA Astrophysics Data System (ADS)

    Kang, Wang; Wang, Zhaohao; Zhang, Youguang; Klein, Jacques-Olivier; Lv, Weifeng; Zhao, Weisheng

    2016-02-01

    Conventional complementary metal-oxide-semiconductor (CMOS) technology is now approaching its physical scaling limits to enable Moore’s law to continue. Spintronic devices, as one of the potential alternatives, show great promise to replace CMOS technology for next-generation low-power integrated circuits in nanoscale technology nodes. Until now, spintronic memory has been successfully commercialized. However spintronic logic still faces many critical challenges (e.g. direct cascading capability and small operation gain) before it can be practically applied. In this paper, we propose a standard complimentary spintronic logic (CSL) design methodology to form a CMOS-like logic design paradigm. Using the spin Hall effect (SHE)-driven magnetic tunnel junction (MTJ) device as an example, we demonstrate CSL implementation, functionality and performance. This logic family provides a unified design methodology for spintronic logic circuits and partly solves the challenges of direct cascading capability and small operation gain in the previously proposed spintronic logic designs. By solving a modified Landau-Lifshitz-Gilbert equation, the magnetization dynamics in the free layer of the MTJ is theoretically described and a compact electrical model is developed. With this electrical model, numerical simulations have been performed to evaluate the functionality and performance of the proposed CSL design. Simulation results demonstrate that the proposed CSL design paradigm is rather promising for low-power logic computing.

  15. Design of polarization encoded all-optical 4-valued MAX logic gate and its applications

    NASA Astrophysics Data System (ADS)

    Chattopadhyay, Tanay; Nath Roy, Jitendra

    2013-07-01

    Quaternary maximum (QMAX) gate is one type of multi-valued logic gate. An all-optical scheme of polarization encoded quaternary (4-valued) MAX logic gate with the help of Terahertz Optical Asymmetric Demultiplexer (TOAD) based fiber interferometric switch is proposed and described. For the quaternary information processing in optics, the quaternary number (0, 1, 2, 3) can be represented by four discrete polarized states of light. Numerical simulation result confirming the described methods is given in this paper. Some applications of MAX gate in logical operation and memory device are also given.

  16. Quantum Logics of Idempotents of Unital Rings

    NASA Astrophysics Data System (ADS)

    Bikchentaev, Airat; Navara, Mirko; Yakushev, Rinat

    2015-06-01

    We introduce some new examples of quantum logics of idempotents in a ring. We continue the study of symmetric logics, i.e., collections of subsets generalizing Boolean algebras and closed under the symmetric difference.

  17. Programmer's guide for the GNAT computer program (numerical analysis of stratification in supercritical oxygen)

    NASA Technical Reports Server (NTRS)

    Heinmiller, J. P.

    1971-01-01

    This document is the programmer's guide for the GNAT computer program developed under MSC/TRW Task 705-2, Apollo cryogenic storage system analysis, subtask 2, is reported. Detailed logic flow charts and compiled program listings are provided for all program elements.

  18. Work Programme, 2014

    ERIC Educational Resources Information Center

    Cedefop - European Centre for the Development of Vocational Training, 2014

    2014-01-01

    Cedefop's work programme 2014 constitutes an ambitious attempt to preserve its core activities, respond to new requests and ensure previous quality standards while respecting resource constraints. Nevertheless, it also reflects the risk that the Centre's ability to deliver its mission and increasing demands may be affected by further budgetary…

  19. Backgrounder: The MAB Programme.

    ERIC Educational Resources Information Center

    United Nations Educational, Scientific, and Cultural Organization, Paris (France). Office of Public Information.

    The Man and the Biosphere Programme (MAB) was launched in November 1971 under the auspices of Unesco. Its aim is to help to develop scientific knowledge with a view to the rational management and conservation of natural resources, to train qualified personnel in this field, and to disseminate the knowledge acquired both to the decision-makers and…

  20. Developing Online Doctoral Programmes

    ERIC Educational Resources Information Center

    Chipere, Ngoni

    2015-01-01

    The objectives of the study were to identify best practices in online doctoral programming and to synthesise these practices into a framework for developing online doctoral programmes. The field of online doctoral studies is nascent and presents challenges for conventional forms of literature review. The literature was therefore reviewed using a…

  1. Computer Programmer/Analyst.

    ERIC Educational Resources Information Center

    Ohio State Univ., Columbus. Center on Education and Training for Employment.

    This publication contains 25 subjects appropriate for use in a competency list for the occupation of computer programmer/analyst, 1 of 12 occupations within the business/computer technologies cluster. Each unit consists of a number of competencies; a list of competency builders is provided for each competency. Titles of the 25 units are as…

  2. Conceptualizing Programme Evaluation

    ERIC Educational Resources Information Center

    Hassan, Salochana

    2013-01-01

    The main thrust of this paper deals with the conceptualization of theory-driven evaluation pertaining to a tutor training programme. Conceptualization of evaluation, in this case, is an integration between a conceptualization model as well as a theoretical framework in the form of activity theory. Existing examples of frameworks of programme…

  3. Programmable calculator stress analysis

    SciTech Connect

    Van Gulick, L.A.

    1983-01-01

    Advanced programmable alphanumeric calculators are well suited for closed-form calculation of pressure-vessel stresses. They offer adequate computing power, portability, special programming features, and simple interactive execution procedures. Representative programs that demonstrate calculator capabilities are presented. Problems treated are stress and strength calculations in thick-walled pressure vessels and the computation of stresses near head/pressure-vessel junctures.

  4. Computerized logic design of digital circuits

    NASA Technical Reports Server (NTRS)

    Sussow, S.; Oglesby, R.

    1973-01-01

    This manual presents a computer program that performs all the work required for the logic design of digital counters or sequential circuits and the simplification of Boolean logic expressions. The program provides both the experienced and inexperienced logic designer with a comprehensive logic design capability. The manual contains Boolean simplification and sequential design theory, detailed instructions for use of the program, a large number of illustrative design examples, and complete program documentation.

  5. Iris Recognition Using Parallel and Sequential Logic in a Reconfigurable Logic Device

    DTIC Science & Technology

    2009-05-05

    UNLIMITED 13. SUPPLEMENTARY NOTES 14. ABSTRACT Iris recognition demonstrates superior performance as a biometric , far exceeding fingerprint...host system for processing. 15. SUBJECT TERMS Biometrics , Iris Recognition, Systolic Architecture, Finite Impulse Response Filtering, Binary...signature) _________________ (date) USNA-1531-2 1 Abstract Biometrics technologies have grown considerably

  6. Enzyme-based logic gates and circuits-analytical applications and interfacing with electronics.

    PubMed

    Katz, Evgeny; Poghossian, Arshak; Schöning, Michael J

    2017-01-01

    The paper is an overview of enzyme-based logic gates and their short circuits, with specific examples of Boolean AND and OR gates, and concatenated logic gates composed of multi-step enzyme-biocatalyzed reactions. Noise formation in the biocatalytic reactions and its decrease by adding a "filter" system, converting convex to sigmoid response function, are discussed. Despite the fact that the enzyme-based logic gates are primarily considered as components of future biomolecular computing systems, their biosensing applications are promising for immediate practical use. Analytical use of the enzyme logic systems in biomedical and forensic applications is discussed and exemplified with the logic analysis of biomarkers of various injuries, e.g., liver injury, and with analysis of biomarkers characteristic of different ethnicity found in blood samples on a crime scene. Interfacing of enzyme logic systems with modified electrodes and semiconductor devices is discussed, giving particular attention to the interfaces functionalized with signal-responsive materials. Future perspectives in the design of the biomolecular logic systems and their applications are discussed in the conclusion. Graphical Abstract Various applications and signal-transduction methods are reviewed for enzyme-based logic systems.

  7. An Introduction to Calculator Logic Systems.

    ERIC Educational Resources Information Center

    Mitchell, Charles E.; Blume, Glendon W.

    1980-01-01

    Each of the hand-held calculator logic systems found on the market today is introduced, along with some of the advantages and disadvantages of each. The systems reviewed are: arithmetic logic, algebraic logic-no hierarchy, algebraic operating system, and reverse polish notation. (MP)

  8. Logics of Business Education for Sustainability

    ERIC Educational Resources Information Center

    Andersson, Pernilla; Öhman, Johan

    2016-01-01

    This paper explores various kinds of logics of "business education for sustainability" and how these "logics" position the subject business person, based on eight teachers' reasoning of their own practices. The concept of logics developed within a discourse theoretical framework is employed to analyse the teachers' reasoning.…

  9. Piaget's Logic of Meanings: Still Relevant Today

    ERIC Educational Resources Information Center

    Wavering, Michael James

    2011-01-01

    In his last book, "Toward a Logic of Meanings" (Piaget & Garcia, 1991), Jean Piaget describes how thought can be categorized into a form of propositional logic, a logic of meanings. The intent of this article is to offer this analysis by Piaget as a means to understand the language and teaching of science. Using binary propositions, conjunctions,…

  10. R-1 (C-620-A) and R-2 (C-620-B) air compressor control logic, computer software description. Revision 1

    SciTech Connect

    Walter, K.E.

    1995-06-08

    This document provides an updated computer software description for the software used on the FFTF R-1 (C-620-A) and R-2 (C-620-B) air compressor programmable controllers. Logic software design changes were required to allow automatic starting of a compressor that had not been previously started.

  11. Applications of Logic Coverage Criteria and Logic Mutation to Software Testing

    ERIC Educational Resources Information Center

    Kaminski, Garrett K.

    2011-01-01

    Logic is an important component of software. Thus, software logic testing has enjoyed significant research over a period of decades, with renewed interest in the last several years. One approach to detecting logic faults is to create and execute tests that satisfy logic coverage criteria. Another approach to detecting faults is to perform mutation…

  12. Logic implementations using a single nanoparticle-protein hybrid

    NASA Astrophysics Data System (ADS)

    Medalsy, Izhar; Klein, Michael; Heyman, Arnon; Shoseyov, Oded; Remacle, F.; Levine, R. D.; Porath, Danny

    2010-06-01

    A Set-Reset machine is the simplest logic circuit with a built-in memory. Its output is a (nonlinear) function of the input and of the state stored in the machine's memory. Here, we report a nanoscale Set-Reset machine operating at room temperature that is based on a 5-nm silicon nanoparticle attached to the inner pore of a stable circular protein. The nanoparticle-protein hybrid can also function as a balanced ternary multiplier. Conductive atomic force microscopy is used to implement the logic input and output operations, and the processing of the logic Set and Reset operations relies on the finite capacitance of the nanoparticle provided by the good electrical isolation given by the protein, thus enabling stability of the logic device states. We show that the machine can be cycled, such that in every successive cycle, the previous state in the memory is retained as the present state. The energy cost of one cycle of computation is minimized to the cost of charging this state.

  13. Magnonic interferometric switch for multi-valued logic circuits

    NASA Astrophysics Data System (ADS)

    Balynsky, Michael; Kozhevnikov, Alexander; Khivintsev, Yuri; Bhowmick, Tonmoy; Gutierrez, David; Chiang, Howard; Dudko, Galina; Filimonov, Yuri; Liu, Guanxiong; Jiang, Chenglong; Balandin, Alexander A.; Lake, Roger; Khitun, Alexander

    2017-01-01

    We investigated a possible use of the magnonic interferometric switches in multi-valued logic circuits. The switch is a three-terminal device consisting of two spin channels where input, control, and output signals are spin waves. Signal modulation is achieved via the interference between the source and gate spin waves. We report experimental data on a micrometer scale prototype based on the Y3Fe2(FeO4)3 structure. The output characteristics are measured at different angles of the bias magnetic field. The On/Off ratio of the prototype exceeds 13 dB at room temperature. Experimental data are complemented by the theoretical analysis and the results of micro magnetic simulations showing spin wave propagation in a micrometer size magnetic junction. We also present the results of numerical modeling illustrating the operation of a nanometer-size switch consisting of just 20 spins in the source-drain channel. The utilization of spin wave interference as a switching mechanism makes it possible to build nanometer-scale logic gates, and minimize energy per operation, which is limited only by the noise margin. The utilization of phase in addition to amplitude for information encoding offers an innovative route towards multi-state logic circuits. We describe possible implementation of the three-value logic circuits based on the magnonic interferometric switches. The advantages and shortcomings inherent in interferometric switches are also discussed.

  14. Quantum dot ternary-valued full-adder: Logic synthesis by a multiobjective design optimization based on a genetic algorithm

    SciTech Connect

    Klymenko, M. V.; Remacle, F.

    2014-10-28

    A methodology is proposed for designing a low-energy consuming ternary-valued full adder based on a quantum dot (QD) electrostatically coupled with a single electron transistor operating as a charge sensor. The methodology is based on design optimization: the values of the physical parameters of the system required for implementing the logic operations are optimized using a multiobjective genetic algorithm. The searching space is determined by elements of the capacitance matrix describing the electrostatic couplings in the entire device. The objective functions are defined as the maximal absolute error over actual device logic outputs relative to the ideal truth tables for the sum and the carry-out in base 3. The logic units are implemented on the same device: a single dual-gate quantum dot and a charge sensor. Their physical parameters are optimized to compute either the sum or the carry out outputs and are compatible with current experimental capabilities. The outputs are encoded in the value of the electric current passing through the charge sensor, while the logic inputs are supplied by the voltage levels on the two gate electrodes attached to the QD. The complex logic ternary operations are directly implemented on an extremely simple device, characterized by small sizes and low-energy consumption compared to devices based on switching single-electron transistors. The design methodology is general and provides a rational approach for realizing non-switching logic operations on QD devices.

  15. Graphene-based aptamer logic gates and their application to multiplex detection.

    PubMed

    Wang, Li; Zhu, Jinbo; Han, Lei; Jin, Lihua; Zhu, Chengzhou; Wang, Erkang; Dong, Shaojun

    2012-08-28

    In this work, a GO/aptamer system was constructed to create multiplex logic operations and enable sensing of multiplex targets. 6-Carboxyfluorescein (FAM)-labeled adenosine triphosphate binding aptamer (ABA) and FAM-labeled thrombin binding aptamer (TBA) were first adsorbed onto graphene oxide (GO) to form a GO/aptamer complex, leading to the quenching of the fluorescence of FAM. We demonstrated that the unique GO/aptamer interaction and the specific aptamer-target recognition in the target/GO/aptamer system were programmable and could be utilized to regulate the fluorescence of FAM via OR and INHIBIT logic gates. The fluorescence changed according to different input combinations, and the integration of OR and INHIBIT logic gates provided an interesting approach for logic sensing applications where multiple target molecules were present. High-throughput fluorescence imagings that enabled the simultaneous processing of many samples by using the combinatorial logic gates were realized. The developed logic gates may find applications in further development of DNA circuits and advanced sensors for the identification of multiple targets in complex chemical environments.

  16. Fuzzy Versions of Epistemic and Deontic Logic

    NASA Technical Reports Server (NTRS)

    Gounder, Ramasamy S.; Esterline, Albert C.

    1998-01-01

    Epistemic and deontic logics are modal logics, respectively, of knowledge and of the normative concepts of obligation, permission, and prohibition. Epistemic logic is useful in formalizing systems of communicating processes and knowledge and belief in AI (Artificial Intelligence). Deontic logic is useful in computer science wherever we must distinguish between actual and ideal behavior, as in fault tolerance and database integrity constraints. We here discuss fuzzy versions of these logics. In the crisp versions, various axioms correspond to various properties of the structures used in defining the semantics of the logics. Thus, any axiomatic theory will be characterized not only by its axioms but also by the set of properties holding of the corresponding semantic structures. Fuzzy logic does not proceed with axiomatic systems, but fuzzy versions of the semantic properties exist and can be shown to correspond to some of the axioms for the crisp systems in special ways that support dependency networks among assertions in a modal domain. This in turn allows one to implement truth maintenance systems. For the technical development of epistemic logic, and for that of deontic logic. To our knowledge, we are the first to address fuzzy epistemic and fuzzy deontic logic explicitly and to consider the different systems and semantic properties available. We give the syntax and semantics of epistemic logic and discuss the correspondence between axioms of epistemic logic and properties of semantic structures. The same topics are covered for deontic logic. Fuzzy epistemic and fuzzy deontic logic discusses the relationship between axioms and semantic properties for these logics. Our results can be exploited in truth maintenance systems.

  17. Block QCA Fault-Tolerant Logic Gates

    NASA Technical Reports Server (NTRS)

    Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

    2003-01-01

    -based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.

  18. Reversible logic gates based on enzyme-biocatalyzed reactions and realized in flow cells: a modular approach.

    PubMed

    Fratto, Brian E; Katz, Evgeny

    2015-05-18

    Reversible logic gates, such as the double Feynman gate, Toffoli gate and Peres gate, with 3-input/3-output channels are realized using reactions biocatalyzed with enzymes and performed in flow systems. The flow devices are constructed using a modular approach, where each flow cell is modified with one enzyme that biocatalyzes one chemical reaction. The multi-step processes mimicking the reversible logic gates are organized by combining the biocatalytic cells in different networks. This work emphasizes logical but not physical reversibility of the constructed systems. Their advantages and disadvantages are discussed and potential use in biosensing systems, rather than in computing devices, is suggested.

  19. Nanowire NMOS Logic Inverter Characterization.

    PubMed

    Hashim, Yasir

    2016-06-01

    This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

  20. The logic of medical diagnosis.

    PubMed

    Stanley, Donald E; Campos, Daniel G

    2013-01-01

    Establishing diagnoses is a crucial aspect of medical practice. However, this process has received comparatively little logical and pedagogical attention when compared to statistical methods for evaluating evidence. This article investigates the logic of medical diagnosis in order to fill this void. It is organized in three parts: the first attempts to explain why more attention ought to be paid to diagnosis, at least as much as to evidence; the second calls attention to the method of diagnosis by abductive reasoning developed in the 19th century by Charles Sanders Peirce (1839-1914); and the third demonstrates the use and pervasiveness of abduction by any other name in clinical diagnosis. We examine six diagnostic strategies in common use that contain most, if not all, of Peirce's structure of inquiry in science.

  1. An Embedded Reconfigurable Logic Module

    NASA Technical Reports Server (NTRS)

    Tucker, Jerry H.; Klenke, Robert H.; Shams, Qamar A. (Technical Monitor)

    2002-01-01

    A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

  2. GMAG Dissertation Award Talk: All Spin Logic -- Multimagnet Networks interacting via Spin currents

    NASA Astrophysics Data System (ADS)

    Srinivasan, Srikant

    2012-02-01

    Digital logic circuits have traditionally been based on storing information as charge on capacitors, and the stored information is transferred by controlling the flow of charge. However, electrons carry both charge and spin, the latter being responsible for magnetic phenomena. In the last few decades, there has been a significant improvement in our ability to control spins and their interaction with magnets. All Spin Logic (ASL) represents a new approach to information processing where spins and magnets now mirror the roles of charges and capacitors in conventional logic circuits. In this talk I first present a model [1] that couples non-collinear spin transport with magnet-dynamics to predict the switching behavior of the basic ASL device. This model is based on established physics and is benchmarked against available experimental data that demonstrate spin-torque switching in lateral structures. Next, the model is extended to simulate multi-magnet networks coupled with spin transport channels. The simulations suggest ASL devices have the essential characteristics for building logic circuits. In particular, (1) the example of an ASL ring oscillator [2, 3] is used to provide a clear signature of directed information transfer in cascaded ASL devices without the need for external control circuitry and (2) a simulated NAND [4] gate with fan-out of 2 suggests that ASL can implement universal logic and drive subsequent stages. Finally I will discuss how ASL based circuits could also have potential use in the design of neuromorphic circuits suitable for hybrid analog/digital information processing because of the natural mapping of ASL devices to neurons [4]. [4pt] [1] B. Behin-Aein, A. Sarkar, S. Srinivasan, and S. Datta, ``Switching Energy-Delay of All-Spin Logic devices,'' Appl. Phys. Lett., 98, 123510 (2011).[0pt] [2] S. Srinivasan, A. Sarkar, B. Behin-Aein, and S. Datta, ``All Spin Logic Device with Inbuilt Non-reciprocity,'' IEEE Trans. Magn., 47, 10 (2011).[0pt] [3

  3. All-optical symmetric ternary logic gate

    NASA Astrophysics Data System (ADS)

    Chattopadhyay, Tanay

    2010-09-01

    Symmetric ternary number (radix=3) has three logical states (1¯, 0, 1). It is very much useful in carry free arithmetical operation. Beside this, the logical operation using this type of number system is also effective in high speed computation and communication in multi-valued logic. In this literature all-optical circuits for three basic symmetrical ternary logical operations (inversion, MIN and MAX) are proposed and described. Numerical simulation verifies the theoretical model. In this present scheme the different ternary logical states are represented by different polarized state of light. Terahertz optical asymmetric demultiplexer (TOAD) based interferometric switch has been used categorically in this manuscript.

  4. PLATO--AN AUTOMATED TEACHING DEVICE.

    ERIC Educational Resources Information Center

    BITZER, D.; AND OTHERS

    PLATO (PROGRAMED LOGIC FOR AUTOMATIC TEACHING OPERATION) IS A DEVICE FOR TEACHING A NUMBER OF STUDENTS INDIVIDUALLY BY MEANS OF A SINGLE, CENTRAL PURPOSE, DIGITAL COMPUTER. THE GENERAL ORGANIZATION OF EQUIPMENT CONSISTS OF A KEYSET FOR STUDENT RESPONSES, THE COMPUTER, STORAGE DEVICE (ELECTRIC BLACKBOARD), SLIDE SELECTOR (ELECTRICAL BOOK), AND TV…

  5. Cosmic logic: a computational model

    SciTech Connect

    Vanchurin, Vitaly

    2016-02-01

    We initiate a formal study of logical inferences in context of the measure problem in cosmology or what we call cosmic logic. We describe a simple computational model of cosmic logic suitable for analysis of, for example, discretized cosmological systems. The construction is based on a particular model of computation, developed by Alan Turing, with cosmic observers (CO), cosmic measures (CM) and cosmic symmetries (CS) described by Turing machines. CO machines always start with a blank tape and CM machines take CO's Turing number (also known as description number or Gödel number) as input and output the corresponding probability. Similarly, CS machines take CO's Turing number as input, but output either one if the CO machines are in the same equivalence class or zero otherwise. We argue that CS machines are more fundamental than CM machines and, thus, should be used as building blocks in constructing CM machines. We prove the non-computability of a CS machine which discriminates between two classes of CO machines: mortal that halts in finite time and immortal that runs forever. In context of eternal inflation this result implies that it is impossible to construct CM machines to compute probabilities on the set of all CO machines using cut-off prescriptions. The cut-off measures can still be used if the set is reduced to include only machines which halt after a finite and predetermined number of steps.

  6. Static impedance behavior of programmable metallization cells

    NASA Astrophysics Data System (ADS)

    Rajabi, S.; Saremi, M.; Barnaby, H. J.; Edwards, A.; Kozicki, M. N.; Mitkova, M.; Mahalanabis, D.; Gonzalez-Velo, Y.; Mahmud, A.

    2015-04-01

    Programmable metallization cell (PMC) devices work by growing and dissolving a conducting metallic bridge across a chalcogenide glass (ChG) solid electrolyte, which changes the resistance of the cell. PMC operation relies on the incorporation of metal ions in the ChG films via photo-doping to lower the off-state resistance and stabilize resistive switching, and subsequent transport of these ions by electric fields induced from an externally applied bias. In this paper, the static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film with active Ag and inert Ni electrodes is characterized and modeled using three dimensional simulation code. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.

  7. Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

    PubMed Central

    Rhee, Minsoung

    2010-01-01

    We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

  8. Microfluidic pneumatic logic circuits and digital pneumatic microprocessors for integrated microfluidic systems.

    PubMed

    Rhee, Minsoung; Burns, Mark A

    2009-11-07

    We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.

  9. Dynamic partial reconfiguration of logic controllers implemented in FPGAs

    NASA Astrophysics Data System (ADS)

    Bazydło, Grzegorz; Wiśniewski, Remigiusz

    2016-09-01

    Technological progress in recent years benefits in digital circuits containing millions of logic gates with the capability for reprogramming and reconfiguring. On the one hand it provides the unprecedented computational power, but on the other hand the modelled systems are becoming increasingly complex, hierarchical and concurrent. Therefore, abstract modelling supported by the Computer Aided Design tools becomes a very important task. Even the higher consumption of the basic electronic components seems to be acceptable because chip manufacturing costs tend to fall over the time. The paper presents a modelling approach for logic controllers with the use of Unified Modelling Language (UML). Thanks to the Model Driven Development approach, starting with a UML state machine model, through the construction of an intermediate Hierarchical Concurrent Finite State Machine model, a collection of Verilog files is created. The system description generated in hardware description language can be synthesized and implemented in reconfigurable devices, such as FPGAs. Modular specification of the prototyped controller permits for further dynamic partial reconfiguration of the prototyped system. The idea bases on the exchanging of the functionality of the already implemented controller without stopping of the FPGA device. It means, that a part (for example a single module) of the logic controller is replaced by other version (called context), while the rest of the system is still running. The method is illustrated by a practical example by an exemplary Home Area Network system.

  10. Programmable calculator stress analysis

    SciTech Connect

    Van Gulick, L.A.

    1983-01-01

    This paper assesses the suitability of advanced programmable alphanumeric calculators for closed form calculation of pressure vessel stresses and offers, as their advantages, adequate computing power, portability, special programming features, and simple interactive execution procedures. Representative programs which demonstrate their capacities are presented. Problems dealing with stress and strength calculations in thick-walled pressure vessels and with the computation of stresses near head/pressure vessel junctures are treated. Assessed favorably in this paper as useful contributors to computeraided design of pressure vessels, programmable alphanumeric calculators have areas of implementation in checking finite element results, aiding in the development of an intuitive understanding of stresses and their parameter dependencies, and evaluating rapidly a variety of preliminary designs.

  11. NSF announces diversity programme

    NASA Astrophysics Data System (ADS)

    Kruesi, Liz

    2016-04-01

    The US National Science Foundation (NSF) has initiated a new funding programme that will create schemes to increase diversity in science, technology, engineering and mathematics (STEM). The initiative - Inclusion across the Nation of Communities of Learners of Underrepresented Discoverers in Engineering and Science (INCLUDES) - aims to increase the participation of women, those with a low socioeconomic status, people with disabilities and those from minority racial backgrounds.

  12. Punch Card Programmable Microfluidics

    PubMed Central

    Korir, George; Prakash, Manu

    2015-01-01

    Small volume fluid handling in single and multiphase microfluidics provides a promising strategy for efficient bio-chemical assays, low-cost point-of-care diagnostics and new approaches to scientific discoveries. However multiple barriers exist towards low-cost field deployment of programmable microfluidics. Incorporating multiple pumps, mixers and discrete valve based control of nanoliter fluids and droplets in an integrated, programmable manner without additional required external components has remained elusive. Combining the idea of punch card programming with arbitrary fluid control, here we describe a self-contained, hand-crank powered, multiplex and robust programmable microfluidic platform. A paper tape encodes information as a series of punched holes. A mechanical reader/actuator reads these paper tapes and correspondingly executes operations onto a microfluidic chip coupled to the platform in a plug-and-play fashion. Enabled by the complexity of codes that can be represented by a series of holes in punched paper tapes, we demonstrate independent control of 15 on-chip pumps with enhanced mixing, normally-closed valves and a novel on-demand impact-based droplet generator. We demonstrate robustness of operation by encoding a string of characters representing the word “PUNCHCARD MICROFLUIDICS” using the droplet generator. Multiplexing is demonstrated by implementing an example colorimetric water quality assays for pH, ammonia, nitrite and nitrate content in different water samples. With its portable and robust design, low cost and ease-of-use, we envision punch card programmable microfluidics will bring complex control of microfluidic chips into field-based applications in low-resource settings and in the hands of children around the world. PMID:25738834

  13. Punch card programmable microfluidics.

    PubMed

    Korir, George; Prakash, Manu

    2015-01-01

    Small volume fluid handling in single and multiphase microfluidics provides a promising strategy for efficient bio-chemical assays, low-cost point-of-care diagnostics and new approaches to scientific discoveries. However multiple barriers exist towards low-cost field deployment of programmable microfluidics. Incorporating multiple pumps, mixers and discrete valve based control of nanoliter fluids and droplets in an integrated, programmable manner without additional required external components has remained elusive. Combining the idea of punch card programming with arbitrary fluid control, here we describe a self-contained, hand-crank powered, multiplex and robust programmable microfluidic platform. A paper tape encodes information as a series of punched holes. A mechanical reader/actuator reads these paper tapes and correspondingly executes operations onto a microfluidic chip coupled to the platform in a plug-and-play fashion. Enabled by the complexity of codes that can be represented by a series of holes in punched paper tapes, we demonstrate independent control of 15 on-chip pumps with enhanced mixing, normally-closed valves and a novel on-demand impact-based droplet generator. We demonstrate robustness of operation by encoding a string of characters representing the word "PUNCHCARD MICROFLUIDICS" using the droplet generator. Multiplexing is demonstrated by implementing an example colorimetric water quality assays for pH, ammonia, nitrite and nitrate content in different water samples. With its portable and robust design, low cost and ease-of-use, we envision punch card programmable microfluidics will bring complex control of microfluidic chips into field-based applications in low-resource settings and in the hands of children around the world.

  14. Programmable matter by folding

    PubMed Central

    Hawkes, E.; An, B.; Benbernou, N. M.; Tanaka, H.; Kim, S.; Demaine, E. D.; Rus, D.; Wood, R. J.

    2010-01-01

    Programmable matter is a material whose properties can be programmed to achieve specific shapes or stiffnesses upon command. This concept requires constituent elements to interact and rearrange intelligently in order to meet the goal. This paper considers achieving programmable sheets that can form themselves in different shapes autonomously by folding. Past approaches to creating transforming machines have been limited by the small feature sizes, the large number of components, and the associated complexity of communication among the units. We seek to mitigate these difficulties through the unique concept of self-folding origami with universal crease patterns. This approach exploits a single sheet composed of interconnected triangular sections. The sheet is able to fold into a set of predetermined shapes using embedded actuation. To implement this self-folding origami concept, we have developed a scalable end-to-end planning and fabrication process. Given a set of desired objects, the system computes an optimized design for a single sheet and multiple controllers to achieve each of the desired objects. The material, called programmable matter by folding, is an example of a system capable of achieving multiple shapes for multiple functions. PMID:20616049

  15. Programmability in AIPS++

    NASA Technical Reports Server (NTRS)

    Hjellming, R. M.

    1992-01-01

    AIPS++ is an Astronomical Information Processing System being designed and implemented by an international consortium of NRAO and six other radio astronomy institutions in Australia, India, the Netherlands, the United Kingdom, Canada, and the USA. AIPS++ is intended to replace the functionality of AIPS, to be more easily programmable, and will be implemented in C++ using object-oriented techniques. Programmability in AIPS++ is planned at three levels. The first level will be that of a command-line interpreter with characteristics similar to IDL and PV-Wave, but with an intensive set of operations appropriate to telescope data handling, image formation, and image processing. The third level will be in C++ with extensive use of class libraries for both basic operations and advanced applications. The third level will allow input and output of data between external FORTRAN programs and AIPS++ telescope and image databases. In addition to summarizing the above programmability characteristics, this talk will given an overview of the classes currently being designed for telescope data calibration and editing, image formation, and the 'toolkit' of mathematical 'objects' that will perform most of the processing in AIPS++.

  16. Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

    NASA Technical Reports Server (NTRS)

    Le, Martin; Zheng, Xin; Katanyoutant, Sunant

    2008-01-01

    Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state

  17. Fuzzy logic controller versus classical logic controller for residential hybrid solar-wind-storage energy system

    NASA Astrophysics Data System (ADS)

    Derrouazin, A.; Aillerie, M.; Mekkakia-Maaza, N.; Charles, J. P.

    2016-07-01

    Several researches for management of diverse hybrid energy systems and many techniques have been proposed for robustness, savings and environmental purpose. In this work we aim to make a comparative study between two supervision and control techniques: fuzzy and classic logics to manage the hybrid energy system applied for typical housing fed by solar and wind power, with rack of batteries for storage. The system is assisted by the electric grid during energy drop moments. A hydrogen production device is integrated into the system to retrieve surplus energy production from renewable sources for the household purposes, intending the maximum exploitation of these sources over years. The models have been achieved and generated signals for electronic switches command of proposed both techniques are presented and discussed in this paper.

  18. Programmable DMA controller

    NASA Technical Reports Server (NTRS)

    Hendry, David F. (Inventor)

    1993-01-01

    In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

  19. An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

    ERIC Educational Resources Information Center

    Foster, D. L.

    2012-01-01

    For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

  20. Integrated logic circuits using single-atom transistors.

    PubMed

    Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

    2011-08-23

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch.

  1. Event-recording devices with identification codes

    NASA Technical Reports Server (NTRS)

    Watters, David G. (Inventor); Huestis, David L. (Inventor); Bahr, Alfred J. (Inventor); Vidmar, Robert J. (Inventor)

    2003-01-01

    A recording device allows wireless interrogation to determine its identity and its state. The state indicates whether one or more physical or chemical events have taken place. In effect, the one or more physical or chemical events are recorded by the device. The identity of the device allows it to be distinguished from a number of similar devices. The recording device may be used in an array of devices that allows wireless probing by an interrogation unit. When probed, each device tells the interrogator who it is and what state it is in. The devices allow multiple use and the interrogator may use a logical reset to determine the state of each device. The interrogator can thus easily identify particular items in an array that have reached a particular condition. The device may record the status of each device in a database to maintain a history for each.

  2. Enzyme-based Logic Gates and Networks with Output Signals Analyzed by Various Methods.

    PubMed

    Katz, Evgeny

    2017-02-27

    The paper overviews various methods for analysis of output signals generated by enzyme-based logic systems. The considered methods include different optical techniques (optical absorbance, fluorescence spectroscopy, surface plasmon resonance), electrochemical techniques (cyclic voltammetry, potentiometry, impedance spectroscopy, conductivity measurements, use of field effect transistor devices, pH measurements), and various mechano-electronic methods (using atomic force microscope, quartz crystal microbalance). While each of the methods is already well known for various bioanalytical applications, their use in combination with the biomolecular logic systems is rather new and sometimes not trivial. Many of the discussed methods have been combined with use of signal-responsive materials to transduce and amplify biomolecular signals generated by the logic operations. Interfacing of biocomputing logic systems with electronics and "smart" signal-responsive materials allowed for extending logic operations to actuation functions, for example, stimulating molecular release and switchable features of bioelectronic devices, such as biofuel cells. The purpose of this review article is to emphasize broad variability of the bioanalytical systems applied for the signal transduction in biocomputing processes. All bioanalytical systems discussed in the article are exemplified with specific logic gates and multi-gate networks realized with enzyme-based biocatalytic cascades.

  3. Programmable RF System for RF System-on-Chip

    NASA Astrophysics Data System (ADS)

    Ryu, Jee-Youl; Kim, Sung-Woo; Lee, Dong-Hyun; Park, Seung-Hun; Lee, Jung-Hoon; Ha, Deock-Ho; Kim, Seung-Un

    This paper proposes a new automatic programmable radio frequency (RF) system for a System-on-Chip (SoC) transceiver. We built a 5-GHz low noise amplifier (LNA) with an on-chip programmable RF system using 0.18-(m SiGe technology. This system is extremely useful for today's RF IC devices in a complete RF transceiver environment. The programmable RF system helps it to provide DC output voltages, hence, making the compensation network automatic. The programmable RF system automatically adjusts performance of 5-GHz low noise amplifier with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to the unusual thermal variation or unusual process variation.

  4. Optical interferometric logic gates based on metal slot waveguide network realizing whole fundamental logic operations.

    PubMed

    Pan, Deng; Wei, Hong; Xu, Hongxing

    2013-04-22

    Optical interferometric logic gates in metal slot waveguide network are designed and investigated by electromagnetic simulations. The designed logic gates can realize all fundamental logic operations. A single Y-shaped junction can work as logic gate for four logic functions: AND, NOT, OR and XOR. By cascading two Y-shaped junctions, NAND, NOR and XNOR can be realized. The working principle is analyzed in detail. In the simulations, these gates show large intensity contrast for the Boolean logic states of the output. These results can be useful for future integrated optical computing.

  5. Notes on stochastic (bio)-logic gates: computing with allosteric cooperativity

    NASA Astrophysics Data System (ADS)

    Agliari, Elena; Altavilla, Matteo; Barra, Adriano; Dello Schiavo, Lorenzo; Katz, Evgeny

    2015-05-01

    Recent experimental breakthroughs have finally allowed to implement in-vitro reaction kinetics (the so called enzyme based logic) which code for two-inputs logic gates and mimic the stochastic AND (and NAND) as well as the stochastic OR (and NOR). This accomplishment, together with the already-known single-input gates (performing as YES and NOT), provides a logic base and paves the way to the development of powerful biotechnological devices. However, as biochemical systems are always affected by the presence of noise (e.g. thermal), standard logic is not the correct theoretical reference framework, rather we show that statistical mechanics can work for this scope: here we formulate a complete statistical mechanical description of the Monod-Wyman-Changeaux allosteric model for both single and double ligand systems, with the purpose of exploring their practical capabilities to express noisy logical operators and/or perform stochastic logical operations. Mixing statistical mechanics with logics, and testing quantitatively the resulting findings on the available biochemical data, we successfully revise the concept of cooperativity (and anti-cooperativity) for allosteric systems, with particular emphasis on its computational capabilities, the related ranges and scaling of the involved parameters and its differences with classical cooperativity (and anti-cooperativity).

  6. Limit, logic, and computation

    PubMed Central

    Freedman, Michael H.

    1998-01-01

    We introduce “ultrafilter limits” into the classical Turing model of computation and develop a paradigm for interpreting the problem of distinguishing the class P from NP as a logical problem of decidability. We use P(NP) to denote decision problems which can be solved on a (nondeterministic) Turing machine in polynomial time. The concept is that in an appropriate limit it may be possible to prove that problems in P are still decidable, so a problem whose limit is undecidable would be established as lying outside of P. PMID:9419334

  7. An error-resilient non-volatile magneto-elastic universal logic gate with ultralow energy-delay product

    PubMed Central

    Biswas, Ayan K.; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2014-01-01

    A long-standing goal of computer technology is to process and store digital information with the same device in order to implement new architectures. One way to accomplish this is to use nanomagnetic logic gates that can perform Boolean operations and then store the output data in the magnetization states of nanomagnets, thereby doubling as both logic and memory. Unfortunately, many of these nanomagnetic devices do not possess the seven essential characteristics of a Boolean logic gate : concatenability, non-linearity, isolation between input and output, gain, universal logic implementation, scalability and error resilience. More importantly, their energy-delay products and error rates tend to vastly exceed that of conventional transistor-based logic gates, which is unacceptable. Here, we propose a non-volatile voltage-controlled nanomagnetic logic gate that possesses all the necessary characteristics of a logic gate and whose energy-delay product is two orders of magnitude less than that of other nanomagnetic (non-volatile) logic gates. The error rate is also superior. PMID:25532757

  8. Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell

    NASA Astrophysics Data System (ADS)

    Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

    2016-06-01

    Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis

  9. Stretch not flex: programmable rubber keyboard

    NASA Astrophysics Data System (ADS)

    Xu, Daniel; Tairych, Andreas; Anderson, Iain A.

    2016-01-01

    Stretchability is a property that brings versatility and design freedom to human interface devices. We present a soft, flexible and stretchable keyboard made from a dielectric elastomer sensor sheet. Using a multi-frequency capacitance sensing technique based on a transmission line model, we demonstrate how this keyboard can detect touch in two dimensions, programmable to increase the number of keys and into different layouts, all without adding any new wires, connections or modifying the hardware. The method is efficient and scalable for large sensing systems with multiple degrees of freedom.

  10. A programmable Fortran preprocessor

    SciTech Connect

    Rosing, M.

    1995-06-01

    A programmable Fortran preprocessor is described. It allows users to define compile time operations that can examine and modify the source tree before it is compiled with a traditional compiler. This intermediate step allows the definition of routines and operations that adapt to the context in which they are used. Context sensitive operations increase the flexibility of abstractions that can be built without degrading efficiency, as compared to using traditional run time based abstractions such as libraries or objects. The preprocessor is described briefly along with an example of how it is used to add CMFortran array operations to Fortran77. Other preprocessors that have been implemented are also briefly described.

  11. NASCAP programmer's reference manual

    NASA Technical Reports Server (NTRS)

    Mandell, M. J.; Stannard, P. R.; Katz, I.

    1993-01-01

    The NASA Charging Analyzer Program (NASCAP) is a computer program designed to model the electrostatic charging of complicated three-dimensional objects, both in a test tank and at geosynchronous altitudes. This document is a programmer's reference manual and user's guide. It is designed as a reference to experienced users of the code, as well as an introduction to its use for beginners. All of the many capabilities of NASCAP are covered in detail, together with examples of their use. These include the definition of objects, plasma environments, potential calculations, particle emission and detection simulations, and charging analysis.

  12. Selection in backcross programmes

    PubMed Central

    Hospital, Frédéric

    2005-01-01

    Backcrossing is a well-known and long established breeding scheme where a characteristic is introgressed from a donor parent into the genomic background of a recurrent parent. The various uses of backcrossing in modern genetics, particularly with the help of molecular markers, are reviewed here. Selection in backcross programmes is used to either improve the genetic value of plant and animal populations or fine map quantitative trait loci. Both cases are helpful in our understanding of the genetic bases of quantitative traits variation. PMID:16048792

  13. Minuteman Weapon System Test Set logic replacement

    NASA Astrophysics Data System (ADS)

    Royse, S. D.

    In the late 1960s, the Minuteman Weapon System Test Set was constructed as a part of the Minuteman development program. The missile Reentry Vehicle is that portion of the Minuteman missile system which reenters the atmosphere with the nuclear warhead. The test set has the objective to test the electrical/electro-mechanical systems and components of the reentry vehicle at both the repair depot and missile maintenance squadron levels. With the recent advances in semiconductor technologies, the Diode Transistor Logic (DTL) technology used to implement the test set logic became obsolete. The present paper is concerned with efforts to develop a prototype replacement for the test set logic. Attention is given to the functions of the test set, the documentation of existing logic, and the prototype design approach, which involves the subdivision of the logic into three basic functional groups. The logic replacement is based on the utilization of a multiple microprocessor system.

  14. Electronic logic for enhanced switch reliability

    DOEpatents

    Cooper, J.A.

    1984-01-20

    A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and fail-safe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.

  15. [Continuity and transformation of body logic].

    PubMed

    Bolens, Guillemette

    2003-01-01

    This article is concerned with two distinct corporeal logics. In the first, corporeality is founded on joints, tendons, and mobility; in the second, the envelope and its apertures are considered primordial. The first logic is extant in very few works. Although these texts (e.g. The Iliad, Beowulf) clearly share the same, very specific, conception of the body, they belong to different histories. The corporeal logic of the 'jointed body' (corps articulaire) cannot, therefore, be appraised in terms of longue durée. The texts represent, instead, a moment of transition between the psychodynamics of orality and literacy. A problem correlated to this fact is that readers (ancient and modern) no longer think using the same logic as that pertaining to the jointed body. They tend to translate information regarding the logic of the jointed body into data meaningful in their own logic.

  16. People Like Logical Truth: Testing the Intuitive Detection of Logical Value in Basic Propositions

    PubMed Central

    2016-01-01

    Recent studies on logical reasoning have suggested that people are intuitively aware of the logical validity of syllogisms or that they intuitively detect conflict between heuristic responses and logical norms via slight changes in their feelings. According to logical intuition studies, logically valid or heuristic logic no-conflict reasoning is fluently processed and induces positive feelings without conscious awareness. One criticism states that such effects of logicality disappear when confounding factors such as the content of syllogisms are controlled. The present study used abstract propositions and tested whether people intuitively detect logical value. Experiment 1 presented four logical propositions (conjunctive, biconditional, conditional, and material implications) regarding a target case and asked the participants to rate the extent to which they liked the statement. Experiment 2 tested the effects of matching bias, as well as intuitive logic, on the reasoners’ feelings by manipulating whether the antecedent or consequent (or both) of the conditional was affirmed or negated. The results showed that both logicality and matching bias affected the reasoners’ feelings, and people preferred logically true targets over logically false ones for all forms of propositions. These results suggest that people intuitively detect what is true from what is false during abstract reasoning. Additionally, a Bayesian mixed model meta-analysis of conditionals indicated that people’s intuitive interpretation of the conditional “if p then q” fits better with the conditional probability, q given p. PMID:28036402

  17. Special Technology Area Review on Field Programmable Gate Arrays (FPGAs) For Military Applications

    DTIC Science & Technology

    2005-07-01

    upset and latchup from nuclear transient effects and a number of single - event effects from cosmic...Programmable devices are particularly sensitive to single event effects (SEE) including single event upsets , single event transients, and single ... event dielectric rupture. In particular, single event upsets in the configuration memory of programmable FPGAs lead to single - event

  18. Towards woven logic from organic electronic fibres.

    PubMed

    Hamedi, Mahiar; Forchheimer, Robert; Inganäs, Olle

    2007-05-01

    The use of organic polymers for electronic functions is mainly motivated by the low-end applications, where low cost rather than advanced performance is a driving force. Materials and processing methods must allow for cheap production. Printing of electronics using inkjets or classical printing methods has considerable potential to deliver this. Another technology that has been around for millennia is weaving using fibres. Integration of electronic functions within fabrics, with production methods fully compatible with textiles, is therefore of current interest, to enhance performance and extend functions of textiles. Standard polymer field-effect transistors require well defined insulator thickness and high voltage, so they have limited suitability for electronic textiles. Here we report a novel approach through the construction of wire electrochemical transistor (WECT) devices, and show that textile monofilaments with 10-100 mum diameters can be coated with continuous thin films of the conducting polythiophene poly(3,4-ethylenedioxythiophene), and used to create micro-scale WECTs on single fibres. We also demonstrate inverters and multiplexers for digital logic. This opens an avenue for three-dimensional polymer micro-electronics, where large-scale circuits can be designed and integrated directly into the three-dimensional structure of woven fibres.

  19. Towards woven logic from organic electronic fibres

    NASA Astrophysics Data System (ADS)

    Hamedi, Mahiar; Forchheimer, Robert; Inganäs, Olle

    2007-05-01

    The use of organic polymers for electronic functions is mainly motivated by the low-end applications, where low cost rather than advanced performance is a driving force. Materials and processing methods must allow for cheap production. Printing of electronics using inkjets or classical printing methods has considerable potential to deliver this. Another technology that has been around for millennia is weaving using fibres. Integration of electronic functions within fabrics, with production methods fully compatible with textiles, is therefore of current interest, to enhance performance and extend functions of textiles. Standard polymer field-effect transistors require well defined insulator thickness and high voltage, so they have limited suitability for electronic textiles. Here we report a novel approach through the construction of wire electrochemical transistor (WECT) devices, and show that textile monofilaments with 10-100μm diameters can be coated with continuous thin films of the conducting polythiophene poly(3,4-ethylenedioxythiophene), and used to create micro-scale WECTs on single fibres. We also demonstrate inverters and multiplexers for digital logic. This opens an avenue for three-dimensional polymer micro-electronics, where large-scale circuits can be designed and integrated directly into the three-dimensional structure of woven fibres.

  20. Teaching Modelling Concepts: Enter the Pocket-Size Programmable Calculator.

    ERIC Educational Resources Information Center

    Gaar, Kermit A., Jr.

    1980-01-01

    Addresses the problem of the failure of students to see a physiological system in an integrated way. Programmable calculators armed with a printer are suggested as useful teaching devices that avoid the expense and the unavailability of computers for modelling in teaching physiology. (Author/SA)