Science.gov

Sample records for programmable logic devices

  1. Fuzzy logic and coarse coding using programmable logic devices

    NASA Astrophysics Data System (ADS)

    Brooks, Geoffrey

    2009-05-01

    Naturally-occurring sensory signal processing algorithms, such as those that inspired fuzzy-logic control, can be integrated into non-naturally-occurring high-performance technology, such as programmable logic devices, to realize novel bio-inspired designs. Research is underway concerning an investigation into using field programmable logic devices (FPLD's) to implement fuzzy logic sensory processing. A discussion is provided concerning the commonality between bio-inspired fuzzy logic algorithms and coarse coding that is prevalent in naturally-occurring sensory systems. Undergraduate design projects using fuzzy logic for an obstacle-avoidance robot has been accomplished at our institution and other places; numerous other successful fuzzy logic applications can be found as well. The long-term goal is to leverage such biomimetic algorithms for future applications. This paper outlines a design approach for implementing fuzzy-logic algorithms into reconfigurable computing devices. This paper is presented in an effort to connect with others who may be interested in collaboration as well as to establish a starting point for future research.

  2. Starting Circuit For Erasable Programmable Logic Device

    NASA Technical Reports Server (NTRS)

    Cole, Steven W.

    1990-01-01

    Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.

  3. Starting Circuit For Erasable Programmable Logic Device

    NASA Technical Reports Server (NTRS)

    Cole, Steven W.

    1990-01-01

    Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.

  4. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm

  5. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment

  6. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

  7. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

  8. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, heavy ion test results, and some total dose results.

  9. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, and some total dose results.

  10. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    2000-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will start a series of notes concentrating on analysis techniques with this issues section discussing worst-case analysis requirements.

  11. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Day, John H. (Technical Monitor)

    2001-01-01

    This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.

  12. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1999-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter the focus is on some experimental data on low voltage drop out regulators to support mixed 5 and 3.3 volt systems. A discussion of the Small Explorer WIRE spacecraft will also be given. Lastly, we show take a first look at robust state machines in Hardware Description Languages (VHDL) and their use in critical systems. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or e-mail.

  13. Flexible programmable logic module

    DOEpatents

    Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

    2001-01-01

    The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

  14. Programmable Logic Controllers.

    ERIC Educational Resources Information Center

    Insolia, Gerard; Anderson, Kathleen

    This document contains a 40-hour course in programmable logic controllers (PLC), developed for a business-industry technology resource center for firms in eastern Pennsylvania by Northampton Community College. The 10 units of the course cover the following: (1) introduction to programmable logic controllers; (2) DOS primer; (3) prerequisite…

  15. A complex programmable logic device-based high-precision electrical capacitance tomography system

    NASA Astrophysics Data System (ADS)

    Zhou, Haili; Xu, Lijun; Cao, Zhang; Liu, XiaoLei; Liu, Shi

    2013-07-01

    In this paper, a high-precision measurement system for electrical capacitance tomography (ECT) is presented. A low-cost complex programmable logic device (CPLD) is employed to accomplish logic control, signal generation, data acquisition, digital demodulation and communication with the aid of external components. By adopting a simple digital demodulator recently developed by the authors, the demodulation to ac signals becomes rather simple and resource-saving. A double-T-switches configuration is developed to improve the precision and lower the limit of multi-channel capacitance measurement. A capacitance network is constructed for system calibration. A square ECT sensor with 16 electrodes is constructed to test the practical performance of the measurement system. With a data acquisition rate of 185 frame s-1, the signal-to-noise ratio and standard deviation of capacitance measurement can reach up to 70 dB and 0.09 fF, respectively. Image reconstruction experiment has validated the CPLD-based ECT system.

  16. Software Safety Assurance of Programmable Logic

    NASA Technical Reports Server (NTRS)

    Berens, Kalynnda

    2002-01-01

    Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

  17. Software Safety Assurance of Programmable Logic

    NASA Technical Reports Server (NTRS)

    Berens, Kalynnda

    2002-01-01

    Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

  18. Programmable Logic Controllers. Teacher Edition.

    ERIC Educational Resources Information Center

    Rauh, Bob; Kaltwasser, Stan

    These materials were developed for a seven-unit secondary or postsecondary education course on programmable logic controllers (PLCs) that treats most of the skills needed to work effectively with PLCs as programming skills. The seven units of the course cover the following topics: fundamentals of programmable logic controllers; contracts, timers,…

  19. Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Darrin, Ann Garrison; Conde, Richard; Chern, Bobbie; Luers, Phil; Jurczyk, Steve; Mills, Carl; Day, John H. (Technical Monitor)

    2001-01-01

    The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of

  20. Microelectromechanical reprogrammable logic device

    PubMed Central

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-01-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

  1. Microelectromechanical reprogrammable logic device

    NASA Astrophysics Data System (ADS)

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-03-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

  2. Universal programmable logic gate and routing method

    NASA Technical Reports Server (NTRS)

    Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

    2009-01-01

    An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

  3. Design of a Ferroelectric Programmable Logic Gate Array

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Ho, Fat Duen

    2003-01-01

    A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

  4. Design of a Ferroelectric Programmable Logic Gate Array

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Ho, Fat Duen

    2003-01-01

    A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

  5. Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

    ERIC Educational Resources Information Center

    Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

    2009-01-01

    Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

  6. Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

    ERIC Educational Resources Information Center

    Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

    2009-01-01

    Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

  7. Voltage controlled spintronics device for logic applications.

    SciTech Connect

    Bader, S. D.; You, C.-Y.

    1999-09-03

    We consider logic device concepts based on our previously proposed spintronics device element whose magnetization orientation is controlled by application of a bias voltage instead of a magnetic field. The basic building block is the voltage-controlled rotation (VCR) element that consists of a four-layer structure--two ferromagnetic layers separated by both nanometer-thick insulator and metallic spacer layers. The interlayer exchange coupling between the two ferromagnetic layers oscillates as a function of applied voltage. We illustrate transistor-like concepts and re-programmable logic gates based on VCR elements.

  8. Firmware Modification Analysis in Programmable Logic Controllers

    DTIC Science & Technology

    2014-03-27

    MODIFICATION ANALYSIS IN PROGRAMMABLE LOGIC CONTROLLERS Arturo M. Garcia Jr., B.S.S.E.C.A. Captain, USA Approved: //signed// Robert F. Mills , PhD...Matthew 5:37 v Acknowledgments My sincere gratitude to my committee for their guidance and teamwork which made this thesis possible. Dr. Mills ...2012. 2012. [5] Bolton, William. Programmable logic controllers. Newnes, 2009. [6] Boyer, Stuart . SCADA: Supervisory Control and Data Aquisition 4th

  9. Implementing neural nets with programmable logic

    NASA Technical Reports Server (NTRS)

    Vidal, Jacques J.

    1988-01-01

    Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

  10. Implementing neural nets with programmable logic

    NASA Technical Reports Server (NTRS)

    Vidal, Jacques J.

    1988-01-01

    Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

  11. Automatic Configuration of Programmable Logic Controller Emulators

    DTIC Science & Technology

    2015-03-01

    you for your passionate teaching , advice, and mentorship. I would also like to thank the other members in my committee, LTC Mason Rice and Mr. Juan...Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4 Protocol Informatics In-depth...tree PI Protocol Informatics PLC programmable logic controller PRISMA Protocol Inspection and State Machine Analysis RA Region Analysis RRP request

  12. G4-FETs as Universal and Programmable Logic Gates

    NASA Technical Reports Server (NTRS)

    Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

    2007-01-01

    An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

  13. Reactivity measurement using a programmable logic controller

    SciTech Connect

    Bobek, L.M.; Miraglia, P.Q.

    1995-12-31

    The application of digital systems for measuring reactor dynamics has been used at experimental and research reactors for almost 30 yr. At the Worcester Polytechnic Institute (WPI) nuclear reactor facility (NRF), a recent modernization effort included the installation of a programmable logic controller (PLC) and an operator interface terminal (OIT). The PLC systems are increasingly being used to replace relay-based monitoring and control systems at nuclear power plants. At WPI, the PLC and OIT provide a digital reactor monitoring system that is remote from the reactor`s analog control instrumentation. The NRF staff has programmed the monitoring system for several reactor-related applications, including reactivity measurement.

  14. PLAFST Programmable Logic Array from State Table.

    DTIC Science & Technology

    1983-12-01

    HD -i8 466 PL AFST PROGRAMMABLE LOGIC ARRAY FROM STATE T ABLE(U) AIR /2 FORC INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF UNCLSSIIED...INSTITUTE OF TECHNOLOGY Wright-Patterson Air Force Base, Ohio ) A ’J[. .:’,,- oved iot public T.,-].:.,’ 8 4 7 x -;..- APIT/GE/EE/83D-57 Accession For...number of rows with y - 1. Don’t care symbols are denoted by a " x ". The l’s and x’s are grouped together like Karnaugh maps with two exceptions. The

  15. Complex cellular logic computation using ribocomputing devices.

    PubMed

    Green, Alexander A; Kim, Jongmin; Ma, Duo; Silver, Pamela A; Collins, James J; Yin, Peng

    2017-08-03

    Synthetic biology aims to develop engineering-driven approaches to the programming of cellular functions that could yield transformative technologies. Synthetic gene circuits that combine DNA, protein, and RNA components have demonstrated a range of functions such as bistability, oscillation, feedback, and logic capabilities. However, it remains challenging to scale up these circuits owing to the limited number of designable, orthogonal, high-performance parts, the empirical and often tedious composition rules, and the requirements for substantial resources for encoding and operation. Here, we report a strategy for constructing RNA-only nanodevices to evaluate complex logic in living cells. Our 'ribocomputing' systems are composed of de-novo-designed parts and operate through predictable and designable base-pairing rules, allowing the effective in silico design of computing devices with prescribed configurations and functions in complex cellular environments. These devices operate at the post-transcriptional level and use an extended RNA transcript to co-localize all circuit sensing, computation, signal transduction, and output elements in the same self-assembled molecular complex, which reduces diffusion-mediated signal losses, lowers metabolic cost, and improves circuit reliability. We demonstrate that ribocomputing devices in Escherichia coli can evaluate two-input logic with a dynamic range up to 900-fold and scale them to four-input AND, six-input OR, and a complex 12-input expression (A1 AND A2 AND NOT A1*) OR (B1 AND B2 AND NOT B2*) OR (C1 AND C2) OR (D1 AND D2) OR (E1 AND E2). Successful operation of ribocomputing devices based on programmable RNA interactions suggests that systems employing the same design principles could be implemented in other host organisms or in extracellular settings.

  16. Reversible logic gate using adiabatic superconducting devices

    PubMed Central

    Takeuchi, N.; Yamanashi, Y.; Yoshikawa, N.

    2014-01-01

    Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic devices. Another difficulty is that reversible logic gates must be both logically and physically reversible. Here we propose the first practical reversible logic gate using adiabatic superconducting devices and experimentally demonstrate the logical and physical reversibility of the gate. Additionally, we estimate the energy dissipation of the gate, and discuss the minimum energy dissipation required for reversible logic operations. It is expected that the results of this study will enable reversible computing to move from the theoretical stage into practical usage. PMID:25220698

  17. Reversible logic gate using adiabatic superconducting devices

    NASA Astrophysics Data System (ADS)

    Takeuchi, N.; Yamanashi, Y.; Yoshikawa, N.

    2014-09-01

    Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic devices. Another difficulty is that reversible logic gates must be both logically and physically reversible. Here we propose the first practical reversible logic gate using adiabatic superconducting devices and experimentally demonstrate the logical and physical reversibility of the gate. Additionally, we estimate the energy dissipation of the gate, and discuss the minimum energy dissipation required for reversible logic operations. It is expected that the results of this study will enable reversible computing to move from the theoretical stage into practical usage.

  18. Reversible logic gate using adiabatic superconducting devices.

    PubMed

    Takeuchi, N; Yamanashi, Y; Yoshikawa, N

    2014-09-15

    Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic devices. Another difficulty is that reversible logic gates must be both logically and physically reversible. Here we propose the first practical reversible logic gate using adiabatic superconducting devices and experimentally demonstrate the logical and physical reversibility of the gate. Additionally, we estimate the energy dissipation of the gate, and discuss the minimum energy dissipation required for reversible logic operations. It is expected that the results of this study will enable reversible computing to move from the theoretical stage into practical usage.

  19. Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

    ERIC Educational Resources Information Center

    Debiec, P.; Byczuk, M.

    2011-01-01

    Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

  20. Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

    ERIC Educational Resources Information Center

    Debiec, P.; Byczuk, M.

    2011-01-01

    Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

  1. All-photonic multifunctional molecular logic device.

    PubMed

    Andréasson, Joakim; Pischel, Uwe; Straight, Stephen D; Moore, Thomas A; Moore, Ana L; Gust, Devens

    2011-08-03

    Photochromes are photoswitchable, bistable chromophores which, like transistors, can implement binary logic operations. When several photochromes are combined in one molecule, interactions between them such as energy and electron transfer allow design of simple Boolean logic gates and more complex logic devices with all-photonic inputs and outputs. Selective isomerization of individual photochromes can be achieved using light of different wavelengths, and logic outputs can employ absorption and emission properties at different wavelengths, thus allowing a single molecular species to perform several different functions, even simultaneously. Here, we report a molecule consisting of three linked photochromes that can be configured as AND, XOR, INH, half-adder, half-subtractor, multiplexer, demultiplexer, encoder, decoder, keypad lock, and logically reversible transfer gate logic devices, all with a common initial state. The system demonstrates the advantages of light-responsive molecules as multifunctional, reconfigurable nanoscale logic devices that represent an approach to true molecular information processing units.

  2. All-Photonic Multifunctional Molecular Logic Device

    PubMed Central

    2011-01-01

    Photochromes are photoswitchable, bistable chromophores which, like transistors, can implement binary logic operations. When several photochromes are combined in one molecule, interactions between them such as energy and electron transfer allow design of simple Boolean logic gates and more complex logic devices with all-photonic inputs and outputs. Selective isomerization of individual photochromes can be achieved using light of different wavelengths, and logic outputs can employ absorption and emission properties at different wavelengths, thus allowing a single molecular species to perform several different functions, even simultaneously. Here, we report a molecule consisting of three linked photochromes that can be configured as AND, XOR, INH, half-adder, half-subtractor, multiplexer, demultiplexer, encoder, decoder, keypad lock, and logically reversible transfer gate logic devices, all with a common initial state. The system demonstrates the advantages of light-responsive molecules as multifunctional, reconfigurable nanoscale logic devices that represent an approach to true molecular information processing units. PMID:21563823

  3. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    SciTech Connect

    Lashin, A. V. Kozyrev, A. V.

    2015-09-15

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

  4. A Device for Logic Information Processing.

    ERIC Educational Resources Information Center

    Levinskiy, L. S.; Vissonova, I. A.

    Two essential components of the information-logic problem are: (1) choosing some known part of the total information block for parallel review of the entire block and (2) parallel logic processing of a sequence of codes. The described device fulfills these essential components thereby improving information processing and increasing the speed of…

  5. Multilevel programmable logic array schemes for microprogrammed automata

    SciTech Connect

    Barkalov, A.A.

    1995-03-01

    Programmable logic arrays (PLAs) provide an efficient tool for implementation of logic schemes of microprogrammed automata (MPA). The number of PLAs in the MPA logic scheme can be minimized by increasing the number of levels. In this paper, we analyze the structures of multilevel schemes of Mealy automata, propose a number of new structures, consider the corresponding correctness conditions, and examine some problems that must be solved in order to satisfy these conditions.

  6. Logic Devices Based on Spin Current

    NASA Astrophysics Data System (ADS)

    Behin-Aein, Behtash

    2011-03-01

    The need to find low power alternatives to digital electronics circuits has led to increasing interest in alternative switching schemes like the magnetic quantum cellular automata that store information in nanomagnets which communicate through their magnetic fields. A recent proposal called all spin logic (ASL) proposes to communicate between nanomagnets using spin currents which are spatially localized and can be conveniently routed. In this talk we present a model for ASL devices that is based on established physics and is benchmarked against available experimental data. We investigate switching energy- delay of ASL devices and provide frameworks that allow simple comparisons with charge based devices like CMOS and can help to determine possible use of ASL in future logic implementation. Expected scaling of switching energy-delay of ASL devices as magnets are downscaled while retaining their stability against thermal fluctuations will be presented. This work was supported by Nanoelectronics Research Initiative (NRI) and Network for Computational Nanotechnology (NCN).

  7. Optical design of programmable logic arrays

    NASA Astrophysics Data System (ADS)

    Murdocca, Miles J.; Huang, Alan; Jahns, Jurgen; Streibl, Norbert

    1988-05-01

    Regular free-space interconnects such as the perfect shuffle and banyan provided by beam splitters, lenses, and mirrors connect optical logic gates arranged in two-dimensional arrays. An algorithmic design technique transforms arbitrary logic equations into a near-optimal depth circuit. Analysis shows that an arbitrary interconnect makes little or no improvement in circuit depth and can even reduce throughput. Gate count is normally higher with a regular interconnect, and cost bounds are shown. It is concluded that regularly interconnected circuits will have a higher gate count compared with arbitrarily interconnected circuits using the design techniques presented here and that regular free-space interconnects are comparable with arbitrary interconnects in terms of circuit depth and are preferred to arbitrary interconnects for maximizing throughput.

  8. Programming Programmable Logic Controller. High-Technology Training Module.

    ERIC Educational Resources Information Center

    Lipsky, Kevin

    This training module on programming programmable logic controllers (PLC) is part of the memory structure and programming unit used in a packaging systems equipment control course. In the course, students assemble, install, maintain, and repair industrial machinery used in industry. The module contains description, objectives, content outline,…

  9. Programmable resistive-switch nanowire transistor logic circuits.

    PubMed

    Shim, Wooyoung; Yao, Jun; Lieber, Charles M

    2014-09-10

    Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

  10. Spin wave nonreciprocity for logic device applications

    PubMed Central

    Jamali, Mahdi; Kwon, Jae Hyun; Seo, Soo-Man; Lee, Kyung-Jin; Yang, Hyunsoo

    2013-01-01

    The utilization of spin waves as eigenmodes of the magnetization dynamics for information processing and communication has been widely explored recently due to its high operational speed with low power consumption and possible applications for quantum computations. Previous proposals of spin wave Mach-Zehnder devices were based on the spin wave phase, a delicate entity which can be easily disrupted. Here, we propose a complete logic system based on the spin wave amplitude utilizing the nonreciprocal spin wave behavior excited by microstrip antennas. The experimental data reveal that the nonreciprocity of magnetostatic surface spin wave can be tuned by the bias magnetic field. Furthermore, engineering of the device structure could result in a high nonreciprocity factor for spin wave logic applications. PMID:24196318

  11. Current Radiation Issues for Programmable Elements and Devices

    NASA Technical Reports Server (NTRS)

    Katz, R.; Wang, J. J.; Koga, R.; LaBel, A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.; Paolini, W.; Sin, B.

    1998-01-01

    State of the an programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.

  12. Programmable Logic Device (PLD) Design Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio

    NASA Technical Reports Server (NTRS)

    Shalkhauser, Mary Jo W.

    2017-01-01

    The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. At the conclusion of the development, the software and hardware description language (HDL) code was delivered to JSC for their use in their iPAS test bed to get hands-on experience with the STRS standard, and for development of their own STRS Waveforms on the now STRS compliant platform.The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe the design of the HDL code for the FPGA portion of the iPAS STRS Radio particularly the design of the FPGA wrapper and the test waveform.

  13. Development of ferrite logic devices for an arithmetic processor

    NASA Technical Reports Server (NTRS)

    Heckler, C. H., Jr.

    1972-01-01

    A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.

  14. Sandia ATM SONET Interface Logic

    SciTech Connect

    Kitta, Joseph P.

    1994-07-21

    SASIL is used to program the EPLD's (Erasable Programmable Logic Devices) and PAL's (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.

  15. Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits

    NASA Astrophysics Data System (ADS)

    Ogawa, Taichi; Hirose, Tetsuya; Asai, Tetsuya; Amemiya, Yoshihito

    A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.

  16. Fuzzy Petri net-based programmable logic controller.

    PubMed

    Andreu, D; Pascal, J C; Valette, R

    1997-01-01

    Programmable logic controllers (PLCs) are able to directly implement control sequences specified by means of standard languages such as Grafcet or formal models such as Petri nets. In the case of simple regulation problems between two steps it could be of great interest to introduce a notion of "fuzzy events" in order to denote a continuous evolution from one state to another. This could result from a linear interpolation between the commands attached to two control steps represented by two Petri net (PN) places. This paper is an attempt to develop fuzzy PN-based PLCs in a similar way as fuzzy controllers (regulators). Our approach is based on a combination of Petri nets with possibility theory (Petri nets with fuzzy markings).

  17. The programmable (logic) controller: Adapting in an environment of change

    SciTech Connect

    Levine, P.S.

    1995-03-01

    Reports of the imminent death of the PLC (programmable logic controller) were greatly exaggerated, to paraphrase Mark Twain. In fact, the PLC is not only alive and working worldwide in thousands of applications, but it is also integrating well with related technologies. Long-term survival is a larger question - probably unanswerable given the pace of technological change. However, a few questions arise about the PLC today and in the immediate future: (1) What`s happening with programming languages? (2) Will there continue to be a {open_quotes}blurring of the lines{close_quotes} between the PLC and other technologies, and what role will software play in this integration? (3) How will the PLC`s cost and size affect the market?

  18. Processing device with self-scrubbing logic

    SciTech Connect

    Wojahn, Christopher K.

    2016-03-01

    An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.

  19. Partial reconfiguration of concurrent logic controllers implemented in FPGA devices

    NASA Astrophysics Data System (ADS)

    Wiśniewski, Remigiusz; Grobelna, Iwona; Stefanowicz, Łukasz

    2016-12-01

    Reconfigurable systems are recently used in many domains. Although the concept of multi-context logic controllers is relatively new, it may be noticed that the subject is receiving a lot of attention, especially in the industry. The work constitutes a stepping stone in design of reconfigurable logic controllers implemented in an FPGA device. An approach of designing of logic controllers oriented for further partial reconfiguration is proposed. A case study of a milling machine is used for an illustration.

  20. Designing a Beamline Equipment Protection System Using a Programmable Logic Controller

    NASA Astrophysics Data System (ADS)

    Minich, James M.

    1996-09-01

    As part of the Synchrotron Radiation Instrumentation Collaborative Access Team (SRI-CAT), a new beamline equipment protection system was designed, implemented and installed. The beamline equipment protection system is designed to assure the safe operation of bending magnet and insertion device beamline components, such as white-beam slits, user filters, shutters and stops, mirrors and monochromators. Design goals of the equipment protection system were to improve equipment safety performance, reduce nuisance trips and incorporate additional system functions with minimal cost. To meet the requirements of such a safety system, it was configured to use a programmable controller, remote block input/output (I/O), local interfaces and a serial communication link known as remote I/O (RIO). Aspects about the design requirements, functionality and constraints are presented, as well as specifics on programmable ladder logic design, hardware selection, testing and interfacing requirements.

  1. Programmable logic controller optical fibre sensor interface module

    NASA Astrophysics Data System (ADS)

    Allwood, Gary; Wild, Graham; Hinckley, Steven

    2011-12-01

    Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

  2. Voltage controlled spintronic devices for logic applications

    DOEpatents

    You, Chun-Yeol; Bader, Samuel D.

    2001-01-01

    A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

  3. Ultrafast phase-change logic device driven by melting processes

    PubMed Central

    Loke, Desmond; Skelton, Jonathan M.; Wang, Wei-Jie; Lee, Tae-Hoon; Zhao, Rong; Chong, Tow-Chong; Elliott, Stephen R.

    2014-01-01

    The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change–based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change–based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change–based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates. PMID:25197044

  4. Ultrafast phase-change logic device driven by melting processes.

    PubMed

    Loke, Desmond; Skelton, Jonathan M; Wang, Wei-Jie; Lee, Tae-Hoon; Zhao, Rong; Chong, Tow-Chong; Elliott, Stephen R

    2014-09-16

    The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change-based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change-based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change-based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates.

  5. Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

    PubMed

    Devaraju, Naga Sai Gopi K; Unger, Marc A

    2012-11-21

    Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

  6. Programmable and multiparameter DNA-based logic platform for cancer recognition and targeted therapy.

    PubMed

    You, Mingxu; Zhu, Guizhi; Chen, Tao; Donovan, Michael J; Tan, Weihong

    2015-01-21

    The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy.

  7. Programmable and Multiparameter DNA-Based Logic Platform For Cancer Recognition and Targeted Therapy

    PubMed Central

    2014-01-01

    The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy. PMID:25361164

  8. SASIL. Sandia ATM SONET Interface Logic

    SciTech Connect

    Kitta, J P

    1994-07-01

    SASIL is used to program the EPLD`s (Erasable Programmable Logic Devices) and PAL`s (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.

  9. Compact programmable photonic variable delay devices

    NASA Technical Reports Server (NTRS)

    Yao, X. Steve (Inventor)

    1999-01-01

    Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm.sup.2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.

  10. General purpose programmable accelerator board

    DOEpatents

    Robertson, Perry J.; Witzke, Edward L.

    2001-01-01

    A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

  11. Memristor-based programmable logic array (PLA) and analysis as Memristive networks.

    PubMed

    Lee, Kwan-Hee; Lee, Sang-Jin; Kim, Seok-Man; Cho, Kyoungrok

    2013-05-01

    A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors.

  12. Experimental demonstration of programmable multi-functional spin logic cell based on spin Hall effect

    NASA Astrophysics Data System (ADS)

    Zhang, X.; Wan, C. H.; Yuan, Z. H.; Fang, C.; Kong, W. J.; Wu, H.; Zhang, Q. T.; Tao, B. S.; Han, X. F.

    2017-04-01

    Confronting with the gigantic volume of data produced every day, raising integration density by reducing the size of devices becomes harder and harder to meet the ever-increasing demand for high-performance computers. One feasible path is to actualize more logic functions in one cell. In this respect, we experimentally demonstrate a prototype spin-orbit torque based spin logic cell integrated with five frequently used logic functions (AND, OR, NOT, NAND and NOR). The cell can be easily programmed and reprogrammed to perform desired function. Furthermore, the information stored in cells is symmetry-protected, making it possible to expand into logic gate array where the cell can be manipulated one by one without changing the information of other undesired cells. This work provides a prospective example of multi-functional spin logic cell with reprogrammability and nonvolatility, which will advance the application of spin logic devices.

  13. pH-programmable DNA logic arrays powered by modular DNAzyme libraries.

    PubMed

    Elbaz, Johann; Wang, Fuan; Remacle, Francoise; Willner, Itamar

    2012-12-12

    Nature performs complex information processing circuits, such the programmed transformations of versatile stem cells into targeted functional cells. Man-made molecular circuits are, however, unable to mimic such sophisticated biomachineries. To reach these goals, it is essential to construct programmable modular components that can be triggered by environmental stimuli to perform different logic circuits. We report on the unprecedented design of artificial pH-programmable DNA logic arrays, constructed by modular libraries of Mg(2+)- and UO(2)(2+)-dependent DNAzyme subunits and their substrates. By the appropriate modular design of the DNA computation units, pH-programmable logic arrays of various complexities are realized, and the arrays can be erased, reused, and/or reprogrammed. Such systems may be implemented in the near future for nanomedical applications by pH-controlled regulation of cellular functions or may be used to control biotransformations stimulated by bacteria.

  14. Energy Efficient Digital Logic Using Nanoscale Magnetic Devices

    NASA Astrophysics Data System (ADS)

    Lambson, Brian James

    Increasing demand for information processing in the last 50 years has been largely satisfied by the steadily declining price and improving performance of microelectronic devices. Much of this progress has been made by aggressively scaling the size of semiconductor transistors and metal interconnects that microprocessors are built from. As devices shrink to the size regime in which quantum effects pose significant challenges, new physics may be required in order to continue historical scaling trends. A variety of new devices and physics are currently under investigation throughout the scientific and engineering community to meet these challenges. One of the more drastic proposals on the table is to replace the electronic components of information processors with magnetic components. Magnetic components are already commonplace in computers for their information storage capability. Unlike most electronic devices, magnetic materials can store data in the absence of a power supply. Today's magnetic hard disk drives can routinely hold billions of bits of information and are in widespread commercial use. Their ability to function without a constant power source hints at an intrinsic energy efficiency. The question we investigate in this dissertation is whether or not this advantage can be extended from information storage to the notoriously energy intensive task of information processing. Several proof-of-concept magnetic logic devices were proposed and tested in the past decade. In this dissertation, we build on the prior work by answering fundamental questions about how magnetic devices achieve such high energy efficiency and how they can best function in digital logic applications. The results of this analysis are used to suggest and test improvements to nanomagnetic computing devices. Two of our results are seen as especially important to the field of nanomagnetic computing: (1) we show that it is possible to operate nanomagnetic computers at the fundamental

  15. Motor imaginary-based brain-machine interface design using programmable logic controllers for the disabled.

    PubMed

    Jeyabalan, Vickneswaran; Samraj, Andrews; Loo, Chu Kiong

    2010-10-01

    Aiming at the implementation of brain-machine interfaces (BMI) for the aid of disabled people, this paper presents a system design for real-time communication between the BMI and programmable logic controllers (PLCs) to control an electrical actuator that could be used in devices to help the disabled. Motor imaginary signals extracted from the brain’s motor cortex using an electroencephalogram (EEG) were used as a control signal. The EEG signals were pre-processed by means of adaptive recursive band-pass filtrations (ARBF) and classified using simplified fuzzy adaptive resonance theory mapping (ARTMAP) in which the classified signals are then translated into control signals used for machine control via the PLC. A real-time test system was designed using MATLAB for signal processing, KEP-Ware V4 OLE for process control (OPC), a wireless local area network router, an Omron Sysmac CPM1 PLC and a 5 V/0.3A motor. This paper explains the signal processing techniques, the PLC's hardware configuration, OPC configuration and real-time data exchange between MATLAB and PLC using the MATLAB OPC toolbox. The test results indicate that the function of exchanging real-time data can be attained between the BMI and PLC through OPC server and proves that it is an effective and feasible method to be applied to devices such as wheelchairs or electronic equipment.

  16. Programmable Metallization Cell Devices for Flexible Electronics

    NASA Astrophysics Data System (ADS)

    Baliga, Sunil

    Programmable metallization cell (PMC) technology is based on an electrochemical phenomenon in which a metallic electrodeposit can be grown or dissolved between two electrodes depending on the voltage applied between them. Devices based on this phenomenon exhibit a unique, self-healing property, as a broken metallic structure can be healed by applying an appropriate voltage between the two broken ends. This work explores methods of fabricating interconnects and switches based on PMC technology on flexible substrates. The objective was the evaluation of the feasibility of using this technology in flexible electronics applications in which reliability is a primary concern. The re-healable property of the interconnect is characterized for the silver doped germanium selenide (Ag-Ge-Se) solid electrolyte system. This property was evaluated by measuring the resistances of the healed interconnect structures and comparing these to the resistances of the unbroken structures. The reliability of the interconnects in both unbroken and healed states is studied by investigating the resistances of the structures to DC voltages, AC voltages and different temperatures as a function of time. This work also explores replacing silver with copper for these interconnects to enhance their reliability. A model for PMC-based switches on flexible substrates is proposed and compared to the observed device behavior with the objective of developing a formal design methodology for these devices. The switches were subjected to voltage sweeps and their resistance was investigated as a function of sweep voltage. The resistance of the switches as a function of voltage pulse magnitude when placed in series with a resistance was also investigated. A model was then developed to explain the behavior of these devices. All observations were based on statistical measurements to account for random errors. The results of this work demonstrate that solid electrolyte based interconnects display self

  17. Towards Quantifying Programmable Logic Controller Resilience Against Intentional Exploits

    DTIC Science & Technology

    2012-03-22

    the metric applicable. The data used for this research is derived from PLC simulations executed on LogixPro ® 500 software. The definition for...applied to the SUT are primarily fixed attributes of the PLC emulation provided by LogixPro ® 500; the varying parameter during experimentation is the...programmed in ladder logic from a laptop with the accompanying LogixPro ® 500 software package associated with the PLC. The program is loaded to the

  18. Preliminary surface-emitting laser logic device evaluation

    NASA Astrophysics Data System (ADS)

    Libby, S. I.; Parker, M. A.; Olbright, G. R.; Swanson, P. D.

    1993-03-01

    This report discusses the evaluation of a monolithically integrated heterojunction phototransistor and vertical-cavity surface-emitting laser, designated the surface-Emitting Laser Logic device (CELL). Included is a discussion of the device structure and theory of operation, test procedures, results, and conclusions. Also presented is the CELL's opto-electronic input/output characteristics which includes spectral analysis, characteristic emitted light versus current and current versus voltage curves, input wavelength tolerance, output wavelength sensitivity to bias current, and insensitivity to input wavelength and power within a specified range.

  19. Binary Arithmetic Using Optical Symbolic Substitution and Cascadable Surface-Emitting Laser Logic Devices,

    DTIC Science & Technology

    LOGIC DEVICES, *OPTICAL CIRCUITS, *OPTICAL SWITCHING, HETEROJUNCTIONS, PHOTOTRANSISTORS, ELECTROOPTICS, LASER CAVITIES, OPTICAL PROCESSING, PARALLEL PROCESSING, BISTABLE DEVICES, GATES(CIRCUITS), VOLTAGE, BINARY ARITHMETIC .

  20. Radio Frequency Based Programmable Logic Controller Anomaly Detection

    DTIC Science & Technology

    2013-09-01

    RF- DNA Transform . . . . . . . . . . . . . . . . . . . . 49 3.7 Region of Interest Selection . . . . . . . . . . . . . . . . . . . . 52 3.8 CBAD...Device, NB=60, NOp=5 . . . . . . . . . . . . . . . 71 4.4 Software Anomaly Detection: RF- DNA Sequences . . . . . . . . 74 vii Page 4.4.1 Single Device...Waveforms . . . . . . . . . . . . . . 50 3.11 RF- DNA Fingerprint Diagram . . . . . . . . . . . . . . . . . 53 3.12 Representative Collected Scan Waveform

  1. Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

    ERIC Educational Resources Information Center

    Todorovich, E.; Marone, J. A.; Vazquez, M.

    2012-01-01

    Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

  2. Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

    ERIC Educational Resources Information Center

    Todorovich, E.; Marone, J. A.; Vazquez, M.

    2012-01-01

    Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

  3. A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

    ERIC Educational Resources Information Center

    Kellett, C. M.

    2012-01-01

    This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is…

  4. Multifunctional devices and logic gates with undoped silicon nanowires.

    PubMed

    Mongillo, Massimo; Spathis, Panayotis; Katsaros, Georgios; Gentile, Pascal; De Franceschi, Silvano

    2012-06-13

    We report on the electronic transport properties of multiple-gate devices fabricated from undoped silicon nanowires. Understanding and control of the relevant transport mechanisms was achieved by means of local electrostatic gating and temperature-dependent measurements. The roles of the source/drain contacts and of the silicon channel could be independently evaluated and tuned. Wrap gates surrounding the silicide-silicon contact interfaces were proved to be effective in inducing a full suppression of the contact Schottky barriers, thereby enabling carrier injection down to liquid helium temperature. By independently tuning the effective Schottky barrier heights, a variety of reconfigurable device functionalities could be obtained. In particular, the same nanowire device could be configured to work as a Schottky barrier transistor, a Schottky diode, or a p-n diode with tunable polarities. This versatility was eventually exploited to realize a NAND logic gate with gain well above one.

  5. 242-A/LERF programmable Logic Controller Ladder. Revision 1

    SciTech Connect

    Teats, M.C.

    1995-05-23

    This document defines and describes the user-generated application software written to transmit digital and analog signals from the Liquid Effluent Retention Facility (LERF) to the 242-A Evaporator Distributed Control System (DCS). PLCs and modems were installed in the 242-A Evaporator by Project W-105 (LERF) to transmit 6 analog liquid level signals, 6 range alarms based on the analog signals, and 6 leak detection and pump status signals to the 242-A Distributive Control System (DCS) from LERF. Communications between the two facilities are also monitored and alarm on the DCS. Following the Project W-105 completion, the communications and signal mix were modified by Project C-018H (ETF). The current PLC software (including ladder logic and data tables), PLC hardware settings, and modern option settings to transmit the signals and monitor communications are documented and described in this document.

  6. Current-limiting challenges for all-spin logic devices

    PubMed Central

    Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

    2015-01-01

    All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications. PMID:26449410

  7. Lateral Programmable Metallization Cell Devices And Applications

    NASA Astrophysics Data System (ADS)

    Ren, Minghan

    2011-12-01

    Programmable Metallization Cell (PMC) is a technology platform which utilizes mass transport in solid or liquid electrolyte coupled with electrochemical (redox) reactions to form or remove nanoscale metallic electrodeposits on or in the electrolyte. The ability to redistribute metal mass and form metallic nanostructure in or on a structure in situ, via the application of a bias on laterally placed electrodes, creates a large number of promising applications. A novel PMC-based lateral microwave switch was fabricated and characterized for use in microwave systems. It has demonstrated low insertion loss, high isolation, low voltage operation, low power and low energy consumption, and excellent linearity. Due to its non-volatile nature the switch operates with fewer biases and its simple planar geometry makes possible innovative device structures which can be potentially integrated into microwave power distribution circuits. PMC technology is also used to develop lateral dendritic metal electrodes. A lateral metallic dendritic network can be grown in a solid electrolyte (GeSe) or electrodeposited on SiO2 or Si using a water-mediated method. These dendritic electrodes grown in a solid electrolyte (GeSe) can be used to lower resistances for applications like self-healing interconnects despite its relatively low light transparency; while the dendritic electrodes grown using water-mediated method can be potentially integrated into solar cell applications, like replacing conventional Ag screen-printed top electrodes as they not only reduce resistances but also are highly transparent. This research effort also laid a solid foundation for developing dendritic plasmonic structures. A PMC-based lateral dendritic plasmonic structure is a device that has metallic dendritic networks grown electrochemically on SiO2 with a thin layer of surface metal nanoparticles in liquid electrolyte. These structures increase the distribution of particle sizes by connecting pre-deposited Ag

  8. 242-A Control System device logic software documentation. Revision 2

    SciTech Connect

    Berger, J.F.

    1995-05-19

    A Distributive Process Control system was purchased by Project B-534. This computer-based control system, called the Monitor and Control System (MCS), was installed in the 242-A Evaporator located in the 200 East Area. The purpose of the MCS is to monitor and control the Evaporator and Monitor a number of alarms and other signals from various Tank Farm facilities. Applications software for the MCS was developed by the Waste Treatment System Engineering Group of Westinghouse. This document describes the Device Logic for this system.

  9. Firmware Counterfeiting and Modification Attacks on Programmable Logic Controllers

    DTIC Science & Technology

    2013-03-01

    RTUs ) are field devices designed to control physical aspects of the system . SCADA systems branch out over various communication channels to assorted... RTUs that control and monitor actual physical objects in the system such as valves and sensors. Another type of ICS, called a distributed control system ...DISTRIBUTION UNLIMITED. AFIT-ENG-13-M-06 Abstract Recent attacks on industrial control systems (ICSs), like the highly publicized Stuxnet malware, have

  10. Towards manufacturing of advanced logic devices by double-patterning

    NASA Astrophysics Data System (ADS)

    Koay, Chiew-seng; Halle, Scott; Holmes, Steven; Petrillo, Karen; Colburn, Matthew; van Dommelen, Youri; Jiang, Aiqin; Crouse, Michael; Dunn, Shannon; Hetzer, David; Kawakami, Shinichiro; Cantone, Jason; Huli, Lior; Rodgers, Martin; Martinick, Brian

    2011-04-01

    As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes, alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting 16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity (CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure (CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction method. The effects of the exposure field size are also compared between a small field and the full field. Included in all the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.

  11. 46 CFR 62.25-25 - Programmable systems and devices.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 46 Shipping 2 2014-10-01 2014-10-01 false Programmable systems and devices. 62.25-25 Section 62.25-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM AUTOMATION General Requirements for All Automated Vital Systems § 62.25-25 Programmable systems and...

  12. Towards building a prototype spin-logic device

    NASA Astrophysics Data System (ADS)

    Penumatcha, Ashish Verma

    Since the late 1980s, several key discoveries, such as Giant and Tunneling Magne- toresistance, and advances in magnetic materials have paved the way for exponentially higher bit-densities in magnetic storage. In particular, the discovery of Spin-Transfer Torque (STT) has allowed information to be written to individual magnets using spin-currents. This has replaced the more traditional Oersted-field control used in field-MRAMs and allowed further scaling of magnetic-memories. A less obvious con- sequence of STT is that it has made possible a logic-technology based on magnets controlled by spin-polarized currents. Charge-coupled Spin Logic (CSL) is one such device proposal that couples a giant spin Hall effect(GSHE) write-unit with a Mag- netic Tunnel Junction read-unit. Several theoretical reports have demonstrated that a CSL-style device can function as a fundamental building block for neuromorphic computing by harnessing the intrinsic properties of magnets. This thesis describes the working of a CSL device. Experimental progress towards building the individual components of CSL and also our efforts to integrate these components into a CSL prototype will be presented. In addition to the integration effort, this work also explores spin-injection from a GSHE metal to a nanoscale magnet through an intermediate non-magnetic metal. Our results indicate that with the right choice of intermediate layers, the spin-angular mo- mentum absorbed by the magnet can be increased without engineering the intrinsic spin Hall angle of the GSHE metal. Finally, this work also proposes a Schottky-barrier model to describe the current flow through low-dimensional semiconductors and uses it to extract the band gap of black-phosphorus thin-films in an attempt to characterize novel 2D-materials.

  13. D0 General Support: The Use of Programmable Logic Controllers (PLCS) at D0

    SciTech Connect

    Hance, R.; /Fermilab

    2000-05-05

    With the exception of control of heating, ventilation, and air conditioning (HVAC) ventilation fans, and their shutdown in the case of smoke in the ducts, all implementations of Programmable Logic Controllers (PLCs) in Dzero have been made within the fundamental premise that no uncertified PLC apparatus shall be entrusted with the safety of equipment or personnel. Thus although PLCs are used to control and monitor all manner of intricate equipment, simple hardware interlocks and relief devices provide basic protection against component failure, control failure, or inappropriate control operation. Nevertheless, this report includes two observations as follows: (1) It may be prudent to reconfigure the link between the Pyrotronics system and the HVAC system such that the Pyrotronics system provides interlocks to the ventilation fans instead of control inputs to the uncertified HVAC PLCs. Although the Pyrotronics system is certified and maintained to life safety standards, the HVAC system is not. A hardware or software failure of the HVAC system probably should not be allowed to result in the situation where the ventilation fans in a smoke filled duct continue to operate. Dan Markley is investigating this matter. (2) It may also be prudent to examine the network security of those systems connected to the Fermilab WAN (HVAC, Cryo, and Solenoid Controls). Even though the impact of a successful hack might only be to operations, it might nevertheless be disruptive and could be expensive. The risks should perhaps be analyzed. One of the most attractive features of these systems, from a user's viewpoint, is their unlimited networking. The unlimited networking that makes the systems so convenient to legitimate access also makes them vulnerable to illegitimate access.

  14. A power-efficient and non-volatile programmable logic array based on phase change memory

    NASA Astrophysics Data System (ADS)

    Du, Yuan; Ye, Yong; Kang, Yong; Xia, Yangyang; Song, Zhitang; Chen, Bomy

    2016-10-01

    Recently, numerous efforts have been made on NVM-based Field Programmable Gate Arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can't be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, Programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of Programmable Element is OFF.

  15. Application of programmable logic controller to pump regulation system for supplying water

    NASA Astrophysics Data System (ADS)

    Ye, Dao-Yi; Yang, Yong-Bin; Lu, Zong-Qi

    This paper describes a pump regulation system for supplying-water. The controlled variable is the output water pressure for supplying-water pumps. The reference input signal is given in PLC. The water pressure for supplying-water pump output is fed back by a A/D converter to CPU in PLC. The output of Programmable Logic Controller Controls a frequency converter. The frequency converter controls three groups of motor-pump. The water from the three pumps enters the same pipe. Programmable Logic Controller (PLC) uses Ladder-shaped diagram software to implement logical control and proportional-plus-integral control. The method for automatic tuning of regulator of the PID type is based on a simple identification method which gives one point on the Nyquist curve of the open loop transfer function. The key idea is a scheme which provides automatic excitation of the process which is nearly optimal for estimating the desired process characteristics. Only a frequency converter controls several groups of motor pumps, therefore, the cost of the system is decreased. This system has electrically breaking off protection function and automatically restoring software. Through a long time operation, the system can work well.

  16. Programmable logic controller performance enhancement by field programmable gate array based design.

    PubMed

    Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

    2015-01-01

    PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported.

  17. Novel nano materials for high performance logic and memory devices

    NASA Astrophysics Data System (ADS)

    Das, Saptarshi

    After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

  18. Programmable synaptic devices for electronic neural nets

    NASA Technical Reports Server (NTRS)

    Moopenn, A.; Thakoor, A. P.

    1990-01-01

    The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

  19. Programmable synaptic devices for electronic neural nets

    NASA Technical Reports Server (NTRS)

    Moopenn, A.; Thakoor, A. P.

    1990-01-01

    The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

  20. A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell

    NASA Astrophysics Data System (ADS)

    Tsai, Yi-Hung; Yang, Hsiao-Lan; Lin, Wun-Jie; Lin, Chrong Jung; King, Ya-Chin

    2010-04-01

    This work presents a novel differential n-channel logic-compatible multiple-time programmable (MTP) memory cell. This cell features double sensing window by a differential pair of floating gates, and therefore increases the retention lifetime of the nonvolatile memory effectively. Also, a self-selective programming (SSP) method is innovated in writing one pair differential data by a single cell without increasing any design or process complexity in peripheral circuit. The differential cell is a promising MTP solution to challenge thin floating gate oxide below 70 Å for 90 nm complementary metal-oxide-semiconductor (CMOS) node and beyond.

  1. Model-based pattern dummy generation for logic devices

    NASA Astrophysics Data System (ADS)

    Jang, Jongwon; Kim, Cheolkyun; Ko, Sungwoo; Byun, Seokyoung; Yang, Hyunjo; Yim, Donggyu

    2014-03-01

    The insertion of SRAF(Sub-Resolution Assist Feature) is one of the most frequently used method to enlarge the process window area. In most cases, the size of SRAF is proportional to the focus margin of drawn patterns. However, there is a trade-off between the SRAF size and SRAF printing, because SRAF is not supposed to be patterned on a wafer. For this reason, a lot of OPC engineers have been tried to put bigger and more SRAFs within the limits of the possible. The fact that many papers about predicting SRAF printability have been published recent years reflects this circumstance. Pattern dummy is inserted to enhance the lithographic process margin and CD uniformity unlike CMP dummy for uniform metal line height. It is ordinary to put pattern dummy at the designated location under consideration of the pitch of real patterns at design step. However, it is not always desirable to generate pattern dummies based on rules at the lithographic point of view. In this paper, we introduce the model based pattern dummy insertion method, which is putting pattern dummies at the location that model based SRAF is located. We applied the model based pattern dummy to the layers in logic devices, and studied which layer is more efficient for the insertion of dummies.

  2. Improvement of photovoltaic pumping systems based on standard frequency converters by means of programmable logic controllers

    SciTech Connect

    Fernandez-Ramos, Jose; Narvarte-Fernandez, Luis; Poza-Saura, Fernando

    2010-01-15

    Photovoltaic pumping systems (PVPS) based on standard frequency converters (SFCs) are currently experiencing a growing interest in pumping programmes implemented in remote areas because of their high performance in terms of component reliability, low cost, high power range and good availability of components virtually anywhere in the world. However, in practical applications there have appeared a number of problems related to the adaptation of the SFCs to the requirements of the photovoltaic pumping systems (PVPS). Another disadvantage of dedicated PVPS is the difficulty in implementing maximum power point tracking (MPPT). This paper shows that these problems can be solved through the addition of a basic industrial programmable logic controller (PLC) to the system. This PLC does not increase the cost and complexity of the system, but improves the adaptation of the SFC to the photovoltaic pumping system, and increases the overall performance of the system. (author)

  3. The research and applications of programmable analog device

    NASA Astrophysics Data System (ADS)

    Yang, Xiaohui; Zhao, Qiudi; Yang, Yongjian

    2005-01-01

    This paper introduces the inner structure principle and signal adjusting applications of programmable analogy device ispPAC which was manufactured by Lattice semiconductor company.It expounds the chip functions of agility,diverse amplification,smoothing and deamplification at length and discusses the design method of every function.

  4. Toward Automating Web Protocol Configuration for a Programmable Logic Controller Emulator

    DTIC Science & Technology

    2014-06-19

    logic controllers ( PLC ). PLC emulators used as honeypots can provide insight into these vulnerabilities. Honeypots can sometimes deter attackers from...real devices and log activity. A variety of PLC emulators exist, but require manual configuration to change their PLC profile. This limits their...flexibility for deployment. An automated process for configuring PLC emulators can open the door for emulation of many types of PLCs . This study

  5. The Programmable Logic Controller and its application in nuclear reactor systems

    SciTech Connect

    Palomar, J.; Wyman, R.

    1993-09-01

    This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out.

  6. A logical molecular circuit for programmable and autonomous regulation of protein activity using DNA aptamer-protein interactions.

    PubMed

    Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R; Tan, Weihong

    2012-12-26

    Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo. (1) As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here, we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy.

  7. All optical logic operations using semiconductor optical amplifier based devices

    NASA Astrophysics Data System (ADS)

    Wang, Qiang

    High-speed optical processing technologies are essential for the construction of all-optical networks in the information era. In this Ph. D. thesis dissertation, essential mechanisms related to the semiconductor optical amplifier (SOA) based device such as the gain and phase dynamics when a short pulse in propagating inside SOA, and, all-optical Boolean function, XOR, AND and OR have been studied. In order to realize the all-optical logic using SOA, the nonlinear gain and phase dynamics in SOA need to be studied first. The experimental results of 10--90% gain recovery curve have been presented. The recovery time is related to the carrier lifetime of the SOA and it varies with gain compression and bias current. For pulse width of a few picosecond, intraband effects need to be considered. In the SOA, phase change is also induced when a short pulse is propagating inside SOA. Unlike the conventional way of estimating the phase shift using alpha factor, the maximum phase shift is obtained first, then the effective alpha factor is calculated. The experimental results of all optical Boolean function XOR and OR at 80 Gb/s are presented using SOA-MZI-DI and SOA-DI respectively. These are the highest operating speed that has been reported. The all optical AND operation at 40 Gb/s using SOA-MZI have also been reported here. The numerical simulation shows that the performance of these all-optical Boolean operations is limited by the carrier lifetime of the SOA. The Boolean functions are the first step towards all optical circuits. The designs of a parity checker and a pseudo-random binary sequence (PRBS) generator are demonstrated. The error analysis using quality factor and eye-diagram is also presented.

  8. Saltwell Leak Detector Station Programmable Logic Controller (PLC) Software Configuration Management Plan (SCMP)

    SciTech Connect

    WHITE, K.A.

    2000-11-28

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell Leak Detector Stations as required by HNF-PRO-309, Rev. 1, Computer Software Quality Assurance, Section 2.4, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell Leak Detector Station Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell Leak Detector Station PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis.

  9. Saltwell PIC Skid Programmable Logic Controller (PLC) Software Configuration Management Plan

    SciTech Connect

    KOCH, M.R.

    1999-11-16

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell PIC Skids as required by LMH-PRO-309, Rev. 0, Computer Software Quality Assurance, Section 2.6, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell PIC Skid Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell PIC Skid PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis.

  10. Implementation of motor speed control using PID control in programmable logic controller

    NASA Astrophysics Data System (ADS)

    Samin, R. E.; Azmi, N. A.; Ahmad, M. A.; Ghazali, M. R.; Zawawi, M. A.

    2012-11-01

    This paper presents the implementation of motor speed control using Proportional Integral Derrivative (PID) controller using Programmable Logic Controller (PLC). Proportional Integral Derrivative (PID) controller is the technique used to actively control the speed of the motor. An AC motor is used in the research together with the PLC, encoder and Proface touch screen. The model of the PLC that has been used in this project is OMRON CJIG-CPU42P where this PLC has a build in loop control that can be made the ladder diagram quite simple using function block in CX-process tools. A complete experimental analysis of the technique in terms of system response is presented. Comparative assessment of the impact of Proportional, Integral and Derivative in the controller on the system performance is presented and discussed.

  11. Programmable logic controller implementation of an auto-tuned predictive control based on minimal plant information.

    PubMed

    Valencia-Palomo, G; Rossiter, J A

    2011-01-01

    This paper makes two key contributions. First, it tackles the issue of the availability of constrained predictive control for low-level control loops. Hence, it describes how the constrained control algorithm is embedded in an industrial programmable logic controller (PLC) using the IEC 61131-3 programming standard. Second, there is a definition and implementation of a novel auto-tuned predictive controller; the key novelty is that the modelling is based on relatively crude but pragmatic plant information. Laboratory experiment tests were carried out in two bench-scale laboratory systems to prove the effectiveness of the combined algorithm and hardware solution. For completeness, the results are compared with a commercial proportional-integral-derivative (PID) controller (also embedded in the PLC) using the most up to date auto-tuning rules.

  12. Controlling High Power Devices with Computers or TTL Logic Circuits

    ERIC Educational Resources Information Center

    Carlton, Kevin

    2002-01-01

    Computers are routinely used to control experiments in modern science laboratories. This should be reflected in laboratories in an educational setting. There is a mismatch between the power that can be delivered by a computer interfacing card or a TTL logic circuit and that required by many practical pieces of laboratory equipment. One common way…

  13. Controlling High Power Devices with Computers or TTL Logic Circuits

    ERIC Educational Resources Information Center

    Carlton, Kevin

    2002-01-01

    Computers are routinely used to control experiments in modern science laboratories. This should be reflected in laboratories in an educational setting. There is a mismatch between the power that can be delivered by a computer interfacing card or a TTL logic circuit and that required by many practical pieces of laboratory equipment. One common way…

  14. Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

    PubMed Central

    Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

    2014-01-01

    A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

  15. Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design.

    DTIC Science & Technology

    2014-09-26

    microns %H*SIC dimensions. Part 2: Various Programmable Logic Array (PLA) implementations with clocked CMOS technology are explored inthis project...Previous research at MSU has dealt with clocked CMOS circuit styles with some application to gate array and microprocessor applications. Work under this...in this report deals with structured logic schemes based on Programmable Logic Arrays (PLAs). Three different PLA design methods are reported with a

  16. Electrically reconfigurable logic array

    NASA Technical Reports Server (NTRS)

    Agarwal, R. K.

    1982-01-01

    To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

  17. Evaluation of commercial programmable floating gate devices as radiation dosimeters

    NASA Astrophysics Data System (ADS)

    Edgecock, R.; Matheson, J.; Weber, M.; Giulio Villani, E.; Bose, R.; Khan, A.; Smith, D. R.; Adil-Smith, I.; Gabrielli, A.

    2009-02-01

    Programmable floating gate MOSFET transistors were tested with gamma radiation with doses up to approximately 100Gy (air equivalent), to evaluate their suitability as dosimeters in radiotherapy. After characterization and programming at different threshold voltages, the devices were irradiated and their Vgs shift with dose monitored in real time. Post-irradiation analysis was carried out to evaluate sensitivity, linearity, reproducibility and voltage threshold annealing. A subsequent re-programming phase followed by characterization was performed to asses their post-irradiation charge restoring capabilities. It was found that up to 73% of the initial maximum threshold voltage could be recovered. A sensitivity of up to 9 mV/Gy with an uncertainty of less than 1%, an excellent linearity up to the maximum programmable threshold voltage and low noise suggest the use of this technology for in vivo dosimetry applications.

  18. Ion-tuned DNA/Ag fluorescent nanoclusters as versatile logic device.

    PubMed

    Li, Tao; Zhang, Libing; Ai, Jun; Dong, Shaojun; Wang, Erkang

    2011-08-23

    A novel kind of versatile logic device has been constructed utilizing ion-tuned DNA/Ag fluorescent nanoclusters, with K(+) and H(+) as two inputs. A well-chosen hairpin DNA with a poly-C loop serves as the template for synthesizing two species of Ag nanoclusters. Several G-tracts and C-tracts on its two terminals enable the hairpin DNA to convert into the G-quadruplex and/or i-motif structures upon input of K(+) and H(+). Such a structural change remarkably influences the spectral behaviors of Ag nanoclusters. In particular, different species of Ag nanoclusters have distinct fluorescence responses to the input of K(+) and H(+). These unique features of DNA/Ag nanoclusters enable multiple logic operations via multichannel fluorescence output, indicating the versatility as a molecular logic device. By altering the specific sequence of the hairpin DNA, more logic gates can be constructed utilizing Ag nanoclusters.

  19. RSFQ logic devices; non-linear properties and experimental investigations

    NASA Astrophysics Data System (ADS)

    Mygind, Jesper

    1998-05-01

    Rapid Single Flux Quantum (RSFQ) logic has a great potential as fast digital and high frequency analog electronics. Several Logic/Memory base elements and integrated sub-systems in the RSFQ family have been devised and tested since the pioneering work in the mid 1980s by K. K. Likharev's group at Moscow State University [1,2]. It is argumented why the RSFQ digital circuits are superior to the voltage state family circuits, which were utilised in the first development of Josephson logic. Also the parameter space for operation of the 1-D RSFQ transmission line is discussed. Presently most RSFQ circuits are made with low-Tc superconductors using the now mature whole-wafer NbAlOxNb technology, which allows for large and densely packed integrated circuits. Recently, a few operational high-Tc RSFQ circuits have been reported. An important development within the last two years is the advent of general-purpose on-chip bit-by-bit verification test systems. Timing of RSFQ circuits and a few recent RSFQ "highlights" are briefly mentioned. Basically the RSFQ technology appears "ready" for widespread industrial use. One of the key components is the RSFQ transmission line, which can both generate and transmit SFQ pulses. In order to demonstrate the importance of the fluxon dynamics we discuss a new phenomenon observed in a parallel array of identical junctions. Steps with extremely low differential resistance in the I-V characteristic are found to be due to the self-induced magnetic field produced by the edge current fed to the array. The underlying mechanism is that the nonuniform field divides the moving fluxon into "domains" covering several (unit) cells. The experimental/numerical results illustrate practical and may be more fundamental limits to RSFQ electronics.

  20. Development and use of the generic WHO/CDC logic model for vitamin and mineral interventions in public health programmes.

    PubMed

    De-Regil, Luz Maria; Peña-Rosas, Juan Pablo; Flores-Ayala, Rafael; del Socorro Jefferds, Maria Elena

    2014-03-01

    Nutrition interventions are critical to achieve the Millennium Development Goals; among them, micronutrient interventions are considered cost-effective and programmatically feasible to scale up, but there are limited tools to communicate the programme components and their relationships. The WHO/CDC (Centers for Disease Control and Prevention) logic model for micronutrient interventions in public health programmes is a useful resource for planning, implementation, monitoring and evaluation of these interventions, which depicts the programme theory and expected relationships between inputs and expected Millennium Development Goals. The model was developed by applying principles of programme evaluation, public health nutrition theory and programmatic expertise. The multifaceted and iterative structure validation included feedback from potential users and adaptation by national stakeholders involved in public health programmes' design and implementation. In addition to the inputs, main activity domains identified as essential for programme development, implementation and performance include: (i) policy; (ii) products and supply; (iii) delivery systems; (iv) quality control; and (v) behaviour change communication. Outputs encompass the access to and coverage of interventions. Outcomes include knowledge and appropriate use of the intervention, as well as effects on micronutrient intake, nutritional status and health of target populations, for ultimate achievement of the Millennium Development Goals. The WHO/CDC logic model simplifies the process of developing a logic model by providing a tool that has identified high-priority areas and concepts that apply to virtually all public health micronutrient interventions. Countries can adapt it to their context in order to support programme design, implementation, monitoring and evaluation for the successful scale-up of nutrition interventions in public health.

  1. The spatial and logical organization of devices in an advanced industrial robot system

    NASA Technical Reports Server (NTRS)

    Ruoff, C. F.

    1980-01-01

    This paper describes the geometrical and device organization of a robot system which is based in part upon transformations of Cartesian frames and exchangeable device tree structures. It discusses coordinate frame transformations, geometrical device representation and solution degeneracy along with the data structures which support the exchangeable logical-physical device assignments. The system, which has been implemented in a minicomputer, supports vision, force, and other sensors. It allows tasks to be instantiated with logically equivalent devices and it allows tasks to be defined relative to appropriate frames. Since these frames are, in turn, defined relative other frames this organization provides a significant simplification in task specification and a high degree of system modularity.

  2. The spatial and logical organization of devices in an advanced industrial robot system

    NASA Technical Reports Server (NTRS)

    Ruoff, C. F.

    1980-01-01

    This paper describes the geometrical and device organization of a robot system which is based in part upon transformations of Cartesian frames and exchangeable device tree structures. It discusses coordinate frame transformations, geometrical device representation and solution degeneracy along with the data structures which support the exchangeable logical-physical device assignments. The system, which has been implemented in a minicomputer, supports vision, force, and other sensors. It allows tasks to be instantiated with logically equivalent devices and it allows tasks to be defined relative to appropriate frames. Since these frames are, in turn, defined relative other frames this organization provides a significant simplification in task specification and a high degree of system modularity.

  3. Designing the Expanded Programme on Immunisation (EPI) as a service: Prioritising patients over administrative logic.

    PubMed

    McKnight, Jacob; Holt, Douglas B

    2014-01-01

    Expanded Programme on Immunisation (EPI) vaccination rates remain well below herd immunity in regions of many countries despite huge international resources devoted to both financing and access. We draw upon service marketing theory, organisational sociology, development anthropology and cultural consumer research to conduct an ethnographic study of vaccination delivery in Jimma Zone, Ethiopia - one such region. We find that Western public health sector policies are dominated by an administrative logic. Critical failures in delivery are produced by a system that obfuscates the on-the-ground problems that mothers face in trying to vaccinate their children, while instead prioritising administrative processes. Our ethnographic analysis of 83 mothers who had not vaccinated their children reveals key barriers to vaccination from a 'customer' perspective. While mothers value vaccination, it is a 'low involvement' good compared to the acute daily needs of a subsistence life. The costs imposed by poor service - such as uncaring staff with class hostilities, unpredictable and missed schedules and long waits - are too much and so they forego the service. Our service design framework illuminates specific service problems from the mother's perspective and points towards simple service innovations that could improve vaccination rates in regions that have poor uptake.

  4. Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications

    NASA Astrophysics Data System (ADS)

    Khatami, Yasin; Kang, Jiahao; Banerjee, Kaustav

    2013-01-01

    Negative resistance devices offer opportunities in design of compact and fast analog and digital circuits. However, their implementation in logic applications has been limited due to their small ON current to OFF current ratios (peak to valley ratio). In this paper, a design for a 2-port negative resistance device based on arm-chair graphene nanoribbon is presented. The proposed structure takes advantage of electrostatic doping, and offers high ON current (˜700 μA/μm) as well as ON current to OFF current ratio of more than 105. The effects of several design parameters such as doping profile, gate workfunction, bandgap, and hetero-interface characteristics are investigated to improve the performance of the proposed devices. The proposed device offers high flexibility in terms of the design and optimization, and is suitable for digital logic applications. A complementary logic is developed based on the proposed device, which can be operated down to 200 mV of supply voltage. The complementary logic is used in design of an ultra-compact bi-stable switching static memory cell. Due to its compactness and high drive current, the proposed memory cell can outperform the conventional static random access memory cells in terms of switching speed and power consumption.

  5. Novel spintronics devices for memory and logic: prospects and challenges for room temperature all spin computing

    NASA Astrophysics Data System (ADS)

    Wang, Jian-Ping

    An energy efficient memory and logic device for the post-CMOS era has been the goal of a variety of research fields. The limits of scaling, which we expect to reach by the year 2025, demand that future advances in computational power will not be realized from ever-shrinking device sizes, but rather by innovative designs and new materials and physics. Magnetoresistive based devices have been a promising candidate for future integrated magnetic computation because of its unique non-volatility and functionalities. The application of perpendicular magnetic anisotropy for potential STT-RAM application was demonstrated and later has been intensively investigated by both academia and industry groups, but there is no clear path way how scaling will eventually work for both memory and logic applications. One of main reasons is that there is no demonstrated material stack candidate that could lead to a scaling scheme down to sub 10 nm. Another challenge for the usage of magnetoresistive based devices for logic application is its available switching speed and writing energy. Although a good progress has been made to demonstrate the fast switching of a thermally stable magnetic tunnel junction (MTJ) down to 165 ps, it is still several times slower than its CMOS counterpart. In this talk, I will review the recent progress by my research group and my C-SPIN colleagues, then discuss the opportunities, challenges and some potential path ways for magnetoresitive based devices for memory and logic applications and their integration for room temperature all spin computing system.

  6. Exploring Spin-transfer-torque devices and memristors for logic and memory applications

    NASA Astrophysics Data System (ADS)

    Pajouhi, Zoha

    As scaling CMOS devices is approaching its physical limits, researchers have begun exploring newer devices and architectures to replace CMOS. Due to their non-volatility and high density, Spin Transfer Torque (STT) devices are among the most prominent candidates for logic and memory applications. In this research, we first considered a new logic style called All Spin Logic (ASL). Despite its advantages, ASL consumes a large amount of static power; thus, several optimizations can be performed to address this issue. We developed a systematic methodology to perform the optimizations to ensure stable operation of ASL. Second, we investigated reliable design of STT-MRAM bit-cells and addressed the conflicting read and write requirements, which results in overdesign of the bit-cells. Further, a Device/Circuit/Architecture co-design framework was developed to optimize the STT-MRAM devices by exploring the design space through jointly considering yield enhancement techniques at different levels of abstraction. Recent advancements in the development of memristive devices have opened new opportunities for hardware implementation of non-Boolean computing. To this end, the suitability of memristive devices for swarm intelligence algorithms has enabled researchers to solve a maze in hardware. In this research, we utilized swarm intelligence of memristive networks to perform image edge detection. First, we proposed a hardware-friendly algorithm for image edge detection based on ant colony. Next, we designed the image edge detection algorithm using memristive networks.

  7. Cellular signaling circuits interfaced with synthetic, post-translational, negating Boolean logic devices.

    PubMed

    Razavi, Shiva; Su, Steven; Inoue, Takanari

    2014-09-19

    A negating functionality is fundamental to information processing of logic circuits within cells and computers. Aiming to adapt unutilized electronic concepts to the interrogation of signaling circuits in cells, we first took a bottom-up strategy whereby we created protein-based devices that perform negating Boolean logic operations such as NOT, NOR, NAND, and N-IMPLY. These devices function in living cells within a minute by precisely commanding the localization of an activator molecule among three subcellular spaces. We networked these synthetic gates to an endogenous signaling circuit and devised a physiological output. In search of logic functions in signal transduction, we next took a top-down approach and computationally screened 108 signaling pathways to identify commonalities and differences between these biological pathways and electronic circuits. This combination of synthetic and systems approaches will guide us in developing foundations for deconstruction of intricate cell signaling, as well as construction of biomolecular computers.

  8. Cellular Signaling Circuits Interfaced with Synthetic, Post-Translational, Negating Boolean Logic Devices

    PubMed Central

    2014-01-01

    A negating functionality is fundamental to information processing of logic circuits within cells and computers. Aiming to adapt unutilized electronic concepts to the interrogation of signaling circuits in cells, we first took a bottom-up strategy whereby we created protein-based devices that perform negating Boolean logic operations such as NOT, NOR, NAND, and N-IMPLY. These devices function in living cells within a minute by precisely commanding the localization of an activator molecule among three subcellular spaces. We networked these synthetic gates to an endogenous signaling circuit and devised a physiological output. In search of logic functions in signal transduction, we next took a top–down approach and computationally screened 108 signaling pathways to identify commonalities and differences between these biological pathways and electronic circuits. This combination of synthetic and systems approaches will guide us in developing foundations for deconstruction of intricate cell signaling, as well as construction of biomolecular computers. PMID:25000210

  9. Irradiation of MOS-FET devices to provide desired logic functions

    NASA Technical Reports Server (NTRS)

    Danchenko, V.; Schaefer, D. H.

    1972-01-01

    Gamma, X-ray, electron, or other radiation is used to shift threshold potentials of MOS devices on logic circuits. Before irradiation MOS gates to be shifted are biased positive and other gates are grounded to substrate. Threshold lasts 10 years. Thermal annealing brings circuit back to original configuration.

  10. Selection of the logical model of the intellectual algorithm for dynamic processing of medical data (obtained through portable medical devices)

    NASA Astrophysics Data System (ADS)

    Starovoytova, V. A.; Taranik, M. A.

    2017-01-01

    Portable devices are one of the important emerging areas of modern medicine. This article presents the rationale for the selection of the logical model of the intellectual algorithm for dynamic processing of medical data obtained through portable medical devices. The description of the main criteria for the selection and application of the method of Saaty is provided. And the conclusion about the feasibility of using fuzzy logic as a logical model for the investigated subject area is made.

  11. Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic

    PubMed Central

    Shim, Jaewoo; Oh, Seyong; Kang, Dong-Ho; Jo, Seo-Hyeon; Ali, Muhammad Hasnain; Choi, Woo-Young; Heo, Keun; Jeon, Jaeho; Lee, Sungjoo; Kim, Minwoo; Song, Young Jae; Park, Jin-Hong

    2016-01-01

    Recently, negative differential resistance devices have attracted considerable attention due to their folded current–voltage characteristic, which presents multiple threshold voltage values. Because of this remarkable property, studies associated with the negative differential resistance devices have been explored for realizing multi-valued logic applications. Here we demonstrate a negative differential resistance device based on a phosphorene/rhenium disulfide (BP/ReS2) heterojunction that is formed by type-III broken-gap band alignment, showing high peak-to-valley current ratio values of 4.2 and 6.9 at room temperature and 180 K, respectively. Also, the carrier transport mechanism of the BP/ReS2 negative differential resistance device is investigated in detail by analysing the tunnelling and diffusion currents at various temperatures with the proposed analytic negative differential resistance device model. Finally, we demonstrate a ternary inverter as a multi-valued logic application. This study of a two-dimensional material heterojunction is a step forward toward future multi-valued logic device research. PMID:27819264

  12. Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic

    NASA Astrophysics Data System (ADS)

    Shim, Jaewoo; Oh, Seyong; Kang, Dong-Ho; Jo, Seo-Hyeon; Ali, Muhammad Hasnain; Choi, Woo-Young; Heo, Keun; Jeon, Jaeho; Lee, Sungjoo; Kim, Minwoo; Song, Young Jae; Park, Jin-Hong

    2016-11-01

    Recently, negative differential resistance devices have attracted considerable attention due to their folded current-voltage characteristic, which presents multiple threshold voltage values. Because of this remarkable property, studies associated with the negative differential resistance devices have been explored for realizing multi-valued logic applications. Here we demonstrate a negative differential resistance device based on a phosphorene/rhenium disulfide (BP/ReS2) heterojunction that is formed by type-III broken-gap band alignment, showing high peak-to-valley current ratio values of 4.2 and 6.9 at room temperature and 180 K, respectively. Also, the carrier transport mechanism of the BP/ReS2 negative differential resistance device is investigated in detail by analysing the tunnelling and diffusion currents at various temperatures with the proposed analytic negative differential resistance device model. Finally, we demonstrate a ternary inverter as a multi-valued logic application. This study of a two-dimensional material heterojunction is a step forward toward future multi-valued logic device research.

  13. Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic.

    PubMed

    Shim, Jaewoo; Oh, Seyong; Kang, Dong-Ho; Jo, Seo-Hyeon; Ali, Muhammad Hasnain; Choi, Woo-Young; Heo, Keun; Jeon, Jaeho; Lee, Sungjoo; Kim, Minwoo; Song, Young Jae; Park, Jin-Hong

    2016-11-07

    Recently, negative differential resistance devices have attracted considerable attention due to their folded current-voltage characteristic, which presents multiple threshold voltage values. Because of this remarkable property, studies associated with the negative differential resistance devices have been explored for realizing multi-valued logic applications. Here we demonstrate a negative differential resistance device based on a phosphorene/rhenium disulfide (BP/ReS2) heterojunction that is formed by type-III broken-gap band alignment, showing high peak-to-valley current ratio values of 4.2 and 6.9 at room temperature and 180 K, respectively. Also, the carrier transport mechanism of the BP/ReS2 negative differential resistance device is investigated in detail by analysing the tunnelling and diffusion currents at various temperatures with the proposed analytic negative differential resistance device model. Finally, we demonstrate a ternary inverter as a multi-valued logic application. This study of a two-dimensional material heterojunction is a step forward toward future multi-valued logic device research.

  14. A programmable nanoreplica molding for the fabrication of nanophotonic devices

    NASA Astrophysics Data System (ADS)

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-Min; Lu, Meng

    2016-03-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively.

  15. A programmable nanoreplica molding for the fabrication of nanophotonic devices

    PubMed Central

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-min; Lu, Meng

    2016-01-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively. PMID:26925828

  16. SLS complementary logic devices with increase carrier mobility

    DOEpatents

    Chaffin, R.J.; Osbourn, G.C.; Zipperian, T.E.

    1991-07-09

    In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated. 5 figures.

  17. SLS complementary logic devices with increase carrier mobility

    DOEpatents

    Chaffin, Roger J.; Osbourn, Gordon C.; Zipperian, Thomas E.

    1991-01-01

    In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.

  18. TAXONOMY OF MEDICAL DEVICES IN THE LOGIC OF HEALTH TECHNOLOGY ASSESSMENT.

    PubMed

    Henschke, Cornelia; Panteli, Dimitra; Perleth, Matthias; Busse, Reinhard

    2015-01-01

    The suitability of general HTA methodology for medical devices is gaining interest as a topic of scientific discourse. Given the broad range of medical devices, there might be differences between groups of devices that impact both the necessity and the methods of their assessment. Our aim is to develop a taxonomy that provides researchers and policy makers with an orientation tool on how to approach the assessment of different types of medical devices. Several classifications for medical devices based on varying rationales for different regulatory and reporting purposes were analyzed in detail to develop a comprehensive taxonomic model. The taxonomy is based on relevant aspects of existing classification schemes incorporating elements of risk and functionality. Its 9 × 6 matrix distinguishes between the diagnostic or therapeutic nature of devices and considers whether the medical device is directly used by patients, constitutes part of a specific procedure, or can be used for a variety of procedures. We considered the relevance of different device categories in regard to HTA to be considerably variable, ranging from high to low. Existing medical device classifications cannot be used for HTA as they are based on different underlying logics. The developed taxonomy combines different device classification schemes used for different purposes. It aims at providing decision makers with a tool enabling them to consider device characteristics in detail across more than one dimension. The placement of device groups in the matrix can provide decision support on the necessity of conducting a full HTA.

  19. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    NASA Technical Reports Server (NTRS)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  20. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    NASA Technical Reports Server (NTRS)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  1. Biofuel cell controlled by enzyme logic network--approaching physiologically regulated devices.

    PubMed

    Tam, Tsz Kin; Pita, Marcos; Ornatska, Maryna; Katz, Evgeny

    2009-09-01

    A "smart" biofuel cell switchable ON and OFF upon application of several chemical signals processed by an enzyme logic network was designed. The biocomputing system performing logic operations on the input signals was composed of four enzymes: alcohol dehydrogenase (ADH), amyloglucosidase (AGS), invertase (INV) and glucose dehydrogenase (GDH). These enzymes were activated by different combinations of chemical input signals: NADH, acetaldehyde, maltose and sucrose. The sequence of biochemical reactions catalyzed by the enzymes models a logic network composed of concatenated AND/OR gates. Upon application of specific "successful" patterns of the chemical input signals, the cascade of biochemical reactions resulted in the formation of gluconic acid, thus producing acidic pH in the solution. This resulted in the activation of a pH-sensitive redox-polymer-modified cathode in the biofuel cell, thus, switching ON the entire cell and dramatically increasing its power output. Application of another chemical signal (urea in the presence of urease) resulted in the return to the initial neutral pH value, when the O(2)-reducing cathode and the entire cell are in the mute state. The reversible activation-inactivation of the biofuel cell was controlled by the enzymatic reactions logically processing a number of chemical input signals applied in different combinations. The studied biofuel cell exemplifies a new kind of bioelectronic device where the bioelectronic function is controlled by a biocomputing system. Such devices will provide a new dimension in bioelectronics and biocomputing benefiting from the integration of both concepts.

  2. A new 28 nm high-k metal gate CMOS logic one-time programmable memory cell

    NASA Astrophysics Data System (ADS)

    Hsiao, Woan Yun; Mei, Chin Yu; Chao Shen, Wen; Der Chih, Yue; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This work presents a high density high-k metal gate (HKMG) one-time programmable (OTP) cell. Without additional processes and steps, this OTP cell is fully compatible to 28 nm HKMG CMOS process. The OTP cell adopts high-k dielectric breakdown as programming mechanism to obtain more than 105 times of on/off read window. Moreover, it features low power and fast program speed by 4.5 V program voltage in 100 µs. In addition to the ultrasmall cell area of 0.0425 µm2, the superior performance of disturb immunities and data retention further support the new logic OTP cell to be a very promising solution in advanced logic non-volatile memory (NVM) applications.

  3. System design specification for rotary mode core sample trucks No. 2, 3, and 4 programmable logic controller

    SciTech Connect

    Dowell, J.L.; Akers, J.C.

    1995-12-31

    The system this document describes controls several functions of the Core Sample Truck(s) used to obtain nuclear waste samples from various underground storage tanks at Hanford. The system will monitor the sampling process and provide alarms and other feedback to insure the sampling process is performed within the prescribed operating envelope. The intended audience for this document is anyone associated with rotary or push mode core sampling. This document describes the Alarm and Control logic installed on Rotary Mode Core Sample Trucks (RMCST) {number_sign}2, 3, and 4. It is intended to define the particular requirements of the RMCST alarm and control operation (not defined elsewhere) sufficiently for detailed design to implement on a Programmable Logic Controller (PLC).

  4. All-optical compact surface plasmonic two-mode interference device for optical logic gate operation.

    PubMed

    Gogoi, Nilima; Sahu, Partha Pratim

    2015-02-10

    In this paper, we have proposed an ultra-compact surface plasmonic two-mode interference (SPTMI) coupler having a silicon core, silver upper and lower cladding, and GaAsInP left and right cladding for basic logic gate operations. By modulating the refractive index of the GaAsInP cladding with incidence of optical pulse energy, we have shown coupling characteristics depending on additional phase change ΔΦ(E) between the excited surface plasmon polariton modes propagating through the silicon core. By using applied optical pulse dependent coupling behavior of the proposed SPTMI device, the operations of NOT, AND, and OR logic gates are shown. It is also seen that the coupling length of the proposed device is 32.3 times more compact than that of a multimode interference-directional coupler.

  5. CAMAC modular programmable function generator

    SciTech Connect

    Turner, G.W.; Suehiro, S.; Hendricks, R.W.

    1980-12-01

    A CAMAC modular programmable function generator has been developed. The device contains a 1024 word by 12-bit memory, a 12-bit digital-to-analog converter with a 600 ns settling time, an 18-bit programmable frequency register, and two programmable trigger output registers. The trigger registers can produce programmed output logic transitions at various (binary) points in the output function curve, and are used to synchronize various other data acquisition devices with the function curve.

  6. Programmable Potentials: Approximate N-body potentials from coarse-level logic

    PubMed Central

    Thakur, Gunjan S.; Mohr, Ryan; Mezić, Igor

    2016-01-01

    This paper gives a systematic method for constructing an N-body potential, approximating the true potential, that accurately captures meso-scale behavior of the chemical or biological system using pairwise potentials coming from experimental data or ab initio methods. The meso-scale behavior is translated into logic rules for the dynamics. Each pairwise potential has an associated logic function that is constructed using the logic rules, a class of elementary logic functions, and AND, OR, and NOT gates. The effect of each logic function is to turn its associated potential on and off. The N-body potential is constructed as linear combination of the pairwise potentials, where the “coefficients” of the potentials are smoothed versions of the associated logic functions. These potentials allow a potentially low-dimensional description of complex processes while still accurately capturing the relevant physics at the meso-scale. We present the proposed formalism to construct coarse-grained potential models for three examples: an inhibitor molecular system, bond breaking in chemical reactions, and DNA transcription from biology. The method can potentially be used in reverse for design of molecular processes by specifying properties of molecules that can carry them out. PMID:27671683

  7. Programmable Potentials: Approximate N-body potentials from coarse-level logic

    NASA Astrophysics Data System (ADS)

    Thakur, Gunjan S.; Mohr, Ryan; Mezić, Igor

    2016-09-01

    This paper gives a systematic method for constructing an N-body potential, approximating the true potential, that accurately captures meso-scale behavior of the chemical or biological system using pairwise potentials coming from experimental data or ab initio methods. The meso-scale behavior is translated into logic rules for the dynamics. Each pairwise potential has an associated logic function that is constructed using the logic rules, a class of elementary logic functions, and AND, OR, and NOT gates. The effect of each logic function is to turn its associated potential on and off. The N-body potential is constructed as linear combination of the pairwise potentials, where the “coefficients” of the potentials are smoothed versions of the associated logic functions. These potentials allow a potentially low-dimensional description of complex processes while still accurately capturing the relevant physics at the meso-scale. We present the proposed formalism to construct coarse-grained potential models for three examples: an inhibitor molecular system, bond breaking in chemical reactions, and DNA transcription from biology. The method can potentially be used in reverse for design of molecular processes by specifying properties of molecules that can carry them out.

  8. Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews.

    PubMed

    Kneale, Dylan; Thomas, James; Harris, Katherine

    2015-01-01

    Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to 'think' conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions.

  9. Spin-wave logic devices based on isotropic forward volume magnetostatic waves

    SciTech Connect

    Klingler, S. Pirro, P.; Brächer, T.; Leven, B.; Hillebrands, B.; Chumak, A. V.

    2015-05-25

    We propose the utilization of isotropic forward volume magnetostatic spin waves in modern wave-based logic devices and suggest a concrete design for a spin-wave majority gate operating with these waves. We demonstrate by numerical simulations that the proposed out-of-plane magnetized majority gate overcomes the limitations of anisotropic in-plane magnetized majority gates due to the high spin-wave transmission through the gate, which enables a reduced energy consumption of these devices. Moreover, the functionality of the out-of-plane majority gate is increased due to the lack of parasitic generation of short-wavelength exchange spin waves.

  10. Peptide logic circuits based on chemoenzymatic ligation for programmable cell apoptosis.

    PubMed

    Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huan, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhuo

    2017-10-03

    A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  11. Structured approach in PLC (programmable logic controller) programming for water/wastewater applications.

    PubMed

    Keskar, P Y

    1990-01-01

    This paper describes a methodology for efficient implementation of PLC programming for water/wastewater applications. The PLC was interfaced with a supervisory host computer which used touch screen equipped color monitors as operator interfaces. PLC ladder logic had to be designed to process real-world hardwired I/O as well as the I/O received from the host computer and/or touch screens, via a communications link. Standard "templates" of PLC networks were developed for (a) pump controls including provision for touch screen I/O; (b) PID control; (c) alarms; (d) motor run times; (e) square root extraction; (f) signal conversion, and (g) flow totalization. All logic was implemented using the standard templates. This structured approach led to efficient implementation, easy debugging/start-up, and easy to read uniform ladder logic.

  12. Versatile and Programmable DNA Logic Gates on Universal and Label-Free Homogeneous Electrochemical Platform.

    PubMed

    Ge, Lei; Wang, Wenxiao; Sun, Ximei; Hou, Ting; Li, Feng

    2016-10-04

    Herein, a novel universal and label-free homogeneous electrochemical platform is demonstrated, on which a complete set of DNA-based two-input Boolean logic gates (OR, NAND, AND, NOR, INHIBIT, IMPLICATION, XOR, and XNOR) is constructed by simply and rationally deploying the designed DNA polymerization/nicking machines without complicated sequence modulation. Single-stranded DNA is employed as the proof-of-concept target/input to initiate or prevent the DNA polymerization/nicking cyclic reactions on these DNA machines to synthesize numerous intact G-quadruplex sequences or binary G-quadruplex subunits as the output. The generated output strands then self-assemble into G-quadruplexes that render remarkable decrease to the diffusion current response of methylene blue and, thus, provide the amplified homogeneous electrochemical readout signal not only for the logic gate operations but also for the ultrasensitive detection of the target/input. This system represents the first example of homogeneous electrochemical logic operation. Importantly, the proposed homogeneous electrochemical logic gates possess the input/output homogeneity and share a constant output threshold value. Moreover, the modular design of DNA polymerization/nicking machines enables the adaptation of these homogeneous electrochemical logic gates to various input and output sequences. The results of this study demonstrate the versatility and universality of the label-free homogeneous electrochemical platform in the design of biomolecular logic gates and provide a potential platform for the further development of large-scale DNA-based biocomputing circuits and advanced biosensors for multiple molecular targets.

  13. Logic circuits based on individual semiconducting and metallic carbon-nanotube devices.

    PubMed

    Ryu, Hyeyeon; Kälblein, Daniel; Weitz, R Thomas; Ante, Frederik; Zschieschang, Ute; Kern, Klaus; Schmidt, Oliver G; Klauk, Hagen

    2010-11-26

    Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.

  14. A novel design-based global CDU metrology for 1X nm node logic devices

    NASA Astrophysics Data System (ADS)

    Yoon, Young-Keun; Chung, Dong H.; Kim, Min-Ho; Seo, Jung-Uk; Kim, Byung-Gook; Jeon, Chan-Uk; Hur, JiUk; Cho, Wonil; Yamamoto, Tetsuya

    2013-09-01

    As dimension of device shrinks to 1X nm node, an extreme control of critical dimension uniformity (CDU) of masks becomes one of key techniques for mask and wafer fabrication. For memory devices, a large number of optical techniques have been studied and applied to mask production so far. The advantages of these methods are to eliminate the sampling dependency due to their high throughput, to minimize the local CD errors due to their large field of view (FOV) and to improve the correlation with wafer infield uniformity if they have scanner-like optics. For logic devices, however, CD-SEM has been a single solution to characterize CD performance of logic masks for a long time and simple monitoring patterns, instead of the cell patterns, have been measured to monitor the CD quality of masks. Therefore a global CDU of the mask tends to show its ambiguity because of the limited number of measurement sites and large local CD errors. An application of optical metrology for logic mask is a challenging task because patterns are more complex and random in shape and because there is no guarantee of finding patterns for CDU everywhere on the mask. CDU map still consists of the results from the indirect measurements and the traditional definition of uniformity, a statistical deviation of a typical pattern, seems to be unsuitable for logic CDU. A new definition of CDU is required in order to maximize the coverage area on a mask. In this study, we have focused of the possibility of measuring cell patterns and of using an inspection tool with data base handling capability, KLA Teron617, to find the areas and positions where the repeating patterns exist and the patterns which satisfy a certain set of condition and we have devised a new definition of CDU, which can handle multiple target CDs. Then we have checked the feasibility and validity of our new methodology through evaluation its fundamental performance such as accuracy, repeatability, and correlation with other CD metrology

  15. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    SciTech Connect

    Mitra, Kalyan Yoti E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-17

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  16. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    NASA Astrophysics Data System (ADS)

    Mitra, Kalyan Yoti; Sowade, Enrico; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-01

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  17. Quantum logical gates with four-level superconducting quantum interference devices coupled to a superconducting resonator

    SciTech Connect

    He Xiaoling; Luo Junyan; Yang Chuiping; Li Sheng; Han Siyuan

    2010-08-15

    We propose a way for realizing a two-qubit controlled phase gate with superconducting quantum interference devices (SQUIDs) coupled to a superconducting resonator. In this proposal, the two lowest levels of each SQUID serve as the logical states and two intermediate levels of each SQUID are used for the gate realization. We show that neither adjustment of SQUID level spacings during the gate operation nor uniformity in SQUID parameters is required by this proposal. In addition, this proposal does not require the adiabatic passage or a second-order detuning and thus the gate is much faster.

  18. Remote Control Laboratory Using EJS Applets and TwinCAT Programmable Logic Controllers

    ERIC Educational Resources Information Center

    Besada-Portas, E.; Lopez-Orozco, J. A.; de la Torre, L.; de la Cruz, J. M.

    2013-01-01

    This paper presents a new methodology to develop remote laboratories for systems engineering and automation control courses, based on the combined use of TwinCAT, a laboratory Java server application, and Easy Java Simulations (EJS). The TwinCAT system is used to close the control loop for the selected plants by means of programmable logic…

  19. Remote Control Laboratory Using EJS Applets and TwinCAT Programmable Logic Controllers

    ERIC Educational Resources Information Center

    Besada-Portas, E.; Lopez-Orozco, J. A.; de la Torre, L.; de la Cruz, J. M.

    2013-01-01

    This paper presents a new methodology to develop remote laboratories for systems engineering and automation control courses, based on the combined use of TwinCAT, a laboratory Java server application, and Easy Java Simulations (EJS). The TwinCAT system is used to close the control loop for the selected plants by means of programmable logic…

  20. Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

    NASA Astrophysics Data System (ADS)

    Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

    2015-02-01

    A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer,a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

  1. Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

    PubMed

    Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

    2015-05-26

    Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

  2. Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes

    NASA Astrophysics Data System (ADS)

    Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Patil, Nishant; Lin, Albert; Mitra, Subhasish; Wong, H.-S. Philip; Zhou, Chongwu

    2008-07-01

    In this paper, high-performance back-gated carbon nanotube field-effect transistors based on transferred aligned carbon nanotubes were fabricated and studies found that the on/off ratio can reach 107 and the current density can reach 1.6μA/μm after electrical breakdown. In addition, chemical doping with hydrazine was used to convert the p-type aligned nanotube devices into n-type. These devices were further utilized to demonstrate various logic circuits, including p-type metal-oxide-semiconductor inverters, diode-loaded inverters, complementary metal-oxide-semiconductor inverters, NAND, and NOR gates. This approach could work as the platform for future nanotube-based nanoelectronics.

  3. Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews

    PubMed Central

    Kneale, Dylan; Thomas, James; Harris, Katherine

    2015-01-01

    Background Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to ‘think’ conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. Methods and Findings In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Conclusions Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions. PMID:26575182

  4. Current Radiation Issues for Programmable Elements and Devices

    NASA Technical Reports Server (NTRS)

    Katz, Richard; LaBel, K.; Reed, R.; Wang, J. J.; Cronquist, B.; McCollum, J.; Paolini, W.; Sin, B.; Koga, R.a; Crain, S.; hide

    1998-01-01

    The purpose of this presentation is to discuss the COTS performance, clock upset / single event transient, device configuration upset, antifuse hardening, heavy ion SEU, total dose, proton sensitivities, latchup, and additional information and data.

  5. Magnetic dipolar coupling and collective effects for binary information codification in cost-effective logic devices

    NASA Astrophysics Data System (ADS)

    Chiolerio, Alessandro; Allia, Paolo; Graziano, Mariagrazia

    2012-09-01

    Physical limitations foreshadow the eventual end to traditional Complementary Metal Oxide Semiconductor (CMOS) scaling. Therefore, interest has turned to various materials and technologies aimed to succeed to traditional CMOS. Magnetic Quantum dot Cellular Automata (MQCA) are one of these technologies. Working MQCA arrays require very complex techniques and an excellent control on the geometry of the nanomagnets and on the quality of the magnetic thin film, thus limiting the possibility for MQCA of representing a definite solution to cost-effective, high density and low power consumption device demand. Counter-intuitively, moving towards bigger sizes and lighter technologies it is still possible to develop multi-state logic devices, as we demonstrated, whose main advantage is cost-effectiveness. Applications may be seen in low cost logic devices where integration and computational power are not the main issue, eventually using flexible substrates and taking advantage of the intrinsic mechanical toughness of systems where long range interactions do not need wirings. We realized cobalt micrometric MQCA arrays by means of Electron Beam Lithography, exploiting cost-effective processes such as lift-off and RF sputtering that usually are avoided due to their low control on array geometry and film roughness. Information relative to the magnetic configuration of MQCA elements including their eventual magnetic interactions was obtained from Magnetic Force Microscope (MFM) images, enhanced by means of a numerical procedure and presented in differential maps. We report the existence of bi-stable magnetic patterns, as detected by MFM while sampling the z-component of magnetic induction field, arising from dipolar inter-element magnetostatic coupling, able to store and propagate binary information. This is achieved despite the array quality and element magnetic state, which are low and multi-domain, respectively. We discuss in detail shape, inter-element spacing and dot profile

  6. Energy consumption analysis of graphene based all spin logic device with voltage controlled magnetic anisotropy

    NASA Astrophysics Data System (ADS)

    Zhang, Zhizhong; Zhang, Yue; Zheng, Zhenyi; Wang, Guanda; Su, Li; Zhang, Youguang; Zhao, Weisheng

    2017-05-01

    All spin logic device (ASLD) is a promising option to realize the ultra-low power computing systems. However, the low spin transport efficiency and the non-local switching of the detector have become two key challenges of the ASLD. In this paper, we analyze the energy consumption of a graphene based ASLD with the ferromagnetic layer switching assistance by voltage control magnetic anisotropy (VCMA) effect. This structure has significant potential towards ultra-low power consumption: the applied voltage can not only shorten switching time of the ferromagnetic layer, but also decreases the critical injection current; the graphene channel enhances greatly the spin transport efficiency. By applying the approximate circuit model, the impact of material configurations, interfaces and geometry can be synthetically studied. An accurate physic model was also developed, based on which, we carry out the micro-magnetic simulations to analyze the magnetization dynamics. Combining these electrical and magnetic investigations, the energy consumption of the proposed ASLD can be estimated. With the optimizing parameters, the energy consumption can be reduced to 2.5 pJ for a logic operation.

  7. Magnetic-field-controlled reconfigurable semiconductor logic.

    PubMed

    Joo, Sungjung; Kim, Taeyueb; Shin, Sang Hoon; Lim, Ju Young; Hong, Jinki; Song, Jin Dong; Chang, Joonyeon; Lee, Hyun-Woo; Rhie, Kungwon; Han, Suk Hee; Shin, Kyung-Ho; Johnson, Mark

    2013-02-07

    Logic devices based on magnetism show promise for increasing computational efficiency while decreasing consumed power. They offer zero quiescent power and yet combine novel functions such as programmable logic operation and non-volatile built-in memory. However, practical efforts to adapt a magnetic device to logic suffer from a low signal-to-noise ratio and other performance attributes that are not adequate for logic gates. Rather than exploiting magnetoresistive effects that result from spin-dependent transport of carriers, we have approached the development of a magnetic logic device in a different way: we use the phenomenon of large magnetoresistance found in non-magnetic semiconductors in high electric fields. Here we report a device showing a strong diode characteristic that is highly sensitive to both the sign and the magnitude of an external magnetic field, offering a reversible change between two different characteristic states by the application of a magnetic field. This feature results from magnetic control of carrier generation and recombination in an InSb p-n bilayer channel. Simple circuits combining such elementary devices are fabricated and tested, and Boolean logic functions including AND, OR, NAND and NOR are performed. They are programmed dynamically by external electric or magnetic signals, demonstrating magnetic-field-controlled semiconductor reconfigurable logic at room temperature. This magnetic technology permits a new kind of spintronic device, characterized as a current switch rather than a voltage switch, and provides a simple and compact platform for non-volatile reconfigurable logic devices.

  8. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    SciTech Connect

    Gao, X.; Mamaluy, D.; Cyr, E. C.; Marinella, M. J.

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device is determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.

  9. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    DOE PAGES

    Gao, X.; Mamaluy, D.; Cyr, E. C.; ...

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

  10. Growth of β-Tungsten Films Towards a Giant Spin Hall Effect Logic Device

    NASA Astrophysics Data System (ADS)

    Jayanthinarasimham, Avyaya; Medikonda, Manasa; Matsubayashi, Akitomo; Khare, Prasanna; Chong, Hyuncher; Matyi, Richard; Diebold, Alain; Labella, Vincent

    2015-03-01

    Spin-orbit coupling in metastable β-W generates spin transfer torques strong enough to flip magnetic moment of an adjacent magnetic layer. In a MTJ stack these torques can be used to switch between high and low resistive states. This technique can be used in designing efficient magnetic memory and non-volatile spin logic devices. Deposition conditions selective to β- W need to be understood for the large scale fabrication of such devices. The transition from β to α phase of Tungsten is strongly governed by thickness of W layer, base pressure and oxygen availability for example, above 5 nm β film relaxes and forms an α phase. Resistivity measurements as well as x-ray photoelectron spectroscopy and x-ray diffraction and reflectivity analysis are performed to determine the phase and thickness of tungsten films. We show that β phase is influenced by ultrathin thermal oxide of Si layer and the amount of oxygen flow during the growth. These results demonstrate a reliable technique to fabricate β W film up to 20 nm on bare Si and silicon dioxide, while providing insight to growing it anywhere in the device stack.

  11. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    SciTech Connect

    Gao, X.; Mamaluy, D.; Cyr, E. C.; Marinella, M. J.

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device is determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.

  12. Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

    NASA Technical Reports Server (NTRS)

    Taylor, B.

    1990-01-01

    The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

  13. The use of programmable logic controllers (PLC) for rocket engine component testing

    NASA Technical Reports Server (NTRS)

    Nail, William; Scheuermann, Patrick; Witcher, Kern

    1991-01-01

    Application of PLCs to the rocket engine component testing at a new Stennis Space Center Component Test Facility is suggested as an alternative to dedicated specialized computers. The PLC systems are characterized by rugged design, intuitive software, fault tolerance, flexibility, multiple end device options, networking capability, and built-in diagnostics. A distributed PLC-based system is projected to be used for testing LH2/LOx turbopumps required for the ALS/NLS rocket engines.

  14. The use of programmable logic controllers (PLC) for rocket engine component testing

    NASA Technical Reports Server (NTRS)

    Nail, William; Scheuermann, Patrick; Witcher, Kern

    1991-01-01

    Application of PLCs to the rocket engine component testing at a new Stennis Space Center Component Test Facility is suggested as an alternative to dedicated specialized computers. The PLC systems are characterized by rugged design, intuitive software, fault tolerance, flexibility, multiple end device options, networking capability, and built-in diagnostics. A distributed PLC-based system is projected to be used for testing LH2/LOx turbopumps required for the ALS/NLS rocket engines.

  15. Design and theoretical investigation of a silicon-on-insulator based electro-optical logic gate device

    NASA Astrophysics Data System (ADS)

    Li, Lei; Qi, Zhipeng; Hu, Guohua; Yun, Binfeng; Zhong, Yuan; Cui, Yiping

    2016-10-01

    A compact electro-optical "NOR" logic gate device based on silicon-on-insulator (SOI) platform is proposed and investigated theoretically. By introducing a hook-type waveguide, the signal could be coupled between the bus and hook-type waveguide to form an optical circuit and realize NOR logic gate. We can easily realize the NOR logical function by the voltage applied on the coupling components. The numerical simulation shows that a high coupling efficiency of more than 99% is obtained at the wavelength of 1550 nm, and the footprint of our device is smaller than 90 μm2. In addition, the response time of the proposed NOR logic gate is 3 ns with a switching voltage of 1.8 V. Moreover, it is demonstrated that such NOR logic gate device could obtain an extinction ratio of 21.8 dB. Thus, it has great potential to achieve high speed response, low power consumption, and small footprint, which fulfill the demands of next-generation on-chip computer multiplex processors.

  16. [Left ventricle assist device: rehabilitation and management programmes].

    PubMed

    D'agrosa-Boiteux, M-C; Geoffroy, E; Dauphin, N; Camilleri, L; Eschalier, R; Cuenin, C; Moisa, A

    2014-09-01

    Progress in the medical management of patients with heart failure with systolic dysfunction has been accompanied by a significant improvement in survival and quality of life. These strategies have also resulted in changes in the clinical profile as well as an increase in the number of patients with advanced heart failure. The technological developments in left ventricular assist devices provide real hope for these patients. This article related our experience of management and the rehabilitation program realized.

  17. High-frequency programmable acoustic wave device realized through ferroelectric domain engineering

    NASA Astrophysics Data System (ADS)

    Ivry, Yachin; Wang, Nan; Durkan, Colm

    2014-03-01

    Surface acoustic wave devices are extensively used in contemporary wireless communication devices. We used atomic force microscopy to form periodic macroscopic ferroelectric domains in sol-gel deposited lead zirconate titanate, where each ferroelectric domain is composed of many crystallites, each of which contains many microscopic ferroelastic domains. We examined the electro-acoustic characteristics of the apparatus and found a resonator behavior similar to that of an equivalent surface or bulk acoustic wave device. We show that the operational frequency of the device can be tailored by altering the periodicity of the engineered domains and demonstrate high-frequency filter behavior (>8 GHz), allowing low-cost programmable high-frequency resonators.

  18. SnO2 nanowire logic devices on deformable nonplanar substrates.

    PubMed

    Shin, Gunchul; Bae, Min Young; Lee, Hyun Jin; Hong, Sahng Ki; Yoon, Chang Hoon; Zi, Goangseup; Rogers, John A; Ha, Jeong Sook

    2011-12-27

    Logic inverters consisting of n-type FETs and resistors with SnO(2) nanowire channels were fabricated on films of the elastomer polydimethylsiloxane, prestrained and flattened into planar sheets from initial, preformed hemispherical shapes. Upon release, thin and narrow interconnects between individual devices in the arrays absorb induced strain by buckling into nonplanar sinusoidal shapes, to allow full recovery of the surfaces to their original convex geometries. The same physics allows deformation of convex shapes into concave ones, as well as more complex surfaces of coexisting convex and concave areas, and small regions with extremely stretched, locally tapered forms, all nondestructively achieved while maintaining electrical performance, enhanced by use of air gap gate dielectrics. This work shows, more generally, that nanowire devices with both conventional and unusual designs can be integrated into overall systems with irregular, nonplanar layouts, easily deformed in reversible fashion without any measurable alteration in electrical characteristics. The results suggest potential applicability of nanowire technologies in systems of tissue-matched implantable electronics for mounting directly on human organs or of sensor skins for integration with robotic manipulators.

  19. A programmable and portable NMES device for drop foot correction and blood flow assist applications.

    PubMed

    Breen, Paul P; Corley, Gavin J; O'Keeffe, Derek T; Conway, Richard; Olaighin, Gearóid

    2009-04-01

    The Duo-STIM, a new, programmable and portable neuromuscular stimulation system for drop foot correction and blood flow assist applications is presented. The system consists of a programmer unit and a portable, programmable stimulator unit. The portable stimulator features fully programmable, sensor-controlled, constant-voltage, dual-channel stimulation and accommodates a range of customized stimulation profiles. Trapezoidal and free-form adaptive stimulation intensity envelope algorithms are provided for drop foot correction applications, while time dependent and activity dependent algorithms are provided for blood flow assist applications. A variety of sensor types can be used with the portable unit, including force sensitive resistor-based foot switches and MEMS-based accelerometer and gyroscope devices. The paper provides a detailed description of the hardware and block-level system design for both units. The programming and operating procedures for the system are also presented. Finally, functional bench test results for the system are presented.

  20. On the Spot: Using Mobile Devices for Listening and Speaking Practice on a French Language Programme

    ERIC Educational Resources Information Center

    Demouy, Valerie; Kukulska-Hulme, Agnes

    2010-01-01

    This paper presents and discusses the initial findings of a mobile language learning project undertaken in the context of an undergraduate distance-learning French language programme at The Open University (UK). The overall objective of the project was to investigate students' experiences when using their own portable devices for additional…

  1. On the Spot: Using Mobile Devices for Listening and Speaking Practice on a French Language Programme

    ERIC Educational Resources Information Center

    Demouy, Valerie; Kukulska-Hulme, Agnes

    2010-01-01

    This paper presents and discusses the initial findings of a mobile language learning project undertaken in the context of an undergraduate distance-learning French language programme at The Open University (UK). The overall objective of the project was to investigate students' experiences when using their own portable devices for additional…

  2. Automated hotspot analysis with aerial image CD metrology for advanced logic devices

    NASA Astrophysics Data System (ADS)

    Buttgereit, Ute; Trautzsch, Thomas; Kim, Min-ho; Seo, Jung-Uk; Yoon, Young-Keun; Han, Hak-Seung; Chung, Dong Hoon; Jeon, Chan-Uk; Meyers, Gary

    2014-09-01

    Continuously shrinking designs by further extension of 193nm technology lead to a much higher probability of hotspots especially for the manufacturing of advanced logic devices. The CD of these potential hotspots needs to be precisely controlled and measured on the mask. On top of that, the feature complexity increases due to high OPC load in the logic mask design which is an additional challenge for CD metrology. Therefore the hotspot measurements have been performed on WLCD from ZEISS, which provides the benefit of reduced complexity by measuring the CD in the aerial image and qualifying the printing relevant CD. This is especially of advantage for complex 2D feature measurements. Additionally, the data preparation for CD measurement becomes more critical due to the larger amount of CD measurements and the increasing feature diversity. For the data preparation this means to identify these hotspots and mark them automatically with the correct marker required to make the feature specific CD measurement successful. Currently available methods can address generic pattern but cannot deal with the pattern diversity of the hotspots. The paper will explore a method how to overcome those limitations and to enhance the time-to-result in the marking process dramatically. For the marking process the Synopsys WLCD Output Module was utilized, which is an interface between the CATS mask data prep software and the WLCD metrology tool. It translates the CATS marking directly into an executable WLCD measurement job including CD analysis. The paper will describe the utilized method and flow for the hotspot measurement. Additionally, the achieved results on hotspot measurements utilizing this method will be presented.

  3. Automated hot-spot fixing system applied for metal layers of 65 nm logic devices

    NASA Astrophysics Data System (ADS)

    Kobayashi, Sachiko; Kyoh, Suigen; Kotani, Toshiya; Tanaka, Satoshi; Inoue, Soichi

    2006-05-01

    Hot spot clearance using process simulation is indispensable under low-k1 lithography process for logic devices of 65 nm and below. Hot spots such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Appropriate calibration of design rule (DR), mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of design at hot spot will be effective, but it takes too much time to determine how to modify layout to be consistent with DR, MDP/OPC rule, and the process often needs to be iterative. Therefore, there is a need for an automated hot spot fixing system is capable of fixing design layout so as to avoid fatal hot spot occurrence, with sufficient process margin and short turn around time (TAT). We developed an automated hot-spot fixing system, Hot Spot Fixer (HSF). The basic system flow in the developed system is as follows; Design data is processed with the conventional mask data preparation process. Then, process simulation is performed to extract hot spots. The hot spots are categorized by lithography error mode, critical level, and surrounding context. An intelligent hot-spot modification instructor, taking the surrounding situation into consideration, generates modification guide for the every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. If necessary, several modification candidates are indicated and the user can choose the most adequate one from them. The design modification process is verified from every aspect, using Design Rule Checker (DRC) and process simulation. The modified design data, with reduced potential hot spot compared with pre

  4. Shot number analysis on character projection e-beam lithography for random logic device fabrication at 70-nm node

    NASA Astrophysics Data System (ADS)

    Tomo, Yoichi; Shimizu, Isao; Kojima, Yoshinori; Yoshida, Akira; Takenaka, Hiroshi; Yamabe, Masaki

    2001-08-01

    A reduction efficiency of shot numbers in character projection (CP) electron-beam (EB) lithography with memory device application depends on a design rule (cell size) and a pattern complexity within a memory cell. Many researchers reported that it was approximately 1/10 to 1/100 compared with conventional variable-shaped beam (VSB) method. The reduction of shot numbers in memory devices mainly comes from allowance to place multiple cells in one CP-cell area and simplicity of the cell's placement (regular pitch with adjacent allocation). On the other hand, there are few reports concerning reduction efficiency of shot numbers with logic specific application in CP EB lithography due to the complexity of logic cell's allocation to CP-cell area. To analyze this, logic device layout data in 70nm node was prepared by shringking actual functional device data of 350 nm node in the ratio of 1/5 and extracting random logic region. The size of this region was 1,094 x 283 micrometers . The height of logic cell was 2.64micrometers and it was smaller than typical one CP-cell size in second aperture (5 x 5micrometers ). The pattern data in GDS-II stream format was converted into EB exposure data: divided figures (rectangles). By this procedure, numbers of figures and cells were obtained. The total number of referred logic cell was 26,812. Among 26,812 cells, only 111 common (unique) logic cells were used for the logic region. The sum of figures in gate layer was 412,251 and this value was assumed to be equal to a total number of shots in conventional VSB method. Among the 111 common cells, only 6 cells in the gate layer showed width more than 5micrometers (maximum CP-cell size). Most frequently referred cell was an inverter and the number of reference was 5,395. The referred frequency of each cell exponentially decreased when the cells were arranged in descending order of reference. Among the total figures, top cell showed 66,120 accumulated number of figures (referred number=2

  5. The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

    SciTech Connect

    Hu, Jiaxi; Haratipour, Nazila; Koester, Steven J.

    2015-05-07

    All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare the effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau–Lifshitz–Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.

  6. High-frequency programmable acoustic wave device realized through ferroelectric domain engineering

    SciTech Connect

    Ivry, Yachin E-mail: cd229@eng.cam.ac.uk; Wang, Nan; Durkan, Colm E-mail: cd229@eng.cam.ac.uk

    2014-03-31

    Surface acoustic wave devices are extensively used in contemporary wireless communication devices. We used atomic force microscopy to form periodic macroscopic ferroelectric domains in sol-gel deposited lead zirconate titanate, where each ferroelectric domain is composed of many crystallites, each of which contains many microscopic ferroelastic domains. We examined the electro-acoustic characteristics of the apparatus and found a resonator behavior similar to that of an equivalent surface or bulk acoustic wave device. We show that the operational frequency of the device can be tailored by altering the periodicity of the engineered domains and demonstrate high-frequency filter behavior (>8 GHz), allowing low-cost programmable high-frequency resonators.

  7. Development and Validation of a Miniature Programmable tDCS Device.

    PubMed

    Kouzani, Abbas Z; Jaberzadeh, Shapour; Zoghi, Maryam; Usma, Clara; Parastarfeizabadi, Mahboubeh

    2016-01-01

    Research is being conducted on the use of transcranial direct current stimulation (tDCS) for therapeutic effects, and also on the mechanisms through which such therapeutic effects are mediated. A bottleneck in the progress of the research has been the large size of the existing tDCS systems which prevents subjects from performing their daily activities. To help research into the principles, mechanisms, and benefits of tDCS, reduction of size and weight, improvement in simplicity and user friendliness, portability, and programmability of tDCS systems are vital. This paper presents a design for a low-cost, light-weight, programmable, and portable tDCS device. The device is head-mountable and can be concealed in a hat and worn on the head by the subject while receiving the stimulation. The strength of the direct current stimulation can be selected through a simple user interface. The device is constructed and its performance evaluated through bench and in vivo tests. The tests validated the operation of the device in inducing neuromodulatory changes in primary motor cortex, M1, through measuring excitability of dominant M1 of resting right first dorsal interosseus muscle by transcranial magnetic stimulation induced motor evoked potentials. It was observed that the tDCS device induced comparable neuromodulatory effects in M1 as the existing bulky tDCS systems.

  8. Extraordinary Transport Characteristics and Multivalue Logic Functions in a Silicon-Based Negative-Differential Transconductance Device.

    PubMed

    Lee, Sejoon; Lee, Youngmin; Kim, Changmin

    2017-09-11

    High-performance negative-differential transconductance (NDT) devices are fabricated in the form of a gated p(+)-i-n(+) Si ultra-thin body transistor. The devices clearly display a Λ-shape transfer characteristic (i.e., Λ-NDT peak) at room temperature, and the NDT behavior is fully based on the gate-modulation of the electrostatic junction characteristics along source-channel-drain. The largest peak-to-valley current ratio of the Λ-NDT peak is greater than 10(4), the smallest full-width at half-maximum is smaller than 170 mV, and the best swing-slope at the Λ-NDT peak region is ~70 mV/dec. The position and the current level of the Λ-NDT peaks are systematically-controllable when modulating the junction characteristics by controlling only bias voltages at gate and/or drain. These unique features allow us to demonstrate the multivalue logic functions such as a tri-value logic and a quattro-value logic. The results suggest that the present type of the Si Λ-NDT device could be prospective for next-generation arithmetic circuits.

  9. Reliability concerns with logical constants in Xilinx FPGA designs

    SciTech Connect

    Quinn, Heather M; Graham, Paul; Morgan, Keith; Ostler, Patrick; Allen, Greg; Swift, Gary; Tseng, Chen W

    2009-01-01

    In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.

  10. Stitching-aware in-design DPT auto fixing for sub-20nm logic devices

    NASA Astrophysics Data System (ADS)

    Choi, Soo-Han; Sai Krishna, K. V. V. S.; Pemberton-Smith, David

    2017-03-01

    As the technology continues to shrink below 20nm, Double Patterning Technology (DPT) becomes one of the mandatory solutions for routing metal layers. From the view point of Place and Route (P&R), the major concerns are how to prevent DPT odd-cycles automatically without sacrificing chip area. Even though the leading-edge P&R tools have advanced algorithms to prevent DPT odd-cycles, it is very hard to prevent the localized DPT odd-cycles, especially in Engineering Change Order (ECO) routing. In the last several years, we developed In-design DPT Auto Fixing method in order to reduce localized DPT odd-cycles significantly during ECO and could achieve remarkable design Turn-Around Times (TATs). But subsequently, as the design complexity continued increasing and chip size continued decreasing, we needed a new In-design DPT Auto Fixing approach to improve the auto. fixing rate. In this paper, we present the Stitching-Aware In-design DPT Auto Fixing method for better fixing rates and smaller chip design. The previous In-design DPT Auto Fixing method detected all DPT odd-cycles and tried to remove oddcycles by increasing the adjacent space. As the metal congestions increase in the newer technology nodes, the older Auto Fixing method has limitations to increase the adjacent space between routing metals. Consequently, the auto fixing rate of older method gets worse with the introduction of the smaller design rules. With DPT stitching enablement at In-design DRC checking procedure, the new Stitching-Aware DPT Auto Fixing method detects the most critical odd-cycles and revolve the odd-cycles automatically. The accuracy of new flow ensures better usage of space in the congested areas, and helps design more smaller chips. By applying the Stitching-Aware DPT Auto Fixing method to sub-20nm logic devices, we can confirm that the auto fixing rate is improved by 2X compared with auto fixing without stitching. Additionally, by developing the better heuristic algorithm and flow for DPT

  11. Digital programmable light spectrum synthesis system using a digital micromirror device.

    PubMed

    Chuang, C H; Lo, Y L

    2006-11-10

    We present a digital programmable light spectrum synthesis system based on a digital micromirror device (DMD) from Texas Instruments. A DMD pattern-scanning calibration method is developed and applied to the synthesis of various infrared C-band (1530-1565 nm) spectral profiles, including a fast programmable tunable light source with a bandwidth of approximately 3.8 nm, a square profile, a sawtooth waveform, and a triangular spectrum profile. The experimental results show that the wavelength resolution of the DMD spectrum synthesis system is approximately 0.076 nm/pixel. The proposed spectrum synthesis system has a number of key advantages, including a rapid and stable performance and multichannel compatibility. The spectrum synthesis system is suitable for various applications, including pulse shaping for coherent control and harmonic generation, a tunable light source, an equalizer for erbium-doped fiber amplifiers, and a wavelength scanner.

  12. Optical logic and signal processing using a semiconductor laser diode-based optical bistability device

    NASA Astrophysics Data System (ADS)

    Zhang, Yuancheng; Song, Qian; He, Shaowei

    1995-02-01

    Using an optical fibre-coupled semiconductor laser diode OBD with output feedback pumping operation in 5 modes (differential gain, bistability, zero-bias, inverted differential gain, and inverted bistability) has been realized respectively, and 5 elementary optical logic functions (AND, OR, NOT, NAND, and NOR) and some optical signal processing such as limiting, reshaping, and triggering have been implemented.

  13. THRESHOLD LOGIC IN ARTIFICIAL INTELLIGENCE

    DTIC Science & Technology

    COMPUTER LOGIC, ARTIFICIAL INTELLIGENCE , BIONICS, GEOMETRY, INPUT OUTPUT DEVICES, LINEAR PROGRAMMING, MATHEMATICAL LOGIC, MATHEMATICAL PREDICTION, NETWORKS, PATTERN RECOGNITION, PROBABILITY, SWITCHING CIRCUITS, SYNTHESIS

  14. Boolean logic tree of graphene-based chemical system for molecular computation and intelligent molecular search query.

    PubMed

    Huang, Wei Tao; Luo, Hong Qun; Li, Nian Bing

    2014-05-06

    The most serious, and yet unsolved, problem of constructing molecular computing devices consists in connecting all of these molecular events into a usable device. This report demonstrates the use of Boolean logic tree for analyzing the chemical event network based on graphene, organic dye, thrombin aptamer, and Fenton reaction, organizing and connecting these basic chemical events. And this chemical event network can be utilized to implement fluorescent combinatorial logic (including basic logic gates and complex integrated logic circuits) and fuzzy logic computing. On the basis of the Boolean logic tree analysis and logic computing, these basic chemical events can be considered as programmable "words" and chemical interactions as "syntax" logic rules to construct molecular search engine for performing intelligent molecular search query. Our approach is helpful in developing the advanced logic program based on molecules for application in biosensing, nanotechnology, and drug delivery.

  15. Static control logic for microfluidic devices using pressure-gain valves

    NASA Astrophysics Data System (ADS)

    Weaver, James A.; Melin, Jessica; Stark, Don; Quake, Stephen R.; Horowitz, Mark A.

    2010-03-01

    Microfluidic technology has developed greatly in recent years, enabling multiple analysis systems to be placed on a microfluidic chip. However, microfluidic large-scale integration of control elements analogous to those achieved in the microelectronics industry is still a challenge. We present an integrated microfluidic valve, compatible with standard soft-lithography processes, which has a pressure gain much greater than unity. We show that this enables integration of fully static digital control logic and state storage directly on-chip, ultimately enabling microfluidic-state machines to be designed. Outputs from this digital control logic can then be used to control traditional analyte flow valves. This strategy enables much of the bulky external hardware at present used to control pneumatically driven microfluidic chips in the laboratory to be transferred onto the microfluidic chip, which drastically reduces the required number of external chip connections.

  16. Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

    NASA Astrophysics Data System (ADS)

    Roy, Debapriya; Biswas, Abhijit

    2016-09-01

    Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4-0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of ION by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.

  17. Project W-058 monitor and control system logic

    SciTech Connect

    ROBERTS, J.B.

    1999-05-12

    This supporting document contains the printout of the control logic for the Project W-058 Monitor and Control System, as developed by Programmable Control Services, Inc. The logic is arranged in five appendices, one for each programmable logic controller console.

  18. Molecular implementation of simple logic programs

    NASA Astrophysics Data System (ADS)

    Ran, Tom; Kaplan, Shai; Shapiro, Ehud

    2009-11-01

    Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) <-- Man(X) (Every Man is Mortal), the system can answer molecular queries such as Mortal(Socrates)? (Is Socrates Mortal?) and Mortal(X)? (Who is Mortal?). This biomolecular computing system compares favourably with previous approaches in terms of expressive power, performance and precision. A compiler translates facts, rules and queries into their molecular representations and subsequently operates a robotic system that assembles the logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

  19. Polymer-based electrochemical devices for logic functions and paper displays

    NASA Astrophysics Data System (ADS)

    Berggren, Magnus; Nilsson, David; Chen, Miaoxiang; Andersson, Peter; Kugler, Thomas; Malmstroem, Anna; Haell, Jessica; Remonen, Tommi; Robinson, Nathaniel D.

    2003-07-01

    Here, we report on devices based on patterned thin films of the conducting polymer system poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulphonic acid) (PEDOT:PSS) combined with patterns of solid electrolyte. The key device functionalities base on the updating of the RedOx state of PEDOT. This results in control of the electronic properties of this conjugated polymer, i.e. the conductivity and optical properties are updated. Based on this we have achieved electric current rectifiers, transistors and display cells. Also, matrix addressed displays will be presented. Electrochemical switching is taking place when the oxidation and reduction potentials are overcome respectively. Therefore, these devices operate at voltage levels less then 2 Volts. Low voltage operation is achieved in devices not requiring any extremely narrow dimensions, as is the case for field effect driven devices. All devices reported can or has been made using standard printing techniques on flexible carriers.

  20. Sensor sentinel computing device

    DOEpatents

    Damico, Joseph P.

    2016-08-02

    Technologies pertaining to authenticating data output by sensors in an industrial environment are described herein. A sensor sentinel computing device receives time-series data from a sensor by way of a wireline connection. The sensor sentinel computing device generates a validation signal that is a function of the time-series signal. The sensor sentinel computing device then transmits the validation signal to a programmable logic controller in the industrial environment.

  1. Programmable spectral engine design of hyperspectral image projectors based on digital micro-mirror device (DMD)

    NASA Astrophysics Data System (ADS)

    Wang, Xicheng; Gao, Jiaobo; Wu, Jianghui; Li, Jianjun; Cheng, Hongliang

    2017-02-01

    Recently, hyperspectral image projectors (HIP) have been developed in the field of remote sensing. For the advanced performance of system-level validation, target detection and hyperspectral image calibration, HIP has great possibility of development in military, medicine, commercial and so on. HIP is based on the digital micro-mirror device (DMD) and projection technology, which is capable to project arbitrary programmable spectra (controlled by PC) into the each pixel of the IUT1 (instrument under test), such that the projected image could simulate realistic scenes that hyperspectral image could be measured during its use and enable system-level performance testing and validation. In this paper, we built a visible hyperspectral image projector also called the visible target simulator with double DMDs, which the first DMD is used to product the selected monochromatic light from the wavelength of 410 to 720 um, and the light come to the other one. Then we use computer to load image of realistic scenes to the second DMD, so that the target condition and background could be project by the second DMD with the selected monochromatic light. The target condition can be simulated and the experiment could be controlled and repeated in the lab, making the detector instrument could be tested in the lab. For the moment, we make the focus on the spectral engine design include the optical system, research of DMD programmable spectrum and the spectral resolution of the selected spectrum. The detail is shown.

  2. Generation-3 programmable array microscope (PAM) with digital micro-mirror device (DMD)

    NASA Astrophysics Data System (ADS)

    De Beule, Pieter A. A.; de Vries, Anthony H. B.; Arndt-Jovin, Donna J.; Jovin, Thomas M.

    2011-03-01

    We report progress on the construction of an optical sectioning programmable array microscope (PAM) implemented with a digital micro-mirror device (DMD) spatial light modulator (SLM) utilized for both fluorescence illumination and detection. The introduction of binary intensity modulation at the focal plane of a microscope objective in a computer controlled pixilated mode allows the recovery of an optically sectioned image. Illumination patterns can be changed very quickly, in contrast to static Nipkow disk or aperture correlation implementations, thereby creating an optical system that can be optimized to the optical specimen in a convenient manner, e.g. for patterned photobleaching, photobleaching reduction, or spatial superresolution. We present a third generation (Gen-3) dual path PAM module incorporating the 25 kHz binary frame rate TI 1080p DMD and a newly developed optical system that offers diffraction limited imaging with compensation of tilt angle distortion.

  3. Programmable immersive peripheral environmental system (PIPES): a prototype control system for environmental feedback devices

    NASA Astrophysics Data System (ADS)

    Frend, Chauncey; Boyles, Michael

    2015-03-01

    This paper describes an environmental feedback device (EFD) control system aimed at simplifying the VR development cycle. Programmable Immersive Peripheral Environmental System (PIPES) affords VR developers a custom approach to programming and controlling EFD behaviors while relaxing the required knowledge and expertise of electronic systems. PIPES has been implemented for the Unity engine and features EFD control using the Arduino integrated development environment. PIPES was installed and tested on two VR systems, a large format CAVE system and an Oculus Rift HMD system. A photocell based end-to-end latency experiment was conducted to measure latency within the system. This work extends previously unpublished prototypes of a similar design. Development and experiments described in this paper are part of the VR community goal to understand and apply environment effects to VEs that ultimately add to users' perceived presence.

  4. Programmable controlled mode-locked fiber laser using a digital micromirror device.

    PubMed

    Liu, Wu; Fan, Jintao; Xie, Chen; Song, Youjian; Gu, Chenlin; Chai, Lu; Wang, Chingyue; Hu, Minglie

    2017-05-15

    A digital micromirror device (DMD)-based arbitrary spectrum amplitude shaper is incorporated into a large-mode-area photonic crystal fiber laser cavity. The shaper acts as an in-cavity programmable filter and provides large tunable dispersion from normal to anomalous. As a result, mode-locking is achieved in different dispersion regimes with watt-level high output power. By programming different filter profiles on the DMD, the laser generates femtosecond pulse with a tunable central wavelength and controllable bandwidth. Under conditions of suitable cavity dispersion and pump power, design-shaped spectra are directly obtained by varying the amplitude transfer function of the filter. The results show the versatility of the DMD-based in-cavity filter for flexible control of the pulse dynamics in a mode-locked fiber laser.

  5. Programmable nanowire circuits for nanoprocessors.

    PubMed

    Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

    2011-02-10

    A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated

  6. Novel Design for Reversible Arithmetic Logic Unit

    NASA Astrophysics Data System (ADS)

    Zhou, Rigui; Li, Yancheng; Zhang, Manqun; Hu, BenQiong

    2015-02-01

    Reversible logic circuits are of high interests to calculate with minimum energy consumption having applications in low-power CMOS design, optical computing and nanotechnology, especially in quantum computer. Quantum computer requires quantum arithmetic. A new design of a reversible arithmetic logic unit (reversible ALU) for quantum arithmetic has been proposed in this article. As we known, ALU is an important part of central processing unit (CPU) as the execution unit. So this article provides explicit construction of reversible ALU effecting basic arithmetic operations. By provided the corresponding control unit, the proposed reversible ALU can combine the classical arithmetic and logic operation in a reversible integrated system. This article provides a new more powerful ALU which contains more functions and it will make contribute to the realization of reversible Programmable Logic Device (RPLD) in future using reversible ALU.

  7. Quantum logic gate operation and entanglement with superconducting quantum interference devices in a cavity via a Raman transition

    SciTech Connect

    Song, K.-H.; Zhou, Z.-W.; Guo, G.-C.

    2005-05-15

    In the system with superconducting quantum interference devices (SQUIDs) in cavity, the quantum logic gates operation and entanglement can be achieved by using a quantized cavity field and classical microwave pluses, via Raman transition. In this scheme, no transfer of quantum information between the SQUIDs and cavity is required, the cavity field is only virtually excited and thus the cavity decay is suppressed during the gate operation and entanglement generations. The gate operation and entanglement generations are realized by using only the two lower flux states of the SQUID system and the excited state would not be excited. Therefore, the effect of docoherence based on the levels of the SQUID system is possible to minimize.

  8. Customizable 3D Printed ‘Plug and Play’ Millifluidic Devices for Programmable Fluidics

    PubMed Central

    Tsuda, Soichiro; Jaffery, Hussain; Doran, David; Hezwani, Mohammad; Robbins, Phillip J.; Yoshida, Mari; Cronin, Leroy

    2015-01-01

    Three dimensional (3D) printing is actively sought after in recent years as a promising novel technology to construct complex objects, which scope spans from nano- to over millimeter scale. Previously we utilized Fused deposition modeling (FDM)-based 3D printer to construct complex 3D chemical fluidic systems, and here we demonstrate the construction of 3D milli-fluidic structures for programmable liquid handling and control of biological samples. Basic fluidic operation devices, such as water-in-oil (W/O) droplet generators for producing compartmentalized mono-disperse droplets, sensor-integrated chamber for online monitoring of cellular growth, are presented. In addition, chemical surface treatment techniques are used to construct valve-based flow selector for liquid flow control and inter-connectable modular devices for networking fluidic parts. As such this work paves the way for complex operations, such as mixing, flow control, and monitoring of reaction / cell culture progress can be carried out by constructing both passive and active components in 3D printed structures, which designs can be shared online so that anyone with 3D printers can reproduce them by themselves. PMID:26558389

  9. Vertically Stackable Novel One-Time Programmable Nonvolatile Memory Devices Based on Dielectric Breakdown Mechanism

    NASA Astrophysics Data System (ADS)

    Cho, Seongjae; Lee, Jung Hoon; Ryoo, Kyung-Chang; Jung, Sunghun; Lee, Jong-Ho; Park, Byung-Gook

    2011-12-01

    In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array structures based on silicon technology are proposed. There have been many features of OTP NVM devices utilizing various combinations of channel, breakdown region, barrier, and contact materials. However, this invention can be realized by simple materials and fabrication methods: it is silicon-based materials and fully compatible with the conventional CMOS process. An individual memory cell is a silicon diode vertically integrated. Historically, OTP memories were widely used for read-only-memory (ROM) in the central processing unit (CPU) of the computer systems. By implanting the nanoscale fabrication technology into the concept of OTP memory, innovative high-density NVM appliances for massive storage media becomes very promising. The program operation is performed by breaking down the thin oxide layer between pn doped structure and wordline (WL) and its state can be sensed by the leakage current through the broken oxide. Since this invention is based on neither transistor structure nor charge-based mechanism, it is highly reliable and functional for the ultra-large scale integration. The feasibility of its stacked array will be also checked.

  10. Customizable 3D Printed 'Plug and Play' Millifluidic Devices for Programmable Fluidics.

    PubMed

    Tsuda, Soichiro; Jaffery, Hussain; Doran, David; Hezwani, Mohammad; Robbins, Phillip J; Yoshida, Mari; Cronin, Leroy

    2015-01-01

    Three dimensional (3D) printing is actively sought after in recent years as a promising novel technology to construct complex objects, which scope spans from nano- to over millimeter scale. Previously we utilized Fused deposition modeling (FDM)-based 3D printer to construct complex 3D chemical fluidic systems, and here we demonstrate the construction of 3D milli-fluidic structures for programmable liquid handling and control of biological samples. Basic fluidic operation devices, such as water-in-oil (W/O) droplet generators for producing compartmentalized mono-disperse droplets, sensor-integrated chamber for online monitoring of cellular growth, are presented. In addition, chemical surface treatment techniques are used to construct valve-based flow selector for liquid flow control and inter-connectable modular devices for networking fluidic parts. As such this work paves the way for complex operations, such as mixing, flow control, and monitoring of reaction / cell culture progress can be carried out by constructing both passive and active components in 3D printed structures, which designs can be shared online so that anyone with 3D printers can reproduce them by themselves.

  11. A Survey of Memristive Threshold Logic Circuits.

    PubMed

    Maan, Akshay Kumar; Jayadevi, Deepthi Anirudhan; James, Alex Pappachen

    2017-08-01

    In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore's law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO2, ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.

  12. An inpatient lifestyle-change programme improves heart rate recovery in overweight and obese children and adolescents (LOGIC Trial).

    PubMed

    Wilks, Désirée C; Rank, Melanie; Christle, Jeff; Langhof, Helmut; Siegrist, Monika; Halle, Martin

    2014-07-01

    Impaired heart rate recovery (HRR) is a strong predictor of overall mortality and cardio-metabolic risk. This study aimed at investigating (1) the effect of participation in a lifestyle-change programme for weight loss on HRR in overweight and obese children and (2) potential associations between the changes in one minute HRR (HRR1) and fitness, weight loss and cardio-metabolic risk. The analysis included 429 individuals (169 boys) aged 13.9 ± 2.3 years who participated in an inpatient weight loss programme for four to six weeks. At baseline and the end of the programme clinical investigations were performed, including blood analyses, blood pressure, anthropometry and maximal cycle ergometer exercise testing with continuous heart rate (HR) monitoring. HRR was calculated as the difference between the highest exercising HR and HR at one, three and five minutes post-exercise. Average body weight decreased from 90.7 ± 22.5 kg to 81.9 ± 20.0 kg and peak exercise capacity increased from 1.66 ± 0.38 W/kg to 2.05 ± 0.45 W/kg (p < 0.001). Cardio-metabolic risk factors improved (waist circumference, LDL-cholesterol, HOMA insulin ratio, blood pressure; p < 0.05). HDL-cholesterol and triglyceride levels remained unchanged. Compared with baseline, at follow-up the decline in HR was more pronounced (+32%, +18% and +11% for HRR1, HRR3 and HRR5; p < 0.001). Improvements in HRR1 were weakly correlated with changes in exercise capacity (p < 0.05; r < 0.13), but not with changes in body weight and cardio-metabolic risk factors. HRR considerably improved after an inpatient weight loss programme in overweight and obese children. This was not associated with improvements in body weight and cardio-metabolic risk; hence HRR would be a valuable addition to cardiovascular risk assessment in this group. © The European Society of Cardiology 2012.

  13. Ballistic Spin Hall Transistor Using a Heterostructure Channel and Its Application to Logic Devices

    NASA Astrophysics Data System (ADS)

    Choi, Won Young; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Koo, Hyun Cheol

    2017-07-01

    In a ballistic spin transport channel, spin Hall and Rashba effects are utilized to provide a gate-controlled spin Hall transistor. A ferromagnetic electrode and a spin Hall probe are employed for spin injection and detection, respectively, in a two-dimensional Rashba system. We utilize the spin current of which polarization direction is controlled by the gate electric field which determines the strength of the Rashba effective field. By observing the spin Hall voltage, spin injection and coherent spin precession are electrically monitored. From the original Datta-Das technique, we measure the channel conductance oscillation as the gate voltage is varied. When the magnetization orientation of the injector is reversed by 180°, the phase of the Datta-Das oscillation shifts by 180° as expected. Depending on the magnetization direction, the spin Hall transistor behaves as an n- or p-type transistor. Thus, we can implement the complementary transistors which are analogous to the conventional complementary metal oxide semiconductor transistors. Using the experimental data extracted from the spin Hall transistor, the logic operation is also presented.

  14. An optical sectioning programmable array microscope implemented with a digital micromirror device.

    PubMed

    Hanley, Q S; Verveer, P J; Gemkow, M J; Arndt-Jovin, D; Jovin, T M

    1999-12-01

    The defining feature of a programmable array microscope (PAM) is the presence of a spatial light modulator in the image plane. A spatial light modulator used singly or as a matched pair for both illumination and detection can be used to generate an optical section. Under most conditions, the basic optical properties of an optically sectioning PAM are similar to those of rotating Nipkow discs. The method of pattern generation, however, is fundamentally different and allows arbitrary illumination patterns to be generated under programmable control, and sectioning strategies to be changed rapidly in response to specific experimental conditions. We report the features of a PAM incorporating a digital micromirror device, including the axial sectioning response to fluorescent thin films and the imaging of biological specimens. Three axial sectioning strategies were compared: line scans, dot lattice scans and pseudo-random sequence scans. The three strategies varied widely in light throughput, sectioning strength and robustness when used on real biological samples. The axial response to thin fluorescent films demonstrated a consistent decrease in the full width at half maximum (FWHM), accompanied by an increase in offset, as the unit cells defining the patterns grew smaller. Experimental axial response curves represent the sum of the response from a given point of illumination and cross-talk from neighbouring points. Cross-talk is minimized in the plane of best focus and when measured together with the single point response produces a decrease in FWHM. In patterns having constant throughput, there appears to be tradeoff between the FWHM and the size of the offset. The PAM was compared to a confocal laser scanning microscope using biological samples. The PAM demonstrated higher signal levels and dynamic range despite a shorter acquisition time. It also revealed more structures in x-z sections and less intensity drop-off with scanning depth.

  15. Nonvolatile, electrically erasable programmable ROM

    NASA Astrophysics Data System (ADS)

    El-Dessouky, A.

    1984-01-01

    The processing technology for integration of MNOS-EEPROMs and NMOS Logic was investigated as p-well isolation. Memory characteristics of both Si gate and metal gate MNOS devices are investigated for nitride constitution which aims for lower programming voltages and good memory performance. The complete fabrication process for 128 byte SNOS-EEPROM chip is described by using high voltage depletion MOS devices in p-well technology. Another test vehicle uses 4 x 4 metal gate MNOS array to demonstrate possible fabrication of 12 V programmable scaled MNOS devices with 10 years retention after 10 to the 5th power endurance.

  16. Beam scanning binary logic

    NASA Astrophysics Data System (ADS)

    Itoh, Hideo; Mukai, Seiji; Watanabe, Masanobu; Mori, Masahiko; Yajima, Hiroyoshi

    1990-07-01

    A beam-scanning laser diode (BSLD) is presently applied to a novel optoelectronic logic operation, designated 'beam-scanning binary logic' (BSBL), that covers the implementation of both the basic logic gates and a spatial code encoder for photodetection, while allowing a greater reduction of the number of active devices than ordinary binary logic operations. BSBL executes multifunctional logic operations simultaneously. The data connections between logic gates in BSLD are flexible, due to the ability to electrically control both output power and laser-beam direction.

  17. Ferrite logic reliability study

    NASA Technical Reports Server (NTRS)

    Baer, J. A.; Clark, C. B.

    1973-01-01

    Development and use of digital circuits called all-magnetic logic are reported. In these circuits the magnetic elements and their windings comprise the active circuit devices in the logic portion of a system. The ferrite logic device belongs to the all-magnetic class of logic circuits. The FLO device is novel in that it makes use of a dual or bimaterial ferrite composition in one physical ceramic body. This bimaterial feature, coupled with its potential for relatively high speed operation, makes it attractive for high reliability applications. (Maximum speed of operation approximately 50 kHz.)

  18. Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

    NASA Astrophysics Data System (ADS)

    Ayyoub, Slimani; Achour, Benslama

    2017-08-01

    Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

  19. Integrated all-optical logic and arithmetic operations with the help of a TOAD-based interferometer device--alternative approach.

    PubMed

    Roy, Jitendra Nath; Gayen, Dilip Kumar

    2007-08-01

    Interferometric devices have drawn a great interest in all-optical signal processing for their high-speed photonic activity. The nonlinear optical loop mirror provides a major support to optical switching based all-optical logic and algebraic operations. The gate based on the terahertz optical asymmetric demultiplexer (TOAD) has added new momentum in this field. Optical tree architecture (OTA) plays a significant role in the optical interconnecting network. We have tried to exploit the advantages of both OTA- and TOAD-based switches. We have proposed a TOAD-based tree architecture, a new and alternative scheme, for integrated all-optical logic and arithmetic operations.

  20. Integrated all-optical logic and arithmetic operations with the help of a TOAD-based interferometer device--alternative approach

    NASA Astrophysics Data System (ADS)

    Nath Roy, Jitendra; Gayen, Dilip Kumar

    2007-08-01

    Interferometric devices have drawn a great interest in all-optical signal processing for their high-speed photonic activity. The nonlinear optical loop mirror provides a major support to optical switching based all-optical logic and algebraic operations. The gate based on the terahertz optical asymmetric demultiplexer (TOAD) has added new momentum in this field. Optical tree architecture (OTA) plays a significant role in the optical interconnecting network. We have tried to exploit the advantages of both OTA- and TOAD-based switches. We have proposed a TOAD-based tree architecture, a new and alternative scheme, for integrated all-optical logic and arithmetic operations.

  1. Exploration of the affordances of mobile devices in integrating theory and clinical practice in an undergraduate nursing programme.

    PubMed

    Willemse, Juliana J; Bozalek, Vivienne

    2015-01-01

    Promoting the quality and effectiveness of nursing education is an important factor, given the increased demand for nursing professionals. It is important to establish learning environments that provide personalised guidance and feedback to students about their practical skills and application of their theoretical knowledge. To explore and describe the knowledge and points of view of students and educators about introduction of new technologies into an undergraduate nursing programme. The qualitative design used Tesch's (1990) steps of descriptive data analysis to complete thematic analysis of the data collected in focus group discussions (FGDs) and individual interviews to identify themes. Themes identified from the students’ FGDs and individual interviews included: mobile devices as a communication tool; email, WhatsApp and Facebook as methods of communication; WhatsApp as a method of communication; nurses as role-models in the clinical setting; setting personal boundaries; and impact of mobile devices in clinical practice on professionalism. Themes identified from the FGD, individual interviews and a discussion session held with educators included: peer learning via mobile devices; email, WhatsApp and Facebook as methods of communication; the mobile device as a positive learning method; students need practical guidance; and ethical concerns in clinical facilities about Internet access and use of mobile devices. The research project established an understanding of the knowledge and points of view of students and educators regarding introduction of new technologies into an undergraduate nursing programme with the aim of enhancing integration of theory and clinical practice through use of mobile devices.

  2. Exploration of the affordances of mobile devices in integrating theory and clinical practice in an undergraduate nursing programme.

    PubMed

    Willemse, Juliana J; Bozalek, Vivienne

    2015-09-28

    Promoting the quality and effectiveness of nursing education is an important factor, given the increased demand for nursing professionals. It is important to establish learning environments that provide personalised guidance and feedback to students about their practical skills and application of their theoretical knowledge. To explore and describe the knowledge and points of view of students and educators about introduction of new technologies into an undergraduate nursing programme. The qualitative design used Tesch's (1990) steps of descriptive data analysis to complete thematic analysis of the data collected in focus group discussions (FGDs) andindividual interviews to identify themes. Themes identified from the students' FGDs and individual interviews included:mobile devices as a communication tool; email, WhatsApp and Facebook as methods of communication; WhatsApp as a method of communication; nurses as role-models in the clinical setting; setting personal boundaries; and impact of mobile devices in clinical practiceon professionalism. Themes identified from the FGD, individual interviews and a discussion session held with educators included: peer learning via mobile devices; email, WhatsApp and Facebook as methods of communication; the mobile device as a positive learning method; students need practical guidance; and ethical concerns in clinical facilities about Internet access and use of mobile devices. The research project established an understanding of the knowledge and points of view of students and educators regarding introduction of new technologies into an undergraduate nursing programme with the aim of enhancing integration of theory and clinical practice through use of mobile devices.

  3. A water pumping control system with a programmable logic controller (PLC) and industrial wireless modules for industrial plants--an experimental setup.

    PubMed

    Bayindir, Ramazan; Cetinceviz, Yucel

    2011-04-01

    This paper describes a water pumping control system that is designed for production plants and implemented in an experimental setup in a laboratory. These plants contain harsh environments in which chemicals, vibrations or moving parts exist that could potentially damage the cabling or wires that are part of the control system. Furthermore, the data has to be transferred over paths that are accessible to the public. The control systems that it uses are a programmable logic controller (PLC) and industrial wireless local area network (IWLAN) technologies. It is implemented by a PLC, an communication processor (CP), two IWLAN modules, and a distributed input/output (I/O) module, as well as the water pump and sensors. Our system communication is based on an Industrial Ethernet and uses the standard Transport Control Protocol/Internet Protocol for parameterisation, configuration and diagnostics. The main function of the PLC is to send a digital signal to the water pump to turn it on or off, based on the tank level, using a pressure transmitter and inputs from limit switches that indicate the level of the water in the tank. This paper aims to provide a convenient solution in process plants where cabling is not possible. It also has lower installation and maintenance cost, provides reliable operation, and robust and flexible construction, suitable for industrial applications.

  4. Programmable Pulser

    NASA Technical Reports Server (NTRS)

    Baumann, Eric; Merolla, Anthony

    1988-01-01

    User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

  5. Architecture and data processing alternatives for the TSE computer. Volume 3: Execution of a parallel counting algorithm using array logic (Tse) devices

    NASA Technical Reports Server (NTRS)

    Metcalfe, A. G.; Bodenheimer, R. E.

    1976-01-01

    A parallel algorithm for counting the number of logic-l elements in a binary array or image developed during preliminary investigation of the Tse concept is described. The counting algorithm is implemented using a basic combinational structure. Modifications which improve the efficiency of the basic structure are also presented. A programmable Tse computer structure is proposed, along with a hardware control unit, Tse instruction set, and software program for execution of the counting algorithm. Finally, a comparison is made between the different structures in terms of their more important characteristics.

  6. System and method for programmable bank selection for banked memory subsystems

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  7. Label-free and enzyme-free platform for the construction of advanced DNA logic devices based on the assembly of graphene oxide and DNA-templated AgNCs.

    PubMed

    Fan, Daoqing; Zhu, Jinbo; Liu, Yaqing; Wang, Erkang; Dong, Shaojun

    2016-02-14

    DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator.

  8. Poly-4-vinylphenol (PVP) and Poly(melamine-co-formaldehyde) (PMF)-Based Atomic Switching Device and Its Application to Logic Gate Circuits with Low Operating Voltage.

    PubMed

    Kang, Dong-Ho; Choi, Woo-Young; Woo, Hyunsuk; Jang, Sungkyu; Park, Hyung-Youl; Shim, Jaewoo; Choi, Jae-Woong; Kim, Sungho; Jeon, Sanghun; Lee, Sungjoo; Park, Jin-Hong

    2017-08-16

    In this study, we demonstrate a high-performance solid polymer electrolyte (SPE) atomic switching device with low SET/RESET voltages (0.25 and -0.5 V, respectively), high on/off-current ratio (10(5)), excellent cyclic endurance (>10(3)), and long retention time (>10(4) s), where poly-4-vinylphenol (PVP)/poly(melamine-co-formaldehyde) (PMF) is used as an SPE layer. To accomplish these excellent device performance parameters, we reduce the off-current level of the PVP/PMF atomic switching device by improving the electrical insulating property of the PVP/PMF electrolyte through adjustment of the number of cross-linked chains. We then apply a titanium buffer layer to the PVP/PMF switching device for further improvement of bipolar switching behavior and device stability. In addition, we first implement SPE atomic switch-based logic AND and OR circuits with low operating voltages below 2 V by integrating 5 × 5 arrays of PVP/PMF switching devices on the flexible substrate. In particular, this low operating voltage of our logic circuits was much lower than that (>5 V) of the circuits configured by polymer resistive random access memory. This research successfully presents the feasibility of PVP/PMF atomic switches for flexible integrated circuits for next-generation electronic applications.

  9. Label-free and enzyme-free platform for the construction of advanced DNA logic devices based on the assembly of graphene oxide and DNA-templated AgNCs

    NASA Astrophysics Data System (ADS)

    Fan, Daoqing; Zhu, Jinbo; Liu, Yaqing; Wang, Erkang; Dong, Shaojun

    2016-02-01

    DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator.DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator. Electronic supplementary information (ESI) available: Optimization experiments, Table S1, Fig. S1-S5 in ESI. See DOI: 10.1039/c6nr00032k

  10. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process

    PubMed Central

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-01-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency −70 cd A−1 under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices. PMID:27187936

  11. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process.

    PubMed

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-05-17

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency -70 cd A(-1) under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices.

  12. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process

    NASA Astrophysics Data System (ADS)

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-05-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency -70 cd A-1 under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices.

  13. Partial spin absorption induced magnetization switching and its voltage-assisted improvement in an asymmetrical all spin logic device at the mesoscopic scale

    NASA Astrophysics Data System (ADS)

    Zhang, Yue; Zhang, Zhizhong; Wang, Lezhi; Nan, Jiang; Zheng, Zhenyi; Li, Xiang; Wong, Kin; Wang, Yu; Klein, Jacques-Olivier; Khalili Amiri, Pedram; Zhang, Youguang; Wang, Kang L.; Zhao, Weisheng

    2017-07-01

    Beyond memory and storage, future logic applications put forward higher requirements for electronic devices. All spin logic devices (ASLDs) have drawn exceptional interest as they utilize pure spin current instead of charge current, which could promise ultra-low power consumption. However, relatively low efficiencies of spin injection, transport, and detection actually impede high-speed magnetization switching and challenge perspectives of ASLD. In this work, we study partial spin absorption induced magnetization switching in asymmetrical ASLD at the mesoscopic scale, in which the injector and detector have the nano-fabrication compatible device size (>100 nm) and their contact areas are different. The enlarged contact area of the detector is conducive to the spin current absorption, and the contact resistance difference between the injector and the detector can decrease the spin current backflow. Rigorous spin circuit modeling and micromagnetic simulations have been carried out to analyze the electrical and magnetic features. The results show that, at the fabrication-oriented technology scale, the ferromagnetic layer can hardly be switched by geometrically partial spin current absorption. The voltage-controlled magnetic anisotropy (VCMA) effect has been applied on the detector to accelerate the magnetization switching by modulating magnetic anisotropy of the ferromagnetic layer. With a relatively high VCMA coefficient measured experimentally, a voltage of 1.68 V can assist the whole magnetization switching within 2.8 ns. This analysis and improving approach will be of significance for future low-power, high-speed logic applications.

  14. Digital Holographic Logic

    NASA Technical Reports Server (NTRS)

    Preston, K., Jr.

    1972-01-01

    The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.

  15. Designing and simulation smart multifunctional continuous logic device as a basic cell of advanced high-performance sensor systems with MIMO-structure

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolskyy, Aleksandr I.; Lazarev, Alexander A.

    2015-01-01

    We have proposed a design and simulation of hardware realizations of smart multifunctional continuous logic devices (SMCLD) as advanced basic cells of the sensor systems with MIMO- structure for images processing and interconnection. The SMCLD realize function of two-valued, multi-valued and continuous logics with current inputs and current outputs. Such advanced basic cells realize function nonlinear time-pulse transformation, analog-to-digital converters and neural logic. We showed advantages of such elements. It's have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The conception of construction of SMCLD consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 50÷70 transistors, 1 PD and 1 LED makes the offered circuits quite compact. The simulation results of NOT, MIN, MAX, equivalence (EQ), normalize summation, averaging and other functions, that implemented SMCLD, showed that the level of logical variables can change from 0.1μA to 10μA for low-power consumption variants. The SMCLD have low power consumption <1mW and processing time about 1÷11μS at supply voltage 2.4÷3.3V.

  16. Logic Programming in LISP.

    DTIC Science & Technology

    1981-01-01

    79/7, Imperial College, University of London. [Colmerauer 1973] Colmerauer, A., Un Systeme de Communication Homme - machine Kanoui, H., en Francais...any of the LOGIC interface functions (,-, THE, ALL, ANY, etc.) can be obtained by invoking the command (DOC fn), where "fn" is the name of the function...well as for output) illustrates one more way in which the LOGLISP programmer can fruitfully exploit the interface between LOGIC and LISP. GIVE is just a

  17. Distributed Logics

    DTIC Science & Technology

    2014-10-03

    introduce distributed logics. Distributed logics lift the distribution structure of a distributed system directly into the logic, thereby parameterizing...the logic by the distribution structure itself. Each domain supports a “local modal logic.” The connections between domains are realized as...There are also multi- agent logic systems [12]. What distinguishes distributed logics from these are that the morphisms, i.e., the nbd maps, have

  18. Field programmable gate arrays: Evaluation report for space-flight application

    NASA Technical Reports Server (NTRS)

    Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

    1992-01-01

    Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

  19. An iLab for Teaching Advanced Logic Concepts with Hardware Descriptive Languages

    ERIC Educational Resources Information Center

    Ayodele, Kayode P.; Inyang, Isaac A.; Kehinde, Lawrence O.

    2015-01-01

    One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on…

  20. Integrated Optical Combinatorial Logic Using Electro-Optic Bragg Gratings

    NASA Astrophysics Data System (ADS)

    Arrathoon, R.; Schroeder, E. R.; Westervelt, F.

    1985-09-01

    Three classes of integrated optical devices suitable for implementing general combinatorial logic are discussed. The categories considered are electric-electric-optic (EEO), electric-optic-optic (E00), and optic-optic-optic (000). Existing gate geometries based on electro-optic Bragg gratings are modified to permit the realization of the NOT, NAND, OR, NOR, and inhibition functions. A full-adder based entirely on electro-optic Bragg gratings is developed, and the device is compared to current VLSI technology in terms of size and speed. The use of programmable logic arrays (PLA's)for implementing general combinatorial logic is discussed. The paper concludes with a proposal for using electro-optic Bragg gratings to construct an integrated optical PLA.

  1. Demonstration of a directed XNOR/XOR optical logic circuit based on silicon Mach-Zehnder interferometer

    NASA Astrophysics Data System (ADS)

    Ding, Jianfeng; Yang, Lin; Chen, Qiaoshan; Zhang, Lei; Zhou, Ping

    2017-07-01

    We demonstrate a directed XNOR/XOR optical logic circuit based on silicon Mach-Zehnder interferometer. The device with the symmetric arm design is wavelength-insensitive in a wavelength range of 40 nm. The device has an electro-optical bandwidth of around 20 GHz. When the device is optically biased at the maximum or minimum transmission points by tuning the heater on one of its arms, it can perform the XNOR or XOR operations respectively at a speed up to 20 Gbps. The high-speed and reconfigurable abilities of the device make it suitable for the future programmable optical logic array.

  2. Digital micromirror device as programmable rough particle in interferometric particle imaging.

    PubMed

    Fromager, M; Aït Ameur, K; Brunel, M

    2017-04-20

    The 2D autocorrelation of the projection of an irregular rough particle can be estimated using the analysis of its interferometric out-of-focus image. We report the development of an experimental setup that creates speckle-like patterns generated by "programmable" rough particles of desired-shape. It should become an important tool for the development of new setups, configurations, and algorithms in interferometric particle imaging.

  3. Excitonic AND Logic Gates on DNA Brick Nanobreadboards

    PubMed Central

    2015-01-01

    A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

  4. Excitonic AND Logic Gates on DNA Brick Nanobreadboards.

    PubMed

    Cannon, Brittany L; Kellis, Donald L; Davis, Paul H; Lee, Jeunghoon; Kuang, Wan; Hughes, William L; Graugnard, Elton; Yurke, Bernard; Knowlton, William B

    2015-03-18

    A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems.

  5. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    PubMed Central

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-01-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

  6. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    NASA Astrophysics Data System (ADS)

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-02-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated.

  7. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure.

    PubMed

    Murapaka, C; Sethi, P; Goolaup, S; Lew, W S

    2016-02-03

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated.

  8. A programmable and configurable multi-port System-on-Chip for stimulating electrokinetically-driven microfluidic devices.

    PubMed

    Lopez, Martha Salome; Gerstlauer, Andreas; Avila, Alfonso; Martinez-Chapa, Sergio O

    2011-01-01

    Recent research has demonstrated the use of microfluidic devices and electro-kinetics in areas such as medicine, genetics, embryology, epidemiology and pollution analysis, where manipulation of particles suspended in liquid media is required. Micro-fabrication technology has made it possible to increase system complexity and functionality by allowing integration of different processing and analysis stages in a single chip. However, fully integrated and autonomous microfluidic systems supporting ad-hoc stimulation have yet to be developed. This paper presents a flexible, configurable and programmable stimulator for electro-kinetically driven microfluidic devices. The stimulator is a dedicated System-on-Chip (SoC) architecture that generates sine, triangle, and sawtooth signals within a frequency range of 1 Hz to 20 MHz, capable of delivering single, dual, and superimposed waveforms, in a user defined test sequence for a selected time period. The system is designed to be integrated into complete, autonomous Lab-on-Chip, portable or implantable devices. As such, it is expected to help significantly advance current and future research on particle manipulation.

  9. flexTMS--a novel repetitive transcranial magnetic stimulation device with freely programmable stimulus currents.

    PubMed

    Gattinger, Norbert; Moessnang, Georg; Gleich, Bernhard

    2012-07-01

    Transcranial magnetic stimulation (TMS) is able to noninvasively excite neuronal populations due to brief magnetic field pulses. The efficiency and the characteristics of stimulation pulse shapes influence the physiological effect of TMS. However, commercial devices allow only a minimum of control of different pulse shapes. Basically, just sinusoidal and monophasic pulse shapes with fixed pulse widths are available. Only few research groups work on TMS devices with controllable pulse parameters such as pulse shape or pulse width. We describe a novel TMS device with a full-bridge circuit topology incorporating four insulated-gate bipolar transistor (IGBT) modules and one energy storage capacitor to generate arbitrary waveforms. This flexible TMS (flexTMS ) device can generate magnetic pulses which can be adjusted with respect to pulse width, polarity, and intensity. Furthermore, the equipment allows us to set paired pulses with a variable interstimulus interval (ISI) from 0 to 20 ms with a step size of 10  μs. All user-defined pulses can be applied continually with repetition rates up to 30 pulses per second (pps) or, respectively, up to 100 pps in theta burst mode. Offering this variety of flexibility, flexTMS will allow the enhancement of existing TMS paradigms and novel research applications.

  10. Development of bioMEMS device and package for a spatially programmable biomolecule assembly

    NASA Astrophysics Data System (ADS)

    Park, Jung Jin

    We report facile in situ biomolecule assembly at readily addressable sites in microfluidic channels after complete fabrication and packaging of the microfluidic device. Aminopolysaccharide chitosan's pH responsive and chemically reactive properties allow electric signal-guided biomolecule assembly onto conductive inorganic surfaces from the aqueous environment, preserving the activity of the biomolecules. Photoimageable SU8 is used on a Pyrex bottom substrate to create microfluidic channels and a PDMS layer is sealed to the SU8 microchannel by compression of their respective substrates between additional top and bottom Plexiglas plates at the package level. Transparent and non-permanently packaged device allows consistently leak-free sealing, simple in situ and ex situ examination of the assembly procedures, fluidic input/outputs for transport of aqueous solutions, and electrical ports to guide the assembly onto the patterned gold electrode sites within the channel. Facile post-fabrication in-situ biomolecule assembly of internal electrodes is demonstrated using electrodeposition of a chitosan film on a patterned gold electrode. Both in situ fluorescence and ex situ profilometer results confirm chitosan-mediated in situ biomolecule assembly, demonstrating a simple approach to direct the assembly of biological components into a completely fabricated device. We believe that this strategy holds significant potential as a simple and generic biomolecule assembly approach for future applications in complex biomolecular or biosensing analyses as well as in sophisticated microfluidic networks as anticipated for future lab-on-a chip.

  11. Amplifying genetic logic gates.

    PubMed

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  12. Smart time-pulse coding photoconverters as basic components 2D-array logic devices for advanced neural networks and optical computers

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Michalnichenko, Nikolay N.

    2004-04-01

    The article deals with a conception of building arithmetic-logic devices (ALD) with a 2D-structure and optical 2D-array inputs-outputs as advanced high-productivity parallel basic operational training modules for realization of basic operation of continuous, neuro-fuzzy, multilevel, threshold and others logics and vector-matrix, vector-tensor procedures in neural networks, that consists in use of time-pulse coding (TPC) architecture and 2D-array smart optoelectronic pulse-width (or pulse-phase) modulators (PWM or PPM) for transformation of input pictures. The input grayscale image is transformed into a group of corresponding short optical pulses or time positions of optical two-level signal swing. We consider optoelectronic implementations of universal (quasi-universal) picture element of two-valued ALD, multi-valued ALD, analog-to-digital converters, multilevel threshold discriminators and we show that 2D-array time-pulse photoconverters are the base elements for these devices. We show simulation results of the time-pulse photoconverters as base components. Considered devices have technical parameters: input optical signals power is 200nW_200μW (if photodiode responsivity is 0.5A/W), conversion time is from tens of microseconds to a millisecond, supply voltage is 1.5_15V, consumption power is from tens of microwatts to a milliwatt, conversion nonlinearity is less than 1%. One cell consists of 2-3 photodiodes and about ten CMOS transistors. This simplicity of the cells allows to carry out their integration in arrays of 32x32, 64x64 elements and more.

  13. Origami-inspired active graphene-based paper for programmable instant self-folding walking devices

    PubMed Central

    Mu, Jiuke; Hou, Chengyi; Wang, Hongzhi; Li, Yaogang; Zhang, Qinghong; Zhu, Meifang

    2015-01-01

    Origami-inspired active graphene-based paper with programmed gradients in vertical and lateral directions is developed to address many of the limitations of polymer active materials including slow response and violent operation methods. Specifically, we used function-designed graphene oxide as nanoscale building blocks to fabricate an all-graphene self-folding paper that has a single-component gradient structure. A functional device composed of this graphene paper can (i) adopt predesigned shapes, (ii) walk, and (iii) turn a corner. These processes can be remote-controlled by gentle light or heating. We believe that this self-folding material holds potential for a wide range of applications such as sensing, artificial muscles, and robotics. PMID:26601135

  14. Remote microwave monitoring of magnetization switching in CoFeB/Ta/CoFeB spin logic device

    NASA Astrophysics Data System (ADS)

    Morgunov, R.; L'vova, G.; Talantsev, A.; Koplak, O.; Petit-Watelot, S.; Devaux, X.; Migot, S.; Lu, Y.; Mangin, S.

    2017-05-01

    Stable magnetic states of the MgO/CoFeB/Ta/CoFeB/MgO/Ta spin valve as well as transitions between the states were detected by microwave magnetoresistance (MMR) measured in the cavity of an electron spin resonance spectrometer. Advantages of this experimental technique are the possibility to study the orientation dependence of the MMR, the absence of the additional contact/sample interfaces, the wireless control of the spin valves, and the compatibility of the MMR measurements with ferromagnetic resonance experiments. The magnetic field dependence of the first derivation of the microwave absorption allows one to judge about the negative magnetoresistance of the layers and positive interlayer giant magnetoresistance. The obtained experimental results could be used for engineering of the microwave high sensitive sensors available for remote identification of the stable magnetic and logic states of the spin valves needful in medical spintronics to detect biological objects labeled with nanoparticles.

  15. Radiation tolerant combinational logic cell

    NASA Technical Reports Server (NTRS)

    Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

    2009-01-01

    A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

  16. Study of design-based e-beam defect inspection for hotspot detection and process window characterization on 10nm logic device

    NASA Astrophysics Data System (ADS)

    Leray, Philippe; Halder, Sandip; Di Lorenzo, Paolo; Wang, Fei; Zhang, Pengcheng; Fang, Wei; Liu, Kevin; Jau, Jack

    2016-03-01

    With the continuous shrink of design rules from 14nm to 10nm to 7nm, conserving process windows in a high volume manufacturing environment is becoming more and more difficult. Masks, scanners, and etch processes have to meet very tight specifications in order to keep defect, CD, as well as overlay within the margins of the process window. In this work, we study a design-based e-beam defect inspection technology for wafer level process window characterization and intra-field defect variability on 10nm logic devices. Due to high resolution, e-beam technology is the natural choice for review and/or detection of subtle pattern deviations, aka defects. The capability of integrating design information (GDS file) with defect detection, dimension measurement of critical structure, and defect classification provides added values for engineers to identify yield limiting systematic defects and to provide feedback to design.

  17. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion.

    PubMed

    Lam, Brian; Zhou, Wendi; Kelley, Shana O; Sargent, Edward H

    2015-04-27

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1-3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top-down template definition with bottom-up three-dimensional nanoscale features.

  18. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion

    NASA Astrophysics Data System (ADS)

    Lam, Brian; Zhou, Wendi; Kelley, Shana O.; Sargent, Edward H.

    2015-04-01

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1-3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top-down template definition with bottom-up three-dimensional nanoscale features.

  19. Solid-state non-volatile electronically programmable reversible variable resistance device

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni (Inventor); Thakoor, Sarita (Inventor); Daud, Taher (Inventor); Thakoor, Aniklumar P. (Inventor)

    1989-01-01

    A solid-state variable resistance device (10) whose resistance can be repeatedly altered by a control signal over a wide range, and which will remain stable after the signal is removed, is formed on an insulated layer (14), supported on a substrate (12) and comprises a set of electrodes (16a, 16b) connected by a layer (18) of material, which changes from an insulator to a conductor upon the injection of ions, covered by a layer (22) of material with insulating properties which permit the passage of ions, overlaid by an ion donor material (20). The ion donor material is overlaid by an insulating layer (24) upon which is deposited a control gate (26) located above the contacts. In a preferred embodiment, the variable resistance material comprises WO.sub.3, the ion donor layer comprises Cr.sub.2 O.sub.3, and the layers sandwiching the ion donor layer comprise silicon monoxide. When a voltage is applied to the gate, the resistance between the electrode contacts changes, decreasing with positive voltage and increasing with negative voltage.

  20. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion

    PubMed Central

    Lam, Brian; Zhou, Wendi; Kelley, Shana O.; Sargent, Edward H.

    2015-01-01

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1–3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top–down template definition with bottom–up three-dimensional nanoscale features. PMID:25914024

  1. Interference of GSM mobile phones with communication between Cardiac Rhythm Management devices and programmers: A combined in vivo and in vitro study.

    PubMed

    Huang, Dong; Dong, Zhi-Feng; Chen, Yan; Wang, Fa-Bin; Wei, Zhi; Zhao, Wen-Bin; Li, Shuai; Liu, Ming-Ya; Zhu, Wei; Wei, Meng; Li, Jing-Bo

    2015-07-01

    To investigate interference, and how to avoid it, by high-frequency electromagnetic fields (EMFs) of Global System for Mobile Communications (GSM) mobile phone with communication between cardiac rhythm management devices (CRMs) and programmers, a combined in vivo and in vitro testing was conducted. During in vivo testing, GSM mobile phones interfered with CRM-programmer communication in 33 of 65 subjects tested (50.8%). Losing ventricle sensing was representative in this study. In terms of clinical symptoms, only 4 subjects (0.6%) felt dizzy during testing. CRM-programmer communication recovered upon termination of mobile phone communication. During in vitro testing, electromagnetic interference by high-frequency (700-950 MHz) EMFs reproducibly occurred in duplicate testing in 18 of 20 CRMs (90%). During each interference, the pacing pulse signal on the programmer would suddenly disappear while the synchronous signal was normal on the amplifier-oscilloscope. Simulation analysis showed that interference by radiofrequency emitting devices with CRM-programmer communication may be attributed to factors including materials, excitation source distance, and implant depth. Results suggested that patients implanted with CRMs should not be restricted from using GSM mobile phones; however, CRMs should be kept away from high-frequency EMFs of GSM mobile phone during programming. © 2015 Wiley Periodicals, Inc.

  2. G(sup 4)FET Implementations of Some Logic Circuits

    NASA Technical Reports Server (NTRS)

    Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

    2009-01-01

    Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

  3. Microfluidic bubble logic.

    PubMed

    Prakash, Manu; Gershenfeld, Neil

    2007-02-09

    We demonstrate universal computation in an all-fluidic two-phase microfluidic system. Nonlinearity is introduced into an otherwise linear, reversible, low-Reynolds number flow via bubble-to-bubble hydrodynamic interactions. A bubble traveling in a channel represents a bit, providing us with the capability to simultaneously transport materials and perform logical control operations. We demonstrate bubble logic AND/OR/NOT gates, a toggle flip-flop, a ripple counter, timing restoration, a ring oscillator, and an electro-bubble modulator. These show the nonlinearity, gain, bistability, synchronization, cascadability, feedback, and programmability required for scalable universal computation. With increasing complexity in large-scale microfluidic processors, bubble logic provides an on-chip process control mechanism integrating chemistry and computation.

  4. Electromechanical Devices and Controllers. Electronics Module 10. Instructor's Guide.

    ERIC Educational Resources Information Center

    Carter, Ed

    This module is the tenth of 10 modules in the competency-based electronics series. Introductory materials include a listing of competencies addressed in the module, a parts/equipment list, and a cross-reference table of instructional materials. Six instructional units cover: electromechanical control devices; programmable logic controllers (PLC);…

  5. Electromechanical Devices and Controllers. Electronics Module 10. Instructor's Guide.

    ERIC Educational Resources Information Center

    Carter, Ed

    This module is the tenth of 10 modules in the competency-based electronics series. Introductory materials include a listing of competencies addressed in the module, a parts/equipment list, and a cross-reference table of instructional materials. Six instructional units cover: electromechanical control devices; programmable logic controllers (PLC);…

  6. LSI/VLSI (Large Scale Integration/Very Large Scale Integration) ion implanted GaAs (Gallium Arsenide) IC processing. Appendix A: Feasibility analysis of Gallium-Arsenide mask programmable functions and logic arrays for high performance communications systems

    NASA Astrophysics Data System (ADS)

    Zucca, R. R.; Kirkpatrick, C. G.; Asbeck, P. M.; Eisen, F. H.; Lee, C. P.

    1984-01-01

    Circuits critical to the performance of advanced radio, radar and spread spectrum communications systems require advances in the state-of-the-art in semiconductor technology to meet the demands of advanced systems. As these systems increase in complexity, extensive digital circuitry is required in addition to the typical linear signal processing circuits. The power, size and weight of advanced systems also becomes unacceptable without continuous advances in semiconductor technology. Moreover an increasing trend is seen in the use of metal mask selectable functions, programmable logic arrays and gate arrays to implement system specific circuitry in an attempt to lower non-recurring costs, minimize risk and shorten development times. GaAs and other technologies with very high speed power-performance figures-of-merit are critical ingredients in systems implementations which satisfy these needs. To meet these advanced system requirements this project was initiated as a multi-phase/year program to develop a group of mask programmable gallium arsenide (GaAs) circuit elements applicable to high speed/performance communications systems.

  7. Dispositional logic

    NASA Technical Reports Server (NTRS)

    Le Balleur, J. C.

    1988-01-01

    The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.

  8. Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

    NASA Astrophysics Data System (ADS)

    Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

    2016-03-01

    Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

  9. Logic programming

    SciTech Connect

    Lusk, E.L.; Overbeek, R.A.

    1989-01-01

    This book contains the proceedings of the 1989 North American Conference on Logic Programming. Included are the following papers: Expanding query power in constrain logic programming languages, Investigating the linguistics of DNA with definite clause grammars, An intermediate language to support prolog's unification.

  10. Parallel optical logic operations on reversible networks

    NASA Astrophysics Data System (ADS)

    Shamir, Joseph

    2013-03-01

    A generic optical network architecture is proposed for the implementation of programmable logic operations. Based on reversible optical gate elements the processor is highly energy efficient and intrinsically fast. In this architecture the whole logic operation is executed by light propagating through the system with no energy dissipation. Energy must be spent only at the input interface and at discrete locations where the logic operation results are to be detected. As a consequence, the theoretical lower limit for energy dissipation in logic operations must be reconsidered. The strength of this approach is demonstrated by examples showing the implementation of various lossless logic operations, including Half Adder and Full Adder.

  11. Logic digital fluidic in miniaturized functional devices: Perspective to the next generation of microfluidic lab-on-chips.

    PubMed

    Zhang, Qiongdi; Zhang, Ming; Djeghlaf, Lyas; Bataille, Jeanne; Gamby, Jean; Haghiri-Gosnet, Anne-Marie; Pallandre, Antoine

    2017-04-01

    Microfluidics has emerged following the quest for scale reduction inherent to micro- and nanotechnologies. By definition, microfluidics manipulates fluids in small channels with dimensions of tens to hundreds of micrometers. Recently, microfluidics has been greatly developed and its influence extends not only the domains of chemical synthesis, bioanalysis, and medical researches but also optics and information technology. In this review article, we will shortly discuss an enlightening analogy between electrons transport in electronics and fluids transport in microfluidic channels. This analogy helps to master transport and sorting. We will present some complex microfluidic devices showing that the analogy is going a long way off toward more complex components with impressive similarities between electronics and microfluidics. We will in particular explore the vast manifold of fluidic operations with passive and active fluidic components, respectively, as well as the associated mechanisms and corresponding applications. Finally, some relevant applications and an outlook will be cited and presented. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. Negative tone imaging (NTI) with KrF: extension of 248nm IIP lithography to under sub-20nm logic device

    NASA Astrophysics Data System (ADS)

    Oh, Tae-Hwan; Kim, Tae-Sun; Kim, Yura; Kim, Jahee; Heo, Sujeong; Youn, Bumjoon; Seo, Jaekyung; Yoon, Kwang-Sub; Choi, Byoung-il

    2013-03-01

    One of the most prospective alternative lithography ways prior to EUV implementation is the reverse imaging by means of a negative tone development (NTD) process with solvent-based developer. Contact and trench patterns can be printed in CAR (Chemically amplified resist) using a bright field mask through NTD development, and can give much better image contrast (NILS) than PTD process. Not only for contact or trench masks, but also pattering of IIP (Ion Implantation) layers whose mask opening ratio is less than 20% may get the benefit of NTD process, not only in the point of aerial imaging, but also in achievement of vertical resist profile, especially for post gate layers which have complex sub_topologies and nitride substrate. In this paper, we present applications for the NTD technique to IIP (Ion Implantation) layer lithography patterning, via KrF exposure, comparing the performance to that of the PTD process. Especially, to extend 248nm IIP litho to sub-20nm logic device, optimization of negative tone imaging (NTI) with KrF exposure is the main focus in this paper. With the special resin system designed for KrF NTD process, even sub 100nm half-pitch trench pattern can be defined with enough process margin and vertical resist profiles can be also obtained on the nitride substrate with KrF exposure.

  13. Nucleic acid based logical systems.

    PubMed

    Han, Da; Kang, Huaizhi; Zhang, Tao; Wu, Cuichen; Zhou, Cuisong; You, Mingxu; Chen, Zhuo; Zhang, Xiaobing; Tan, Weihong

    2014-05-12

    Researchers increasingly visualize a significant role for artificial biochemical logical systems in biological engineering, much like digital logic circuits in electrical engineering. Those logical systems could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expression in vivo. Nucleic acids (NA), as carriers of genetic information with well-regulated and predictable structures, are promising materials for the design and engineering of biochemical circuits. A number of logical devices based on nucleic acids (NA) have been designed to handle various processes for technological or biotechnological purposes. This article focuses on the most recent and important developments in NA-based logical devices and their evolution from in vitro, through cellular, even towards in vivo biological applications.

  14. Programmable Pacemaker

    NASA Technical Reports Server (NTRS)

    1980-01-01

    St. Jude Medical's Cardiac Rhythm Management Division, formerly known as Pacesetter Systems, Inc., incorporated Apollo technology into the development of the programmable pacemaker system. This consists of the implantable pacemaker together with a physician's console containing the programmer and a data printer. Physician can communicate with patient's pacemaker by means of wireless telemetry signals transmitted through the communicating head held over the patient's chest. Where earlier pacemakers deliver a fixed type of stimulus once implanted, Programalith enables surgery free "fine tuning" of device to best suit the patient's changing needs.

  15. Are the UK systems of innovation and evaluation of medical devices compatible? The role of NICE's Medical Technologies Evaluation Programme (MTEP).

    PubMed

    Chapman, A M; Taylor, C A; Girling, A J

    2014-08-01

    The economic evaluation of medical products and services is increasingly prioritised by healthcare decision makers and plays a key role in informing funding allocation decisions. It is well known that there are a number of methodological difficulties in the health technology assessment of medical devices, particularly in the provision of efficacy evidence. By contrasting devices with pharmaceuticals, the way in which the differing systems of innovation mould the UK's industry landscape is described and substantiated with market statistics. In recognition of the challenges faced by industry, as well as the growing need for cost-effective allocation of National Health Service (NHS) resources, the National Institute for Health and Care Excellence (NICE) led the development of the Medical Technologies Evaluation Programme (MTEP), which launched in 2009/2010. The review of the UK's medical devices market supports the programme's three principal aims: to simplify access to evaluation, speed up the process, and increase evaluative capacity for devices within NICE. However, an analysis of the output of MTEP's first 3 years suggests that it has some way to go to meet each of these aims.

  16. Deposition of TiO2/Al2O3 bilayer on hydrogenated diamond for electronic devices: Capacitors, field-effect transistors, and logic inverters

    NASA Astrophysics Data System (ADS)

    Liu, J. W.; Liao, M. Y.; Imura, M.; Banal, R. G.; Koide, Y.

    2017-06-01

    The wide bandgap semiconductor diamond has been studied to develop high-power and high-frequency electronic devices. Here, high dielectric constant (high-k) TiO2/Al2O3 bilayers are deposited on hydrogenated diamond (H-diamond) channel layers using sputter deposition (SD) and atomic layer deposition (ALD) techniques. Thin ALD-Al2O3 films are employed as buffer layers for the SD-TiO2 and ALD-TiO2 on H-diamond to suppress plasma discharge effect and to decrease leakage current density (J), respectively. The electrical properties of the resulting TiO2/Al2O3/H-diamond metal-oxide-semiconductor (MOS) capacitors, MOS field-effect transistors (MOSFETs), and MOSFET logic inverters are investigated. With the same thickness (4.0 nm) for ALD-Al2O3 buffer layer, the ALD-TiO2/ALD-Al2O3/H-diamond MOS capacitor shows a lower J and better capacitance-voltage characteristics than the SD-TiO2/ALD-Al2O3/H-diamond capacitor. The maximum capacitance of the ALD-TiO2/ALD-Al2O3/H-diamond capacitor and the k value of the ALD-TiO2/ALD-Al2O3 bilayer are 0.83 μF cm-2 and 27.2, respectively. Valence band offset between ALD-TiO2 and H-diamond is calculated to be 2.3 ± 0.2 eV based on the element binding energies measured using an X-ray photoelectron spectroscopy technique. Both the SD-TiO2/ALD-Al2O3/H-diamond and ALD-TiO2/ALD-Al2O3/H-diamond MOSFETs show p-type, pinch-off, and enhancement mode characteristics with on/off current ratios around 109. The subthreshold swings of them are 115 and as low as 79 mV dec-1, respectively. The ALD-TiO2/ALD-Al2O3/H-diamond MOSFET logic inverters, when coupled with load resistors, show distinct inversion characteristics with gains of 6.2-12.7.

  17. New Polysilicon-Oxide-Nitride-Oxide-Silicon Electrically Erasable Programmable Read-only Memory Device Approach for Eliminating Off-Cell Leakage Current

    NASA Astrophysics Data System (ADS)

    Lin, Jyh-Kuang; Chang, Chun-Yen; Huang, Heng-Sheng; Chen, Kun-Luh; Kuo, Dah-Chih

    1994-05-01

    A new polysilicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory (EEPROM) device, which eliminated off-cell leakage current, has been described and fabricated. The leakage current is easily encountered in metal-nitride-oxide-silicon (MNOS)-type EEPROMs. Two parasitic transistors, which are in parallel with the desired variable V t cell, are responsible for the leakage current. We demonstrated that the parasitic transistors are caused either by the nearly constant-threshold-voltage parasitic transistors surrounding the active region or by the “fringing effect” in poly-Si gate edges. The on-state and off-state I-V curves of the cell are shown and compared with those of two other different devices. The results reveal that the off-cell leakage current, which is observed in the other two devices, is completely eliminated in the proposed cell.

  18. Tribotronic Logic Circuits and Basic Operations.

    PubMed

    Zhang, Chi; Zhang, Li Min; Tang, Wei; Han, Chang Bao; Wang, Zhong Lin

    2015-06-17

    A tribotronic logic device is fabricated to convert external mechanical stimuli into logic level signals, and tribotronic logic circuits such as NOT, AND, OR, NAND, NOR, XOR, and XNOR gates are demonstrated for performing mechanical-electrical coupled tribotronic logic operations, which realize the direct interaction between the external environment and the current silicon integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. The universal magnetic tunnel junction logic gates representing 16 binary Boolean logic operations

    NASA Astrophysics Data System (ADS)

    Lee, Junwoo; Suh, Dong Ik; Park, Wanjun

    2015-05-01

    The novel devices are expected to shift the paradigm of a logic operation by their own nature, replacing the conventional devices. In this study, the nature of our fabricated magnetic tunnel junction (MTJ) that responds to the two external inputs, magnetic field and voltage bias, demonstrated seven basic logic operations. The seven operations were obtained by the electric-field-assisted switching characteristics, where the surface magnetoelectric effect occurs due to a sufficiently thin free layer. The MTJ was transformed as a universal logic gate combined with three supplementary circuits: A multiplexer (MUX), a Wheatstone bridge, and a comparator. With these circuits, the universal logic gates demonstrated 16 binary Boolean logic operations in one logic stage. A possible further approach is parallel computations through a complimentary of MUX and comparator, capable of driving multiple logic gates. A reconfigurable property can also be realized when different logic operations are produced from different level of voltages applying to the same configuration of the logic gate.

  20. Experience with an external quality assessment programme for point-of-care-testing (POCT) devices for the determination of blood glucose.

    PubMed

    Wood, William Graham; Hanke, Rainer; Meissner, Dieane; Reinauer, Hans

    2003-01-01

    This article describes the preparation and internal and external evaluation of materials, critical issues in the external quality assessment (EQA) of point-of-care testing (POCT) devices for measuring blood glucose. A comparison was made between different materials, both of natural and synthetic origin and with and without stabilisers. The aims were to produce a material which was compatible with as many POCT-devices as possible and so reduce the number of materials sent out in each campaign as well as to optimise the precision and comparability of results between methods and devices. Although the use of near natural material--sterile-filtered plasma spiked with glucose--survived internal testing, this material proved to be unsuitable for EQA surveys. The study resulted in the reduction of materials for each survey to stabilised whole blood for one device, stabilised plasma for two devices and a synthetic material based on a polyethylene glycol matrix for all other devices. Samples were sent as pairs six times annually. The POCT-devices tested measured precisely but inaccurately in the synthetic material, when compared with the reference method (gas-chromatography coupled with isotope-dilution mass-spectrometry; GC-IDMS), so that the devices could only be evaluated for precision. The construction of ratios between the concentrations measured on the two samples distributed allowed an indirect assessment of accuracy. The need for surveillance of POCT devices is stressed in this publication, which combines theory and practice in setting up and running an EQA programme for blood glucose.

  1. A label-free and enzyme-free system for operating various logic devices using poly(thymine)-templated CuNPs and SYBR Green I as signal transducers

    NASA Astrophysics Data System (ADS)

    Wu, Changtong; Zhou, Chunyang; Wang, Erkang; Dong, Shaojun

    2016-07-01

    For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations.For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr04069a

  2. Effects of gamma-ray irradiation on electronic and non-electronic equipment of Large Helical Device

    NASA Astrophysics Data System (ADS)

    K, Ogawa; T, Nishitani; M, Isobe; M, Sato; M, Yokota; H, Hayashi; T, Kobuchi; T, Nishimura

    2017-02-01

    In a deuterium operation on the Large Helical Device, the measurement and control equipment placed in the torus hall must survive under an environment of radiation. To study the effects of gamma-ray irradiation on the equipment, an irradiation experiment is performed at the Cobalt-60 irradiation facility of Nagoya University. Transient and permanent effects on a personal computer, media converters, programmable logic controllers, isolation amplifiers, a web camera, optical flow meters, and water sealing gaskets are experimentally surveyed. Transient noise appears on the web camera. Offset of the signal increases with an increase of the integrated dose on the programmable logic controller. The DeviceNet module on the programmable logic controller is broken at the integrated dose of 72 Gy, which is the expected range of the integrated dose of the torus hall. The other equipment can survive under the gamma-ray field in the torus hall.

  3. Effects of gamma-ray irradiation on electronic and non-electronic equipment of Large Helical Device

    NASA Astrophysics Data System (ADS)

    Ogawa, K.; Nishitani, T.; Isobe, M.; Sato, M.; Yokota, M.; Hayashi, H.; Kobuchi, T.; Nishimura, T.

    2017-02-01

    In a deuterium operation on the Large Helical Device, the measurement and control equipment placed in the torus hall must survive under an environment of radiation. To study the effects of gamma-ray irradiation on the equipment, an irradiation experiment is performed at the Cobalt-60 irradiation facility of Nagoya University. Transient and permanent effects on a personal computer, media converters, programmable logic controllers, isolation amplifiers, a web camera, optical flow meters, and water sealing gaskets are experimentally surveyed. Transient noise appears on the web camera. Offset of the signal increases with an increase of the integrated dose on the programmable logic controller. The DeviceNet module on the programmable logic controller is broken at the integrated dose of 72 Gy, which is the expected range of the integrated dose of the torus hall. The other equipment can survive under the gamma-ray field in the torus hall.

  4. Surface-emitting laser logic

    SciTech Connect

    Olbright, G.R.; Bryan, R.P.; Brennan, T.M.; Lear, K.; Poirier, G.E.; Fu, W.S. ); Jewell, J.L.; Lee, Y.H. )

    1990-10-31

    We describe a new class of optical logic devices which consist of integrated phototransistors and surface-emitting lasers. The devices function as optical neurons having high gain and, as arrays, are ideal for neural networks, parallel optical signal processing and optical computing applications. 3 refs., 3 figs.

  5. Interlocked DNA nanostructures controlled by a reversible logic circuit

    PubMed Central

    Li, Tao; Lohmann, Finn; Famulok, Michael

    2014-01-01

    DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207

  6. Interlocked DNA nanostructures controlled by a reversible logic circuit.

    PubMed

    Li, Tao; Lohmann, Finn; Famulok, Michael

    2014-09-17

    DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems.

  7. Fuzzy logic

    NASA Technical Reports Server (NTRS)

    Zadeh, Lofti A.

    1988-01-01

    The author presents a condensed exposition of some basic ideas underlying fuzzy logic and describes some representative applications. The discussion covers basic principles; meaning representation and inference; basic rules of inference; and the linguistic variable and its application to fuzzy control.

  8. Fuzzy logic

    NASA Technical Reports Server (NTRS)

    Zadeh, Lofti A.

    1988-01-01

    The author presents a condensed exposition of some basic ideas underlying fuzzy logic and describes some representative applications. The discussion covers basic principles; meaning representation and inference; basic rules of inference; and the linguistic variable and its application to fuzzy control.

  9. Synthesizing Biomolecule-based Boolean Logic Gates

    PubMed Central

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2012-01-01

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

  10. Synthesizing biomolecule-based Boolean logic gates.

    PubMed

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2013-02-15

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications.

  11. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  12. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  13. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  14. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to noninvasively change one or more...

  15. A label-free and enzyme-free system for operating various logic devices using poly(thymine)-templated CuNPs and SYBR Green I as signal transducers.

    PubMed

    Wu, Changtong; Zhou, Chunyang; Wang, Erkang; Dong, Shaojun

    2016-08-07

    For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations.

  16. PROGRAMMABLE DISPLAY PUSHBUTTON LEGEND EDITOR

    NASA Technical Reports Server (NTRS)

    Busquets, A. M.

    1994-01-01

    The Programmable Display Pushbutton (PDP) is a pushbutton device available from Micro Switch which has a programmable 16 x 35 matrix of LEDs on the pushbutton surface. Any desired legends can be displayed on the PDPs, producing user-friendly applications which greatly reduce the need for dedicated manual controls. Because the PDP can interact with the operator, it can call for the correct response before transmitting its next message. It is both a simple manual control and a sophisticated programmable link between the operator and the host system. The Programmable Display Pushbutton Legend Editor, PDPE, is used to create the LED displays for the pushbuttons. PDPE encodes PDP control commands and legend data into message byte strings sent to a Logic Refresh and Control Unit (LRCU). The LRCU serves as the driver for a set of four PDPs. The legend editor (PDPE) transmits to the LRCU user specified commands that control what is displayed on the LED face of the individual pushbuttons. Upon receiving a command, the LRCU transmits an acknowledgement that the message was received and executed successfully. The user then observes the effect of the command on the PDP displays and decides whether or not to send the byte code of the message to a data file so that it may be called by an applications program. The PDPE program is written in FORTRAN for interactive execution. It was developed on a DEC VAX 11/780 under VMS. It has a central memory requirement of approximately 12800 bytes. It requires four Micro Switch PDPs and two RS-232 VAX 11/780 terminal ports. The PDPE program was developed in 1985.

  17. Optically controllable molecular logic circuits

    SciTech Connect

    Nishimura, Takahiro Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-07-06

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.

  18. Low delay and area efficient soft error correction in arbitration logic

    DOEpatents

    Sugawara, Yutaka

    2013-09-10

    There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.

  19. Summary of Proton Test on the Quick Logic QL3025 at Indiana University

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This issue of the Programmable Logic Application Notes is a compilation of topics: (1) Proton irradiation tests were performed on the Quick Logic QL3025 at the Indian University Cyclotron facility. The devices, tests, and results are discussed; (2) The functional failure of EEPROM's in heavy ion environment is presented; (3) the Act 1 architecture is summarized; (4) Antifuse hardness and hardness testing is updated; the single even upset (SEU) response of hardwired flip-flops is also presented; (4) Total dose results of the ACT 2 and ACT 3 circuits is presented in a chart; (5) Recent sub-micron devices testing of total dose is presented in a chart along with brief discussion; and (6) a reference to the WWW site for more articles of interest.

  20. The combination of a programmable valve and a subclavicular anti-gravity device in hydrocephalus patients at high risk for hygromas.

    PubMed

    Zachenhofer, Iris; Donat, Markus; Roessler, Karl

    2012-04-01

    In order to avoid occurrence of post-operative hygromas in specific hydrocephalus patients being at high risk of overdrainage, a combination of programmable valve and anti-gravity device is widely recommended. We analyzed our series of hydrocephalus patients implanted with such a shunt configuration focusing on complications in relation to over-/underdrainage and neurological outcome. In 28 hydrocephalic patients (14 women and 14 men; mean age 65 years, range from 14 to 82 years; 11 normal pressure, 7 post-traumatic, and 4 post-hemorrhagic hydrocephalus), a Codman Medos programmable valve combined with a Miethke shunt assistant (SA) was implanted at the Department of Neurosurgery of the Academic Teaching Hospital Feldkirch. Implantation was performed simultaneously in 20 patients during the primary procedure: in five patients, SA was placed during revision surgery, and in three patients, the patent system was completed by additional implantation of an SA. Subdural hematoma occurred in one out of 20 patients with SA implantation during primary procedure and in two out of eight patients with SA implantation as secondary procedure, respectively. Shunt occlusion occurred in one patient out of the patients with SA implantation during primary procedure, but was seen in three patients with pre-existing shunt without SA. Shunt infection occurred in one case. Our results suggest the combination of an adjustable valve and SA as an effective treatment for a specific group of hydrocephalus patients being at high risk for overdrainage.

  1. A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

    NASA Astrophysics Data System (ADS)

    Szplet, R.; Kalisz, J.; Jachna, Z.

    2009-02-01

    We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

  2. On plant roots logical gates.

    PubMed

    Adamatzky, Andrew; Sirakoulis, Georgios Ch; Martínez, Genaro J; Baluška, Frantisek; Mancuso, Stefano

    Theoretical constructs of logical gates implemented with plant roots are morphological computing asynchronous devices. Values of Boolean variables are represented by plant roots. A presence of a plant root at a given site symbolises the logical True, an absence the logical False. Logical functions are calculated via interaction between roots. Two types of two-inputs-two-outputs gates are proposed: a gate 〈x, y〉→〈xy, x+y〉 where root apexes are guided by gravity and a gate 〈x,y〉→〈x¯y,x〉 where root apexes are guided by humidity. We propose a design of binary half-adder based on the gates. Copyright © 2017 Elsevier B.V. All rights reserved.

  3. Nanoparticle Based Logic Gates

    NASA Astrophysics Data System (ADS)

    Berven, Christopher; Wybourne, Martin; Longstreth, Lydia

    2003-05-01

    Ligand stabilized gold nanoparticles have novel properties that can be exploited for their use as possible building blocks for room-temperature single electron devices. With a core of 70 gold atoms or less (diameter <= 1.4 nm), the self-capacitance of these particles is a fraction of an atto-Farad. This small capacitance translates into an electrostatic charging energy well in excess of the thermal energy at room temperature. Single electron behavior has been demonstrated in one- and two-dimensional arrays of nanoparticles. In traditional single electron devices, the self-capacitance is negligible, whereas the self-capacitance in nanoparticle based devices can be the dominant capacitance. This means that the effect of charging a nanoparticle chain is highly localized which is in contrast to traditional single electron devices where the induced potential due to an excess electron on an island is felt by many neighboring islands. As a result, the current-voltage characteristics and plots of stable electron occupancy in the arrays have different behavior to that found in traditional devices. We show that this new regime of tunneling behavior can be exploited to create a novel family of single-electron logic gate devices. Using numerical simulation we have found that when a one-dimensional array of nanoparticles is gated in an electron-pump arrangement and properly biased, the behavior is that of an AND gate. The addition of an inverter circuit results in NAND gate behavior, the inverter providing the power necessary for the cascading of multiple NAND gates and the generation of arbitrary logic circuits.

  4. Digitally controlled fault-tolerant multiwavelength programmable fiber-optic attenuator using a two-dimensional digital micromirror device.

    PubMed

    Riza, N A; Sumriddetchkajorn, S

    1999-03-01

    A digitally controlled multiwavelength variable fiber-optic attenuator using a two-dimensional digital micromirror device (DMD) is introduced. The results from an experimental four-wavelength (i.e., 1546.92, 1548.52, 1550.12, and 1551.72 nm) proof-of-concept attenuator indicate a 26-dB dynamic range and 11-bit resolution. The measured attenuator average coherent optical cross talk per wavelength channel is -38 dB , limited by the additive noise resulting from the nonideal isolation of the optical circulator and the attenuator module. The average optical loss for our experimental attenuator is 15 dB and is limited mainly by the visible-mode DMD that is used as a 1550-nm infrared window device. Our theoretical estimate of a <8-dB loss optimized attenuator can be used for equalization in multiwavelength fiber-optic communications with as many as 108 wavelengths.

  5. Gate-Controlled BP-WSe2 Heterojunction Diode for Logic Rectifiers and Logic Optoelectronics.

    PubMed

    Li, Dong; Wang, Biao; Chen, Mingyuan; Zhou, Jun; Zhang, Zengxing

    2017-06-01

    p-n junctions play an important role in modern semiconductor electronics and optoelectronics, and field-effect transistors are often used for logic circuits. Here, gate-controlled logic rectifiers and logic optoelectronic devices based on stacked black phosphorus (BP) and tungsten diselenide (WSe2 ) heterojunctions are reported. The gate-tunable ambipolar charge carriers in BP and WSe2 enable a flexible, dynamic, and wide modulation on the heterojunctions as isotype (p-p and n-n) and anisotype (p-n) diodes, which exhibit disparate rectifying and photovoltaic properties. Based on such characteristics, it is demonstrated that BP-WSe2 heterojunction diodes can be developed for high-performance logic rectifiers and logic optoelectronic devices. Logic optoelectronic devices can convert a light signal to an electric one by applied gate voltages. This work should be helpful to expand the applications of 2D crystals. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. A portable microfluidic device for the rapid diagnosis of cancer metastatic potential which is programmable for temperature and CO2.

    PubMed

    Yu, I F; Yu, Y H; Chen, L Y; Fan, S K; Chou, H Y E; Yang, J T

    2014-09-21

    If metastasis of lung cancer can be found and treated early, a victim might have an improved chance to prevail over it, but routine examinations such as chest radiography, computed tomography and biopsy cannot characterize the metastatic potential of lung cancer cells; critical diagnoses to define optimal therapeutic strategies are thus lost. We designed a portable microfluidic device for the rapid diagnosis of cancer metastatic potential. Featuring a micro system to control temperature and a bicarbonate buffered environment, our device discriminates a rate of surface detachment as an index of the migratory ability of cells cultured on pH-responsive chitosan. We labeled metastatic subpopulations of lung cancer cell lines, and verified that our device is capable of separating cells according to their metastatic ability. As only few cells are needed, a patient's specimen from biopsies, e.g. from fine-needle aspiration, can be processed on site to offer immediate information to physicians. We expect that our design will provide valuable information in pre-operative evaluations to assist the definition of therapeutic plans for lung cancer, as well as for metastatic tumors of other types.

  7. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

    SciTech Connect

    Berger, Andrew J. Page, Michael R.; Young, Justin R.; Bhallamudi, Vidya P.; Johnston-Halperin, Ezekiel; Pelekhov, Denis V.; Hammel, P. Chris; Jacob, Jan; Lewis, Jim; Wenzel, Lothar

    2014-12-15

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  8. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

    PubMed

    Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

    2014-12-01

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  9. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

    NASA Astrophysics Data System (ADS)

    Berger, Andrew J.; Page, Michael R.; Jacob, Jan; Young, Justin R.; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P.; Johnston-Halperin, Ezekiel; Pelekhov, Denis V.; Hammel, P. Chris

    2014-12-01

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  10. Efficient G(sup 4)FET-Based Logic Circuits

    NASA Technical Reports Server (NTRS)

    Vatan, Farrokh

    2008-01-01

    A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

  11. Adaptive parallel logic networks

    NASA Technical Reports Server (NTRS)

    Martinez, Tony R.; Vidal, Jacques J.

    1988-01-01

    Adaptive, self-organizing concurrent systems (ASOCS) that combine self-organization with massive parallelism for such applications as adaptive logic devices, robotics, process control, and system malfunction management, are presently discussed. In ASOCS, an adaptive network composed of many simple computing elements operating in combinational and asynchronous fashion is used and problems are specified by presenting if-then rules to the system in the form of Boolean conjunctions. During data processing, which is a different operational phase from adaptation, the network acts as a parallel hardware circuit.

  12. Slime mould processors, logic gates and sensors.

    PubMed

    Adamatzky, A

    2015-07-28

    A heterotic, or hybrid, computation implies that two or more substrates of different physical nature are merged into a single device with indistinguishable parts. These hybrid devices then undertake coherent acts on programmable and sensible processing of information. We study the potential of heterotic computers using slime mould acting under the guidance of chemical, mechanical and optical stimuli. Plasmodium of acellular slime mould Physarum polycephalum is a gigantic single cell visible to the unaided eye. The cell shows a rich spectrum of behavioural morphological patterns in response to changing environmental conditions. Given data represented by chemical or physical stimuli, we can employ and modify the behaviour of the slime mould to make it solve a range of computing and sensing tasks. We overview results of laboratory experimental studies on prototyping of the slime mould morphological processors for approximation of Voronoi diagrams, planar shapes and solving mazes, and discuss logic gates implemented via collision of active growing zones and tactile responses of P. polycephalum. We also overview a range of electronic components--memristor, chemical, tactile and colour sensors-made of the slime mould. © 2015 The Author(s) Published by the Royal Society. All rights reserved.

  13. Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions

    NASA Astrophysics Data System (ADS)

    Suzuki, D.; Natsui, M.; Endoh, T.; Ohno, H.; Hanyu, T.

    2012-04-01

    A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ devices make it possible not only to reduce the effect of resistance variation, but also to enhance the programmability of resistance values, which achieves a sufficient sensing margin even when process variation is serious in the recent nanometer-scaled VLSI. Moreover, the additional MTJ devices do not increase the effective chip area because the configuration circuit using MTJ devices is simplified and these devices are stacked over the CMOS plane. As a result, the transistor counts of the proposed circuit are reduced by 62% in comparison with those of a conventional nonvolatile LUT circuit where CMOS-only-based volatile static random access memory cell circuits are replaced by MTJ-based nonvolatile ones.

  14. Majority logic gate for 3D magnetic computing.

    PubMed

    Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

    2014-08-22

    For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

  15. Queuing register uses fluid logic elements

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Queuing register /a multistage bit-shifting device/ uses a series of pure fluid elements to perform the required logic operations. The register has several stages of three-state pure fluid elements combined with two-input NOR gates.

  16. Programmable scan/read circuitry for charge coupled device imaging detectors. [spcecraft attitude control and star trackers

    NASA Technical Reports Server (NTRS)

    Salomon, P. M.; Smilowitz, K.

    1984-01-01

    A circuit for scanning and outputting the induced charges in a solid state charge coupled device (CCD) image detector is disclosed in an image detection system for use in a spacecraft attitude control system. The image detection system includes timing control circuitry for selectively controlling the output of the CCD detector so that video outputs are provided only with respect to induced charges corresponding to predetermined sensing element lines of the CCD detector. The timing control circuit and the analog to digital converter are controlled by a programmed microprocessor which defines the video outputs to be converted and further controls the timing control circuit so that no video outputs are provided during the delay associated with analog to digital conversion.

  17. Molecular processors: from qubits to fuzzy logic.

    PubMed

    Gentili, Pier Luigi

    2011-03-14

    Single molecules or their assemblies are information processing devices. Herein it is demonstrated how it is possible to process different types of logic through molecules. As long as decoherent effects are maintained far away from a pure quantum mechanical system, quantum logic can be processed. If the collapse of superimposed or entangled wavefunctions is unavoidable, molecules can still be used to process either crisp (binary or multi-valued) or fuzzy logic. The way for implementing fuzzy inference engines is declared and it is supported by the examples of molecular fuzzy logic systems devised so far. Fuzzy logic is drawing attention in the field of artificial intelligence, because it models human reasoning quite well. This ability may be due to some structural analogies between a fuzzy logic system and the human nervous system. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  18. Bilayer avalanche spin-diode logic

    SciTech Connect

    Friedman, Joseph S. Querlioz, Damien; Fadel, Eric R.; Wessels, Bruce W.; Sahakian, Alan V.

    2015-11-15

    A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.

  19. A new laterally conductive bridge random access memory by fully CMOS logic compatible process

    NASA Astrophysics Data System (ADS)

    Hsieh, Min-Che; Chin, Yung-Wen; Lin, Yu-Cheng; Chih, Yu-Der; Tsai, Kan-Hsueh; Tsai, Ming-Jinn; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

  20. Using a Commercial Ethernet PHY Device in a Radiation Environment

    NASA Technical Reports Server (NTRS)

    Parks, Jeremy; Arani, Michael; Arroyo, Roberto

    2014-01-01

    This work involved placing a commercial Ethernet PHY on its own power boundary, with limited current supply, and providing detection methods to determine when the device is not operating and when it needs either a reset or power-cycle. The device must be radiation-tested and free of destructive latchup errors. The commercial Ethernet PHY's own power boundary must be supplied by a current-limited power regulator that must have an enable (for power cycling), and its maximum power output must not exceed the PHY's input requirements, thus preventing damage to the device. A regulator with configurable output limits and short-circuit protection (such as the RHFL4913, rad hard positive voltage regulator family) is ideal. This will prevent a catastrophic failure due to radiation (such as a short between the commercial device's power and ground) from taking down the board's main power. Logic provided on the board will detect errors in the PHY. An FPGA (field-programmable gate array) with embedded Ethernet MAC (Media Access Control) will work well. The error detection includes monitoring the PHY's interrupt line, and the status of the Ethernet's switched power. When the PHY is determined to be non-functional, the logic device resets the PHY, which will often clear radiation induced errors. If this doesn't work, the logic device power-cycles the FPGA by toggling the regulator's enable input. This should clear almost all radiation induced errors provided the device is not latched up.

  1. "Modeling" Youth Work: Logic Models, Neoliberalism, and Community Praxis

    ERIC Educational Resources Information Center

    Carpenter, Sara

    2016-01-01

    This paper examines the use of logic models in the development of community initiatives within the AmeriCorps program. AmeriCorps is the civilian national service programme in the U.S., operating as a grants programme to local governments and not-for-profit organisations and providing low-cost labour to address pressing issues of social…

  2. Assembly For Moving a Robotic Device Along Selected Axes

    NASA Technical Reports Server (NTRS)

    Nowlin, Brentley Craig (Inventor); Koch, Lisa Danielle (Inventor)

    2001-01-01

    An assembly for moving a robotic device along selected axes includes a programmable logic controller (PLC) for controlling movement of the device along selected axes to effect movement of the device to a selected disposition. The PLC includes a plurality of single axis motion control modules, and a central processing unit (CPU) in communication with the motion control modules. A human-machine interface is provided for operator selection of configurations of device movements and is in communication with the CPU. A motor drive is in communication with each of the motion control modules and is operable to effect movement of the device along the selected axes to obtain movement of the device to the selected disposition.

  3. Assembly For Moving a Robotic Device Along Selected Axes

    NASA Technical Reports Server (NTRS)

    Nowlin, Brentley Craig (Inventor); Koch, Lisa Danielle (Inventor)

    2001-01-01

    An assembly for moving a robotic device along selected axes includes a programmable logic controller (PLC) for controlling movement of the device along selected axes to effect movement of the device to a selected disposition. The PLC includes a plurality of single axis motion control modules, and a central processing unit (CPU) in communication with the motion control modules. A human-machine interface is provided for operator selection of configurations of device movements and is in communication with the CPU. A motor drive is in communication with each of the motion control modules and is operable to effect movement of the device along the selected axes to obtain movement of the device to the selected disposition.

  4. Proposed ultralow-energy dual photonic-crystal nanobeam devices for on-chip N x N switching, logic, and wavelength multiplexing.

    PubMed

    Soref, Richard; Hendrickson, Joshua

    2015-12-14

    Silicon-on-insulator Mach-Zehnder interferometer structures that utilize a photonic crystal nanobeam waveguide in each of two connecting arms are proposed here as efficient 2 × 2 resonant, wavelength-selective electro-optical routing switches that are readily cascaded into on-chip N × N switching networks. A localized lateral PN junction of length ~2 μm within each of two identical nanobeams is proposed as a means of shifting the transmission resonance by 400 pm within the 1550 nm band. Using a bias swing ΔV = 2.7 V, the 474 attojoules-per-bit switching mechanism is free-carrier sweepout due to PN depletion layer widening. Simulations of the 2 × 2 outputs versus voltage are presented. Dual-nanobeam designs are given for N × N data-routing matrix switches, electrooptical logic unit cells, N × M wavelength selective switches, and vector matrix multipliers. Performance penalties are analyzed for possible fabrication induced errors such as non-ideal 3-dB couplers, differences in optical path lengths, and variations in photonic crystal cavity resonances.

  5. Fluid logic control circuit operates nutator actuator motor

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.

  6. Oscillatory threshold logic.

    PubMed

    Borresen, Jon; Lynch, Stephen

    2012-01-01

    In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory.

  7. Oscillatory Threshold Logic

    PubMed Central

    Borresen, Jon; Lynch, Stephen

    2012-01-01

    In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

  8. LOGIC CIRCUIT

    DOEpatents

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  9. Possible realization of entanglement, logical gates, and quantum-information transfer with superconducting-quantum-interference-device qubits in cavity QED

    SciTech Connect

    Yang, C.-P.; Chu, S.-I.; Han Siyuan

    2003-04-01

    We present a scheme to achieve maximally entangled states, controlled phase-shift gate, and SWAP gate for two superconducting-quantum-interference-device (SQUID) qubits, by placing SQUIDs in a microwave cavity. We also show how to transfer quantum information from one SQUID qubit to another. In this scheme, no transfer of quantum information between the SQUIDs and the cavity is required, the cavity field is only virtually excited and thus the requirement on the quality factor of the cavity is greatly relaxed.

  10. Application of SEU imaging for analysis of device architecture using a 25 MeV/u 86Kr ion microbeam at HIRFL

    NASA Astrophysics Data System (ADS)

    Liu, Tianqi; Yang, Zhenlei; Guo, Jinlong; Du, Guanghua; Tong, Teng; Wang, Xiaohui; Su, Hong; Liu, Wenjing; Liu, Jiande; Wang, Bin; Ye, Bing; Liu, Jie

    2017-08-01

    The heavy-ion imaging of single event upset (SEU) in a flash-based field programmable gate array (FPGA) device was carried out for the first time at Heavy Ion Research Facility in Lanzhou (HIRFL). The three shift register chains with separated input and output configurations in device under test (DUT) were used to identify the corresponding logical area rapidly once an upset occurred. The logic units in DUT were partly configured in order to distinguish the registers in SEU images. Based on the above settings, the partial architecture of shift register chains in DUT was imaged by employing the microbeam of 86Kr ion with energy of 25 MeV/u in air. The results showed that the physical distribution of registers in DUT had a high consistency with its logical arrangement by comparing SEU image with logic configuration in scanned area.

  11. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Pacemaker programmers. 870.3700 Section 870.3700 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers...

  12. Fuzzy logic controller optimization

    DOEpatents

    Sepe, Jr., Raymond B; Miller, John Michael

    2004-03-23

    A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.

  13. Probabilistic and fuzzy logic in clinical diagnosis.

    PubMed

    Licata, G

    2007-06-01

    In this study I have compared classic and fuzzy logic and their usefulness in clinical diagnosis. The theory of probability is often considered a device to protect the classical two-valued logic from the evidence of its inadequacy to understand and show the complexity of world [1]. This can be true, but it is not possible to discard the theory of probability. I will argue that the problems and the application fields of the theory of probability are very different from those of fuzzy logic. After the introduction on the theoretical bases of fuzzy approach to logic, I have reported some diagnostic argumentations employing fuzzy logic. The state of normality and the state of disease often fight their battle on scalar quantities of biological values and it is not hard to establish a correspondence between the biological values and the percent values of fuzzy logic. Accordingly, I have suggested some applications of fuzzy logic in clinical diagnosis and in particular I have utilised a fuzzy curve to recognise subjects with diabetes mellitus, renal failure and liver disease. The comparison between classic and fuzzy logic findings seems to indicate that fuzzy logic is more adequate to study the development of biological events. In fact, fuzzy logic is useful when we have a lot of pieces of information and when we dispose to scalar quantities. In conclusion, increasingly the development of technology offers new instruments to measure pathological parameters through scalar quantities, thus it is reasonable to think that in the future fuzzy logic will be employed more in clinical diagnosis.

  14. Nonlinear dynamics based digital logic and circuits

    PubMed Central

    Kia, Behnam; Lindner, John. F.; Ditto, William L.

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096

  15. Nonlinear dynamics based digital logic and circuits.

    PubMed

    Kia, Behnam; Lindner, John F; Ditto, William L

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

  16. Programmable physiological infusion

    NASA Technical Reports Server (NTRS)

    Howard, W. H.; Young, D. R.; Adachi, R. R. (Inventor)

    1974-01-01

    A programmable physiological infusion device and method are provided wherein a program source, such as a paper tape, is used to actuate an infusion pump in accordance with a desired program. The system is particularly applicable for dispensing calcium in a variety of waveforms.

  17. Fuzzy Logic Particle Tracking

    NASA Technical Reports Server (NTRS)

    2005-01-01

    A new all-electronic Particle Image Velocimetry technique that can efficiently map high speed gas flows has been developed in-house at the NASA Lewis Research Center. Particle Image Velocimetry is an optical technique for measuring the instantaneous two component velocity field across a planar region of a seeded flow field. A pulsed laser light sheet is used to illuminate the seed particles entrained in the flow field at two instances in time. One or more charged coupled device (CCD) cameras can be used to record the instantaneous positions of particles. Using the time between light sheet pulses and determining either the individual particle displacements or the average displacement of particles over a small subregion of the recorded image enables the calculation of the fluid velocity. Fuzzy logic minimizes the required operator intervention in identifying particles and computing velocity. Using two cameras that have the same view of the illumination plane yields two single exposure image frames. Two competing techniques that yield unambiguous velocity vector direction information have been widely used for reducing the single-exposure, multiple image frame data: (1) cross-correlation and (2) particle tracking. Correlation techniques yield averaged velocity estimates over subregions of the flow, whereas particle tracking techniques give individual particle velocity estimates. For the correlation technique, the correlation peak corresponding to the average displacement of particles across the subregion must be identified. Noise on the images and particle dropout result in misidentification of the true correlation peak. The subsequent velocity vector maps contain spurious vectors where the displacement peaks have been improperly identified. Typically these spurious vectors are replaced by a weighted average of the neighboring vectors, thereby decreasing the independence of the measurements. In this work, fuzzy logic techniques are used to determine the true

  18. Reversible logic for supercomputing.

    SciTech Connect

    DeBenedictis, Erik P.

    2005-05-01

    This paper is about making reversible logic a reality for supercomputing. Reversible logic offers a way to exceed certain basic limits on the performance of computers, yet a powerful case will have to be made to justify its substantial development expense. This paper explores the limits of current, irreversible logic for supercomputers, thus forming a threshold above which reversible logic is the only solution. Problems above this threshold are discussed, with the science and mitigation of global warming being discussed in detail. To further develop the idea of using reversible logic in supercomputing, a design for a 1 Zettaflops supercomputer as required for addressing global climate warming is presented. However, to create such a design requires deviations from the mainstream of both the software for climate simulation and research directions of reversible logic. These deviations provide direction on how to make reversible logic practical.

  19. Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs

    NASA Astrophysics Data System (ADS)

    Fang, Wu; Huowen, Zhang; Jinmei, Lai; Yuan, Wang; Liguang, Chen; Lei, Duan; Jiarong, Tong

    2009-06-01

    This paper presents a universal field programmable gate array (FPGA) programmable routing circuit, focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.

  20. Logic Design Pathology and Space Flight Electronics

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Barto, Rod L.; Erickson, K.

    1997-01-01

    Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

  1. Toward spin-based Magneto Logic Gate in Graphene

    NASA Astrophysics Data System (ADS)

    Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

    Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

  2. Nonvolatile ``AND,'' ``OR,'' and ``NOT'' Boolean logic gates based on phase-change memory

    NASA Astrophysics Data System (ADS)

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-01

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  3. Separation Logic and Concurrency

    NASA Astrophysics Data System (ADS)

    Bornat, Richard

    Concurrent separation logic is a development of Hoare logic adapted to deal with pointers and concurrency. Since its inception, it has been enhanced with a treatment of permissions to enable sharing of data between threads, and a treatment of variables as resource alongside heap cells as resource. An introduction to the logic is given with several examples of proofs, culminating in a treatment of Simpson's 4-slot algorithm, an instance of racy non-blocking concurrency.

  4. Optical Logic Gates

    NASA Technical Reports Server (NTRS)

    Du Fresne, E. R.; Dowler, W. L.

    1985-01-01

    Logic gates for light signals constructed from combinations of prisms, polarizing plates, and quarterwave plates. Optical logic gate performs elementary logic operation on light signals received along two optical fibers. Whether gate performs OR function or exclusive-OR function depends on orientation of analyzer. Nonbinary truth tables also obtained by rotating polarizer or analyzer to other positions or inserting other quarter-wave plates.

  5. Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; LaBel, Kenneth; Kim, Hak

    2014-01-01

    An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

  6. Complete all-optical processing polarization-based binary logic gates and optical processors.

    PubMed

    Zaghloul, Y A; Zaghloul, A R M

    2006-10-16

    We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple

  7. Complete all-optical processing polarization-based binary logic gates and optical processors

    NASA Astrophysics Data System (ADS)

    Zaghloul, Y. A.; Zaghloul, A. R. M.

    2006-10-01

    We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple

  8. A programmable heater control circuit for spacecraft

    NASA Technical Reports Server (NTRS)

    Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

    1994-01-01

    Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

  9. Fuzzy Logic Engine

    NASA Technical Reports Server (NTRS)

    Howard, Ayanna

    2005-01-01

    The Fuzzy Logic Engine is a software package that enables users to embed fuzzy-logic modules into their application programs. Fuzzy logic is useful as a means of formulating human expert knowledge and translating it into software to solve problems. Fuzzy logic provides flexibility for modeling relationships between input and output information and is distinguished by its robustness with respect to noise and variations in system parameters. In addition, linguistic fuzzy sets and conditional statements allow systems to make decisions based on imprecise and incomplete information. The user of the Fuzzy Logic Engine need not be an expert in fuzzy logic: it suffices to have a basic understanding of how linguistic rules can be applied to the user's problem. The Fuzzy Logic Engine is divided into two modules: (1) a graphical-interface software tool for creating linguistic fuzzy sets and conditional statements and (2) a fuzzy-logic software library for embedding fuzzy processing capability into current application programs. The graphical- interface tool was developed using the Tcl/Tk programming language. The fuzzy-logic software library was written in the C programming language.

  10. SRAM Based Re-programmable FPGA for Space Applications

    NASA Technical Reports Server (NTRS)

    Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

    1999-01-01

    An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

  11. Design and simulation of programmable relational optoelectronic time-pulse coded processors as base elements for sorting neural networks

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Lazareva, Maria V.

    2010-05-01

    In the paper we show that the biologically motivated conception of time-pulse encoding usage gives a set of advantages (single methodological basis, universality, tuning simplicity, learning and programming et al) at creation and design of sensor systems with parallel input-output and processing for 2D structures hybrid and next generations neuro-fuzzy neurocomputers. We show design principles of programmable relational optoelectronic time-pulse encoded processors on the base of continuous logic, order logic and temporal waves processes. We consider a structure that execute analog signal extraction, analog and time-pulse coded variables sorting. We offer optoelectronic realization of such base relational order logic element, that consists of time-pulse coded photoconverters (pulse-width and pulse-phase modulators) with direct and complementary outputs, sorting network on logical elements and programmable commutation blocks. We make technical parameters estimations of devices and processors on such base elements by simulation and experimental research: optical input signals power 0.2 - 20 uW, processing time 1 - 10 us, supply voltage 1 - 3 V, consumption power 10 - 100 uW, extended functional possibilities, learning possibilities. We discuss some aspects of possible rules and principles of learning and programmable tuning on required function, relational operation and realization of hardware blocks for modifications of such processors. We show that it is possible to create sorting machines, neural networks and hybrid data-processing systems with untraditional numerical systems and pictures operands on the basis of such quasiuniversal hardware simple blocks with flexible programmable tuning.

  12. Indexing and Retrieval Performance: The Logical Evidence.

    ERIC Educational Resources Information Center

    Soergel, Dagobert

    1994-01-01

    Presents a logical analysis of the characteristics of indexing and their effects on retrieval. The foundational questions of performance evaluation and the basic quantitative performance measures for binary noninteractive retrieval systems are established. The effects of indexing devices, indexing exhaustivity, specificity, correctness, and…

  13. Fundamentals of Digital Logic.

    ERIC Educational Resources Information Center

    Noell, Monica L.

    This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…

  14. Identifying Logical Necessity

    ERIC Educational Resources Information Center

    Yopp, David

    2010-01-01

    Understanding logical necessity is an important component of proof and reasoning for teachers of grades K-8. The ability to determine exactly where young students' arguments are faulty offers teachers the chance to give youngsters feedback as they progress toward writing mathematically valid deductive proofs. As defined, logical necessity is the…

  15. Logic via Computer Programming.

    ERIC Educational Resources Information Center

    Wieschenberg, Agnes A.

    This paper proposed the question "How do we teach logical thinking and sophisticated mathematics to unsophisticated college students?" One answer among many is through the writing of computer programs. The writing of computer algorithms is mathematical problem solving and logic in disguise and it may attract students who would otherwise stop…

  16. AROUSAL AND LOGICAL INFERENCE.

    ERIC Educational Resources Information Center

    KOEN, FRANK

    THE PURPOSE OF THE EXPERIMENT WAS TO DETERMINE THE DEGREE TO WHICH PHYSIOLOGICAL AROUSAL, AS INDEXED BY THE GRASON STADLER TYPE OPERANT CONDITIONING APPARATUS (GSR), IS RELATED TO THE ACCURACY OF LOGICAL REASONING. THE STIMULI WERE 12 SYLLOGISMS, THREE OF EACH OF FOUR DIFFERENT LOGICAL FORMS. THE 14 SUBJECTS (SS) INDICATED THEIR AGREEMENT OR…

  17. Fundamentals of Digital Logic.

    ERIC Educational Resources Information Center

    Noell, Monica L.

    This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…

  18. Logic Programming: PROLOG.

    ERIC Educational Resources Information Center

    Lopez, Antonio M., Jr.

    1989-01-01

    Provides background material on logic programing and presents PROLOG as a high-level artificial intelligence programing language that borrows its basic constructs from logic. Suggests the language is one which will help the educator to achieve various goals, particularly the promotion of problem solving ability. (MVL)

  19. Programmability of Co-antidot lattices of optimized geometry

    PubMed Central

    Schneider, Tobias; Langer, Manuel; Alekhina, Julia; Kowalska, Ewa; Oelschlägel, Antje; Semisalova, Anna; Neudert, Andreas; Lenz, Kilian; Potzger, Kay; Kostylev, Mikhail P.; Fassbender, Jürgen; Adeyeye, Adekunle O.; Lindner, Jürgen; Bali, Rantej

    2017-01-01

    Programmability of stable magnetization configurations in a magnetic device is a highly desirable feature for a variety of applications, such as in magneto-transport and spin-wave logic. Periodic systems such as antidot lattices may exhibit programmability; however, to achieve multiple stable magnetization configurations the lattice geometry must be optimized. We consider the magnetization states in Co-antidot lattices of ≈50 nm thickness and ≈150 nm inter-antidot distance. Micromagnetic simulations were applied to investigate the magnetization states around individual antidots during the reversal process. The reversal processes predicted by micromagnetics were confirmed by experimental observations. Magnetization reversal in these antidots occurs via field driven transition between 3 elementary magnetization states – termed G, C and Q. These magnetization states can be described by vectors, and the reversal process proceeds via step-wise linear operations on these vector states. Rules governing the co-existence of the three magnetization states were empirically observed. It is shown that in an n × n antidot lattice, a variety of field switchable combinations of G, C and Q can occur, indicating programmability of the antidot lattices. PMID:28145463

  20. Programmability of Co-antidot lattices of optimized geometry

    NASA Astrophysics Data System (ADS)

    Schneider, Tobias; Langer, Manuel; Alekhina, Julia; Kowalska, Ewa; Oelschlägel, Antje; Semisalova, Anna; Neudert, Andreas; Lenz, Kilian; Potzger, Kay; Kostylev, Mikhail P.; Fassbender, Jürgen; Adeyeye, Adekunle O.; Lindner, Jürgen; Bali, Rantej

    2017-02-01

    Programmability of stable magnetization configurations in a magnetic device is a highly desirable feature for a variety of applications, such as in magneto-transport and spin-wave logic. Periodic systems such as antidot lattices may exhibit programmability; however, to achieve multiple stable magnetization configurations the lattice geometry must be optimized. We consider the magnetization states in Co-antidot lattices of ≈50 nm thickness and ≈150 nm inter-antidot distance. Micromagnetic simulations were applied to investigate the magnetization states around individual antidots during the reversal process. The reversal processes predicted by micromagnetics were confirmed by experimental observations. Magnetization reversal in these antidots occurs via field driven transition between 3 elementary magnetization states – termed G, C and Q. These magnetization states can be described by vectors, and the reversal process proceeds via step-wise linear operations on these vector states. Rules governing the co-existence of the three magnetization states were empirically observed. It is shown that in an n × n antidot lattice, a variety of field switchable combinations of G, C and Q can occur, indicating programmability of the antidot lattices.

  1. Regulatory Conformance Checking: Logic and Logical Form

    ERIC Educational Resources Information Center

    Dinesh, Nikhil

    2010-01-01

    We consider the problem of checking whether an organization conforms to a body of regulation. Conformance is studied in a runtime verification setting. The regulation is translated to a logic, from which we synthesize monitors. The monitors are evaluated as the state of an organization evolves over time, raising an alarm if a violation is…

  2. Regulatory Conformance Checking: Logic and Logical Form

    ERIC Educational Resources Information Center

    Dinesh, Nikhil

    2010-01-01

    We consider the problem of checking whether an organization conforms to a body of regulation. Conformance is studied in a runtime verification setting. The regulation is translated to a logic, from which we synthesize monitors. The monitors are evaluated as the state of an organization evolves over time, raising an alarm if a violation is…

  3. Digital Device Architecture and the Safe Use of Flash Devices in Munitions

    NASA Technical Reports Server (NTRS)

    Katz, Richard B.; Flowers, David; Bergevin, Keith

    2017-01-01

    Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

  4. Rapid engineering of versatile molecular logic gates using heterologous genetic transcriptional modules.

    PubMed

    Wang, Baojun; Buck, Martin

    2014-10-11

    We designed and constructed versatile modular genetic logic gates in bacterial cells. These function as digital logic 1-input Buffer gate, 2-input and 3-input AND gates with one inverted input and integrate multiple chemical input signals in customised logic manners. Such rapidly engineered devices serve to achieve increased sensing signal selectivity.

  5. Valve system incorporating single failure protection logic

    DOEpatents

    Ryan, Rodger; Timmerman, Walter J. H.

    1980-01-01

    A valve system incorporating single failure protective logic. The system consists of a valve combination or composite valve which allows actuation or de-actuation of a device such as a hydraulic cylinder or other mechanism, integral with or separate from the valve assembly, by means of three independent input signals combined in a function commonly known as two-out-of-three logic. Using the input signals as independent and redundant actuation/de-actuation signals, a single signal failure, or failure of the corresponding valve or valve set, will neither prevent the desired action, nor cause the undesired action of the mechanism.

  6. Applications of fuzzy logic

    SciTech Connect

    Zargham, M.R.

    1995-06-01

    Recently, fuzzy logic has been applied to many areas, such as process control, image understanding, robots, expert systems, and decision support systems. This paper will explain the basic concepts of fuzzy logic and its application in different fields. The steps to design a control system will be explained in detail. Fuzzy control is the first successful industrial application of fuzzy logic. A fuzzy controller is able to control systems which previously could only be controlled by skilled operators. In recent years Japan has achieved significant progress in this area and has applied it to variety of products such as cruise control for cars, video cameras, rice cookers, washing machines, etc.

  7. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.

    PubMed

    Sun, Li; Savory, Joshua J; Warncke, Kurt

    2013-08-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range.

  8. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications

    PubMed Central

    Sun, Li; Savory, Joshua J.; Warncke, Kurt

    2014-01-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range. PMID:25076864

  9. Photonic encryption using all optical logic.

    SciTech Connect

    Blansett, Ethan L.; Schroeppel, Richard Crabtree; Tang, Jason D.; Robertson, Perry J.; Vawter, Gregory Allen; Tarman, Thomas David; Pierson, Lyndon George

    2003-12-01

    With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an

  10. Aptamer-Binding Directed DNA Origami Pattern for Logic Gates.

    PubMed

    Yang, Jing; Jiang, Shuoxing; Liu, Xiangrong; Pan, Linqiang; Zhang, Cheng

    2016-12-14

    In this study, an aptamer-substrate strategy is introduced to control programmable DNA origami pattern. Combined with DNA aptamer-substrate binding and DNAzyme-cutting, small DNA tiles were specifically controlled to fill into the predesigned DNA origami frame. Here, a set of DNA logic gates (OR, YES, and AND) are performed in response to the stimuli of adenosine triphosphate (ATP) and cocaine. The experimental results are confirmed by AFM imaging and time-dependent fluorescence changes, demonstrating that the geometric patterns are regulated in a controllable and programmable manner. Our approach provides a new platform for engineering programmable origami nanopatterns and constructing complex DNA nanodevices.

  11. Event Logic Assistant (Elan)

    DTIC Science & Technology

    2008-07-14

    as a basis for Phase II research. 2 Background 2.1 Event logic 2.1.1 Event structures Intuitively, an event structure is an abstract algebraic ...Theoretical Computer Science, 149:257–298, 1995. [2] Uri Abraham. Models for Concurrency, volume 11 of Algebra , Logic and Applications Series. Gordon...the ordering of events in a distributed system. Comms. ACM, 21(7):558–65, 1978. [28] Leslie Lamport. Hybrid systems in TLA+. In Grossman , Nerode, Ravn

  12. Feasibility study for future implantable neural-silicon interface devices.

    PubMed

    Al-Armaghany, Allann; Yu, Bo; Mak, Terrence; Tong, Kin-Fai; Sun, Yihe

    2011-01-01

    The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and transmission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. Field programmable logic arrays (FPGAs) are used to evaluate various structures.

  13. Towards bioelectronic logic (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Meredith, Paul; Mostert, Bernard; Sheliakina, Margarita; Carrad, Damon J.; Micolich, Adam P.

    2016-09-01

    One of the critical tasks in realising a bioelectronic interface is the transduction of ion and electron signals at high fidelity, and with appropriate speed, bandwidth and signal-to-noise ratio [1]. This is a challenging task considering ions and electrons (or holes) have drastically different physics. For example, even the lightest ions (protons) have mobilities much smaller than electrons in the best semiconductors, effective masses are quite different, and at the most basic level, ions are `classical' entities and electrons `quantum mechanical'. These considerations dictate materials and device strategies for bioelectronic interfaces alongside practical aspects such as integration and biocompatibility [2]. In my talk I will detail these `differences in physics' that are pertinent to the ion-electron transduction challenge. From this analysis, I will summarise the basic categories of device architecture that are possibilities for transducing elements and give recent examples of their realisation. Ultimately, transducing elements need to be combined to create `bioelectronic logic' capable of signal processing at the interface level. In this regard, I will extend the discussion past the single element concept, and discuss our recent progress in delivering all-solids-state logic circuits based upon transducing interfaces. [1] "Ion bipolar junction transistors", K. Tybrandt, K.C. Larsson, A. Richter-Dahlfors and M. Berggren, Proc. Natl Acad. Sci., 107, 9929 (2010). [2] "Electronic and optoelectronic materials and devices inspired by nature", P Meredith, C.J. Bettinger, M. Irimia-Vladu, A.B. Mostert and P.E. Schwenn, Reports on Progress in Physics, 76, 034501 (2013).

  14. The Rocky Road to Logical Thinking.

    ERIC Educational Resources Information Center

    Burch, Fern; Aaronson, Tim

    1985-01-01

    Presents offline logic activities to extend concepts in "Rocky's Boots." Activities focus on: (1) building logic circuits; (2) recognizing logic in language; (3) playing logic games; and (4) testing logic circuits. Detailed procedures accompanied by illustrative examples are included. (JN)

  15. Nanoeletromechanical switch and logic circuits formed therefrom

    DOEpatents

    Nordquist, Christopher D.; Czaplewski, David A.

    2010-05-18

    A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

  16. DNA “Nano-Claw”: Logic-based Autonomous Cancer Targeting and Therapy

    PubMed Central

    You, Mingxu; Peng, Lu; Shao, Na; Zhang, Liqin; Qiu, Liping; Cui, Cheng; Tan, Weihong

    2014-01-01

    Cell types, both healthy and diseased, can be classified by inventories of their cell-surface markers. Programmable analysis of multiple markers would enable clinicians to develop a comprehensive disease profile, leading to more accurate diagnosis and intervention. As a first step to accomplish this, we have designed a DNA-based device, called “Nano-Claw”. Combining the special structure-switching properties of DNA aptamers with toehold-mediated strand displacement reactions, this claw is capable of performing autonomous logic-based analysis of multiple cancer cell-surface markers and, in response, producing a diagnostic signal and/or targeted photodynamic therapy. We anticipate that this design can be widely applied in facilitating basic biomedical research, accurate disease diagnosis and effective therapy. PMID:24367989

  17. Fuzzy logic based on-line fault detection and classification in transmission line.

    PubMed

    Adhikari, Shuma; Sinha, Nidul; Dorendrajit, Thingam

    2016-01-01

    This study presents fuzzy logic based online fault detection and classification of transmission line using Programmable Automation and Control technology based National Instrument Compact Reconfigurable i/o (CRIO) devices. The LabVIEW software combined with CRIO can perform real time data acquisition of transmission line. When fault occurs in the system current waveforms are distorted due to transients and their pattern changes according to the type of fault in the system. The three phase alternating current, zero sequence and positive sequence current data generated by LabVIEW through CRIO-9067 are processed directly for relaying. The result shows that proposed technique is capable of right tripping action and classification of type of fault at high speed therefore can be employed in practical application.

  18. Advanced logic gates for ultrafast network interchanges

    NASA Astrophysics Data System (ADS)

    Islam, Mohammed N.

    1995-08-01

    By overcoming speed bottlenecks from electronic switching as well as optical/electronic conversions, all-optical logic gates can permit further exploitation of the nearly 40 THz of bandwidth available from optical fibers. We focus on the use of optical solitons and all-optical logic gates to implement ultrafast ``interchanges'' or switching nodes on packet networks with speeds of 100 Gbit/s or greater. For example, all-optical logic gates have been demonstrated with speeds up to 200 Gbit/s, and they may be used to decide whether to add or drop a data packet. The overall goal of our effort is to demonstrate the key enabling technologies and their combination for header processing in 100 Gbit/s, time-division-multiplexed, packed switched networks. Soliton-based fiber logic gates are studied with the goal of combining attractive features of soliton-dragging logic gates, nonlinear loop mirrors, and erbium-doped fiber amplifiers to design logic gates with optimum switching energy, contrast ratio, and timing sensitivity. First, the experimental and numerical work studies low-latency soliton logic gates based on frequency shifts associated with cross-phase modulation. In preliminary experiments, switching in 15 m long low-birefringent fibers has been demonstrated with a contrast ratio of 2.73:1. Using dispersion-shifted fiber in the gate should lower the switching energy and improve the contrast ratio. Next, the low-birefringent fiber can be cross-spliced and wrapped into a nonlinear optical loop mirror to take advantage of mechanisms from both soliton dragging and loop mirrors. The resulting device can have low switching energy and a timing window that results from a combination of soliton dragging and the loop mirror mechanisms.

  19. Complementary symmetry nanowire logic circuits: experimental demonstrations and in silico optimizations.

    PubMed

    Sheriff, Bonnie A; Wang, Dunwei; Heath, James R; Kurtin, Juanita N

    2008-09-23

    Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations.

  20. Magnetic logic based on diode-assisted magnetoresistance

    NASA Astrophysics Data System (ADS)

    Luo, Zhaochu; Zhang, Xiaozhong

    2017-05-01

    Conventional computer suffers from the von Neumann performance bottleneck due to its hardware architecture that non-volatile memory and logic are separated. The new emerging magnetic logic coupling the extra dimension of spin, shows the potential to overcome this performance bottleneck. Here, we propose a novel category of magnetic logic based on diode-assisted magnetoresistance. By coupling Hall effect and nonlinear transport property in silicon, all four basic Boolean logic operations including AND, NAND, OR and NOR, can be programmed at room temperature with high output ratio in one silicon-based device. Further introducing anomalous Hall effect of magnetic material into magnetic logic, we achieve perpendicular magnetic anisotropy-based magnetic logic which combines the advantages of both high output ratio (>103 %) and low work magnetic field (˜1 mT). Integrated with non-volatile magnetic memory, our logic device with unique magnetoelectric properties has the advantages of current-controlled reconfiguration, zero refresh consumption, instant-on performance and would bridge the processor-memory gap. Our findings would pave the way in magnetic logic and offer a feasible platform to build a new kind of magnetic microprocessor with potential of high performance.

  1. The Lick Observatory charge-coupled device /CCD/ and controller

    NASA Technical Reports Server (NTRS)

    Robinson, L. B.

    1981-01-01

    A description is given of a flexible microprocessor-based controller for charge-coupled device two-dimensional detectors. It is noted that the controller can operate under manual control or as a slave to a remote computer linked by coaxial cable. The system is discussed, together with data taken at the telescope and in the laboratory. The flexibility of the controller derives from its modular form and from the use of a programmable 8-bit microprocessor to control and sequence the electronic logic. The electronic circuits for such functions as signal processing, clock sequencing, voltage level adjustment, and temperature control are on small individual plug-in cards, making future improvements and changes simple. The software of the microprocessor is stored in erasable, programmable, read-only memory. Among the limitations of the controller is a scan speed of roughly 35 microsec per pixel.

  2. A programmable CCD driver circuit for multiphase CCD operation

    NASA Technical Reports Server (NTRS)

    Ewin, Audrey J.; Reed, Kenneth V.

    1989-01-01

    A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

  3. Programmable synchronization unit

    SciTech Connect

    Kang, H.

    1984-10-01

    A Programmable Synchronization Unit (PSU, 135-726) has been designed as an element of the new timing system for the Stanford Linear Collider (SLC) project to provide synchronization signals needed for various apparatus in the SLC Damping Ring, or anywhere it is necessary to monitor longer than the fiducial period (approx. = 2.8 ..mu..s). A 119 MHz pulse train derived from the 476 MHz main drive line and superimposed with 360 Hz fiducial signal is the frequency source. Following a programmable delay D of up to 4.4 ..mu..s, the PSU can deliver N pulses of width W (in increments of 8.4 ns) with a pulse period of P (in increments of 58.8 ns, the damping ring half period). The device may be programmed at any time during the interfiducial period.

  4. The impact of software and CAE tools on SEU in field programmable gate arrays

    NASA Astrophysics Data System (ADS)

    Katz, R.; Wang, J.; McCollum, J.; Cronquist, B.

    1999-12-01

    Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements.

  5. 21 CFR 866.5400 - Alpha-globulin immuno-logical test system.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Alpha-globulin immuno-logical test system. 866.5400 Section 866.5400 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5400 Alpha-globulin immuno-logical test system. ...

  6. From Indexed Lax Logic to Intuitionistic Logic

    DTIC Science & Technology

    2008-01-07

    Categorical and Kripke semantics for constructive S4 modal logic. In CSL ’01: Proceedings of the 15th International Workshop on Computer Science Logic, pages...af(K,a) ⇒ af(K,a) by ⊥L 2. Σ, a; pΓ,⊥q, pCq ⊃ af(K,a) ⇒ af(K,a) by definition of p·q Case: D = D1 Σ;Γ, A ⊃ B ⇒ A D2 Σ;Γ, A ⊃ B,B ⇒ C Σ;Γ, A ⊃ B ⇒ C...L 1. Σ; pΓ, A ⊃ Bq ⇒ pAq by i.h. on D1 2. Σ; pΓq, pAq ⊃ pBq ⇒ pAq by definition of p·q 3. Σ; pΓ, A ⊃ B,Bq ⇒ pCq by i.h. on D2 4. Σ; pΓq, pAq ⊃ pBq

  7. Diagnosable structured logic array

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling (Inventor); Miles, Lowell (Inventor); Gambles, Jody (Inventor); Maki, Gary K. (Inventor)

    2009-01-01

    A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.

  8. Extremely large magnetoresistance and magnetic logic by coupling semiconductor nonlinear transport effect and anomalous Hall Effect

    NASA Astrophysics Data System (ADS)

    Zhang, Xiaozhong; Luo, Zhaochu

    Size limitation of silicon FET hinders the further scaling down of silicon based CPU. To solve this problem, spin based magnetic logic devices were proposed but almost all of them could not be realized experimentally except for NOT logic operation. A magnetic field controlled reconfigurable semiconductor logic using InSb was reported. However, InSb is very expensive and not compatible with the silicon technology. Based on our Si based magnetoresistance (MR) device, we developed a Si based reconfigurable magnetic logic device, which could do all four Boolean logic operations including AND, OR, NOR and NAND. By coupling nonlinear transport effect of semiconductor and anomalous Hall effect of magnetic material, we propose a PMA material based MR device with a remarkable non local MR of >20000 % at ~1 mT. Based on this MR device, we further developed a PMA material based magnetic logic device which could do all four Boolean logic operations. This makes it possible that magnetic material does both memory and logic. This may result in a memory-logic integrated system leading to a non von Neumann computer

  9. Reconfigurable magnetic logic combined with non-volatile memory in silicon

    NASA Astrophysics Data System (ADS)

    Luo, Zhaochu; Zhang, Xiaozhong

    Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.

  10. Reconfigurable Boolean Logic Using Magnetic Single-Electron Transistors

    PubMed Central

    Gonzalez-Zalba, M. Fernando; Ciccarelli, Chiara; Zarbo, Liviu P.; Irvine, Andrew C.; Campion, Richard C.; Gallagher, Bryan L.; Jungwirth, Tomas; Ferguson, Andrew J.; Wunderlich, Joerg

    2015-01-01

    We propose a novel hybrid single-electron device for reprogrammable low-power logic operations, the magnetic single-electron transistor (MSET). The device consists of an aluminium single-electron transistor with a GaMnAs magnetic back-gate. Changing between different logic gate functions is realized by reorienting the magnetic moments of the magnetic layer, which induces a voltage shift on the Coulomb blockade oscillations of the MSET. We show that we can arbitrarily reprogram the function of the device from an n-type SET for in-plane magnetization of the GaMnAs layer to p-type SET for out-of-plane magnetization orientation. Moreover, we demonstrate a set of reprogrammable Boolean gates and its logical complement at the single device level. Finally, we propose two sets of reconfigurable binary gates using combinations of two MSETs in a pull-down network. PMID:25923789

  11. Fuzzy logic controller to improve powerline communication

    NASA Astrophysics Data System (ADS)

    Tirrito, Salvatore

    2015-12-01

    The Power Line Communications (PLC) technology allows the use of the power grid in order to ensure the exchange of data information among devices. This work proposes an approach, based on Fuzzy Logic, that dynamically manages the amplitude of the signal, with which each node transmits, by processing the master-slave link quality measured and the master-slave distance. The main objective of this is to reduce both the impact of communication interferences induced and power consumption.

  12. A digital magnetic resonance imaging spectrometer using digital signal processor and field programmable gate array

    NASA Astrophysics Data System (ADS)

    Liang, Xiao; Binghe, Sun; Yueping, Ma; Ruyan, Zhao

    2013-05-01

    A digital spectrometer for low-field magnetic resonance imaging is described. A digital signal processor (DSP) is utilized as the pulse programmer on which a pulse sequence is executed as a subroutine. Field programmable gate array (FPGA) devices that are logically mapped into the external addressing space of the DSP work as auxiliary controllers of gradient control, radio frequency (rf) generation, and rf receiving separately. The pulse programmer triggers an event by setting the 32-bit control register of the corresponding FPGA, and then the FPGA automatically carries out the event function according to preset configurations in cooperation with other devices; accordingly, event control of the spectrometer is flexible and efficient. Digital techniques are in widespread use: gradient control is implemented in real-time by a FPGA; rf source is constructed using direct digital synthesis technique, and rf receiver is constructed using digital quadrature detection technique. Well-designed performance is achieved, including 1 μs time resolution of the gradient waveform, 1 μs time resolution of the soft pulse, and 2 MHz signal receiving bandwidth. Both rf synthesis and rf digitalization operate at the same 60 MHz clock, therefore, the frequency range of transmitting and receiving is from DC to ˜27 MHz. A majority of pulse sequences have been developed, and the imaging performance of the spectrometer has been validated through a large number of experiments. Furthermore, the spectrometer is also suitable for relaxation measurement in nuclear magnetic resonance field.

  13. Synthetic circuits integrating logic and memory in living cells.

    PubMed

    Siuti, Piro; Yazbek, John; Lu, Timothy K

    2013-05-01

    Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications.

  14. Molecules with a sense of logic: a progress report.

    PubMed

    Andréasson, Joakim; Pischel, Uwe

    2015-03-07

    In this tutorial review, the most recent developments in the field of molecular logic and information processing are discussed. Special emphasis is given to the report of progress in the concatenation of molecular logic devices and switches, the design of memory systems working according to the principles of sequential logic, the mimicking of transistors, and the research on photochromic platforms with an unprecedented degree of functional integration. Furthermore, a series of achievements that add up to the conceptual diversity of molecular logic is introduced, such as the realization of highly complex and logically reversible Toffoli and Fredkin gates by the action of DNAzymes or the use of a multifluorophoric platform as a viable approach towards keypad lock functions.

  15. Anion Sensors as Logic Gates: A Close Encounter?

    PubMed

    Madhuprasad; Bhat, Mahesh P; Jung, Ho-Young; Losic, Dusan; Kurkuri, Mahaveer D

    2016-04-25

    Computers have become smarter, smaller, and more efficient due to the downscaling of silicon-based components. Top-down miniaturisation of silicon-based computer components is fast reaching its limitations because of physical constraints and economical non-feasibility. Therefore, the possibility of a bottom-up approach that uses molecules to build nano-sized devices has been initiated. As a result, molecular logic gates based on chemical inputs and measurable optical outputs have captured significant attention very recently. In addition, it would be interesting if such molecular logic gates could be developed by making use of ion sensors, which can give significantly sensitive output information. This review provides a brief introduction to anion receptors, molecular logic gates, a comprehensive review on describing recent advances and progress on development of ion receptors for molecular logic gates, and a brief idea about the application of molecular logic gates.

  16. The new FDA combination products programme.

    PubMed

    Donawa, Maria

    2002-10-01

    The United States (US) Food and Drug Administration (FDA) has established a Combination Products Programme and developed a new internal procedure to increase its effectiveness in regulating products consisting of combinations of drugs, devices and biological products. This article provides a brief overview of the FDA regulation of combination products and discusses the new Programme.

  17. Stacked resistive switches for AND/OR logic gates

    NASA Astrophysics Data System (ADS)

    Kim, Myung Ju; Son, Kyung Rock; Park, Ju Hyun; Kim, Tae Geun

    2017-06-01

    This paper reports the use of stacked resistive switches as logic gates for implementing the ;AND; and ;OR; operations. These stacked resistive switches consist of two resistive switches that share a middle electrode, and they operate based on the difference in resistance between the low and high resistance states indicating the logical states of ;0; and ;1;, respectively. The stacked resistive switches can perform either AND or OR operation, using two read schemes in one device. To perform the AND (or OR) operation, two resistive switches are arranged in a serial (or parallel) connection. AND and OR operations have been successfully demonstrated using the stacked resistive switches. The use of stacked resistive switches as logic gates that utilize the advantages of memristive devices shows the possibility of stateful logic circuits.

  18. A high-speed digitally programmable CCD transversal filter

    NASA Astrophysics Data System (ADS)

    Chiang, A. M.; Burke, B. E.

    1983-12-01

    A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25 MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 sq mm. To obtain high-speed operation, the pipe organ architecture which allows use of a simple floating diffusion output circuit was adopted. The tap weight values are set by a 6-bit multiplying D/A converter (MDAC) at each delay line input. The MDAC is a multiple CCD input structure with binary-weighted input gate areas and logic-controlled gates to multiply each charge packet by 0 or 1. The conversion speed of this structure is as high as that of a CCD input structure, but careful control of threshold voltage variations is required to achieve high accuracy. Experiments are described which show that threshold offsets can be reduced to about 2 mV rms for a fill-and-spill input, indicating that MDACs of this type, with 8-bit accuracy, are feasible.

  19. A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

    NASA Astrophysics Data System (ADS)

    Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

    2017-03-01

    A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

  20. The Logic of Evaluation.

    ERIC Educational Resources Information Center

    Welty, Gordon A.

    The logic of the evaluation of educational and other action programs is discussed from a methodological viewpoint. However, no attempt is made to develop methods of evaluating programs. In Part I, the structure of an educational program is viewed as a system with three components--inputs, transformation of inputs into outputs, and outputs. Part II…

  1. Quantum probabilistic logic programming

    NASA Astrophysics Data System (ADS)

    Balu, Radhakrishnan

    2015-05-01

    We describe a quantum mechanics based logic programming language that supports Horn clauses, random variables, and covariance matrices to express and solve problems in probabilistic logic. The Horn clauses of the language wrap random variables, including infinite valued, to express probability distributions and statistical correlations, a powerful feature to capture relationship between distributions that are not independent. The expressive power of the language is based on a mechanism to implement statistical ensembles and to solve the underlying SAT instances using quantum mechanical machinery. We exploit the fact that classical random variables have quantum decompositions to build the Horn clauses. We establish the semantics of the language in a rigorous fashion by considering an existing probabilistic logic language called PRISM with classical probability measures defined on the Herbrand base and extending it to the quantum context. In the classical case H-interpretations form the sample space and probability measures defined on them lead to consistent definition of probabilities for well formed formulae. In the quantum counterpart, we define probability amplitudes on Hinterpretations facilitating the model generations and verifications via quantum mechanical superpositions and entanglements. We cast the well formed formulae of the language as quantum mechanical observables thus providing an elegant interpretation for their probabilities. We discuss several examples to combine statistical ensembles and predicates of first order logic to reason with situations involving uncertainty.

  2. Temporal logics meet telerobotics

    NASA Technical Reports Server (NTRS)

    Rutten, Eric; Marce, Lionel

    1989-01-01

    The specificity of telerobotics being the presence of a human operator, decision assistance tools are necessary for the operator, especially in hostile environments. In order to reduce execution hazards due to a degraded ability for quick and efficient recovery of unexpected dangerous situations, it is of importance to have the opportunity, amongst others, to simulate the possible consequences of a plan before its actual execution, in order to detect these problematic situations. Hence the idea of providing the operator with a simulator enabling him to verify the temporal and logical coherence of his plans. Therefore, the power of logical formalisms is used for representation and deduction purposes. Starting from the class of situations that are represented, a STRIPS (the STanford Research Institute Problem Solver)-like formalism and its underlying logic are adapted to the simulation of plans of actions in time. The choice of a temporal logic enables to build a world representation, on which the effects of plans, grouping actions into control structures, will be transcribed by the simulation, resulting in a verdict and information about the plan's coherence.

  3. Substructural Logical Specifications

    DTIC Science & Technology

    2012-11-14

    pronounced “A mobile” or, whimsically, “gnab A” in reference to the pronunciation of !A as “bang A.” The primary sequent of ordered logic is Γ; ∆; Ω =⇒ A...distinguished atomic proposition by inserting a rule into the signature that teaches the atomic proposition how to act like the nested rule. (Or, looking at it

  4. Metacomputation and logic programming

    SciTech Connect

    Abramov, S.M.

    1992-03-01

    This paper presents an approach to logic programming based on implementing reverse semantics of programming languages. The interpreter that implements reverse semantics is called a Universal Resolving Algorithm (URA). Implementation and methods for application of a URA are based on methods of metacomputation. 12 refs., 2 figs.

  5. Mapping Individual Logical Processes

    ERIC Educational Resources Information Center

    Smetana, Frederick O.

    1975-01-01

    A technique to measure and describe concisely a certain class of individual mental reasoning processes has been developed. The measurement is achieved by recording the complete dialog between a large, varied computerized information system with a broad range of logical operations and options and a human information seeker. (Author/RC)

  6. Logic and Simulation.

    ERIC Educational Resources Information Center

    Straumanis, Joan

    A major problem in teaching symbolic logic is that of providing individualized and early feedback to students who are learning to do proofs. To overcome this difficulty, a computer program was developed which functions as a line-by-line proof checker in Sentential Calculus. The program, DEMON, first evaluates any statement supplied by the student…

  7. Behavior of faulty double BJT BiCMOS logic gates

    NASA Technical Reports Server (NTRS)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  8. Boolean logic gates that use enzymes as input signals.

    PubMed

    Strack, Guinevere; Pita, Marcos; Ornatska, Maryna; Katz, Evgeny

    2008-05-23

    Biochemical systems that demonstrate the Boolean logic operations AND, OR, XOR, and InhibA were developed by using soluble compounds, which represent the chemical "devices", and the enzymes glucose oxidase (GOx), glucose dehydrogenase (GDH), alcohol dehydrogenase (AlcDH), and microperoxidase-11 (MP-11), which operated as the input signals that activated the logic gates. The enzymes were used as soluble materials and as immobilized biocatalysts. The studied systems are proposed to be a step towards the construction of "smart" signal-responsive materials with built-in Boolean logic.

  9. Programmable Logic Controller Modification Attacks for use in Detection Analysis

    DTIC Science & Technology

    2014-03-27

    Control System IDS Intrusion Detection System IP Internet Protocol IT Information Technology JTAG Joint Test Action Group LAN Local Area Network PLC...firewalls or Intrusion Detection System (IDS), implementing cryptography, and improving protocol security. There are few vendors, however, that include...Mode Setting Register Values. Mode r0 Value r3 Value PRGM 0x11 0x1 RUN 0x11 0x2 REM PRGM 0x12 0x1 REM RUN 0x12 0x2 cpmode 1 contains two

  10. Application of programmable logic controllers to space simulation

    NASA Technical Reports Server (NTRS)

    Sushon, Janet

    1992-01-01

    Incorporating a state-of-the-art process control and instrumentation system into a complex system for thermal vacuum testing is discussed. The challenge was to connect several independent control systems provided by various vendors to a supervisory computer. This combination will sequentially control and monitor the process, collect the data, and transmit it to color a graphic system for subsequent manipulation. The vacuum system upgrade included: replacement of seventeen diffusion pumps with eight cryogenic pumps and one turbomolecular pump, replacing a relay based control system, replacing vacuum instrumentation, and upgrading the data acquisition system.

  11. Design of Multiple-Valued Programmable Logic Arrays

    DTIC Science & Technology

    1988-12-01

    M2,32,4),inreplicator, 12); /* put Vdd line with label */ inreplicator = ttdx( cydy (box(M2,8,nvar*42+24),vdd,-4),inreplicator,- 18); /* dummy lablel *f...mvpla); /* put GND base line at the right side of layout * tmpcell = cydy (box(M2,8,4),box(M2,8.8),72). if (nvar == 1) tmpcell = cy(box(M2,8,8),tmpcell...tt(tmpcell, cydy (box(M2,8 ,nvar*42+66 ),grl ,-4)):. /* complete layout */ mvpla = bbdy(mvpla,box(M2,8.4).16); mvpla = ttdx(mvpla,tmpcell,-8); /* save

  12. Analysis of an innovative user threshold programmable photoreceiver monolithically integrated in a multitechnology field programmable gate array (MT-FPGA)

    NASA Astrophysics Data System (ADS)

    Mal, Prosenjit; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-10-01

    In the past decade, Field Programmable Gate Arrays (FPGA) has significantly influenced the landscape of the electronic industry. In particular, in the areas of semiconductor manufacturing, CAD tool designs and a wide range of digital logic applications. Primarily, research efforts in the FPGA community have concentrated on improving the reconfigurability or programmability of present day architecture for digital applications. However, the digital nature of FPGA technologies limits their applicability to a wide range of applications that depend on analog circuitry, photonic and RF based technologies. As with any ASIC design, the turn-around time between design iterations may be several months which is prohibitively long for multi-technology test-bed systems where the system designer depends on a rapid prototyping/experimentation environment that allows for optimization of processing algorithms and system architecture. Therefore, we developed innovative FPGA architecture that merges conventional FPGA technology with mixed signal and other multi-technology device. In this paper we discuss the Multi-Technology-FPGA (MT-FPGA) architecture that allows the user to have flexible rapid prototyping environment and provides him or her with the benefits of a conventional FPGA in a mixed signal domain. We substantiate this concept by implementing this architecture in TSMC 0.35 μm process and discussing the results of a variable threshold optical receiver circuit suitable for photonic information processing.

  13. Two-dimensional non-volatile programmable p-n junctions

    NASA Astrophysics Data System (ADS)

    Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

    2017-09-01

    Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

  14. Smart programmable wireless microaccelerometers

    NASA Astrophysics Data System (ADS)

    Varadan, Vijay K.; Subramanian, Hareesh; Varadan, Vasundara V.

    1998-07-01

    The integration of MEMS, SAW devices and required microelectronics and conformal antenna to realize a programmable wireless accelerometer is presented in this paper. This unique combination of technologies results in a novel accelerometer that can be remotely sensed by a microwave system with the advantage of no power requirements at the sensor site. The microaccelerometer presented is simple in construction and easy to manufacture with existing silicon micromachining techniques. Programmable accelerometers can be achieved with splitfinger interdigital transducers (IDTs) as reflecting structures. If IDTs are short circuited or capacitively loaded, the wave propagates without any reflection whereas in an open circuit configuration, the IDTs reflect the incoming SAW signal. The programmable accelerometers can thus be achieved by using an external circuitry on a semiconductor chip using hybrid technology. The relatively small size of the sensor makes it an ideal conformal sensor. The accelerometer finds application as air bag deployment sensors, vibration sensors for noise control, deflection and strain sensors, inertial and dimensional positioning systems, ABS/traction control, smart suspension, active roll stabilization and four wheel steering. The wireless accelerometer is very attractive to study the response of a `dummy' in automobile crash test.

  15. Logical and pseudo-logical optical fibre networks based on two-state (binary) optical fibre sensors for industrial monitoring and control systems

    NASA Astrophysics Data System (ADS)

    Szczot, Feliks

    2005-09-01

    The possibilities of development of logical and pseudo-logical optical fibre networks for monitoring and control of equipment and industrial sites are presented. Such networks composed of simple binary attenuation and optical fibre communication lines may also be used as fast and reliable systems developing a final command signal - logical and/or pseudo-logical, depending or the architecture of network and the type of located sensors. They realise the process similar to standard electronic logical sets but use the optical signal directly on the monitored or controlled device. The analysis of serial and parallel networks was carried out in the "dark" mode detection. The examples of networks in power industry were presented where technical and economical merits of logical and pseudo-logical monitoring and controlling networks are clearly visible.

  16. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  17. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  18. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  19. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  20. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  1. [Vaccination programmes].

    PubMed

    Varela, M Carmen

    2009-01-01

    Immunization is a highly cost-effective intervention that saves many lives. Its objective is to control and eliminate vaccine-preventable diseases (when the characteristics of the disease and the vaccine make it possible), resulting in improvements in the health of the population. In Spain, the first vaccination schedule was introduced in 1975 and currently coverages > 95% are achieved in children aged < 2 years of age. Before deciding to introduce a vaccination programme in a community or country, a series of aspects should be considered, including the disease burden in the population, the effectiveness and safety of the vaccine, the changes in the dynamics of the infection when the vaccine is introduced, the cost-effectiveness of the vaccine, the theoretical potential of elimination/eradication of the disease and the existence of other preventive or therapeutic measures. Once the programme has been introduced it should be subject to evaluation, considering aspects such as the coverage, effectiveness, safety and the impact on the population. This work defines different vaccination strategies for three diseases for which efficacious and safe vaccines are available: hepatitis A, influenza and varicella.

  2. Logical stochastic resonance with correlated internal and external noises in a synthetic biological logic block

    NASA Astrophysics Data System (ADS)

    Dari, Anna; Kia, Behnam; Bulsara, Adi R.; Ditto, William L.

    2011-12-01

    Following the advent of synthetic biology, several gene networks have been engineered to emulate digital devices, with the ability to program cells for different applications. In this work, we adapt the concept of logical stochastic resonance to a synthetic gene network derived from a bacteriophage λ. The intriguing results of this study show that it is possible to build a biological logic block that can emulate or switch from the AND to the OR gate functionalities through externally tuning the system parameters. Moreover, this behavior and the robustness of the logic gate are underpinned by the presence of an optimal amount of random fluctuations. We extend our earlier work in this field, by taking into account the effects of correlated external (additive) and internal (multiplicative or state-dependent) noise. Results obtained through analytical calculations as well as numerical simulations are presented.

  3. Conditional Logic and Primary Children.

    ERIC Educational Resources Information Center

    Ennis, Robert H.

    Conditional logic, as interpreted in this paper, means deductive logic characterized by "if-then" statements. This study sought to investigate the knowledge of conditional logic possessed by primary children and to test their readiness to learn such concepts. Ninety students were designated the experimental group and participated in a…

  4. Optically programmable encoder based on light propagation in two-dimensional regular nanoplates.

    PubMed

    Li, Ya; Zhao, Fangyin; Guo, Shuai; Zhang, Yongyou; Niu, Chunhui; Zeng, Ruosheng; Zou, Bingsuo; Zhang, Wensheng; Ding, Kang; Bukhtiar, Arfan; Liu, Ruibin

    2017-04-07

    We design an efficient optically controlled microdevice based on CdSe nanoplates. Two-dimensional CdSe nanoplates exhibit lighting patterns around the edges and can be realized as a new type of optically controlled programmable encoder. The light source is used to excite the nanoplates and control the logical position under vertical pumping mode by the objective lens. At each excitation point in the nanoplates, the preferred light-propagation routes are along the normal direction and perpendicular to the edges, which then emit out from the edges to form a localized lighting section. The intensity distribution around the edges of different nanoplates demonstrates that the lighting part with a small scale is much stronger, defined as '1', than the dark section, defined as '0', along the edge. These '0' and '1' are the basic logic elements needed to compose logically functional devices. The observed propagation rules are consistent with theoretical simulations, meaning that the guided-light route in two-dimensional semiconductor nanoplates is regular and predictable. The same situation was also observed in regular CdS nanoplates. Basic theoretical analysis and experiments prove that the guided light and exit position follow rules mainly originating from the shape rather than material itself.

  5. Optically programmable encoder based on light propagation in two-dimensional regular nanoplates

    NASA Astrophysics Data System (ADS)

    Li, Ya; Zhao, Fangyin; Guo, Shuai; Zhang, Yongyou; Niu, Chunhui; Zeng, Ruosheng; Zou, Bingsuo; Zhang, Wensheng; Ding, Kang; Bukhtiar, Arfan; Liu, Ruibin

    2017-04-01

    We design an efficient optically controlled microdevice based on CdSe nanoplates. Two-dimensional CdSe nanoplates exhibit lighting patterns around the edges and can be realized as a new type of optically controlled programmable encoder. The light source is used to excite the nanoplates and control the logical position under vertical pumping mode by the objective lens. At each excitation point in the nanoplates, the preferred light-propagation routes are along the normal direction and perpendicular to the edges, which then emit out from the edges to form a localized lighting section. The intensity distribution around the edges of different nanoplates demonstrates that the lighting part with a small scale is much stronger, defined as ‘1’, than the dark section, defined as ‘0’, along the edge. These ‘0’ and ‘1’ are the basic logic elements needed to compose logically functional devices. The observed propagation rules are consistent with theoretical simulations, meaning that the guided-light route in two-dimensional semiconductor nanoplates is regular and predictable. The same situation was also observed in regular CdS nanoplates. Basic theoretical analysis and experiments prove that the guided light and exit position follow rules mainly originating from the shape rather than material itself.

  6. Fluidic-thermochromic display device

    NASA Technical Reports Server (NTRS)

    Grafstein, D.; Hilborn, E. H.

    1968-01-01

    Fluidic decoder and display device has low-power requirements for temperature control of thermochromic materials. An electro-to-fluid converter translates incoming electrical signals into pneumatics signal of sufficient power to operate the fluidic logic elements.

  7. Fuzzy logic program at SGS-Thomson

    NASA Astrophysics Data System (ADS)

    Pagni, Andrea; Poluzzi, Rinaldo; Rizzotto, GianGuido

    1993-12-01

    From its conception by Professor Lotfi A. Zadeh in the early '60s, Fuzzy Logic has slowly won acceptance, first in the academic world, then in industry. Its success is mainly due to the different perspective with which problems are tackled. Thanks to Fuzzy Logic we have moved from a numerical/analytical description to a quantitative/qualitative one. It is important to stress that this different perspective not only allows us to solve analysis/control problems at lower costs but can also allow otherwise insoluble problems to be solved at acceptable costs. Of course, it must be stressed that Fuzzy Systems cannot match the computational precision of traditional techniques but seek, instead, to find acceptable solutions in shorter times. Recognizing the enormous importance of fuzzy logic in the markets of the future, SGS-THOMSON intends to produce devices belonging to a new class of machines: Fuzzy Computational Machines. For this purpose a major research project has been established considering the architectural aspects and system implications of fuzzy logic, the development of dedicated VLSI components and supporting software.

  8. The Logic of Life

    NASA Astrophysics Data System (ADS)

    Pascal, Robert; Pross, Addy

    2016-11-01

    In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the `regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both `regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.

  9. The Logic of Life.

    PubMed

    Pascal, Robert; Pross, Addy

    2016-11-01

    In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the 'regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both 'regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.

  10. Development and applications of supersonic unsteady consistent aerodynamics for intering parallel wings: Programmer's manual

    NASA Technical Reports Server (NTRS)

    Paine, A. A.

    1972-01-01

    The computer program written in support of the problem to determine aerodynamic influence coefficients on parallel interfering wings is described. The information is geared to the programmer. It is sufficient to describe the program logic and the required peripheral storage.

  11. Flight dynamics analysis and simulation of heavy lift airships. Volume 5: Programmer's manual

    NASA Technical Reports Server (NTRS)

    Ringland, R. F.; Tischler, M. B.; Jex, H. R.; Emmen, R. D.; Ashkenas, I. L.

    1982-01-01

    The Programmer's Manual contains explanations of the logic embodied in the various program modules, a dictionary of program variables, a subroutine listing, subroutine/common block/cross reference listing, and a calling/called subroutine cross reference listing.

  12. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at preselected...

  13. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at preselected...

  14. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at preselected...

  15. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at preselected...

  16. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at preselected...

  17. The Logic of Occurrence

    DTIC Science & Technology

    1986-12-01

    determining the consequences of assumptions about the behavior of a system . If the space of behaviors is represented by an envisionment , many such...consequences can be represented by pruning states from the envisionment . This paper provides a formal logic of occurrence which justifies the...algorithms involved and provides a language for relating specific histories to envisionments . The concepts and axioms are general enough to be applicable to

  18. A molecular logic gate

    PubMed Central

    Kompa, K. L.; Levine, R. D.

    2001-01-01

    We propose a scheme for molecule-based information processing by combining well-studied spectroscopic techniques and recent results from chemical dynamics. Specifically it is discussed how optical transitions in single molecules can be used to rapidly perform classical (Boolean) logical operations. In the proposed way, a restricted number of states in a single molecule can act as a logical gate equivalent to at least two switches. It is argued that the four-level scheme can also be used to produce gain, because it allows an inversion, and not only a switching ability. The proposed scheme is quantum mechanical in that it takes advantage of the discrete nature of the energy levels but, we here discuss the temporal evolution, with the use of the populations only. On a longer time range we suggest that the same scheme could be extended to perform quantum logic, and a tentative suggestion, based on an available experiment, is discussed. We believe that the pumping can provide a partial proof of principle, although this and similar experiments were not interpreted thus far in our terms. PMID:11209046

  19. Distributed solid state programmable thermostat/power controller

    NASA Technical Reports Server (NTRS)

    Alexander, Jane C. (Inventor); Howard, David E. (Inventor); Smith, Dennis A. (Inventor)

    2008-01-01

    A self-contained power controller having a power driver switch, programmable controller, communication port, and environmental parameter measuring device coupled to a controllable device. The self-contained power controller needs only a single voltage source to power discrete devices, analog devices, and the controlled device. The programmable controller has a run mode which, when selected, upon the occurrence of a trigger event changes the state of a power driver switch and wherein the power driver switch is maintained by the programmable controller at the same state until the occurrence of a second event.

  20. Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar Array for Large-Scale Circuits.

    PubMed

    Huang, Peng; Kang, Jinfeng; Zhao, Yudi; Chen, Sijie; Han, Runze; Zhou, Zheng; Chen, Zhe; Ma, Wenjia; Li, Mu; Liu, Lifeng; Liu, Xiaoyan

    2016-11-01

    Resistance switching (RS) devices have potential to offer computing and memory function. A new computer unit is built of RS array, where processing and storing of information occur on same devices. Resistance states stored in devices located in arbitrary positions of RS array can be performed various nonvolatile logic operations. Logic functions can be reconfigured by altering trigger signals. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. Concrete Quantum Logics and Δ -Logics, States and Δ -States

    NASA Astrophysics Data System (ADS)

    Hroch, Michal; Pták, Pavel

    2017-04-01

    By a concrete quantum logic (in short, by a logic) we mean the orthomodular poset that is set-representable. If L=({Ω },L) is a logic and L is closed under the formation of symmetric difference, Δ , we call L a Δ -logic. In the first part we situate the known results on logics and states to the context of Δ -logics and Δ -states (the Δ -states are the states that are subadditive with respect to the symmetric difference). Moreover, we observe that the rather prominent logic E^{even}_{Ω } of all even-coeven subsets of the countable set Ω possesses only Δ -states. Then we show when a state on the logics given by the divisibility relation allows for an extension as a state. In the next paragraph we consider the so called density logic and its Δ -closure. We find that the Δ -closure coincides with the power set. Then we investigate other properties of the density logic and its factor.

  2. The JOSHUA (J80) system programmer`s manual

    SciTech Connect

    Smetana, A.O.; McCort, J.T.; Westmoreland, B.W.

    1993-08-01

    The JOSHUA system routines (JS routines) can be used to manage a JOSHUA data base and execute JOSHUA modules on VAX/VMS and IBM/MVS computer systems. This manual provides instructions for using the JS routines and information about the internal data structures and logic used by the routines. It is intended for use primarily by JOSHUA systems programmers, however, advanced applications programmers may also find it useful. The JS routines are, as far as possible, written in ANSI FORTRAN 77 so that they are easily maintainable and easily portable to different computer systems. Nevertheless, the JOSHUA system provides features that are not available in ANSI FORTRAN 77, notably dynamic module execution and a data base of named, variable length, unformatted records, so some parts of the routines are coded in nonstandard FORTRAN or assembler (as a last resort). In most cases, the nonstandard sections of code are different for each computer system. To make it easy for programmers using the JS routines to avoid naming conflicts, the JS routines and common block all have six character names that begin with the characters {open_quotes}JS.{close_quotes} Before using this manual, one should be familiar with the JOSHUA system as described in {open_quotes}The JOSHUA Users` Manual,{close_quotes} ANSI FORTRAN 77, and at least one of the computer systems for which the JS routines have been implemented.

  3. The evolvability of programmable hardware

    PubMed Central

    Raman, Karthik; Wagner, Andreas

    2011-01-01

    In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 1045 logic circuits (‘genotypes’) and 1019 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry. PMID:20534598

  4. Mathematical logic in the human brain: semantics.

    PubMed

    Friedrich, Roland M; Friederici, Angela D

    2013-01-01

    As a higher cognitive function in humans, mathematics is supported by parietal and prefrontal brain regions. Here, we give an integrative account of the role of the different brain systems in processing the semantics of mathematical logic from the perspective of macroscopic polysynaptic networks. By comparing algebraic and arithmetic expressions of identical underlying structure, we show how the different subparts of a fronto-parietal network are modulated by the semantic domain, over which the mathematical formulae are interpreted. Within this network, the prefrontal cortex represents a system that hosts three major components, namely, control, arithmetic-logic, and short-term memory. This prefrontal system operates on data fed to it by two other systems: a premotor-parietal top-down system that updates and transforms (external) data into an internal format, and a hippocampal bottom-up system that either detects novel information or serves as an access device to memory for previously acquired knowledge.

  5. Mathematical Logic in the Human Brain: Semantics

    PubMed Central

    Friedrich, Roland M.; Friederici, Angela D.

    2013-01-01

    As a higher cognitive function in humans, mathematics is supported by parietal and prefrontal brain regions. Here, we give an integrative account of the role of the different brain systems in processing the semantics of mathematical logic from the perspective of macroscopic polysynaptic networks. By comparing algebraic and arithmetic expressions of identical underlying structure, we show how the different subparts of a fronto-parietal network are modulated by the semantic domain, over which the mathematical formulae are interpreted. Within this network, the prefrontal cortex represents a system that hosts three major components, namely, control, arithmetic-logic, and short-term memory. This prefrontal system operates on data fed to it by two other systems: a premotor-parietal top-down system that updates and transforms (external) data into an internal format, and a hippocampal bottom-up system that either detects novel information or serves as an access device to memory for previously acquired knowledge. PMID:23301101

  6. Active matter logic for autonomous microfluidics

    PubMed Central

    Woodhouse, Francis G.; Dunkel, Jörn

    2017-01-01

    Chemically or optically powered active matter plays an increasingly important role in materials design, but its computational potential has yet to be explored systematically. The competition between energy consumption and dissipation imposes stringent physical constraints on the information transport in active flow networks, facilitating global optimization strategies that are not well understood. Here, we combine insights from recent microbial experiments with concepts from lattice-field theory and non-equilibrium statistical mechanics to introduce a generic theoretical framework for active matter logic. Highlighting conceptual differences with classical and quantum computation, we demonstrate how the inherent non-locality of incompressible active flow networks can be utilized to construct universal logical operations, Fredkin gates and memory storage in set–reset latches through the synchronized self-organization of many individual network components. Our work lays the conceptual foundation for developing autonomous microfluidic transport devices driven by bacterial fluids, active liquid crystals or chemically engineered motile colloids. PMID:28440273

  7. Logic gates based on ion transistors.

    PubMed

    Tybrandt, Klas; Forchheimer, Robert; Berggren, Magnus

    2012-05-29

    Precise control over processing, transport and delivery of ionic and molecular signals is of great importance in numerous fields of life sciences. Integrated circuits based on ion transistors would be one approach to route and dispense complex chemical signal patterns to achieve such control. To date several types of ion transistors have been reported; however, only individual devices have so far been presented and most of them are not functional at physiological salt concentrations. Here we report integrated chemical logic gates based on ion bipolar junction transistors. Inverters and NAND gates of both npn type and complementary type are demonstrated. We find that complementary ion gates have higher gain and lower power consumption, as compared with the single transistor-type gates, which imitates the advantages of complementary logics found in conventional electronics. Ion inverters and NAND gates lay the groundwork for further development of solid-state chemical delivery circuits.

  8. Active matter logic for autonomous microfluidics

    NASA Astrophysics Data System (ADS)

    Woodhouse, Francis G.; Dunkel, Jörn

    2017-04-01

    Chemically or optically powered active matter plays an increasingly important role in materials design, but its computational potential has yet to be explored systematically. The competition between energy consumption and dissipation imposes stringent physical constraints on the information transport in active flow networks, facilitating global optimization strategies that are not well understood. Here, we combine insights from recent microbial experiments with concepts from lattice-field theory and non-equilibrium statistical mechanics to introduce a generic theoretical framework for active matter logic. Highlighting conceptual differences with classical and quantum computation, we demonstrate how the inherent non-locality of incompressible active flow networks can be utilized to construct universal logical operations, Fredkin gates and memory storage in set-reset latches through the synchronized self-organization of many individual network components. Our work lays the conceptual foundation for developing autonomous microfluidic transport devices driven by bacterial fluids, active liquid crystals or chemically engineered motile colloids.

  9. The connection between logical and thermodynamic irreversibility

    NASA Astrophysics Data System (ADS)

    Ladyman, James; Presnell, Stuart; Short, Anthony J.; Groisman, Berry

    There has recently been a good deal of controversy about Landauer's Principle, which is often stated as follows: the erasure of one bit of information in a computational device is necessarily accompanied by a generation of kT ln 2 heat. This is often generalised to the claim that any logically irreversible operation cannot be implemented in a thermodynamically reversible way. Norton [2005. Eaters of the lotus: Landauer's principle and the return of Maxwell's demon. Studies in History and Philosophy of Modern Physics, 36, 375-411] and Maroney [2005. The (absence of a) relationship between thermodynamic and logical reversibility. Studies in History and Philosophy of Modern Physics, 36, 355-374] both argue that Landauer's Principle has not been shown to hold in general, and Maroney offers a method that he claims instantiates the operation Reset in a thermodynamically reversible way. In this paper we defend the qualitative form of Landauer's Principle, and clarify its quantitative consequences (assuming the second law of thermodynamics). We analyse in detail what it means for a physical system to implement a logical transformation L, and we make this precise by defining the notion of an L-machine. Then we show that logical irreversibility of L implies thermodynamic irreversibility of every corresponding L-machine. We do this in two ways. First, by assuming the phenomenological validity of the Kelvin statement of the second law, and second, by using information-theoretic reasoning. We illustrate our results with the example of the logical transformation 'Reset', and thereby recover the quantitative form of Landauer's Principle.

  10. Connectable DNA logic gates: OR and XOR logics.

    PubMed

    Gerasimova, Yulia V; Kolpashchikov, Dmitry M

    2012-03-05

    Modern computer processors are based on semiconductor logic gates connected to each other in complex circuits. This study contributes to the development of a new class of connectable logic gates made of DNA in which the transfer of oligonucleotide fragments as input/output signals occurs upon hybridization of DNA sequences. The DNA strands responsible for a logic function form associates containing immobile DNA four-way junction structures when the signal is high and dissociate into separate strands when the signal is low. A basic set of logic gates (NOT, AND, and OR) was designed. Two NOT gates, two AND gates, and an OR gate were connected in a network that corresponds to an XOR logic function. The design of the logic gates presented here may contribute to the development of the first biocompatible molecular computer. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  11. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    SciTech Connect

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-21

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  12. A reconfigurable NAND/NOR genetic logic gate

    PubMed Central

    2012-01-01

    Background Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. Results We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. Conclusions We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications. PMID:22989145

  13. A reconfigurable NAND/NOR genetic logic gate.

    PubMed

    Goñi-Moreno, Angel; Amos, Martyn

    2012-09-18

    Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.

  14. Novel Ferroelectric CMOS Circuits as a Nonvolatile Logic

    NASA Astrophysics Data System (ADS)

    Takahashi, M.; Horiuchi, T.; Li, Q.-H.; Wang, S.; Yun, K. Y.; Sakai, S.

    2008-03-01

    We propose a novel and promising nonvolatile-logic circuit constructed by p channel type (Pch) and n channel type (Nch) ferroelectric gate field effect transistors (FeFETs), which we named a ferroelectric CMOS (FeCMOS) circuit. The circuit works as both logic and memory. We fabricated a NOT logic FeCMOS device which have Pt metal gates and gate oxides of ferroelectric SrBi2Ta2O9 (SBT) and high-k HfAlO on Si. Key technology was adjusting threshold voltages of the FeFETs as well as preparing those of high quality. We demonstrate basic operations of the NOT-logic response, memory writing, holding and non-destructive reading. The memory writing is done by amplifying the input node voltage to a higher level when the node was logically high and to a lower one when it was logically low just before the writing operation. The data retention was also measured. The retained high and low voltages were almost unchanged for 1.2 days. The idea of this FeCMOS will enhance flexibility of circuit designing by merging logic and memory functions. This work was partially supported by NEDO.

  15. Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control.

    PubMed

    Geier, Michael L; Prabhumirashi, Pradyumna L; McMorrow, Julian J; Xu, Weichao; Seo, Jung-Woo T; Everaerts, Ken; Kim, Chris H; Marks, Tobin J; Hersam, Mark C

    2013-10-09

    In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

  16. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

    NASA Astrophysics Data System (ADS)

    Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.

    2016-01-01

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.

  17. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

    PubMed Central

    Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.

    2016-01-01

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412

  18. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls.

    PubMed

    Currivan-Incorvia, J A; Siddiqui, S; Dutta, S; Evarts, E R; Zhang, J; Bono, D; Ross, C A; Baldo, M A

    2016-01-12

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.

  19. Logical empiricists on race.

    PubMed

    Bright, Liam Kofi

    2017-07-10

    The logical empiricists expressed a consistent attitude to racial categorisation in both the ethical and scientific spheres. Their attitude may be captured in the following slogan: human racial taxonomy is an empirically meaningful mode of classifying persons that we should refrain from deploying. I offer an interpretation of their position that would render coherent their remarks on race with positions they adopted on the scientific status of taxonomy in general, together with their potential moral or political motivations for adopting that position. Copyright © 2017. Published by Elsevier Ltd.

  20. Gallium arsenide processing for gate array logic

    NASA Astrophysics Data System (ADS)

    Cole, Eric D.

    1989-09-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  1. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  2. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  3. Rapidly Reconfigurable All-Optical Universal Logic Gates

    SciTech Connect

    Goddard, L L; Kallman, J S; Bond, T C

    2006-06-21

    We present designs and simulations for a highly cascadable, rapidly reconfigurable, all-optical, universal logic gate. We will discuss the gate's expected performance, e.g. speed, fanout, and contrast ratio, as a function of the device layout and biasing conditions. The gate is a three terminal on-chip device that consists of: (1) the input optical port, (2) the gate selection port, and (3) the output optical port. The device can be built monolithically using a standard multiple quantum well graded index separate confinement heterostructure laser configuration. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog electrical or optical signal at the gate selection port. Specifically, the same gate can be selected to execute one of the 2 basic unary operations (NOT or COPY), or one of the 6 binary operations (OR, XOR, AND, NOR, XNOR, or NAND), or one of the many logic operations involving more than two inputs. The speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal modulation speed of a laser, which can be on the order of tens of GHz. The reprogrammable nature of the universal gate offers maximum flexibility and interchangeability for the end user since the entire application of a photonic integrated circuit built from cascaded universal logic gates can be changed simply by adjusting the gate selection port signals.

  4. A single nano cantilever as a reprogrammable universal logic gate

    NASA Astrophysics Data System (ADS)

    Chappanda, K. N.; Ilyas, S.; Kazmi, S. N. R.; Holguin-Lerma, J.; Batra, N. M.; Costa, P. M. F. J.; Younis, M. I.

    2017-04-01

    The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.

  5. A Very Small Logical Qubit

    NASA Astrophysics Data System (ADS)

    Kapit, Eliot

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven SQUID couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multi-qubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of forty or more compared to the individual qubit T1 and T2 using this technique.

  6. Construction of a fuzzy and Boolean logic gates based on DNA.

    PubMed

    Zadegan, Reza M; Jepsen, Mette D E; Hildebrandt, Lasse L; Birkedal, Victoria; Kjems, Jørgen

    2015-04-17

    Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. Barriers in Concurrent Separation Logic

    NASA Astrophysics Data System (ADS)

    Hobor, Aquinas; Gherghina, Cristian

    We develop and prove sound a concurrent separation logic for Pthreads-style barriers. Although Pthreads barriers are widely used in systems, and separation logic is widely used for verification, there has not been any effort to combine the two. Unlike locks and critical sections, Pthreads barriers enable simultaneous resource redistribution between multiple threads and are inherently stateful, leading to significant complications in the design of the logic and its soundness proof. We show how our logic can be applied to a specific example program in a modular way. Our proofs are machine-checked in Coq.

  8. An SEU immune logic family

    NASA Technical Reports Server (NTRS)

    Canaris, J.

    1991-01-01

    A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.

  9. Programmer's manual for the Banning artwork program

    NASA Technical Reports Server (NTRS)

    Taylor, J. F.

    1970-01-01

    The document is intended to serve as the programmer's Manual for the Banning Artwork Program. A detailed description of the internal logic and flow of the Artwork Program has been included in this report. It is recommended that every user review this manual in order to receive an appreciation of the functions performed by the Artwork Program; however, the User's Manual for the Artwork Program contains sufficient information to allow the designer/engineer to efficiently use the Artwork Program. Before beginning a detailed study of this Programmer's Manual, the reader should have a complete understanding of the contents of the User's Manual for the Banning Artwork Program. It is assumed that the programmer using this manual has a working knowledge of FORTRAN IV.

  10. Making programmable BMS safe and reliable

    SciTech Connect

    Cusimano, J.A.

    1995-12-01

    Burner management systems ensure safe admission of fuel to the furnace and prevent explosions. This article describes how programmable control systems can be every bit as safe and reliable as hardwired or standard programmable logic controller-based designs. High-pressure boilers are required by regulatory agencies and insurance companies alike to be equipped with a burner management system (BMS) to ensure safe admission of fuel to the furnace and to prevent explosions. These systems work in parallel with, but independently of, the combustion and feedwater control systems that start up, monitor, and shut down burners and furnaces. Safety and reliability are the fundamental requirements of a BMS. Programmable control system for BMS applications are now available that incorporate high safety and reliability into traditional microprocessor-based designs. With one of these control systems, a qualified systems engineer applying relevant standards, such as the National Fire Protection Assn (NFPA) 85 series, can design and implement a superior BMS.

  11. Surface-confined assemblies and polymers for molecular logic.

    PubMed

    de Ruiter, Graham; van der Boom, Milko E

    2011-08-16

    Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the

  12. A programmable video image remapper

    NASA Technical Reports Server (NTRS)

    Fisher, Timothy E.; Juday, Richard D.

    1988-01-01

    NASA's Johnson Space Center (JSC) has created the specifications for a new kind of image processing machine, a video-rate coordinate remapper. Previous image-processing machines for machine vision typically have done point operations without changing the geometry of the image. The JSC Programmable Remapper offers complete flexibility in changing the coordinates of an input image at video rates. Presented here are the main capabilities and some of the applications of such a device.

  13. Application of digital pulse delay device in range-gated control for range-gated imaging lidar

    NASA Astrophysics Data System (ADS)

    Yuan, Chaokai; Chen, Siying; Zhang, Yinchao; Qiu, Zongjia; Ni, Guoqiang

    2009-11-01

    Digital pulse delay device is one of the key techniques of range-gated imaging lidar. At present, Digital method and analog method are the two main implementations of pulse delay device. Digital method is mainly achieved by counter or FIFO memory. With the development of Complex Programmable Logic Device (CPLD), the digital delay device can be achieved with a single chip of CPLD. With this method, the digital delay device enjoys the advantages of high integration, high reliability and strong ability of anti-electromagnetic interference. However, since the maximum clock frequency of CPLD is limited, the improvement of temporal resolution is restricted. Analog method is mainly realized by the delay-line, which is one of the dedicated integrated circuit. Using this method, a higher time resolution can be arrived. In this paper, the timing characteristics of the delay signal are analyzed. Three design options are presented and the advantages and deficiencies are discussed. Based on the theoretical analysis and numerical simulation, the digital delay device combined with the delay chip AD9501 and Field Programmable Gate Array (FPGA) is chosen because of its large dynamic range and high accuracy. Besides, the output pulse width can be adjusted conveniently. The digital delay device is simulated and the result shows that the delay control for range-gated imaging lidar is feasible.

  14. Parsing with logical variables (logic-based programming systems)

    SciTech Connect

    Finin, T.W.; Stone Palmer, M.

    1983-01-01

    Logic based programming systems have enjoyed an increasing popularity in applied AI work in the last few years. One of the contributions to computational linguistics made by the logic programming paradigm has been the definite clause grammar. In comparing DCGS with previous parsing mechanisms such as ATNS, certain clear advantages are seen. The authors feel that the most important of these advantages are due to the use of logical variables with unification as the fundamental operation on them. To illustrate the power of the logical variable, they have implemented an experimental atn system which treats atn registers as logical variables and provides a unification operation over them. They aim to simultaneously encourage the use of the powerful mechanisms available in DCGS and demonstrate that some of these techniques can be captured without reference to a resolution theorem prover. 14 references.

  15. The cognitive bases for the design of a new class of fuzzy logic controllers: The clearness transformation fuzzy logic controller

    NASA Technical Reports Server (NTRS)

    Sultan, Labib; Janabi, Talib

    1992-01-01

    This paper analyses the internal operation of fuzzy logic controllers as referenced to the human cognitive tasks of control and decision making. Two goals are targeted. The first goal focuses on the cognitive interpretation of the mechanisms employed in the current design of fuzzy logic controllers. This analysis helps to create a ground to explore the potential of enhancing the functional intelligence of fuzzy controllers. The second goal is to outline the features of a new class of fuzzy controllers, the Clearness Transformation Fuzzy Logic Controller (CT-FLC), whereby some new concepts are advanced to qualify fuzzy controllers as 'cognitive devices' rather than 'expert system devices'. The operation of the CT-FLC, as a fuzzy pattern processing controller, is explored, simulated, and evaluated.

  16. Program to Optimize Simulated Trajectories (POST). Volume 3: Programmer's manual

    NASA Technical Reports Server (NTRS)

    Brauer, G. L.; Cornick, D. E.; Habeger, A. R.; Petersen, F. M.; Stevenson, R.

    1975-01-01

    Information pertinent to the programmer and relating to the program to optimize simulated trajectories (POST) is presented. Topics discussed include: program structure and logic, subroutine listings and flow charts, and internal FORTRAN symbols. The POST core requirements are summarized along with program macrologic.

  17. Reversible logic gates on Physarum Polycephalum

    SciTech Connect

    Schumann, Andrew

    2015-03-10

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.

  18. IC Piracy Protection by APUF and Logic Obfuscation

    DTIC Science & Technology

    2014-01-01

    performance due to Vth shift by hot carrier injection (HCI) and negative bias temperature instability (NBTI). Vth of devices is continuously increased as...13 3.2.5.3 Runtime temperature difference between two cores .................................. 13 3.2.6 Implementation overhead...voltage and temperature fluctuations), error correction logic overhead is inevitable, yet desired to be reduced. Moreover, natural PUFs may have

  19. Mechanically Flexible and High-Performance CMOS Logic Circuits.

    PubMed

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-10-13

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

  20. Confinement-modulated junctionless nanowire transistors for logic circuits.

    PubMed

    Vaurette, François; Leturcq, Renaud; Lepilliet, Sylvie; Grandidier, Bruno; Stiévenard, Didier

    2014-11-21

    We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of the current in the nanowire. The constrictions act as potential barriers and the height of the barriers can be selectively tuned by gates, making the device concept compatible with the crossbar geometry in order to create logic circuits. The functionality of the architecture and the reliability of the fabrication process are demonstrated by designing decoder devices.

  1. Quantificational logic of context

    SciTech Connect

    Buvac, Sasa

    1996-12-31

    In this paper we extend the Propositional Logic of Context, to the quantificational (predicate calculus) case. This extension is important in the declarative representation of knowledge for two reasons. Firstly, since contexts are objects in the semantics which can be denoted by terms in the language and which can be quantified over, the extension enables us to express arbitrary first-order properties of contexts. Secondly, since the extended language is no longer only propositional, we can express that an arbitrary predicate calculus formula is true in a context. The paper describes the syntax and the semantics of a quantificational language of context, gives a Hilbert style formal system, and outlines a proof of the system`s completeness.

  2. A Logical Process Calculus

    NASA Technical Reports Server (NTRS)

    Cleaveland, Rance; Luettgen, Gerald; Bushnell, Dennis M. (Technical Monitor)

    2002-01-01

    This paper presents the Logical Process Calculus (LPC), a formalism that supports heterogeneous system specifications containing both operational and declarative subspecifications. Syntactically, LPC extends Milner's Calculus of Communicating Systems with operators from the alternation-free linear-time mu-calculus (LT(mu)). Semantically, LPC is equipped with a behavioral preorder that generalizes Hennessy's and DeNicola's must-testing preorder as well as LT(mu's) satisfaction relation, while being compositional for all LPC operators. From a technical point of view, the new calculus is distinguished by the inclusion of: (1) both minimal and maximal fixed-point operators and (2) an unimple-mentability predicate on process terms, which tags inconsistent specifications. The utility of LPC is demonstrated by means of an example highlighting the benefits of heterogeneous system specification.

  3. Simulated Laboratory in Digital Logic.

    ERIC Educational Resources Information Center

    Cleaver, Thomas G.

    Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

  4. Simulated Laboratory in Digital Logic.

    ERIC Educational Resources Information Center

    Cleaver, Thomas G.

    Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

  5. Japanese Logic Puzzles and Proof

    ERIC Educational Resources Information Center

    Wanko, Jeffrey J.

    2009-01-01

    An understanding of proof does not start in a high school geometry course. Rather, attention to logical reasoning throughout a student's school experience can help the development of proof readiness. In the spirit of problem solving, the author has begun to use some Japanese logic puzzles other than sudoku to help students develop additional…

  6. Logic, Probability, and Human Reasoning

    DTIC Science & Technology

    2015-01-01

    multiplication, it needs a working memory to hold intermediate results. Syllogism: a form of inference that Aristotle formulated based on two premises and a...where knowledge itself takes the form of fully Box 1. The application of p-logic to syllogistic reasoning Aristotle formulated the logic of syllogisms

  7. Logic, reasoning, and verbal behavior

    PubMed Central

    Terrell, Dudley J.; Johnston, J. M.

    1989-01-01

    This paper analyzes the traditional concepts of logic and reasoning from the perspective of radical behaviorism and in the terms of Skinner's treatment of verbal behavior. The topics covered in this analysis include the proposition, premises and conclusions, logicality and rules, and deductive and inductive reasoning. PMID:22478015

  8. Logic and the National Curriculum.

    ERIC Educational Resources Information Center

    Nelson, David

    2000-01-01

    Reviews the historic relationship between logic and the mathematics curriculum. Proposes a list of logical elements for modern school mathematics. Checks the current national curriculum against this list and finds it to be deficient, especially in relation to the development of ideas of proof. Presents arguments for reform. (Contains 29…

  9. Binary logic is rich enough

    SciTech Connect

    Zapatrin, R.R.

    1992-02-01

    Given a finite ortholattice L, the *-semigroup is explicitly built whose annihilator ortholattice is isomorphic to L. Thus, it is shown that any finite quantum logic is the additive part of a binary logic. Some areas of possible applications are outlined. 7 refs.

  10. MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic

    NASA Astrophysics Data System (ADS)

    Jaiswal, Akhilesh; Roy, Kaushik

    2017-01-01

    In the quest for novel, scalable and energy-efficient computing technologies, many non-charge based logic devices are being explored. Recent advances in multi-ferroic materials have paved the way for electric field induced low energy and fast switching of nano-magnets using the magneto-electric (ME) effect. In this paper, we propose a voltage driven logic-device based on the ME induced switching of nano-magnets. We further demonstrate that the proposed logic-device, which exhibits decoupled read and write paths, can be used to construct a complete logic family including XNOR, NAND and NOR gates. The proposed logic family shows good scalability with a quadratic dependence of switching energy with respect to the switching voltage. Further, the proposed logic-device has better robustness against the effect of thermal noise as compared to the conventional current driven switching of nano-magnets. A device-to-circuit level coupled simulation framework, including magnetization dynamics and electron transport model, has been developed for analyzing the present proposal. Using our simulation framework, we present energy and delay results for the proposed Magneto-Electric Spin Logic (MESL) gates.

  11. MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic

    PubMed Central

    Jaiswal, Akhilesh; Roy, Kaushik

    2017-01-01

    In the quest for novel, scalable and energy-efficient computing technologies, many non-charge based logic devices are being explored. Recent advances in multi-ferroic materials have paved the way for electric field induced low energy and fast switching of nano-magnets using the magneto-electric (ME) effect. In this paper, we propose a voltage driven logic-device based on the ME induced switching of nano-magnets. We further demonstrate that the proposed logic-device, which exhibits decoupled read and write paths, can be used to construct a complete logic family including XNOR, NAND and NOR gates. The proposed logic family shows good scalability with a quadratic dependence of switching energy with respect to the switching voltage. Further, the proposed logic-device has better robustness against the effect of thermal noise as compared to the conventional current driven switching of nano-magnets. A device-to-circuit level coupled simulation framework, including magnetization dynamics and electron transport model, has been developed for analyzing the present proposal. Using our simulation framework, we present energy and delay results for the proposed Magneto-Electric Spin Logic (MESL) gates. PMID:28045074

  12. Emergent programme theories of a national quality register - a longitudinal study in Swedish elderly care.

    PubMed

    Nordin, Annika; Andersson Gäre, Boel; Andersson, Ann-Christine

    2017-07-27

    This study aimed to explore programme theories of a national quality register. A programme theory is a bundle of assumptions underpinning how and why an improvement initiative functions. The purpose was to examine and establish programme theories of a national quality register widely used in Sweden: Senior alert. The paper reports on how programme theories among change recipients emerge in relation to the established programme theory of the initiator. A qualitative approach and a longitudinal research design were used. To develop programme theories among change recipients, individual semistructured interviews were conducted. Three sets of interviews were conducted in the period of 2011 to 2013, totalling 22 interviews. In addition, 4 participant observations were made. To develop the initiator's programme theory, an iterative multistage collaboration process between the researchers and the initiator was used. A directed content analysis was used to analyse data. The initiator and change recipients described similar programme logics, but differing programme theories. With time, change recipients' programme theories emerged. Their programme theories converged and became more like the programme theory of the initiator. This study has demonstrated the importance of making both the initiator's and change recipients' programme theories explicit. To learn about conditions for improvement initiatives, comparisons between their programme theories are valuable. Differences in programme theories provide information on how initiators can customize support for their improvement initiatives. Similar programme logics can be underpinned by different programme theories, which can be deceptive. Programme theories emerge over time and need to be understood as dynamic phenomena. © 2017 The Authors Journal of Evaluation in Clinical Practice Published by John Wiley & Sons Ltd.

  13. Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures

    NASA Technical Reports Server (NTRS)

    Rickard, D. A.; Bodenheimer, R. E.

    1976-01-01

    Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.

  14. Power optimization in logic isomers

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.

  15. Weighted Automata and Weighted Logics

    NASA Astrophysics Data System (ADS)

    Droste, Manfred; Gastin, Paul

    In automata theory, a fundamental result of Büchi and Elgot states that the recognizable languages are precisely the ones definable by sentences of monadic second order logic. We will present a generalization of this result to the context of weighted automata. We develop syntax and semantics of a quantitative logic; like the behaviors of weighted automata, the semantics of sentences of our logic are formal power series describing ‘how often’ the sentence is true for a given word. Our main result shows that if the weights are taken in an arbitrary semiring, then the behaviors of weighted automata are precisely the series definable by sentences of our quantitative logic. We achieve a similar characterization for weighted Büchi automata acting on infinite words, if the underlying semiring satisfies suitable completeness assumptions. Moreover, if the semiring is additively locally finite or locally finite, then natural extensions of our weighted logic still have the same expressive power as weighted automata.

  16. Realization of morphing logic gates in a repressilator with quorum sensing feedback

    NASA Astrophysics Data System (ADS)

    Agrawal, Vidit; Kang, Shivpal Singh; Sinha, Sudeshna

    2014-03-01

    We demonstrate how a genetic ring oscillator network with quorum sensing feedback can operate as a robust logic gate. Specifically we show how a range of logic functions, namely AND/NAND, OR/NOR and XOR/XNOR, can be realized by the system, thus yielding a versatile unit that can morph between different logic operations. We further demonstrate the capacity of this system to yield complementary logic operations in parallel. Our results then indicate the computing potential of this biological system, and may lead to bio-inspired computing devices.

  17. Develop reusable and combinable designs for transcriptional logic gates.

    PubMed

    Zhan, Jian; Ding, Bo; Ma, Rui; Ma, Xiaoyu; Su, Xiaofeng; Zhao, Yun; Liu, Ziqing; Wu, Jiarui; Liu, Haiyan

    2010-07-13

    One limit on developing complex synthetic gene circuits is the lack of basic components such as transcriptional logic gates that can process combinatorial inputs. Here, we propose a strategy to construct such components based on reusable designs and convergent reengineering of well-studied natural systems. We demonstrated the strategy using variants of the transcription factor (TF) LacI and operator Olac that form specifically interacting pairs. Guided by a mathematical model derived from existing quantitative knowledge, rational designs of transcriptional NAND, NOR and NOT gates have been realized. The NAND gates have been designed based on direct protein-protein interactions in coupling with DNA looping. We demonstrated that the designs are reusable: a multiplex of logic devices can be readily created using the same designs but different combinations of sequence variants. The designed logic gates are combinable to form compound circuits: a demonstration logic circuit containing all three types of designed logic gates has been synthesized, and the circuit truthfully reproduces the pre-designed input-output logic relations.

  18. N channel JFET based digital logic gate structure

    NASA Technical Reports Server (NTRS)

    Krasowski, Michael J. (Inventor)

    2010-01-01

    A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

  19. Computerized logic design of digital circuits

    NASA Technical Reports Server (NTRS)

    Gussow, S.; Oglesby, R.

    1974-01-01

    Procedure performs all work required for logic design of digital counters or sequential circuits and simplification of Boolean expressions. Program provides simple, accurate, and comprehensive logic design capability to users both experienced and totally inexperienced in logic design

  20. LSI/VLSI (Large Scale Integration/Very Large Scale Integration) ion implanted GaAs (Gallium Arsenide) IC processing. Appendix B: Two-dimensional modeling of GaAs MESFET devices for integrated high-speed logic circuits

    NASA Astrophysics Data System (ADS)

    Zucca, R. R.; Kirkpatrick, C. G.; Asbeck, P. M.; Eisen, F. H.; Lee, C. P.

    1984-01-01

    This report summarizes the research carried out at North Carolina State University in support of the Rockwell International Program on LSI-VLSI Ion Implanted Planar GaAs IC Processing. The major thrust of the program at NCSU was to develop accurate computer models for analyzing the performance of short-channel GaAs MESFET devices as used in the Rockwell VLSI circuits. The modeling research is divided into three parts: (1) Two-dimensional finite difference simulation, (2) Two-dimensional Monte Carlo analysis, and (3) Analytical modeling. The intent was to use the two-dimensional analyses to give exact solutions to the device operation and to serve as a guide for developing a simpler, and less expensive, analytical model of sufficient accuracy to be valuable as a design aid and to study effects of parameter changes.