Science.gov

Sample records for radhard soi technology

  1. Study of proton radiation effects on analog IC designed for high energy physics in a BICMOS-JFET radhard SOI technology

    SciTech Connect

    Blanquart, L.; Delpierre, P.; Habrard, M.C.

    1994-12-01

    The authors present experimental results from a fast charge amplifier and a wideband analog buffer processed in the DMILL BiCMOS-JFET radhard SOI technology and irradiated up to 4.5 {times} 10{sup 14} protons/cm{sup 2}. In parallel, they have irradiated elementary transistors. These components were biased and electrical measurements were done 30 min after beam stop. By evaluating variations of main SPICE parameters, i.e., threshold voltage shift for CMOS and current gain variation for bipolar transistors, they have simulated the wideband analog buffer at different doses. These SPICE simulations are in good agreement with measured circuit degradations. The behavior of the charge amplifier is consistent with extraction of transconductance and pinch-off voltage shift of the PJFET.

  2. Advanced monolithic pixel sensors using SOI technology

    NASA Astrophysics Data System (ADS)

    Miyoshi, Toshinobu; Arai, Yasuo; Asano, Mari; Fujita, Yowichi; Hamasaki, Ryutaro; Hara, Kazuhiko; Honda, Shunsuke; Ikegami, Yoichi; Kurachi, Ikuo; Mitsui, Shingo; Nishimura, Ryutaro; Tauchi, Kazuya; Tobita, Naoshi; Tsuboyama, Toru; Yamada, Miho

    2016-07-01

    We are developing advanced pixel sensors using silicon-on-insulator (SOI) technology. A SOI wafer is used; top silicon is used for electric circuit and bottom silicon is used as a sensor. Target applications are high-energy physics, X-ray astronomy, material science, non-destructive inspection, medical application and so on. We have developed two integration-type pixel sensors, FPIXb and INTPIX7. These sensors were processed on single SOI wafers with various substrates in n- or p-type and double SOI wafers. The development status of double SOI sensors and some up-to-date test results of n-type and p-type SOI sensors are shown.

  3. Measurement results of DIPIX pixel sensor developed in SOI technology

    NASA Astrophysics Data System (ADS)

    Ahmed, Mohammed Imran; Arai, Yasuo; Idzik, Marek; Kapusta, Piotr; Miyoshi, Toshinobu; Turala, Michal

    2013-08-01

    The development of integration type pixel detectors presents interest for physics communities because it brings optimization of design, simplicity of production-which means smaller cost, and reduction of detector material budget. During the last decade a lot of research and development activities took place in the field of CMOS Silicon-On-Insulator (SOI) technology resulting in improvement in wafer size, wafer resistivity and MIM capacitance. Several ideas have been tested successfully and are gradually entering into the application phase. Some of the novel concepts exploring SOI technology are pursued at KEK; several prototypes of dual mode integration type pixel (DIPIX) have been recently produced and described. This report presents initial test results of some of the prototypes including tests obtained with the infrared laser beams and Americium (Am-241) source. The Equivalent Noise Charge (ENC) of 86 e - has been measured. The measured performance demonstrates that SOI technology is a feasible choice for future applications.

  4. A Wide Range Temperature Sensor Using SOI Technology

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Elbuluk, Malik E.; Hammoud, Ahmad

    2009-01-01

    Silicon-on-insulator (SOI) technology is becoming widely used in integrated circuit chips for its advantages over the conventional silicon counterpart. The decrease in leakage current combined with lower power consumption allows electronics to operate in a broader temperature range. This paper describes the performance of an SOIbased temperature sensor under extreme temperatures and thermal cycling. The sensor comprised of a temperature-to-frequency relaxation oscillator circuit utilizing an SOI precision timer chip. The circuit was evaluated under extreme temperature exposure and thermal cycling between -190 C and +210 C. The results indicate that the sensor performed well over the entire test temperature range and it was able to re-start at extreme temperatures.

  5. Monolithic pixel detectors with 0.2 μm FD-SOI pixel process technology

    NASA Astrophysics Data System (ADS)

    Miyoshi, Toshinobu; Arai, Yasuo; Chiba, Tadashi; Fujita, Yowichi; Hara, Kazuhiko; Honda, Shunsuke; Igarashi, Yasushi; Ikegami, Yoichi; Ikemoto, Yukiko; Kohriki, Takashi; Ohno, Morifumi; Ono, Yoshimasa; Shinoda, Naoyuki; Takeda, Ayaki; Tauchi, Kazuya; Tsuboyama, Toru; Tadokoro, Hirofumi; Unno, Yoshinobu; Yanagihara, Masashi

    2013-12-01

    Truly monolithic pixel detectors were fabricated with 0.2 μm SOI pixel process technology by collaborating with LAPIS Semiconductor Co., Ltd. for particle tracking experiment, X-ray imaging and medical applications. CMOS circuits were fabricated on a thin SOI layer and connected to diodes formed in the silicon handle wafer through the buried oxide layer. We can choose the handle wafer and therefore high-resistivity silicon is also available. Double SOI (D-SOI) wafers fabricated from Czochralski (CZ)-SOI wafers were newly obtained and successfully processed in 2012. The top SOI layers are used as electric circuits and the middle SOI layers used as a shield layer against the back-gate effect and cross-talk between sensors and CMOS circuits, and as an electrode to compensate for the total ionizing dose (TID) effect. In 2012, we developed two SOI detectors, INTPIX5 and INTPIX3g. A spatial resolution study was done with INTPIX5 and it showed excellent performance. The TID effect study with D-SOI INTPIX3g detectors was done and we confirmed improvement of TID tolerance in D-SOI sensors.

  6. Mongoose: Creation of a Rad-Hard MIPS R3000

    NASA Technical Reports Server (NTRS)

    Lincoln, Dan; Smith, Brian

    1993-01-01

    This paper describes the development of a 32 Bit, full MIPS R3000 code-compatible Rad-Hard CPU, code named Mongoose. Mongoose progressed from contract award, through the design cycle, to operational silicon in 12 months to meet a space mission for NASA. The goal was the creation of a fully static device capable of operation to the maximum Mil-883 derated speed, worst-case post-rad exposure with full operational integrity. This included consideration of features for functional enhancements relating to mission compatibility and removal of commercial practices not supported by Rad-Hard technology. 'Mongoose' developed from an evolution of LSI Logic's MIPS-I embedded processor, LR33000, code named Cobra, to its Rad-Hard 'equivalent', Mongoose. The term 'equivalent' is used to infer that the core of the processor is functionally identical, allowing the same use and optimizations of the MIPS-I Instruction Set software tool suite for compilation, software program trace, etc. This activity was started in September of 1991 under a contract from NASA-Goddard Space Flight Center (GSFC)-Flight Data Systems. The approach affected a teaming of NASA-GSFC for program development, LSI Logic for system and ASIC design coupled with the Rad-Hard process technology, and Harris (GASD) for Rad-Hard microprocessor design expertise. The program culminated with the generation of Rad-Hard Mongoose prototypes one year later.

  7. Integrated Optical Switch Based on SOI-Technology

    NASA Astrophysics Data System (ADS)

    Aalto, T.; Heimala, P.; Katila, P.

    An integrated optical thermo-optic switch has been designed using silicon-on-insulator (SOI) waveguide technology. The switch consists of two cascaded waveguide couplers with thermo-optic heaters on the waveguide arms connecting the two couplers. A detailed modelling of the optical and thermal operation of the switch has been made. A single-mode ridge waveguide structure with large cross-section was designed. The fibre-waveguide mode coupling loss was calculated to be 0.6dB. According to the thermal modelling, a 3K temperature change is enough to switch the output state of the device. The switching time is expected to be 0.2ms and the electrical power consumption 120mW.

  8. High gain CMOS image sensor design and fabrication on SOI and bulk technology

    NASA Astrophysics Data System (ADS)

    Zhang, Weiquan

    2000-12-01

    The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

  9. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

    NASA Astrophysics Data System (ADS)

    Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

    2016-01-01

    We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

  10. Nonvolatile Rad-Hard Holographic Memory

    NASA Technical Reports Server (NTRS)

    Chao, Tien-Hsin; Zhou, Han-Ying; Reyes, George; Dragoi, Danut; Hanna, Jay

    2001-01-01

    We are investigating a nonvolatile radiation-hardened (rad-hard) holographic memory technology. Recently, a compact holographic data storage (CHDS) breadboard utilizing an innovative electro-optic scanner has been built and demonstrated for high-speed holographic data storage and retrieval. The successful integration of this holographic memory breadboard has paved the way for follow-on radiation resistance test of the photorefractive (PR) crystal, Fe:LiNbO3. We have also started the investigation of using two-photon PR crystals that are doubly doped with atoms of iron group (Ti, Cr, Mn, Cu) and of rare-earth group (Nd, Tb) for nonvolatile holographic recordings.

  11. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    NASA Technical Reports Server (NTRS)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  12. Special Issue: Planar Fully-Depleted SOI technology

    NASA Astrophysics Data System (ADS)

    Allibert, F.; Hiramoto, T.; Nguyen, B. Y.

    2016-03-01

    We are in the era of mobile computing with smart handheld devices and remote data storage "in the cloud," with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer mobile and wearable markets. The Fully-Depleted SOI device/circuit is a unique option that can satisfy all these requirements and has made tremendous progress in development for various applications and adoption by foundries, integrated device manufacturers (IDM), and fabless companies in the last 3 years.

  13. Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

    NASA Technical Reports Server (NTRS)

    DeGregorio, Kelly; Wilson, Dale G.

    2009-01-01

    Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand

  14. Study of silicon-germanium junction formation for SOI based CMOS technology

    NASA Astrophysics Data System (ADS)

    Du, Yan

    Si1-xGex source/drain technology has been sucessfully applied to bulk metal oxide semiconductor field effect transistors (MOSFETs). Both channel mobility and source/drain contact resistivity are substantially improved with this technology. In this dissertation, Si1-xGex junction formation for silicon on insulator (SOI) based CMOS technology was investigated. Strain in epitaxially grown films on SOI films and silicon nanowires is studied using Raman spectroscopy and transmission electron microscope (TEM). For epitaxially grown Si1-xGe x film on SOI, there is lower degree of strain development in the SOI layer due to the rigid interface between the SOI and the burried oxide as compared to bulk. However, for silicon nanowires on oxide, the situation is different since nanowires serve as compliant substrates. Part of the strain energy is transferred to silicon nanowires. The consistency between synthesized Raman peak shifts and the experimental measurements verified the strain sharing between the epitaxially grown Si1-xGe x films and the silicon nanowires. Splittings of high order Laue zone line (HOLZ) from a convergent beam electron diffraction (CBED) pattern was quantified to study the strain distribution in epitaxial Si1- xGex films grown on silicon nanowires. It was found out in this study that elastic deformation of epitaxial Si 1-xGex at free surfaces leads to strain relaxation at these surfaces. This phenomenon is detrimental to strain engineering in a nanowire MOSFET and provides new challenges to develop smart designs for constraining strain in the nano-structures. Moreover, atomic layer deposition (ALD) Platinum is proposed for metal deposition on 3D epitaxial Si1-xGex source/drain. The uniform deposition around 3D Si1- xGex films effectively increases the contact surface area which is highly desired in the FinFET application.

  15. Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology

    NASA Technical Reports Server (NTRS)

    Ned, Alex; Kurtz, Anthony; Shang, Tonghuo; Goodman, Scott; Giemette. Gera (d)

    2013-01-01

    This work focused on developing, fabricating, and fully calibrating a flowangle probe for aeronautics research by utilizing the latest microelectromechanical systems (MEMS), leadless silicon on insulator (SOI) sensor technology. While the concept of angle probes is not new, traditional devices had been relatively large due to fabrication constraints; often too large to resolve flow structures necessary for modern aeropropulsion measurements such as inlet flow distortions and vortices, secondary flows, etc. Mea surements of this kind demanded a new approach to probe design to achieve sizes on the order of 0.1 in. (.3 mm) diameter or smaller, and capable of meeting demanding requirements for accuracy and ruggedness. This approach invoked the use of stateof- the-art processing techniques to install SOI sensor chips directly onto the probe body, thus eliminating redundancy in sensor packaging and probe installation that have historically forced larger probe size. This also facilitated a better thermal match between the chip and its mount, improving stability and accuracy. Further, the leadless sensor technology with which the SOI sensing element is fabricated allows direct mounting and electrical interconnecting of the sensor to the probe body. This leadless technology allowed a rugged wire-out approach that is performed at the sensor length scale, thus achieving substantial sensor size reductions. The technology is inherently capable of high-frequency and high-accuracy performance in high temperatures and harsh environments.

  16. Low thermal budget for Si and SiGe surface preparation for FD-SOI technology

    NASA Astrophysics Data System (ADS)

    Labrot, M.; Cheynis, F.; Barge, D.; Müller, P.; Juhel, M.

    2016-05-01

    Ultra thin Silicon films of Silicon-on-Insulator technology are metastable and thus cannot be submitted to high temperature treatments that may roughen or disrupt the film during the set of technological steps required for device fabrication. This paper concerns the development of an efficient low temperature cleaning process of Si and SiGe surfaces that enables a subsequent good-quality epitaxy of raised source and drain. For this purpose wet-clean, plasma-clean and several combinations of both are used. We thus propose two effective surface cleaning processes with low thermal budget optimized for FD-SOI technology.

  17. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  18. Micro/nano-mechanical sensors and actuators based on SOI-MEMS technology

    NASA Astrophysics Data System (ADS)

    Viet Dao, Dzung; Nakamura, Koichi; Thanh Bui, Tung; Sugiyama, Susumu

    2010-03-01

    MEMS (micro-electro-mechanical systems) technology has undergone almost 40 years of development, with significant technology advancement and successful commercialization of single-functional MEMS devices, such as pressure sensors, accelerometers, gyroscopes, microphones, micro-mirrors, etc. In this context of MEMS technology, this paper introduces our studies and developments of novel micro/nano-mechanical sensors and actuators based on silicon- on-insulator (SOI)-MEMS technology, as well as fundamental research on piezoresistive effects in single-crystal silicon nanowires (SiNWs). In the first area, novel mechanical sensors, such as 6-DOF micro-force moment sensors, multi-axis inertial sensors and micro-electrostatic actuators developed with SOI-MEMS technology will be presented. In the second area, we have combined atomic-level simulation and experimental evaluation methods to explain the giant piezoresistive effect in single crystalline SiNWs along different crystallographic orientations. This discovery is significant for developing more highly sensitive and miniaturized mechanical sensors in the near future.

  19. Temperature behavior of spiral inductors on high resistivity substrate in SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    El Kaamouchi, M.; Delatte, P.; Si Moussa, M.; Raskin, J.-P.; Vanhoenacker-Janvier, D.

    2008-12-01

    This paper reviews and analyzes a compact model for integrated planar spiral inductors on standard and high resistivity substrates in silicon-on-insulator (SOI) technology. The inductors have been characterized over a temperature range from 25 to 200 °C. The temperature variation of each model parameter has been investigated. It demonstrates that only the variations of the metallic losses versus temperature have to be taken into account to model properly the high frequency behavior over a wide temperature range of a spiral inductor integrated on silicon high resistivity substrate. Based on these experimental and characterization results, guidelines for practical inductor designs in RFICs for high-temperature applications are drawn.

  20. Numerical simulation of a new generation of high-temperature micropower gas and odor sensors based on SOI technology

    NASA Astrophysics Data System (ADS)

    Gardner, Julian W.; Udrea, Florin; Milne, William I.

    1999-07-01

    Gas sensors fabricated using conventional silicon microtechnology can suffer from a number of significant disadvantages when compared with commercially available thick-film, screen-printed devices. For example, platinum gate MOSFET devices normally operate only at a temperature of up to 180 degree(s)C and this limits the catalyst activity, and hence their sensitivity and response time. In addition, the fabrication of an integrated, resistive heater poses interesting problems; thus whilst polysilicon heaters are CMOS compatible, they tend to suffer from non-linearity, poor reproducibility and stability; whereas platinum resistive heaters are incompatible with a CMOS process and thus difficult and expensive to manufacture. Here we propose the use of SOI technology leading to a new generation of high-temperature, silicon smart gas sensors (patent pending). Numerical simulations of an n-channel MOSFET structure on a thin SOI membrane have been performed in non- isothermal conditions using a MEDICI simulator. Our results demonstrate that SOI-based devices can operate at temperatures of up to 350 degree(s)C without causing a problem for neighboring CMOS I.C. circuitry. The power consumption of our SOI-based designs may be as low as ca. 10 mW at 300 degree(s)C and so compares favorably with previously reported values for non-SOI based silicon micromachined gas sensors. In conclusion, SOI technology may be used to fabricate novel high-temperature, micropower resistive and catalytic-gate MOSFET gas/odor sensors. These devices can be fabricated in a standard SOI CMOS process at low unit cost and should offer an excellent degree of reproducibility. Applications envisaged are in air quality sensors for the automotive industry and odor sensors for electronic noses.

  1. 15158A SP6T RF switch based on IBM SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhiqun, Cheng; Guoguo, Yan; Wayne, Ni; Dandan, Zhu; Hannah, Ni; Jin, Li; Shuai, Chen; Guohua, Liu

    2016-05-01

    This paper presents the design of single-pole six-throw (SP6T) RF switch with IBM 0.18 μm SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is (+2.46 V, 0, -2.46 V) in the frequency from 0.1 to 2.7 GHz. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LZ16F010001).

  2. 15158A SP6T RF switch based on IBM SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhiqun, Cheng; Guoguo, Yan; Wayne, Ni; Dandan, Zhu; Hannah, Ni; Jin, Li; Shuai, Chen; Guohua, Liu

    2016-05-01

    This paper presents the design of single-pole six-throw (SP6T) RF switch with IBM 0.18 μm SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is (+2.46 V, 0, ‑2.46 V) in the frequency from 0.1 to 2.7 GHz. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LZ16F010001).

  3. SEMICONDUCTOR DEVICES: A new integrated SOI power device based on self-isolation technology

    NASA Astrophysics Data System (ADS)

    Huanmei, Gao; Xiaorong, Luo; Wei, Zhang; Hao, Deng; Tianfei, Lei

    2010-08-01

    A new SOI LDMOS structure with buried n-islands (BNIs) on the top interface of the buried oxide (BOX) is presented in a p-SOI high voltage integrated circuits (p-SOI HVICs), which exhibits good self-isolation performance between the power device and low-voltage control circuits. Furthermore, both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm, but also modulate the lateral electric field distribution, resulting in an improvement of the breakdown voltage of the BNI SOI LDMOS. A 673 V BNI SOI LDMOS is experimentally obtained and presents an excellent self-isolation performance in a p-SOI HVIC.

  4. The development of x-ray bolometers based on SOI technology for astronomy

    NASA Astrophysics Data System (ADS)

    Aliane, A.; De Moro, F.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; Szeflinski, V.; Gasse, A.; Arnaud, M.; de la Broïse, X.; Navick, X.-F.; Routin, J.; Mathieu, L.; Cigna, J.-C.; Berger, F.; Ribot, H.; Gobil, Y.

    2008-07-01

    Several successful development programs have been conducted on Infra-Red bolometer arrays at the French Atomic Energy Commission (CEA-LETI Grenoble), in collaboration with the CEA-Sap (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors. These micro-calorimeter arrays will be used for future space missions. A 8×8 array prototype consisting of a grid of 64 suspended pixels on SOI (Silicon On Insulator) has been created. Each pixel of this array detector is made of a tantalum (Ta) absorber and is bonded, by means of an indium bump hybridization process, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process step. The fabrication process of our detector involves a combination of standard silicon technologies such as Si bulk micromachining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on the different building elements and processes that are required to create a detector array up to 32*32 pixels in size.

  5. Study of millisecond laser annealing on ion implanted soi and application to scaled finfet technology

    NASA Astrophysics Data System (ADS)

    Michalak, Tyler J.

    The fabrication of metal-oxide-semiconductor field effect transistors (MOSFET) requires the engineering of low resistance, low leakage, and extremely precise p-n junctions. The introduction of finFET technology has introduced new challenges for traditional ion implantation and annealing techniques in junction design as the fin widths continue to decrease for improved short channel control. This work investigates the use of millisecond scanning laser annealing in the formation of n-type source/drain junctions in next generation MOSFET. We present a model to approximate the true thermal profile for a commercial laser annealing process which allows us to represent more precisely specific thermal steps using Technology Computer Aided Design (TCAD). Sheet resistance and Hall Effect measurements for blanket films are used to correlate dopant activation and mobility with the regrowth process during laser anneal. We show the onset of high conductivity associated with completion of solid phase epitaxial regrowth (SPER) in the films. The Lattice Kinetic Monte Carlo (LKMC) model shows excellent agreement with cross section transmission electron microscopy (TEM), correlating the increase of conductivity with completion of crystal regrowth, increased activation, and crystal quality at various temperatures. As scaled devices move into the non-planar geometries and possibly adopt silicon-on-insulator (SOI) substrates, the crystal regrowth and dopant activation of amorphizing implants becomes more complicated and doping methods must adapt accordingly. Following the concept of the more recently proposed hot ion implantation and the benefits of laser anneal, we investigate a possible process flow for a 10/14 nm node SOI finFET by utilizing process and device TCAD. Device simulation parameters for the 10/14 nm node device are taken from a calibrated model based on fabricated non-planar 40 nm gate length device finFET. The implications on device performance are considered for the

  6. Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

    NASA Astrophysics Data System (ADS)

    Kranti, Abhinav; Hao, Ying; Armstrong, G. Alastair

    2008-04-01

    In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (Ion/Ioff). Based on the investigation of on-current (Ion), off-current (Ioff), Ion/Ioff, intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on Ion, Ioff and τ is also investigated for optimized underlap devices.

  7. Sensors and actuators based on SOI materials

    NASA Astrophysics Data System (ADS)

    Sanz-Velasco, Anke; Nafari, Alexandra; Rödjegård, Henrik; Bring, Martin; Hedsten, Karin; Enoksson, Peter; Bengtsson, Stefan

    2006-05-01

    Examples of using SOI materials for formation of novel sensor and actuator structures at Chalmers University of Technology are given. Using SOI material gives advantages in formation of sensor and actuator structures, such as a nanoindentation force sensor, a three-axis accelerometer, a miniaturized pinball game and integration of diffractive optical elements onto silicon.

  8. Design and fabrication process of silicon micro-calorimeters on simple SOI technology for X-ray spectral imaging

    NASA Astrophysics Data System (ADS)

    Aliane, A.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; de Moro, F.; Ribot, H.; Gasse, A.; Szeflinski, V.; Gobil, Y.

    2008-09-01

    Several successful development programs have been conducted on infra-red bolometer arrays at the "Commissariat à l'Energie Atomique" (CEA-LETI Grenoble) in collaboration with the CEA-SAp (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon only technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors in an improved array that could be used for future space missions. The 8×8 array consists of a grid of 64 suspended pixels fabricated on a silicon on insulator (SOI) wafer. Each pixel of this detector array is made of a tantalum (Ta) absorber, which is bound by means of indium bump hybridization, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process. The fabrication process of our detector involves a combination of standard technologies and silicon bulk micro-machining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on these four primary building blocks that are required to create a detector array up to 32×32 pixels in size.

  9. Development of a CMOS SOI Pixel Detector

    SciTech Connect

    Arai, Y.; Hazumi, M.; Ikegami, Y.; Kohriki, T.; Tajima, O.; Terada, S.; Tsuboyama, T.; Unno, Y.; Ushiroda, Y.; Ikeda, H.; Hara, K.; Ishino, H.; Kawasaki, T.; Miyake, H.; Martin, E.; Varner, G.; Tajima, H.; Ohno, M.; Fukuda, K.; Komatsubara, H.; Ida, J.; /NONE - OKI ELECTR INDUST TOKYO

    2008-08-19

    We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 {micro}m fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5 mm{sup 2} consisting of 20 x 20 {micro}m{sup 2} pixels have been designed and manufactured. Performance tests with a laser light illumination and a {beta} ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

  10. Development of X-ray microcalorimeters based on SOI technology and experimental results

    NASA Astrophysics Data System (ADS)

    Szeflinski, V.; Aliane, A.; De Moro, F.; Pigot, C.; Sauvageot, J.-L.; Agnèse, P.; Gasse, A.; Ribot, H.; Gremion, E.; De La Broise, X.; Navick, X. F.

    2009-10-01

    We are developing an X-ray spectro-imaging detector at cryogenic temperature (<100 mK) for next space generation missions, using silicon technology. Each pixel of this array detector is made of a tantalum absorber bonded by indium bump hybridization, to an implanted and high-temperature diffused silicon thermistor. The thermo-mechanical link, provided by the indium bump hybridization, is being improved in terms of thermal capacitance. We present the state of development and experimental results on this new generation of X-ray microcalorimeters.

  11. Development of Radhard VLSI electronics for SSC calorimeters

    SciTech Connect

    Dawson, J.W.; Nodulman, L.J.

    1989-01-01

    A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs.

  12. RC64, a Rad-Hard Many-Core High- Performance DSP for Space Applications

    NASA Astrophysics Data System (ADS)

    Ginosar, Ran; Aviely, Peleg; Gellis, Hagay; Liran, Tuvia; Israeli, Tsvika; Nesher, Roy; Lange, Fredy; Dobkin, Reuven; Meirov, Henri; Reznik, Dror

    2015-09-01

    RC64, a novel rad-hard 64-core signal processing chip targets DSP performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. RC64 integrates advanced DSP cores with a multi-bank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 3.125 Gbps full duplex high speed serial links using SpaceFibre and other protocols. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 300 MHz integrated circuit on a 65nm CMOS technology, assembled in hermetically sealed ceramic CCGA624 package and qualified to the highest space standards.

  13. SEMICONDUCTOR DEVICES: Conductivity modulation enhanced lateral IGBT with SiO2 shielded layer anode by SIMOX technology on SOI substrate

    NASA Astrophysics Data System (ADS)

    Wensuo, Chen; Bo, Zhang; Zhaoji, Li; Jian, Fang; Xu, Guan

    2010-06-01

    A new lateral insulated-gate bipolar transistor (LIGBT) with a SiO2 shielded layer anode on SOI substrate is proposed and discussed. Compared to the conventional LIGBT, the proposed device offers an enhanced conductivity modulation effect due to the SiO2 shielded layer anode structure which can be formed by SIMOX technology. Simulation results show that, for the proposed LIGBT, during the conducting state, the electron-hole plasma concentrations in the n-drift region are several times larger than those of the conventional LIGBT; the conducting current is up to 37% larger than that of the conventional one. The enhanced conductivity modulation effect by SiO2 shielded layer anode does not sacrifice other characteristics of the device, such as breakdown and switching, but is compatible with other optimized technologies.

  14. A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

    NASA Astrophysics Data System (ADS)

    Yan-Hui, Zhang; Jie, Wei; Chao, Yin; Qiao, Tan; Jian-Ping, Liu; Peng-Cheng, Li; Xiao-Rong, Luo

    2016-02-01

    A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

  15. BUSFET - A Novel Radiation-Hardened SOI Transistor

    SciTech Connect

    Dodd, P.E.; Draper, B.L.; Schwank, J.R.; Shaneyfelt, M.R.

    1999-02-04

    A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology.

  16. Statistical Modeling of Soi Devices for Low-Power Electronics.

    NASA Astrophysics Data System (ADS)

    Phelps, Mark Joseph

    1995-01-01

    This dissertation addresses the needs of low-power, large-scale integrated circuit device design, advanced materials technology, and computer simulation for statistical modeling. The main body of work comprises the creation and implementation of a software shell (STADIUM-SOI) that automates the application of statistics to commercial technology computer-aided design tools. The objective is to demonstrate that statistical design of experiments methodology can be employed for the advanced material technology of Silicon -On-Insulator (SOI) devices. The culmination of this effort was the successful modeling of the effect of manufacturing process variation on SOI device characteristics and the automation of this procedure.

  17. SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

    NASA Astrophysics Data System (ADS)

    Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

    2010-02-01

    To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

  18. Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

    NASA Astrophysics Data System (ADS)

    Koyama, M.; Cassé, M.; Barraud, S.; Ghibaudo, G.; Iwai, H.; Faynot, O.; Reimbold, G.

    2015-06-01

    A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm × 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors.

  19. A 60 GOPS/W, -1.8V to 0.9V body bias ULP cluster in 28nm UTBB FD-SOI technology

    NASA Astrophysics Data System (ADS)

    Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca

    2016-03-01

    Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from -1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range -40 °C to 120 °C exploiting -1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors

  20. Atmel's New Rad-Hard Sparc V8 Processor 200Mhz & Low Power System on Chip

    NASA Astrophysics Data System (ADS)

    Ganry, Nicolas; Mantelet, Guy; Parkes, Steve; McClements, Chris

    2014-08-01

    The AT6981 is a new generation of processor designed for critical spaceflight applications, which combines a high-performance SPARC® V8 radiation hard processor, with enough on-chip memory for many aerospace applications and state-of-the-art SpaceWire networking technology from STARDundee. The AT6981 is implemented in Atmel 90nm rad-hard technology, enabling 200 MHz operating speed for the processor with power consumption levels around 1W. This advanced technology allows strong system integration in a SoC with embedded peripherals like CAN, 1553, Ethernet, DDR and embedded memory with 1Mbytes SRAM. The device is ITARfree and is developed in France by Atmel Aerospace having more than of 30years space experience. This paper describes this new SoC architecture and technical options considered to insure the best performances, the minimum power consumption and high reliability. This device will be available on the market in H2 2014 for evaluation with first flight models targeted end 2015.

  1. Characteristics of non-irradiated and irradiated double SOI integration type pixel sensor

    NASA Astrophysics Data System (ADS)

    Asano, M.; Sekigawa, D.; Hara, K.; Aoyagi, W.; Honda, S.; Tobita, N.; Arai, Y.; Miyoshi, T.; Kurachi, I.; Tsuboyama, T.; Yamada, M.

    2016-09-01

    We are developing monolithic pixel sensors based on a 0.2 μm fully depleted silicon-on-insulator (FD-SOI) technology for high-energy physics experiment applications. With this SOI technology, the wafer resistivities for the electronics and sensor parts can be chosen separately. Therefore, a device with full depletion and fast charge collection is realized. The total ionizing dose (TID) effect is the major challenge for application in hard radiation environments. To compensate for TID damage, we introduced a double SOI structure that implements an additional middle silicon layer (SOI2 layer). Applying a negative voltage to the SOI2 layer should compensate for the effects induced by holes trapped in the buried oxide layers. We studied the recovery from TID damage induced by 60Co γ and other characteristics of the integration-type double SOI sensor INTPIXh2. When the double SOI sensor was irradiated to 100 kGy, it showed a response to the infrared laser similar to that of a non-irradiated sensor when we applied a negative voltage to the SOI2 layer. Thus, we concluded that the double SOI sensor is very effective at sufficiently enhancing the radiation hardness for application in experiments with harsh radiation environments, such as at Belle II or ILC.

  2. Assessment of SOI Devices and Circuits at Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Elbuluk, Malik; Hammoud, Ahmad; Patterson, Richard L.

    2007-01-01

    Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

  3. Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability

    NASA Astrophysics Data System (ADS)

    Schwarzenbach, Walter; Nguyen, Bich-Yen; Allibert, Frederic; Girard, Christophe; Maleville, Christophe

    2016-03-01

    This paper reviews the properties of the SOI wafers fabricated using the Smart Cut™ technology, with ultra-thin body and buried oxide (BOX) required for the FD-SOI CMOS platform. It focuses on the parameters that require specific attention for this technology, namely, the top silicon layer thickness uniformity and buried oxide reliability. The first one is linked to the threshold voltage variability and the second to the active role played by the BOX when a back-bias is used. An overview of the specific process optimization and metrology developed to achieve the targeted specifications is given.

  4. BUSFET - A Novel Radiation-Hardened SOI Transistor

    SciTech Connect

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-07-20

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10{sup 18} cm{sup {minus}3} and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10{sup 17} cm{sup {minus}3}, a thicker silicon film (300 nm) must be used.

  5. Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements

    NASA Astrophysics Data System (ADS)

    Kazemi Esfeh, B.; Kilchytska, V.; Barral, V.; Planes, N.; Haond, M.; Flandre, D.; Raskin, J.-P.

    2016-03-01

    This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD-SOI) planar ultra-thin body and BOX (UTBB) MOSFETs for high frequency applications. All parasitic elements such as the parasitic gate and source/drain series resistances, total capacitances are extracted and their effects on RF performance are analyzed and compared with previous work on similar devices. Two main RF figures of merit (FoM) such as the current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are determined. It is shown that fT of ∼280 GHz and fmax of ∼250 GHz are achievable in the shortest devices. Based on the extracted parameters, the validation of the small-signal equivalent circuit used for modeling UTBB MOSFETs is investigated by comparing simulated and measured S-parameters.

  6. A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

    NASA Astrophysics Data System (ADS)

    Hemperek, Tomasz; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert

    2015-10-01

    An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

  7. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    DOEpatents

    Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  8. New RAD-Hard STRH3260L6 Bipolar And STRH100N10 Mosfet Power Transistors

    NASA Astrophysics Data System (ADS)

    Camonita, Giuseppe; Pintacuda, Francesco

    2011-10-01

    This article describes two new power discrete components from STMicroelectronics, specifically offered for Space applications. The STRH3260L6 is a double bipolar rad-hard transistor in an SMD package that houses two complementary devices, one NPN and one PNP. The STRH100N10 is an N-channel rad-hard power MOSFET, the first that is ESCC qualified and available in Europe without procurement restrictions. The purpose of this writing is to give details about the devices' main features, characterization for static, dynamic and radiation performances.

  9. Micro biochemical sensor based on SOI planar optical waveguide

    NASA Astrophysics Data System (ADS)

    Du, Yang; Dong, Ying

    2014-02-01

    A novel biochemical sensor based on planar optical waveguide is presented in this paper. The features of the sensor are as follows, the planar optical waveguide is made of SOI (Silicon-On-Insulator) material, a Mach Zehnder (M-Z) Interferometer structure is adopted as the sensing part, the sensor chip is fabricated using CMOS compatible technology and the size of the sensor chip is on the micron scale. Compared with the traditional biochemical sensors, this new type of sensor has such notable advantages as miniaturization, integration, high sensitivity and strong anti-interference capability, which provide the sensor with potential applications where traditional biochemical sensors cannot be used. At first, the benefits of SOI material comparing to other optical waveguide materials were analyzed in this paper. Then, according to the optical waveguide mode theory, M-Z interferometer waveguide was designed for the single mode behavior. By theoretical analysis of the radiation loss in the Y-junction of the planar waveguide interferometer, the relationship between the branch angle and the radiation loss was obtained. The power transfer function and the parametric equation of sensitivity of the M-Z interferometer were obtained through analysis of the waveguide structure. At last, the resolution of the effective refractive index and the characteristics of sensitivity of the sensor based on SOI M-Z Interferometer waveguide were simulated and analyzed by utilizing MATLAB software. As a result, the sensitivity of SOI M-Z Interferometer sensor can reach the order of 10-7 magnitude.

  10. FinFET and UTBB for RF SOI communication systems

    NASA Astrophysics Data System (ADS)

    Raskin, Jean-Pierre

    2016-11-01

    Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

  11. First results of a Double-SOI pixel chip for X-ray imaging

    NASA Astrophysics Data System (ADS)

    Lu, Yunpeng; Ouyang, Qun; Arai, Yasuo; Liu, Yi; Wu, Zhigang; Zhou, Yang

    2016-09-01

    Aiming at low energy X-ray imaging, a prototype chip based on Double-SOI process was designed and tested. The sensor and pixel circuit were characterized. The long lasting crosstalk issue in SOI technology was understood. The operation of pixel was verified with a pulsed infrared laser beam. The depletion of sensor revealed by signal amplitudes is consistent with the one revealed by I-V curve. An s-curve fitting resulted in a sigma of 153 e- among which equivalent noise charge (ENC) contributed 113 e-. It's the first time that the crosstalk issue in SOI technology was solved and a counting type SOI pixel demonstrated the detection of low energy radiation quantitatively.

  12. Method to improve commercial bonded SOI material

    DOEpatents

    Maris, Humphrey John; Sadana, Devendra Kumar

    2000-07-11

    A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

  13. MEMS Using SOI Substrate

    NASA Technical Reports Server (NTRS)

    Tang, Tony K.

    1999-01-01

    At NASA, the focus for smaller, less costly missions has given impetus for the development of microspacecraft. MicroElectroMechanical System (MEMS) technology advances in the area of sensor, propulsion systems, and instruments, make the notion of a specialized microspacecraft feasible in the immediate future. Similar to the micro-electronics revolution,the emerging MEMS technology offers the integration of recent advances in micromachining and nanofabrication techniques with microelectronics in a mass-producible format,is viewed as the next step in device and instrument miniaturization. MEMS technology offers the potential of enabling or enhancing NASA missions in a variety of ways. This new technology allows the miniaturization of components and systems, where the primary benefit is a reduction in size, mass and power. MEMS technology also provides new capabilities and enhanced performance, where the most significant impact is in performance, regardless of system size. Finally,with the availability of mass-produced, miniature MEMS instrumentation comes the opportunity to rethink our fundamental measurement paradigms. It is now possible to expand our horizons from a single instrument perspective to one involving multi-node distributed systems. In the distributed systems and missions, a new system in which the functionality is enabled through a multiplicity of elements. Further in the future, the integration of electronics, photonics, and micromechanical functionalities into "instruments-on-a-chip" will provide the ultimate size, cost, function, and performance advantage. In this presentation, I will discuss recent development, requirement, and applications of various MEMS technologies and devices for space applications.

  14. Rad-Hard Structured ASIC Body of Knowledge

    NASA Technical Reports Server (NTRS)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  15. Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

    NASA Astrophysics Data System (ADS)

    Ruddell, F. H.; Suder, S. L.; Bain, M. F.; Montgomery, J. H.; Armstrong, B. M.; Gamble, H. S.; Denvir, D.; Casse, G.; Bowcock, T.; Allport, P. P.; Marczewski, J.; Kucharski, K.; Tomaszewski, D.; Niemiec, H.; Kucewicz, W.

    2008-12-01

    Silicon on insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100 V and average leakage current densities at 70 V were only 55 nA/cm 2. MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45 × 10 11 cm -2 for a dose of 2.7 Mrad.

  16. Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

    SciTech Connect

    Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

    2010-09-01

    Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

  17. Electron trapping in rad-hard RCA IC's irradiated with electrons and gamma rays

    NASA Technical Reports Server (NTRS)

    Danchenko, V.; Brashears, S. S.; Fang, P. H.

    1984-01-01

    Enhanced electron trapping has been observed in n-channels of rad-hard CMOS devices due to electron and gamma-ray irradiation. Room-temperature annealing results in a positive shift in the threshold potential far beyond its initial value. The slope of the annealing curve immediately after irradiation was found to depend strongly on the gate bias applied during irradiation. Some dependence was also observed on the electron dose rate. No clear dependence on energy and shielding over a delidded device was observed. The threshold shift is probably due to electron trapping at the radiation-induced interface states and tunneling of electrons through the oxide-silicon energy barrier to fill the radiation-induced electron traps. A mathematical analysis, based on two parallel annealing kinetics, hole annealing and electron trapping, is applied to the data for various electron dose rates.

  18. SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell

    SciTech Connect

    Alles, M.L. )

    1994-12-01

    Fully depleted silicon-on-insulator (SOI) technologies are of interest for commercial applications as well as for use in harsh (radiation-intensive) environments. In both types of application, effects of charged particles (single-event effects) are of concern. Here, SPICE analysis of SEU sensitivity of a 6-T SRAM cell using commercially-representative fully depleted SOI CMOS technology parameters indicates that reduction of the minority carrier lifetime (parasitic bipolar gain) and use of thinner silicon can significantly reduce SEU sensitivity.

  19. SOI nanowires as sensors for charge detection

    NASA Astrophysics Data System (ADS)

    Naumova, O. V.; Fomin, B. I.; Nasimov, D. A.; Dudchenko, N. V.; Devyatova, S. F.; Zhanaev, E. D.; Popov, V. P.; Latyshev, A. V.; Aseev, A. L.; Ivanov, Yu D.; Archakov, A. I.

    2010-05-01

    The properties of silicon-on-insulator nanowires (SOI NWs) fabricated by means of electron lithography and gas etching of SOI in XeF2 or SF6:CFCl3 have been investigated. The method used to fabricate the nanowires was found to require no additional anneal to be given to the final structure for defect removal after nanostructuring. The sensitivity of SOI NWs to negative protein BSA molecules in the pH 7.4 buffer solution was shown to be as high as 1 femtomoles. The gate characteristics of SOI NWs were used to determine the charge density of particles adsorbed on the NW surface. A charge density of 4.6 × 1011 cm-2 was estimated for a 1 femtomole protein concentration. The combined use of open-channel structures with top gates was employed for determining the charge state of structure surfaces after different chemical treatments. Chemical treatments giving rise to a density of the negative charges on the surface of NWs ranging in the interval (7-23) × 1011 cm-2 were examined. Treatments in methanol (after removal of the native oxide) were found to provide stabilization of the SOI surface over a 3-h interval after the treatments.

  20. Opposite-channel-based hot-carrier injection in SOI MOSFET's

    NASA Astrophysics Data System (ADS)

    Zaleski, Andrzej Dariusz

    1997-04-01

    As progress is being continuously made on various Silicon-On-Insulator (SOI) technologies there is much current interest aimed on studies which exploit unique properties exhibited by MOSFET devices made by these technologies for VLSI applications. With ever decreasing VLSI device dimensions, degradation caused by hot carriers in such circuits is especially important. The hot carrier related phenomena have been studied extensively for bulk and SOI MOSFET's, and although a wealth of information has been accumulated over the years by a large number of researchers around the world, the topic continues to be the subject of intense investigations. In this work, a new method of the hot carrier injection, a hot hole injection into the opposite channel of the SOI nMOSFET's is first experimentally demonstrated and explained. This hot hole injection is obtained by operating one channel of a typical SOI nMOSFET in avalanche while keeping the opposite channel accumulated. The potential of using the 'opposite-channel-based' hot hole injection to enhance existing MOSFET's characterization techniques is then exploited by the development of the sequential front/back channel stressing technique, which is further used to conduct comparative studies of the hot-carrier-induced degradation of SOI MOSFET's as a function of drain design. Finally, the new hot carrier injection method is explored for possible device applications, where the structure and operation of a single cell and a cell array of a new Electrically Erasable Programmable Read Only Memory (EEPROM) on SOI substrates are described. This new EEPROM cell exploits the 'back-channel-based' hot hole injection to erase information, and it can be selectively read, written and erased in the cell array.

  1. Low-Power SOI CMOS Transceiver

    NASA Technical Reports Server (NTRS)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  2. Performance analysis of SOI MOSFET with rectangular recessed channel

    NASA Astrophysics Data System (ADS)

    Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

    2016-03-01

    In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

  3. Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2010-01-01

    Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  4. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

    PubMed

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-08-18

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

  5. C- V characterization of MOS capacitors in SOI structures

    NASA Astrophysics Data System (ADS)

    Rustagi, S. C.; Mohsen, Z. O.; Chandra, S.; Chand, A.

    1996-06-01

    The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out and the results have been interpreted with the help of a numerical solution to the one-dimensional Laplace-Poisson's equation. Various parameters characterizing the SOI MOS structures have been extracted. It has been shown that the C- V data on a simple three-terminal SOI MOS capacitor structure can yield all the information such as the thickness of the gate oxide, buried-oxide as well as the SOI film, along with the doping density in the film and the substrate.

  6. Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

    NASA Technical Reports Server (NTRS)

    Brucker, G. J.; Van Gunten, O.; Stassinopoulos, E. G.; Shapiro, P.; August, L. S.; Jordan, T. M.

    1983-01-01

    This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

  7. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

    PubMed Central

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-01-01

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA. PMID:26295235

  8. Design and coupled-effect simulations of CMOS micro gas sensors built on SOI thin membranes

    NASA Astrophysics Data System (ADS)

    Lu, Chih-Cheng; Udrea, Florin; Gardner, Julian W.; Setiadi, D.; Dogaru, T.; Tsai, T. H.; Covington, James A.

    2001-04-01

    This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro- thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

  9. Effect of phosphorus ion implantation on back gate effect of partially depleted SOI NMOS under total dose radiation

    NASA Astrophysics Data System (ADS)

    Leilei, Li; Xinjie, Zhou; Zongguang, Yu; Qing, Feng

    2015-01-01

    The mechanism of improving the TID radiation hardened ability of partially depleted silicon-on-insulator (SOI) devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps introduced in SiO2 near back SiO2/Si interface by phosphorus ions implantation can offset positive trapped charges near the back-gate interface. The implanted high concentration phosphorus ions can greatly reduce the back-gate effect of a partially depleted SOI NMOS device, and anti-total-dose radiation ability can reach the level of 1 Mrad(Si) for experimental devices.

  10. Studies of vertex tracking with SOI pixel sensors for future lepton colliders

    NASA Astrophysics Data System (ADS)

    Battaglia, Marco; Contarato, Devis; Denes, Peter; Liko, Dietrich; Mattiazzo, Serena; Pantano, Devis

    2012-07-01

    This paper presents a study of vertex tracking with a beam hodoscope consisting of three layers of monolithic pixel sensors in SOI technology on high-resistivity substrate. We study the track extrapolation accuracy, two-track separation and vertex reconstruction accuracy in π- Cu interactions with 150 and 300 GeV/c pions at the CERN SPS. Results are discussed in the context of vertex tracking at future lepton colliders.

  11. CCSDS SOIS Onboard Application Support Services

    NASA Astrophysics Data System (ADS)

    Ciccone, M.; Fowell, S. D.

    2007-08-01

    The CCSDS is developing recommendations for space data systems. The SOIS area aims to standardize the interfaces between onboard subsystems and provide the application software with a common, consistent service interface to various low-level functionalities. This will allow spacecraft application to be developed independently of the specific mechanisms necessary to implement these services. The eventual goal is reusable software that can be easily ported to new missions and run on a range of onboard buses without substantial modification. Late configuration changes can be accommodated through simple spacecraft database changes without affecting onboard software. This consistent interface should facilitate the implementation of more robust, complex and potable software architectures. This paper describes the suite of "SOIS Application Support Services" which are designed to provide standardized access to sensors, actuators, devices and generic spacecraft functions for space applications running on any computing node of the spacecraft. This approach aims to insulate the applications from the specifics of a particular spacecraft platform and its underlying topology and communication architecture.

  12. Cassini SOI: Magnetometer data re-analysed

    NASA Astrophysics Data System (ADS)

    Southwood, D. J.; Yates, J. N.; Dougherty, M. K.

    2015-10-01

    The Cassini Saturn Orbit Insertion (SOI) on June 30 2004 marked Cassini's closest approach to Saturn in the mission so far. In advance of the proximal orbits it is appropriate to re-examine in preparation for the proximal orbit mission phase. SOI was the only occasion so far that Cassini has been on magnetic shells mapping to the A and B rings. At periapsis (r = 1.33 RS, Γ = 15°) it was magnetically conjugate to the inner edge of the C ring. It cannot be ruled out that the observed field inside L ≈ 1.5 is partly due to the longitude dependent internal field. g11 is a primary target and should show up in the data in special manner in part because of the spacecraft switch from retrograde to prograde motion around L &sim 2. Accordingly, for a source rotating at around 10.5-10.7 h., the spacecraft would sample azimuthal phase three times. This is illustrated here for the external cam source (G11) where the effect is dramatic as the amplitude does change with r. We show in particular that the cam fields appear to extend into the regime over the rings.

  13. SEMICONDUCTOR DEVICES Process optimization of a deep trench isolation structure for high voltage SOI devices

    NASA Astrophysics Data System (ADS)

    Kuiying, Zhu; Qinsong, Qian; Jing, Zhu; Weifeng, Sun

    2010-12-01

    The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry's 0.5-μm HV SOI technology.

  14. Charge accumulation in the buried oxide of SOI structures with the bonded Si/SiO2 interface under γ-irradiation: effect of preliminary ion implantation

    NASA Astrophysics Data System (ADS)

    Naumova, O. V.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P.

    2012-06-01

    In this study, we examined the effect of preliminary boron or phosphorous implantation on charge accumulation in the buried oxide of SOI-MOSFETs irradiated with γ-rays in the total dose range (D) of 105-5 × 107 rad. The buried oxide was obtained by high-temperature thermal oxidation of Si, and it was not subjected to any implantation during the fabrication process of SOI structures. It was found that implantation with boron or phosphorous ions, used in fabrication technologies of SOI-MOSFETs, increases the concentration of precursor traps in the buried oxide of SOI structures. Unlike in the case of boron implantation, phosphorous implantation leads to an increased density of states at the Si/buried SiO2 interface during subsequent γ-irradiation. In the γ-irradiated SOI-MOSFETs, the accumulated charge density and the density of surface states in the Si/buried oxide layer systems both vary in proportion to kiln D. The coefficients ki for as-fabricated and ion-implanted Si/buried SiO2 systems were evaluated. From the data obtained, it was concluded that a low density of precursor hole traps was a factor limiting the positive charge accumulation in the buried oxide of as-fabricated (non-implanted) SOI structures with the bonded Si/buried SiO2 interface.

  15. High temperature spice modeling of partially depleted SOI MOSFETs

    SciTech Connect

    Osman, M.A.; Osman, A.A.

    1996-03-01

    Several partially depleted SOI N- and P-mosfets with dimensions ranging from W/L=30/10 to 15/3 were characterized from room temperature up to 300 C. The devices exhibited a well defined and sharp zero temperature coefficient biasing point up to 573 K in both linear and saturation regions. Simulation of the I-V characteristics using a temperature dependent SOI SPICE were in excellent agreement with measurements. Additionally, measured ZTC points agreed favorably with the predicted ZTC points using expressions derived from the temperature dependent SOI model for the ZTC {copyright} {ital 1996 American Institute of Physics.}

  16. Application of heat flow models to SOI current mirrors

    NASA Astrophysics Data System (ADS)

    Yu, Feixia; Cheng, Ming-C.

    2004-11-01

    An analytical heat flow model for SOI circuits is presented. The model is able to account for heat exchanges among devices and heat loss from the silicon film and interconnects to the substrate through the buried oxide. The developed model can accurately and efficiently predict the temperature distribution in the interconnect/poly-lines and SOI devices. The model is applied to SOI current mirrors to study heat flow in different layout designs. The results from the developed model are verified with those from Raphael, a 3D numerical simulator that can provide the detailed 3D temperature distribution in interconnect/poly-lines.

  17. Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

    2008-01-01

    Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

  18. Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  19. Design and optimization of the SOI field effect diode (FED) for ESD protection

    NASA Astrophysics Data System (ADS)

    Yang, Yang; Salman, Akram A.; Ioannou, Dimitris E.; Beebe, Stephen G.

    2008-10-01

    A thorough investigation is carried out by numerical simulations of the field effect diode (FED) with the aim to explore its potential for ESD protection applications in silicon on insulator (SOI) technologies. It is shown that the carrier lifetime value has an important impact on the device operation. By careful sizing and doping, FED devices with reasonable breakdown voltage values can be achieved but at rather high gate voltage values. Better results are achieved by modifying the doping profile to resemble a PNPN structure with two gates.

  20. The effect of integration of Strontium-Bismuth-Tantalate capacitors onto SOI wafers

    NASA Technical Reports Server (NTRS)

    Joshi, Vikram; Ohno, Morifumo; Ida, Jiro; Nagatomo, Yoshiki; Strauss, Karl

    2005-01-01

    We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

  1. The Effect of Integration of Strontium-Bismuth-Tantalate Capacitors onto SOI Wafers

    NASA Technical Reports Server (NTRS)

    Strauss, Karl F.; Joshi, Vikram; Ohno, Morifumo; Ida, Jiro; Nagatomo, Yoshiki

    2006-01-01

    We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

  2. Tunable optical delay line in SOI implemented with step chirped Bragg gratings and serial grating arrays

    NASA Astrophysics Data System (ADS)

    Spasojevic, Mina; Chen, Lawrence R.

    2013-10-01

    Tunable optical delay devices have numerous applications in optical communications [1] and have been successfully implemented using slow light elements and fiber or waveguide gratings. There has been considerable interest in siliconon- insulator (SOI) as a technology platform for compact integration of optical signal processing systems. SOI-based delay lines have been realized using coupled ring resonators [2], photonic crystals [3], and various Bragg grating-based configurations including single or coupled chirped sidewall gratings [4,5] as well as tapered rib waveguide gratings [6]. By linearly chirping the period in sidewall gratings, relatively small delays (a few ps) over a bandwidth of tens of nm were demonstrated [4]; with tapered waveguides, significantly larger delays (300-500 ps) were obtained, albeit over a narrower bandwidth (< 2 nm) [6]. On the other hand, some signal processing applications may require large delays (e.g., tens to hundreds of ps) over large bandwidths (several to tens of nm). Several designs have been proposed to meet these requirements, e.g., a step-chirped rib waveguide grating providing 50 ps delay over 15 nm [7] or complementary apodized sidewall gratings providing up to 275 ps over 3 nm [8], however, they have not been realized experimentally. In this paper, we demonstrate discretely tunable optical delay lines that provide tens of ps delay (up to 65 ps) in steps of 15-32 ps over bandwidths of several tens of nm (35-70 nm). The devices are fabricated on SOI using electron beam lithography and implemented through two different approaches: serial sidewall Bragg grating arrays and the step-chirped sidewall Bragg gratings.

  3. Analytical modeling and numerical simulations of the thermal behavior of trench-isolated bipolar transistors on SOI substrates

    NASA Astrophysics Data System (ADS)

    Marano, I.; d'Alessandro, V.; Rinaldi, N.

    2008-05-01

    The thermal behavior of trench-isolated structures on SOI (silicon-on-insulator) substrates is analyzed. Detailed 3-D numerical simulations have been performed to investigate the impact of all technological and material parameters of interest. A novel analytical model for the temperature field is proposed, which is based on the reduction of the domain under analysis to a silicon rectangular parallelepiped with convective boundary conditions at lateral and bottom faces. An extensive comparison with numerical results proves that the model is extremely accurate in the overall parameter range, and can be adopted for a fast evaluation of the thermal resistance of a trench SOI device as well as of the temperature gradients within the silicon island surrounded by trenches and buried oxide.

  4. An analytical model for nanowire junctionless SOI FinFETs with considering three-dimensional coupling effect

    NASA Astrophysics Data System (ADS)

    Fan-Yu, Liu; Heng-Zhu, Liu; Bi-Wei, Liu; Yu-Feng, Guo

    2016-04-01

    In this paper, the three-dimensional (3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator (SOI) FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional (2D) potential model is proposed for the subthreshold region of junctionless SOI FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted. Project supported by the Research Program of the National University of Defense Technology (Grant No. JC 13-06-04).

  5. An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

    NASA Technical Reports Server (NTRS)

    Jackson, S. A.; Blalock, B. J.; Mojarradi, M. M.; Li, H. W.

    2001-01-01

    The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

  6. On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

    NASA Astrophysics Data System (ADS)

    de Souza, Michelly; Flandre, Denis; Doria, Rodrigo Trevisoli; Trevisoli, Renan; Pavanello, Marcelo Antonio

    2016-03-01

    This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology.

  7. Analysis of Aluminum-Nitride SOI for High-Temperature Electronics

    NASA Technical Reports Server (NTRS)

    Biegel, Bryan A.; Osman, Mohamed A.; Yu, Zhiping

    2000-01-01

    We use numerical simulation to investigate the high-temperature (up to 500K) operation of SOI MOSFETs with Aluminum-Nitride (AIN) buried insulators, rather than the conventional silicon-dioxide (SiO2). Because the thermal conductivity of AIN is about 100 times that of SiO2, AIN SOI should greatly reduce the often severe self-heating problem of conventional SOI, making SOI potentially suitable for high-temperature applications. A detailed electrothermal transport model is used in the simulations, and solved with a PDE solver called PROPHET In this work, we compare the performance of AIN-based SOI with that of SiO2-based SOI and conventional MOSFETs. We find that AIN SOI does indeed remove the self-heating penalty of SOL However, several device design trade-offs remain, which our simulations highlight.

  8. Building blocks X-FAB SOI 0.18 μm

    NASA Astrophysics Data System (ADS)

    Cizel, J.-B.; Ahmad, S.; Callier, S.; Cornat, R.; Dulucq, F.; Fleury, J.; Martin-Chassard, G.; Raux, L.; de La Taille, C.; Thienpont, D.

    2015-02-01

    This work has been done in order to study a new technology provided by X-FAB named xt018. It is an SOI (Silicon On Insulator) technology with a minimal gate length of 180 nm. Building blocks have been done to test the advantages and drawbacks of this technology compared to the one currently used (AMS SiGe 0.35 μm). These building blocks have been designed to fit in an existing experience housed by the CALICE collaboration: the read-out chip for the Electromagnetic CALorimeter (ECAL) of the foreseen International Linear Collider (ILC). Performances will be compared to those of the SKIROC2 chip designed by the OMEGA laboratory, trying to fit the same requirements. The chip is being manufactured and will be back for measurements in December, the displayed results are only simulation results and thus the conclusions concerning the performances of these building blocks are subject to change.

  9. SEMICONDUCTOR DEVICES: A new SOI high voltage device based on E-SIMOX substrate

    NASA Astrophysics Data System (ADS)

    Lijuan, Wu; Shengdong, Hu; Bo, Zhang; Zhaoji, Li

    2010-04-01

    A new NI (n+ charge islands) high voltage device structure based on E-SIMOX (epitaxy-the separation by implantation of oxygen) substrate is proposed. It is characterized by equidistant high concentration n+-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field (EV) are located in the spacing of two neighboring n+-regions on the interface by the force from lateral electric field (EL) and the compositive operation of Coulomb's forces with the ionized donors in the undepleted n+-regions. This effectively enhances the electric field of dielectric buried layer (EI) and increases breakdown voltage (VB). An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology (E-SIMOX).

  10. Development and performance of Kyoto's x-ray astronomical SOI pixel (SOIPIX) sensor

    NASA Astrophysics Data System (ADS)

    Tsuru, Takeshi G.; Matsumura, Hideaki; Takeda, Ayaki; Tanaka, Takaaki; Nakashima, Shinya; Arai, Yasuo; Mori, Koji; Takenaka, Ryota; Nishioka, Yusuke; Kohmura, Takayoshi; Hatsui, Takaki; Kameshima, Takashi; Ozaki, Kyosuke; Kohmura, Yoshiki; Wagai, Tatsuya; Takei, Dai; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita; Kamehama, Hiroki

    2014-08-01

    We have been developing monolithic active pixel sensors, known as Kyoto's X-ray SOIPIXs, based on the CMOS SOI (silicon-on-insulator) technology for next-generation X-ray astronomy satellites. The event trigger output function implemented in each pixel offers microsecond time resolution and enables reduction of the non-X-ray background that dominates the high X-ray energy band above 5-10 keV. A fully depleted SOI with a thick depletion layer and back illumination offers wide band coverage of 0.3-40 keV. Here, we report recent progress in the X-ray SOIPIX development. In this study, we achieved an energy resolution of 300 eV (FWHM) at 6 keV and a read-out noise of 33 e- (rms) in the frame readout mode, which allows us to clearly resolve Mn-Kα and Kβ. Moreover, we produced a fully depleted layer with a thickness of 500 μm. The event-driven readout mode has already been successfully demonstrated.

  11. 3D through silicon via profile metrology based on spectroscopic reflectometry for SOI applications

    NASA Astrophysics Data System (ADS)

    Fursenko, O.; Bauer, J.; Marschmeyer, S.

    2016-04-01

    Through-silicon via (TSV) technology is a key feature for 3D circuit integration. TSVs are formed by etching a vertical via and filling them with a conductive material for creation of interconnections which go through the silicon or silicon-on-insulator (SOI) wafer. The Bosch etch process on Deep Reactive Ion Etching (DRIE) is commonly used for this purpose. The etch profile defined by the critical dimensions (CDs) at the top and at the bottom, by the depth and by the scallop size on the sidewall needs to be monitored and well controlled. In this work a nondestructive 3D metrology of deeply-etched structures with an aspect ratio of more than 10 and patterns with lateral dimensions from 2 to 7 μm in SOI wafer is proposed. Spectroscopic reflectometry in the spectral range of 250-800 nm using a production metrology tool was applied. The depth determinations based on different algorithms are compared. The Pearson correlation coefficient between measured and calculated reflection is suggested as the most appropriate method. A simple method for top CD evaluation is proposed by the measurement of reflection and using the polynomial approximation of reflection versus TSV filling coefficient which is determined as ratio of CD to pitch. The 3D RCWA simulations confirm this dependence.

  12. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    NASA Astrophysics Data System (ADS)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  13. Single Event Transient Analysis of an SOI Operational Amplifier for Use in Low-Temperature Martian Exploration

    NASA Technical Reports Server (NTRS)

    Laird, Jamie S.; Scheik, Leif; Vizkelethy, Gyorgy; Mojarradi, Mohammad M; Chen, Yuan; Miyahira, Tetsuo; Blalock, Benjamin; Greenwell, Robert; Doyle, Barney

    2006-01-01

    The next generation of Martian rover#s to be launched by JPL are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients (SET) which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-On-Insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shownto be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xebeams of energy 25MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36MeV O6(+) microbeam. the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern. This is a viewgraph presentation

  14. Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature

  15. Metallic behaviour in SOI quantum wells with strong intervalley scattering.

    PubMed

    Renard, V T; Duchemin, I; Niida, Y; Fujiwara, A; Hirayama, Y; Takashina, K

    2013-01-01

    The fundamental properties of valleys are recently attracting growing attention due to electrons in new and topical materials possessing this degree-of-freedom and recent proposals for valleytronics devices. In silicon MOSFETs, the interest has a longer history since the valley degree of freedom had been identified as a key parameter in the observation of the controversial "metallic behaviour" in two dimensions. However, while it has been recently demonstrated that lifting valley degeneracy can destroy the metallic behaviour, little is known about the role of intervalley scattering. Here, we show that the metallic behaviour can be observed in the presence of strong intervalley scattering in silicon on insulator (SOI) quantum wells. Analysis of the conductivity in terms of quantum corrections reveals that interactions are much stronger in SOI than in conventional MOSFETs, leading to the metallic behaviour despite the strong intervalley scattering. PMID:23774638

  16. Metallic behaviour in SOI quantum wells with strong intervalley scattering.

    PubMed

    Renard, V T; Duchemin, I; Niida, Y; Fujiwara, A; Hirayama, Y; Takashina, K

    2013-01-01

    The fundamental properties of valleys are recently attracting growing attention due to electrons in new and topical materials possessing this degree-of-freedom and recent proposals for valleytronics devices. In silicon MOSFETs, the interest has a longer history since the valley degree of freedom had been identified as a key parameter in the observation of the controversial "metallic behaviour" in two dimensions. However, while it has been recently demonstrated that lifting valley degeneracy can destroy the metallic behaviour, little is known about the role of intervalley scattering. Here, we show that the metallic behaviour can be observed in the presence of strong intervalley scattering in silicon on insulator (SOI) quantum wells. Analysis of the conductivity in terms of quantum corrections reveals that interactions are much stronger in SOI than in conventional MOSFETs, leading to the metallic behaviour despite the strong intervalley scattering.

  17. Characterization and modeling of capacitances in FD-SOI devices

    NASA Astrophysics Data System (ADS)

    Ben Akkez, Imed; Cros, Antoine; Fenouillet-Beranger, Claire; Perreau, P.; Margain, A.; Boeuf, Frederic; Balestra, Francis; Ghibaudo, Gérard

    2012-05-01

    Gate-to-channel capacitance Cgc(Vg) data obtained on FD-SOI MOS devices with gate lengths down to 35 nm are first reported. Thus, a 2D numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and buried oxide capacitances in the structure.

  18. Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

    NASA Astrophysics Data System (ADS)

    Ramezani, Zeinab; Orouji, Ali A.

    2016-10-01

    For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

  19. New linear sweep technique to measure generation lifetimes in thin-film SOI MOSFET's

    NASA Astrophysics Data System (ADS)

    Venkatesan, S.; Pierret, R. F.; Neudeck, G. W.

    1994-04-01

    A new linear sweep technique to measure generation lifetimes (tau(sub g)) in silicon-on-insulator (SOI) material is presented. A detailed analytic formulation is applied to fully-depleted and partially-depleted SOI films and used to simulate the behavior of the SOI devices under linear sweep conditions. A novel algorithm accurately determines the effective generation width in fully depleted SOI films. The measurement technique is experimentally verified by applying the algorithm to fully depleted SIMOX P-channel MOSFET's where observed lifetimes ranged from 0.3 mu s to 2.4 mu s.

  20. Development of an X-ray imaging system with SOI pixel detectors

    NASA Astrophysics Data System (ADS)

    Nishimura, Ryutaro; Arai, Yasuo; Miyoshi, Toshinobu; Hirano, Keiichi; Kishimoto, Shunji; Hashimoto, Ryo

    2016-09-01

    An X-ray imaging system employing pixel sensors in silicon-on-insulator technology is currently under development. The system consists of an SOI pixel detector (INTPIX4) and a DAQ system based on a multi-purpose readout board (SEABAS2). To correct a bottleneck in the total throughput of the DAQ of the first prototype, parallel processing of the data taking and storing processes and a FIFO buffer were implemented for the new DAQ release. Due to these upgrades, the DAQ throughput was improved from 6 Hz (41 Mbps) to 90 Hz (613 Mbps). The first X-ray imaging system with the new DAQ software release was tested using 33.3 keV and 9.5 keV mono X-rays for three-dimensional computerized tomography. The results of these tests are presented.

  1. Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors

    NASA Astrophysics Data System (ADS)

    Cortes, I.; Fernández-Martínez, P.; Flores, D.; Hidalgo, S.; Rebollo, J.

    2008-09-01

    The benefits of applying the shallow trench isolation (STI) concept to a higher voltage thin-SOI laterally diffused metal oxide semiconductor (LDMOS) (in the range of 80 V) are analysed in this paper by means of 2D technology computer-aided design (TCAD) numerical simulations. The TCAD simulation results allow comparing the electrical performance of the studied STI LDMOS structure with that of a conventional LDMOS in terms of the main static (breakdown voltage (VBR) and specific on-state resistance (RON-sp)) and dynamic (gate-drain capacitance (CGD) and cut-off frequency (fT)) characteristics. Moreover, the impact of the STI length (LSTI) and thickness (TSTI), and the N-drift implantation energy on the electrical characteristics is considered in detail. On the other hand, the STI block helps to move the harmful high electric field further away from the silicon surface, thus minimizing gate-oxide degradation by hot carriers.

  2. Monolithic optical phased-array transceiver in a standard SOI CMOS process.

    PubMed

    Abediasl, Hooman; Hashemi, Hossein

    2015-03-01

    Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

  3. Monolithic optical phased-array transceiver in a standard SOI CMOS process.

    PubMed

    Abediasl, Hooman; Hashemi, Hossein

    2015-03-01

    Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system. PMID:25836869

  4. Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

  5. Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad; Dones, Keishla Rivera

    2009-01-01

    Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing

  6. Design, simulation, and fabrication of a 90° SOI optical hybrid based on the self-imaging principle

    NASA Astrophysics Data System (ADS)

    Abdul-Majid, Sawsan; Hasan, Imad I.; Bock, Przemek J.; Hall, Trevor J.

    2010-05-01

    This paper introduces a compact 90º optical hybrid, built on small size SOI waveguide technology .This optical hybrid is a critical component of a potentially low-cost coherent optical receiver design developed within the frame of our Optical Coherent Transmission for Access Network Extensions (OCTANE) project. In previous recent work, 90º optical hybrids were realized in SOI rib waveguide technology with 4 μm top silicon and a rib height of approximately 2 μm. In this paper, we introduce a compact 90º optical hybrid, built on small size SOI waveguide technology (1.5 μm SOI -based rib waveguide, with 0.8μm rib height). The proposed device consists of multimode interferometers (MMIs) connected in such a way that four different vector additions of a reference signal (local oscillator) and the signal to be detected are obtained. At the outputs, the hybrid provides four linear combination of the signal with the reference which differs by a relative phase shift of the reference of 90º. The four output signals are detected by a pair of balanced receivers to provide in-phase and quadrature (I&Q) channels. The phase differences arise naturally from the self imaging property of a MMI. The key elements of the 90º optical hybrid, including a 2×2 MMI, a 4×4 MMI, and polarization diversity configuration have been designed and simulated, using the numerical mode solving tool FIMMPROB. The 2×2 and 4×4 MMI had overall lengths of 701μm and 3712.5μm lengths respectively. Tapers are used to couple adiabatically single mode waveguides to the entrance and exit ports of the MMI to assure correct operation by avoiding coupling to the higher order transverse modes allowed at the entrance and exit ports of the MMI. The simulation results at 1550nm show polarization independence and phase errors between the ports of less than 0.03 degrees. Currently the design is in fabrication at the Canadian Photonics Fabrication Center with the support of CMC Microsystems and experimental

  7. Using SST, PDO and SOI for Streamflow Reconstruction

    NASA Astrophysics Data System (ADS)

    Bukhary, S. S.; Kalra, A.; Ahmad, S.

    2015-12-01

    Recurring droughts in southwestern U.S. particularly California, have strained the existing water reserves of the region. Frequency, severity and duration of these recurring drought events may not be captured by the available instrumental records. Thus streamflow reconstruction becomes imperative to identify the historic hydroclimatic extremes of a region and assists in developing better water management strategies, vital for sustainability of water reserves. Tree ring chronologies (TRC) are conventionally used to reconstruct streamflows, since tree rings are representative of climatic information. Studies have shown that sea surface temperature (SST) and climate indices of southern oscillation index (SOI) and pacific decadal oscillation (PDO) influence U.S. streamflow volumes. The purpose of this study was to improve the traditional reconstruction methodology by incorporating the oceanic-atmospheric variables of PDO, SOI, and Pacific Ocean SST, alongwith TRC as predictors in a step-wise linear regression model. The methodology of singular value decomposition was used to identify teleconnected regions of streamflow and SST. The approach was tested on eleven gage stations in Sacramento River Basin (SRB) and San Joaquin River Basin (JRB). The reconstructions were successfully generated from 1800-1980, having an overlap period of 1932-1980. Improved results were exhibited when using the predictor variable of SST along with TRC (calibration r2=0.6-0.91) compared to when using TRC in combination with SOI and PDO (calibration r2=0.51-0.78) or when using TRC by itself (calibration r2=0.51-0.86). For future work, this approach can be replicated for other watersheds by using the oceanic-atmospheric climate variables influencing that region.

  8. SOI CMOS Imager with Suppression of Cross-Talk

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  9. SOI/MDI studies of active region seismology and evolution

    NASA Technical Reports Server (NTRS)

    Tarbell, Ted D.; Title, Alan; Hoeksema, J. Todd; Scherrer, Phil; Zweibel, Ellen

    1995-01-01

    The solar oscillations investigation (SOI) will study solar active regions using both helioseismic and conventional observation techniques. The Michelson Doppler imager (MDI) can perform Doppler continuum and line depth imagery and can produce longitudinal magnetograms, showing either the full disk or a high resolution field of view. A dynamics program of continuous full disk Doppler observations for two months per year, campaign programs of eight hours of continuous observation per day, and a synoptic magnetic program of about 15 full disk magnetograms per day, are planned. The scientific plans, measurements and observation programs, are described.

  10. Improving breakdown voltage performance of SOI power device with folded drift region

    NASA Astrophysics Data System (ADS)

    Qi, Li; Hai-Ou, Li; Ping-Jiang, Huang; Gong-Li, Xiao; Nian-Jiong, Yang

    2016-07-01

    A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V. Project supported by the Guangxi Natural Science Foundation of China (Grant Nos. 2013GXNSFAA019335 and 2015GXNSFAA139300), Guangxi Experiment Center of Information Science of China (Grant No. YB1406), Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China, Key Laboratory of Cognitive Radio and Information Processing (Grant No. GXKL061505), Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China (Grant No. 2014KFMS04), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

  11. Reducing the temperature sensitivity of SOI waveguide-based biosensors

    NASA Astrophysics Data System (ADS)

    Gylfason, Kristinn B.; Mola Romero, Albert; Sohlström, Hans

    2012-06-01

    Label-free photonic biosensors fabricated on silicon-on-insulator (SOI) can provide compact size, high evanescent field strength at the silicon waveguide surface, and volume fabrication potential. However, due to the large thermo optic coefficient of water-based biosamples, the sensors are temperature-sensitive. Consequently, active temperature control is usually used. However, for low cost applications, active temperature control is often not feasible. Here, we use the opposite polarity of the thermo-optic coefficients of silicon and water to demonstrate a photonic slot waveguide with a distribution of power between sample and silicon that aims to give athermal operation in water. Based on simulations, we made three waveguide designs close to the athermal point, and asymmetric integrated Mach- Zehnder interferometers for their characterization. The devices were fabricated on SOI with a 220 nm device layer and 2 μm buried oxide, by electron beam lithography of hydrogen silsesquioxane (HSQ) resist, and etching in a Cl2/HBr/O2/He plasma. With Cargile 50350 fused silica matching oil as top cladding, the group index of the three guides varies from 1.9 to 2.8 at 1550 nm. The temperature sensitivity of the devices varied from -70 to -160 pm/K under the same conditions. A temperature sensitivity of -2 pm/K is projected with water as top cladding.

  12. Investigation of a radiation-hardened quasi-SOI device: performance degradation induced by single ion irradiation

    NASA Astrophysics Data System (ADS)

    Wu, Weikang; An, Xia; Que, Taotao; Zhang, Xing; Shen, Dongjun; Guo, Gang; Huang, Ru

    2016-10-01

    In this paper, performance degradation after heavy-ion irradiation in novel quasi-SOI devices are investigated and compared with bulk Si MOSFETs through experiment and simulation. A quasi-SOI device is characterized with an L-type insulator surrounding the source and drain regions. The I-V characteristic of the quasi-SOI device may degrade after heavy-ion irradiation and the degradation phenomena are demonstrated and statistically analyzed. The results show that compared with bulk Si devices, quasi-SOI devices illustrate a reduced performance degradation induced by heavy-ion irradiation. Therefore, quasi-SOI devices are promising candidates for future space applications.

  13. Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI

    NASA Astrophysics Data System (ADS)

    Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander

    2016-03-01

    In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The inherent benefits of the low-granularity body-bias control, provided by the GLBB approach, are emphasized by the efficiency of forward body bias (FBB) in the FD-SOI technology. In addition, the possibility to integrate PMOS and NMOS devices into a single common well configuration allows significant area reduction, as compared to an equivalent triple well implementation. Some arithmetic circuits were designed using GLBB approach and compared to their conventional CMOS and DTMOS counterparts under different running conditions at low voltage regime. Simulation results shows that, for 300 mV of supply voltage, a 4 × 4-bit GLBB Baugh Wooley multiplier allows performance improvement of about 30% and area reduction of about 35%, while maintaining low energy consumption as compared to the conventional CMOS ⧹ DTMOS solutions. Performance and energy benefits are maintained over a wide range of process-voltage-temperature (PVT) variations.

  14. Dynamics Explorer 1 SOI images of the Antarctic ozone hole

    NASA Technical Reports Server (NTRS)

    Keating, G. M.; Bressette, W. E.; Chen, C.; Pitts, M. C.; Craven, J.

    1988-01-01

    The Dynamics Explorer (DE) satellite carries an Auroral Imaging Package which contains filters designed for performing backscatter ultraviolet measurements to measure total column ozone in the Earth's middle and lower atmosphere. Measurements are obtained at 317.5 mm (to measure ozone absorption) and 360 nm (to measure scene reflectivity). In October 1985 and 1986, measurements were obtained near apogee of the Antarctic ozone hole. The only other high spatial resolution measurements were obtained from the Nimbus 7 Total Ozone Mapping Spectrometer (TOMS) experiment. In October 1987, the Dynamics Explorer apogee had precessed into the Northern Hemisphere preventing measurements of the ozone hole. However, measurements should be obtained from DE of the ozone hole in both 1988 and 1989. Considering that the Nimbus 7 TOMS instrument has long exceeded its expected lifetime, the DE Spin Scan Ozone Imager (SOI) experiment could easily play a crucial role in studies of the ozone hole over the next few years.

  15. Magnetoresistance mobility characterization in advanced FD-SOI n-MOSFETs

    NASA Astrophysics Data System (ADS)

    Shin, Minju; Shi, Ming; Mouis, Mireille; Cros, Antoine; Josse, Emmanuel; Mukhopadhyay, Sutirha; Piot, Benjamin; Kim, Gyu-Tae; Ghibaudo, Gérard

    2015-01-01

    In this work, we applied the magnetoresistance (MR) characterization technique on n-type FD-SOI devices from a 14 nm-node technology. A notable advantage of MR is that it can probe the sub-threshold region, where Coulomb scattering influence is unscreened, while classical methods are validated to the strong inversion regime. At first, we discuss the influence of series resistance depending on gate bias, gate stack and temperature in this technology. Secondly, for long channel devices, we show that Coulomb scattering plays no significant role below threshold voltage at room temperature, in spite of the presence of a high-k/metal gate stack. MR-mobility (μMR) measurements were also performed in interface coupling conditions in order to further assess the role of the high-k/metal gate stack on transport properties and to analyze back bias induced mobility variations, depending on temperature range. Finally, the comparative study of low field effective mobility (μ0) and μMR shows that critical gate length of mobility degradation can be overestimated by using μ0 at low temperature due to a lack of ability of Y-function method to capture unscreened Coulomb scattering.

  16. The Dwell Time of Electron Tunneling Through a Double Barrier in the Presence of Rashba SOI

    SciTech Connect

    Baltateanu, Doru-Marcel

    2011-10-03

    Some aspects related to the influence of the Rashba spin-orbit interaction (SOI) on the dwell time spent by the electrons in an asymmetric double barrier are analyzed. It is revealed that in the presence of the Rashba SOI, a difference between the dwell times associated to the spin-up and spin-down species can be obtained. This opens the way to a spin filtration in the time domain.

  17. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

  18. Higher-Order Factors in Structure-of-Intellect (SOI) Aptitude Tests Hypothesized to Portray Constructs of Military Leadership: A Re-analysis of an SOI Data Base.

    ERIC Educational Resources Information Center

    Ulosevich, Steven N.; And Others

    1991-01-01

    A correlation matrix of 21 structure-of-intellect (SOI) tests taken by 204 Marine officers at a military base in Southern California, which was intended to reflect aptitudes for military leadership, was reanalyzed through exploratory factor analysis and confirmatory maximum likelihood factor analysis. Higher order factors appeared to have…

  19. Compensation for radiation damage of SOI pixel detector via tunneling

    NASA Astrophysics Data System (ADS)

    Yamada, M.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Ikegami, Y.; Kurachi, I.; Miyoshi, T.; Nishimura, R.; Tauchi, K.; Tsuboyama, T.

    2016-09-01

    We are developing a method for removing holes trapped in the oxide layer of a silicon-on-insulator (SOI) monolithic pixel detector after irradiation. Radiation that passes through the detector generates positive charge by trapped holes in the buried oxide layer (BOX) underneath the MOSFET. The positive potential caused by these trapped holes modifies the characteristics of the MOSFET of the signal readout circuit. In order to compensate for the effect of the positive potential, we tried to recombine the trapped holes with electrons via Fowler-Nordheim (FN) tunneling. By applying high voltage to the buried p-well (BPW) under the oxide layer with the MOSFET fixed at 0 V, electrons are injected into the BOX by FN tunneling. X-rays cause a negative shift in the threshold voltage Vth of the MOSFET. We can successfully recover Vth close to its pre-irradiation level after applying VBPW ≥ 120 V. However, the drain leakage current increased after applying VBPW; we find that this can be suppressed by applying a negative voltage to the BPW.

  20. In situ characterization of PDMS in SOI-MEMS

    NASA Astrophysics Data System (ADS)

    Gerratt, Aaron P.; Penskiy, Ivan; Bergbreiter, Sarah

    2013-04-01

    This paper presents the in situ characterization of microscale poly(dimethylsiloxane) (PDMS) springs using silicon-on-insulator-microelectromechanical systems (SOI-MEMS). PDMS samples that were 30 μm long, 20 μm thick, and 6 μm wide were fabricated on-chip along with a test mechanism that included electrostatic comb drive actuators and silicon flexures. The test mechanism allowed for applying strains up to 65%. The in situ test results were compared with results of tests on macroscale samples performed using a dynamic mechanical analyzer. The results imply that the process steps during fabrication initially led to increased crosslinking of the PDMS but that the final release of the structure in buffered hydrofluoric acid decreased the crosslink density, thereby decreasing the stiffness of the PDMS. Several implications of the results on processing PDMS in MEMS are presented. The results of this work are important for the design of MEMS devices which incorporate PDMS as a mechanical material.

  1. High performance SOI microring resonator for biochemical sensing

    NASA Astrophysics Data System (ADS)

    Ciminelli, C.; Dell'Olio, F.; Conteduca, D.; Campanella, C. M.; Armenise, M. N.

    2014-07-01

    In this work we have investigated different silicon-on-insulator (SOI) microcavities based on a planar geometry having a footprint on chip as small as 100 μm2 with a ring, disk and hybrid configurations with the aim of being poorly intrusive for both in-body and out-of-body biosensing purposes. Accurate numerical results have been achieved by using the 3D finite element method and compared to 3D finite discrete time domain ones with a good agreement for both methods. The most promising resonator among the devices we have analyzed shows a Q-factor of the order of 105, that allows a limit of detection for the sensor equal to 10-6 RIU and a sensor sensitivity of 120 nm/RIU. The resonator has been designed for glucose biosensing, considering both the homogeneous sensing and the surface one, that enhances the sensor selectivity by the device functionalization with a glucose-oxidase (GOD) layer. The glucose concentration has been evaluated both with the microcavity surrounded by a water solution and with water only in the inner part of the cavity.

  2. Scaling issues for analogue circuits using Double Gate SOI transistors

    NASA Astrophysics Data System (ADS)

    Lim, Tao Chuan; Armstrong, G. Alastair

    2007-02-01

    This work presents a systematic analysis on the impact of source-drain engineering using gate "non-overlapped" on the RF performance of nano-scaled fully depleted Double Gate SOI transistors, when used in the design of a typical two stage Operational Transconductance Amplifier (OTA). It is evident that for a gate length less than 40 nm, the incorporation of optimal source-drain engineering requiring a spacer length, which may exceed the length of the gate, is particularly beneficial in analogue applications. Lengthening the spacer reduces gate capacitance in the weak/moderate inversion region more than transconductance, improving cut-off frequency fT. This improvement is particularly significant in a circuit application where an optimal spacer of 1.5 times the gate length is proposed. This gate under-lapped concept with extended spacer can also significantly enhance DC gain of the OTA, by increasing the Early Voltage, while maximising the transconductance to current ratio in the weak to moderate inversion, close to threshold voltage. With optimally designed devices, the sensitivity of OTA circuit performance to doping profile is shown to be relatively low.

  3. Rad-hard vertical JFET switch for the HV-MUX system of the ATLAS upgrade Inner Tracker

    NASA Astrophysics Data System (ADS)

    Fernández-Martínez, P.; Ullán, M.; Flores, D.; Hidalgo, S.; Quirion, D.; Lynn, D.

    2016-01-01

    This work presents a new silicon vertical JFET (V-JFET) device, based on the trenched 3D-detector technology developed at IMB-CNM, to be used as a switch for the High-Voltage powering scheme of the ATLAS upgrade Inner Tracker. The optimization of the device characteristics is performed by 2D and 3D TCAD simulations. Special attention has been paid to the on-resistance and the switch-off and breakdown voltages to meet the specific requirements of the system. In addition, a set of parameter values has been extracted from the simulated curves to implement a SPICE model of the proposed V-JFET transistor. As these devices are expected to operate under very high radiation conditions during the whole experiment life-time, a study of the radiation damage effects and the expected degradation of the device performance is also presented at the end of the paper.

  4. Higher-Order Abilities Conceptualized within Guilford's Structure-of-Intellect (SOI) Model for a Sample of United States Coast Guard Academy Cadets: A Reanalysis of an SOI Data Base.

    ERIC Educational Resources Information Center

    Chen, Chin-Yi; Michael, William B.

    1993-01-01

    Empirical validation of the first-order and higher-order factor structures of the structure-of-intellect (SOI) model was provided by reanalysis of a database of 39 measures administered to 178 Coast Guard Cadets. Results suggest that SOI could be reconceptualized as a pyramid-like hierarchical theory of intelligence. (SLD)

  5. An area efficient body contact for low and high voltage SOI MOSFET devices

    NASA Astrophysics Data System (ADS)

    Daghighi, Arash; Osman, Mohamed; Imam, Mohamed A.

    2008-02-01

    A simple and high-performance area efficient body-tied-source (BTS) contact for SOI MOSFET is presented. By simple modification to the physical layout and without introducing any increase to the fabrication process steps, the proposed body contact can be implemented. Three-dimensional (3D) non-isothermal simulation on SOI CMOS devices showed higher current drive while floating body effects were completely suppressed. In addition, improved performance is achieved when comparing on-resistance (RON) and breakdown voltage (VBR) with the conventional BTS structures. The new body contact structure is applicable to both low and high voltage (planar or trench) SOI and bulk devices. Experimental results obtained from fabricated bulk MOSFET devices utilizing the proposed body contact structure agreed well with the simulation findings.

  6. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    NASA Astrophysics Data System (ADS)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  7. A novel high-performance high-frequency SOI MESFET by the damped electric field

    NASA Astrophysics Data System (ADS)

    Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

    2016-06-01

    In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

  8. Instrument Technology Development: Key Enabling-Technologies for the Future of Planetary Science

    NASA Astrophysics Data System (ADS)

    Hoffman, J. P.; Piepmeier, J. R.

    2001-11-01

    What are the enabling technologies for the next decade of planetary exploration? The Instrumentation Technology Development Panel (ITD) is working to identify the areas of recent innovation and continuing deficiency in instrument technology as it pertains to planetary science goals and missions. Collaboration between science and technology aspects of all planetary science disciplines is crucial to the success of this task. While it is obvious that mission success, even mission plausibility, is strongly dependent on technical capability, it is, perhaps, less obvious that improvements in technology can also lead to a greater number and/or new types of missions. Therefore, we are interested not only in identifying new types of instrumentation, but also in improving existing (even mature) technologies by reducing size, complexity, and cost. Improvements of this type not only lower mission costs, but also enable more complex instrument suites to be considered for advanced data fusion measurement concepts. We need to identify the short-term and long-term technological needs (new instruments) and bottlenecks (better instruments) for each of the planetary science disciplines and we need input from every discipline to do this. Certain disciplines may feel little pressure to invest time and money into ITD since their instruments are mature. However, if mature technologies can be made less expensive and smaller, more opportunities for science will become available by enabling previously impossible secondary mission instruments. Currently identified areas requiring technology development: - Deployable large (10's of meters) microwave antennas - FIR (sub/mmwave) detectors and antennas - Extreme-temperature semiconductors for Venus (high-temp), Titan (low-temp) - Low power rad-hard electronics - Rad-hard on-board processing power - Increased DSN capacity - Optical interplanetary communications - Lightweight deployable optics - Lightweight, inexpensive, in-situ atmospheric probes

  9. A photonic crystal ring resonator formed by SOI nano-rods.

    PubMed

    Chiu, Wei-Yu; Huang, Tai-Wei; Wu, Yen-Hsiang; Chan, Yi-Jen; Hou, Chia-Hunag; Chien, Huang Ta; Chen, Chii-Chang

    2007-11-12

    The design, fabrication and measurement of a silicon-on-insulator (SOI) two-dimensional photonic crystal ring resonator are demonstrated in this study. The structure of the photonic crystal is comprised of silicon nano-rods arranged in a hexagonal lattice on an SOI wafer. The photonic crystal ring resonator allows for the simultaneous separation of light at wavelengths of 1.31 and 1.55mum. The device is fabricated by e-beam lithography. The measurement results confirm that a 1.31mum/1.55mum wavelength ring resonator filter with a nano-rod photonic crystal structure can be realized. PMID:19550835

  10. ENVIRONMENTAL TECHNOLOGY VERIFICATION REPORT: IMMUNOASSAY KIT, ENVIROLOGIX, INC., PCB IN SOIL TUBE ASSAY

    EPA Science Inventory

    In July 1997, the U.S. Environmental Protection Agency (EPA) conducted a demonstration of polychlorinated biphenyl (PCB) field analytical techniques. The purpose of this demonstration was to evaluate field analytical technologies capable of detecting and quantifying PCB's in soi...

  11. Symmetrical SOI MESFET with a dual cavity region (DCR-SOI MESFET) to promote high-voltage and radio-frequency performances

    NASA Astrophysics Data System (ADS)

    Anvarifard, Mohammad K.

    2016-10-01

    A novel symmetrical SOI-MESFET is reported to enhance high-voltage and radio-frequency performances, successfully. Two p-type cavity regions with certain features are embedded in the proposed structure to control the channel region. The cavity regions absorb the channel potential lines resulting in an evener potential profile throughout the channel region. Hence, the critical electric field at the end of gate edge near the drain will be considerably reduced thus increasing the breakdown voltage, finally. A comprehensive comparison in terms of breakdown voltage, radio-frequency parameters, drain-source conductance and minimum noise figure shows that the reported new device reaches a superior electrical performance when compared with a conventional SOI MESFET.

  12. GSFC Cutting Edge Avionics Technologies for Spacecraft

    NASA Technical Reports Server (NTRS)

    Luers, Philip J.; Culver, Harry L.; Plante, Jeannette

    1998-01-01

    With the launch of NASA's first fiber optic bus on SAMPEX in 1992, GSFC has ushered in an era of new technology development and insertion into flight programs. Predating such programs the Lewis and Clark missions and the New Millenium Program, GSFC has spearheaded the drive to use cutting edge technologies on spacecraft for three reasons: to enable next generation Space and Earth Science, to shorten spacecraft development schedules, and to reduce the cost of NASA missions. The technologies developed have addressed three focus areas: standard interface components, high performance processing, and high-density packaging techniques enabling lower cost systems. To realize the benefits of standard interface components GSFC has developed and utilized radiation hardened/tolerant devices such as PCI target ASICs, Parallel Fiber Optic Data Bus terminals, MIL-STD-1773 and AS1773 transceivers, and Essential Services Node. High performance processing has been the focus of the Mongoose I and Mongoose V rad-hard 32-bit processor programs as well as the SMEX-Lite Computation Hub. High-density packaging techniques have resulted in 3-D stack DRAM packages and Chip-On-Board processes. Lower cost systems have been demonstrated by judiciously using all of our technology developments to enable "plug and play" scalable architectures. The paper will present a survey of development and insertion experiences for the above technologies, as well as future plans to enable more "better, faster, cheaper" spacecraft. Details of ongoing GSFC programs such as Ultra-Low Power electronics, Rad-Hard FPGAs, PCI master ASICs, and Next Generation Mongoose processors.

  13. Multiple-layer SOI based on Single-Crystal Si Nanomembrane Transfer

    NASA Astrophysics Data System (ADS)

    Peng, Weina; Roberts, Michelle; Nordberg, Eric; Flack, Frank; Colavita, Paula; Hamers, Robert; Savage, Donald; Lagally, Max; Eriksson, Mark

    2007-03-01

    Silicon-on-insulator (SOI) has many advantages over bulk Si including the reduction of parasitic resistance and increased device speed. Multiple-layer SOI, having more device layers per unit area, enables 3D process integration as well as applications in optics. However, it is impossible to achieve such a system by growth techniques (one can grow only non-crystalline Si on SiO2), and multiple Smart Cut transfers used to create single layer SOI may be prohibitively expensive. We present here a novel method to fabricate such a multiple SOI system using transferred Si nanomembranes^ and subsequent oxidation. The surface roughness and interface quality are examined respectively by AFM and cross-sectional SEM. Low surface roughness (0.176nm) and smooth interfaces are achieved. As an example optical application, we apply the multilayer system to fabricate a Si-based Bragg reflector. The specular reflectivity of one, two, and three-membrane mirrors is measured using FTIR. High specular reflectivity, above 99%, is achieved for three stacked membranes. Comparison of the measured reflectivity with theoretical calculations shows good agreement.

  14. A novel four-quadrant analog multiplier using SOI four-gate transitors (G4-FETs)

    NASA Technical Reports Server (NTRS)

    Akarvardar, K.; Chen, S.; Blalock, B. J.; Cristoloveanu, S.; Gentil, P.; Mojarradi, M.

    2005-01-01

    A novel analog muliplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers.

  15. Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

    NASA Technical Reports Server (NTRS)

    Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

    2007-01-01

    We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

  16. A novel mechanism of ultrathin SOI synthesis by extremely low-energy hot O+ implantation

    NASA Astrophysics Data System (ADS)

    Hoshino, Yasushi; Yachida, Gosuke; Inoue, Kodai; Toyohara, Taiga; Nakata, Jyoji

    2016-08-01

    Extremely low-energy oxygen implantations at 10 keV in silicon were challengingly performed to directly synthesize ultrathin silicon-on-insulator (SOI) structure separated by a buried oxide (BOX) layer. We quantitatively investigated the optimum condition and the formation mechanism of homogeneous and continuous stoichiometric SOI/BOX structure. In this study, oxygen ions were implanted into Si(0 0 1) substrates with keeping the temperatures at 500, 800, and 1000 °C with ion-fluences from 0.5 to 2.0× {{10}17} ions cm-2. These samples were then postannealed at high temperatures from 950 to 1150 °C in Ar ambient for several hours. We found that ultrathin stoichiometric SOI/BOX structure with less than 20 nm thick was synthesized by oxygen implantation with an ion dose of 1.0× {{10}17} ions cm-2 from 500 °C to 800 °C followed by annealing at a significantly low temperature of 1050 °C for 5 h. According to the RBS-channeling analysis, the crystallinity was excellent as quality as that of the SOI structure formed by a wafer-bonding method. We found that the BOX layer was finally formed around the deeper end of the oxygen distribution in the as-implanted sample, though the depth of the BOX formation was much deeper than the projected range of oxygen and the damage peak of silicon. The formation process of the SOI/BOX structure proposed so far could not be applicable to the present conditions for ultrathin SOI/BOX synthesis by extremely low-energy implantation followed by low-temperature annealing. We thus suggested a novel mechanism of the ultrathin SOI/BOX synthesis as follows. The mechanism during the thermal treatment was demonstrated that the recrystallization of the damaged Si layers induced by ion irradiation took place from the very surface with relatively less irradiation-damages toward deeper layers with sweeping interstitial oxygen atoms, and the condensed oxygen atoms finally synthesized the stoichiometric BOX layer.

  17. A novel mechanism of ultrathin SOI synthesis by extremely low-energy hot O+ implantation

    NASA Astrophysics Data System (ADS)

    Hoshino, Yasushi; Yachida, Gosuke; Inoue, Kodai; Toyohara, Taiga; Nakata, Jyoji

    2016-08-01

    Extremely low-energy oxygen implantations at 10 keV in silicon were challengingly performed to directly synthesize ultrathin silicon-on-insulator (SOI) structure separated by a buried oxide (BOX) layer. We quantitatively investigated the optimum condition and the formation mechanism of homogeneous and continuous stoichiometric SOI/BOX structure. In this study, oxygen ions were implanted into Si(0 0 1) substrates with keeping the temperatures at 500, 800, and 1000 °C with ion-fluences from 0.5 to 2.0× {{10}17} ions cm‑2. These samples were then postannealed at high temperatures from 950 to 1150 °C in Ar ambient for several hours. We found that ultrathin stoichiometric SOI/BOX structure with less than 20 nm thick was synthesized by oxygen implantation with an ion dose of 1.0× {{10}17} ions cm‑2 from 500 °C to 800 °C followed by annealing at a significantly low temperature of 1050 °C for 5 h. According to the RBS-channeling analysis, the crystallinity was excellent as quality as that of the SOI structure formed by a wafer-bonding method. We found that the BOX layer was finally formed around the deeper end of the oxygen distribution in the as-implanted sample, though the depth of the BOX formation was much deeper than the projected range of oxygen and the damage peak of silicon. The formation process of the SOI/BOX structure proposed so far could not be applicable to the present conditions for ultrathin SOI/BOX synthesis by extremely low-energy implantation followed by low-temperature annealing. We thus suggested a novel mechanism of the ultrathin SOI/BOX synthesis as follows. The mechanism during the thermal treatment was demonstrated that the recrystallization of the damaged Si layers induced by ion irradiation took place from the very surface with relatively less irradiation-damages toward deeper layers with sweeping interstitial oxygen atoms, and the condensed oxygen atoms finally synthesized the stoichiometric BOX layer.

  18. Novel spot size converter for coupling standard single mode fibers to SOI waveguides

    NASA Astrophysics Data System (ADS)

    Sisto, Marco Michele; Fisette, Bruno; Paultre, Jacques-Edmond; Paquet, Alex; Desroches, Yan

    2016-03-01

    We have designed and numerically simulated a novel spot size converter for coupling standard single mode fibers with 10.4μm mode field diameter to 500nm × 220nm SOI waveguides. Simulations based on the eigenmode expansion method show a coupling loss of 0.4dB at 1550nm for the TE mode at perfect alignment. The alignment tolerance on the plane normal to the fiber axis is evaluated at +/-2.2μm for <=1dB excess loss, which is comparable to the alignment tolerance between two butt-coupled standard single mode fibers. The converter is based on a cross-like arrangement of SiOxNy waveguides immersed in a 12μm-thick SiO2 cladding region deposited on top of the SOI chip. The waveguides are designed to collectively support a single degenerate mode for TE and TM polarizations. This guided mode features a large overlap to the LP01 mode of standard telecom fibers. Along the spot size converter length (450μm), the mode is first gradually confined in a single SiOxNy waveguide by tapering its width. Then, the mode is adiabatically coupled to a SOI waveguide underneath the structure through a SOI inverted taper. The shapes of SiOxNy and SOI tapers are optimized to minimize coupling loss and structure length, and to ensure adiabatic mode evolution along the structure, thus improving the design robustness to fabrication process errors. A tolerance analysis based on conservative microfabrication capabilities suggests that coupling loss penalty from fabrication errors can be maintained below 0.3dB. The proposed spot size converter is fully compliant to industry standard microfabrication processes available at INO.

  19. Simulation of ultra thin film SOI transistors using a non-local ballistic model for impact ionisation

    NASA Astrophysics Data System (ADS)

    Armstrong, G. A.; French, W. D.

    1992-12-01

    To model bipolar snapback in thin film SOI transistors accurately, it is necessary to employ a non-local model of impact ionisation. Such a model, based on the "Lucky electron" theory, has been incorporated in a two-dimensional device simulator. Accurate prediction of bipolar holding voltage has been obtained for SOI transistors with sub-micron gate lengths. The model has been applied to analyse separately the effects of both lightly doped source and lightly doped drain in maximising the holding voltage. The advantage of using ultra thin highly doped SOI films in conjunction with a lightly doped drain is discussed.

  20. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

    NASA Astrophysics Data System (ADS)

    Fengying, Qiao; Liyang, Pan; Dong, Wu; Lifang, Liu; Jun, Xu

    2014-02-01

    In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode.

  1. Suppression of 1/f Noise in Accumulation Mode FD-SOI MOSFETs on Si(100) and (110) Surfaces

    SciTech Connect

    Cheng, W.; Gaubert, P.; Teramoto, A.; Tye, C.; Sugawa, S.; Ohmi, T.

    2009-04-23

    In this paper, a new approach to reduce the 1/f noise levels in the MOSFETs on varied silicon orientations, such as Si(100) and (110) surfaces, has been carried out. We focus on the Accumulation-mode (AM) FD-SOI device structure and demonstrate that the 1/f noise levels in this AM FD-SOI MOSFETs are obviously reduced on both the Si(100) and (110) surfaces.

  2. Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer

    NASA Astrophysics Data System (ADS)

    Hu, Shengdong; Luo, Jun; Jiang, YuYu; Cheng, Kun; Chen, Yinhui; Jin, Jingjing; Wang, Jian'an; Zhou, Jianlin; Tang, Fang; Zhou, Xichuan; Gan, Ping

    2016-03-01

    A novel SOI LDMOS with a partial compound buried layer structure (P-CBL SOI) is proposed in this paper. The buried oxide layer at the source-side is replaced by a compound buried layer (CBL) of "top oxide-middle polysilicon-bottom oxide", and the buried oxide layer at the drain-side is just as the conventional SOI LDMOS (C-SOI). Firstly, a new peak of electric field is introduced at the interface and the whole lateral electric field in the top silicon layer is modulated, resulting in a higher lateral BV. Secondly, impurity doping meeting the RESURF effect in the top silicon layer is higher because the top oxide is thinner than the conventional buried oxide layer, leading to a lower Ron,sp at the on-state and an enhanced vertical BV at the off-state. Finally, thermal conductivity of polysilicon is higher than that of SiO2, offering a lower self-heating effect. The influences of structure parameters on the devices performances are investigated. Compared with those of C-SOI LDMOS on the same top silicon layer of 4 μm, buried dielectric layer of 4 μm, and drift region of 40 μm, BV of P-CBL SOI LDMOS is enhanced by 33.4%, Ron,sp is reduced by 37.4%, and the maximum temperature at the power of 1 mW/μm is depressed by 13.3 K, respectively.

  3. Fabrication of capacitive absolute pressure sensor using Si-Au eutectic bonding in SOI wafer

    NASA Astrophysics Data System (ADS)

    Ryeol Lee, Kang; Kim, Kunnyun; Park, Hyo-Derk; Kim, Yong Kook; Choi, Seung-Woo; Choi, Woo-Beom

    2006-04-01

    A capacitive absolute pressure sensor was fabricated using a large deflected diaphragm with a sealed vacuum cavity formed by removing handling silicon wafer and oxide layers from a SOI wafer after eutectic bonding of a silicon wafer to the SOI wafer. The deflected displacements of the diaphragm formed by the vacuum cavity in the fabricated sensor were similar to simulation results. Initial capacitance values were about 2.18pF and 3.65pF under normal atmosphere, where the thicknesses of the diaphragm used to fabricate the vacuum cavity were 20 µm and 30 µm, respectively. Also, it was confirmed that the differences of capacitance value from 1000hPa to 5hPa were about 2.57pF and 5.35pF, respectively.

  4. [SOI-nanowire biosensor for the detection of D-NFAT 1 protein].

    PubMed

    Malsagova, K A; Ivanov, Yu D; Pleshakova, T O; Kozlov, A F; Krohin, N V; Kaysheva, A L; Shumov, I D; Popov, V P; Naumova, O V; Fomin, B I; Nasimov, D A

    2015-01-01

    The nanowire (NW) detection is one of fast-acting and high-sensitive methods allowing to reveal potentially relevant protein molecules. A NW biosensor based on the silicon-on-insulator (SOI)-structures was used for biospecific label-free detection of NFAT 1 (D-NFAT 1) oncomarker in real time. For this purpose, SOI-nanowires (NWs) were modified with aptamers against NFAT 1 used as molecular probes. It was shown that using this biosensor it is possible to reach the sensitivity of ~10(-15) M. This sensitivity was comparable with that of the NW biosensor with immobilized antibodies used as macromolecular probes. The results demonstrate promising approaches used to form the sensor elements for high-sensitive disease diagnostics.

  5. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging.

    PubMed

    Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

    2015-09-21

    This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  6. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET

    NASA Astrophysics Data System (ADS)

    Navarenho de Souza Fino, Leonardo; Davini Neto, Enrico; Aparecida Guazzelli da Silveira, Marcilei; Renaux, Christian; Flandre, Denis; Pinillos Gimenez, Salvador

    2015-10-01

    This paper performs an experimental comparative study of the total ionizing dose effects due to the x-ray radiation between the silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) manufactured with octagonal gate geometry and the standard counterpart. Our main focus is on integrated transceivers for wireless communications and smart-power dc/dc converters for mobile electronics, where the transistor is used as the key switching element. It is shown that this innovative layout can reduce the total ionizing dose (TID) effects due to the special characteristics of the OCTO SOI MOSFET bird’s beak regions, where longitudinal electrical field lines in these regions are not parallel to the drain and source regions. Consequently, the parasitic MOSFETs associated with these regions are practically deactivated.

  7. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    PubMed Central

    Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

    2015-01-01

    This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%. PMID:26402679

  8. Electron Pattern Recognition using trigger mode SOI pixel sensor for Advanced Compton Imaging

    NASA Astrophysics Data System (ADS)

    Shimazoe, K.; Yoshihara, Y.; Fairuz, A.; Koyama, A.; Takahashi, H.; Takeda, A.; Tsuru, T.; Arai, Y.

    2016-02-01

    Compton imaging is a useful method for localizing sub MeV to a few MeV gamma-rays and widely used for environmental and medical applications. The direction of recoiled electrons in Compton scattering process provides the additional information to limit the Compton cones and increases the sensitivity in the system. The capability of recoiled electron tracking using trigger-mode Silicon-On-Insulator (SOI) sensor is investigated with various radiation sources. The trigger-mode SOI sensor consists of 144 by 144 active pixels with 30 μm cells and the thickness of sensor is 500 μm. The sensor generates the digital output when it is hit by gamma-rays and 25 by 25 pixel pattern of surrounding the triggered pixel is readout to extract the recoiled electron track. The electron track is successfully observed for 60Co and 137Cs sources, which provides useful information for future electron tracking Compton camera.

  9. Investigation of the chip to photodetector coupler with subwavelength grating on SOI

    NASA Astrophysics Data System (ADS)

    Li, Hongqiang; Cui, Beibei; Liu, Yu; Liu, Hongwei; Zhang, Zanyun; Zhang, Cheng; Tang, Chunxiao; Li, Enbang

    2016-01-01

    We report on two kinds of investigation of the chip to photodetector coupler (CTPC) with uniform and blazed subwavelength grating (SWG) on silicon-on-insulator (SOI) that were conducted for silicon-based hybrid photodetector integration in an arrayed waveguide grating demodulation integrated microsystem. The theoretical model is presented, 3D FDTD and BPM simulations are used to optimize the coupler design. InP/InGaAs photodetector and SOI wafer were integrated through benzocyclobutene bonding. An efficient high-power absorption for TE mode in a broad band is achieved. The power absorption efficiencies of uniform and blazed SWGs in silicon-based hybrid photodetector integration at 1550 nm reach 73% and 75%, respectively in the simulation and it reaches as high as 25% in the measurement when coupling the TE-polarized 1550 nm light.

  10. Formation of SIMOX-SOI structure by high-temperature oxygen implantation

    NASA Astrophysics Data System (ADS)

    Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

    2015-12-01

    We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 1017-1018 ions/cm2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

  11. SOI-based high performance multi-subpart profile grating mirror

    NASA Astrophysics Data System (ADS)

    Huang, L.; Liang, D.; Zeng, J.; Xiao, Y.; Wu, H.; Xiao, W.

    2016-04-01

    In this study, a SOI-based high performance multi-subpart profile grating mirror (MPGM) is proposed and fabricated. It is shown that with the multi-subpart profile and strongly modulated thin grating layer, the MPGM experimentally demonstrated an ultra broadband reflection spectrum from 1.21 to1.62 μm, very high reflectivity (R>97%), and low sensitivity to incident angle at the range of -12.3°<θ<+13.1°.

  12. Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

    NASA Astrophysics Data System (ADS)

    Nigrin, S.; Armstrong, G. A.; Kranti, A.

    2007-09-01

    This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area.

  13. A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

    2008-01-01

    A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

  14. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

    2002-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  15. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    NASA Technical Reports Server (NTRS)

    Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

    2005-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  16. Foundry-compatible SOI waveguides with a graphene top layer for wideband wavelength conversion

    NASA Astrophysics Data System (ADS)

    Vermeulen, N.; Cheng, J. L.; Sipe, J. E.; Thienpont, H.

    2016-05-01

    The tremendous progress in the fabrication of highly confining silicon-on-insulator (SOI) waveguides has been very beneficial for four-wave-mixing (FWM)-based wavelength conversion applications. Nevertheless, to establish power-efficient and wideband FWM wavelength conversion, one typically requires long (cm-scale) SOI waveguides with dispersion-engineered cross-sections that do not comply with the fabrication constraints of multiproject- wafer-oriented silicon photonics foundries. In this paper, we numerically examine the opportunities for wideband wavelength conversion through FWM in a foundry-compatible SOI waveguide covered with the highly nonlinear two-dimensional material of graphene. When combining subwatt level pump powers with a short waveguide length of only a few hundreds of microns, perfectly phase-matched conversion with significant efficiencies close to 20 dB can be obtained over a more than 40 THz-wide signal band adjacent to the pump frequency. Because of the tunability of the graphene properties, it is also possible to obtain quasi-phase matched FWM conversion through a periodic sign reversal of the graphene third-order nonlinearity along the waveguide. Conversion efficiencies exceeding 30 dB can be achieved over a 3.4 THz-wide signal band that is situated as much as 58 THz away from the pump frequency. Finally, the graphene tunability also allows for switching between the perfectly phase-matched and quasi-phase-matched operation modes.

  17. Comparative study of NSB and UTB SOI MOSFETs characteristics by extraction of series resistance

    NASA Astrophysics Data System (ADS)

    Karsenty, A.; Chelly, A.

    2014-01-01

    The electrical characteristics of two kinds of n-type SOI-MOSFETs are analyzed and compared in order to build a consistent model. The first kind is an Ultra-Thin Body (UTB) device for which the channel thickness is equal to the initial SOI wafer thickness value (here 46 nm). The second kind is what we refer to Nano-Scale Body (NSB) device for which the initial SOI channel is thinned down to 1.6 nm using a recessed-gate process. The drain current values were found surprisingly different by three orders of magnitude. Such a huge contrast was not found coherent with the literature, reporting the decrease of the electron mobility with the channel thickness. We interpret our result by the probable influence of an extreme drain-to-source series resistance rather than by vanishing carrier mobility. The interpretation is sustained experimentally by the Rm-L and C-V methods. By integrating a gate-voltage dependence to the series resistance, the linear and saturation regions of the output characteristics of the NSB can be analytically derived from the UTB ones. This simple modeling approach may be useful to interpret anomalous electrical behavior of other nano-devices in which series resistance is of a great concern.

  18. Features of SOI substrates heating in MBE growth process obtained by low-coherence tandem interferometry

    NASA Astrophysics Data System (ADS)

    Volkov, P. V.; Goryunov, A.. V.; Lobanov, D. N.; Luk'yanov, A. Yu.; Novikov, A. V.; Tertyshnik, A. D.; Shaleev, M. V.; Yurasov, D. V.

    2016-08-01

    Differences in heating of silicon and silicon-on-insulator (SOI) substrates in molecular beam epitaxy were revealed by low-coherence tandem interferometry. Using this technique the interference effects which impede the correct evaluation of SOI substrate temperature by infrared pyrometers can be eliminated and so the reliable temperature readout can be achieved. It was shown that at the same thermocouple and heater power settings the real temperature of SOI substrates is higher than of silicon ones and the difference may be as high as 40-50 °C at temperatures close to 600 °C. It is supposed that such effect is caused by the additional absorption of heater radiation by the buried oxide layer in the mid-infrared range. Independent proof of this effect was obtained by growing on both types of substrates a series of structures with self-assembled Ge nanoislands whose parameters are known to be very temperature sensitive. The proposed low-coherence interferometry technique provides precise real-time control of the growth temperature and so allows formation of SiGe nanostructures with desired parameters.

  19. Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

    SciTech Connect

    Naumova, O. V. Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P.

    2015-10-15

    The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

  20. Plasma immersion ion implantation for SOI synthesis: SIMOX and ion-cut

    SciTech Connect

    Lu, X.; Iyer, S.S.K.; Hu, C.; Cheung, N.W.; Lee, J.; Doyle, B.; Fan, Z.; Chu, P.K.

    1998-09-01

    The authors have demonstrated feasibility to form silicon-on-insulator (SOI) substrates using plasma immersion ion implantation (PIII) for both separation by implantation of oxygen and ion-cut. This high throughput technique can substantially lower the high cost of SOI substrates due to the simpler implanter design as well as ease of maintenance. For separation by plasma implantation of oxygen wafers, secondary ion mass spectrometry analysis and cross-sectional transmission electron micrographs show continuous buried oxide formation under a single-crystal silicon overlayer with sharp Si/SiO{sub 2} interfaces after oxygen plasma implantation and high-temperature (1,300 C) annealing. Ion-cut SOI wafer fabrication technique is implemented for the first time using PIII. The hydrogen plasma can be optimized so that only one ion species is dominant in concentration and there are minimal effects by other residual ions on the ion-cut process. The physical mechanism of hydrogen induced silicon surface layer cleavage has been investigated. An ideal gas law model of the microcavity internal pressure combined with a two-dimensional finite element fracture mechanics model is used to approximate the fracture driving force which is sufficient to overcome the silicon fracture resistance.

  1. Differentially piezoresistive transduction of high-Q encapsulated SOI-MEMS resonators with sub-100 nm gaps.

    PubMed

    Li, Cheng-Syun; Li, Ming-Huang; Li, Sheng-Shian

    2015-01-01

    A differentially piezoresistive (piezo-R) readout proposed for single-crystal-silicon (SCS) microelectromechanical systems (MEMS) resonators is implemented in a foundrybased resonator platform, demonstrating effective feedthrough cancellation using just simple piezoresistors from the resonator supports while maximizing their capacitively transduced driving areas. The SCS resonators are fabricated by a CMOS foundry using an SOI-MEMS technology together with a polysilicon refill process. A high electromechanical coupling coefficient is attained by the use of 50-nm transducer gap spacing. Moreover, a vacuum package of the fabricated resonators is carried out through wafer-level bonding process. In this work, the corner supporting beams of the resonator serve not only mechanical supports but also piezoresistors for detecting the motional signal, hence substantially simplifying the overall resonator design to realize the piezo-R sensing. In addition, the fabricated resonators are capable of either capacitive sensing or piezo-R detection under the same capacitive drive. To mitigate feedthrough signals from parasitics, a differential measurement configuration of the piezo-R transduction is implemented in this work, featuring more than 30-dB improvement on the feedthrough level as compared with the single-ended piezo-R counterpart and purely capacitive sensing readout. Furthermore, the high-Q design of the mechanical supports is also investigated, offering Q more than 10 000 with efficient piezo-R transduction for MEMS resonators.

  2. Differentially piezoresistive transduction of high-Q encapsulated SOI-MEMS resonators with sub-100 nm gaps.

    PubMed

    Li, Cheng-Syun; Li, Ming-Huang; Li, Sheng-Shian

    2015-01-01

    A differentially piezoresistive (piezo-R) readout proposed for single-crystal-silicon (SCS) microelectromechanical systems (MEMS) resonators is implemented in a foundrybased resonator platform, demonstrating effective feedthrough cancellation using just simple piezoresistors from the resonator supports while maximizing their capacitively transduced driving areas. The SCS resonators are fabricated by a CMOS foundry using an SOI-MEMS technology together with a polysilicon refill process. A high electromechanical coupling coefficient is attained by the use of 50-nm transducer gap spacing. Moreover, a vacuum package of the fabricated resonators is carried out through wafer-level bonding process. In this work, the corner supporting beams of the resonator serve not only mechanical supports but also piezoresistors for detecting the motional signal, hence substantially simplifying the overall resonator design to realize the piezo-R sensing. In addition, the fabricated resonators are capable of either capacitive sensing or piezo-R detection under the same capacitive drive. To mitigate feedthrough signals from parasitics, a differential measurement configuration of the piezo-R transduction is implemented in this work, featuring more than 30-dB improvement on the feedthrough level as compared with the single-ended piezo-R counterpart and purely capacitive sensing readout. Furthermore, the high-Q design of the mechanical supports is also investigated, offering Q more than 10 000 with efficient piezo-R transduction for MEMS resonators. PMID:25585404

  3. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

  4. Atomic Precision Donor Devices Fabricated on Strained Silicon on Insulator (sSOI) with SiGe

    NASA Astrophysics Data System (ADS)

    Yitamben, E.; Bussmann, E.; Scrymgeour, D. A.; Rudolph, M.; Carr, S. M.; Ward, D. R.; Carroll, M. S.

    Recently, Si:P donor spin qubits have achieved coherence times (nuclear & e-) that underscore their quantum computing potential. One next major challenge is to integrate donors into a gated structure where electrons can be moved between P, or drawn off of the P to interact, e.g. to an interface as in Kane's proposal. A key constraint is limited thermal budget, to limit P thermal segregation, which precludes typical gate oxidation of Si. We are developing an alternative materials stack utilizing an interfacial barrier layer of relaxed epitaxial SiGe, with donors placed in a strained Si-on-insulator (sSOI) substrate. We fabricate atomic precision donor structures in sSOI via STM hydrogen lithography. Utilizing Si microfabrication and STM in tandem with our Si and Ge molecular beam epitaxy (MBE), we fabricated devices to test our SiGe/sSOI stack concept and atomic-precision fab techniques. To establish our donor-doping capability, we made Hall and Van der Pauw devices in P:sSOI delta-doped layers exhibiting ne >1014/cm2 and mobilities of ~100 cm2/Vs (T =4K) similar to results reported relaxed Si reported elsewhere. Second, we have grown our concept epitaxial SiGe/sSOI stack, evaluated the morphology using STM, and fabricated Hall devices to evaluate low-T transport in our first SiGe/sSOI. Here, we report on these advances in atomic precision donor fab, along with STM analysis our MBE SiGe/sSOI. This work extends STM-based atom precision fab on strained Si toward a vertically gated architecture.

  5. Application of Silicon Selective Epitaxial Growth and Chemo-Mechanical Polishing to Bipolar and Soi Mosfet Devices.

    NASA Astrophysics Data System (ADS)

    Nguyen, Cuong Tan

    1994-01-01

    Polished Epitaxy, or the combination of silicon Selective Epitaxial Growth and Chemo-Mechanical Polishing, provides new flexibility in process and device design, including optimized isolation, planar active-area definition, low-capacitance contacts, and SOI thin films. In this work, Polished Epitaxy has been developed with particular effort on overcoming junction leakage problems widely reported in devices fabricated in similar processes. It was found that in addition to careful surface preparation and defect control in the selective epitaxy process, issues such as sidewall orientation, junction passivation, crystal annealing, and surface damage removal were equally important and needed to be addressed. Coupled with the proper processing steps, Polished Epitaxy was able to deliver material of comparable quality to bulk silicon, suitable for device applications. By growing epitaxy laterally over an oxide step followed by polishing, a pedestal structure was created in which a thin film of single-crystal silicon was formed over oxide. Serving as the extrinsic base contact to a T-Pedestal bipolar transistor device, this pedestal helped minimize the parasitic extrinsic-base-collector overlap capacitance. The cut-off frequency (f_ {T}) in a device with a 1.0-mu m wide emitter stripe was found to improve from 17GHz to 22GHz when the contact overlap was reduced from a more conventional, larger size of 1.0 mu m to 0.2 mum. It is expected that the high-frequency performance of this structure can still be improved further in an optimized process with reduced emitter and collector resistances. The same pedestal structure was applied to a Pedestal -SOI (Silicon-On-Insulator) MOSFET device concept. At one extreme, a conventional bulk MOSFET structure is obtained when the pedestal is not utilized; quasi-SOI occurs when the drain and part of the channel overlap with the pedestal over buried oxide; at the other extreme, complete-SOI behavior results when source, channel, and drain

  6. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    NASA Astrophysics Data System (ADS)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  7. Low-loss and flatband silicon-nanowire-based 5th-order coupled resonator optical waveguides (CROW) fabricated by ArF-immersion lithography process on a 300-mm SOI wafer

    NASA Astrophysics Data System (ADS)

    Jeong, Seok-Hwan; Shimura, Daisuke; Simoyama, Takasi; Seki, Miyoshi; Yokoyama, Nobuyuki; Ohtsuka, Minoru; Koshino, Keiji; Horikawa, Tsuyoshi; Tanaka, Yu; Morito, Ken

    2014-03-01

    We present flatband, low-loss and low-crosstalk characteristics of Si-nanowire-based 5th-order coupled resonator optical waveguides (CROW) fabricated by ArF-immersion lithography process on a 300-mm silicon-on-insulator (SOI) wafer. We theoretically specified why phase controllability over Si-nanowire waveguides is prerequisite to attain desired spectral response, discussing spectral degradation by random phase errors during fabrication process. It was experimentally demonstrated that advanced patterning technology based on ArF-immersion lithography process showed extremely low phase errors even for Si-nanowire channel waveguides. As a result, the device exhibited extremely low loss of <0.2dB and low crosstalk of <-40dB without any external phase compensation. Furthermore, fairly good spectral uniformity for all fabricated devices was found both in intra-dies and inter-dies. The center wavelengths for box-like drop channel responses were distributed within 0.4 nm in the same die. This tendency was kept nearly constant for other dies on the 300-mm SOI wafer. In the case of the inter-die distribution where each die is spaced by ~3cm, the deviation of the center wavelengths was as low as +/-1.8 nm between the dies separated by up to ~15 cm. The spectral superiority was reconfirmed by measuring 25 Gbps modulation signals launched into the device. Clear eye openings were observed as long as the optical signal wavelengths are stayed within the flat-topped passband of the 5th-order CROW. We believe these high-precision fabrication technologies based on 300-mm SOI wafer scale ArF-immersion lithography would be promising for several kinds of WDM multiplexers/demultiplexers having much complicated configurations and requiring much finer phase controllability.

  8. A hetero-dielectric stack gate SOI-TFET with back gate and its application as a digital inverter

    NASA Astrophysics Data System (ADS)

    Mitra, Suman Kr.; Goswami, Rupam; Bhowmick, Brinda

    2016-04-01

    A Silicon based two dimensional (2D) hetero-dielectric stack gate SOI Tunneling Field Effect Transistor (SOI-TFET) with back-gate is proposed. Simulation results show that the proposed structure can be scaled down without affecting Subthreshold Swing unlike conventional TFETs with SiO2 as gate dielectric. On state of the device is independent of back-gate voltage unlike MOSFETs. The effects of gate lengths, lengths of high-k dielectric in lower stack (L) and back-gate voltages on the threshold voltage, Ion/Ioff and Subthreshold Swing (SS) of the SOI-TFET are analyzed. Capacitance components CGG, CGD, CGS are also observed and device shows good performance as an inverter. The fall time, overshoot and undershoot are not above 27 fs, 1.712% and 0.77% respectively considering mixed mode device and circuit simulation of capacitive loaded inverter.

  9. New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation

    SciTech Connect

    BURNS,J.A.; DODD,PAUL E.; KEAST,C.L.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; WYATT,P.W.

    1999-09-14

    Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.

  10. XeF2 vapor phase silicon etch used in the fabrication of movable SOI structures.

    SciTech Connect

    Wiwi, M.; Sanchez, Carlos Anthony; Plut, Thomas Alvin; Salazar, M.; Stevens, Jeffrey; Bauer, Todd M.; Ford, C.; Shul, Randy John; Grossetete, Grant David

    2010-10-01

    Vapor phase XeF{sub 2} has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF{sub 2} Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF{sub 2} vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO{sub 2}) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF{sub 2} etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO{sub 2}. The buried SiO{sub 2} was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO{sub 2}. FC polymer was deposited from C4F8 gas precursor in an inductively coupled plasma reactor, and SiO{sub 2} was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF{sub 2} was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF{sub 2} due to protection from the top SiO{sub 2} mask, sidewall passivation, and the buried SiO{sub 2} layer. Optimization of the XeF{sub 2

  11. Low-frequency noise in bare SOI wafers: Experiments and model

    NASA Astrophysics Data System (ADS)

    Pirro, L.; Ionica, I.; Cristoloveanu, S.; Ghibaudo, G.

    2016-11-01

    Low-frequency noise (LFN) measurements are largely used for interface quality characterization in MOSFETs. In this work, a detailed investigation of LFN technique applied to pseudo-MOSFETs in bare silicon-on-insulator (SOI) substrates is provided. A physical model capable to describe the experimental results is proposed and validated using different die areas and inter-probe distances. The effective silicon area contributing to the noise signal, the impact of defects induced by probes and the possibility to extract interface trap density are addressed.

  12. Trigger voltage walk-out phenomenon in SOI lateral insulated gate bipolar transistor under repetitive electrostatic discharge stresses

    NASA Astrophysics Data System (ADS)

    Zhang, Shifeng; Han, Yan; Ma, Fei

    2016-05-01

    Trigger voltage walk-out phenomenon is found in SOI LIGBT's under repetitive ESD stresses. Such a characteristic would cause an IC to be susceptible to the risk of exceeding the ESD design window and thus resulting in core circuit damages when the LIGBT is served as an ESD protection device in the SOI process. This trigger-voltage walk-out phenomenon is investigated in this paper, and both the experimental evidences and device simulation results are presented to offer the insight of the underlying physical mechanism.

  13. DETECTORS AND EXPERIMENTAL METHODS: Radiation response of pseudo-MOS transistors fabricated in hardened fully-depleted SIMOX SOI wafers

    NASA Astrophysics Data System (ADS)

    Bi, Da-Wei; Zhang, Zheng-Xuan; Zhang, Shuai; Chen, Ming; Yu, Wen-Jie; Wang, Ru; Tian, Hao; Liu, Zhang-Li

    2009-10-01

    The total dose radiation response of pseudo-MOS transistors fabricated in hardened and unhardened FD (fully-depleted) SIMOX (Separation by Implanted Oxygen) SOI (Silicon-on-insulator) wafers is presented. At 1 Mrad(Si) radiation dose, the threshold voltage shift of the pseudo-MOS transistor is reduced from -115.5 to -1.9 V by the hardening procedure. The centroid location of the net positive charge trapped in BOX, the hole-trap density and the hole capture fraction of BOX are also shown. The results suggest that hardened FD SIMOX SOI wafers can perform well in a radiation environment.

  14. Semi-analytical model of arrayed waveguide grating in SOI using Gaussian beam approximation.

    PubMed

    Sidharth, R; Das, B K

    2015-03-10

    The arrayed waveguide grating structure can be used as an important component in high-speed CMOS optical interconnects in silicon-on-insulator (SOI) platform. However, the performance of such device is found to be extremely sensitive to the fabrication-related errors in defining the critical features. In the absence of an appropriate analytical model, one needs to rely on numerical computation to analyze the device characteristics and fabrication tolerances. Because compact design of such a device structure has foot-print ∼mm2 and the smallest features can be as small as ∼500  nm×220  nm (waveguide cross section), it demands a huge computational budget to optimize the design parameters. A semi-analytical model using Gaussian beam approximation of guided mode profiles has been developed to analyze the output spectrum of arrayed waveguide grating and to estimate the phase errors due to waveguide inhomogeneities. This model has been validated with existing numerical methods and published experimental results. It has been observed that a probabilistic waveguide width variations of ΔW∼5  nm can cause a cross-talk degradation of about 40 dB (25 dB) for a device (operating at λ∼1550  nm) fabricated on SOI substrate with 220 nm (2 μm) device layer thickness.

  15. High LET Single Event Upset Cross Sections For Bulk and SOI CMOS SRAMs

    SciTech Connect

    McDaniel, F.D.; Doyle, B.L.; Vizkelethy, G.; Dodd, P.E.; Rossi, P.

    2003-08-26

    Electronics in spacecraft and satellites are exposed to high-energy cosmic radiation. In addition, terrestrial radiation can also affect earth-based electronics. To study the effects of radiation upon integrated circuits and to insure the reliability of electronic devices, cosmic and terrestrial radiations are simulated with ion beams from particle accelerators. A new, higher Linear Energy Transfer (LET) acceleration system for heavy ions has been developed at Sandia National Laboratories. Heavy ions from a 6.5 MV EN tandem Van de Graaff accelerator at 0.25 MeV/amu are injected into a two-stage Radio Frequency Quadrupole (RFQ) linac, which accelerates the ions to 1.9 MeV/amu. These ions together with those from the Brookhaven National Laboratory MP Tandem have been used to measure single event upset (SEU) cross sections as a function of LET for both bulk and Silicon on Insulator (SOI) Complementary Metal Oxide Semiconductor, Static Random Access Memories. The magnitudes of these cross sections indicate that the upsets in both the SOI and bulk parts are caused by OFF-drain strikes.

  16. Defect Characterization in SiGe/SOI Epitaxial Semiconductors by Positron Annihilation

    NASA Astrophysics Data System (ADS)

    Ferragut, R.; Calloni, A.; Dupasquier, A.; Isella, G.

    2010-12-01

    The potential of positron annihilation spectroscopy (PAS) for defect characterization at the atomic scale in semiconductors has been demonstrated in thin multilayer structures of SiGe (50 nm) grown on UTB (ultra-thin body) SOI (silicon-on-insulator). A slow positron beam was used to probe the defect profile. The SiO2/Si interface in the UTB-SOI was well characterized, and a good estimation of its depth has been obtained. The chemical analysis indicates that the interface does not contain defects, but only strongly localized charged centers. In order to promote the relaxation, the samples have been submitted to a post-growth annealing treatment in vacuum. After this treatment, it was possible to observe the modifications of the defect structure of the relaxed film. Chemical analysis of the SiGe layers suggests a prevalent trapping site surrounded by germanium atoms, presumably Si vacancies associated with misfit dislocations and threading dislocations in the SiGe films.

  17. AlN-on-SOI platform-based micro-machined hydrophone

    NASA Astrophysics Data System (ADS)

    Xu, Jinghui; Zhang, Xiaolin; Fernando, Sanchitha N.; Chai, Kevin Tshunchuan; Gu, Yuandong

    2016-07-01

    This paper reports a piezoelectric aluminum nitride (AlN) based micro-machined infrasonic hydrophone. We have conducted a systematic design study for the hydrophone sensor to meet the stringent requirements of underwater applications. The hydrophone sensor was fabricated on a cavity silicon-on-insulator (SOI) substrate using an in-house CMOS-compatible AlN-on-SOI process platform. A 5 × 5 arrayed hydrophone sensor was characterized thoroughly using an industry-standard hydrophone calibration instrument. The results show that the hydrophone achieved a sound sensitivity of -182.5 dB ± 0.3 dB (ref. to 1 V rms/μPa) and an eligible acceleration sensitivity of only -196.5 dB (ref. to 1 V rms/μg), respectively, a non-linearity of 0.11%, a noise resolution of 57.5 dB referenced to 1 μPa/√Hz within an ultra-low operation bandwidth of 10 Hz˜100 Hz, the highest noise resolution of micro-machined hydrophones reported to date, and better than traditional bulky hydrophones in terms of the same application. The size of the 5 × 5 arrayed hydrophone sensor is about 2 mm × 2 mm.

  18. Overcritical damped laterally moving microstructures by ADRIE using SOI-substrates for automotive applications

    NASA Astrophysics Data System (ADS)

    Krampitz, Oliver; Wycisk, Michael; Biefeld, Volker; Binder, Josef

    2000-08-01

    A fabrication process for laterally moving single crystal silicon microstructures on SOI substrates is presented. Due to an ADRIE process high aspect ratio structures are realized. The underlying silicon dioxide layer of the SOI substrate serves as sacrificial layer. A HF vapor etching system is used for the sacrificial layer etching to avoid sticking effects of the structures. For the fabrication of an acceleration threshold switch a metallized contact area is necessary. The switching contact is realized using a sidewall metalization of the laterally moving structures. The sensor structure is that of a spring mass system. To avoid uncontrollable switchings of the device, an overcritical damping of the sensor structure is needed. The high aspect ratio of the structures makes these high damping coefficients possible. The dynamic behavior of the device is achieved by squeeze-film damping of the high aspect ratio structures. Using optical measurement equipment for the device characterization, overcritical damping coefficients can be verified for the fabricated structures. The mechanical properties and the dynamic behavior of the structures are ideal for the construction of acceleration threshold switches for automotive applications.

  19. Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

    NASA Astrophysics Data System (ADS)

    Zheng, Zhi; Li, Wei; Li, Ping

    2013-04-01

    A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.

  20. Reduction of cross-talks between circuit and sensor layer in the Kyoto's X-ray astronomy SOI pixel sensors with Double-SOI wafer

    NASA Astrophysics Data System (ADS)

    Ohmura, Shunichi; Tsuru, Takeshi Go; Tanaka, Takaaki; Uchida, Hiroyuki; Takeda, Ayaki; Matsumura, Hideaki; Ito, Makoto; Arai, Yasuo; Kurachi, Ikuo; Miyoshi, Toshinobu; Nakashima, Shinya; Mori, Koji; Nishioka, Yusuke; Takebayashi, Nobuaki; Noda, Koki; Kohmura, Takayoshi; Tamasawa, Kouki; Ozawa, Yusuke; Sato, Tadashi; Konno, Takahiro; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita; Kamehama, Hiroki; Shrestha, Sumeet; Hara, Kazuhiko; Honda, Shunsuke

    2016-09-01

    We have been developing silicon-on-insulator pixel sensors, "XRPIXs," for future X-ray astronomy satellites. XRPIXs are equipped with a function of "event-driven readout," with which we can read out only hit pixels by trigger signals and hence realize good time resolution reaching ∼ 10 μs . The current version of XRPIX suffers from a problem that the spectral performance degrades in the event-driven readout mode compared to the frame-readout mode, in which all the pixels are read out serially. Previous studies have clarified that one of the causes is capacitive coupling between the sense node and the trigger signal line in the circuit layer. In order to solve the problem, we adopt the Double SOI structure having a middle silicon layer between the circuit and the sensor layers. We expect the middle silicon layer to work as an electrostatic shield and reduces the capacitive coupling. In this paper, we report the spectroscopic performance of XRPIX with the middle silicon layer. We successfully reduce the capacitive coupling and the readout noise.

  1. SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Almad

    2009-01-01

    Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80

  2. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    SciTech Connect

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  3. Worst case total dose radiation response of 0.35 {micro}m SOI CMOSFETs

    SciTech Connect

    Liu, S.T.; Balster, S.; Sinha, S.; Jenkins, W.C.

    1999-12-01

    Through experimental results and analysis by TSUPREM4/MEDICI simulations, the worst case back gate total dose bias condition is established for body tied SOI NMOSFETs. Utilizing the worst-case bias condition, a recently proposed model that describes the back n-channel threshold voltage shift as a function of total dose, TSUPREM4/MEDICI simulations, and circuit level SPICE simulations, a methodology to model post-rad standby current is developed and presented. This methodology requires the extraction of fundamental starting material/material preparation constants, and then can be utilized to examine post-rad stand-by current at the device and circuit level as function of total dose. Good agreement between experimental results and simulations is demonstrated.

  4. Novel adiabatic tapered couplers for active III-V/SOI devices fabricated through transfer printing.

    PubMed

    Dhoore, Sören; Uvin, Sarah; Van Thourhout, Dries; Morthier, Geert; Roelkens, Gunther

    2016-06-13

    We present the design of two novel adiabatic tapered coupling structures that allow efficient and alignment tolerant mode conversion between a III-V membrane waveguide and a single-mode SOI waveguide in active heterogeneously integrated devices. Both proposed couplers employ a broad intermediate waveguide to facilitate highly alignment tolerant coupling. This robustness is needed to comply with the current misalignment tolerance requirements for high-throughput transfer printing. The proposed coupling structures are expected to pave the way for transfer-printing-based heterogeneous integration of active III-V devices such as semiconductor optical amplifiers (SOAs), photodetectors, electro-absorption modulators (EAMs) and single wavelength lasers on silicon photonic integrated circuits. PMID:27410317

  5. Increase in the scattering of electric field lines in a new high voltage SOI MESFET

    NASA Astrophysics Data System (ADS)

    Anvarifard, Mohammad K.

    2016-09-01

    This paper illustrates a new efficient technique to enhance the critical features of a silicon-on-insulator metal-semiconductor field-effect transistor (SOI MESFET) applied in high voltage applications. The structure we proposed utilizes a new method to scatter the electric field lines along the channel region. Realization of two trenches with different materials, which a trench is created in the channel region and the other one is created in the buried oxide, helps the proposed structure to improve the breakdown voltage, driving current, drain-source conductance, minimum noise figure, unilateral power gain and output power density. Exploring the obtained results, the proposed structure has superior electrical performance in comparison to the conventional structure.

  6. Prediction of coronal and heliospheric magnetic fields: The promise of SOI-MDI on SOHO

    NASA Technical Reports Server (NTRS)

    Hoeksema, J. T.; Zhao, X. P.; Scherrer, P. H.

    1995-01-01

    Models of the coronal magnetic field have been developed over the years that reproduce the static characteristics of coronal and heliospheric structures fairly well. Limitations of spatial and temporal resolution and nonuniform quality of the input data have made it particularly difficult to investigate the response of the corona to rapidly changing photospheric conditions. The Solar Oscillations Investigation (SOI) experiment on SOHO, scheduled for launch late in 1995, will produce a series of full-disk photospheric magnetic field observations with 4" resolution about every 2 hours for the next several years. Higher resolution observations of the center of the disk will be available several times per day. These data should provide a basis for predicting the coronal and heliospheric field and their changes with unprecedented accuracy during the rising phase of Solar Cycle 23.

  7. SOI-Diode TEC-less Uncooled Infrared Micro-camera

    NASA Astrophysics Data System (ADS)

    Kibe, Michiya; Nagashima, Mitsuhiro; Doshida, Minoru; Kama, Keisuke; Ohnakado, Takahiro

    This paper describes an uncooled infrared (IR) camera especially optimized for small size & weight, less power consumption without degrading noise equivalent temperature difference (NETD). This camera has two features, including a wafer-level chip scale vacuum package with 160x120 SOI-diode array and germanium lid for good IR transmission, and also a real-time signal correction capability with respect to ambient temperature. These features enabled the considerable size/power consumption reduction and the operation without thermoelectric cooler (TEC) which usual IR cameras require for temperature stabilization. As a result, we realized compact infrared camera (less than 71grams) with low-power consumption and excellent NETD of 22 mK (F/0.8 optics).

  8. Seismic Study of the Solar Interior: Inferences from SOI/MDI Observations During Solar Activity

    NASA Technical Reports Server (NTRS)

    Korzennik, Sylvain G.; Wagner, William J. (Technical Monitor)

    2005-01-01

    Work on the structure, asphericity and dynamics of the solar interior from p-mode frequencies and frequency splittings was carried out primarily in collaboration with Dr. Eff-Darwich (University of La Laguna, Tenerife). This ongoing collaboration produced new results for the inversion of the internal solar rotation rate and further development in inversion methodologies. It also resulted in inferences on the solar stratification. Substantial progress towards the characterization of high-degree p-modes has been achieved. In collaboration with Drs. Rabello-Soares and Schou (Stanford University), we have gained a clear conceptual understanding of the various elements that affect the leakage matrix of the SOI/MDI instrument. This work has precise implications on the properties and the characterization of the HMI instrument being developed for the SDO mission.

  9. MONOLITHIC ACTIVE PIXEL MATRIX WITH BINARY COUNTERS IN AN SOI PROCESS.

    SciTech Connect

    DUPTUCH,G.; YAREMA, R.

    2007-06-07

    The design of a Prototype monolithic active pixel matrix, designed in a 0.15 {micro}m CMOS SOI Process, is presented. The process allowed connection between the electronics and the silicon volume under the layer of buried oxide (BOX). The small size vias traversing through the BOX and implantation of small p-type islands in the n-type bulk result in a monolithic imager. During the acquisition time, all pixels register individual radiation events incrementing the counters. The counting rate is up to 1 MHz per pixel. The contents of counters are shifted out during the readout phase. The designed prototype is an array of 64 x 64 pixels and the pixel size is 26 x 26 {micro}m{sup 2}.

  10. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    NASA Astrophysics Data System (ADS)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  11. Technology.

    ERIC Educational Resources Information Center

    Callison, Daniel

    2002-01-01

    Discussion of technology focuses on instructional technology. Topics include inquiry and technology; curriculum development; reflection and curriculum evaluation; criteria for technological innovations that will increase student motivation; standards; impact of new technologies on library media centers; software; and future trends. (LRW)

  12. Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

  13. A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

    NASA Astrophysics Data System (ADS)

    Lu, Darsen D.; Dunga, Mohan V.; Lin, Chung-Hsun; Niknejad, Ali M.; Hu, Chenming

    2011-08-01

    In this paper a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates is presented. A fully-depleted SOI MOSFET with a back-gate is essentially an independent double-gate device. To the best of our knowledge, existing surface-potential-based models for independent double-gate devices require numerical iteration to compute the surface potentials. This increases the model computational time and may cause convergence difficulties. In this work, a new approximation scheme is developed to compute the surface potentials and charge densities using explicit analytical equations. The approximation is shown to be computationally efficient and preserves important properties of fully-depleted SOI MOSFETs such as volume inversion. Drain current and charge expressions are derived without using the charge sheet approximation and agree well with TCAD simulations. Non-ideal effects are added to describe the I- V and C- V of a real device. Source-drain symmetry is preserved for both the current and the charge models. The full model is implemented in Verilog-A and its convergence is demonstrated through transient simulation of a coupled ring oscillator circuit with 2020 transistors.

  14. Self-aligned maskless process for etching cavities in SOI wafers to enhance the quality factor of MEMS resonators

    NASA Astrophysics Data System (ADS)

    Mohammad, Wajihuddin; Kaajakari, Ville

    2010-02-01

    We present a low cost, self-aligned, process to etch cavities under movable structures in commercially available SOI wafers. The cavity is formed by electrochemically etching the substrate through the openings in the SOI structural layer. A tuning fork structure fabricated with the cavity SOI process has resonant frequency of 247 kHz and the measured intrinsic is Q = 82,000 at 35 mTorr. Comparing the measured quality factor as function of pressure for devices with and without the cavity, the devices with cavity showed a consistent improvement in the quality factor by a factor of 2-3 except for very low pressures where the intrinsic mechanical quality factor dominates. As the distance between the device and substrate is increased from 2 μm (buried oxide thickness) to 10 μm (electrochemically etched cavity), the parasitic capacitance to the substrate is also reduced by 5x. In addition, the stiction between the device and substrate is effectively eliminated.

  15. Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper

    PubMed Central

    Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

    2014-01-01

    A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM0 mode into the TE1 mode, which will output as the TE0 mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < −17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology. PMID:25402029

  16. Low-loss delay lines with small footprint on a micron-scale SOI platform

    NASA Astrophysics Data System (ADS)

    Cherchi, Matteo; Harjanne, Mikko; Vyrsokinos, Konstantinos; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani; Aalto, Timo

    2015-02-01

    Long and yet compact spiral waveguides based on micron-scale silicon strip waveguides has been enabled very recently by the introduction of the Euler bends. By ensuring effective broadband single mode operation of otherwise highly multimodal waveguides, these bends can have very low losses (<0.01 dB/90°) even with effective radii of a few microns. Together with the low propagation losses (< 0.15 dB/cm) of micron-scale strip waveguides, these bends enable centimeter-long delay lines with negligible losses and very small foot-print (< 1 mm2). In particular, interferometers delayed by ≈ 1 cm long spirals on one of the two arms have been fabricated on SOI wafers with both 3 um- and 4 umthick silicon layer, based on the well assessed process developed by VTT. The full devices have footprint smaller than 1.5 mm2, and they have been measured to have extinction ratios < 15 dB (reaching up to 21 dB) and about 3 dB excess losses. Functional characterization of the delayed interferometers at about 10 Gbps through demodulation of pseudorandom Differential Phase Shift Keying signals led to clearly opened eye diagrams with Q factor of 8.6 and bit error rates lower than 10-15.

  17. Electrical detection of amine ligation to a metalloporphyrin via a hybrid SOI-MOSFET.

    PubMed

    Takulapalli, Bharath R; Laws, Gez M; Liddell, Paul A; Andréasson, Joakim; Erno, Zach; Gust, Devens; Thornton, Trevor J

    2008-02-20

    A close-packed monolayer of zinc 5,10,15,20-tetrakis(3-carboxyphenyl)porphyrin has been prepared and deposited on the thin native oxide covering the surface of an SOI-MOSFET (silicon-on-insulator metal-oxide-semiconductor field effect transistor) using Langmuir-Blodgett techniques. When the device is exposed to amine vapors in a nitrogen atmosphere, the amine coordinates to the zinc atom. The resulting change in electron distribution within the porphyrin leads to a large change in the drain current of the transistor, biased via a back gate. This change is sensitive to both the amount of amine present and the base strength of the amine. Only very small changes in drain current were observed with a monolayer of free base porphyrin or palmitic acid. After exposure to high pyridine concentrations, the device response saturates, but partially recovers after overnight exposure to flowing nitrogen gas. Interestingly, the device response is instantaneously reset by exposure to visible light, suggesting that photode-ligation occurs. An electrical model for the hybrid device that describes its response to ligand binding in terms of a change in the work function of the porphyrin monolayer has been developed. A transistor response to a few hundred attomoles of bound pyridine can be readily detected. This extreme sensitivity, coupled with the ability to reset the device using light, suggests that such systems might be useful as sensors.

  18. Nanopore patterning using Al2O3 hard masks on SOI substrates

    NASA Astrophysics Data System (ADS)

    Wang, Xiaofeng; Goryll, Michael

    2015-07-01

    Aluminum oxide Al2O3, deposited using amorphous atomic layer deposition (ALD), is a very promising material to be utilized as a hard mask for nano-patterning. We used an aluminum oxide hard mask on a silicon-on-insulator (SOI) substrate to implement a sub-100 nm nanopore process. The transfer of nanoscale patterns via dry etching of the Al2O3 thin film was investigated by comparing etch profiles, etch rates, and selectivity of Al2O3 over PMMA resist, using different gas chemistries such as Cl2, Ar, Ar/BCl3 mixtures, and BCl3 plasma. A selectivity of 1:4 was observed using an inductively coupled plasma reactive ion etching (ICP-RIE) tool with BCl3 plasma, and the sub-100 nm nanopore patterns were anisotropically transferred to the alumina layer from a 250 nm PMMA layer. The dense and inert Al2O3 hard mask showed exceptional etch selectivity to Si and SiO2, which allowed the subsequent transfer of the nanopore patterns into the 340 nm-thick Si device layer and made it possible to attempt etching the 1 μm-thick buried oxide (BOX) layer. Using chlorine chemistry, nanopores patterned in the Si device layer showed excellent anisotropy while preserving the original pattern dimensions. The process demonstrated is ideally suited for patterning high aspect ratio nanofluidic structures.

  19. SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

    SciTech Connect

    Trimpl, M.; Deptuch, G.; Yarema, R.; /Fermilab

    2010-11-01

    This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm{sup 2} large detector array with 20 {micro}m and 40 {micro}m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

  20. Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

    NASA Astrophysics Data System (ADS)

    Xiaorong, Luo; Xiaowei, Wang; Gangyi, Hu; Yuanhang, Fan; Kun, Zhou; Yinchun, Luo; Ye, Fan; Zhengyuan, Zhang; Yong, Mei; Bo, Zhang

    2014-02-01

    An improved breakdown voltage (BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches (DTMOS), an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide (BOX). The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide (ɛox) than that of Si (ɛSi). Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF (reduced surface field) effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit (HVIC), effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.

  1. A dicing-free SOI process for MEMS devices based on the lag effect

    NASA Astrophysics Data System (ADS)

    Xie, J.; Hao, Y.; Shen, Q.; Chang, H.; Yuan, W.

    2013-12-01

    This paper presents a dicing-free process for silicon-on-insulator (SOI) microelectromechanical systems (MEMS). In the process, the lag effect in deep reactive ion etching (DRIE) is used to form the breaking trenches. In the backside DRIE, the wide backside cavities are etched down to the buried oxide layer. The narrow breaking trenches, in contrast, are not etched to the buried oxide layer. Therefore, the narrow trench can be used to break the wafer after the entire process; in addition, the handle layer can still act as a bracing structure before ‘breaking’. Finally, the device layer is patterned, and a DRIE step is used to form the MEMS devices. In this way, the dicing step can be omitted to prevent further damages from high pressure water jets and silicon dust. Meanwhile, the process can also prevent notching simply because the insulating layer is removed before device etching. To demonstrate the feasibility of the proposed fabrication process, a micromachined gyroscope is designed and fabricated.

  2. Two-port multimode interference reflectors based on aluminium mirrors in a thick SOI platform.

    PubMed

    Fandiño, Javier S; Doménech, José David; Muñoz, Pascual

    2015-08-10

    Multimode interference reflectors (MIRs) were recently introduced as a new type of photonic integrated devices for on-chip, broadband light reflection. In the original proposal, different MIRs were demonstrated based on total internal reflection mirrors made of two deep-etched facets. Although simpler to fabricate, this approach imposes certain limits on the shape of the field pattern at the reflecting facets, which in turn restricts the types of MIRs that can be implemented. In this work, we propose and experimentally demonstrate the use of aluminium-based mirrors for the design of 2-port MIRs with variable reflectivity. These mirrors do not impose any restrictions on the incident field, and thus give more flexibility at the design stage. Devices with different reflectivities in the range between 0 and 0.5 were fabricated in a 3 um thick SOI platform, and characterization of multiple dies was performed to extract statistical data about their performance. Our measurements show that, on average, losses both in the aluminium mirror and in the access waveguides reduce the reflectivities to about 79% of their target value. Moreover, standard deviations lower than ±5% are obtained over a 20 nm wavelength range (1540-1560 nm). We also provide a theoretical model of the aluminium mirror based on the effective index method and Fresnel equations in multilayer thin films, which shows good agreement with FDTD simulations.

  3. Line-edge roughness induced single event transient variation in SOI FinFETs

    NASA Astrophysics Data System (ADS)

    Weikang, Wu; Xia, An; Xiaobo, Jiang; Yehua, Chen; Jingjing, Liu; Xing, Zhang; Ru, Huang

    2015-11-01

    The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (Vgs = 0, Vds = Vdd) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

  4. Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

    NASA Astrophysics Data System (ADS)

    Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

    2016-09-01

    In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

  5. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    SciTech Connect

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-04-24

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10{sup −9} of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

  6. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    NASA Astrophysics Data System (ADS)

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-04-01

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (˜ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and - 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10-9 of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

  7. Electrical detection of amine ligation to a metalloporphyrin via a hybrid SOI-MOSFET.

    PubMed

    Takulapalli, Bharath R; Laws, Gez M; Liddell, Paul A; Andréasson, Joakim; Erno, Zach; Gust, Devens; Thornton, Trevor J

    2008-02-20

    A close-packed monolayer of zinc 5,10,15,20-tetrakis(3-carboxyphenyl)porphyrin has been prepared and deposited on the thin native oxide covering the surface of an SOI-MOSFET (silicon-on-insulator metal-oxide-semiconductor field effect transistor) using Langmuir-Blodgett techniques. When the device is exposed to amine vapors in a nitrogen atmosphere, the amine coordinates to the zinc atom. The resulting change in electron distribution within the porphyrin leads to a large change in the drain current of the transistor, biased via a back gate. This change is sensitive to both the amount of amine present and the base strength of the amine. Only very small changes in drain current were observed with a monolayer of free base porphyrin or palmitic acid. After exposure to high pyridine concentrations, the device response saturates, but partially recovers after overnight exposure to flowing nitrogen gas. Interestingly, the device response is instantaneously reset by exposure to visible light, suggesting that photode-ligation occurs. An electrical model for the hybrid device that describes its response to ligand binding in terms of a change in the work function of the porphyrin monolayer has been developed. A transistor response to a few hundred attomoles of bound pyridine can be readily detected. This extreme sensitivity, coupled with the ability to reset the device using light, suggests that such systems might be useful as sensors. PMID:18225896

  8. The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

    NASA Astrophysics Data System (ADS)

    Lim, Tao Chuan; Armstrong, G. Alastair

    2006-05-01

    In this paper, the analogue performance of a 65 nm node double gate SOI (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as fT, and fMAX. It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of fT, and fMAX on extrinsic source, drain and gate resistances RS, RD and RG have been derived. While RD and RS have equal effect on fT, RD appears to be more influential than RS in reducing fMAX. The sensitivity of fMAX to RS and RD. has been shown to be greater than to RG.

  9. A band-modulation device in advanced FDSOI technology: Sharp switching characteristics

    NASA Astrophysics Data System (ADS)

    El Dirani, Hassan; Solaro, Yohann; Fonteneau, Pascal; Legrand, Charles-Alex; Marin-Cudraz, David; Golanski, Dominique; Ferrari, Philippe; Cristoloveanu, Sorin

    2016-11-01

    A band-modulation device is demonstrated experimentally in advanced FDSOI (Fully Depleted SOI). The Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a very recent sharp switching device which achieves remarkable performance in terms of leakage current and triggering control. The device is fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator (SOI) technology, features an extremely sharp on-switch, low leakage and an adjustable triggering voltage (VON). The Z2-FET operation relies on the modulation of electrons and holes injection barriers. In this paper, we show, for the first time, experimental data obtained with the most advanced FDSOI node.

  10. Global and Local Helioseismic Studies of Solar Convection Zone Dynamics Using SOI-MDI on SOHO

    NASA Technical Reports Server (NTRS)

    Toomre, Juri; Haber, Deborah; Hindman, Bradley; Christensen-Dalsgaard, Joergen; Gough, Douglas; Thompson, Michael

    2003-01-01

    Our joint collaborative analyses of global mode data to characterize the solar differential rotation (e.g. Thompson et al. 1996, Schou et al. 1998), and most recently to detect and analyze temporal variations in angular velocity Omega profiles both within the convection zone and in the deeper radiative interior (e.g. Howe et al 2000a,b; Toomre et al. 2000), have led to a series of fascinating discoveries. These should be pursued further as the solar cycle continues. The physical deductions being made from these studies have been greatly strengthened by utilizing both SOI-MDI and GONG data in order to have two independent observational realizations of Doppler images spanning a five-year interval, using two separate procedures to determine global mode splittings, and then analyzing those splitting data sets using both RLS and SOLA inversion procedures. There are considerable subtleties in the effects of instrumental response functions and calibrations, sensitivity of peak finding algorithms and their mode leakage estimates, and stochastic variations in mode amplitudes that can all contribute to apparent changes in the Omega profiles being inferred from sequences of helioseismic data. We have come to understand the implications of many of these calibration and analysis steps, greatly aided by frequent multi-week collaborative working sessions in our Helioseismic Analysis Facility (HAF) at JILA involving many members of the SO1 dynamics and inversion team, including most of our Co-Is during the summer months when we hold intensive working sessions. Considerable further focused attention is required in a collaborative setting on such global mode issues as we continue studying the changing sun.

  11. Highland-lowland conflict over natural resources: a case of Mae Soi, Chiang Mai, Thailand.

    PubMed

    Tungittiplakorn, W

    1995-01-01

    Interviews were conducted among 150 Hmong highland and ethnic Thai lowland villagers during May-August 1992 in Chiang Mai in northern Thailand. Officials from national and international drug abuse control and development agencies were also interviewed. The aim was to determine the nature of the conflict between the highlanders and the lowlanders. The lowlanders perceived that the conflict was due to environmental causes brought on by the Hmongs' destruction of forest and pollution of the river. The Mai Soi stream that was relied on by lowlanders was viewed as threatened by drought and water reduction from forest destruction. Shinawatra researched water runoff from major rivers during seasonal changes and found reduced volume during 1970-80. Alford found no significant change in stream flow. 71% of lowlanders reported that stream flow was reduced over a 3-6 year period. 40% reported that the forests were fenced off in order to protect the forests, but 22% were forced by village headmen to do so. 32% were promised land in the allocation areas. The highlanders perceived the conflict in diverse ways. Many attributed the conflict to the murder of a lowlander cattle thief in a Hmong village in 1984. A 1983 report confirmed ethnic conflict and the killing and stealing of Hmong animals. Some highlanders and lowlanders believe the conflict arose due to one person, Ajahn Pongsak Techadhammo, who tried to create environmental awareness among all tribes and ethnic groups. He was against lowlanders' misuse of forests and wanted relocation of the hill tribes that cultivated opium. Social status differences fuel the conflict. Lowlanders consider themselves superior to hill tribes that do not speak Thai and are not Buddhists. The hill tribes create discord because of their economic success with cash crops. The authors recommend forest, soil, and water conservation among highlanders and lowlanders and broadening development to include other communities.

  12. Seismic Study of the Solar Interior: Inferences from SOI/MDI Observations During Solar Activity

    NASA Technical Reports Server (NTRS)

    Korzennik, Sylvain G.; Wagner, William J. (Technical Monitor)

    2001-01-01

    We have continued in collaboration with Dr. Eff-Darwich (University of La Laguna, Tenerife, Spain) the study of the structure, asphericity and dynamics of the solar interior from p-mode frequencies and frequency splittings. In March 2001, Dr. Eff-Darwich came for 3 weeks visit to CfA. During this visit we completed our work on the inversion of the internal solar rotation rate, and submitted a paper describing this work to the Astrophysical Journal. This paper has been recently revised in response to the referee comments and I expect that it will be accepted for publication very soon. We also have analyzed helioseismic data looking for temporal variations of the solar stratification near the base of the convection zone. We have expanded on the initial work that was presented at the SOHO-10/GONG-2000 meeting (October 2000, Tenerife), and are in the process of writing this up. Substantial progress towards the characterization of high-degree p-modes has been achieved. Indeed, in collaboration Dr. Rabello-Soares (Stanford University), we have gained a clear conceptual understanding of the various elements that affect the leakage matrix of the SOI/MDI instrument. This was presented in an invited talk at the SOHO-10/GONG-2000 meeting (October 2000, Tenerife). Once we will have successfully migrated from a qualitative to a quantitative assessment of these effects, we should be able to generate high-degree p-modes frequencies so crucial in the diagnostic of the layers just below solar surface.

  13. A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

    NASA Astrophysics Data System (ADS)

    Priya, Anjali; Mishra, Ram Awadh

    2016-04-01

    In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

  14. A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

    NASA Astrophysics Data System (ADS)

    Jamali Mahabadi, S. E.; Rajabi, Saba; Loiacono, Julian

    2015-09-01

    In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs. Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100 μA), at drain-source voltage of VDS = 100 V and gate-source voltage of VGS = 25 V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87 μA and 51 μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

  15. Technology.

    ERIC Educational Resources Information Center

    Giorgis, Cyndi; Johnson, Nancy J.

    2002-01-01

    Presents annotations of 30 works of children's literature that support the topic of technology and its influences on readers' daily lives. Notes some stories tell about a time when simple tools enabled individuals to accomplish tasks, and others feature visionaries who used technology to create buildings, bridges, roads, and inventions. Considers…

  16. Bonding III-V material to SOI with transparent and conductive ZnO film at low temperature.

    PubMed

    Huang, Xinnan; Gao, Yonghao; Xu, Xingsheng

    2014-06-16

    A procedure of bonding III-V material to SOI at low temperature using conductive and transparent adhesive ZnO as intermediate layer is demonstrated. Bonding layer thickness of less than 100 nm was achieved in our experiment that guaranteed good light coupling efficiency between III-V and silicon. This bonding method showed good bonding strength with shear stress of 80 N/cm(2). The lowest resistance of the bonded samples was 48.9 Ω and the transmittance of the spin-coated ZnO layer was above 99%. This procedure is applicable for fabricating hybrid III-V/Si lasers. PMID:24977526

  17. SEMICONDUCTOR DEVICES: Analysis of the thermo-optic effect in lateral-carrier-injection SOI ridge waveguide devices

    NASA Astrophysics Data System (ADS)

    Jiate, Zhao; Yong, Zhao; Wanjun, Wang; Yinlei, Hao; Qiang, Zhou; Jianyi, Yang; Minghua, Wang; Xiaoqing, Jiang

    2010-06-01

    The thermo-optic effect in the lateral-carrier-injection pin junction SOI ridge waveguide is analyzed according to the thermal field equation. Numerical analysis and experimental results show that the thermo-optic effect caused by carrier injection is significant in such devices, especially for small structure ones. For a device with a 1000 μm modulation length, the refractive index rise introduced by heat accounts for 1/8 of the total effect under normal working conditions. A proposal of adjusting the electrode position to cool the devices to diminish the thermal-optic effect is put forward.

  18. Ultrafast lateral 600 V silicon SOI PiN diode with geometric traps for preventing waveform oscillation

    NASA Astrophysics Data System (ADS)

    Tsukuda, Masanori; Imaki, Hironori; Omura, Ichiro

    2015-02-01

    An ultrafast lateral silicon PiN diode with geometric traps is proposed using a silicon-on-insulator (SOI) substrate with the traps. The proposed diode successfully suppresses waveform oscillation because the trapped hole suppresses electric field penetration and prevents the oscillation trigger known as 'dynamic punch-through.' Because of the short current path caused by the oscillation prevention, the reverse recovery speed was higher and the reverse recovery loss was strongly reduced. The proposed trap structure and design method would contribute to performance improvement of all power semiconductor devices including IGBTs and power MOSFETs.

  19. The nature and impact of chronic stressors on refugee children in Ban Mai Nai Soi camp, Thailand.

    PubMed

    Meyer, Sarah; Murray, Laura K; Puffer, Eve S; Larsen, Jillian; Bolton, Paul

    2013-01-01

    Refugee camps are replete with risk factors for mental health problems among children, including poverty, disruption of family structure, family violence and food insecurity. This study, focused on refugee children from Burma, in Ban Mai Nai Soi camp in Thailand, sought to identify the particular risks children are exposed to in this context, and the impacts on their mental health and psychosocial well-being. This study employed two qualitative methods--free list interviews and key informant interviews--to identify the main problems impacting children in Ban Mai Nai Soi camp and to explore the causes of these problems and their impact on children's well-being. Respondents in free list interviews identified a number of problems that impact children in this context, including fighting between adults, alcohol use by adults and children, and child abuse and neglect. Across the issues, the causes included economic and social conditions associated with living in the camp and changes in family structures. Children are chronically exposed to stressors during their growth and development in the camp environment. Policies and interventions in areas of protracted displacement in camp-based settings should work to address these stressors and their impacts at community, household and individual levels.

  20. One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

    NASA Astrophysics Data System (ADS)

    Zhang, Jun; Guo, Yu-Feng; Xu, Yue; Lin, Hong; Yang, Hui; Hong, Yang; Yao, Jia-Fei

    2015-02-01

    A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device. Project supported by the National Natural Science Foundation of China (Grant No. 61076073) and the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20133223110003).

  1. Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

    NASA Technical Reports Server (NTRS)

    Tu, Juliana; Smith, Rosemary L.

    1995-01-01

    The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

  2. A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

    NASA Astrophysics Data System (ADS)

    Mert Torunbalci, Mustafa; Emre Alper, Said; Akin, Tayfun

    2015-12-01

    This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au-Si eutectic bonding techniques. The dies sealed with anodic and Au-Si eutectic bonding provide a low vertical feedthrough resistance around 50 Ω. Glass-to-silicon anodically and Au-Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au-Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

  3. Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    We report low-energy proton and alpha particle SEE data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) that demonstrates the criticality of understanding and using low-energy protons for SEE testing of highly-scaled technologies

  4. Technology.

    ERIC Educational Resources Information Center

    Online-Offline, 1998

    1998-01-01

    Focuses on technology, on advances in such areas as aeronautics, electronics, physics, the space sciences, as well as computers and the attendant progress in medicine, robotics, and artificial intelligence. Describes educational resources for elementary and middle school students, including Web sites, CD-ROMs and software, videotapes, books,…

  5. Model of Vernier devices in silicon-on-insulator technology

    NASA Astrophysics Data System (ADS)

    Fan, Guofang; Li, Yuan; Hu, Chunguang; Lei, Lihua; Zhao, Dong; Li, Hongyu; Luo, Yunhan; Zhen, Zhen

    2014-07-01

    In order to increase the number of channels that could be multiplexed or demultiplexed in the dense wavelength division multiplexed (DWDM) system based on the resonators on silicon-on-insulator (SOI) technology, the Vernier effect in the series-coupled racetrack resonators is presented to extend the free spectral range (FSR) of the DWDM systems. A method is developed based on a matrix approach to simulate Vernier devices. A three-dimensional full vectorial finite difference (FVFD) model, specifically suited for high index contrast and smaller size waveguides, for example, a waveguide in SOI technology, is developed to obtain the properties of a waveguide. Finally, the Vernier effect in the two series-coupled racetrack resonators is experimentally verified with an improved FSR and interstitial resonance suppression.

  6. Influence of plasma-etch damage on the interface states in SOI structures investigated by capacitance-voltage measurements and simulations

    NASA Astrophysics Data System (ADS)

    Jo, Yeong-Deuk; Koh, Jung-Hyuk; Ha, Jae-Geun; Kim, Ji-Hong; Cho, Dae-Hyung; Moon, Byung-Moo; Koo, Sang-Mo

    2009-12-01

    Au/SiO2/n-Si metal-oxide-silicon-on-insulator (MOSOI) capacitors were fabricated to study the damage caused by reactive ion etching (RIE) on (1 1 0) oriented silicon-on-insulator (SOI) substrates. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measurements revealed that C-V curves significantly change and a negative voltage shift occurs for plasma-damaged capacitors. The simulated band diagram profiles and potential distribution of the corresponding structures indicate that the C-V shift is mainly due to the removal of a parasitic depletion capacitance (Cp) in the substrate, when the interface charges (Qf) are present at the gate oxide/SOI interface. For etch-damaged MOSOI samples, the surface roughness and the interface charges (Qf) have been found to increase by ~1.94 × 1012 cm-2 with respect to the reference devices, whereas the increase was reduced for sacrificial-oxidation treated samples, which implies a recovery from the plasma-induced etch damage on SOI structures.

  7. Structural makeup, biopolymer conformation, and biodegradation characteristics of a newly developed super genotype of oats (CDC SO-I versus conventional varieties): a novel approach.

    PubMed

    Damiran, Daalkhaijav; Yu, Peiqiang

    2010-02-24

    Recently, a new "super" genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE(L3x), 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  8. Structural Make-up, Biopolymer Conformation, and Biodegradation Characteristics of Newly Developed Super Genotype of Oats (CDC SO-I vs. Conventional Varieties): Novel Approach

    SciTech Connect

    Damiran, D.; Yu, P

    2010-01-01

    Recently, a new 'super' genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE{sub L3x}, 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  9. Development FD-SOI MOSFET Amplifiers for Integrated Read-Out Circuit of Superconducting-Tunnel-Junction Single-Photon-Detectors

    SciTech Connect

    Kiuchi, Kenji; et al.

    2015-07-27

    We proposed a new high-resolution single-photon infrared spectrometer for search for radiative decay of cosmic neutrino background (Cν#23;B). The superconducting-tunnel-junctions(STJs) are used as a single-photon counting device. Each STJ consists of Nb/Al/AlxOy/Al/Nb layers, and their thicknesses are optimized for the operation temperature at 370 mK cooled by a 3He sorption refrigerator. Our STJs achieved the leak current 250 pA, and the measured data implies that a smaller area STJ fulfills our requirement. FD-SOI MOSFETs are employed to amplify the STJ signal current in order to increase signal-to-noise ratio (S/N). FD-SOI MOSFETs can be operated at cryogenic temperature of 370 mK, which reduces the noise of the signal amplification system. FD-SOI MOSFET characteristics are measured at cryogenic temperature. The Id-Vgs curve shows a sharper turn on with a higher threshold voltage and the Id-Vds curve shows a nonlinear shape in linear region at cryogenic temperature. Taking into account these effects, FD-SOI MOSFETs are available for read-out circuit of STJ detectors. The bias voltage for STJ detectors is 0.4 mV, and it must be well stabilized to deliver high performance. We proposed an FD-SOI MOSFET-based charge integrated amplifier design as a read-out circuit of STJ detectors. The requirements for an operational amplifier used in the amplifier is estimated using SPICE simulation. The op-amp is required to have a fast response (GBW ≥ #21;100 MHz), and it must have low power dissipation as compared to the cooling power of refrigerator.

  10. A femtogram resolution mass sensor platform, based on SOI electrostatically driven resonant cantilever. Part I: electromechanical model and parameter extraction.

    PubMed

    Teva, J; Abadal, G; Torres, F; Verd, J; Pérez-Murano, F; Barniol, N

    2006-01-01

    A microcantilever based platform for mass detection in the femtogram range has been integrated in the doped top silicon layer of a SOI substrate. The on-plane fundamental resonance mode of the cantilever is excited electrostatically and detected capacitively by means of two parallel placed electrodes in a two port configuration. An electromechanical model of the cantilever-electrodes transducer and its implementation in a SPICE environment are presented. The model takes into account non-linearities from variable cantilever-electrode gap, fringing field contributions and real deflection shape of the cantilever for the calculation of the driving electrostatic force. A fitting of the model to the measured S(21) transmitted power frequency response is performed to extract the characteristic sensor parameters as Young modulus, Q factor, electrical parasitics and mass responsivity.

  11. Increased sensitivity through maximizing the extinction ratio of SOI delay-interferometer receiver for 10G DPSK.

    PubMed

    Aamer, M; Griol, A; Brimont, A; Gutierrez, A M; Sanchis, P; Håkansson, A

    2012-06-18

    We present an optimized design for a 10G- differential-phase-shift-keyed (DPSK) receiver based on a silicon-on-insulator (SOI) unbalanced tunable Mach-Zehnder interferometer (MZI) switch in sequence with a Mach-Zehnder delay interferometer (MZDI). The proposed design eliminates the limitation in sensitivity of the device produced by the waveguide propagation losses in the delay line. A 2.3 dB increase in receiver sensitivity at a bit-error-rate (BER) of 10(-9) is experimentally measured over a standard implementation. The enhanced sensitivity is achieved with zero power consumption by tuning the operating wavelength or with less than 5 mW for a fixed wavelength using microheaters. Also the foot-print of the device is minimized to 0.11 mm(2) by the use of compact spirals.

  12. Low frequency noise variability in ultra scaled FD-SOI n-MOSFETs: Dependence on gate bias, frequency and temperature

    NASA Astrophysics Data System (ADS)

    Theodorou, C. G.; Ioannidis, E. G.; Haendler, S.; Josse, E.; Dimitriadis, C. A.; Ghibaudo, G.

    2016-03-01

    In this paper, a parametric statistical analysis of the low-frequency noise (LFN) in very small area (W·L ≈ 10-3 μm2) 14 nm fully depleted silicon-on-insulator (FD-SOI) n-MOS devices is presented. It has been demonstrated that the LFN origin is due to carrier trapping/detrapping into gate dielectric traps near the interface and the mean noise level in such small area MOSFETs is well approached by the carrier number fluctuations model in all measurement conditions. The impact of gate voltage bias and temperature on the LFN variability, as well as the standard deviation dependence on frequency have been studied for the first time, focusing on their relation to the Random Telegraph Noise (RTN) effect and its characteristics.

  13. Comparison of the radiation hardness of various VLSI technologies for defense applications

    SciTech Connect

    Gibbon, C.F.

    1985-01-01

    In this review the radiation hardness of various potential very large scale (VLSI) IC technologies is evaluated. IC scaling produces several countervailing trends. Reducing vertical dimensions tends to increase total dose hardness, while reducing lateral feature sizes may increase susceptibility to transient radiation effects. It is concluded that during the next decade at least, silicon complimentary MOS (CMOS), perhaps on an insulating substrate (SOI) will be the technology of choice for VLSI in defense systems.

  14. A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology

    PubMed Central

    Sun, Kexu; Gao, Zheng; Gui, Ping; Wang, Rui; Oguzman, Ismail; Xu, Xiaochen; Vasanth, Karthik; Zhou, Qifa; Shung, K. Kirk

    2015-01-01

    This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7-μm CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 Vpp, and a second-order harmonic distortion (HD2) of −56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle. PMID:25914609

  15. Design of a switch matrix gate/bulk driver controller for thin film lithium microbatteries using microwave SOI technology

    NASA Technical Reports Server (NTRS)

    Whitacre, J.; West, W. C.; Mojarradi, M.; Sukumar, V.; Hess, H.; Li, H.; Buck, K.; Cox, D.; Alahmad, M.; Zghoul, F. N.; Jackson, J.; Terry, S.; Blalock, B.

    2003-01-01

    This paper presents a design approach to help attain any random grouping pattern between the microbatteries. In this case, the result is an ability to charge microbatteries in parallel and to discharge microbatteries in parallel or pairs of microbatteries in series.

  16. Three-dimensional simulations in optimal performance trial between two types of Hall sensors fabrication technologies

    NASA Astrophysics Data System (ADS)

    Paun, Maria-Alexandra

    2015-10-01

    The main objective of the present work is to make a comparison between Hall devices integrated in regular bulk and Silicon-on-Insulator (SOI) CMOS technology. A three-dimensional model based on numerical estimation is provided for a particular XL Hall structure in two different technologies (the first one is XFAB XH 0.35 μm regular bulk CMOS and the second one is XFAB SOI XI10 1 μm non-fully depleted). In assessing the performance of the Hall Effect sensors included in the comparison, both three-dimensional physical simulations and measurements results will be used. In order to discriminate which category of sensors has the highest performance, their main characteristic parameters, including input resistance, Hall voltage, absolute sensitivity and their temperature drift, will be extracted and compared. Electrostatic potential and current density distribution are important aspects that are also investigated. The particular technology offering the highest sensor performance is identified.

  17. Advanced Microelectronics Technologies for Future Small Satellite Systems

    NASA Technical Reports Server (NTRS)

    Alkalai, Leon

    1999-01-01

    Future small satellite systems for both Earth observation as well as deep-space exploration are greatly enabled by the technological advances in deep sub-micron microelectronics technologies. Whereas these technological advances are being fueled by the commercial (non-space) industries, more recently there has been an exciting new synergism evolving between the two otherwise disjointed markets. In other words, both the commercial and space industries are enabled by advances in low-power, highly integrated, miniaturized (low-volume), lightweight, and reliable real-time embedded systems. Recent announcements by commercial semiconductor manufacturers to introduce Silicon On Insulator (SOI) technology into their commercial product lines is driven by the need for high-performance low-power integrated devices. Moreover, SOI has been the technology of choice for many space semiconductor manufacturers where radiation requirements are critical. This technology has inherent radiation latch-up immunity built into the process, which makes it very attractive to space applications. In this paper, we describe the advanced microelectronics and avionics technologies under development by NASA's Deep Space Systems Technology Program (also known as X2000). These technologies are of significant benefit to both the commercial satellite as well as the deep-space and Earth orbiting science missions. Such a synergistic technology roadmap may truly enable quick turn-around, low-cost, and highly capable small satellite systems for both Earth observation as well as deep-space missions.

  18. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures

    NASA Astrophysics Data System (ADS)

    Oliveira, Alberto Vinicius de; Agopian, Paula Ghedini Der; Martino, Joao Antonio; Simoen, Eddy; Claeys, Cor; Collaert, Nadine; Thean, Aaron

    2016-09-01

    This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25 °C to 150 °C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.

  19. A silicon doped hafnium oxide ferroelectric p-n-p-n SOI tunneling field-effect transistor with steep subthreshold slope and high switching state current ratio

    NASA Astrophysics Data System (ADS)

    Marjani, Saeid; Hosseini, Seyed Ebrahim; Faez, Rahim

    2016-09-01

    In this paper, a silicon-on-insulator (SOI) p-n-p-n tunneling field-effect transistor (TFET) with a silicon doped hafnium oxide (Si:HfO2) ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band-to-band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3) and strontium bismuth tantalate (SrBi2Ta2O9) provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p-n-p-n SOI TFET, the on-state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS) is effectively reduced. The simulation results of Si:HfO2 ferroelectric p-n-p-n SOI TFET show significant improvement in transconductance (˜9.8X enhancement) at high overdrive voltage and average subthreshold slope (˜35% enhancement over nine decades of drain current) at room temperature, indicating that this device is a promising candidate to strengthen the performance of p-n-p-n and conventional TFET for a switching performance.

  20. A National Partnership-Based Summer Learning Initiative to Engage Underrepresented Students with Science, Technology, Engineering and Mathematics

    NASA Technical Reports Server (NTRS)

    Melvin, Leland

    2010-01-01

    In response to the White House Educate to Innovate campaign, NASA developed a new science, technology, engineering, and mathematics (STEM) education program for non-traditional audiences that also focused on public-private partnerships and nationwide participation. NASA recognized that summer break is an often overlooked but opportune time to engage youth in STEM experiences, and elevated its ongoing commitment to the cultivation of diversity. The Summer of Innovation (SoI) is the resulting initiative that uses NASA's unique missions and resources to boost summer learning, particularly for students who are underrepresented, underserved and underperforming in STEM. The SoI pilot, launched in June 2010, is a multi-faceted effort designed to improve STEM teaching and learning through partnership, multi-week summer learning programs, special events, a national concluding event, and teacher development. The SoI pilot features strategic infusion of NASA content and educational resource materials, sustainability through STEM Learning Communities, and assessments of effectiveness of SoI interventions with other pilot efforts. This paper examines the inception and development of the Summer of Innovation pilot project, including achievements and effectiveness, as well as lessons learned for future efforts.

  1. Engineered SOI slot waveguide ring resonator V-shape resonance combs for refraction index sensing up to 1300nm/RIU (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Zhang, Weiwei; Serna, Samuel; Le Roux, Xavier; Vivien, Laurent; Cassan, Eric

    2016-05-01

    Bio-detection based on CMOS technology boosts the miniaturization of detection systems and the success on highly efficient, robust, accurate, and low coast Lab-on-Chip detection schemes. Such on chip detection technologies have covered healthy related harmful gases, bio-chemical analytes, genetic micro RNA, etc. Their monitoring accuracy is mainly qualified in terms of sensitivity and limit of the detection (LOD) of the detection system. In this context, recently developed silicon on insulator (SOI) optical devices have displayed highly performant detection abilities that LOD could go beyond 10-8RIU and sensitivity could exceeds 103nm/RIU. The SOI integrated optical sensing devices include strip/slotted waveguide consisting in structures like Mach-Zehnder interferometers (MZI), ring resonators (RR), nano cavities, etc. Typically, hollow core RR and nano-cavities could exhibit higher sensitivity due to their optical mode confinement properties with a partial localization of the electric field in low index sensing regions than devices based on evanescent field tails outside of the optical cores. Furthermore, they also provide larger sensing areas for surface functionalization to reach higher sensitivities and lower LODs. The state of art of hollow core devices, either based on Bragg gratings formed from a slot waveguide cavity or photonic crystal slot cavities, show sensitivities (S) up to 400nm/RIU and Figure of Merit (FOM) around 3,000 in water environment, FOM being defined as the inverse of LOD and precisely as FOM=SQ/λ, with λ the resonance wavelength and Q the quality factor of the considered resonator. Such high achieved FOMs in nano cavities are mainly due to their large Q factors around 15,000. While for mostly used RR, which do not require particular design strategies, relatively low Q factors around 1800 in water are met and moderate sensitivities about 300nm/RIU are found. In this work, we present here a novel slot ring resonator design to make

  2. Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

    NASA Astrophysics Data System (ADS)

    Kilchytska, V.; Bol, D.; De Vos, J.; Andrieu, F.; Flandre, D.

    2013-06-01

    This paper investigates both electrostatic control improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing top- and back-gate (substrate or ground plane) as Vbg = k · Vg) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. Improved performance (in terms of transconductance, drive current and early voltage) in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. QDG mode is demonstrated to allow threshold voltage tuning, subthreshold swing reduction and on-current enhancement without off-state current degradation, thus of interest for digital applications. The unique feature of QDG mode is finally exploited to boost the performances of the sleep transistor in the practical use case of a power-gated processor. About 30% reduction of the leakage in stand-by mode is achieved at nominal Vg with a Vbg of 3 V, which can be generated at marginal area/power overheads with an on-chip charge pump with an architecture proposed in this paper.

  3. Collaboration and involvement of persons with lived experience in planning Canada's At Home/Chez Soi project.

    PubMed

    Nelson, Geoffrey; Macnaughton, Eric; Curwood, Susan Eckerle; Egalité, Nathalie; Voronka, Jijian; Fleury, Marie-Josée; Kirst, Maritt; Flowers, Linsay; Patterson, Michelle; Dudley, Michael; Piat, Myra; Goering, Paula

    2016-03-01

    Planning the implementation of evidence-based mental health services entails commitment to both rigour and community relevance, which entails navigating the challenges of collaboration between professionals and community members in a planning environment which is neither 'top-down' nor 'bottom-up'. This research focused on collaboration among different stakeholders (e.g. researchers, service-providers, persons with lived experience [PWLE]) at five project sites across Canada in the planning of At Home/Chez Soi, a Housing First initiative for homeless people with mental health problems. The research addressed the question of what strategies worked well or less well in achieving successful collaboration, given the opportunities and challenges within this complex 'hybrid' planning environment. Using qualitative methods, 131 local stakeholders participated in key informant or focus group interviews between October 2009 and February 2010. Site researchers identified themes in the data, using the constant comparative method. Strategies that enhanced collaboration included the development of a common vision, values and purpose around the Housing First approach, developing a sense of belonging and commitment among stakeholders, bridging strategies employed by Site Co-ordinators and multiple strategies to engage PWLE. At the same time, a tight timeline, initial tensions, questions and resistance regarding project and research parameters, and lack of experience in engaging PWLE challenged collaboration. In a hybrid planning environment, clear communication and specific strategies are required that flow from an understanding that the process is neither fully participatory nor expert-driven, but rather a hybrid of both. PMID:25689287

  4. New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

    NASA Astrophysics Data System (ADS)

    Li, Qi; Li, Hai-Ou; Tang, Ning; Zhai, Jiang-Hui; Song, Shu-Xiang

    2015-03-01

    A new SOI power device with multi-region high-concentration fixed charge (MHFC) is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer (BOX), by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS. Project supported by the State Key Laboratory of Electronic Thin Films and Integrated Devices of China (Grant No. KFJJ201205), the Department of Education Project of Guangxi Province, China (Grant No. 201202ZD041), the Postdoctoral Science Foundation Project of China (Grant Nos. 2012M521127 and 2013T60566), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

  5. SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs

    SciTech Connect

    Huque, Mohammad A; Tolbert, Leon M; Blalock, Benjamin; Islam, Syed K

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  6. Double gate (DG)-SOI ratioed logic with symmetric DG load??a novel approach for sub 50 nm low-voltage/low-power circuit design

    NASA Astrophysics Data System (ADS)

    Mitra, S.; Salman, A.; Ioannou, D. P.; Tretz, C.; Ioannou, D. E.

    2004-11-01

    In this paper we introduce a novel logic gate family based on Double Gate (DG) SOI MOSFETs for low voltage/low power circuits. The logic gates are based on ratioed logic with depletion-mode (i.e., intrinsically on) Symmetric DG (SDG) load transistors and inversion-mode Asymmetric DG (ADG) driver transistors. Using this technique a basic inverter was designed, with better performance compared to "classical" CMOS DG design. This technique was extended to create a complete set of basic logic gates including NOR2, NAND2 and XOR2 gates.

  7. On-chip grating coupler array on the SOI platform for fan-in/fan-out of MCFs with low insertion loss and crosstalk.

    PubMed

    Ding, Yunhong; Ye, Feihong; Peucheret, Christophe; Ou, Haiyan; Miyamoto, Yutaka; Morioka, Toshio

    2015-02-01

    We report the design and fabrication of a compact multi-core fiber fan-in/fan-out using a grating coupler array on the SOI platform. The grating couplers are fully-etched, enabling the whole circuit to be fabricated in a single lithography and etching step. Thanks to the apodized design for the grating couplers and the introduction of an aluminum reflective mirror, a highest coupling efficiency of -3.8 dB with 3 dB coupling bandwidth of 48 nm and 1.5 dB bandwidth covering the whole C band, together with crosstalk lower than -32 dB are demonstrated.

  8. Preliminary Investigation of an SOI-based Arrayed Waveguide Grating Demodulation Integration Microsystem

    PubMed Central

    Li, Hongqiang; Zhou, Wenqian; Liu, Yu; Dong, Xiaye; Zhang, Cheng; Miao, Changyun; Zhang, Meiling; Li, Enbang; Tang, Chunxiao

    2014-01-01

    An arrayed waveguide grating (AWG) demodulation integration microsystem is investigated in this study. The system consists of a C-band on-chip LED, a 2 × 2 silicon nanowire-based coupler, a fiber Bragg grating (FBG) array, a 1 × 8 AWG, and a photoelectric detector array. The coupler and AWG are made from silicon-on-insulator wafers using electron beam exposure and response-coupled plasma technology. Experimental results show that the excess loss in the MMI coupler with a footprint of 6 × 100 μm2 is 0.5423 dB. The 1 × 8 AWG with a footprint of 267 × 381 μm2 and a waveguide width of 0.4 μm exhibits a central channel loss of −3.18 dB, insertion loss non-uniformity of −1.34 dB, and crosstalk level of −23.1 dB. The entire system is preliminarily tested. Wavelength measurement precision is observed to reach 0.001 nm. The wavelength sensitivity of each FBG is between 0.04 and 0.06 nm/dB. PMID:24797561

  9. A 100-V High-Performance SOI Trench LDMOS with Low Cell Pitch

    NASA Astrophysics Data System (ADS)

    Punetha, Mayank; Singh, Yashvir

    2015-10-01

    In this paper, we report structural modifications in the conventional laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor on thin silicon-on-insulator by incorporating trenches into the planar technology. The proposed power LDMOS includes two trenches built in the drift region on both sides of the p-base. The gate electrode is placed vertically in the left-side trench, while the right-side trench is filled with oxide. The proposed trench structure suppresses the electric field in the drift region due to the reduced-surface-field effect and allows increased doping concentration to achieve a better trade-off between breakdown voltage and on-resistance. At breakdown voltage of 103 V, the proposed device provides six times higher Baliga's figure of merit, 38% decrease in gate-drain charge, and 9.5 times improvement in dynamic figure of merit as compared with the conventional LDMOS. Further, the proposed device achieves four times reduction in cell pitch as compared with the conventional structure.

  10. Recent developments in terahertz sensing technology

    NASA Astrophysics Data System (ADS)

    Shur, Michael

    2016-05-01

    Terahertz technology has found numerous applications for the detection of biological and chemical hazardous agents, medical diagnostics, detection of explosives, providing security in buildings, airports, and other public spaces, shortrange covert communications (in the THz and sub-THz windows), and applications in radio astronomy and space research. The expansion of these applications will depend on the development of efficient electronic terahertz sources and sensitive low-noise terahertz detectors. Schottky diode frequency multipliers have emerged as a viable THz source technology reaching a few THz. High speed three terminal electronic devices (FETs and HBTs) have entered the THz range (with cutoff frequencies and maximum frequencies of operation above 1 THz). A new approach called plasma wave electronics recently demonstrated an efficient terahertz detection in GaAs-based and GaN-based HEMTs and in Si MOS, SOI, FINFETs and in FET arrays. This progress in THz electronic technology has promise for a significant expansion of THz applications.

  11. Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Saramekala, Gopi Krishna; Dubey, Sarvesh; Tiwari, Pramod Kumar

    2014-12-01

    Ultrathin-body (UTB) SOI MOSFETs, which possess excellent short-channel effect immunity and high current on-off ratio, are expected to put back the conventional MOSFETs in high performance digital integrated circuits by the end of year 2014 to continue the current scaling trend. In this paper, targeting systems-on-a-chip (SOC) applications, a simulation based extensive study is carried out to evaluate the analog and RF performance of source/drain and gate engineered ultrathin body SOI MOSFETs, as both the digital and analog performance of the device must be excellent for SOC applications. The performance evaluation has been done in terms of device parameters like device capacitances (Cgs and Cgd), drain current (Id), transconductance (gm), transconductance generation efficiency (gm/Id), intrinsic gain (gm/gd), cut-off frequency (fT) and the maximum frequency of oscillation (fmax). The RF figures-of-merit (FoM) i.e., fT and fmax have been determined by using H and Y parameters obtained from high frequency simulation of the structure. The numerical simulation is performed using ATLASTM, a 2-D device simulator from SILVACO Inc.

  12. Effects of substrate voltage on noise characteristics and hole lifetime in SOI metal-oxide-semiconductor field-effect transistor photon detector.

    PubMed

    Putranto, Dedy Septono Catur; Priambodo, Purnomo Sidi; Hartanto, Djoko; Du, Wei; Satoh, Hiroaki; Ono, Atsushi; Inokawa, Hiroshi

    2014-09-01

    Low-frequency noise and hole lifetime in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are analyzed, considering their use in photon detection based on single-hole counting. The noise becomes minimum at around the transition point between front- and back-channel operations when the substrate voltage is varied, and increases largely on both negative and positive sides of the substrate voltage showing peculiar Lorentzian (generation-recombination) noise spectra. Hole lifetime is evaluated by the analysis of drain current histogram at different substrate voltages. It is found that the peaks in the histogram corresponding to the larger number of stored holes become higher as the substrate bias becomes larger. This can be attributed to the prolonged lifetime caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small absolute substrate bias is favorable for short lifetime and low noise, leading to high-speed operation. PMID:25321581

  13. 6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

    NASA Astrophysics Data System (ADS)

    Rashmi; Kranti, Abhinav; Armstrong, G. Alastair

    2008-07-01

    The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/σ) ratio in the range 2 3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM ~ 162 mV, Iwr ~ 35 µA and low Ileak ~ 70 pA at VDD = 0.6 V, while maintaining SNM ~ 30%VDD over the supply voltage (VDD) range of 0.4 0.9 V.

  14. Low frequency noise and radiation response in the partially depleted SOI MOSFETs with ion implanted buried oxide

    NASA Astrophysics Data System (ADS)

    Liu, Yuan; Chen, Hai-Bo; Liu, Yu-Rong; Wang, Xin; En, Yun-Fei; Li, Bin; Lu, Yu-Dong

    2015-08-01

    Low frequency noise behaviors of partially depleted silicon-on-insulator (PDSOI) n-channel metal-oxide semiconductors (MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from 44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/V·s to 363.65 cm2/V·s. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10-10 V2·Hz-1 and 2.7×10-8 V2·Hz-1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017 cm-3·eV-1 to 6.16×1018 cm-3·eV-1. Based on carrier mobility fluctuation theory, the extracted average Hooge’s parameter in these devices increases from 3.92×10-5 to 1.34×10-2 after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 M·rad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are -10.82 V and -31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed. Project supported by the National Natural Science Foundation of China (Grant Nos. 61204112 and 61204116).

  15. A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

    NASA Astrophysics Data System (ADS)

    Morin, Pierre; Maitrejean, Sylvain; Allibert, Frederic; Augendre, Emmanuel; Liu, Qing; Loubet, Nicolas; Grenouillet, Laurent; Pofelski, Alexandre; Chen, Kangguo; Khakifirooz, Ali; Wacquez, Romain; Reboh, Shay; Bonnevialle, Aurore; le Royer, Cyrille; Morand, Yves; Kanyandekwe, Joel; Chanemougamme, Daniel; Mignot, Yann; Escarabajal, Yann; Lherron, Benoit; Chafik, Fadoua; Pilorget, Sonia; Caubet, Pierre; Vinet, Maud; Clement, Laurent; Desalvo, Barbara; Doris, Bruce; Kleemeier, Walter

    2016-03-01

    This paper reviews the different stressor techniques used in microelectronics, in the scope of the Ultra-Thin Body & Buried Oxide Fully-Depleted Silicon On Insulator technology (UTBB FD-SOI). We compare the mechanical efficiency of the various stressors and present the impact of device dimensions (active area, gate length and pitch) on their efficiency. Our study emphasizes the high efficiency, for the FD-SOI technology, of the intrinsically strained channels, compared to the traditional embedded raised source/drain and contact-etch stop liner. With these techniques FD-SOI technology has already demonstrated channel stress higher than 1.5 GPa for n type transistor and -2.3 GPa for the p type devices and we envision channel stress values up to ±3 GPa for n and p transistor channel, respectively. This performance is partly due to the mechanical configuration of intrinsically strained channels, in parallel mode rather than in serial mode as for the previous generation of stressors, which makes them less sensitive to the scaling of the contacted gate pitch. We also highlight another key element the high mechanical stability of the UTBB technology, related to the limited channel thickness (around 6 nm) which enables achieving highly stressed channel without substantial adaptation of the integration flows.

  16. Introducing porous silicon as a sacrificial material to obtain cavities in substrate of SOI wafers and a getter material for MEMS devices

    NASA Astrophysics Data System (ADS)

    Mohammad, Wajihuddin

    Microelectromechanical system (MEMS) resonators have been a subject of research for more than four decades. The reason is the huge potential they possess for frequency applications. The use of a MEMS resonator as the timing element has an experimental history and huge progress has been made in this direction. Vacuum encapsulated MEMS resonators are required for high precision frequency control. Hence, a device with a high quality factor and durability is needed. In this effort, a new process for producing a cavity in the substrate of Silicon on insulator (SOI) MEMS devices and augmenting it with a getter using porous silicon is developed. The process involves a mask-less, self-aligned cost effective electrochemical etching process. A 10 mum cavity is introduced in the substrate of SOI dies. This helps in increasing the packaging volume of the SOI resonators along with mitigating the viscous damping effects. The stiction problem in MEMS devices is effectively eliminated and millimeter long slender MEMS structures do not get stuck to the substrate. It also helps in reducing the parasitic capacitance between the device side and the substrate. The porous silicon getter is introduced as a getter material for vacuum encapsulated MEMS devices. This getter needs no external mask and is self-aligned. It requires no external heat or additional materials to operate. The highly reactive porous silicon can readily react with the oxygen gas and form an oxide layer that can trap other gas molecules. This helps in maintaining low pressures in the cavity of the bonded MEMS resonators. A tuning fork resonator with a resonant frequency of 245 kHz was used to realize the benefits of the cavity and the getter. It was observed that the unpackaged device with the cavity in the substrate showed two times better quality factor at different pressures, than the device with no cavity. In order to understand the benefits of porous silicon as a getter, the MEMS devices (one with only a cavity

  17. Determined Initial lead for South Of Isua (SOI) terrain suggests a single homogeneous source for it and possibly other archaean rocks

    NASA Astrophysics Data System (ADS)

    Tera, F.

    2011-12-01

    A Thorogenic-Uranogenic Lead Isotope Plane (TULIP), which entails plotting 206/208 (or its reverse) vs 207/208 (or its reverse), was applied to the Pb data on South of Isua (SOI) by Kamber et al., (1). When the data on 20 samples of these rocks and feldspars are plotted in pairs (each pair is a rock and its feldspar) on TULIP, they fall on 10 mixing lines that converge on a single spot (Fig. 1). This is the end member initial lead (EMIL). The 206/208 & 207/208 so determined are 0.3675 and 0.43525, respectively. From these values one calculates 207/206 = 1.1843 ± 0.0007, for EMIL. This pattern requires either: A) each pair has a singular kappa, K = 232Th/238U, different from others, or B) a pair's in situ decay Pb was homogenized in recent times. On 204/206 vs 207/206 diagram, the whole rocks of SOI define a 3.776 Ga isochron (2). From this and EMIL's 207/206, one obtains: 206/204 = 10.977, 207/204 = 12.974; and 208/204 = 29.756. This singularity of initial Pb contrasts with a deduced variability by the original authors (1). EMIL's radiogenic *(207/206) = 1.6220, gives a single-stage age = 5.9 Ga, indicating inapplicability of its evolution in one stage. Also, the μ calculated from 238U-206Pb for the single stage is different from that inferred from 235U-207Pb, confirming disqualification of this scenario. Reconciliation of the two decay schemes necessitates assumption of EMIL evolution in a minimum of two stages. Starting at 4.563 Ga, five scenarios were assumed: First stage ends and second starts at 4.55, 4.54, 4.53, 4.52 or 4.51 Ga. Second stages end at 3.776 Ga. The calculated μ1 for the first stage are 106, 59.5, 44.6, 36.3 and 30.9 respectively. For μ2 the change is limited, from 5.45 to 5.28. Only an average calculated K for both stages is possible. For the five outlined scenarios it ranges from 1.118 to 1.111. Earlier, Tera (3) observed that initial Pb of the oldest terrestrial reservoir requires evolution in two stages. There too μ1 >> μ2. Data on

  18. Mourir chez soi

    PubMed Central

    Kiyanda, Brigitte Gagnon; Dechêne, Geneviève; Marchand, Robert

    2015-01-01

    Résumé Objectif Démontrer que des infirmières dédiées en soins palliatifs d’un centre local de services communautaires (CLSC) urbain peuvent garder à domicile jusqu’au décès plus de 50 % de leurs patients en fin de vie et que le suivi médical à domicile est un facteur déterminant du décès à domicile. Type d’étude Analyse du lieu de décès des patients décédés en 2012 et 2013 suivis par les infirmières dédiées (N = 212), en fonction du suivi médical. Contexte Soins palliatifs du CLSC de Verdun, un territoire urbain situé dans le sud-ouest de Montréal. Participants Un total de 212 patients en fin de vie décédés en 2012 et 2013, suivis par 3 infirmières dédiées en soins palliatifs. Principaux paramètres à l’étude Le pourcentage de décès à domicile. Résultats Des 212 patients suivis à domicile par les infirmières en soins palliatifs, 56,6 % sont décédés à domicile, 62,6 % lorsque suivis par des médecins à domicile du CLSC, contre 5,0 % lorsque sans médecin à domicile. Conclusion Le développement des services médicaux à domicile au Québec, couplé à une simple restructuration des services de soins infirmiers des CLSC, permettrait à plus de 50 % des patients en fin de vie à domicile suivis par ces CLSC d’y demeurer jusqu’au décès, le souhait d’une majorité.

  19. Investigation of Coulomb scattering on sSi/Si0.5Ge0.5/sSOI quantum-well p-MOSFETs

    NASA Astrophysics Data System (ADS)

    Jiao, Wen; Qiang, Liu; Chang, Liu; Yize, Wang; Bo, Zhang; Zhongying, Xue; Zengfeng, Di; Wenjie, Yu; Qingtai, Zhao

    2016-09-01

    sSi/Si0.5Ge0.5/sSOI quantum-well (QW) p-MOSFETs with HfO2/TiN gate stack were fabricated and characterized. According to the low temperature experimental results, carrier mobility of the strained Si0.5Ge0.5 QW p-MOSFET was mainly governed by phonon scattering from 300 to 150 K and Coulomb scattering below 150 K, respectively. Coulomb scattering was intensified by the accumulated inversion charges in the Si cap layer of this Si/SiGe heterostructure, which led to a degradation of carrier mobility in the SiGe channel, especially at low temperature. Project supported by the National Natural Science Foundation of China (Nos. 61306126, 61306127, 61106015) and the CAS International Collaboration and Innovation Program on High Mobility Materials Engineering.

  20. In depth static and low-frequency noise characterization of n-channel FinFETs on SOI substrates at cryogenic temperature

    NASA Astrophysics Data System (ADS)

    Achour, H.; Cretu, B.; Routoure, J.-M.; Carin, R.; Talmat, R.; Benfdila, A.; Simoen, E.; Claeys, C.

    2014-08-01

    The impact of cryogenic temperature operation (10 K) on the short channel effects and low frequency noise was analysed on strained and unstrained n-channel FinFET transistors fabricated on silicon on insulator (SOI) substrates in order to evaluate the devices static performances and to study the low frequency noise mechanisms. The main electrical parameters are investigated and it is evidenced that even at very low temperatures, the strain-engineering techniques boost the devices performances in terms of mobility, threshold voltage, access resistances and drain saturation currents. The DIBL effect, Early voltage and the intrinsic gain are ameliorated only for the short channel devices. A drawback, however, is that slightly improved turn-on capabilities may be noted for standard channel devices compared to strained ones. Low frequency noise measurements show that the carrier number fluctuations dominate the flicker noise in weak inversion even at 10 K operation. Access resistance noise contributions were evidenced in strong inversion.

  1. Vertically Integrated MEMS SOI Composite Porous Silicon-Crystalline Silicon Cantilever-Array Sensors: Concept for Continuous Sensing of Explosives and Warfare Agents

    NASA Astrophysics Data System (ADS)

    Stolyarova, Sara; Shemesh, Ariel; Aharon, Oren; Cohen, Omer; Gal, Lior; Eichen, Yoav; Nemirovsky, Yael

    This study focuses on arrays of cantilevers made of crystalline silicon (c-Si), using SOI wafers as the starting material and using bulk micromachining. The arrays are subsequently transformed into composite porous silicon-crystalline silicon cantilevers, using a unique vapor phase process tailored for providing a thin surface layer of porous silicon on one side only. This results in asymmetric cantilever arrays, with one side providing nano-structured porous large surface, which can be further coated with polymers, thus providing additional sensing capabilities and enhanced sensing. The c-Si cantilevers are vertically integrated with a bottom silicon die with electrodes allowing electrostatic actuation. Flip Chip bonding is used for the vertical integration. The readout is provided by a sensitive Capacitance to Digital Converter. The fabrication, processing and characterization results are reported. The reported study is aimed towards achieving miniature cantilever chips with integrated readout for sensing explosives and chemical warfare agents in the field.

  2. Quantum Dots Based Rad-Hard Computing and Sensors

    NASA Technical Reports Server (NTRS)

    Fijany, A.; Klimeck, G.; Leon, R.; Qiu, Y.; Toomarian, N.

    2001-01-01

    Quantum Dots (QDs) are solid-state structures made of semiconductors or metals that confine a small number of electrons into a small space. The confinement of electrons is achieved by the placement of some insulating material(s) around a central, well-conducting region. Thus, they can be viewed as artificial atoms. They therefore represent the ultimate limit of the semiconductor device scaling. Additional information is contained in the original extended abstract.

  3. Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications Rad-Hard, Miniaturized

    NASA Technical Reports Server (NTRS)

    Adell, Philippe C.; Mojarradi, Mohammad; DelCastillo, Linda Y.; Vo, Tuan A.

    2011-01-01

    A paper discusses the successful development of a miniaturized radiation hardened high-voltage switching module operating at 2.5 kV suitable for space application. The high-voltage architecture was designed, fabricated, and tested using a commercial process that uses a unique combination of 0.25 micrometer CMOS (complementary metal oxide semiconductor) transistors and high-voltage lateral DMOS (diffusion metal oxide semiconductor) device with high breakdown voltage (greater than 650 V). The high-voltage requirements are achieved by stacking a number of DMOS devices within one module, while two modules can be placed in series to achieve higher voltages. Besides the high-voltage requirements, a second generation prototype is currently being developed to provide improved switching capabilities (rise time and fall time for full range of target voltages and currents), the ability to scale the output voltage to a desired value with good accuracy (few percent) up to 10 kV, to cover a wide range of high-voltage applications. In addition, to ensure miniaturization, long life, and high reliability, the assemblies will require intensive high-voltage electrostatic modeling (optimized E-field distribution throughout the module) to complete the proposed packaging approach and test the applicability of using advanced materials in a space-like environment (temperature and pressure) to help prevent potential arcing and corona due to high field regions. Finally, a single-event effect evaluation would have to be performed and single-event mitigation methods implemented at the design and system level or developed to ensure complete radiation hardness of the module.

  4. Housing First for People With Severe Mental Illness Who Are Homeless: A Review of the Research and Findings From the At Home–Chez soi Demonstration Project

    PubMed Central

    Aubry, Tim; Nelson, Geoffrey; Tsemberis, Sam

    2015-01-01

    Objective: To provide a review of the extant research literature on Housing First (HF) for people with severe mental illness (SMI) who are homeless and to describe the findings of the recently completed At Home (AH)–Chez soi (CS) demonstration project. HF represents a paradigm shift in the delivery of community mental health services, whereby people with SMI who are homeless are supported through assertive community treatment or intensive case management to move into regular housing. Method: The AH–CS demonstration project entailed a randomized controlled trial conducted in 5 Canadian cities between 2009 and 2013. Mixed methods were used to examine the implementation of HF programs and participant outcomes, comparing 1158 people receiving HF to 990 people receiving standard care. Results: Initial research conducted in the United States shows HF to be a promising approach, yielding superior outcomes in helping people to rapidly exit homelessness and establish stable housing. Findings from the AH–CS demonstration project reveal that HF can be successfully adapted to different contexts and for different populations without losing its fidelity. People receiving HF achieved superior housing outcomes and showed more rapid improvements in community functioning and quality of life than those receiving treatment as usual. Conclusions: Knowledge translation efforts have been undertaken to disseminate the positive findings and lessons learned from the AH–CS project and to scale up the HF approach across Canada. PMID:26720504

  5. 110 GHz hybrid mode-locked fiber laser with enhanced extinction ratio based on nonlinear silicon-on-insulator micro-ring-resonator (SOI MRR)

    NASA Astrophysics Data System (ADS)

    Liu, Yang; Hsu, Yung; Chow, Chi-Wai; Yang, Ling-Gang; Yeh, Chien-Hung; Lai, Yin-Chieh; Tsang, Hon-Ki

    2016-03-01

    We propose and experimentally demonstrate a new 110 GHz high-repetition-rate hybrid mode-locked fiber laser using a silicon-on-insulator microring-resonator (SOI MRR) acting as the optical nonlinear element and optical comb filter simultaneously. By incorporating a phase modulator (PM) that is electrically driven at a fraction of the harmonic frequency, an enhanced extinction ratio (ER) of the optical pulses can be produced. The ER of the optical pulse train increases from 3 dB to 10 dB. As the PM is only electrically driven by the signal at a fraction of the harmonic frequency, in this case 22 GHz (110 GHz/5 GHz), a low bandwidth PM and driving circuit can be used. The mode-locked pulse width and the 3 dB spectral bandwidth of the proposed mode-locked fiber laser are measured, showing that the optical pulses are nearly transform limited. Moreover, stability evaluation for an hour is performed, showing that the proposed laser can achieve stable mode-locking without the need for optical feedback or any other stabilization mechanism.

  6. Analysis of Stress Effect on (110)-Oriented Single-Gate SOI nMOSFETs Using a Silicon-Thickness-Dependent Deformation Potential.

    PubMed

    Choi, S; Sun, W; Lee, I; Shin, H

    2016-05-01

    The stress effect in uniaxially strained (100)- and (110)-oriented single-gate (SG) silicon-on-insulator (SOI) n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) was analyzed. A model of a silicon-thickness-dependent deformation potential (D(as_T(si))) was used for accurate calculation of mobility using a Schrödinger-Poisson solver. The simulation results obtained using the D(ac_T(si)) model exhibited excellent agreement with the measured mobility for both strained and unstrained conditions. The enhancements in electron mobility under conditions of longitudinal tensile strain were analyzed as a function of the silicon thickness and strain. As the silicon thickness decreased, the mobility enhancement in (100) SG MOSFETs reached a peak, whereas it diminished in (110) SG MOSFETs. As the strain increased, mobility enhancement increased in the (110) case, whereas it saturated in the (100) case. Therefore, larger mobility enhancement in the (110) orientation is expected. These differences in enhancement between the (100) and (110) cases resulted from differences in the quantization mass, which affect the energy difference between the 1st subbands of two-fold and four-fold degenerate valleys, as well as occupancy change. PMID:27483890

  7. Power-efficient carrier-depletion SOI Mach-Zehnder modulators for 4x25Gbit/s operation in the O-band

    NASA Astrophysics Data System (ADS)

    Ferrotti, Thomas; Chantre, Alain; Blampey, Benjamin; Duprez, Hélène; Milesi, Frédéric; Myko, André; Sciancalepore, Corrado; Hassan, Karim; Harduin, Julie; Baudot, Charles; Menezo, Sylvie; Boeuf, Frédéric; Ben Bakir, Badhise

    2015-02-01

    In this paper, we communicate on the design, fabrication, and testing of optical modulators for Silicon-based photonic integrated circuits (Si-PICs) in the O-band (1.31 μm), targeting the 100GBASE-LR4 norm (4 wavelengths at 25 Gbit/s). The modulators have been conceived to be later coupled with hybrid-III-V/Si lasers as well as echelle grating multiplexer, to create a hetero-integrated optical transmitter on a silicon-on-insulator (SOI) platform. The devices are based on a Mach-Zehnder Interferometer (MZI) architecture, where a p-n junction is implanted to provide optical modulation through carrier depletion. A detailed study focusing on the best doping scheme for the junction, aimed at optimizing the overall transmitter performance and power-efficiency is presented. In detail, the trade-off between low optical losses and high modulation efficiency is tackled, with a targeted CMOS-compatible voltage drive of 2.5 V. Process simulations of the junction are realized for the doping profile optimization. Modulators of different lengths are also investigated to study the compromise between extinction ratio, insertion losses and bandwidth. Furthermore, coplanar-strip (SGS) travelling-wave electrodes are designed to maximize the bandwidth, to reach the targeted bit rate of 25 Gbit/s. Measurements show modulation efficiencies up to 19 °/mm (or 2.4 V.cm) for a 2.5 V input voltage, with doping-related losses below 1 dB/mm, in line with theoretical estimates, and well-suited to enhance the Si-PIC transmission and power-efficiency. Finally, an electro-optical (EO) bandwidth at 1.25 V bias is measured above 28 GHz.

  8. Development and characterization of the latest X-ray SOI pixel sensor for a future astronomical mission

    NASA Astrophysics Data System (ADS)

    Nakashima, Shinya; Gando Ryu, Syukyo; Tanaka, Takaaki; Go Tsuru, Takeshi; Takeda, Ayaki; Arai, Yasuo; Imamura, Toshifumi; Ohmoto, Takafumi; Iwata, Atsushi

    2013-12-01

    We have been developing active pixel sensors based on silicon-on-insulator technology for future X-ray astronomy missions. Recently we fabricated the new prototype named “XRPIX2”, and investigated its spectroscopic performance. For comparison and evaluation of different chip designs, XRPIX2 consists of 3 pixel types: Small Pixel, Large Pixel 1, and Large Pixel 2. In Small Pixel, we found that the gains of the 68% pixels are within 1.4% of the mean value, and the energy resolution is 656 eV (FWHM) for 8 keV X-rays, which is the best spectroscopic performance in our development. The pixel pitch of Large Pixel 1 and Large Pixel 2 is twice as large as that of Small Pixel. Charge sharing events are successfully reduced for Large Pixel 1. Moreover Large Pixel 2 has multiple nodes for charge collection in a pixel. We confirmed that the multi-nodes structure is effective to increase charge collection efficiency.

  9. STADIUM SOI reliability simulator for the analysis of hot-electron and ESD-induced degradation in nonisothermal devices

    NASA Astrophysics Data System (ADS)

    Lee, David; Sanders, Thomas J.

    1997-09-01

    This paper addresses the integrated circuit industry needs for non-isothermal simulation in device reliability analysis, initial input factor sensitivity analysis and their software implementation. The key reliability issues are the hot-electron induced oxide damages and electro-static discharge (ESD) damages. The main purpose of this work is to provide a design aid tool to improve device reliability and performance. The reliability simulator developed in this work not only predicts designed device reliability, but also provides some information about the effect of manufacturing variations on reliability. This is accomplished by combining the statistical methodology with existing technology computer aided design (TCAD) tools. The design of experiment (DoE) technique can be successfully employed to analyze the effect of manufacturing variations on the SOT device reliability. As an example, the reliability analysis and the statistical analysis have performed on SOT MOS devices (partially depleted and fully depleted SOT) and submicron bulk-Si MOSFET's to verify the applied modeling method.

  10. Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

    NASA Astrophysics Data System (ADS)

    Tu, Hongen

    This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high

  11. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  12. The role of advocacy coalitions in a project implementation process: the example of the planning phase of the At Home/Chez Soi project dealing with homelessness in Montreal.

    PubMed

    Fleury, Marie-Josée; Grenier, Guy; Vallée, Catherine; Hurtubise, Roch; Lévesque, Paul-André

    2014-08-01

    This study analyzed the planning process (summer 2008 to fall 2009) of a Montreal project that offers housing and community follow-up to homeless people with mental disorders, with or without substance abuse disorders. With the help of the Advocacy Coalition Framework (ACF), advocacy groups that were able to navigate a complex intervention implementation process were identified. In all, 25 people involved in the Montreal At Home/Chez Soi project were surveyed through interviews (n=18) and a discussion group (n=7). Participant observations and documentation (minutes and correspondence) were also used for the analysis. The start-up phase of the At Home/Chez may be broken down into three separate periods qualified respectively as "honeymoon;" "clash of cultures;" and "acceptance & commitment". In each of the planning phases of the At Home/Chez Soi project in Montreal, at least two advocacy coalitions were in confrontation about their specific belief systems concerning solutions to address the recurring homelessness social problem, while a third, more moderate one contributed in rallying most key actors under specified secondary aspects. The study confirms the importance of policy brokers in achieving compromises acceptable to all advocacy coalitions.

  13. Ending homelessness among people with mental illness: the At Home/Chez Soi randomized trial of a Housing First intervention in Toronto

    PubMed Central

    2012-01-01

    Background The At Home/Chez Soi (AH/CS) Project is a randomized controlled trial of a Housing First intervention to meet the needs of homeless individuals with mental illness in five cities across Canada. The objectives of this paper are to examine the approach to participant recruitment and community engagement at the Toronto site of the AH/CS Project, and to describe the baseline demographics of participants in Toronto. Methods Homeless individuals (n = 575) with either high needs (n = 197) or moderate needs (n = 378) for mental health support were recruited through service providers in the city of Toronto. Participants were randomized to Housing First interventions or Treatment as Usual (control) groups. Housing First interventions were offered at two different mental health service delivery levels: Assertive Community Treatment for high needs participants and Intensive Case Management for moderate needs participants. Demographic data were collected via quantitative questionnaires at baseline interviews. Results The effectiveness of the recruitment strategy was influenced by a carefully designed referral system, targeted recruitment of specific groups, and an extensive network of pre-existing services. Community members, potential participants, service providers, and other stakeholders were engaged through active outreach and information sessions. Challenges related to the need for different sectors to work together were resolved through team building strategies. Randomization produced similar demographic, mental health, cognitive and functional impairment characteristics in the intervention and control groups for both the high needs and moderate needs groups. The majority of participants were male (69%), aged >40 years (53%), single/never married (69%), without dependent children (71%), born in Canada (54%), and non-white (64%). Many participants had substance dependence (38%), psychotic disorder (37%), major depressive episode (36%), alcohol

  14. The Impact of a 24 Month Housing First Intervention on Participants’ Body Mass Index and Waist Circumference: Results from the At Home / Chez Soi Toronto Site Randomized Controlled Trial

    PubMed Central

    Woodhall-Melnik, Julia; Misir, Vachan; Kaufman-Shriqui, Vered; O’Campo, Patricia; Stergiopoulos, Vicky; Hwang, Stephen

    2015-01-01

    Research suggests that individuals experiencing homelessness have high rates of overweight and obesity. Unhealthy weights and homelessness are both associated with increased risk of poor health and mortality. Using longitudinal data from 575 participants at the Toronto site of the At Home/Chez Soi randomized controlled trial, we investigate the impact of receiving a Housing First intervention on the Body Mass Index (BMI) and waist circumference of participants with moderate and high needs for mental health support services. The ANCOVA results indicate that the intervention resulted in no significant change in BMI or waist circumference from baseline to 24 months. The findings suggest a need for a better understanding of factors contributing to overweight, obesity, and high waist circumference in populations who have histories of housing precarity and experience low-income in tandem with other concerns such as mental illness and addictions. Trial Registration International Standard Randomized Control Trial Number Register ISRCTN42520374 PMID:26418677

  15. Technology Development.

    ERIC Educational Resources Information Center

    Gomory, Ralph E.

    1983-01-01

    The evolutionary character and complexity of technological development is discussed, focusing on the steam engine and computer as examples. Additional topics include characteristics of science/technology, cultural factors in technological development, technology transfer, and problems in technological organization. (JN)

  16. Laser Technology.

    ERIC Educational Resources Information Center

    Gauger, Robert

    1993-01-01

    Describes lasers and indicates that learning about laser technology and creating laser technology activities are among the teacher enhancement processes needed to strengthen technology education. (JOW)

  17. Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    We report low-energy proton and low-energy alpha particle single-event effects (SEE) data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latches and static random access memory (SRAM) that demonstrates the criticality of using low-energy protons for SEE testing of highly-scaled technologies. Low-energy protons produced a significantly higher fraction of multi-bit upsets relative to single-bit upsets when compared to similar alpha particle data. This difference highlights the importance of performing hardness assurance testing with protons that include energy distribution components below 2 megaelectron-volt. The importance of low-energy protons to system-level single-event performance is based on the technology under investigation as well as the target radiation environment.

  18. Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

    NASA Astrophysics Data System (ADS)

    Pengcheng, Huang; Shuming, Chen; Jianjun, Chen

    2016-03-01

    In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D-TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout. Project supported by the National Natural Science Foundation of China (Grant Nos. 61376109, 61434007, and 61176030) and the Advanced Research Project of National University of Defense Technology, China (Grant No. 0100066314001).

  19. Planning a multi-site, complex intervention for homeless people with mental illness: the relationships between the national team and local sites in Canada's At Home/Chez Soi project.

    PubMed

    Nelson, Geoffrey; Macnaughton, Eric; Goering, Paula; Dudley, Michael; O'Campo, Patricia; Patterson, Michelle; Piat, Myra; Prévost, Natasha; Strehlau, Verena; Vallée, Catherine

    2013-06-01

    This research focused on the relationships between a national team and five project sites across Canada in planning a complex, community intervention for homeless people with mental illness called At Home/Chez Soi, which is based on the Housing First model. The research addressed two questions: (a) what are the challenges in planning? and (b) what factors that helped or hindered moving project planning forward? Using qualitative methods, 149 national, provincial, and local stakeholders participated in key informant or focus group interviews. We found that planning entails not only intervention and research tasks, but also relational processes that occur within an ecology of time, local context, and values. More specifically, the relationships between the national team and the project sites can be conceptualized as a collaborative process in which national and local partners bring different agendas to the planning process and must therefore listen to, negotiate, discuss, and compromise with one another. A collaborative process that involves power-sharing and having project coordinators at each site helped to bridge the differences between these two stakeholder groups, to find common ground, and to accomplish planning tasks within a compressed time frame. While local context and culture pushed towards unique adaptations of Housing First, the principles of the Housing First model provided a foundation for a common approach across sites and interventions. The implications of the findings for future planning and research of multi-site, complex, community interventions are noted.

  20. Assistive Technology

    MedlinePlus

    ... Page Resize Text Printer Friendly Online Chat Assistive Technology Assistive technology (AT) is any service or tool that helps ... be difficult or impossible. For older adults, such technology may be a walker to improve mobility or ...

  1. Dimension Technologies

    NASA Video Gallery

    Command and Control Technologies (CCT) Corporation of Titusville, Florida, a Florida/NASA Business Incubator tenant, is commercializing technology based on Kennedy Space Center's (KSC's) spacecraft...

  2. Guerilla Technology.

    ERIC Educational Resources Information Center

    Van Horn, Royal

    1999-01-01

    Staff at disadvantaged schools lacking sufficient technology must take matters into their own hands. Guerilla technology tactics include finding all the hidden technology on campus, scanning the school budget carefully, helping others spend their technology money, and scrounging free computers at universities and local businesses. (MLH)

  3. Technology 2020

    ERIC Educational Resources Information Center

    Newby, Mike

    2005-01-01

    This brief article discusses the new technologies that may be available in 2020 that will impact the field of education. The author believes that the new educational themes will be "flexibility" and "autonomy", and the new technological theme will be "transparency". Topics discussed include genetic technology, pharmacological technology, digital…

  4. Technology coordination

    NASA Technical Reports Server (NTRS)

    Hartman, Steven

    1992-01-01

    Viewgraphs on technology coordination are provided. Topics covered include: technology coordination process to date; goals; how the Office of Aeronautics and Space Technology (OAST) can support the Office of Space Science and Applications (OSSA); how OSSA can support OAST; steps to technology transfer; and recommendations.

  5. Twenty Years of Rad-Hard K14 SPAD in Space Projects

    PubMed Central

    Michálek, Vojtěch; Procházka, Ivan; Blažej, Josef

    2015-01-01

    During last two decades, several photon counting detectors have been developed in our laboratory. One of the most promising detector coming from our group silicon K14 Single Photon Avalanche Diode (SPAD) is presented with its valuable features and space applications. Based on the control electronics, it can be operated in both gated and non-gated mode. Although it was designed for photon counting detection, it can be employed for multiphoton detection as well. With respect to control electronics employed, the timing jitter can be as low as 20 ps RMS. Detection efficiency is about 40 % in range of 500 nm to 800 nm. The detector including gating and quenching circuitry has outstanding timing stability. Due to its radiation resistivity, the diode withstands 100 krad gamma ray dose without parameters degradation. Single photon detectors based on K14 SPAD were used for planetary altimeter and atmospheric lidar in MARS92/96 and Mars Surveyor ’98 space projects, respectively. Recent space applications of K14 SPAD comprises LIDAR and mainly time transfer between ground stations and artificial satellites. These include Laser Time Transfer, Time Transfer by Laser Link, and European Laser Timing projects. PMID:26213945

  6. Twenty Years of Rad-Hard K14 SPAD in Space Projects.

    PubMed

    Michálek, Vojtěch; Procházka, Ivan; Blažej, Josef

    2015-01-01

    During last two decades, several photon counting detectors have been developed in our laboratory. One of the most promising detector coming from our group silicon K14 Single Photon Avalanche Diode (SPAD) is presented with its valuable features and space applications. Based on the control electronics, it can be operated in both gated and non-gated mode. Although it was designed for photon counting detection, it can be employed for multiphoton detection as well. With respect to control electronics employed, the timing jitter can be as low as 20 ps RMS. Detection efficiency is about 40%in range of 500 nm to 800 nm. The detector including gating and quenching circuitry has outstanding timing stability. Due to its radiation resistivity, the diode withstands 100 krad gamma ray dose without parameters degradation. Single photon detectors based on K14 SPAD were used for planetary altimeter and atmospheric lidar in MARS92/96 and Mars Surveyor '98 space projects, respectively. Recent space applications of K14 SPAD comprises LIDAR and mainly time transfer between ground stations and artificial satellites. These include Laser Time Transfer, Time Transfer by Laser Link, and European Laser Timing projects.

  7. Being technological

    NASA Astrophysics Data System (ADS)

    Denning, Kathryn

    2011-02-01

    SETI's essential premises involve evolution in multiple domains: cosmology, biology, culture and technology. Comparatively little has been written about the last of these, technology, in relation to SETI's targets, but it is a crucial variable and well worth deep examination. In particular, it would seem prudent to consider carefully our assumptions about hypothetical extraterrestrial societies which have developed technology that SETI could detect, or which could detect, at interstellar distances, the existence of intelligent life on Earth. This paper contributes to that effort by reflecting upon our habits of projecting terracentric assumptions onto hypothetical worlds, exploring dominant narratives about technological development and presenting varied philosophical theories about the nature of technology. It highlights the cultural aspects of technology here on Earth, particularly their role in the development of radio technology. In the end, it is clear that technology need not develop along a prescribed, linear path; projections about extraterrestrial societies which rely on this assumption need to be reconsidered.

  8. Assistive Technologies

    ERIC Educational Resources Information Center

    Auat Cheein, Fernando A., Ed.

    2012-01-01

    This book offers the reader new achievements within the Assistive Technology field made by worldwide experts, covering aspects such as assistive technology focused on teaching and education, mobility, communication and social interactivity, among others. Each chapter included in this book covers one particular aspect of Assistive Technology that…

  9. Technology Night.

    ERIC Educational Resources Information Center

    DuPont, Albert P.

    1998-01-01

    A Maryland elementary school enlightened parents and community members about school technology by hosting a technology night showcasing student work. Through staff and community members' cooperative efforts, the technology committee created a comprehensive program composed of several elements: student involvement, district vision,…

  10. Contemporary Technology.

    ERIC Educational Resources Information Center

    Clark, Gilbert, Ed.

    1999-01-01

    This theme issue of "InSEA News" focuses on contemporary technology and art education. The articles are: "International Travel and Contemporary Technology" (Gilbert Clark); "Recollections and Visions for Electronic Computing in Art Education" (Guy Hubbard); "Using Technologies in Art Education: A Review of Current Issues" (Li-Fen Lu); "Reflections…

  11. Radiation Effects and Hardening Techniques for Spacecraft Microelectronics

    NASA Astrophysics Data System (ADS)

    Gambles, J. W.; Maki, G. K.

    2002-01-01

    The natural radiation from the Van Allen belts, solar flares, and cosmic rays found outside of the protection of the earth's atmosphere can produce deleterious effects on microelectronics used in space systems. Historically civil space agencies and the commercial satellite industry have been able to utilize components produced in special radiation hardened fabrication process foundries that were developed during the 1970s and 1980s under sponsorship of the Departments of Defense (DoD) and Energy (DoE). In the post--cold war world the DoD and DoE push to advance the rad--hard processes has waned. Today the available rad--hard components lag two-plus technology node generations behind state- of-the-art commercial technologies. As a result space craft designers face a large performance gap when trying to utilize available rad--hard components. Compounding the performance gap problems, rad--hard components are becoming increasingly harder to get. Faced with the economic pitfalls associated with low demand versus the ever increasing investment required for integrated circuit manufacturing equipment most sources of rad--hard parts have simply exited this market in recent years, leaving only two domestic US suppliers of digital rad--hard components. This paper summarizes the radiation induced mechanisms that can cause digital microelectronics to fail in space, techniques that can be applied to mitigate these failure mechanisms, and ground based testing used to validate radiation hardness/tolerance. The radiation hardening techniques can be broken down into two classes, Hardness By Process (HBP) and Hardness By Design (HBD). Fortunately many HBD techniques can be applied to commercial fabrication processes providing space craft designer with radiation tolerant Application Specific Integrated Circuits (ASICs) that can bridge the performance gap between the special HBP foundries and the commercial state-of-the-art performance.

  12. Being Technological

    NASA Astrophysics Data System (ADS)

    Denning, Kathryn

    SETI's essential premises involve evolution in multiple domains: cosmology, biology, culture, and technology. Comparatively little has been written about the last of these, technology, in relation to SETI's targets, but it is a crucial variable, and well worth deep examination. In particular, it would seem prudent to consider carefully our assumptions about hypothetical extraterrestrial societies which have developed technology that SETI could detect, or which could detect, at interstellar distances, the existence of intelligent life on Earth. This chapter contributes to that effort by reflecting upon our habits of projecting terracentric assumptions onto hypothetical worlds, exploring dominant narratives about technological development, and presenting varied philosophical theories about the nature of technology. It highlights the cultural aspects of technology here on Earth, particularly their role in the development of radio technology.

  13. Advanced manufacturing of SIMOX for low power electronics

    NASA Astrophysics Data System (ADS)

    Alles, Michael; Krull, Wade

    1996-04-01

    Silicon-on-insulator (SOI) has emerged as a key technology for low power electronics. The merits of SOI technology have been demonstrated, and are gaining acceptance in the semiconductor industry. In order for the SOI approach to be viable, several factors must converge, including the availability of SOI substrates in sufficient quantity, of acceptable quality, and at a competitive price. This work describes developments in SIMOX manufacturing technology and summarizes progress in each of these areas.

  14. Technology '90

    SciTech Connect

    Not Available

    1991-01-01

    The US Department of Energy (DOE) laboratories have a long history of excellence in performing research and development in a number of areas, including the basic sciences, applied-energy technology, and weapons-related technology. Although technology transfer has always been an element of DOE and laboratory activities, it has received increasing emphasis in recent years as US industrial competitiveness has eroded and efforts have increased to better utilize the research and development resources the laboratories provide. This document, Technology '90, is the latest in a series that is intended to communicate some of the many opportunities available for US industry and universities to work with the DOE and its laboratories in the vital activity of improving technology transfer to meet national needs. Technology '90 is divided into three sections: Overview, Technologies, and Laboratories. The Overview section describes the activities and accomplishments of the DOE research and development program offices. The Technologies section provides descriptions of new technologies developed at the DOE laboratories. The Laboratories section presents information on the missions, programs, and facilities of each laboratory, along with a name and telephone number of a technology transfer contact for additional information. Separate papers were prepared for appropriate sections of this report.

  15. III-V/Ge MOS device technologies for low power integrated systems

    NASA Astrophysics Data System (ADS)

    Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

    2016-11-01

    CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

  16. Technology transfer

    NASA Technical Reports Server (NTRS)

    Handley, Thomas

    1992-01-01

    The requirements for a successful technology transfer program and what such a program would look like are discussed. In particular, the issues associated with technology transfer in general, and within the Jet Propulsion Laboratory (JPL) environment specifically are addressed. The section on background sets the stage, identifies the barriers to successful technology transfer, and suggests actions to address the barriers either generally or specifically. The section on technology transfer presents a process with its supporting management plan that is required to ensure a smooth transfer process. Viewgraphs are also included.

  17. Technological Tyranny

    NASA Astrophysics Data System (ADS)

    Greenwood, Dick

    1984-08-01

    It is implicitly assumed by those who create, develop, control and deploy new technology, as well as by society at-large, that technological innovation always represents progress. Such an unchallenged assumption precludes an examination and evaluation of the interrelationships and impact the development and use of technology have on larger public policy matters, such as preservation of democratic values, national security and military policies, employment, income and tax policies, foreign policy and the accountability of private corporate entities to society. This brief challenges those assumptions and calls for social control of technology.

  18. Polysomnographic Technology

    MedlinePlus

    ... ACCREDITATION MENTOR | TAKE THE SITE VISITOR QUIZ Polysomnographic Technology Occupational Description Polysomnographic technologists perform sleep tests and work with physicians to provide information needed ...

  19. Thermally activated technologies: Technology Roadmap

    SciTech Connect

    None, None

    2003-05-01

    The purpose of this Technology Roadmap is to outline a set of actions for government and industry to develop thermally activated technologies for converting America’s wasted heat resources into a reservoir of pollution-free energy for electric power, heating, cooling, refrigeration, and humidity control. Fuel flexibility is important. The actions also cover thermally activated technologies that use fossil fuels, biomass, and ultimately hydrogen, along with waste heat.

  20. Plastics Technology.

    ERIC Educational Resources Information Center

    Barker, Tommy G.

    This curriculum guide is designed to assist junior high schools industrial arts teachers in planning new courses and revising existing courses in plastics technology. Addressed in the individual units of the guide are the following topics: introduction to production technology; history and development of plastics; safety; youth leadership,…

  1. Technological Advancements

    ERIC Educational Resources Information Center

    Kennedy, Mike

    2010-01-01

    The influx of technology has brought significant improvements to school facilities. Many of those advancements can be found in classrooms, but when students head down the hall to use the washrooms, they are likely to find a host of technological innovations that have improved conditions in that part of the building. This article describes modern…

  2. Technology Tips

    ERIC Educational Resources Information Center

    Santos-Trigo, Manuel

    2004-01-01

    A dynamic program for geometry called Cabri Geometry II is used to examine properties of figures like triangles and make connections with other mathematical ideas like ellipse. The technology tip includes directions for creating such a problem with technology and suggestions for exploring it.

  3. Technology Integration

    ERIC Educational Resources Information Center

    T.H.E. Journal, 2004

    2004-01-01

    The use of instructional technology has evolved over the last two decades, initially, instructional technology had two uses: learning about computers and using computers to increase basic skills. Learning about computers morphed into computer literacy, which is typically defined as the history, terminology and background of computing, using…

  4. Use Technology

    ERIC Educational Resources Information Center

    Teo, Timothy

    2013-01-01

    Technology acceptance is posited to be influenced by a variety of factors, including individual differences, social influences, beliefs, attitudes and situational influences (Agarwal, 2000; Teo, 2009a). A majority of the conceptualisations of technology acceptance have drawn on theories and models from social psychology, notably the theory of…

  5. Modern Technology

    ERIC Educational Resources Information Center

    Smyth, Michael P.

    1971-01-01

    Describes a PMC college course which is an introduction to technology and its impact upon society for non-scientists. Case studies of computer technology, pollution, communications, and other systems are used to bring into perspective the roles and responsibilities of the engineer and scientist in today's society. (Author/TS)

  6. Technology Transformation

    ERIC Educational Resources Information Center

    Scott, Heather; McGilll, Toria

    2011-01-01

    Social networking and other technologies, if used judiciously, present the means to integrate 21st century skills into the classroom curriculum. But they also introduce challenges that educators must overcome. Increased concerns about plagiarism and access to technology can test educators' creativity and school resources. Air Academy High School,…

  7. Woodworking Technology.

    ERIC Educational Resources Information Center

    Kirk, Albert S.; And Others

    1991-01-01

    Three articles discuss the importance of wood processing to manufacturing and construction industries and the need for progressive change in the curriculum; the evolution of wood-based synthetic panel materials; and the technological advances in the computer control of machine tools and their incorporation into wood technology curricula. (JOW)

  8. Videodisc Technology.

    ERIC Educational Resources Information Center

    Ullmer, Eldon J.

    Developed as a service to the health sciences community, this monograph is intended as an introduction to interactive videodisk technology. It describes both videodisk and compact disk technologies and different videodisk player formats, and discusses some of the major factors that educators considering videodisk adoption should consider. The…

  9. Information Technology.

    ERIC Educational Resources Information Center

    Reynolds, Roger

    1983-01-01

    Describes important information-handling products, predicting future devices in light of convergence and greater flexibility offered through use of microchip technology. Contends that information technology and its impact of privacy depends on how information systems are used, arguing that the privacy issue deals more with moral/physiological…

  10. Technology Push

    ERIC Educational Resources Information Center

    Kennedy, Mike

    2008-01-01

    When students, teachers, administrators and others employed in education arrive at work every day on thousands of campuses across the nation, it should come as no surprise that at every step along the way, technology is there to greet them. Technological advancements in education, as well as in facilities operation and management, are not a…

  11. Recycling Technology.

    ERIC Educational Resources Information Center

    Aviation/Space, 1982

    1982-01-01

    In a comprehensive nationwide effort, National Aeronautics and Space Administration (NASA) seeks to increase public and private sector benefits by broadening and accelerating the secondary application of aerospace technology. Discussed are NASA's Applications Centers, publications, technology applications, and Computer Software Management and…

  12. Heterogeneous integration technology for hybrid optoelectronic and electronic device and module fabrication

    NASA Astrophysics Data System (ADS)

    Jin, Michael Sungchun

    Various forms of optical computing architectures have promised enhanced processing capabilities well beyond the limits of traditional VLSI technology during the past decade. However, the progress toward realizing this vision has been severely limited by the lack of mature technology to fabricate heterogeneously integrated optoelectronic transceiver arrays (consisting of VLSI electronics with optoelectronic devices) that are necessary to link the functionality of photonic input/output devices with electronic processors. This dissertation describes a research effort that addressed this need by exploring innovative, yet highly manufacturable integration approaches that can be utilized to fabricate hybrid optoelectronic transceivers by integrating thin silicon device layers on bulk electro-optic (e.g. lead lanthanum zirconate titanate- PLZT) and other host substrates. The two integration techniques developed are: (1) B& P (Bond and Processing) technology involving bonding of bulk-quality thin silicon layer to PLZT followed by low temperature NMOS processing and (2) DDB (Direct-Device Bonding) technology, where circuit layer fabricated in SOI-silicon is thinned and bonded directly to a PLZT substrate. Characteristics of electronic circuits and modulators in integrated Si/PLZT SLMs are measured to be comparable to that of reference devices fabricated in bulk silicon and PLZT substrates. The application of the developed integration technology specifically toward fabricating Si/PLZT spatial light modulator is examined in detail. The developed device layer grafting technology based on chemo-mechanical lapping and reactive ion etching processes can be applied to assemble miniature ``mixed technology'' systems consisting of devices fabricated by different manufacturing processes (e.g. CMOS, MEMS, VCSEL and GaAs processes) in a monolithic fashion. The latter half of the thesis details experimental

  13. Ergonomics technology

    NASA Technical Reports Server (NTRS)

    Jones, W. L.

    1977-01-01

    Major areas of research and development in ergonomics technology for space environments are discussed. Attention is given to possible applications of the technology developed by NASA in industrial settings. A group of mass spectrometers for gas analysis capable of fully automatic operation has been developed for atmosphere control on spacecraft; a version for industrial use has been constructed. Advances have been made in personal cooling technology, remote monitoring of medical information, and aerosol particle control. Experience gained by NASA during the design and development of portable life support units has recently been applied to improve breathing equipment used by fire fighters.

  14. Technology development.

    PubMed

    Gomory, R E

    1983-05-01

    In technology development significant advances are as often the result of a series of evolutionary steps as they are of breakthroughs. This is illustrated by the examples of the steam engine and the computer. Breakthroughs, such as the transistor, are relatively rare, and are often the result of the introduction of new knowledge coming from a quite different area. Technology development is often difficult to predict because of its complexity; practical considerations may far outweigh apparent scientific advantages, and cultural factors enter in at many levels. In a large technological organization problems exist in bringing scientific knowledge to bear on development, but much can be done to obviate these difficulties. PMID:17749515

  15. Technology development.

    PubMed

    Gomory, R E

    1983-05-01

    In technology development significant advances are as often the result of a series of evolutionary steps as they are of breakthroughs. This is illustrated by the examples of the steam engine and the computer. Breakthroughs, such as the transistor, are relatively rare, and are often the result of the introduction of new knowledge coming from a quite different area. Technology development is often difficult to predict because of its complexity; practical considerations may far outweigh apparent scientific advantages, and cultural factors enter in at many levels. In a large technological organization problems exist in bringing scientific knowledge to bear on development, but much can be done to obviate these difficulties.

  16. Electrosynthesis Technology.

    ERIC Educational Resources Information Center

    Weinberg, Norman L.

    1983-01-01

    Provides a prospective on electrosynthesis technology for chemical educators and students by discussing electrosynthesis reactions and experiments. Includes tables illustrating some electrochemical products, variables to consider in electrochemical reactions, indirect electrolysis of organic compounds, examples of direct/indirect electrochemical…

  17. Banana technology

    NASA Astrophysics Data System (ADS)

    van Amstel, Willem D.; Schellekens, E. P. A.; Walravens, C.; Wijlaars, A. P. F.

    1999-09-01

    With 'Banana Technology' an unconventional hybrid fabrication technology is indicated for the production of very large parabolic and hyperbolic cylindrical mirror systems. The banana technology uses elastic bending of very large and thin glass substrates and fixation onto NC milled metal moulds. This technology has matured during the last twenty years for the manufacturing of large telecentric flat-bed scanners. Two construction types, called 'internal banana' and 'external banana; are presented. Optical figure quality requirements in terms of slope and curvature deviations are discussed. Measurements of these optical specifications by means of a 'finishing rod' type of scanning deflectometer or slope tester are presented. Design constraints for bending glass and the advantages of a new process will be discussed.

  18. Videodisc technology

    SciTech Connect

    Marsh, F.E. Jr.

    1981-03-01

    An overview of the technology of videodiscs is given. The emphasis is on systems that use reflection or transmission of laser light. Possible use of videodiscs for storage of bibliographic information is considered. 6 figures, 3 tables. (RWR)

  19. Radiator technology

    NASA Technical Reports Server (NTRS)

    Juhasz, Albert J.

    1993-01-01

    Radiator technology is discussed in the context of the Civilian Space Technology Initiative's (CSTI's) high capacity power-thermal management project. The CSTI project is a subset of a project to develop a piloted Mars nuclear electric propulsion (NEP) vehicle. The following topics are presented in vugraph form: advanced radiator concepts; heat pipe codes and testing; composite materials; radiator design and integration; and surface morphology.

  20. Technology Report

    NASA Technical Reports Server (NTRS)

    Repucci, George

    1996-01-01

    This is the fourth report of a series of semi-annual reports that describe the technology areas being advanced under this contract and the progress achieved to date. The most significant technical event this period was the successful completion of the Lewis spacecraft in 2 years (contract award date was June 1994). In August of 1996 we held a program-wide Technology Workshop which covered all aspects of the Lewis payload. A copy of the Workshop proceedings is attached.

  1. Aerocapture Technologies

    NASA Technical Reports Server (NTRS)

    Keys, Andrew S.

    2006-01-01

    Aeroassist technology development is a vital part of the NASA In-Space Propulsion Technology (ISPT) Program. One of the main focus areas of ISPT is aeroassist technologies through the Aerocapture Technology (AT) Activity. Within the ISPT, the current aeroassist technology development focus is aerocapture. Aerocapture relies on the exchange of momentum with an atmosphere to achieve thrust, in this case a decelerating thrust leading to orbit capture. Without aerocapture, a substantial propulsion system would be needed on the spacecraft to perform the same reduction of velocity. This could cause reductions in the science payload delivered to the destination, increases in the size of the launch vehicle (to carry the additional fuel required for planetary capture) or could simply make the mission impossible due to additional propulsion requirements. The AT is advancing each technology needed for the successful implementation of aerocapture in future missions. The technology development focuses on both rigid aeroshell systems as well as the development of inflatable aerocapture systems, advanced aeroshell performance sensors, lightweight structure and higher temperature adhesives. Inflatable systems such as tethered trailing ballutes ('balloon parachutes'), clamped ballutes, and inflatable aeroshells are also under development. Aerocapture-specific computational tools required to support future aerocapture missions are also an integral part of the ATP. Tools include: engineering reference atmosphere models, guidance and navigation, aerothermodynamic modeling, radiation modeling and flight simulation. Systems analysis plays a key role in the AT development process. The NASA in-house aerocapture systems analysis team has been taken with multiple systems definition and concept studies to complement the technology development tasks. The team derives science requirements, develops guidance and navigation algorithms, as well as engineering reference atmosphere models and

  2. Fabrication Technology

    SciTech Connect

    Blaedel, K.L.

    1993-03-01

    The mission of the Fabrication Technology thrust area is to have an adequate base of manufacturing technology, not necessarily resident at Lawrence Livermore National Laboratory (LLNL), to conduct the future business of LLNL. The specific goals continue to be to (1) develop an understanding of fundamental fabrication processes; (2) construct general purpose process models that will have wide applicability; (3) document findings and models in journals; (4) transfer technology to LLNL programs, industry, and colleagues; and (5) develop continuing relationships with the industrial and academic communities to advance the collective understanding of fabrication processes. The strategy to ensure success is changing. For technologies in which they are expert and which will continue to be of future importance to LLNL, they can often attract outside resources both to maintain their expertise by applying it to a specific problem and to help fund further development. A popular vehicle to fund such work is the Cooperative Research and Development Agreement with industry. For technologies needing development because of their future critical importance and in which they are not expert, they use internal funding sources. These latter are the topics of the thrust area. Three FY-92 funded projects are discussed in this section. Each project clearly moves the Fabrication Technology thrust area towards the goals outlined above. They have also continued their membership in the North Carolina State University Precision Engineering Center, a multidisciplinary research and graduate program established to provide the new technologies needed by high-technology institutions in the US. As members, they have access to and use of the results of their research projects, many of which parallel the precision engineering efforts at LLNL.

  3. Emerging technologies

    SciTech Connect

    Hodson, C.O.; Williams, D.

    1996-07-01

    Among the emerging technologies for air, hazardous waste and water come new ways of looking at pollution, in both the figurative and quite literal sense. The use of microbes for remediation and pollution control is a component in many of the technologies in this report and is the focus of environmental research at many university and industry labs. Bacteria are the engines driving one featured emissions control technology: the air biofilter. Biofilters are probably more acceptable to most engineers as a soil remediation technology--such as the innovative method described in the hazardous waste section--rather than as means of cleaning off-gases, but in many cases bugs can perform the function inexpensively. The authors give the basics on this available technology. A more experimental application of microbes is being investigated as a potential quantum leap in heavy metals removal technology: bio-engineered, metal consuming plants. The effort to genetically engineer a green remediation tool is detailed in the hazardous waste section.

  4. Spontaneous parametric fluorescence in SOI integrated micoresonators

    NASA Astrophysics Data System (ADS)

    Azzini, Stefano; Grassani, Davide; Liscidini, Marco; Galli, Matteo; Gerace, Dario; Sorel, Marc; Strain, Michael J.; Velha, Philippe; Bajoni, Daniele

    2013-10-01

    Four-wave mixing can be stimulated or occur spontaneously: the latter effect, also known as parametric fluorescence, can be explained only in the framework of a quantum theory of light, and it is at the basis of many protocols to generate nonclassical states of the electromagnetic field. In this work we report on our experimental study of spontaneous four wave mixing in microring resonators and photonic crystal molecules integrated on a silicon on insulator platform. We find that both structures are able to generate signal and idler beams in the telecom band, at rates of millions of photons per second, under sub-mW pumping. By comparing the experiments on the two structures we find that the photonic molecule is an order of magnitude more efficient than the ring resonator, due to the reduced mode volume of the individual resonators.

  5. Pixel frontend electronics in a radiation hard technology for hybrid and monolithic applications

    SciTech Connect

    Pengg, F. |; Campbell, M.; Heijne, E.H.M.; Snoeys, W.

    1996-06-01

    Pixel detector readout cells have been designed in the radiation hard DMILL technology and their characteristics evaluated before and after irradiation to 14Mrad. The test chip consists of two blocks of six readout cells each. Two different charge amplifiers are implemented, one of them using a capacitive feedback loop, the other the fast signal charge transfer to a high impedance integrating node. The measured equivalent noise charge is 110e{sup {minus}}r.m.s. before and 150e{sup {minus}}r.m.s. after irradiation. With a discriminator threshold set to 5000e{sup {minus}}, which reduces for the same bias setting to 400e{sup {minus}} after irradiation, the threshold variation is 300e{sup {minus}}r.m.s. and 250e{sup {minus}}r.m.s. respectively. The time walk is 40ns before and after irradiation. The use of this SOI technology for monolithic integration of electronics and detector in one substrate is under investigation.

  6. Diabetes Technology.

    PubMed

    Pfützner, Andreas

    2016-01-01

    Diabetes technology is an evolving field. The research started with the development of blood glucose meters for patient self-testing and the introduction of insulin pen injection devices. Modern devices employ new technological features, such as the use of computer simulations and mathematical algorithms, connectivity and signal transfer, and the use of modern (space research-derived) materials. With these innovations, the goal to develop an artificial pancreas by closing the loop between a continuous glucose sensor and a continuous insulin-delivering device via insulin delivery algorithms is coming closer to reality. As a consequence, interim achievements on this way result in the commercialization of innovative new diabetes technology devices, which help to facilitate the daily life of the affected people with diabetes. PMID:26824436

  7. Technology Transfer

    NASA Technical Reports Server (NTRS)

    Smith, Nanette R.

    1995-01-01

    The objective of this summer's work was to attempt to enhance Technology Application Group (TAG) ability to measure the outcomes of its efforts to transfer NASA technology. By reviewing existing literature, by explaining the economic principles involved in evaluating the economic impact of technology transfer, and by investigating the LaRC processes our William & Mary team has been able to lead this important discussion. In reviewing the existing literature, we identified many of the metrics that are currently being used in the area of technology transfer. Learning about the LaRC technology transfer processes and the metrics currently used to track the transfer process enabled us to compare other R&D facilities to LaRC. We discuss and diagram impacts of technology transfer in the short run and the long run. Significantly, it serves as the basis for analysis and provides guidance in thinking about what the measurement objectives ought to be. By focusing on the SBIR Program, valuable information regarding the strengths and weaknesses of this LaRC program are to be gained. A survey was developed to ask probing questions regarding SBIR contractors' experience with the program. Specifically we are interested in finding out whether the SBIR Program is accomplishing its mission, if the SBIR companies are providing the needed innovations specified by NASA and to what extent those innovations have led to commercial success. We also developed a survey to ask COTR's, who are NASA employees acting as technical advisors to the SBIR contractors, the same type of questions, evaluating the successes and problems with the SBIR Program as they see it. This survey was developed to be implemented interactively on computer. It is our hope that the statistical and econometric studies that can be done on the data collected from all of these sources will provide insight regarding the direction to take in developing systematic evaluations of programs like the SBIR Program so that they can

  8. Manufacturing technology

    SciTech Connect

    Blaedel, K.L.

    1997-02-01

    The specific goals of the Manufacturing Technology thrust area are to develop an understanding of fundamental fabrication processes, to construct general purpose process models that will have wide applicability, to document our findings and models in journals, to transfer technology to LLNL programs, industry, and colleagues, and to develop continuing relationships with industrial and academic communities to advance our collective understanding of fabrication processes. Advances in four projects are described here, namely Design of a Precision Saw for Manufacturing, Deposition of Boron Nitride Films via PVD, Manufacturing and Coating by Kinetic Energy Metallization, and Magnet Design and Application.

  9. Mirror Technology

    NASA Technical Reports Server (NTRS)

    1992-01-01

    Under a NASA contract, MI-CVD developed a process for producing bulk silicon carbide by means of a chemical vapor deposition process. The technology allows growth of a high purity material with superior mechanical/thermal properties and high polishability - ideal for mirror applications. The company employed the technology to develop three research mirrors for NASA Langley and is now marketing it as CVD SILICON CARBIDE. Its advantages include light weight, thermal stability and high reflectivity. The material has nuclear research facility applications and is of interest to industrial users of high power lasers.

  10. Technology Benefits

    NASA Technical Reports Server (NTRS)

    Haller, William

    2001-01-01

    An assessment was recently performed by NASA s Inter-Center Systems Analysis Team to quantify the potential emission reduction benefits from technologies being developed under UEET. The CO2 and LTO NO, reductions were estimated for 4 vehicles: a 50-passenger regional jet, a twin-engine, long-range subsonic transport, a high-speed (Mach 2.4) civil transport and a supersonic (Mach 2) business jet. The results of the assessment confirm that the current portfolio of technologies within the UEET program provides an opportunity for substantial reductions in CO2 and NO, emissions.

  11. Manufacturing technologies

    NASA Astrophysics Data System (ADS)

    The Manufacturing Technologies Center is at the core of Sandia National Laboratories' advanced manufacturing effort which spans the entire product realization process. The center's capabilities in product and process development are summarized in the following disciplines: (1) mechanical - rapid prototyping, manufacturing engineering, machining and computer-aided manufacturing, measurement and calibration, and mechanical and electronic manufacturing liaison; (2) electronics - advanced packaging for microelectronics, printed circuits, and electronic fabrication; and (3) materials - ceramics, glass, thin films, vacuum technology, brazing, polymers, adhesives, composite materials, and process analysis.

  12. Technology Transfer: Marketing Tomorrow's Technology

    NASA Technical Reports Server (NTRS)

    Tcheng, Erene

    1995-01-01

    The globalization of the economy and the end of the Cold War have triggered many changes in the traditional practices of U.S. industry. To effectively apply the resources available to the United States, the federal government has firmly advocated a policy of technology transfer between private industry and government labs, in this case the National Aeronautics and Space Administration (NASA). NASA Administrator Daniel Goldin is a strong proponent of this policy and has organized technology transfer or commercialization programs at each of the NASA field centers. Here at Langley Research Center, the Technology Applications Group (TAG) is responsible for facilitating the transfer of Langley developed research and technology to U.S. industry. Entering the program, I had many objectives for my summer research with TAG. Certainly, I wanted to gain a more thorough understanding of the concept of technology transfer and Langley's implementation of a system to promote it to both the Langley community and the community at large. Also, I hoped to become more familiar with Langley's research capabilities and technology inventory available to the public. More specifically, I wanted to learn about the technology transfer process at Langley. Because my mentor is a member of Materials and Manufacturing marketing sector of the Technology Transfer Team, another overriding objective for my research was to take advantage of his work and experience in materials research to learn about the Advanced Materials Research agency wide and help market these developments to private industry. Through the various projects I have been assigned to work on in TAG, I have successfully satisfied the majority of these objectives. Work on the Problem Statement Process for TAG as well as the development of the Advanced Materials Research Brochure have provided me with the opportunity to learn about the technology transfer process from the outside looking in and the inside looking out. Because TAG covers

  13. SUPERFUND INNOVATIVE TECHNOLOGY EVALUATION - TECHNOLOGY PROFILES

    EPA Science Inventory

    This document is intended as a reference guide for EPA Regional decision makers and others interested in technologies in the SITE Demonstration and Emerging Technologies programs. The Technologies are described in technology profiles, presented in alphabetical order by developer ...

  14. Videodisc Technology.

    ERIC Educational Resources Information Center

    Marsh, Fred E., Jr.

    1982-01-01

    Identifies and describes the major areas of videodisc technology; discusses the operation, reliability, storage capacities, and applications of two types of laser systems; and illustrates the versatility of the optical digital disc through a description of its ability to digitize large bodies of data. Included are six figures and three tables.…

  15. Technology Theme.

    ERIC Educational Resources Information Center

    Garrahy, Dennis J.

    One of a series of social studies units designed to develop the reading and writing skills of low achievers, this student activity book focuses on the theme of technology. The unit can be used for high school classes, individual study in alternative and continuing high schools, and adult education classes. Material is divided into four sections.…

  16. Manufacturing technologies

    SciTech Connect

    1995-09-01

    The Manufacturing Technologies Center is an integral part of Sandia National Laboratories, a multiprogram engineering and science laboratory, operated for the Department of Energy (DOE) with major facilities at Albuquerque, New Mexico, and Livermore, California. Our Center is at the core of Sandia`s Advanced Manufacturing effort which spans the entire product realization process.

  17. Information Technology.

    ERIC Educational Resources Information Center

    Marcum, Deanna; Boss, Richard

    1982-01-01

    Discusses a problem commonly encountered in library automation projects: the conversion from existing card catalog formats to machine readable catalog (MARC) records. Catalog formats, the advantages of full versus limited records, changing computer technology, the advantages of full MARC records, and record standardization are among the topics…

  18. Measurement Technology

    NASA Technical Reports Server (NTRS)

    1972-01-01

    New and improved materials, equipment, and techniques in measurement technology, developed by the aerospace industry, are presented for economic development in other industries. The developments are grouped as follows: (1) surface measurement, (2) alignment and orientation of bodies, (3) fluid measurement, (4) linear and angular measurements, and (5) force measurements.

  19. (Environmental technology)

    SciTech Connect

    Boston, H.L.

    1990-10-12

    The traveler participated in a conference on environmental technology in Paris, sponsored by the US Embassy-Paris, US Environmental Protection Agency (EPA), the French Environmental Ministry, and others. The traveler sat on a panel for environmental aspects of energy technology and made a presentation on the potential contributions of Oak Ridge National Laboratory (ORNL) to a planned French-American Environmental Technologies Institute in Chattanooga, Tennessee, and Evry, France. This institute would provide opportunities for international cooperation on environmental issues and technology transfer related to environmental protection, monitoring, and restoration at US Department of Energy (DOE) facilities. The traveler also attended the Fourth International Conference on Environmental Contamination in Barcelona. Conference topics included environmental chemistry, land disposal of wastes, treatment of toxic wastes, micropollutants, trace organics, artificial radionuclides in the environment, and the use biomonitoring and biosystems for environmental assessment. The traveler presented a paper on The Fate of Radionuclides in Sewage Sludge Applied to Land.'' Those findings corresponded well with results from studies addressing the fate of fallout radionuclides from the Chernobyl nuclear accident. There was an exchange of new information on a number of topics of interest to DOE waste management and environmental restoration needs.

  20. Technology Transfer

    NASA Technical Reports Server (NTRS)

    Bullock, Kimberly R.

    1995-01-01

    The development and application of new technologies in the United States has always been important to the economic well being of the country. The National Aeronautics and Space Administration (NASA) has been an important source of these new technologies for almost four decades. Recently, increasing global competition has emphasized the importance of fully utilizing federally funded technologies. Today NASA must meet its mission goals while at the same time, conduct research and development that contributes to securing US economic growth. NASA technologies must be quickly and effectively transferred into commercial products. In order to accomplish this task, NASA has formulated a new way of doing business with the private sector. Emphasis is placed on forming mutually beneficial partnerships between NASA and US industry. New standards have been set in response to the process that increase effectiveness, efficiency, and timely customer response. This summer I have identified potential markets for two NASA inventions: including the Radially Focused Eddy Current Sensor for Characterization of Flaws in Metallic Tubing and the Radiographic Moire. I have also worked to establish a cooperative program with TAG, private industry, and a university known as the TAG/Industry/Academia Program.

  1. Energy Technology.

    ERIC Educational Resources Information Center

    Eaton, William W.

    Reviewed are technological problems faced in energy production including locating, recovering, developing, storing, and distributing energy in clean, convenient, economical, and environmentally satisfactory manners. The energy resources of coal, oil, natural gas, hydroelectric power, nuclear energy, solar energy, geothermal energy, winds, tides,…

  2. Manufacturing Technology.

    ERIC Educational Resources Information Center

    Barnes, James L.

    This curriculum guide is designed to assist junior high school industrial arts teachers in planning new courses and revising existing courses in manufacturing technology. Addressed in the individual units of the guide are the following topics: introduction to manufacturing, materials processing, personnel management, production management,…

  3. Geospatial Technology

    ERIC Educational Resources Information Center

    Reed, Philip A.; Ritz, John

    2004-01-01

    Geospatial technology refers to a system that is used to acquire, store, analyze, and output data in two or three dimensions. This data is referenced to the earth by some type of coordinate system, such as a map projection. Geospatial systems include thematic mapping, the Global Positioning System (GPS), remote sensing (RS), telemetry, and…

  4. Technology Tools

    ERIC Educational Resources Information Center

    Kennedy, Mike

    2005-01-01

    Personal computers (PCs) have transformed the way teachers teach, students learn, and school operations are conducted. However, the addition of PCs is not the only technological advancement that can help education institutions run more productively. The progress that has made computers smaller, faster and cheaper also has led to the availability…

  5. Vacuum Technology

    SciTech Connect

    Biltoft, P J

    2004-10-15

    The environmental condition called vacuum is created any time the pressure of a gas is reduced compared to atmospheric pressure. On earth we typically create a vacuum by connecting a pump capable of moving gas to a relatively leak free vessel. Through operation of the gas pump the number of gas molecules per unit volume is decreased within the vessel. As soon as one creates a vacuum natural forces (in this case entropy) work to restore equilibrium pressure; the practical effect of this is that gas molecules attempt to enter the evacuated space by any means possible. It is useful to think of vacuum in terms of a gas at a pressure below atmospheric pressure. In even the best vacuum vessels ever created there are approximately 3,500,000 molecules of gas per cubic meter of volume remaining inside the vessel. The lowest pressure environment known is in interstellar space where there are approximately four molecules of gas per cubic meter. Researchers are currently developing vacuum technology components (pumps, gauges, valves, etc.) using micro electro mechanical systems (MEMS) technology. Miniature vacuum components and systems will open the possibility for significant savings in energy cost and will open the doors to advances in electronics, manufacturing and semiconductor fabrication. In conclusion, an understanding of the basic principles of vacuum technology as presented in this summary is essential for the successful execution of all projects that involve vacuum technology. Using the principles described above, a practitioner of vacuum technology can design a vacuum system that will achieve the project requirements.

  6. Technological Networks

    NASA Astrophysics Data System (ADS)

    Mitra, Bivas

    The study of networks in the form of mathematical graph theory is one of the fundamental pillars of discrete mathematics. However, recent years have witnessed a substantial new movement in network research. The focus of the research is shifting away from the analysis of small graphs and the properties of individual vertices or edges to consideration of statistical properties of large scale networks. This new approach has been driven largely by the availability of technological networks like the Internet [12], World Wide Web network [2], etc. that allow us to gather and analyze data on a scale far larger than previously possible. At the same time, technological networks have evolved as a socio-technological system, as the concepts of social systems that are based on self-organization theory have become unified in technological networks [13]. In today’s society, we have a simple and universal access to great amounts of information and services. These information services are based upon the infrastructure of the Internet and the World Wide Web. The Internet is the system composed of ‘computers’ connected by cables or some other form of physical connections. Over this physical network, it is possible to exchange e-mails, transfer files, etc. On the other hand, the World Wide Web (commonly shortened to the Web) is a system of interlinked hypertext documents accessed via the Internet where nodes represent web pages and links represent hyperlinks between the pages. Peer-to-peer (P2P) networks [26] also have recently become a popular medium through which huge amounts of data can be shared. P2P file sharing systems, where files are searched and downloaded among peers without the help of central servers, have emerged as a major component of Internet traffic. An important advantage in P2P networks is that all clients provide resources, including bandwidth, storage space, and computing power. In this chapter, we discuss these technological networks in detail. The review

  7. Technology utilization. [aerospace technology transfer

    NASA Technical Reports Server (NTRS)

    Kubokawa, C. C.

    1978-01-01

    NASA developed technologies were used to tackle problems associated with safety, transportation, industry, manufacturing, construction and state and local governments. Aerospace programs were responsible for more innovations for the benefit of mankind than those brought about by either major wars, or peacetime programs. Briefly outlined are some innovations for manned space flight, satellite surveillance applications, and pollution monitoring techniques.

  8. Technology: Technology and Common Sense

    ERIC Educational Resources Information Center

    Van Horn, Royal

    2004-01-01

    The absence of common sense in the world of technology continues to amaze the author. Things that seem so logical to just aren nott for many people. The installation of Voice-over IP (VoIP, with IP standing for Internet Protocol) in many school districts is a good example. Schools have always had trouble with telephones. Many districts don't even…

  9. Innovative Technology in Automotive Technology

    ERIC Educational Resources Information Center

    Gardner, John

    2007-01-01

    Automotive Technology combines hands-on training along with a fully integrated, interactive, computerized multistationed facility. Our program is a competency based, true open-entry/open-exit program that utilizes flexible self-paced course outlines. It is designed around an industry partnership that promotes community and economic development,…

  10. Communications technology

    NASA Technical Reports Server (NTRS)

    Cuccia, C. Louis; Sivo, Joseph

    1986-01-01

    The technologies for optimized, i.e., state of the art, operation of satellite-based communications systems are surveyed. Features of spaceborne active repeater systems, low-noise signal amplifiers, power amplifiers, and high frequency switches are described. Design features and capabilities of various satellite antenna systems are discussed, including multiple beam, shaped reflector shaped beam, offset reflector multiple beam, and mm-wave and laser antenna systems. Attitude control systems used with the antenna systems are explored, along with multiplexers, filters, and power generation, conditioning and amplification systems. The operational significance and techniques for exploiting channel bandwidth, baseband and modulation technologies are described. Finally, interconnectivity among communications satellites by means of RF and laser links is examined, as are the roles to be played by the Space Station and future large space antenna systems.

  11. Manufacturing technology

    SciTech Connect

    Leonard, J.A.; Floyd, H.L.; Goetsch, B.; Doran, L.

    1993-08-01

    This bulletin depicts current research on manufacturing technology at Sandia laboratories. An automated, adaptive process removes grit overspray from jet engine turbine blades. Advanced electronic ceramics are chemically prepared from solution for use in high- voltage varistors. Selective laser sintering automates wax casting pattern fabrication. Numerical modeling improves performance of photoresist stripper (simulation on Cray supercomputer reveals path to uniform plasma). And mathematical models help make dream of low- cost ceramic composites come true.

  12. AEDOT technology

    SciTech Connect

    Shankle, D.L.

    1993-03-01

    Most commercial buildings designed today will use more energy and cost more to operate and maintain than necessary. If energy performance were considered early in building design, 30% to 60% of the energy now used in new commercial buildings could be saved cost-effectively. However, most building design teams do not adequately consider the energy impacts of design decisions to achieve these savings; the tools for doing so simply do not yet exist. Computer technology can help design teams consider energy performance as an integral part of the design process. This technology could enable designers to produce much more energy-efficient buildings without increasing the costs of building design. Recognizing this, the US Department of Energy (DOE) has initiated the Advanced Energy Design and Operation Technologies (AEDOT) project, led by Pacific Northwest Laboratory (PNL). The aim of the project is to develop advanced computer-based technologies that will help designers take advantage of these potentially large energy savings. The success of the AEDOT project depends largely on the ability to develop energy design-support tools that can be integrated into comprehensive building design environments so that all parts of the design process willbe supported. Energy, just one consideration among many in building design, must be considered in a context that includes visual, acoustic, and structural aspects; accessibility; thermal comfort; indoor air quality; cost; and other factors associated with the quality, acceptability, and performance of a building. Advanced computer-aided design support environments will need to integrate tools from many different domains and provide access to the vast amounts of data that designers need to apply these tools and to make informed decisions.

  13. Communications technology

    NASA Technical Reports Server (NTRS)

    Sokoloski, Martin M.

    1988-01-01

    The objective of the Communications Technology Program is to enable data transmission to and from low Earth orbit, geostationary orbit, and solar and deep space missions. This can be achieved by maintaining an effective, balances effort in basic, applied, and demonstration prototype communications technology through work in theory, experimentation, and components. The program consists of three major research and development discipline areas which are: microwave and millimeter wave tube components; solid state monolithic integrated circuit; and free space laser communications components and devices. The research ranges from basic research in surface physics (to study the mechanisms of surface degradation from under high temperature and voltage operating conditions which impacts cathode tube reliability and lifetime) to generic research on the dynamics of electron beams and circuits (for exploitation in various micro- and millimeter wave tube devices). Work is also performed on advanced III-V semiconductor materials and devices for use in monolithic integrated analog circuits (used in adaptive, programmable phased arrays for microwave antenna feeds and receivers) - on the use of electromagnetic theory in antennas and on technology necessary for eventual employment of lasers for free space communications for future low earth, geostationary, and deep space missions requiring high data rates with corresponding directivity and reliability.

  14. Technology disrupted

    SciTech Connect

    Papatheodorou, Y.

    2007-02-15

    Three years ago, the author presented a report on power generation technologies which in summary said 'no technology available today has the potential of becoming transformational or disruptive in the next five to ten years'. In 2006 the company completed another strategic view research report covering the electric power, oil, gas and unconventional energy industries and manufacturing industry. This article summarises the strategic view findings and then revisits some of the scenarios presented in 2003. The cost per megawatt-hour of the alternatives is given for plants ordered in 2005 and then in 2025. The issue of greenhouse gas regulation is dealt with through carbon sequestration and carbon allowances or an equivalent carbon tax. Results reveal substantial variability through nuclear power, hydro, wind, geothermal and biomass remain competitive through every scenario. Greenhouse gas scenario analysis shows coal still be viable, albeit less competitive against nuclear and renewable technologies. A carbon tax or allowance at $24 per metric ton has the same effect on IGCC cost as a sequestration mandate. However, the latter would hurt gas plants much more than a tax or allowance. Sequestering CO{sub 2} from a gas plant is almost as costly per megawatt-hour as for coal. 5 refs., 5 figs., 5 tabs.

  15. Emerging technologies

    SciTech Connect

    Lu, Shin-yee

    1993-03-01

    The mission of the Emerging Technologies thrust area at Lawrence Livermore National Laboratory is to help individuals establish technology areas that have national and commercial impact, and are outside the scope of the existing thrust areas. We continue to encourage innovative ideas that bring quality results to existing programs. We also take as our mission the encouragement of investment in new technology areas that are important to the economic competitiveness of this nation. In fiscal year 1992, we have focused on nine projects, summarized in this report: (1) Tire, Accident, Handling, and Roadway Safety; (2) EXTRANSYT: An Expert System for Advanced Traffic Management; (3) Odin: A High-Power, Underwater, Acoustic Transmitter for Surveillance Applications; (4) Passive Seismic Reservoir Monitoring: Signal Processing Innovations; (5) Paste Extrudable Explosive Aft Charge for Multi-Stage Munitions; (6) A Continuum Model for Reinforced Concrete at High Pressures and Strain Rates: Interim Report; (7) Benchmarking of the Criticality Evaluation Code COG; (8) Fast Algorithm for Large-Scale Consensus DNA Sequence Assembly; and (9) Using Electrical Heating to Enhance the Extraction of Volatile Organic Compounds from Soil.

  16. Hearing Assistive Technology

    MedlinePlus

    ... for the Public / Hearing and Balance Hearing Assistive Technology Hearing Assistive Technology: FM Systems | Infrared Systems | Induction ... Assistive Technology Systems Solutions What are hearing assistive technology systems (HATS)? Hearing assistive technology systems (HATS) are ...

  17. Manufacturing technology

    SciTech Connect

    Blaedel, K L

    1998-01-01

    The mission of the Manufacturing Technology thrust area at Lawrence Livermore National Laboratory (LLNL) has been to have an adequate base of manufacturing technology, not necessarily resident at LLNL, to conduct their future business. The specific goals were (1) to develop an understanding of fundamental fabrication processes; (2) to construct general purpose process models that have wide applicability; (3) to document their findings and models in journals; (4) to transfer technology to LLNL programs, industry, and colleagues; and (5) to develop continuing relationships with the industrial and academic communities to advance their collective understanding of fabrication processes. In support of this mission, two projects were reported here, each of which explores a way to bring higher precision to the manufacturing challenges that we face over the next few years. The first, ''A Spatial-Frequency-Domain Approach to Designing a Precision Machine Tools,'' is an overall view of how they design machine tools and instruments to make or measure workpieces that are specified in terms of the spatial frequency content of the residual errors of the workpiece surface. This represents an improvement of an ''error budget,'' a design tool that saw significant development in the early 1980's, and has been in active use since then. The second project, ''Micro-Drilling of ICF Capsules,'' is an attempt to define the current state in commercial industry for drilling small holes, particularly laser-drilling. The report concludes that 1-{micro}m diameter holes cannot currently be drilled to high aspect ratios, and then defines the engineering challenges that will have to be overcome to machine holes small enough for NIF capsules.

  18. Telemetry Technology

    NASA Technical Reports Server (NTRS)

    1997-01-01

    In 1990, Avtec Systems, Inc. developed its first telemetry boards for Goddard Space Flight Center. Avtec products now include PC/AT, PCI and VME-based high speed I/O boards and turn-key systems. The most recent and most successful technology transfer from NASA to Avtec is the Programmable Telemetry Processor (PTP), a personal computer- based, multi-channel telemetry front-end processing system originally developed to support the NASA communication (NASCOM) network. The PTP performs data acquisition, real-time network transfer, and store and forward operations. There are over 100 PTP systems located in NASA facilities and throughout the world.

  19. Testing technology

    SciTech Connect

    Not Available

    1993-10-01

    This bulletin from Sandia National Laboratories presents current research highlights in testing technology. Ion microscopy offers new nondestructive testing technique that detects high resolution invisible defects. An inexpensive thin-film gauge checks detonators on centrifuge. Laser trackers ride the range and track helicopters at low-level flights that could not be detected by radar. Radiation transport software predicts electron/photon effects via cascade simulation. Acoustic research in noise abatement will lead to quieter travelling for Bay Area Rapid Transport (BART) commuters.

  20. Wearable Technology

    NASA Technical Reports Server (NTRS)

    Watson, Amanda

    2013-01-01

    Wearable technology projects, to be useful, in the future, must be seamlessly integrated with the Flight Deck of the Future (F.F). The lab contains mockups of space vehicle cockpits, habitat living quarters, and workstations equipped with novel user interfaces. The Flight Deck of the Future is one element of the Integrated Power, Avionics, and Software (IPAS) facility, which, to a large extent, manages the F.F network and data systems. To date, integration with the Flight Deck of the Future has been limited by a lack of tools and understanding of the Flight Deck of the Future data handling systems. To remedy this problem it will be necessary to learn how data is managed in the Flight Deck of the Future and to develop tools or interfaces that enable easy integration of WEAR Lab and EV3 products into the Flight Deck of the Future mockups. This capability is critical to future prototype integration, evaluation, and demonstration. This will provide the ability for WEAR Lab products, EV3 human interface prototypes, and technologies from other JSC organizations to be evaluated and tested while in the Flight Deck of the Future. All WEAR Lab products must be integrated with the interface that will connect them to the Flight Deck of the Future. The WEAR Lab products will primarily be programmed in Arduino. Arduino will be used for the development of wearable controls and a tactile communication garment. Arduino will also be used in creating wearable methane detection and warning system.

  1. Dezincing Technology

    SciTech Connect

    Dudek, F.J.; Daniels, E.J.; Morgan, W.A.

    1997-08-01

    Half of the steel produced in the US is derived from scrap. With zinc-coated prompt scrap increasing fivefold since 1980, steel-makers are feeling the effect of increased contaminant loads on their operations. The greatest concern is the cost of treatment before disposal of waste dusts and water that arise from remelting zinc-coated scrap. An economic process is needed to strip and recover the zinc from scrap to provide a low residual scrap for steel- and iron-making. Metal Recovery Technologies, Inc., with the assistance of Argonne National Laboratory, have been developing a caustic leach dezincing process for upgrading galvanized stamping plant scrap into clean scrap with recovery of the zinc. With further development the technology could also process galvanized scrap from obsolete automobiles. This paper will review: (1) the status of recent pilot plant operations and plans for a commercial demonstration facility with a dezincing capacity of up to 250,000 tons/year, (2) the economics of caustic dezincing, and (3) benefits of decreased cost of environmental compliance, raw material savings, and improved operations with use of dezinced scrap.

  2. Microfluidic technologies.

    PubMed

    Bhagat, Ali Asgar S; Lim, Chwee Teck

    2012-01-01

    Presence of circulating tumor cells (CTCs) in blood is an important intermediate step in cancer metastasis, a mortal consequence of cancer. However, CTCs are extremely rare in blood with highly heterogeneous morphologies and molecular signatures, thus making their isolation technically very challenging. In the past decade, a flurry of new microfluidic-based technologies has emerged to address this compelling problem. This chapter highlights the current state of the art in microfluidic systems developed for CTCs separation and isolation. The techniques presented are broadly classified as physical- or affinity-based isolation depending on the separation principle. The performance of these techniques is evaluated based on accepted separation metrics including sensitivity, purity and processing/analysis time. Finally, further insights associated with realizing an integrated microfluidic CTC lab-on-chip system as an onco-diagnostic tool will be discussed. PMID:22527494

  3. How Technology Teachers Understand Technological Knowledge

    ERIC Educational Resources Information Center

    Norström, Per

    2014-01-01

    Swedish technology teachers' views of technological knowledge are examined through a written survey and a series of interviews. The study indicates that technology teachers' understandings of what constitutes technological knowledge and how it is justified vary considerably. The philosophical discussions on the topic are unknown to them.…

  4. CMM Technology

    SciTech Connect

    Ward, Robert C.

    2008-10-20

    This project addressed coordinate measuring machine (CMM) technology and model-based engineering. CMM data analysis and delivery were enhanced through the addition of several machine types to the inspection summary program. CMM hardware and software improvements were made with the purchases of calibration and setup equipment and new model-based software for the creation of inspection programs. Kansas City Plant (KCP) personnel contributed to and influenced the development of dimensional metrology standards. Model-based engineering capabilities were expanded through the development of software for the tolerance analysis of piece parts and for the creation of model-based CMM inspection programs and inspection plans and through the purchase of off-the-shelf software for the tolerance analysis of mechanical assemblies. An obsolete database application used to track jobs in Precision Measurement was replaced by a web-based application with improved query and reporting capabilities. A potential project to address the transformation of the dimensional metrology enterprise at the Kansas City Plant was identified.

  5. Technology transfer within NASA

    NASA Technical Reports Server (NTRS)

    St.cyr, William

    1992-01-01

    Viewgraphs on technology transfer within NASA are provided. Assessment of technology transfer process, technology being transfered, issues and barriers, and observations and suggestions are addressed. Topics covered include: technology transfer within an organization (and across organization lines/codes) and space science/instrument technology and the role of universities in the technology development/transfer process.

  6. Guidance, navigation, and control digital emulation technology laboratory

    NASA Astrophysics Data System (ADS)

    1994-07-01

    The tasks of a speed test on the rad-hard FPU chip developed by Harris and the development of an FPA Test System are reviewed. Georgia Tech got three hardened chips from Harris: FPU 1, FPU 2, and FPU 3. The third chip (FPU 3) gave erroneous results at any frequency. This may have been caused by inserting the chip into the socket incorrectly due to an incorrect pin diagram. FPU 2 was also inserted into the socket incorrectly; however, it did not stay in that configuration for very long and the only damage was a disabling of the fourth bit on the chip output. This was remedied by modifying the test software to mask out that bit. A commercial chip was designed on the Genesil silicon Compiler and fabricated by NCR using their 1.25 micron CMOS process. The rad-hard FPU chips were designed using a new version of the Genesil silicon compiler. The hardened chips, in a non-active mode, use about half the power of the commercial FPU chip. Tests were separated into 10 categories: logical, shift, integer addition, integer multiplication, floating point addition, floating point multiplication, pack exponent and float, generate speed, round or truncate a result, and sign manipulation. The FPA test system is being developed to analyze the characteristics and quality of an FPA sensor. It allows a user to study the effectiveness of the FPA sensor when using various signal and image processing functions. The primary features supported by the Georgia Tech system are the ability to: (1) interface a wide range of FPA's using a specification defined by USASSDC; (2) display the raw FPA image live on a color monitor to enable a user to visually locate bad detectors, and to compare and characterize the quality of an FPA sensor; (3) select or program any of the four signal/image filters provided (non-uniformity compensation, temporal filtering, spatial filtering, and thresholding); and (4) display the intermediate filtered frame outputs in real time, at a refresh rate that does not strain

  7. Flywheel Technology

    NASA Technical Reports Server (NTRS)

    Ritchie, Lisa M.

    2004-01-01

    Throughout the summer of 2004, I am working on a number of different projects. While located in the Space Power and Propulsion Test Engineering branch, my main area of study is flywheel technology. I have been exposed to flywheels, their components, and their uses in today's society. I have been able to experience numerous flywheels here in the flywheel lab at NASA Glenn. My first main project was to explore the attributes and physical characteristics of a flywheel. Our branch was constructing a flywheel demonstration to be presented at the public open house taking place in June. Our Flywheel Interactive Demo, or FIDO, represents a real life multi-flywheel system here at NASA. I was given the opportunity to learn about how these flywheels store energy and are able to position a satellite. With all of this new knowledge, I was able to create the posters that explained how our demonstration worked. I also composed a step-by-step process made up of four experiments that any visitor could follow and perform on FIDO. By stepping through these experiments, the individual learns how a flywheel works. They not only read the explanation of what is happening, but they are also able to see it happen. Creating these two posters not only taught me, but also helped teach the general public during the open house, how flywheel technology is a very important part of our future. Through my research, I have learned that flywheels are able to store massive amounts of energy. They can be described as an electro-mechanical battery that stores kinetic energy while rotating. The faster it rotates, the more energy it stores. Their lifetime is about triple that of an ordinary battery. Flywheels also have the ability to combine energy storage with attitude control all in a single system. Attitude control is the ability to position a satellite as required. FIDO helps us to understand the rotational force (torque) that is applied upon a turn-table or satellite during wheel acceleration

  8. CLIC-ACM: generic modular rad-hard data acquisition system based on CERN GBT versatile link

    NASA Astrophysics Data System (ADS)

    Bielawski, B.; Locci, F.; Magnoni, S.

    2015-01-01

    CLIC is a world-wide collaboration to study the next ``terascale'' lepton collider, relying upon a very innovative concept of two-beam-acceleration. This accelerator, currently under study, will be composed of the subsequence of 21000 two-beam-modules. Each module requires more than 300 analogue and digital signals which need to be acquired and controlled in a synchronous way. CLIC-ACM (Acquisition and Control Module) is the 'generic' control and acquisition module developed to accommodate the controls of all these signals for various sub-systems and related specification in term of data bandwidth, triggering and timing synchronization. This paper describes the system architecture with respect to its radiation-tolerance, power consumption and scalability.

  9. Militarily Critical Technology Program

    NASA Astrophysics Data System (ADS)

    Doherty, J.; Wick, R.; Sellers, P.

    The Militarily Critical Technology Program (MCTP) creates two technology lists: Militarily Critical Technology List (MCTL), which is focused on protecting US technology, and Developing Science and Technology List (DSTL). There are 20 different technology areas; two in particular are discussed in this poster paper, Space Systems Technologies and Lasers & Optics Technologies. The authors are the Technology Working Group chairs for Space Systems (Jim Doherty) and Lasers & Optics (Ray Wick), both from Institute for Defense Analyses (IDA), and also IDAs task leader for the MCTP (Paul Sellers).

  10. ENVIRONMENTAL TECHNOLOGY VERIFICATION (ETV) PROGRAM: STORMWATER TECHNOLOGIES

    EPA Science Inventory

    The U.S. Environmental Protection Agency (EPA) Environmental Technology Verification (ETV) program evaluates the performance of innovative air, water, pollution prevention and monitoring technologies that have the potential to improve human health and the environment. This techn...

  11. Plasma technology directory

    SciTech Connect

    Ward, P.P.; Dybwad, G.L.

    1995-03-01

    The Plasma Technology Directory has two main goals: (1) promote, coordinate, and share plasma technology experience and equipment within the Department of Energy; and (2) facilitate technology transfer to the commercial sector where appropriate. Personnel are averaged first by Laboratory and next by technology area. The technology areas are accelerators, cleaning and etching deposition, diagnostics, and modeling.

  12. Technological Literacy. ERIC Digest.

    ERIC Educational Resources Information Center

    Wonacott, Michael E.

    Technological literacy includes the following elements: (1) the ability to use technology; (2) knowledge about the details of individual technologies and the processes of technology development; (3) a holistic understanding of the historical and cultural context of technology and adaptability based on initiative and resourceful thinking; and (4) a…

  13. Technology Education: Craft, Creativity, Textbooks or Technology

    ERIC Educational Resources Information Center

    Autio, Ossi

    2006-01-01

    Changes in the economy, nature, production and society together with increasing scientific and technological knowledge make demands of transforming school teaching in the field of technology education. This article analyses current trends in Finnish technology education. The aim of the article is to explore briefly the integration between Science…

  14. Greenhouse Gas Monitoring Technologies Technology Brief

    EPA Science Inventory

    This is a Technology Brief for the ETV Program. The EPA Environmental Technology Verification Program (ETV) develops test protocols and verifies the performance of innovative technologies that have the potential to improve protection of human health and the environment. The progr...

  15. Engaging Technology & Learning Opportunities: Technology Assessment Tools.

    ERIC Educational Resources Information Center

    Phye, Gary D.

    This paper focuses on the development of instruments to measure technology integration in learning environments. The model used as the basis for these instruments is the Technology Effectiveness Framework developed at the North Central Regional Educational Laboratory and described in "Designing Learning and Technology for Educational Reform" (B.…

  16. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    NASA Astrophysics Data System (ADS)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  17. Prosthetics and Related Technology

    MedlinePlus

    ... and Related Technology for Restoring Veterans’ Abilities DISCOVERY INNOVATION ADVANCEMENT PROSTHETICS AND RELATED TECHNOLOGY VA Research and ... technology to perform day-to-day activities. DISCOVERY INNOVATION ADVANCEMENT DISCOVERY INNOVATION ADVANCEMENT A Message to Our ...

  18. Technology Demonstration Missions

    NASA Video Gallery

    NASA's Technology Demonstration Missions (TDM) Program seeks to infuse new technology into space applications, bridging the gap between mature “lab-proven” technology and "flight-ready" status....

  19. International Technology Transfer.

    ERIC Educational Resources Information Center

    Morris, Robert G.

    The flow of technology out of the United States is discussed. Methods of technology flow, such as licensing and investing, are identified, and the advantages and disadvantages of technology transfer are discussed, especially in relation to the government's role. (MLH)

  20. Information Technology for Education.

    ERIC Educational Resources Information Center

    Snyder, Cathrine E.; And Others

    1990-01-01

    Eight papers address technological, behavioral, and philosophical aspects of the application of information technology to training. Topics include instructional technology centers, intelligent training systems, distance learning, automated task analysis, training system selection, the importance of instructional methods, formative evaluation and…

  1. EPA ENVIRONMENTAL TECHNOLOGY EXPERIENCE

    EPA Science Inventory

    THE USEPA's Environmental Technology Verification for Metal Finishing Pollution Prevention Technologies (ETV-MF) Program verifies the performance of innovative, commercial-ready technologies designed to improve industry performance and achieve cost-effective pollution prevention ...

  2. Technology and Distance Education.

    ERIC Educational Resources Information Center

    Pelton, J. N.; Bates, A. W.

    1991-01-01

    Two articles evaluate the impact of new transmission and information technologies on education: "Technology and Education--Friend or Foe?" (Pelton) and "Third Generation Distance Education: The Challenge of New Technology" (Bates). (SK)

  3. Technology Transfer Report

    NASA Technical Reports Server (NTRS)

    2000-01-01

    Since its inception, Goddard has pursued a commitment to technology transfer and commercialization. For every space technology developed, Goddard strives to identify secondary applications. Goddard then provides the technologies, as well as NASA expertise and facilities, to U.S. companies, universities, and government agencies. These efforts are based in Goddard's Technology Commercialization Office. This report presents new technologies, commercialization success stories, and other Technology Commercialization Office activities in 1999.

  4. Morgantown Energy Technology Center, technology summary

    SciTech Connect

    Not Available

    1994-06-01

    This document has been prepared by the DOE Environmental Management (EM) Office of Technology Development (OTD) to highlight its research, development, demonstration, testing, and evaluation activities funded through the Morgantown Energy Technology Center (METC). Technologies and processes described have the potential to enhance DOE`s cleanup and waste management efforts, as well as improve US industry`s competitiveness in global environmental markets. METC`s R&D programs are focused on commercialization of technologies that will be carried out in the private sector. META has solicited two PRDAs for EM. The first, in the area of groundwater and soil technologies, resulted in twenty-one contact awards to private sector and university technology developers. The second PRDA solicited novel decontamination and decommissioning technologies and resulted in eighteen contract awards. In addition to the PRDAs, METC solicited the first EM ROA in 1993. The ROA solicited research in a broad range of EM-related topics including in situ remediation, characterization, sensors, and monitoring technologies, efficient separation technologies, mixed waste treatment technologies, and robotics. This document describes these technology development activities.

  5. Technology and Economics, Inc. Technology Application Team

    NASA Technical Reports Server (NTRS)

    Ballard, T.; Macfadyen, D. J.

    1981-01-01

    Technology + Economics, Inc. (T+E), under contract to the NASA Headquarters Technology Transfer Division, operates a Technology Applications Team (TATeam) to assist in the transfer of NASA-developed aerospace technology. T+E's specific areas of interest are selected urban needs at the local, county, and state levels. T+E contacts users and user agencies at the local, state, and county levels to assist in identifying significant urban needs amenable to potential applications of aerospace technology. Once viable urban needs have been identified in this manner, or through independent research, T+E searches the NASA technology database for technology and/or expertise applicable to the problem. Activities currently under way concerning potential aerospace applications are discussed.

  6. Digital SPC switching technology: Foreign technology assessment

    NASA Astrophysics Data System (ADS)

    Fischman, Kurt; Jorstad, Norman D.

    1990-12-01

    This paper provides a foreign technology assessment of digital switching technology. Leading suppliers of digital switching technology are identified; although the United States holds a large part of the market, major companies in France, Sweden, Japan, the U.K., and Germany are also important. These countries, along with Belgium and Canada, are the most innovative and technically advanced. A listing is provided of transfers of digital switching technology to non-COCOM countries through licensing and joint ventures which reflects the widespread dissemination of this technology. Detailed technical specifications are provided for selected digital switching systems worldwide. The report concludes that considering the degree to which the technology is in place, that control of digital switching technology may not be feasible.

  7. Technology 2000, volume 2

    NASA Technical Reports Server (NTRS)

    1991-01-01

    Technology 2000 was the first major industrial conference and exposition spotlighting NASA technology and technology transfer. It's purpose was, and continues to be, to increase awareness of existing NASA-developed technologies that are available for immediate use in the development of new products and processes, and to lay the groundwork for the effective utilization of emerging technologies. Included are sessions on: computer technology and software engineering; human factors engineering and life sciences; materials science; sensors and measurement technology; artificial intelligence; environmental technology; optics and communications; and superconductivity.

  8. Synchronous Energy Technology

    NASA Technical Reports Server (NTRS)

    1980-01-01

    The synchronous technology requirements for large space power systems are summarized. A variety of technology areas including photovoltaics, thermal management, and energy storage, and power management are addressed.

  9. Technology Drives Exploration

    NASA Video Gallery

    NASA is investing in the future by advancing its capabilities and developing transformative technologies required to reach the challenging destinations that await exploration. The Space Technology ...

  10. Desert Research and Technology Studies (DRATS) Traverse Planning

    NASA Technical Reports Server (NTRS)

    Horz, Friedrich

    2012-01-01

    Slide 1] The Desert Research and Technology Studies (DRATS) include large scale field tests of manned lunar surface exploration systems; these tests are sponsored by the Director s Office of Integration (DOI) [sic, Directorate Integration Office (DIO)] within the Constellation Program and they include geological exploration objectives along well designed traverses. These traverses are designed by the Traverse Team, an ad hoc group of some 10 geologists form NASA and academia, as well as experts in mission operation who define the operational constraints applicable to specific simulation scenarios. [Slide 2] These DRATS/DOI tests focus on 1) the performance of major surface systems, such as rovers, mobile habitats, communication architecture, navigation tools, earth-moving equipment, unmanned reconnaissance robots etc. under realistic field conditions and 2) the development of operational concepts that integrate all of these systems into a single, optimized operation. The participation of science is currently concentrating on geological sciences, with the objective of developing suitable tools and documentation protocols to sample representative rocks for Earth return, and to generate some conceptual understanding of the ground support structure that will be needed for the real time science-support of a lunar surface crew. [Slide 3] Major surface systems exercised in the June 2008 analog tests at the Moses Lake site, WA. [Upper left] The Chariot Rover (developed at Johnson Space Center) is an unpressurized vehicle driven by fully suited crews. [Upper right] Mobile Habitat provided by the Jet Propulsion Laboratory. Chariot is the more nimble and mobile vehicle and the idea is to drive the habitat remotely to some rendezvous place where Chariot would catch up - after a lengthy traverse - at the end of the day. [Lower left] The K-10 remotely operated robot (provided by NASA Ames Research Center) conducting scientific/geologic reconnaissance of the prospective traverse

  11. Fundamentals of technology roadmapping

    SciTech Connect

    Garcia, M.L.; Bray, O.H.

    1997-04-01

    Technology planning is important for many reasons. Globally, companies are facing many competitive problems. Technology roadmapping, a form of technology planning can help deal with this increasingly competitive environment. While it has been used by some companies and industries, the focus has always been on the technology roadmap as a product, not on the process. This report focuses on formalizing the process so that it can be more broadly and easily used. As a DOE national security laboratory with R&D as a major product, Sandia must do effective technology planning to identify and develop the technologies required to meet its national security mission. Once identified, technology enhancements or new technologies may be developed internally or collaboratively with external partners. For either approach, technology roadmapping, as described in this report, is an effective tool for technology planning and coordination, which fits within a broader set of planning activities. This report, the second in a series on technology roadmapping, develops and documents this technology roadmapping process, which can be used by Sandia, other national labs, universities, and industry. The main benefit of technology roadmapping is that it provides information to make better technology investment decisions by identifying critical technologies and technology gaps and identifying ways to leverage R&D investments. It can also be used as a marketing tool. Technology roadmapping is critical when the technology investment decision is not straight forward. This occurs when it is not clear which alternative to pursue, how quickly the technology is needed, or when there is a need to coordinate the development of multiple technologies. The technology roadmapping process consists of three phases - preliminary activity, development of the technology roadmap, and follow-up activity.

  12. Advanced Compact Holographic Data Storage System

    NASA Technical Reports Server (NTRS)

    Chao, Tien-Hsin; Zhou, Hanying; Reyes, George

    2000-01-01

    JPL, under current sponsorship from NASA Space Science and Earth Science Programs, is developing a high-density, nonvolatile and rad-hard Advanced Holographic Memory (AHM) system to enable large-capacity, high-speed, low power consumption, and read/write of data in a space environment. The entire read/write operation will be controlled with electro-optic mechanism without any moving parts. This CHDS will consist of laser diodes, photorefractive crystal, spatial light modulator, photodetector array, and I/O electronic interface. In operation, pages of information would be recorded and retrieved with random access and highspeed. The nonvolatile, rad-hard characteristics of the holographic memory will provide a revolutionary memory technology to enhance mission capabilities for all NASA's Earth Science Mission. In this paper, recent technology progress in developing this CHDS at JPL will be presented.

  13. Technology in TESOL.

    ERIC Educational Resources Information Center

    TESOL Journal, 1993

    1993-01-01

    This special issue is devoted to the theme of advancing technology in the teaching of English to speakers of other languages (TESOL). Articles include: "Technology in TESOL" (Richard Orem, Cynthia Holliday); TESOL Technology: Imposition or Opportunity?" (Simon Murison-Bowie); "A Review of Advanced Technologies for L2 Learning" (Nancy Hunt); "A…

  14. The Technological Personality

    ERIC Educational Resources Information Center

    Stivers, Richard

    2004-01-01

    If technology is the single most important factor in explaining the organization of modern societies, it is likewise the key to understanding the modern personality. The technological personality is the psychological counterpart to the technological society.Technology indirectly destroys the basis of a common morality and so leaves human…

  15. Students Attitudes towards Technology

    ERIC Educational Resources Information Center

    Ardies, Jan; De Maeyer, Sven; Gijbels, David; van Keulen, Hanno

    2015-01-01

    Technology is more present than ever. Young people are interested in technological products, but their opinions on education and careers in technology are not particularly positive (Johansson in "Mathematics, Science & Technology Education Report." European Round Table of Industrials, Brussel, 2009). If we want to stimulate…

  16. Children, Technology, and Flowers.

    ERIC Educational Resources Information Center

    Druin, Allison

    2003-01-01

    Suggests that as technology becomes more pervasive, it is important to ask why it can be important for children, discussing: how today's technologies offer new ways for children to socialize, how technology can empower children, and how new technologies create learning opportunities that support the "messiness" of being a child, the interactive…

  17. EPA'S ENVIRONMENTAL TECHNOLOGIES

    EPA Science Inventory

    The use of innovative technology is impeded by the lack of independent, credible information as to how the technology performs. Such data is needed by technology buyers and regulatory decision makers to make informed decisions on technologies that represent good financial invest...

  18. Technology Education: The Transition.

    ERIC Educational Resources Information Center

    Pedras, Melvin J.; And Others

    With technology constantly changing, educators are challenged to integrate technology education into the curriculum. In an effort to integrate a study of technology into the public school curriculum, educators at the University of Idaho identified the following areas as representative of modern technology literacy: computers and computer-aided…

  19. Technophobes Teaching with Technology

    ERIC Educational Resources Information Center

    Lecher, Mark

    2004-01-01

    Technology has been used in classroom situations for years now. Traditionally, technology has been used by faculty that were early adopters or who liked the technology. These faculty members would handle the implementation of technology and bring it into the classroom by themselves, with only a small amount of outside support. This evolved into…

  20. Technology in the Classroom.

    ERIC Educational Resources Information Center

    Speidel, Gisela E., Ed.

    1995-01-01

    This theme issue contains 20 articles dealing with technology in the classroom. The articles are: (1) "Distance Learning and the Future of Kamehameha Schools Bishop Estate" (Henry E. Meyer); (2) "Technology and Multiple Intelligences" (Bette Savini); (3) "Technology Brings Voyagers into Classrooms" (Kristina Inn and others); (4) "Technologies Old…

  1. Educational Technology in China

    ERIC Educational Resources Information Center

    Meifeng, Liu; Jinjiao, Lv; Cui, Kang

    2010-01-01

    This paper elaborates the two different academic views of the identity of educational technology in China at the current time--advanced-technology-oriented cognition, known as Electrifying Education, and problem-solving-oriented cognition, known as Educational Technology. It addresses five main modes of educational technology in China: as a…

  2. Technology and Education.

    ERIC Educational Resources Information Center

    O'Loughlin, Michael

    1985-01-01

    Discussed are possible ways in which new technology will affect society, particularly its impact on the distribution of power and economic wealth. Also considered are the impact of technological change on educational goals, education about technology, and use of technology in education. Implications for the future are addressed. (JN)

  3. Technology Standards for Students.

    ERIC Educational Resources Information Center

    Burke, Jennifer

    In many states technology standards for students have focused on basic computer skills, but more standards are beginning to focus on identifying technology skills that students need for school and the workplace. In most states in the Southern Region, technology standards for students are based on the National Educational Technology Standards for…

  4. Space and military radiation effects in silicon-on-insulator devices

    SciTech Connect

    Schwank, J.R.

    1996-09-01

    Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed.

  5. Pretreatment Technology Plan

    SciTech Connect

    Barker, S.A.; Thornhill, C.K.; Holton, L.K. Jr.

    1993-03-01

    This technology plan presents a strategy for the identification, evaluation, and development of technologies for the pretreatment of radioactive wastes stored in underground storage tanks at the Hanford Site. This strategy includes deployment of facilities and process development schedules to support the other program elements. This document also presents schedule information for alternative pretreatment systems: (1) the reference pretreatment technology development system, (2) an enhanced pretreatment technology development system, and (3) alternative pretreatment technology development systems.

  6. GRACE BIOREMEDIATION TECHNOLOGIES - DARAMEND™ BIOREMEDIATION TECHNOLOGY. INNOVATIVE TECHNOLOGY EVALUATION REPORT

    EPA Science Inventory

    Grace Dearborn's DARAMEND™ Bioremediation Technology was developed to treat soils/sediment contaminated with organic contaminants using solid-phase organic amendments. The amendments increase the soil’s ability to supply biologically available water/nutrients to micro...

  7. Payload software technology: Software technology development plan

    NASA Technical Reports Server (NTRS)

    1977-01-01

    Programmatic requirements for the advancement of software technology are identified for meeting the space flight requirements in the 1980 to 1990 time period. The development items are described, and software technology item derivation worksheets are presented along with the cost/time/priority assessments.

  8. Emerging Technologies Integrating Technology into Study Abroad

    ERIC Educational Resources Information Center

    Godwin-Jones, Robert

    2016-01-01

    "Ready access to travel and to technology-enhanced social networking (e.g., Facebook or Skype) has changed the nature of study abroad to the point where today's experiences are fundamentally different from those of earlier eras" (Kinginger, 2013a, p. 345). In addition to more travel options and greater technology availability, study…

  9. Technology for small spacecraft

    NASA Technical Reports Server (NTRS)

    1994-01-01

    This report gives the results of a study by the National Research Council's Panel on Small Spacecraft Technology that reviewed NASA's technology development program for small spacecraft and assessed technology within the U.S. government and industry that is applicable to small spacecraft. The panel found that there is a considerable body of advanced technology currently available for application by NASA and the small spacecraft industry that could provide substantial improvement in capability and cost over those technologies used for current NASA small spacecraft. These technologies are the result of developments by commercial companies, Department of Defense agencies, and to a lesser degree NASA. The panel also found that additional technologies are being developed by these same entities that could provide additional substantial improvement if development is successfully completed. Recommendations for future technology development efforts by NASA across a broad technological spectrum are made.

  10. Introducing Current Technologies

    NASA Technical Reports Server (NTRS)

    Mitchell, Tiffany

    1995-01-01

    The objective of the study was a continuation of the 'technology push' activities that the Technology Transfer Team conducts at this time. It was my responsibility to research current technologies at Langley Research Center and find a commercial market for these technologies in the private industry. After locating a market for the technologies, a mailing package was put together which informed the companies of the benefits of NASA Langley's technologies. The mailing package included articles written about the technology, patent material, abstracts from technical papers, and one-pagers which were used at the Technology Opportunities Showcase (TOPS) exhibitions. The companies were encouraged to consult key team members for further information on the technologies.

  11. SHARED TECHNOLOGY TRANSFER PROGRAM

    SciTech Connect

    GRIFFIN, JOHN M. HAUT, RICHARD C.

    2008-03-07

    The program established a collaborative process with domestic industries for the purpose of sharing Navy-developed technology. Private sector businesses were educated so as to increase their awareness of the vast amount of technologies that are available, with an initial focus on technology applications that are related to the Hydrogen, Fuel Cells and Infrastructure Technologies (Hydrogen) Program of the U.S. Department of Energy. Specifically, the project worked to increase industry awareness of the vast technology resources available to them that have been developed with taxpayer funding. NAVSEA-Carderock and the Houston Advanced Research Center teamed with Nicholls State University to catalog NAVSEA-Carderock unclassified technologies, rated the level of readiness of the technologies and established a web based catalog of the technologies. In particular, the catalog contains technology descriptions, including testing summaries and overviews of related presentations.

  12. [Health technology in Mexico].

    PubMed

    Cruz, C; Faba, G; Martuscelli, J

    1992-01-01

    The features of the health technology cycle are presented, and the effects of the demographic, epidemiologic and economic transition on the health technology demand in Mexico are discussed. The main problems of science and technology in the context of a decreasing scientific and technological activity due to the economic crisis and the adjustment policies are also analyzed: administrative and planning problems, low impact of scientific production, limitations of the Mexican private sector, and the obstacles for technology assessment. Finally, this paper also discusses the main support strategies for science and technology implemented by the Mexican government during the 1980s and the challenges and opportunities that lie ahead.

  13. Civil space technology initiative

    NASA Technical Reports Server (NTRS)

    1990-01-01

    The Civil Space Technology Initiative (CSTI) is a major, focused, space technology program of the Office of Aeronautics, Exploration and Technology (OAET) of NASA. The program was initiated to advance technology beyond basic research in order to expand and enhance system and vehicle capabilities for near-term missions. CSTI takes critical technologies to the point at which a user can confidently incorporate the new or expanded capabilities into relatively near-term, high-priority NASA missions. In particular, the CSTI program emphasizes technologies necessary for reliable and efficient access to and operation in Earth orbit as well as for support of scientific missions from Earth orbit.

  14. Technology 2000, volume 1

    NASA Technical Reports Server (NTRS)

    1991-01-01

    The purpose of the conference was to increase awareness of existing NASA developed technologies that are available for immediate use in the development of new products and processes, and to lay the groundwork for the effective utilization of emerging technologies. There were sessions on the following: Computer technology and software engineering; Human factors engineering and life sciences; Information and data management; Material sciences; Manufacturing and fabrication technology; Power, energy, and control systems; Robotics; Sensors and measurement technology; Artificial intelligence; Environmental technology; Optics and communications; and Superconductivity.

  15. Mars Technology Program: Planetary Protection Technology Development

    NASA Technical Reports Server (NTRS)

    Lin, Ying

    2006-01-01

    This slide presentation reviews the development of Planetary Protection Technology in the Mars Technology Program. The goal of the program is to develop technologies that will enable NASA to build, launch, and operate a mission that has subsystems with different Planetary Protection (PP) classifications, specifically for operating a Category IVb-equivalent subsystem from a Category IVa platform. The IVa category of planetary protection requires bioburden reduction (i.e., no sterilization is required) The IVb category in addition to IVa requirements: (i.e., terminal sterilization of spacecraft is required). The differences between the categories are further reviewed.

  16. FY04 Engineering Technology Reports Technology Base

    SciTech Connect

    Sharpe, R M

    2005-01-27

    Lawrence Livermore National Laboratory's Engineering Directorate has two primary discretionary avenues for its investment in technologies: the Laboratory Directed Research and Development (LDRD) program and the ''Tech Base'' program. This volume summarizes progress on the projects funded for technology-base efforts in FY2004. The Engineering Technical Reports exemplify Engineering's more than 50-year history of researching and developing (LDRD), and reducing to practice (technology-base) the engineering technologies needed to support the Laboratory's missions. Engineering has been a partner in every major program and project at the Laboratory throughout its existence, and has prepared for this role with a skilled workforce and technical resources. This accomplishment is well summarized by Engineering's mission: ''Enable program success today and ensure the Laboratory's vitality tomorrow''. LDRD is the vehicle for creating those technologies and competencies that are cutting edge. These require a significant level of research or contain some unknown that needs to be fully understood. Tech Base is used to apply those technologies, or adapt them to a Laboratory need. The term commonly used for Tech Base projects is ''reduction to practice''. Tech Base projects effect the natural transition to reduction-to-practice of scientific or engineering methods that are well understood and established. They represent discipline-oriented, core competency activities that are multi-programmatic in application, nature, and scope. The objectives of technology-base funding include: (1) the development and enhancement of tools and processes to provide Engineering support capability, such as code maintenance and improved fabrication methods; (2) support of Engineering science and technology infrastructure, such as the installation or integration of a new capability; (3) support for technical and administrative leadership through our technology Centers; and (4) the initial scoping and

  17. Geared power transmission technology

    NASA Technical Reports Server (NTRS)

    Coy, J. J.

    1983-01-01

    The historical path of the science and art of gearing is reviewed. The present state of gearing technology is discussed along with examples of some of the NASA-sponsored contributions to gearing technology. Future requirements in gearing are summarized.

  18. NASA Technology Applications Team

    NASA Technical Reports Server (NTRS)

    1979-01-01

    The contributions of NASA to the advancement of the level of the technology base of the United States are highlighted. Technological transfer from preflight programs, the Viking program, the Apollo program, and the Shuttle and Skylab programs is reported.

  19. Choosing the Right Technology.

    ERIC Educational Resources Information Center

    Shakeshaft, Charol; Mann, Dale; Becker, Jonathan; Sweeney, Kara

    2002-01-01

    Offers advice on how to identify, select, and implement the technology-based reading instruction program best suited to a school district's needs. Lists organizations that screen instructional technology products. (PKP)

  20. Aeronautics systems technology studies

    NASA Technical Reports Server (NTRS)

    Bauchspies, J. S.

    1983-01-01

    Data collection and analysis in the areas of air transportation, aircraft manufacturing and sales, airline operations, market projections, internal trade, and energy consumption; legislation and regulations, technology needs; surveys; decision-making; cost analyses; and technology transfer are discussed.

  1. Technology transfer for adaptation

    NASA Astrophysics Data System (ADS)

    Biagini, Bonizella; Kuhl, Laura; Gallagher, Kelly Sims; Ortiz, Claudia

    2014-09-01

    Technology alone will not be able to solve adaptation challenges, but it is likely to play an important role. As a result of the role of technology in adaptation and the importance of international collaboration for climate change, technology transfer for adaptation is a critical but understudied issue. Through an analysis of Global Environment Facility-managed adaptation projects, we find there is significantly more technology transfer occurring in adaptation projects than might be expected given the pessimistic rhetoric surrounding technology transfer for adaptation. Most projects focused on demonstration and early deployment/niche formation for existing technologies rather than earlier stages of innovation, which is understandable considering the pilot nature of the projects. Key challenges for the transfer process, including technology selection and appropriateness under climate change, markets and access to technology, and diffusion strategies are discussed in more detail.

  2. Neuroanatomy and transgenic technologies

    Technology Transfer Automated Retrieval System (TEKTRAN)

    This is a short review that introduces recent advances of neuroanatomy and transgenic technologies. The anatomical complexity of the nervous system remains a subject of tremendous fascination among neuroscientists. In order to tackle this extraordinary complexity, powerful transgenic technologies a...

  3. Effects of New Technologies.

    ERIC Educational Resources Information Center

    Social and Labour Bulletin, 1980

    1980-01-01

    Transnational implications of technological change and innovation in telecommunications are discussed, including impact on jobs and industrial relations, computer security, access to information, and effects of technological innovation on international economic systems. (SK)

  4. Potential Technology Needs

    NASA Technical Reports Server (NTRS)

    Platts, Steven H.

    2010-01-01

    This slide presentation reviews some of the technologies that will be required to maintain crew health. The general principle guiding the technology development is to integrate individual devices into small, flight-ready, reportable units.

  5. Vehicle Technologies Program Implementation

    SciTech Connect

    none,

    2009-06-19

    The Vehicle Technologies Program takes a systematic approach to Program implementation. Elements of this approach include the evaluation of new technologies, competitive selection of projects and partners, review of Program and project improvement, project tracking, and portfolio management and adjustment.

  6. Vehicle Technologies Program Planning

    SciTech Connect

    2009-06-19

    The Vehicle Technologies Program’s strategic goal is to develop sustainable, cost-competitive technologies to reduce U.S. dependence on petroleum, increase fuel efficiency, reduce greenhouse gas emissions and improve the Nation's energy security.

  7. Technology in Residence.

    ERIC Educational Resources Information Center

    Fox, Jordan

    1999-01-01

    Discusses the necessity for incorporating current technology in today's college residence halls to meet the more diverse and continued activities of its students. Technology addressed covers data networking and telecommunications, heating and cooling systems, and fire-safety systems. (GR)

  8. AMBIENT AMMONIA MONITORING TECHNOLOGIES

    EPA Science Inventory

    The Environmental Technology Verification (ETV) Program develops testing protocols and verifies the performance of innovative technologies that have the potential to improve the protection of human health and the environment. This abstract and poster describe the process by whic...

  9. FCS Technology Investigation Overview

    NASA Technical Reports Server (NTRS)

    Budinger, James; Gilbert, Tricia

    2007-01-01

    This working paper provides an overview of the Future Communication Study (FCS) technology investigation progress. It includes a description of the methodology applied to technology evaluation; evaluation criteria; and technology screening (down select) results. A comparison of screening results with other similar technology screening activities is provided. Additional information included in this working paper is a description of in-depth studies (including characterization of the L-band aeronautical channel; L-band deployment cost assessment; and performance assessments of candidate technologies in the applicable aeronautical channel) that have been conducted to support technology evaluations. The paper concludes with a description on-going activities leading to conclusion of the technology investigation and the development of technology recommendations.

  10. Exploration technology prioritization

    NASA Technical Reports Server (NTRS)

    Dula, Alex

    1992-01-01

    A series of outlines and graphs describing NASA's Space Exploration Initiative (SEI) technology prioritization are presented. Prioritization criteria and preliminary critical technology priorities for a first lunar outpost and a Mars and permanently-manned lunar mission are addressed.

  11. Crystal-Clear Technology.

    ERIC Educational Resources Information Center

    Ondris-Crawford, Renate J.; And Others

    1993-01-01

    Provides diagrams to aid in discussing polymer dispersed liquid crystal (PDLC) technology. Equipped with a knowledge of PDLC, teachers can provide students with insight on how the gap between basic science and technology is bridged. (ZWH)

  12. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

    PubMed

    Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

    2012-07-01

    In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

  13. Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

    NASA Astrophysics Data System (ADS)

    Seoane, N.; Aldegunde, M.; Nagy, D.; Elmessary, M. A.; Indalecio, G.; García-Loureiro, A. J.; Kalna, K.

    2016-07-01

    We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON/I OFF ratio (5.9 × 104 when L G = 12.8 nm and 5.7 × 104 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts.

  14. Radiation effects at cryogenic temperatures in Si-JEFT, GaAs MESFET, and MOSFET devices

    SciTech Connect

    Citterio, M.; Rescia, S.; Radeka, V.

    1995-12-01

    Front-end electronics for liquid ionization chamber calorimetry at hadron collider experiments may be exposed to substantial levels of ionizing radiation and neutron fluences in a cryogenic environment. Measurements of devices built with rad-hard technologies have shown that devices able to operate in these conditions exist. Several families of devices (Si-JFET`s, rad-hard MOSFET`s, and GaAs MESFET`s) have been irradiated and tested at a stable cryogenic temperature up to doses of 55 Mrad of ionizing radiation and up to neutron fluences of 4 {times} 10{sup 14} n/cm{sup 2}. Radiation effects on dc characteristics and on noise will be presented.

  15. Geothermal drilling technology update

    SciTech Connect

    Glowka, D.A.

    1997-04-01

    Sandia National Laboratories conducts a comprehensive geothermal drilling research program for the US Department of Energy, Office of Geothermal Technologies. The program currently includes seven areas: lost circulation technology, hard-rock drill bit technology, high-temperature instrumentation, wireless data telemetry, slimhole drilling technology, Geothermal Drilling Organization (GDO) projects, and drilling systems studies. This paper describes the current status of the projects under way in each of these program areas.

  16. Emerging technologies for telemedicine.

    PubMed

    Cao, Minh Duc; Minh, Cao Duc; Shimizu, Shuji; Antoku, Yasuaki; Torata, Nobuhiro; Kudo, Kuriko; Okamura, Koji; Nakashima, Naoki; Tanaka, Masao

    2012-01-01

    This paper focuses on new technologies that are practically useful for telemedicine. Three representative systems are introduced: a Digital Video Transport System (DVTS), an H.323 compatible videoconferencing system, and Vidyo. Based on some of our experiences, we highlight the advantages and disadvantages of each technology, and point out technologies that are especially targeted at doctors and technicians, so that those interested in using similar technologies can make appropriate choices and achieve their own goals depending on their specific conditions. PMID:22563284

  17. Emerging Technologies for Telemedicine

    PubMed Central

    Minh, Cao Duc; Antoku, Yasuaki; Torata, Nobuhiro; Kudo, Kuriko; Okamura, Koji; Nakashima, Naoki; Tanaka, Masao

    2012-01-01

    This paper focuses on new technologies that are practically useful for telemedicine. Three representative systems are introduced: a Digital Video Transport System (DVTS), an H.323 compatible videoconferencing system, and Vidyo. Based on some of our experiences, we highlight the advantages and disadvantages of each technology, and point out technologies that are especially targeted at doctors and technicians, so that those interested in using similar technologies can make appropriate choices and achieve their own goals depending on their specific conditions. PMID:22563284

  18. NASA Astrophysics Technology Needs

    NASA Technical Reports Server (NTRS)

    Stahl, H. Philip

    2012-01-01

    July 2010, NASA Office of Chief Technologist (OCT) initiated an activity to create and maintain a NASA integrated roadmap for 15 key technology areas which recommend an overall technology investment strategy and prioritize NASA?s technology programs to meet NASA?s strategic goals. Science Instruments, Observatories and Sensor Systems(SIOSS) roadmap addresses technology needs to achieve NASA?s highest priority objectives -- not only for the Science Mission Directorate (SMD), but for all of NASA.

  19. Creative Technology and Rap

    ERIC Educational Resources Information Center

    Ch'ien, Evelyn

    2011-01-01

    This paper describes how a linguistic form, rap, can evolve in tandem with technological advances and manifest human-machine creativity. Rather than assuming that the interplay between machines and technology makes humans robotic or machine-like, the paper explores how the pressure of executing artistic visions using technology can drive…

  20. Technology in Context

    ERIC Educational Resources Information Center

    Jeans, Nick; Manches, Andrew; Stokes, Eleanor; Balmer, Kim

    2011-01-01

    People frequently hear competing media and research claims about the educational value of new technologies. But too often it is not clear how, if at all, these technologies are supporting learning. And there is not enough attention paid to the challenges of trying to introduce these technologies successfully into an educational context. To what…

  1. Education Technology Transformation

    ERIC Educational Resources Information Center

    Kennedy, Mike

    2012-01-01

    Years ago, as personal computers and other technological advancements began to find their way into classrooms and other educational settings, teachers and administrators sought ways to use new technology to benefit students. The potential for improving education was clear, but the limitations of the available education technology made it difficult…

  2. Technology Must Bow

    ERIC Educational Resources Information Center

    Milne, Raymond S.

    1973-01-01

    Certain types of technological decision making are socially harmful causing unemployment, inequities of income, and decreased production. Technology should promote the improvement of society, not industry along. Social objectives of the developing countries should be thoroughly examined before instituting any technological decisions. (BL)

  3. Theme: Emerging Technologies.

    ERIC Educational Resources Information Center

    Malpiedi, Barbara J.; And Others

    1989-01-01

    Consists of six articles discussing the effect of emerging technologies on agriculture. Specific topics include (1) agriscience programs, (2) the National Conference on Agriscience and Emerging Occupations and Technologies, (3) biotechnology, (4) program improvement through technology, (5) the Agriscience Teacher of the Year program, and (6)…

  4. Resources in Technology 7.

    ERIC Educational Resources Information Center

    International Technology Education Association, Reston, VA.

    This volume of Resources in Technology contains the following eight instructional modules: (1) "Processing Technology"; (2) "Water--A Magic Resource"; (3) "Hazardous Waste Disposal--The NIMBY (Not in My Backyard) Syndrome"; (4) "Processing Fibers and Fabrics"; (5) "Robotics--An Emerging Technology"; (6) Machine Vision--Giving Eyes to Robots"; (7)…

  5. Technology 2004, Vol. 2

    NASA Technical Reports Server (NTRS)

    1995-01-01

    Proceedings from symposia of the Technology 2004 Conference, November 8-10, 1994, Washington, DC. Volume 2 features papers on computers and software, virtual reality simulation, environmental technology, video and imaging, medical technology and life sciences, robotics and artificial intelligence, and electronics.

  6. Science and Technology.

    ERIC Educational Resources Information Center

    Wise, George

    1985-01-01

    Discusses differing views of the science and technology relationship held by policymakers (with budgets to defend) and historians of science and technology (largely without budgets). Focuses on the period after 1945 when leaders of United States science agencies propagandized an older idea that only "basic" science led to technology/technological…

  7. SITE EMERGING TECHNOLOGY Program

    EPA Science Inventory

    This document is intended as a reference guide for EPA Regional decision makers and others interested in tchnologies in the SITE Demonstration and Technologies programs. The Technologies are described in technology profiles presented in alphabetical order by developer name and se...

  8. Advanced Manufacturing Technologies

    NASA Technical Reports Server (NTRS)

    Fikes, John

    2016-01-01

    Advanced Manufacturing Technologies (AMT) is developing and maturing innovative and advanced manufacturing technologies that will enable more capable and lower-cost spacecraft, launch vehicles and infrastructure to enable exploration missions. The technologies will utilize cutting edge materials and emerging capabilities including metallic processes, additive manufacturing, composites, and digital manufacturing. The AMT project supports the National Manufacturing Initiative involving collaboration with other government agencies.

  9. Charting Community Technology Connections.

    ERIC Educational Resources Information Center

    Wahl, Ellen; Hobson, Hartley; Jeffers, Laura

    Communities have a wealth of technology resources and history on which to draw in thinking about and using technology in ways that support their values and goals. The technology connections that exist in a community may not be obvious, however. The activities presented in this guide are designed to help identify some of those connections and…

  10. Technology Performance Exchange

    SciTech Connect

    2015-09-01

    To address the need for accessible, high-quality data, the Department of Energy has developed the Technology Performance Exchange (TPEx). TPEx enables technology suppliers, third-party testing laboratories, and other entities to share product performance data. These data are automatically transformed into a format that technology evaluators can easily use in their energy modeling assessments to inform procurement decisions.

  11. High Technology Partnership Project.

    ERIC Educational Resources Information Center

    Francis Tuttle Vo-Tech Center, Oklahoma City, OK.

    The High Technology Center at Francis Tuttle Vo-Tech Center in Oklahoma City conducted an 18-month demonstration program, beginning in January 1989, to train or retrain average workers, unemployed because of cutbacks in their field or lack of marketable skills, for careers in high technology. The High Technology Center offered adults training in…

  12. Teaching Information Technology Law

    ERIC Educational Resources Information Center

    Taylor, M. J.; Jones, R. P.; Haggerty, J.; Gresty, D.

    2009-01-01

    In this paper we discuss an approach to the teaching of information technology law to higher education computing students that attempts to prepare them for professional computing practice. As information technology has become ubiquitous its interactions with the law have become more numerous. Information technology practitioners, and in particular…

  13. Trends in Technology Transfer.

    ERIC Educational Resources Information Center

    Starnick, Jurgen

    1988-01-01

    Various forms of technology transfer in Europe and North America are discussed including research contracts, cooperative research centers, and personnel transfer. Examples of approaches to technology transfer are given and the establishment of personnel transfer is discussed. Preconditions for successful technology transfer in the future are…

  14. Technology Assessment in Medicine.

    ERIC Educational Resources Information Center

    Littenberg, Benjamin

    1992-01-01

    This article defines the concepts of medical technology and technology assessment and offers a five-level assessment scheme for the evaluation of medical technologies, including (1) biologic plausibility; (2) technical feasibility; (3) intermediate outcomes; (4) patient outcomes; and (5) societal outcomes. This scheme is applied to the use of…

  15. TIPs for Technology Integration.

    ERIC Educational Resources Information Center

    Mandell, Susan; Sorge, Dennis H.; Russell, James D.

    2002-01-01

    Discusses the role of the teacher in effectively using technology in education based on the Technology Integration Project (TIP). Topics include why use technology; types of computer software; how to select software; software integration strategies; and effectively planning lessons that integrate the chosen software and integration strategy. (LRW)

  16. Educational Technology, Reimagined

    ERIC Educational Resources Information Center

    Eisenberg, Michael

    2010-01-01

    "Educational technology" is often equated in the popular imagination with "computers in the schools." But technology is much more than merely computers, and education is much more than mere schooling. The landscape of child-accessible technologies is blossoming in all sorts of directions: tools for communication, for physical construction and…

  17. Refocusing Space Technology

    NASA Technical Reports Server (NTRS)

    1994-01-01

    This video presents two examples of NASA Technology Transfer. The first is a Downhole Video Logger, which uses remote sensing technology to help in mining. The second example is the use of satellite image processing technology to enhance ultrasound images taken during pregnancy.

  18. Liberal Education and Technology.

    ERIC Educational Resources Information Center

    Brown, Peggy Ann, Ed.

    1985-01-01

    Projects at liberal arts colleges to help students understand technology, most of which were funded by the Alfred P. Sloan Foundations' New Liberal Arts Program, are described. Also included are John G. Truxal's essay, "Thoughts on Teaching Technology," which includes an illustration of technological problems/solutions posed by the pacemaker. The…

  19. Technology and Individual Differences.

    ERIC Educational Resources Information Center

    Cavalier, Albert R.; And Others

    1994-01-01

    Six papers on special education technology and individual differences are introduced. The papers illustrate the growing influence of constructivist perspectives on the use of technology to accommodate individual differences among people. The papers recognize the importance of using technology to scaffold the client's construction of different…

  20. A Technology Checkup.

    ERIC Educational Resources Information Center

    Sydow, James A.; Kirkpatrick, Clark M.

    1996-01-01

    A technology audit compares a school district's plans and expectations for technology with actual deployment and use. The audit addresses information systems; operational environment; administrative, teaching, and learning applications; student, finance, and human resources systems; technology; infrastructure; office automation and productivity…

  1. Selecting Security Technology Providers

    ERIC Educational Resources Information Center

    Schneider, Tod

    2009-01-01

    The world of security technology holds great promise, but it is fraught with opportunities for expensive missteps and misapplications. The quality of the security technology consultants and system integrators one uses will have a direct bearing on how well his school masters this complex subject. Security technology consultants help determine…

  2. Teaching Technology and Engineering

    ERIC Educational Resources Information Center

    de Vries, Marc J.; Hacker, Michael; Burghardt, David

    2010-01-01

    The publication of "Standards for Technological Literacy: Content for the Study of Technology" (ITEA/ITEEA, 2000/2002/2007) represented a major step forward in identifying the educational components necessary for life in a technological world. But this list of standards, though substantial, does not clearly identify the components that are most…

  3. Resources in Technology III.

    ERIC Educational Resources Information Center

    Ritz, John M.; And Others

    This document--intended to help technology education teachers plan their classroom curriculum for secondary school and college students--contains units on exploring high-impact technology, microcomputers as technological tools, integrated manufacturing systems (the future of design and production), the role of robotics in integrated manufacturing…

  4. Advanced manufacturing: Technology diffusion

    SciTech Connect

    Tesar, A.

    1995-12-01

    In this paper we examine how manufacturing technology diffuses rom the developers of technology across national borders to those who do not have the capability or resources to develop advanced technology on their own. None of the wide variety of technology diffusion mechanisms discussed in this paper are new, yet the opportunities to apply these mechanisms are growing. A dramatic increase in technology diffusion occurred over the last decade. The two major trends which probably drive this increase are a worldwide inclination towards ``freer`` markets and diminishing isolation. Technology is most rapidly diffusing from the US In fact, the US is supplying technology for the rest of the world. The value of the technology supplied by the US more than doubled from 1985 to 1992 (see the Introduction for details). History shows us that technology diffusion is inevitable. It is the rates at which technologies diffuse to other countries which can vary considerably. Manufacturers in these countries are increasingly able to absorb technology. Their manufacturing efficiency is expected to progress as technology becomes increasingly available and utilized.

  5. New Technologies in Mathematics.

    ERIC Educational Resources Information Center

    Sarmiento, Jorge

    An understanding of past technological advancements can help educators understand the influence of new technologies in education. Inventions such as the abacus, logarithms, the slide rule, the calculating machine, computers, and electronic calculators have all found their place in mathematics education. While new technologies can be very useful,…

  6. Thriving on Technology's Edge

    ERIC Educational Resources Information Center

    Huwe, Terence K.

    2009-01-01

    New technology appears at a fast pace these days. As individuals people must choose how much technology to allow into their personal worlds. Within organizations, people must collectively decide how to build, sustain, and perhaps jettison new technologies as they consider their long-term value and life span. This requires a collaborative spirit…

  7. Research and technology

    NASA Technical Reports Server (NTRS)

    1986-01-01

    The research and technology accomplishments of the NASA Lewis Research Center are summarized for the fiscal year 1986, the 45th anniversary year of the Center. Five major sections are presented covering: aeronautics, aerospace technology, space communications, space station systems, and computational technology support. A table of contents by subjects was developed to assist the reader in finding articles of special interest.

  8. Implementing technology assessments

    NASA Technical Reports Server (NTRS)

    Kasper, R. G. (Editor); Logsdon, J. M. (Editor); Mottur, E. R. (Editor)

    1975-01-01

    Five case studies of specific technology assessments and the ways in which they influenced (or did not influence) the development of the assessed technology are discussed. Automotive air pollution and problems of implementing technology assessment are considered. The assessment-acceptance-implementation process is discussed in detail using the five case studies as examples.

  9. Sex, Technology and Morality.

    ERIC Educational Resources Information Center

    Case, Verna; And Others

    1986-01-01

    Provides an overview of the course "Sex, Technology, and Morality" which focuses on the human reproductive process and examines the advances in reproductive technology. The course emphasizes the social, political, and ethical implications of actual and possible technologies associated with human reproduction. (ML)

  10. Options for Technology Transfer.

    ERIC Educational Resources Information Center

    Anderson, Richard E.; Sugarman, Barry

    1989-01-01

    Structural means by which institutions of higher education can tap technology are explored with an examination of the licensing of technological discoveries as well as the creation of start-up companies based upon university-developed technology. Additionally, the corporate structures that are being formed so that institutions can more easily hold…

  11. Enhancing Teaching with Technology.

    ERIC Educational Resources Information Center

    Pedras, Melvin J.; Oaks, Merrill

    Students who are not educated in the modern advances of our technological society will be ill-prepared for the world of work in the 21st century. It is therefore incumbent upon all educators to modify traditional curriculum to reflect contemporary technology. School technology education programs today are being developed to reflect the needs of…

  12. Stretching Your Technology Dollar

    ERIC Educational Resources Information Center

    Johnson, Doug

    2012-01-01

    A school district technology director offers 10 strategies to help schools make the most of their technology dollar. These include using effective budgeting techniques, taking advantage of the buying power of groups, practicing sustainable technology, purchasing the right tool for the right job, taking advantage of free software, using cloud…

  13. Sharing Science and Technology.

    ERIC Educational Resources Information Center

    Morgan, Robert P.

    1983-01-01

    Defining development as some combination of improving the standard of living and quality of life, meeting basic needs, and increasing per capita gross national product, this article discusses the role science and technology can play in developing countries. Considers technology transfer, appropriate technology, and other issues. (JN)

  14. Conducting a Technology Audit

    ERIC Educational Resources Information Center

    Flaherty, William

    2011-01-01

    Technology is a critical component in the success of any high-functioning school district, thus it is important that education leaders should examine it closely. Simply put, the purpose of a technology audit is to assess the effectiveness of the technology for administrative or instructional use. Rogers Public Schools in Rogers, Arkansas, recently…

  15. Mineral Processing Technology Roadmap

    SciTech Connect

    none,

    2000-09-01

    This document represents the roadmap for Processing Technology Research in the US Mining Industry. It was developed based on the results of a Processing Technology Roadmap Workshop sponsored by the National Mining Association in conjunction with the US Department of Energy, Office of Energy Efficiency and Renewable Energy, Office of Industrial Technologies. The Workshop was held January 24 - 25, 2000.

  16. The Technology Balance Beam

    ERIC Educational Resources Information Center

    Coulson, Eddie K.

    2006-01-01

    "The Technology Balance Beam" is designed to question the role of technology within school districts. This case study chronicles a typical school district in relation to the school district's implementation of technology beginning in the 1995-1996 school year. The fundamental question that this scenario raises is, What is the balance between…

  17. IVS Technology Coordinator Report

    NASA Technical Reports Server (NTRS)

    Whitney, Alan

    2013-01-01

    This report of the Technology Coordinator includes the following: 1) continued work to implement the new VLBI2010 system, 2) the 1st International VLBI Technology Workshop, 3) a VLBI Digital- Backend Intercomparison Workshop, 4) DiFX software correlator development for geodetic VLBI, 5) a review of progress towards global VLBI standards, and 6) a welcome to new IVS Technology Coordinator Bill Petrachenko.

  18. Technology Panel Reports

    NASA Technical Reports Server (NTRS)

    1984-01-01

    Results are presented from five technology panels which convened to identify relevant technologies within their discipline for the Large Deployable Reflector (LDR) and to assess the current and projected state of these technologies. The five panels considered the following topics: optics, materials and structure, sensing and control, science instruments, and systems and missions.

  19. New Technologies in Education.

    ERIC Educational Resources Information Center

    Grayson, Lawrence P.

    Many technologies besides microcomputers and videodiscs have been and are being used effectively in education, and this article provides an overview of the current utilization of a variety of educational technologies. Existing technologies are categorized according to their accessibility, whether used locally or over a distance, and their…

  20. Education Technology Success Stories

    ERIC Educational Resources Information Center

    West, Darrell M.; Bleiberg, Joshua

    2013-01-01

    Advances in technology are enabling dramatic changes in education content, delivery, and accessibility. Throughout history, new technologies have facilitated the exponential growth of human knowledge. In the early twentieth century, the focus was on the use of radios in education. But since then, innovators have seen technology as a way to improve…

  1. Technology in Education

    ERIC Educational Resources Information Center

    Roden, Kasi

    2011-01-01

    This paper was written to support a position on using technology in education. The purpose of this study was to support the use of technology in education by synthesizing previous research. A variety of sources including books and journal articles were studied in order to compile an overview of the benefits of using technology in elementary,…

  2. Recording Technologies: Sights & Sounds. Resources in Technology.

    ERIC Educational Resources Information Center

    Deal, Walter F., III

    1994-01-01

    Provides information on recording technologies such as laser disks, audio and videotape, and video cameras. Presents a design brief that includes objectives, student outcomes, and a student quiz. (JOW)

  3. Technology Assessment Report: Aqueous Sludge Gasification Technologies

    EPA Science Inventory

    The study reveals that sludge gasification is a potentially suitable alternative to conventional sludge handling and disposal methods. However, very few commercial operations are in existence. The limited pilot, demonstration or commercial application of gasification technology t...

  4. Payload software technology

    NASA Technical Reports Server (NTRS)

    1976-01-01

    A software analysis was performed of known STS sortie payload elements and their associated experiments. This provided basic data for STS payload software characteristics and sizes. A set of technology drivers was identified based on a survey of future technology needs and an assessment of current software technology. The results will be used to evolve a planned approach to software technology development. The purpose of this plan is to ensure that software technology is advanced at a pace and a depth sufficient to fulfill the identified future needs.

  5. Advanced sensors technology survey

    NASA Technical Reports Server (NTRS)

    Cooper, Tommy G.; Costello, David J.; Davis, Jerry G.; Horst, Richard L.; Lessard, Charles S.; Peel, H. Herbert; Tolliver, Robert

    1992-01-01

    This project assesses the state-of-the-art in advanced or 'smart' sensors technology for NASA Life Sciences research applications with an emphasis on those sensors with potential applications on the space station freedom (SSF). The objectives are: (1) to conduct literature reviews on relevant advanced sensor technology; (2) to interview various scientists and engineers in industry, academia, and government who are knowledgeable on this topic; (3) to provide viewpoints and opinions regarding the potential applications of this technology on the SSF; and (4) to provide summary charts of relevant technologies and centers where these technologies are being developed.

  6. Central receiver technology

    SciTech Connect

    Holl, R.L. )

    1989-09-01

    The research and development described in this document was conducted within the US Department of Energy's (DOE) Solar Thermal Technology Program. The goal of this program is to advance the engineering and scientific understanding of solar thermal technology and to establish the technology base from which private industry can develop solar thermal power production options for introduction into the competitive energy market. This report describes central receiver technology: its accomplishments to date, its current technology status, and the efforts still necessary to fully exploit it.

  7. Transferring Technology to Industry

    NASA Technical Reports Server (NTRS)

    Wolfenbarger, J. Ken

    2006-01-01

    This slide presentation reviews the technology transfer processes in which JPL has been involved to assist in transferring the technology derived from aerospace research and development to industry. California Institute of Technology (CalTech), the organization that runs JPL, is the leading institute in patents for all U.S. universities. There are several mechanisms that are available to JPL to inform industry of these technological advances: (1) a dedicated organization at JPL, National Space Technology Applications (NSTA), (2) Tech Brief Magazine, (3) Spinoff magazine, and (4) JPL publications. There have also been many start-up organizations and businesses from CalTech.

  8. Technology reviews: Glazing systems

    SciTech Connect

    Schuman, J.; Rubinstein, F.; Papamichael, K.; Beltran, L.; Lee, E.S.; Selkowitz, S.

    1992-09-01

    We present a representative review of existing, emerging, and future technology options in each of five hardware and systems areas in envelope and lighting technologies: lighting systems, glazing systems, shading systems, daylighting optical systems, and dynamic curtain wall systems. The term technology is used here to describe any design choice for energy efficiency, ranging from individual components to more complex systems to general design strategies. The purpose of this task is to characterize the state of the art in envelope and lighting technologies in order to identify those with promise for advanced integrated systems, with an emphasis on California commercial buildings. For each technology category, the following activities have been attempted to the extent possible: Identify key performance characteristics and criteria for each technology; determine the performance range of available technologies; identify the most promising technologies and promising trends in technology advances; examine market forces and market trends; and develop a continuously growing in-house database to be used throughout the project. A variety of information sources have been used in these technology characterizations, including miscellaneous periodicals, manufacturer catalogs and cut sheets, other research documents, and data from previous computer simulations. We include these different sources in order to best show the type and variety of data available, however publication here does not imply our guarantee of these data. Within each category, several broad classes are identified, and within each class we examine the generic individual technologies that fag into that class.

  9. Technology reviews: Shading systems

    SciTech Connect

    Schuman, J.; Rubinstein, F.; Papamichael, K.; Beltran, L.; Lee, E.S.; Selkowitz, S.

    1992-09-01

    We present a representative review of existing, emerging, and future technology options in each of five hardware and systems areas in envelope and lighting technologies: lighting systems, glazing systems, shading systems, daylighting optical systems, and dynamic curtain wall systems. The term technology is used here to describe any design choice for energy efficiency, ranging from individual components to more complex systems to general design strategies. The purpose of this task is to characterize the state of the art in envelope and lighting technologies in order to identify those with promise for advanced integrated systems, with an emphasis on California commercial buildings. For each technology category, the following activities have been attempted to the extent possible: Identify key performance characteristics and criteria for each technology. Determine the performance range of available technologies. Identify the most promising technologies and promising trends in technology advances. Examine market forces and market trends. Develop a continuously growing in-house database to be used throughout the project. A variety of information sources have been used in these technology characterizations, including miscellaneous periodicals, manufacturer catalogs and cut sheets, other research documents, and data from previous computer simulations. We include these different sources in order to best show the type and variety of data available, however publication here does not imply our guarantee of these data. Within each category, several broad classes are identified, and within each class we examine the generic individual technologies that fall into that class.

  10. Digital voltmeter technology acquisition

    NASA Astrophysics Data System (ADS)

    Chen, Qilin; Cui, Jianping

    1985-09-01

    China began its development of digital voltmeter at a fairly early stage. In 1965, the Beijing Radio Technology Research Bureau had already built a 5 digit voltmeter whose technical performance was comparable to the international standards at that time. However, at the present time, of the more than 50 models of 5 digit voltmeters produced by State designated factories, only 2 or 3 use the international standard interface and microcomputer technology; furthermore, due to the limited capability in processing, equipment and testing, they cannot be mass produced. As a result, the gap between the Chinese standard and international standard in digital voltmeter is further widened. The Beijing Radio Technology Institute prepared a plan to import the manufacturing technology of the 8520A digital system multimeters from the U.S. FLUKE Co., by using foreign exchange funds designated for mechanical and electrical instruments under the joint technology and trade program. In September 1981, an official contract and an agreement for technology cooperation were signed. The items imported to the 8520A technology and trade program can be divided into several stages: (1) import automated test and standard systems which are built using advanced technologies of the 1980's; (2) train personnel and begin production; (3) import key production equipment to coordinate with China's existing facilities; (4) modify the production lines based on FLUKE's advanced technology and begin CKD production; and (5) use the results of imported technologies in other research projects to stimulate development in related technologies.

  11. CSP: A Multifaceted Hybrid Architecture for Space Computing

    NASA Technical Reports Server (NTRS)

    Rudolph, Dylan; Wilson, Christopher; Stewart, Jacob; Gauvin, Patrick; George, Alan; Lam, Herman; Crum, Gary Alex; Wirthlin, Mike; Wilson, Alex; Stoddard, Aaron

    2014-01-01

    Research on the CHREC Space Processor (CSP) takes a multifaceted hybrid approach to embedded space computing. Working closely with the NASA Goddard SpaceCube team, researchers at the National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC) at the University of Florida and Brigham Young University are developing hybrid space computers that feature an innovative combination of three technologies: commercial-off-the-shelf (COTS) devices, radiation-hardened (RadHard) devices, and fault-tolerant computing. Modern COTS processors provide the utmost in performance and energy-efficiency but are susceptible to ionizing radiation in space, whereas RadHard processors are virtually immune to this radiation but are more expensive, larger, less energy-efficient, and generations behind in speed and functionality. By featuring COTS devices to perform the critical data processing, supported by simpler RadHard devices that monitor and manage the COTS devices, and augmented with novel uses of fault-tolerant hardware, software, information, and networking within and between COTS devices, the resulting system can maximize performance and reliability while minimizing energy consumption and cost. NASA Goddard has adopted the CSP concept and technology with plans underway to feature flight-ready CSP boards on two upcoming space missions.

  12. Technology and Global Change

    NASA Astrophysics Data System (ADS)

    Grübler, Arnulf

    2003-10-01

    Technology and Global Change describes how technology has shaped society and the environment over the last 200 years. Technology has led us from the farm to the factory to the internet, and its impacts are now global. Technology has eliminated many problems, but has added many others (ranging from urban smog to the ozone hole to global warming). This book is the first to give a comprehensive description of the causes and impacts of technological change and how they relate to global environmental change. Written for specialists and nonspecialists alike, it will be useful for researchers and professors, as a textbook for graduate students, for people engaged in long-term policy planning in industry (strategic planning departments) and government (R & D and technology ministries, environment ministries), for environmental activists (NGOs), and for the wider public interested in history, technology, or environmental issues.

  13. Applications of aerospace technology

    NASA Technical Reports Server (NTRS)

    Rouse, Doris J.

    1984-01-01

    The objective of the Research Triangle Institute Technology Transfer Team is to assist NASA in achieving widespread utilization of aerospace technology in terrestrial applications. Widespread utilization implies that the application of NASA technology is to benefit a significant sector of the economy and population of the Nation. This objective is best attained by stimulating the introduction of new or improved commercially available devices incorporating aerospace technology. A methodology is presented for the team's activities as an active transfer agent linking NASA Field Centers, industry associations, user groups, and the medical community. This methodology is designed to: (1) identify priority technology requirements in industry and medicine, (2) identify applicable NASA technology that represents an opportunity for a successful solution and commercial product, (3) obtain the early participation of industry in the transfer process, and (4) successfully develop a new product based on NASA technology.

  14. Space technology research plans

    NASA Technical Reports Server (NTRS)

    Hook, W. Ray

    1992-01-01

    Development of new technologies is the primary purpose of the Office of Aeronautics and Space Technology (OAST). OAST's mission includes the following two goals: (1) to conduct research to provide fundamental understanding, develop advanced technology and promote technology transfer to assure U.S. preeminence in aeronautics and to enhance and/or enable future civil space missions: and (2) to provide unique facilities and technical expertise to support national aerospace needs. OAST includes both NASA Headquarters operations as well as programmatic and institutional management of the Ames Research Center, the Langley Research Center and the Lewis Research Center. In addition. a considerable portion of OAST's Space R&T Program is conducted through the flight and science program field centers of NASA. Within OAST, the Space Technology Directorate is responsible for the planning and implementation of the NASA Space Research and Technology Program. The Space Technology Directorate's mission is 'to assure that OAST shall provide technology for future civil space missions and provide a base of research and technology capabilities to serve all national space goals.' Accomplishing this mission entails the following objectives: y Identify, develop, validate and transfer technology to: (1) increase mission safety and reliability; (2) reduce flight program development and operations costs; (3) enhance mission performance; and (4) enable new missions. Provide the capability to: (1) advance technology in critical disciplines; and (2) respond to unanticipated mission needs. In-space experiments are an integral part of OAST's program and provides for experimental studies, development and support for in-space flight research and validation of advanced space technologies. Conducting technology experiments in space is a valuable and cost effective way to introduce advanced technologies into flight programs. These flight experiments support both the R&T base and the focussed programs

  15. Emerging Propulsion Technologies

    NASA Technical Reports Server (NTRS)

    Keys, Andrew S.

    2006-01-01

    The Emerging Propulsion Technologies (EPT) investment area is the newest area within the In-Space Propulsion Technology (ISPT) Project and strives to bridge technologies in the lower Technology Readiness Level (TRL) range (2 to 3) to the mid TRL range (4 to 6). A prioritization process, the Integrated In-Space Transportation Planning (IISTP), was developed and applied in FY01 to establish initial program priorities. The EPT investment area emerged for technologies that scored well in the IISTP but had a low technical maturity level. One particular technology, the Momentum-eXchange Electrodynamic-Reboost (MXER) tether, scored extraordinarily high and had broad applicability in the IISTP. However, its technical maturity was too low for ranking alongside technologies like the ion engine or aerocapture. Thus MXER tethers assumed top priority at EPT startup in FY03 with an aggressive schedule and adequate budget. It was originally envisioned that future technologies would enter the ISP portfolio through EPT, and EPT developed an EPT/ISP Entrance Process for future candidate ISP technologies. EPT has funded the following secondary, candidate ISP technologies at a low level: ultra-lightweight solar sails, general space/near-earth tether development, electrodynamic tether development, advanced electric propulsion, and in-space mechanism development. However, the scope of the ISPT program has focused over time to more closely match SMD needs and technology advancement successes. As a result, the funding for MXER and other EPT technologies is not currently available. Consequently, the MXER tether tasks and other EPT tasks were expected to phased out by November 2006. Presentation slides are presented which provide activity overviews for the aerocapture technology and emerging propulsion technology projects.

  16. Technology transfer 1994

    SciTech Connect

    Not Available

    1994-01-01

    This document, Technology Transfer 94, is intended to communicate that there are many opportunities available to US industry and academic institutions to work with DOE and its laboratories and facilities in the vital activity of improving technology transfer to meet national needs. It has seven major sections: Introduction, Technology Transfer Activities, Access to Laboratories and Facilities, Laboratories and Facilities, DOE Office, Technologies, and an Index. Technology Transfer Activities highlights DOE`s recent developments in technology transfer and describes plans for the future. Access to Laboratories and Facilities describes the many avenues for cooperative interaction between DOE laboratories or facilities and industry, academia, and other government agencies. Laboratories and Facilities profiles the DOE laboratories and facilities involved in technology transfer and presents information on their missions, programs, expertise, facilities, and equipment, along with data on whom to contact for additional information on technology transfer. DOE Offices summarizes the major research and development programs within DOE. It also contains information on how to access DOE scientific and technical information. Technologies provides descriptions of some of the new technologies developed at DOE laboratories and facilities.

  17. [Earth Science Technology Office's Computational Technologies Project

    NASA Technical Reports Server (NTRS)

    Fischer, James (Technical Monitor); Merkey, Phillip

    2005-01-01

    This grant supported the effort to characterize the problem domain of the Earth Science Technology Office's Computational Technologies Project, to engage the Beowulf Cluster Computing Community as well as the High Performance Computing Research Community so that we can predict the applicability of said technologies to the scientific community represented by the CT project and formulate long term strategies to provide the computational resources necessary to attain the anticipated scientific objectives of the CT project. Specifically, the goal of the evaluation effort is to use the information gathered over the course of the Round-3 investigations to quantify the trends in scientific expectations, the algorithmic requirements and capabilities of high-performance computers to satisfy this anticipated need.

  18. Wibree: wireless communication technology

    NASA Astrophysics Data System (ADS)

    Fernandes e Fizardo, Trima Piedade

    2011-12-01

    Nowadays everywhere we come across electronic devices and now the world has become entirely mobile with so many new electronic equipments. The number of computing and telecommunications devices is increasing and consequently the focus on how to connect them to each other. The usual solution is to connect the device with cables or using infra red light to make file transfer and synchronizations possible but infrared light requires line of sight. To solve these problems a new technology,Wibree radio technology complements other local connectivity technologies, consuming only a fraction of the power compared to other radio technologies, enabling smaller and less costly implementations and being easy to integrate with Bluetooth solutions, Furthermore it can be also used to enable communication between several units such as small radio LANs.This paper focuses on why this technology has got large attention although there are pro's and con's with respect to other technologies.

  19. Global medicine technology.

    PubMed

    Mason, Cindy

    2005-01-01

    In little more than a decade, linkages between health care technologies of different cultures and continents have merged, resulting in global medicine technology. The next generation of young scientists and clinicians from both the research and clinical communities are merging established ancient technologies from outside the U.S. with modern medical technology and forging new ground in an increasingly challenging health care climate. Presently researchers, clinicians and communities are active in finding ways of using global medical technology to attack our most difficult and chronic (therefore expensive) health care problems. Using recent inventions, such as the fMRI, researchers and clinicians are understanding how and why they work. This chapter briefly discusses key ideas in the movement towards global medical technology: healthcare culture, mind-brain-body dialogue, and self-care including a self care exercise for the spine. PMID:16301783

  20. Emerging and Disruptive Technologies

    PubMed Central

    2016-01-01

    Several emerging or disruptive technologies can be identified that might, at some point in the future, displace established laboratory medicine technologies and practices. These include increased automation in the form of robots, 3-D printing, technology convergence (e.g., plug-in glucose meters for smart phones), new point-of-care technologies (e.g., contact lenses with sensors, digital and wireless enabled pregnancy tests) and testing locations (e.g., Retail Health Clinics, new at-home testing formats), new types of specimens (e.g., cell free DNA), big biology/data (e.g., million genome projects), and new regulations (e.g., for laboratory developed tests). In addition, there are many emerging technologies (e.g., planar arrays, mass spectrometry) that might find even broader application in the future and therefore also disrupt current practice. One interesting source of disruptive technology may prove to be the Qualcomm Tricorder XPrize, currently in its final stages.