Science.gov

Sample records for radhard soi technology

  1. Study of proton radiation effects on analog IC designed for high energy physics in a BICMOS-JFET radhard SOI technology

    SciTech Connect

    Blanquart, L.; Delpierre, P.; Habrard, M.C.

    1994-12-01

    The authors present experimental results from a fast charge amplifier and a wideband analog buffer processed in the DMILL BiCMOS-JFET radhard SOI technology and irradiated up to 4.5 {times} 10{sup 14} protons/cm{sup 2}. In parallel, they have irradiated elementary transistors. These components were biased and electrical measurements were done 30 min after beam stop. By evaluating variations of main SPICE parameters, i.e., threshold voltage shift for CMOS and current gain variation for bipolar transistors, they have simulated the wideband analog buffer at different doses. These SPICE simulations are in good agreement with measured circuit degradations. The behavior of the charge amplifier is consistent with extraction of transconductance and pinch-off voltage shift of the PJFET.

  2. Silicon pixel detector prototyping in SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    Dasgupta, Roma; Bugiel, Szymon; Idzik, Marek; Kapusta, Piotr; Kucewicz, Wojciech; Turala, Michal

    2016-12-01

    The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

  3. Realizing high breakdown voltages (>600 V) in partial SOI technology

    NASA Astrophysics Data System (ADS)

    Tadikonda, Ramakrishna; Hardikar, Shyam; Sankara Narayanan, E. M.

    2004-09-01

    A combination of uniform and variation in lateral doping (UVLD) profiles is proposed for the drift region of lateral power devices in partial SOI (PSOI) technology in order to achieve breakdown voltages above 600 V. LDMOS transistor structures incorporating the proposed doping profile are analyzed for their electrical characteristics and compared with conventional uniformly doped PSOI and thin layer SOI by extensive 2-D numerical simulations using MEDICI. The results indicate that the proposed doping profile can significantly improve the trade-off between breakdown voltage and specific on-resistance as well as the heat dissipation in comparison to uniformly doped PSOI and thin layer VLD SOI.

  4. Radhard and fast

    NASA Astrophysics Data System (ADS)

    Colucci, Frank

    1992-05-01

    The development of radiation-hardened processors and computers for the space environment is discussed from the point of view of proprietary signal and data processors for the Strategic Defense Initiative. The technology is developed specifically to qualify for military space applications, and the components can withstand up to 1,000 krad-Si. A radhard space-qualified 32-bit processor is described that is in the final stages of development and can be employed for signal and data processing in space.

  5. Measurement results of DIPIX pixel sensor developed in SOI technology

    NASA Astrophysics Data System (ADS)

    Ahmed, Mohammed Imran; Arai, Yasuo; Idzik, Marek; Kapusta, Piotr; Miyoshi, Toshinobu; Turala, Michal

    2013-08-01

    The development of integration type pixel detectors presents interest for physics communities because it brings optimization of design, simplicity of production-which means smaller cost, and reduction of detector material budget. During the last decade a lot of research and development activities took place in the field of CMOS Silicon-On-Insulator (SOI) technology resulting in improvement in wafer size, wafer resistivity and MIM capacitance. Several ideas have been tested successfully and are gradually entering into the application phase. Some of the novel concepts exploring SOI technology are pursued at KEK; several prototypes of dual mode integration type pixel (DIPIX) have been recently produced and described. This report presents initial test results of some of the prototypes including tests obtained with the infrared laser beams and Americium (Am-241) source. The Equivalent Noise Charge (ENC) of 86 e - has been measured. The measured performance demonstrates that SOI technology is a feasible choice for future applications.

  6. SOI technology for power management in automotive and industrial applications

    NASA Astrophysics Data System (ADS)

    Stork, Johannes M. C.; Hosey, George P.

    2017-02-01

    Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufacturers in the Power Management market. Recent advances in the automotive and industrial markets, along with emerging features, the increasing use of sensors, and the ever-expanding "Internet of Things" (IoT) are providing for continued growth in these markets while also driving more complex solutions. The potential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a single chip, saving space and cost, simplifying designs and models, and improving performance, thereby cutting development costs and improving time to market. SOI also offers novel new approaches to long-standing technologies.

  7. Rad-Hard Silicon Detectors

    NASA Astrophysics Data System (ADS)

    Giorgi, Marco

    2005-06-01

    For the next generation of High Energy Physics (HEP) Experiments silicon microstrip detectors working in harsh radiation environments with excellent performances are necessary. The irradiation causes bulk and surface damages that modify the electrical properties of the detector. Solutions like AC coupled strips, overhanging metal contact, <100> crystal lattice orientation, low resistivity n-bulk and Oxygenated substrate are studied for rad-hard detectors. The paper presents an outlook of these technologies.

  8. Monolithic pixel detectors with 0.2 μm FD-SOI pixel process technology

    NASA Astrophysics Data System (ADS)

    Miyoshi, Toshinobu; Arai, Yasuo; Chiba, Tadashi; Fujita, Yowichi; Hara, Kazuhiko; Honda, Shunsuke; Igarashi, Yasushi; Ikegami, Yoichi; Ikemoto, Yukiko; Kohriki, Takashi; Ohno, Morifumi; Ono, Yoshimasa; Shinoda, Naoyuki; Takeda, Ayaki; Tauchi, Kazuya; Tsuboyama, Toru; Tadokoro, Hirofumi; Unno, Yoshinobu; Yanagihara, Masashi

    2013-12-01

    Truly monolithic pixel detectors were fabricated with 0.2 μm SOI pixel process technology by collaborating with LAPIS Semiconductor Co., Ltd. for particle tracking experiment, X-ray imaging and medical applications. CMOS circuits were fabricated on a thin SOI layer and connected to diodes formed in the silicon handle wafer through the buried oxide layer. We can choose the handle wafer and therefore high-resistivity silicon is also available. Double SOI (D-SOI) wafers fabricated from Czochralski (CZ)-SOI wafers were newly obtained and successfully processed in 2012. The top SOI layers are used as electric circuits and the middle SOI layers used as a shield layer against the back-gate effect and cross-talk between sensors and CMOS circuits, and as an electrode to compensate for the total ionizing dose (TID) effect. In 2012, we developed two SOI detectors, INTPIX5 and INTPIX3g. A spatial resolution study was done with INTPIX5 and it showed excellent performance. The TID effect study with D-SOI INTPIX3g detectors was done and we confirmed improvement of TID tolerance in D-SOI sensors.

  9. Mongoose: Creation of a Rad-Hard MIPS R3000

    NASA Technical Reports Server (NTRS)

    Lincoln, Dan; Smith, Brian

    1993-01-01

    This paper describes the development of a 32 Bit, full MIPS R3000 code-compatible Rad-Hard CPU, code named Mongoose. Mongoose progressed from contract award, through the design cycle, to operational silicon in 12 months to meet a space mission for NASA. The goal was the creation of a fully static device capable of operation to the maximum Mil-883 derated speed, worst-case post-rad exposure with full operational integrity. This included consideration of features for functional enhancements relating to mission compatibility and removal of commercial practices not supported by Rad-Hard technology. 'Mongoose' developed from an evolution of LSI Logic's MIPS-I embedded processor, LR33000, code named Cobra, to its Rad-Hard 'equivalent', Mongoose. The term 'equivalent' is used to infer that the core of the processor is functionally identical, allowing the same use and optimizations of the MIPS-I Instruction Set software tool suite for compilation, software program trace, etc. This activity was started in September of 1991 under a contract from NASA-Goddard Space Flight Center (GSFC)-Flight Data Systems. The approach affected a teaming of NASA-GSFC for program development, LSI Logic for system and ASIC design coupled with the Rad-Hard process technology, and Harris (GASD) for Rad-Hard microprocessor design expertise. The program culminated with the generation of Rad-Hard Mongoose prototypes one year later.

  10. Mongoose: Creation of a Rad-Hard MIPS R3000

    NASA Technical Reports Server (NTRS)

    Lincoln, Dan; Smith, Brian

    1993-01-01

    This paper describes the development of a 32 Bit, full MIPS R3000 code-compatible Rad-Hard CPU, code named Mongoose. Mongoose progressed from contract award, through the design cycle, to operational silicon in 12 months to meet a space mission for NASA. The goal was the creation of a fully static device capable of operation to the maximum Mil-883 derated speed, worst-case post-rad exposure with full operational integrity. This included consideration of features for functional enhancements relating to mission compatibility and removal of commercial practices not supported by Rad-Hard technology. 'Mongoose' developed from an evolution of LSI Logic's MIPS-I embedded processor, LR33000, code named Cobra, to its Rad-Hard 'equivalent', Mongoose. The term 'equivalent' is used to infer that the core of the processor is functionally identical, allowing the same use and optimizations of the MIPS-I Instruction Set software tool suite for compilation, software program trace, etc. This activity was started in September of 1991 under a contract from NASA-Goddard Space Flight Center (GSFC)-Flight Data Systems. The approach affected a teaming of NASA-GSFC for program development, LSI Logic for system and ASIC design coupled with the Rad-Hard process technology, and Harris (GASD) for Rad-Hard microprocessor design expertise. The program culminated with the generation of Rad-Hard Mongoose prototypes one year later.

  11. RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers

    NASA Astrophysics Data System (ADS)

    Kazemi Esfeh, B.; Makovejev, S.; Basso, Didier; Desbonnets, Eric; Kilchytska, V.; Flandre, D.; Raskin, J.-P.

    2017-02-01

    In this work three different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard HR-SOI and two types of trap-rich high resistivity HR-SOI substrates named enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) provided by SOITEC are studied and compared. The DC and RF performances of these wafers are compared by means of passive and active devices such as coplanar waveguide (CPW) lines, crosstalk- and noise injection-structures as well as partially-depleted (PD) SOI MOSFETs. It is demonstrated that by employing enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) compared to HR-SOI wafer, a reduction of 24 dB is measured on both generations of trap-rich HR-SOI for 2nd harmonics. Furthermore, it is shown that in eSI HR-SOI, digital substrate noise is effectively reduced compared with HR-SOI. Purely capacitive behavior of eSI HR-SOI is demonstrated by crosstalk structure. Reduction of self-heating effect in the trap-rich HR-SOI with thinner BOX is finally studied.

  12. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

    NASA Astrophysics Data System (ADS)

    Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

    2016-01-01

    We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

  13. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    NASA Technical Reports Server (NTRS)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  14. Special Issue: Planar Fully-Depleted SOI technology

    NASA Astrophysics Data System (ADS)

    Allibert, F.; Hiramoto, T.; Nguyen, B. Y.

    2016-03-01

    We are in the era of mobile computing with smart handheld devices and remote data storage "in the cloud," with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer mobile and wearable markets. The Fully-Depleted SOI device/circuit is a unique option that can satisfy all these requirements and has made tremendous progress in development for various applications and adoption by foundries, integrated device manufacturers (IDM), and fabless companies in the last 3 years.

  15. Study of silicon-germanium junction formation for SOI based CMOS technology

    NASA Astrophysics Data System (ADS)

    Du, Yan

    Si1-xGex source/drain technology has been sucessfully applied to bulk metal oxide semiconductor field effect transistors (MOSFETs). Both channel mobility and source/drain contact resistivity are substantially improved with this technology. In this dissertation, Si1-xGex junction formation for silicon on insulator (SOI) based CMOS technology was investigated. Strain in epitaxially grown films on SOI films and silicon nanowires is studied using Raman spectroscopy and transmission electron microscope (TEM). For epitaxially grown Si1-xGe x film on SOI, there is lower degree of strain development in the SOI layer due to the rigid interface between the SOI and the burried oxide as compared to bulk. However, for silicon nanowires on oxide, the situation is different since nanowires serve as compliant substrates. Part of the strain energy is transferred to silicon nanowires. The consistency between synthesized Raman peak shifts and the experimental measurements verified the strain sharing between the epitaxially grown Si1-xGe x films and the silicon nanowires. Splittings of high order Laue zone line (HOLZ) from a convergent beam electron diffraction (CBED) pattern was quantified to study the strain distribution in epitaxial Si1- xGex films grown on silicon nanowires. It was found out in this study that elastic deformation of epitaxial Si 1-xGex at free surfaces leads to strain relaxation at these surfaces. This phenomenon is detrimental to strain engineering in a nanowire MOSFET and provides new challenges to develop smart designs for constraining strain in the nano-structures. Moreover, atomic layer deposition (ALD) Platinum is proposed for metal deposition on 3D epitaxial Si1-xGex source/drain. The uniform deposition around 3D Si1- xGex films effectively increases the contact surface area which is highly desired in the FinFET application.

  16. Development of a CMOS Oscillator Chain for Particle Detection based on SOI technology

    SciTech Connect

    Coulie-Castellani, K.; Ben Krit, S.; Rahajandraibe, W.; Aziza, H.; Portal, J-M.; Micolau, G.

    2015-07-01

    A new development of an oscillator concept, dedicated to the detection and tracking of particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a Voltage Controlled Oscillator (VCO) response. The very first solution was proposed using bulk technology. This new development is based on SOI technology what makes it tolerant to radiations. (authors)

  17. Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology

    NASA Technical Reports Server (NTRS)

    Ned, Alex; Kurtz, Anthony; Shang, Tonghuo; Goodman, Scott; Giemette. Gera (d)

    2013-01-01

    This work focused on developing, fabricating, and fully calibrating a flowangle probe for aeronautics research by utilizing the latest microelectromechanical systems (MEMS), leadless silicon on insulator (SOI) sensor technology. While the concept of angle probes is not new, traditional devices had been relatively large due to fabrication constraints; often too large to resolve flow structures necessary for modern aeropropulsion measurements such as inlet flow distortions and vortices, secondary flows, etc. Mea surements of this kind demanded a new approach to probe design to achieve sizes on the order of 0.1 in. (.3 mm) diameter or smaller, and capable of meeting demanding requirements for accuracy and ruggedness. This approach invoked the use of stateof- the-art processing techniques to install SOI sensor chips directly onto the probe body, thus eliminating redundancy in sensor packaging and probe installation that have historically forced larger probe size. This also facilitated a better thermal match between the chip and its mount, improving stability and accuracy. Further, the leadless sensor technology with which the SOI sensing element is fabricated allows direct mounting and electrical interconnecting of the sensor to the probe body. This leadless technology allowed a rugged wire-out approach that is performed at the sensor length scale, thus achieving substantial sensor size reductions. The technology is inherently capable of high-frequency and high-accuracy performance in high temperatures and harsh environments.

  18. Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

    NASA Technical Reports Server (NTRS)

    DeGregorio, Kelly; Wilson, Dale G.

    2009-01-01

    Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand

  19. Low thermal budget for Si and SiGe surface preparation for FD-SOI technology

    NASA Astrophysics Data System (ADS)

    Labrot, M.; Cheynis, F.; Barge, D.; Müller, P.; Juhel, M.

    2016-05-01

    Ultra thin Silicon films of Silicon-on-Insulator technology are metastable and thus cannot be submitted to high temperature treatments that may roughen or disrupt the film during the set of technological steps required for device fabrication. This paper concerns the development of an efficient low temperature cleaning process of Si and SiGe surfaces that enables a subsequent good-quality epitaxy of raised source and drain. For this purpose wet-clean, plasma-clean and several combinations of both are used. We thus propose two effective surface cleaning processes with low thermal budget optimized for FD-SOI technology.

  20. Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

    PubMed Central

    Malits, Maria; Nemirovsky, Yael

    2017-01-01

    This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. PMID:28758932

  1. Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

    PubMed

    Malits, Maria; Nemirovsky, Yael

    2017-07-29

    This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

  2. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  3. Performance Analysis of Si3N4 Capping Layer and SOI Technology in Sub 90 nm PMOS Device

    NASA Astrophysics Data System (ADS)

    Rahim, Noor Ashikin Binti Abdul; Abdullah, Mohd. Hanapiah B.; Rusop, Mohamad

    2009-06-01

    This technical paper investigates the electrical analysis in sub 90 nm of PMOS. The investigation was carried out by using two different methods which is PMOS with strained silicon and Silicon-on-Insulator (SOI) technology. Strained silicon engineering has become a key innovation to enhance device on current. Recently, SOI technology has been widely accepted for use in mainstream high performance logic applications due to some advantageous offered over the bulk silicon. The performance of the devices is analyzed by focusing on the electrical characteristics of Id-Vd and Id-Vg curves for three different structures. Firstly, PMOS with strained silicon of Si3N4 capping layer covering the gate area and secondly the device with and without SOI technology. The fabrication process simulation was simulated by using SILVACO TCAD ATHENA simulator and the electrical characteristic was simulated by SILVACO TCAD ATLAS simulator to obtain Id-Vd and Id-Vg curves. A fruitful and knowledgeable results were reported from this paper, it could be seen that high tensile strain introduced to the device causing the drain current to decreased from Id(bulk) = -400 uA/um of bulk to Id(Strain) = -310 uA/um which is about 25% of decrement. Since the drain current decreased, the carrier mobility and the performance also decreased proportional to drain current. However when SOI technology is applied to the PMOS device, the drain current was increased up to Id(SOI) = -431 uA/um over the bulk, the increment of about 9.25% reported. A higher Id-Vg curve and lower threshold of about pVth(SOI) = -0.2178 V also reported from this paper which tells that the device with SOI technology exhibits low power consumption device and fast switching which in turns contribute to a faster performance.

  4. Simulation study of a novel 3D SPAD pixel in an advanced FD-SOI technology

    NASA Astrophysics Data System (ADS)

    Vignetti, M. M.; Calmon, F.; Lesieur, P.; Savoy-Navarro, A.

    2017-02-01

    In this paper, a novel SPAD architecture implemented in a Fully-Depleted Silicon-On-Insulator (SOI) CMOS technology is presented. Thanks to its intrinsic vertical 3D structure, the proposed solution is expected to allow further scaling of the pixel size while ensuring high fill factors. Moreover the pixel and the detector electronics can benefit of the well-known advantages brought by SOI technology with respect to bulk CMOS, such as higher speed and lower power consumption. TCAD simulations based on realistic process parameters and dedicated post-processing analysis are carried out in order to optimize and validate the avalanche diode architecture for an optimal electric field distribution in the device but also to extract the main parameters of the SPAD, such as the breakdown voltage, the avalanche triggering probability, the dark count rate and the photon detection probability. A comparison between the efficiency in back-side and front-side approaches is carried out with a particular focus on time-of-flight applications.

  5. Characterization of high resolution CMOS monolithic active pixel detector in SOI technology

    NASA Astrophysics Data System (ADS)

    Ahmed, M. I.; Arai, Y.; Glab, S.; Idzik, M.; Kapusta, P.; Miyoshi, T.; Takeda, A.; Turala, M.

    2015-05-01

    Novel CMOS monolithic pixel detectors designed at KEK and fabricated at Lapis Semiconductor in 0.2 μm Silicon-on-Insulator (SOI) technology are presented. A thin layer of silicon oxide separates high and low resistivity silicon layers, allowing for optimization of design of detector and readout parts. Shallow wells buried under the oxide in the detector part screen the entire pixel electronics from electrical field applied to the detector. Several integration type SOI pixel detectors have been developed with pixel sizes 8-20 μm. The general features of 14 × 14 μm2 detectors designed on different wafers (CZ-n, FZ-n and FZ-p) were measured and compared. The detector performance was studied under irradiation with visible and infra-red laser, and also X-ray ionizing source. Using X-rays from an Am-241 source the noise of readout electronics was measured at different working conditions, showing the ENC in the range of 88-120 e-. The pixel current was calculated from average DC pedestal shift while varying the pixel integration time. The operation of the detector was studied under partial and full depletion conditions. The effects of temperature and detector bias voltage on noise and leakage current were studied. Characteristics of an ADC integrated in the front-end chip are also presented.

  6. Development of a pixel sensor with fine space-time resolution based on SOI technology for the ILC vertex detector

    NASA Astrophysics Data System (ADS)

    Ono, Shun; Togawa, Manabu; Tsuji, Ryoji; Mori, Teppei; Yamada, Miho; Arai, Yasuo; Tsuboyama, Toru; Hanagaki, Kazunori

    2017-02-01

    We have been developing a new monolithic pixel sensor with silicon-on-insulator (SOI) technology for the International Linear Collider (ILC) vertex detector system. The SOI monolithic pixel detector is realized using standard CMOS circuits fabricated on a fully depleted sensor layer. The new SOI sensor SOFIST can store both the position and timing information of charged particles in each 20×20 μm2 pixel. The position resolution is further improved by the position weighted with the charges spread to multiple pixels. The pixel also records the hit timing with an embedded time-stamp circuit. The sensor chip has column-parallel analog-to-digital conversion (ADC) circuits and zero-suppression logic for high-speed data readout. We are designing and evaluating some prototype sensor chips for optimizing and minimizing the pixel circuit.

  7. Cost-effective mask-sharing technology for SOI LIGBT and PLDMOS

    NASA Astrophysics Data System (ADS)

    Huang, Yong; Qiao, Ming; Zhou, Xin; Liang, Tao; Li, Yang; Li, Zhaoji; Zhang, Bo

    2016-04-01

    Cost-effective mask-sharing technology for the 200 V silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) and p-channel lateral double-diffused MOS (PLDMOS) are proposed in this paper. N-well and P-body implantations are shared as an N-buffer implantation of the LIGBT and P-buffer implantation of the PLDMOS, respectively, which reduces two masks compared with the conventional process. The structure and process parameters for LIGBT and PLDMOS with the new process are optimized by simulation to achieve good performance. The experimental results indicate that the LIGBT and PLDMOS using the new process maintain the same performance compared to the conventional devices.

  8. Hardening CMOS imagers: radhard-by-design or radhard-by-foundry

    NASA Astrophysics Data System (ADS)

    Pain, Bedabrata; Hancock, Bruce R.; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao; Pedadda, Pavani; Wrigley, Christopher J.; Stirbl, Robert C.

    2004-01-01

    A comparative study between radhard-by-design and radhard-by-foundry approaches for radiation hardening of CMOS imagers is presented. Main mechanisms for performance degradation in CMOS imagers in a radiation environment are identified, and key differences between the radiation effects in CMOS imagers and that in digital logic circuits are explained. Design methodologies for implementation of CMOS imagers operating in a radiation environment are presented. By summarizing the performance results obtained from imagers implemented in both radhard-by-design and radhard-by-foundry approaches, the advantages and shortcomings of both approaches are identified. It is shown that neither approach presents an optimum solution. The paper concludes by discussing an alternate pathway to overcome these limitations and enable the next-generation high-performance radiation-hard CMOS imagers.

  9. Mode-converter and multiplexer based on SOI technology for few-mode fiber at 1550 nm

    NASA Astrophysics Data System (ADS)

    Garcia-Rodriguez, David; Corral, Juan L.; Griol, Amadeu; Llorente, Roberto

    2017-01-01

    The Asymmetric Directional Coupler (ADC) based on SOI (Silicon-on-Insulator) technology converts and couples the fundamental mode to the first higher order mode. The ADC is designed to achieve phase-matching condition, which is accomplished when both propagation constants are equal in each waveguide arm. Devices are fabricated in a SOI wafer with a 220 nm thick silicon layer. The refractive indexes of Si and SiO2 are nSi=3.47 and nSi02=1.46 respectively. The access waveguides (W1=0.45 μm) have been designed to propagate just the fundamental mode, TE0. The optimum width for the second waveguide was chosen to achieve the phase-matching condition for the TE1 mode, which corresponds to W2=0.962 μm. The coupling to the input and output waveguides is achieved through grating couplers. The input grating coupler will need to couple the LP01 mode from the SSMF (Standard Single-Mode Fiber) to the TE0 mode in the SOI waveguide; thus a typical design for a SOI coupler can be used. However, the output coupler must simultaneously couple the TE0 and TE1 modes in the SOI wide waveguide to the LP01 and LP11 modes in the FMF (Few-Mode Fiber). Input gratings are designed to have an area of 12x12 μm2 and a period of Λ=610 nm in order to maximize the optical power coupled between the fiber and the waveguide for an incident angle of 10 degrees. Output gratings are designed with the same period but distinct area (12.5x12.5 μm2) to correctly couple the LP01 and LP11 modes in the FMF.

  10. Study of millisecond laser annealing on ion implanted soi and application to scaled finfet technology

    NASA Astrophysics Data System (ADS)

    Michalak, Tyler J.

    The fabrication of metal-oxide-semiconductor field effect transistors (MOSFET) requires the engineering of low resistance, low leakage, and extremely precise p-n junctions. The introduction of finFET technology has introduced new challenges for traditional ion implantation and annealing techniques in junction design as the fin widths continue to decrease for improved short channel control. This work investigates the use of millisecond scanning laser annealing in the formation of n-type source/drain junctions in next generation MOSFET. We present a model to approximate the true thermal profile for a commercial laser annealing process which allows us to represent more precisely specific thermal steps using Technology Computer Aided Design (TCAD). Sheet resistance and Hall Effect measurements for blanket films are used to correlate dopant activation and mobility with the regrowth process during laser anneal. We show the onset of high conductivity associated with completion of solid phase epitaxial regrowth (SPER) in the films. The Lattice Kinetic Monte Carlo (LKMC) model shows excellent agreement with cross section transmission electron microscopy (TEM), correlating the increase of conductivity with completion of crystal regrowth, increased activation, and crystal quality at various temperatures. As scaled devices move into the non-planar geometries and possibly adopt silicon-on-insulator (SOI) substrates, the crystal regrowth and dopant activation of amorphizing implants becomes more complicated and doping methods must adapt accordingly. Following the concept of the more recently proposed hot ion implantation and the benefits of laser anneal, we investigate a possible process flow for a 10/14 nm node SOI finFET by utilizing process and device TCAD. Device simulation parameters for the 10/14 nm node device are taken from a calibrated model based on fabricated non-planar 40 nm gate length device finFET. The implications on device performance are considered for the

  11. Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

    NASA Astrophysics Data System (ADS)

    Kho Ching Tee, Elizabeth; Antoniou, Marina; Udrea, Florin; Hoelke, Alexander; Ng, Liang Yew; Bin Wan Zainal Abidin, Wan Azlan; Pilkington, Steven John; Pal, Deb Kumar

    2014-06-01

    Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given.

  12. Single-Event Transient Characterization of a Radiation-Tolerant Charge-Pump Phase-Locked Loop Fabricated in 130 nm PD-SOI Technology

    NASA Astrophysics Data System (ADS)

    Chen, Zhuojun; Lin, Min; Zheng, Yunlong; Wei, Zuodong; Huang, Shuigen; Zou, Shichang

    2016-08-01

    In this paper, a radiation-tolerant phase-locked loop (PLL) is designed and fabricated with 130 nm PD-SOI technology. A current-based charge pump is hardened using a current compensation technique in combination with the differential charge cancellation (DCC) layout of the complementary switches. Besides, the stacked SOI transistors are employed to mitigate single-event effects of the voltage-controlled oscillator. The experimental results show that the proposed PLL has no significant jitter variations under heavy-ion experiments, compared with TMR-hardened PLL. Besides, pulsed-laser testing comprehensively characterizes the single-event transients of the PLL and demonstrates its radiation tolerant performance.

  13. Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

    NASA Astrophysics Data System (ADS)

    Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

    2017-02-01

    We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

  14. Synchrotron beam test of a photon counting pixel prototype based on Double-SOI technology

    NASA Astrophysics Data System (ADS)

    Zhou, Y.; Lu, Y.; Hashimoto, R.; Nishimura, R.; Kishimoto, S.; Arai, Y.; Ouyang, Q.

    2017-01-01

    The overall noise performances and first synchrotron beam measurement results of CPIXETEG3b, the first counting type Silicon-On-Insulator (SOI) pixel sensor prototype without crosstalk issue, are reported. The prototype includes a 64 × 64 pixel matrix with 50 μm pitch size. Each pixel consists of an N-in-P charge collection diode, a charge sensitive preamplifier, a shaper, a discriminator with thresholds adjustable by an in-pixel 4-bit DAC, and a 6-bit counter. The study was performed using the beam line 14A at KEK Photon Factory (KEK-PF) . The homogeneous response of the prototype, including charging-sharing effects between pixels were studied. 16 keV and 8 keV monochromatic small size (~ 10 μm diameter) X-ray beams were used for the charge sharing study, and a flat-field was added for homogenous response investigation. The overall detector homogeneity and the influence of basic detector parameters on charge sharing between pixels has been investigated.

  15. Sensors and actuators based on SOI materials

    NASA Astrophysics Data System (ADS)

    Sanz-Velasco, Anke; Nafari, Alexandra; Rödjegård, Henrik; Bring, Martin; Hedsten, Karin; Enoksson, Peter; Bengtsson, Stefan

    2006-05-01

    Examples of using SOI materials for formation of novel sensor and actuator structures at Chalmers University of Technology are given. Using SOI material gives advantages in formation of sensor and actuator structures, such as a nanoindentation force sensor, a three-axis accelerometer, a miniaturized pinball game and integration of diffractive optical elements onto silicon.

  16. Low power wide spectrum optical transmitter using avalanche mode LEDs in SOI CMOS technology.

    PubMed

    Agarwal, Vishal; Dutta, Satadal; Annema, Anne-Johan; Hueting, Raymond J E; Steeneken, Peter G; Nauta, Bram

    2017-07-24

    This paper presents a low power monolithically integrated optical transmitter with avalanche mode light emitting diodes in a 140 nm silicon-on-insulator CMOS technology. Avalanche mode LEDs in silicon exhibit wide-spectrum electroluminescence (400 nm < λ < 850 nm), which has a significant overlap with the responsivity of silicon photodiodes. This enables monolithic CMOS integration of optocouplers, for e.g. smart power applications requiring high data rate communication with a large galvanic isolation. To ensure a certain minimum number of photons per data pulse (or per bit), light emitting diode drivers must be robust against process, operating conditions and temperature variations of the light emitting diode. Combined with the avalanche mode light emitting diode's steep current-voltage curve at relatively high breakdown voltages, this conventionally results in high power consumption and significant heating. The presented transmitter circuit is intrinsically robust against these issues, thereby enabling low power operation.

  17. Implementation of a Readout Circuit on SOI Technology for the Signal Conditioning of a Neutron Detector in Harsh Environment

    SciTech Connect

    Ben Krit, S.; Coulie-Castellani, K.; Rahajandraibe, W.; Micolau, G.; Lyoussi, A.

    2015-07-01

    A transistor level implementation of the analog block of a readout system on SOI process is presented here. This system is dedicated to the signal conditioning of a neutron detector in harsh environment. The different parts of the readout circuits are defined. The harsh environment constraints (crossing particle effect, high temperatures) are also detailed and modeled in the circuit in order to test and evaluate the characteristics of the designed block when working under these conditions. (authors)

  18. ST Rad-Hard Power Bipolar Transistors Product Portfolio

    NASA Astrophysics Data System (ADS)

    Camonita, Giuseppe; Pintacuda, Francesco

    2011-10-01

    This article describes the STMicroelectronics Rad-Hard Bipolar Transistors product range addressed specifically for space applications. Available up to 100krad Total Ionized Dose radiation level at LDRS (Low Dose Rate Sensitivity) conditions, they are qualified according to the ESCC specifications. Here follows the main features, the characterization curves including static and dynamic behaviours, and the radiation performances for some products. Also some application examples are given.

  19. Development of Radhard VLSI electronics for SSC calorimeters

    SciTech Connect

    Dawson, J.W.; Nodulman, L.J.

    1989-01-01

    A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs.

  20. Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies

    SciTech Connect

    Brothers, C.; Pugh, R.; Duggan, P.; Chavez, J.; Schepis, D.; Yee, D.; Wu, S.

    1997-12-01

    Total-dose and single-event-effect radiation characterization of 0.25 micron test macro SRAMs fabricated at IBM`s East Fishkill research foundry in unhardened bulk and unhardened partially-depleted SOI silicon, are reported. The design and fabrication process were optimized for high-performance and short access time using supply voltages of 2.5v for the 64K-bit and 1.8v for the 144K and 288K-bit test macro SRAMs.

  1. Reliability challenge of ESD protection: From planner SOI MOSFET to SOI FinFET

    NASA Astrophysics Data System (ADS)

    Jiang, Yibo; Bi, Hui; Dong, Liangwei; Li, Qinglong

    2017-07-01

    Implementation of Electrostatic Discharge (ESD) protection in Silicon on Insulator (SOI) technology is a challenge because of the inherent properties of poor heat conductor and heat trapping. In this paper, a novel device as ESD clamp is proposed as Fix-Base SOI FinFET clamp which addresses the troublesome problem of floating base. Moreover, its manufacturing process is compatible to the normal SOI process flow well. Finally, a detailed discussion including current density and thermal distribution are presented with the technique of 3D TCAD simulation.

  2. A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

    NASA Astrophysics Data System (ADS)

    Yan-Hui, Zhang; Jie, Wei; Chao, Yin; Qiao, Tan; Jian-Ping, Liu; Peng-Cheng, Li; Xiao-Rong, Luo

    2016-02-01

    A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

  3. RC64, a Rad-Hard Many-Core High-Performance DSP for Space Applications

    NASA Astrophysics Data System (ADS)

    Ginosar, Ran; Aviely, Peleg; Liran, Tuvia; Alon, Dov; Mandler, Alberto; Lange, Fredy; Dobkin, Reuven; Goldberg, Miki

    2014-08-01

    RC64, a novel rad-hard 64-core signal processing chip targets DSP performance of 75 GMACs (16bit), 150 GOPS and 20 single precision GFLOPS while dissipating less than 10 Watts. RC64 integrates advanced DSP cores with a multi-bank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 2.5 Gbps full duplex high speed serial links using SpaceFibre and other protocols. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 300 MHz integrated circuit on a 65nm CMOS technology, assembled in hermetically sealed ceramic CCGA624 package and qualified to the highest space standards.

  4. RC64, a Rad-Hard Many-Core High- Performance DSP for Space Applications

    NASA Astrophysics Data System (ADS)

    Ginosar, Ran; Aviely, Peleg; Gellis, Hagay; Liran, Tuvia; Israeli, Tsvika; Nesher, Roy; Lange, Fredy; Dobkin, Reuven; Meirov, Henri; Reznik, Dror

    2015-09-01

    RC64, a novel rad-hard 64-core signal processing chip targets DSP performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. RC64 integrates advanced DSP cores with a multi-bank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 3.125 Gbps full duplex high speed serial links using SpaceFibre and other protocols. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 300 MHz integrated circuit on a 65nm CMOS technology, assembled in hermetically sealed ceramic CCGA624 package and qualified to the highest space standards.

  5. BUSFET - A Novel Radiation-Hardened SOI Transistor

    SciTech Connect

    Dodd, P.E.; Draper, B.L.; Schwank, J.R.; Shaneyfelt, M.R.

    1999-02-04

    A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology.

  6. SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

    NASA Astrophysics Data System (ADS)

    Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

    2010-02-01

    To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

  7. A 60 GOPS/W, -1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

    NASA Astrophysics Data System (ADS)

    Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca

    2016-03-01

    Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from -1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range -40 °C to 120 °C exploiting -1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors

  8. Implementaton of SOIS in TASTE

    NASA Astrophysics Data System (ADS)

    Delange, Julien; Torelli, Felice; Terraillon, Jean-Loup

    2012-08-01

    The design and implementation of space software needs to be rigorous: as mission- or life-critical systems, they must be designed without error. For that purpose, developers have to use methods, tools and libraries that provide guidance during the production process. In addition, to ease software reuse through different projects, reduce development costs and avoid revalidation of software that provides the same functions, reference on-board software architecture are defined, and standardized interfaces are introduced. They define interaction methods between system components, either software or hardware. The past years have also shown the emerging need to abstract system specifications using models, also at software or hardware level. This consists in capturing system architecture with its requirements using specific tools that automatically check their correctness and produce implementation to be deployed on the target.Therefore, the reference architecture and system interfaces must be consistent with development tools. The code generator must generates the right calls to the standardized interface. In the case of communication interface, the communication services can be implemented either in a hidden way within the generated code, or as explicit design patterns of the application software model. Thus, integrating existing standards into the reference architecture is still under investigation and different integration scenarios could be envisioned and so, need to be evaluated.In this paper, we explain the mapping of the CCSDS standardized communication interface (the Spacecraft Onboard Interface Service, SOIS) into an established modelling technology (TASTE). We detail SOIS integration into models so that engineers can directly use them from modelling tool that automatically calls appropriate procedure when generating the implementation. We also assess the meaning of being "SOIS compliant" with the example of TASTE.

  9. Atmel's New Rad-Hard Sparc V8 Processor 200Mhz & Low Power System on Chip

    NASA Astrophysics Data System (ADS)

    Ganry, Nicolas; Mantelet, Guy; Parkes, Steve; McClements, Chris

    2014-08-01

    The AT6981 is a new generation of processor designed for critical spaceflight applications, which combines a high-performance SPARC® V8 radiation hard processor, with enough on-chip memory for many aerospace applications and state-of-the-art SpaceWire networking technology from STAR- Dundee. The AT6981 is implemented in Atmel 90nm rad-hard technology, enabling 200 MHz operating speed for the processor with power consumption levels around 1W. This advanced technology allows strong system integration in a SoC with embedded peripherals like CAN, 1553, Ethernet, DDR and embedded memory with 1Mbytes SRAM. The device is ITAR- free and is developed in France by Atmel Aerospace having more than of 30years space experience. This paper describes this new SoC architecture and technical options considered to insure the best performances, the minimum power consumption and high reliability. This device will be available on the market in H2 2014 for evaluation with first flight models targeted end 2015.

  10. A fully differential OTA with dynamic offset cancellation in 28nm FD-SOI process

    NASA Astrophysics Data System (ADS)

    Jaworski, Zbigniew

    2016-12-01

    This papers presents a classic fully differential operational transconductance amplifier (FDOTA) implemented in industrial 28 nm FD-SOI (Fully-Depleted SOI) technology. A novel approach to minimized the FDOTA offset voltage is proposed. The solution employs the unique feature of FD-SOI technology - back-gate biasing - combined with modern compensation methodology. The proposed method results in considerable design overhead. However, this offset cancellation approach is very effective and allows to improve FDOTA performance when classic techniques reach their limits.

  11. Isolated Islands by Selective Local Oxidation (islo): a Silicon-On (soi) Technology for Nanoelectronic and Nanoelectromechanical Applications.

    NASA Astrophysics Data System (ADS)

    Arney, Susanne Christine

    The development of an advanced fully-integrated nanometer-scale isolation technology called the Isolated Islands of Substrate-Silicon by Selective Lateral Oxidation (ISLO) technology is reported. The versatility and applicability of the ISLO technology for diverse nanoelectronic and nanoelectromechanical devices and systems are described relative to the challenging issues of isolation and contacts. The basic ISLO structure is fabricated using electron beam lithography and standard VLSI reactive ion etching and oxidation processes. Single crystal silicon (SCS) islands 100-300-nm-wide, and 500 -2000-nm-tall are electrically and thermally isolated from the underlying substrate by selective lateral thermal oxidation at the base of the islands. Dislocation-free fully-isolated islands are obtained. Full-isolation of the basic ISLO structure depends on island linewidth, oxidation-masking film thicknesses, recess etch profile, and oxidation time and temperature. The extended ISLO technology provides 100-nm-wide, movable, suspended, high stiffness, low mass, SCS or SCS-dielectric-composite beam segments with integrated electrical contacts and metallization for high frequency (5-10 MHz) nanodynamic applications. Fixed or cantilevered beam segments are isolated from the underlying substrate -silicon by thermally grown oxide or an air-bridge. Wedge -pairs or tip-pairs vertically opposed across the isolation oxide or air-bridge have application to electron tunneling or field emission devices. A selectively-sharpened tip -above-a-tip structure is formed at the intersection of cantilevered beam segments. Vertical triple-tip and quadruple -tip structures are demonstrated. A new deep-submicron self-aligned sidewall source/drain, top-surface gate Thin -Film-Silicon-On-Insulator (TFSOI) MOSFET (ISLO FET) based on the inherently three-dimensional, non-planar ISLO structure is presented. Stress-related defect generation and dopant segregation during the oxidation, erosion of the high

  12. Testing Concepts of Advanced Rad-Hard SoC

    NASA Astrophysics Data System (ADS)

    Liran, Tuvia; Ginosar, Ran; Dobkin, Reuven; Alon, Dov

    2012-08-01

    Advanced System on Chip (SoC) devices for space applications require very high reliability and quality, while maintaining high performance. They require high integration level, high speed, and immunity to all radiation effects. Protecting against soft errors leads to an increased number of memory bits, increased gate count and die size and higher power. On top of that, the need for high quality by high test coverage requires special testability features like SCAN, and extensive memory access.The use of Iddq testing provides significant improvement of test coverage, forcing some design restrictions. It provides additional test coverage, beyond the coverage of conventional tests and without stressing the devices. The production test includes also high voltage stress (HVS) procedure that stresses some of the failure mechanisms. By comparing Iddq before and after the HVS, it is possible to detect degradation at early stage, even before the functional failure has developed, which makes it efficient screening method.The methodology for covering almost all failure mechanisms in the SRAMs is based on internal testability features and on test patterns based on MARCH-C algorithm.The key concepts employed for testing of some rad-hard space SoC devices are described in this paper.

  13. SOI-CMOS-MEMS electrothermal micromirror arrays

    NASA Astrophysics Data System (ADS)

    Gilgunn, Peter J.

    A fabrication technology called SOI-CMOS-MEMS is developed to realize arrays of electrothermally actuated micromirror arrays with fill factors up to 90% and mechanical scan ranges up to +/-45°. SOI-CMOS-MEMS features bonding of a CMOS-MEMS folded electrothermal actuator chip with a SOI mirror chip. Actuators and micromirrors are separately released using Bosch-type and isotropic Si etch processes. A 1-D, 3 x 3 SOI-CMOS-MEMS mirror array is characterized at a 1 mm scale that meets fill factor and scan range targets with a power sensitivity of 1.9 deg·m W-1 and -0.9 deg·m W-1 on inner and outer actuator legs, respectively. Issues preventing fabrication of SOI-CMOS-MEMS micromirror arrays designed for 1-D and 3-D motion at scales from 500 microm to 50 microm are discussed. Electrothermomechanical analytic models of power response of a generic folded actuator topology are developed that provide insight into the trends in actuator behavior for actuator design elements such as beam geometry and heater type, among others. Adverse power and scan range scaling and favorable speed scaling are demonstrated. Mechanical constraints on device geometry are derived. Detailed material, process, test structure and device characterization is presented that demonstrates the consistency of measured device behavior with analytic models. A unified model for aspect ratio dependent etch modulation is developed that achieves depth prediction accuracy of better than 10% up to 160 microm depth over a range of feature shapes and dimensions. The technique is applied extensively in the SOI-CMOS-MEMS process to produce deep multi-level structures in Si with a single etch mask and to control uniformity and feature profiles. TiW attack during release etch is shown to be the driving factor in mirror coplanarity loss. The effect is due to thermally accelerated etching caused by heating of released structures by the exothermic reaction of Si and F. The effect is quantified using in situ infrared

  14. Test results of a counting type SOI device for a new x-ray area detector

    SciTech Connect

    Hashimoto, R. Igarashi, N.; Kumai, R.; Kishimoto, S.; Arai, Y.; Miyoshi, T.

    2016-07-27

    Development of a new detector using Silicon-On-Insulator (SOI) technology has been started in the Photon Factory, KEK. The aim of this project is to develop a pulse-counting-type X-ray detector that can be used in synchrotron radiation experiments using soft X-rays. We started to make a Test Element Group of SOI chip, which is called CPIXPTEG1 and evaluated its performance. We succeeded in readout of output signals for 16 keV X-rays from the SOI chips. We also found that the middle-SOI structure was effective against a signal distortion caused by hole traps in the buried oxide layer.

  15. SOI Hall cells design selection using three-dimensional physical simulations

    NASA Astrophysics Data System (ADS)

    Paun, Maria-Alexandra; Udrea, Florin

    2014-12-01

    The main characteristics of Hall Effect Sensors, based on “silicon-on-insulator” (SOI) structure in the ideal design features, are evaluated by performing three-dimensional physical simulations. A particular Hall shape reproducing an XFAB SOI XI10 integration process is analyzed in details. In order to assess the performance of the considered Hall cell, the Hall voltage, absolute sensitivity and input resistance were extracted through simulations. Electrostatic potential distribution and Hall mobility were also produced through simulations for the considered SOI Hall Basic cell. A comparison between the performance of the same Hall cell manufactured in regular bulk and SOI CMOS technology respectively is given.

  16. Characteristics of non-irradiated and irradiated double SOI integration type pixel sensor

    NASA Astrophysics Data System (ADS)

    Asano, M.; Sekigawa, D.; Hara, K.; Aoyagi, W.; Honda, S.; Tobita, N.; Arai, Y.; Miyoshi, T.; Kurachi, I.; Tsuboyama, T.; Yamada, M.

    2016-09-01

    We are developing monolithic pixel sensors based on a 0.2 μm fully depleted silicon-on-insulator (FD-SOI) technology for high-energy physics experiment applications. With this SOI technology, the wafer resistivities for the electronics and sensor parts can be chosen separately. Therefore, a device with full depletion and fast charge collection is realized. The total ionizing dose (TID) effect is the major challenge for application in hard radiation environments. To compensate for TID damage, we introduced a double SOI structure that implements an additional middle silicon layer (SOI2 layer). Applying a negative voltage to the SOI2 layer should compensate for the effects induced by holes trapped in the buried oxide layers. We studied the recovery from TID damage induced by 60Co γ and other characteristics of the integration-type double SOI sensor INTPIXh2. When the double SOI sensor was irradiated to 100 kGy, it showed a response to the infrared laser similar to that of a non-irradiated sensor when we applied a negative voltage to the SOI2 layer. Thus, we concluded that the double SOI sensor is very effective at sufficiently enhancing the radiation hardness for application in experiments with harsh radiation environments, such as at Belle II or ILC.

  17. A low-noise wide-dynamic-range event-driven detector using SOI pixel technology for high-energy particle imaging

    NASA Astrophysics Data System (ADS)

    Shrestha, Sumeet; Kamehama, Hiroki; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

    2015-08-01

    This paper presents a low-noise wide-dynamic-range pixel design for a high-energy particle detector in astronomical applications. A silicon on insulator (SOI) based detector is used for the detection of wide energy range of high energy particles (mainly for X-ray). The sensor has a thin layer of SOI CMOS readout circuitry and a thick layer of high-resistivity detector vertically stacked in a single chip. Pixel circuits are divided into two parts; signal sensing circuit and event detection circuit. The event detection circuit consisting of a comparator and logic circuits which detect the incidence of high energy particle categorizes the incident photon it into two energy groups using an appropriate energy threshold and generate a two-bit code for an event and energy level. The code for energy level is then used for selection of the gain of the in-pixel amplifier for the detected signal, providing a function of high-dynamic-range signal measurement. The two-bit code for the event and energy level is scanned in the event scanning block and the signals from the hit pixels only are read out. The variable-gain in-pixel amplifier uses a continuous integrator and integration-time control for the variable gain. The proposed design allows the small signal detection and wide dynamic range due to the adaptive gain technique and capability of correlated double sampling (CDS) technique of kTC noise canceling of the charge detector.

  18. Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

    NASA Astrophysics Data System (ADS)

    Tong, Q.-Y.; Gösele, U.

    1993-07-01

    Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.

  19. Nonclassical devices in SOI: Genuine or copyright from III V

    NASA Astrophysics Data System (ADS)

    Luryi, S.; Zaslavsky, A.

    2007-02-01

    The combination of semiconductor-on-insulator (SOI) substrates with ultrathin Si (or Ge) channel and gate insulator layers opens new opportunities for nonclassical CMOS-compatible devices and possibly optical sources. Unlike their III-V counterparts, which often came first, SOI-based devices have the crucial advantage of potential integrability with dominant silicon technology. We discuss the examples of lateral and vertical tunneling transistors, as well as a tunneling-based SOI intersubband laser. None of these devices has progressed beyond either proof-of-concept demonstrations or, in the case of the intersubband laser, a purely theoretical concept. Still, the unique characteristics deriving from quantum mechanical tunneling make such devices an interesting playground for innovative device research, especially as standard Si CMOS heads towards the rapidly approaching end of scaling.

  20. BUSFET - A Novel Radiation-Hardened SOI Transistor

    SciTech Connect

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-07-20

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10{sup 18} cm{sup {minus}3} and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10{sup 17} cm{sup {minus}3}, a thicker silicon film (300 nm) must be used.

  1. Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements

    NASA Astrophysics Data System (ADS)

    Kazemi Esfeh, B.; Kilchytska, V.; Barral, V.; Planes, N.; Haond, M.; Flandre, D.; Raskin, J.-P.

    2016-03-01

    This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD-SOI) planar ultra-thin body and BOX (UTBB) MOSFETs for high frequency applications. All parasitic elements such as the parasitic gate and source/drain series resistances, total capacitances are extracted and their effects on RF performance are analyzed and compared with previous work on similar devices. Two main RF figures of merit (FoM) such as the current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are determined. It is shown that fT of ∼280 GHz and fmax of ∼250 GHz are achievable in the shortest devices. Based on the extracted parameters, the validation of the small-signal equivalent circuit used for modeling UTBB MOSFETs is investigated by comparing simulated and measured S-parameters.

  2. SOIS and Software Reference Architecture

    NASA Astrophysics Data System (ADS)

    Torelli, Felice; Taylor, Chris; Viana Sanchez, Aitor; Mendham, Peter; Fowell, Stuart

    2011-08-01

    In the recent years ESA, in conjunction with the European space industry, has supported a number of initiatives aimed at increasing the level of standardisation in the elements composing a spacecraft avionics system. This is an ongoing process with many contributors including SAVOIR, SAVOIR-FAIRE1, CCSDS SOIS and the ECSS protocol standardisation activities. The SOIS service framework and the accompanying ECSS protocols play a key role in the evolution of flight avionics as, on the one side they standardise the external hardware interfaces required for interconnection and on the other standardise the communication services seen by applications. Much still remains to be done, in particular, the communications based services defined by SOIS must be incorporated into a standard software architecture such that real implementations can take benefit from the standards. Aspects such as the use of Electronic Data Sheets2 need to be evaluated, as does the use of plug and play concepts. This paper will present the latest evolution of the SOIS architecture and related CCSDS recommendations including the relationship and status of the software reference architecture being developed under SAVOIR-FAIRE. The potential impacts on the design of a system adopting the standardised services will also be discussed in three main areas: communication with external equipments, abstraction of sensors & actuators and software bus.

  3. A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

    NASA Astrophysics Data System (ADS)

    Hemperek, Tomasz; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert

    2015-10-01

    An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

  4. Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

    NASA Astrophysics Data System (ADS)

    Lin, Chiung-Wen; Yang, Hsueh-An; Wang, Wei Chung; Fang, Weileun

    2007-06-01

    Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.

  5. MEMS Using SOI Substrate

    NASA Technical Reports Server (NTRS)

    Tang, Tony K.

    1999-01-01

    At NASA, the focus for smaller, less costly missions has given impetus for the development of microspacecraft. MicroElectroMechanical System (MEMS) technology advances in the area of sensor, propulsion systems, and instruments, make the notion of a specialized microspacecraft feasible in the immediate future. Similar to the micro-electronics revolution,the emerging MEMS technology offers the integration of recent advances in micromachining and nanofabrication techniques with microelectronics in a mass-producible format,is viewed as the next step in device and instrument miniaturization. MEMS technology offers the potential of enabling or enhancing NASA missions in a variety of ways. This new technology allows the miniaturization of components and systems, where the primary benefit is a reduction in size, mass and power. MEMS technology also provides new capabilities and enhanced performance, where the most significant impact is in performance, regardless of system size. Finally,with the availability of mass-produced, miniature MEMS instrumentation comes the opportunity to rethink our fundamental measurement paradigms. It is now possible to expand our horizons from a single instrument perspective to one involving multi-node distributed systems. In the distributed systems and missions, a new system in which the functionality is enabled through a multiplicity of elements. Further in the future, the integration of electronics, photonics, and micromechanical functionalities into "instruments-on-a-chip" will provide the ultimate size, cost, function, and performance advantage. In this presentation, I will discuss recent development, requirement, and applications of various MEMS technologies and devices for space applications.

  6. FinFET and UTBB for RF SOI communication systems

    NASA Astrophysics Data System (ADS)

    Raskin, Jean-Pierre

    2016-11-01

    Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

  7. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    DOEpatents

    Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  8. New RAD-Hard STRH3260L6 Bipolar And STRH100N10 Mosfet Power Transistors

    NASA Astrophysics Data System (ADS)

    Camonita, Giuseppe; Pintacuda, Francesco

    2011-10-01

    This article describes two new power discrete components from STMicroelectronics, specifically offered for Space applications. The STRH3260L6 is a double bipolar rad-hard transistor in an SMD package that houses two complementary devices, one NPN and one PNP. The STRH100N10 is an N-channel rad-hard power MOSFET, the first that is ESCC qualified and available in Europe without procurement restrictions. The purpose of this writing is to give details about the devices' main features, characterization for static, dynamic and radiation performances.

  9. First results of a Double-SOI pixel chip for X-ray imaging

    NASA Astrophysics Data System (ADS)

    Lu, Yunpeng; Ouyang, Qun; Arai, Yasuo; Liu, Yi; Wu, Zhigang; Zhou, Yang

    2016-09-01

    Aiming at low energy X-ray imaging, a prototype chip based on Double-SOI process was designed and tested. The sensor and pixel circuit were characterized. The long lasting crosstalk issue in SOI technology was understood. The operation of pixel was verified with a pulsed infrared laser beam. The depletion of sensor revealed by signal amplitudes is consistent with the one revealed by I-V curve. An s-curve fitting resulted in a sigma of 153 e- among which equivalent noise charge (ENC) contributed 113 e-. It's the first time that the crosstalk issue in SOI technology was solved and a counting type SOI pixel demonstrated the detection of low energy radiation quantitatively.

  10. Method to improve commercial bonded SOI material

    DOEpatents

    Maris, Humphrey John; Sadana, Devendra Kumar

    2000-07-11

    A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

  11. Leakage Current Measurements in SOI Devices

    DTIC Science & Technology

    1991-12-01

    Total dose response of both NMOS and PMOS FETs fabrication on SOI substrates were studied. Back channel leakage currents were studied. Two types of...dose of the back channel and front channel of SIMOX and ZMR SOI substrates are reported. Some preliminary reports on the buried oxide leakage current are also provided. Bach channel leakage, SIMOX, ZMR, Total Dose Response .

  12. Rad-Hard Structured ASIC Body of Knowledge

    NASA Technical Reports Server (NTRS)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  13. Performance of the INTPIX6 SOI pixel detector

    NASA Astrophysics Data System (ADS)

    Arai, Y.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Kucewicz, W.; Miyoshi, T.; Turala, M.

    2017-01-01

    Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e-. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e-. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

  14. Front-end electronics of double SOI X-ray imaging sensors

    NASA Astrophysics Data System (ADS)

    Miyoshi, T.; Arai, Y.; Fujita, Y.; Hara, K.; Ikegami, Y.; Kurachi, I.; Tauchi, K.; Tsuboyama, T.; Yamada, M.; Ono, S.; Nishimura, R.; Hamasaki, R.

    2017-02-01

    We have developed monolithic CMOS pixel sensor using fully-depleted (FD) silicon-on-insulator (SOI) pixel process technology. The SOI substrates consist of high-resistivity silicon with p-n junctions and low-resistivity silicon layers for forming SOI-CMOS circuitry. Tungsten vias are used to make connections between p-n junctions in the silicon substrate and the first metal layers in the top-layer circuitry. Using this sensor construction, high sensor gain in small pixel areas can be achieved. In 2014, a high-resolution, integrated SOI pixel sensor, called INTPIX8, was developed with two types of substrates: a float-zone, p-type layer on a single SOI (SSOI) wafer and a Czochralski, p-type layer on a double SOI (DSOI) wafer. The X-ray spectra were obtained using Am-241 radiation source. The SSOI-based and DSOI-based sensors exhibited different levels of sensor gain and there were no large differences in the noise levels between them.

  15. Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

    SciTech Connect

    Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

    2010-09-01

    Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

  16. Electron trapping in rad-hard RCA IC's irradiated with electrons and gamma rays

    NASA Technical Reports Server (NTRS)

    Danchenko, V.; Brashears, S. S.; Fang, P. H.

    1984-01-01

    Enhanced electron trapping has been observed in n-channels of rad-hard CMOS devices due to electron and gamma-ray irradiation. Room-temperature annealing results in a positive shift in the threshold potential far beyond its initial value. The slope of the annealing curve immediately after irradiation was found to depend strongly on the gate bias applied during irradiation. Some dependence was also observed on the electron dose rate. No clear dependence on energy and shielding over a delidded device was observed. The threshold shift is probably due to electron trapping at the radiation-induced interface states and tunneling of electrons through the oxide-silicon energy barrier to fill the radiation-induced electron traps. A mathematical analysis, based on two parallel annealing kinetics, hole annealing and electron trapping, is applied to the data for various electron dose rates.

  17. SOI LDMOSFET with Up and Down Extended Stepped Drift Region

    NASA Astrophysics Data System (ADS)

    Saremi, Mehdi; Saremi, Masoumeh; Niazi, Hamid; Saremi, Maryam; Goharrizi, Arash Yazdanpanah

    2017-10-01

    To increase the breakdown voltage and decrease the ON resistance, a silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) in which the drift region extends to the up and down oxides in a step shape is proposed. This up and down extended stepped drift SOI (UDESD-SOI) structure demonstrates a modified lateral electric field distribution with additional peaks as well as a decrease of the usual peaks near the drain and gate. Two-dimensional (2D) simulations were used to compare the characteristics of the proposed UDESD-SOI structure with those of other structures, viz. down extended stepped drift SOI (DESD-SOI), up extended stepped drift SOI (UESD-SOI), and conventional SOI (C-SOI). Under the same conditions, the breakdown voltage of the UDESD-SOI structure was nearly 35%, 117%, and 318% higher compared with the DESD-SOI, UESD-SOI, and C-SOI structure, respectively. To determine the optimum parameters for the UDESD-SOI structure leading to the highest breakdown voltage, a comparative study was performed to investigate the effect of the doping concentration in the drift region, buried oxide (BOX) thickness, and thickness of up and down extended steps ( T 1 and T 2, respectively). In addition, the drain current (ON resistance) of the UDESD-SOI structure was found to be 13%, 43%, and 229% higher (16%, 65%, and 257% lower) than the values for the DESD-SOI, UESD-SOI, and C-SOI structure, respectively.

  18. SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell

    SciTech Connect

    Alles, M.L. )

    1994-12-01

    Fully depleted silicon-on-insulator (SOI) technologies are of interest for commercial applications as well as for use in harsh (radiation-intensive) environments. In both types of application, effects of charged particles (single-event effects) are of concern. Here, SPICE analysis of SEU sensitivity of a 6-T SRAM cell using commercially-representative fully depleted SOI CMOS technology parameters indicates that reduction of the minority carrier lifetime (parasitic bipolar gain) and use of thinner silicon can significantly reduce SEU sensitivity.

  19. Oxygen out-diffusion from buried layers in SOI and SiC-SOI substrates

    NASA Astrophysics Data System (ADS)

    Li, L.-G.; Vallin, Ö.; Lu, J.; Smith, U.; Norström, H.; Olsson, J.

    2010-02-01

    We have made a comparative study of the oxygen out-diffusion process during heat treatment of SOI wafers and SiC-SOI hybrid substrates. SOI materials with three different thicknesses (2, 20 and 410 nm) of buried oxide (BOX) were used in the investigation. High-resolution cross-sectional transmission electron microscopy (HRXTEM) together with laser interferometry was used to determine the remaining thickness of the BOX-layer after heat treatment. After complete removal of the BOX-layer of SOI wafers, the Si/Si interface appears to be sharp and defect-free. Similar results were obtained for SiC-SOI hybrid substrates after removal of the entire buried oxide layer. For all combinations investigated oxide removal was accompanied by a thickness reduction and roughening of the silicon surface layer as verified by atomic force microscopy (AFM).

  20. A 10 Gs/s latched comparator with dynamic offset cancellation in 28nm FD-SOI process

    NASA Astrophysics Data System (ADS)

    Jaworski, Zbigniew

    2016-12-01

    This papers presents a high-speed, latched comparator implemented in industrial 28 nm FD-SOI technology. A novel approach to counter the mismatch is proposed. The solution employs trimming the threshold voltage by means of modulating of back-gate polarization of FD-SOI transistors. The comparator is a first step towards the design of a complete 4-bit FLASH analog-to-digital converter, with a sampling frequency of 10 GHz.

  1. Design of single-gate n-channel and p-channel MOSFETs with enhanced current-drive due to simultaneous switching of front and back channels in SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    Bindu, B.; Lakshmi, N.; Bhat, K. N.; DasGupta, Amitava

    2006-07-01

    In this paper, we show that when single gate SOI MOSFETs are biased at a particular ideal back gate voltage, the front and back channels can be turned ON and OFF simultaneously using the front gate voltage, thereby enhancing the current drive of the device. It is shown by analytical models as well as 2-D numerical simulation that both maximum transconductance and minimum subthreshold slope are obtained for this ideal back gate bias. Subsequently, n-channel and p-channel MOSFETs are designed for a conventional SOI CMOS process, where both the front and back channels of these devices turn ON and OFF simultaneously resulting in enhanced current drive and superior performance. The design has been carried out with the help of analytical formulation and verified using the 2-D Device Simulator MEDICI.

  2. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

    NASA Astrophysics Data System (ADS)

    Pavanello, Marcelo Antonio; de Souza, Michelly; Ribeiro, Thales Augusto; Martino, João Antonio; Flandre, Denis

    2016-11-01

    This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

  3. A platform for monolithic CMOS-MEMS integration on SOI wafers

    NASA Astrophysics Data System (ADS)

    Villarroya, María; Figueras, Eduard; Montserrat, Josep; Verd, Jaume; Teva, Jordi; Abadal, Gabriel; Pérez Murano, Francesc; Esteve, Jaume; Barniol, Núria

    2006-10-01

    A new platform for micro- and nano-electromechanical systems based on crystalline silicon as the structural layer in CMOS substrates is presented. This platform is fabricated using silicon on insulator (SOI) substrates, which allows the monolithic integration of the mechanical transducer on crystalline silicon while the characteristics of the structural layer are kept independent from the CMOS technology. We report the design characteristics, the fabrication process and an example of application of the CMOS SOI-MEMS platform to obtain a mass sensor based on a crystalline silicon resonating cantilever.

  4. Experimental developments of A2RAM memory cells on SOI and bulk substrates

    NASA Astrophysics Data System (ADS)

    Rodriguez, Noel; Gamiz, Francisco; Navarro, Carlos; Marquez, Carlos; Andrieu, François; Faynot, Olivier; Cristoloveanu, Sorin

    2015-01-01

    A2RAM prototype devices have been demonstrated in both SOI and bulk technologies. The fabrication process has successfully achieved the characteristic retrograde doping profile of the channel which allows the coexistence of electrons and holes in the same body while maintaining low-voltage single-gate operation. The different prototypes have been electrically characterized, all of them exhibiting memory effect. The SOI samples present the best performance, showing very attractive current margin between states, competitive retention time, reasonable variability, immunity to disturbance events and no endurance issues even in the short-channel devices fabricated in the most advanced 22 nm process.

  5. Advanced CAD methodology for history effect characterization in partially depleted SOI libraries

    NASA Astrophysics Data System (ADS)

    Liot, Vincent; Flatresse, Philippe; Fournier, Jean Michel; Belleville, Marc

    2005-09-01

    To design large digital circuits in partially depleted SOI technology, worst and best case propagation delays of digital cells induced by floating body effects must be predicted. In this paper, we propose a time efficient and accurate method based on a smart transistor initialisation technique. This solution allows dividing by a factor 2 n-1 the number of simulations required to completely characterize an n-input gate. This method offers the opportunity to build CAD tools suitable for industrial PD-SOI standard cell libraries characterization.

  6. Test of a fine pitch SOI pixel detector with laser beam

    NASA Astrophysics Data System (ADS)

    Liu, Yi; Lu, Yunpeng; Ju, Xudong; Qun, Ou-Yang

    2016-01-01

    A silicon pixel detector with fine pitch size of 19 μm × 19 μm, developed based on SOI (silicon-on-insulator) technology, was tested under the illumination of infrared laser pulses. As an alternative method for particle beam tests, the laser pulses were tuned to very short duration and small transverse profile to simulate the tracks of MIPs (minimum ionization particles) in silicon. Hit cluster sizes were measured with focused laser pulses propagating through the SOI detector perpendicular to its surface and most of the induced charge was found to be collected inside the seed pixel. For the first time, the signal amplitude as a function of the applied bias voltage was measured for this SOI detector, deepening understanding of its depletion characteristics. Supported by National Natural Science Foundation of China (11375226)

  7. Electro-Optical Modulator Performance in SOI

    NASA Astrophysics Data System (ADS)

    Mardiana, B.; Hanim, A. R.; Hazura, H.; Shaari, Sahbudin; Menon, P. S.

    2011-05-01

    Silicon has been chosen as a photonic medium due to its special characteristics that is not possessed by other materials. Here, we reported the performance of Silicon on Insulator (SOI) phase modulator. The phase modulator devices have been integrated in the silicon-on-insulator (SOI) waveguide by using the p-i-n diode structure. The electrical device performance is predicted by using the 2-D semiconductor package SILVACO (CAD) software under DC operation. The performance of the modulator is evaluated in terms of its modulation efficiency and absorption loss. Modulation efficiency (VπLπ) is minimized at a greater applied voltage. Nevertheless, the absorption loss increased at higher injected free carriers.

  8. The damage equivalence of electrons, protons, alphas and gamma rays in rad-hard MOS devices

    NASA Technical Reports Server (NTRS)

    Stassinopoulos, E. G.; Van Gunten, O.; Brucker, G. J.; Knudson, A. R.; Jordan, T. M.

    1983-01-01

    This paper reports on a study of damage equivalence in rad-hard MOS devices with 100,000 rads (SiO2) capability. Damage sensitivities for electrons of 1, 2, 3, 5, and 7 MeV, protons of 1, 3, 7, 22, and 40 MeV, 3.4-MeV alphas, and Co-60 gammas were measured and compared. Results indicated that qualitatively the same charge recombination effects occurred in hard oxide devices for doses of 100,000 rads (SiO2) as in soft oxide parts for doses of 1 to 4 krads (SiO2). Consequently, damage equivalency or non-equivalency depended on radiation type and energy. However, recovery effects, both during and after irradiation, controlled relative damage sensitivity and its dependency on total dose, dose rate, supply bias, gate bias, radiation type, and energy. Correction factors can be derived from these data or from similar tests of other hard oxide type, so as to properly evaluate the combined effects of the total space environment.

  9. A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

    NASA Astrophysics Data System (ADS)

    Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

    2001-04-01

    Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

  10. Low-Power SOI CMOS Transceiver

    NASA Technical Reports Server (NTRS)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  11. Cantilever-type Thermal Microactuators Fabricated by SOI-MUMPs with U-type and I-type Configurations

    NASA Astrophysics Data System (ADS)

    Osada, Takahiro; Ochiai, Kuniyuki; Osada, Kazuki; Muro, Hideo

    Recently, the micro fluid systems have been extensively studied, where microactuators such as micro valves fabricated by MEMS technology are essential for realizing these systems. In this paper thermal microactuators with U-type and I-type shapes fabricated by SOI-MUMPs technology have been investigated for optimizing their configurations.

  12. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

    PubMed

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-08-18

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

  13. Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2010-01-01

    Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  14. Modeling high-frequency capacitance in SOI MOS capacitors

    NASA Astrophysics Data System (ADS)

    Łukasiak, Lidia; Jasiński, Jakub; Beck, Romuald B.; Ikraiam, Fawzi A.

    2016-12-01

    This paper presents a model of high frequency capacitance of a SOI MOSCAP. The capacitance in strong inversion is described with minority carrier redistribution in the inversion layer taken into account. The efficiency of the computational process is significantly improved. Moreover, it is suitable for the simulation of thin-film SOI structures. It may also be applied to the characterization of non-standard SOI MOSCAPS e.g. with nanocrystalline body.

  15. Monolithic integration of a 16-channel VMUX on SOI platform

    NASA Astrophysics Data System (ADS)

    Pei, Yuan; Yuanda, Wu; Yue, Wang; Junming, An; Xiongwei, Hu

    2015-08-01

    A 16-channel variable attenuator multiplexer/demultiplexer (VMUX) device is demonstrated. The VMUX is based on a rib-type structure on a silicon-on-insulator (SOI) platform. It consists of a 100-GHz arrayed waveguide grating (AWG) and an electro-optic variable optical attenuator (VOA) array with a p-i-n lateral diode structure. The insertion loss of the demonstrated device is about 9.1 dB and the corresponding crosstalk is about 10 dB. The injected current of the VOA is 60.74 mA at 20 dB attenuation and the whole area of the device is 2.9 × 1 mm2. The VMUX performs an excellent function of wavelength demultiplexing and optical power balancing in 16 channels. Project supported by the National High Technology Research and Development Program of China (No. 2013AA031402).

  16. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

    PubMed Central

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-01-01

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA. PMID:26295235

  17. Low-power thermal tuning of SOI-CMOS photonic structures

    NASA Astrophysics Data System (ADS)

    Shubin, Ivan; Zheng, Xuezhe; Li, Guoliang; Thacker, Hiren; Yao, Jin; Guenin, Bruce; Pinguet, Thierry; Mekis, Attila; Krishnamoorthy, A. V.; Cunningham, J. E.

    2011-01-01

    Ring waveguide resonating structures with high quality factors are the key components servicing silicon photonic links. We demonstrate highly efficient spectral tunability of the microphotonic ring structures manufactured in commercial 130 nm SOI CMOS technology. Our rings are fitted with dedicated heaters and integrated with silicon micro-machined features. Optimized layout and structure of the devices result in their maximized thermal impedance and increased efficiency of the thermal tuning.

  18. Cassini SOI Radio Occultation of Saturn's Rings

    NASA Astrophysics Data System (ADS)

    Marouf, E.; French, R.; Rappaport, N.; Thomson, F.; McGhee, C.; Asmar, S.; Johnston, D.

    2004-11-01

    On July 1, 2005 at 01:12 SCET-UTC, Cassini started the engine burn required to insert the spacecraft into orbit around Saturn (SOI). Almost 30 minutes later, Cassini was occulted by Saturn's rings as seen from the Earth. The geometric ring occultation covered all main ring features, starting at the outer edge of Ring A at 01:42 and ending at the inner edge of Ring C at 02:40. From 01:12 to 03:07, Cassini X-band radio signal (3.6 cm-wavelength) was turned on, primarily to monitor the burn. The sinusoidal transmitted signal was referenced to the on board ultrastable oscillator, allowing measurement of the signal amplitude and phase at the 70-m ground receiving station of the Deep Space Network at Canberra, Australia. As a useful by-product, a complete ring occultation observation, including free-space baseline, was achieved. Because of the special orientation of the spacecraft during the burn, the Cassini low-gain antenna was used to transmit the signal. Nominal radio occultations are conducted using the high-gain antenna, hence have intrinsic free-space signal-to-noise ratio (SNR) higher by a factor of 10,000 than the SOI occultation. Nonetheless, clearly detectable signal was observed during occultation by features in Rings A, Cassini Division, and Ring C, but not Ring B. The measurements, after reconstruction to remove diffraction effects, may be used to obtain an optical-depth and phase-shift profiles of resolved ring features. Achievable radial resolution primarily depends on the ring-opening-angle B, available free-space SNR, and occultation geometry. We compare radial resolution achievable for the Cassini SOI occultation (B = 24.7 deg, SNR = 10 dB-Hz) with those of the Voyager ring occultation (B = 5.9 deg, SNR = 50 dB-Hz), and contrast the results with those expected from nominal radio occultations during the Cassini tour. Example optical depth profiles from the Cassini SOI occultation are presented.

  19. Effect of phosphorus ion implantation on back gate effect of partially depleted SOI NMOS under total dose radiation

    NASA Astrophysics Data System (ADS)

    Leilei, Li; Xinjie, Zhou; Zongguang, Yu; Qing, Feng

    2015-01-01

    The mechanism of improving the TID radiation hardened ability of partially depleted silicon-on-insulator (SOI) devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps introduced in SiO2 near back SiO2/Si interface by phosphorus ions implantation can offset positive trapped charges near the back-gate interface. The implanted high concentration phosphorus ions can greatly reduce the back-gate effect of a partially depleted SOI NMOS device, and anti-total-dose radiation ability can reach the level of 1 Mrad(Si) for experimental devices.

  20. Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

    NASA Technical Reports Server (NTRS)

    Brucker, G. J.; Van Gunten, O.; Stassinopoulos, E. G.; Shapiro, P.; August, L. S.; Jordan, T. M.

    1983-01-01

    This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

  1. Advanced Silicon Technology for Microwave Circuits

    DTIC Science & Technology

    1994-03-08

    Pennsylvania 15235-5098 ABSTRACT MICROX is a silicon-on-insulator ( SOI ) technology using high resistivity (>3,000 ohm-cm) silicon substrates to...consideration in SOI devices. H. B. Dietrich, NRL, suggested making the technology capability comparisons covering GaAs FETs and HEMTs and Si FETs. R...Westinghouse Baltimore, arranged for thinning of wafers prior to via processing. 1. SUiKuRR MICROX is a silicon-on-insulator ( SOI ) technology which employs high

  2. Cassini SOI: Magnetometer data re-analysed

    NASA Astrophysics Data System (ADS)

    Southwood, D. J.; Yates, J. N.; Dougherty, M. K.

    2015-10-01

    The Cassini Saturn Orbit Insertion (SOI) on June 30 2004 marked Cassini's closest approach to Saturn in the mission so far. In advance of the proximal orbits it is appropriate to re-examine in preparation for the proximal orbit mission phase. SOI was the only occasion so far that Cassini has been on magnetic shells mapping to the A and B rings. At periapsis (r = 1.33 RS, Γ = 15°) it was magnetically conjugate to the inner edge of the C ring. It cannot be ruled out that the observed field inside L ≈ 1.5 is partly due to the longitude dependent internal field. g11 is a primary target and should show up in the data in special manner in part because of the spacecraft switch from retrograde to prograde motion around L &sim 2. Accordingly, for a source rotating at around 10.5-10.7 h., the spacecraft would sample azimuthal phase three times. This is illustrated here for the external cam source (G11) where the effect is dramatic as the amplitude does change with r. We show in particular that the cam fields appear to extend into the regime over the rings.

  3. Effects of patterning induced stress relaxation in strained SOI/SiGe layers and substrate

    NASA Astrophysics Data System (ADS)

    Hermann, P.; Hecker, M.; Renn, F.; Rölke, M.; Kolanek, K.; Rinderknecht, J.; Eng, L. M.

    2011-06-01

    Local stress fields in strained silicon structures important for CMOS technology are essentially related to size effects and properties of involved materials. In the present investigation, Raman spectroscopy was utilized to analyze the stress distribution within strained silicon (sSi) and silicon-germanium (SiGe) island structures. As a result of the structuring of initially unpatterned strained films, a size-dependent relaxation of the intrinsic film stresses was obtained in agreement with model calculations. This changed stress state in the features also results in the appearance of opposing stresses in the substrate underneath the islands. Even for strained island structures on top of silicon-on-insulator (SOI) wafers, corresponding stresses in the silicon substrate underneath the oxide were detected. Within structures, the stress relaxation is more pronounced for islands on SOI substrates as compared to those on bulk silicon substrates.

  4. Noise modeling and performance in 0.15-μm fully depleted SOI MOSFET

    NASA Astrophysics Data System (ADS)

    Pailloncy, Guillaume; Iniguez, Benjamin; Dambrine, Gilles; Dehan, Morin; Raskin, Jean-Pierre; Matsuhashi, Hideaki; Delatte, Pierre; Danneville, Francois

    2004-05-01

    This paper is intended to describe on one part theoretical results issued from a physical noise modeling and on the other part the noise performance of Fully Depleted (FD) SOI MOSFET of 0.15 μm gate length. In the theoretical part, the physical noise model is applied to two distinct applications; first to study the influence of the microscopic diffusion noise sources definition (located in the channel device) on the noise performance, second to check the concept of un-correlated noise sources, if one uses an input noise voltage and output drain noise current representation. In the experimental part, both bias and frequency dependences of the measured noise performances of the 0.15 μm gate length fully depleted (FD) SOI MOSFET (OKI technology) are presented, and a comparison with the results issued from the physical noise model is proposed.

  5. Evaluation of a pulse counting type SOI pixel using synchrotron radiation X-ray

    NASA Astrophysics Data System (ADS)

    Hashimoto, R.; Arai, Y.; Igarashi, N.; Kumai, R.; Lu, Y.; Miyoshi, T.; Nishimura, R.; Ouyang, Q.; Zhou, Y.; Kishimoto, S.

    2017-03-01

    Silicon-On-Insulator (SOI) technology was used to develop a fine pixelated detector with high performance. The first beam test for a prototype pulse-counting-type SOI chip, CPIXTEG3b, was performed at beamline BL-14A of the Photon Factory, KEK. CPIXTEG3b was designed using double SOI technology for decreasing crosstalk and increasing radiation hardness. It has a 64 × 64 pixel array wherein each pixel size is 50 μm × 50 μm. The sensitivity to incident X-rays was measured for each pixel with an X-ray beam 10 μm in diameter. We used the X-ray energy of 16 keV. Because of its small size, the pixel response was sensitive to the charge-sharing effect. We also considered the point spread function of the sensor. The discriminator of each pixel circuit was calibrated using a pulse generator, and performance was checked using flat-field X-rays.

  6. FDTD simulation of an 1x2 beam splitter using photonic bandgap on SOI wafer

    NASA Astrophysics Data System (ADS)

    Tsao, Shyh-Lin; Yang, Lan-Chih; Huang, Hsin-Chun; Hu, Shu-Fen

    2003-12-01

    In recent years, SOI optical waveguide is an attractive component of optical waveguide elements. Because fabrication of complementary metal oxide semiconductor (CMOS) electronic devices on SOI wafers shows promising results in the future low-power, high speed electronic device, and SOI opto-electronic integrated devices becomes an important issue[1]. Owing to the presence of periodically positioned scatters, the PBG theory is based on the principle of localization. If periodicity is equal or near a wavelength, the frequency of lightwave within the bandgap is stuck inside the material and not allowed to propagation. Recently, PBG have been suggested for a variety of optoelectronic applications, such as ultra low threshold lasers, high transmission waveguides with a bending radius comparable to the light wavelength[2]. In this paper, we design and analyze the 3 db 1x2 PBG splitter on SOI wafer, we simulated the 1x2 PBG splitter by finite difference time domain ( FDTD ) technology. In this work, our designed SOI wafer waveguide includes a 0.4 μm oxide layer and a 1.5 μm crystal silicon surface layer. The buried oxide structure is a planar slab working as the lower cladding ( nsio2 = 1.5 ) layer, the surface silicon layer (nsi = 3.5 ) is the waveguide core and the top cladding is air ( nair = 1 ). The width of rib waveguide is 4μm. The device is less than 30μm2, the input lightwave is separated into two opposite directions. In the future, we expect such a novel device can be applied in many very large scale opto-electronic integrated circuits. Reference [1] A. Layadi, A. Vonsovical, R. Orobtchouk, D. Pascal, and A. Koster, 'Low loss optical waveguide on standard SOI/SIMOX substrate', Optical Communication, vol. 146, pp. 31-33, 1998. [2] Park Young-Jin, A. Herschlein and W. Wiesbeck, 'A photonic bandgap (PBG) structure for guiding and suppressing surface waves in millimeter-wave antennas', IEEE Transactions on Microwave Theory and Techniques, vol. 49, pp. 1854

  7. Application of heat flow models to SOI current mirrors

    NASA Astrophysics Data System (ADS)

    Yu, Feixia; Cheng, Ming-C.

    2004-11-01

    An analytical heat flow model for SOI circuits is presented. The model is able to account for heat exchanges among devices and heat loss from the silicon film and interconnects to the substrate through the buried oxide. The developed model can accurately and efficiently predict the temperature distribution in the interconnect/poly-lines and SOI devices. The model is applied to SOI current mirrors to study heat flow in different layout designs. The results from the developed model are verified with those from Raphael, a 3D numerical simulator that can provide the detailed 3D temperature distribution in interconnect/poly-lines.

  8. High temperature spice modeling of partially depleted SOI MOSFETs

    SciTech Connect

    Osman, M.A.; Osman, A.A.

    1996-03-01

    Several partially depleted SOI N- and P-mosfets with dimensions ranging from W/L=30/10 to 15/3 were characterized from room temperature up to 300 C. The devices exhibited a well defined and sharp zero temperature coefficient biasing point up to 573 K in both linear and saturation regions. Simulation of the I-V characteristics using a temperature dependent SOI SPICE were in excellent agreement with measurements. Additionally, measured ZTC points agreed favorably with the predicted ZTC points using expressions derived from the temperature dependent SOI model for the ZTC {copyright} {ital 1996 American Institute of Physics.}

  9. Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

    2008-01-01

    Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

  10. ESD performance of 65 nm partially depleted n and p channel SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Mishra, R.; Ioannou, D. E.; Mitra, S.; Gauthier, R.; Seguin, C.; Halbach, R.

    2010-04-01

    A study on the electrostatic discharge (ESD) behaviors of silicide blocked (Sblk) n and p channel MOSFETs is presented for a state-of-the-art 65 nm SOI technology. It is observed that the charge in the floating body SOI MOSFETs helps to improve their ESD characteristics over the grounded body devices. The ESD behavior of the thin-oxide pMOSFETs shows failure current similar to the corresponding nMOSFETs but at the expense of higher power dissipation and higher parasitic bipolar transistor (pBJT) turn-on voltages. The study of gate-silicided (GS) and gate-non-silicided (GNS) nMOSFETs show that the GNS devices exhibit approximately 30% higher failure current than the similar sized GS devices. Transmission line pulsing (TLP) measurement with different stress pulse widths reveals that the self-heating effects are more pronounced in the GNS devices than the similar sized GS devices. The analytical thermal model for the bulk MOSFET when applied to the SOI MOSFET indicates that the high temperature region during the breakdown is not only at the drain-body junction but extends into the highly resistive drain silicide-blocked region.

  11. Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  12. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  13. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  14. The Effect of Integration of Strontium-Bismuth-Tantalate Capacitors onto SOI Wafers

    NASA Technical Reports Server (NTRS)

    Strauss, Karl F.; Joshi, Vikram; Ohno, Morifumo; Ida, Jiro; Nagatomo, Yoshiki

    2006-01-01

    We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

  15. The effect of integration of Strontium-Bismuth-Tantalate capacitors onto SOI wafers

    NASA Technical Reports Server (NTRS)

    Joshi, Vikram; Ohno, Morifumo; Ida, Jiro; Nagatomo, Yoshiki; Strauss, Karl

    2005-01-01

    We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

  16. The effect of integration of Strontium-Bismuth-Tantalate capacitors onto SOI wafers

    NASA Technical Reports Server (NTRS)

    Joshi, Vikram; Ohno, Morifumo; Ida, Jiro; Nagatomo, Yoshiki; Strauss, Karl

    2005-01-01

    We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

  17. The Effect of Integration of Strontium-Bismuth-Tantalate Capacitors onto SOI Wafers

    NASA Technical Reports Server (NTRS)

    Strauss, Karl F.; Joshi, Vikram; Ohno, Morifumo; Ida, Jiro; Nagatomo, Yoshiki

    2006-01-01

    We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

  18. The Bridges SOI Model School Program at Palo Verde School, Palo Verde, Arizona.

    ERIC Educational Resources Information Center

    Stock, William A.; DiSalvo, Pamela M.

    The Bridges SOI Model School Program is an educational service based upon the SOI (Structure of Intellect) Model School curriculum. For the middle seven months of the academic year, all students in the program complete brief daily exercises that develop specific cognitive skills delineated in the SOI model. Additionally, intensive individual…

  19. Reduced nonlinearities in 100-nm high SOI waveguides

    NASA Astrophysics Data System (ADS)

    Lacava, C.; Marchetti, R.; Vitali, V.; Cristiani, I.; Giuliani, G.; Fournier, M.; Bernabe, S.; Minzioni, P.

    2016-03-01

    Here we show the results of an experimental analysis dedicated to investigate the impact of optical non linear effects, such as two-photon absorption (TPA), free-carrier absorption (FCA) and free-carrier dispersion (FCD), on the performance of integrated micro-resonator based filters for application in WDM telecommunication systems. The filters were fabricated using SOI (Silicon-on-Insulator) technology by CEA-Leti, in the frame of the FP7 Fabulous Project, which aims to develop low-cost and high-performance integrated optical devices to be used in new generation passive optical- networks (NG-PON2). Different designs were tested, including both ring-based structures and racetrack-based structures, with single-, double- or triple- resonator configuration, and using different waveguide cross-sections (from 500 x 200 nm to 825 x 100 nm). Measurements were carried out using an external cavity tunable laser source operating in the extended telecom bandwidth, using both continuous wave signals and 10 Gbit/s modulated signals. Results show that the use 100-nm high waveguide allows reducing the impact of non-linear losses, with respect to the standard waveguides, thus increasing by more than 3 dB the maximum amount of optical power that can be injected into the devices before causing significant non-linear effects. Measurements with OOK-modulated signals at 10 Gbit/s showed that TPA and FCA don't affect the back-to-back BER of the signal, even when long pseudo-random-bit-sequences (PRBS) are used, as the FCD-induced filter-detuning increases filter losses but "prevents" excessive signal degradation.

  20. An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

    NASA Technical Reports Server (NTRS)

    Jackson, S. A.; Blalock, B. J.; Mojarradi, M. M.; Li, H. W.

    2001-01-01

    The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

  1. An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

    NASA Technical Reports Server (NTRS)

    Jackson, S. A.; Blalock, B. J.; Mojarradi, M. M.; Li, H. W.

    2001-01-01

    The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

  2. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

    PubMed

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-11-04

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)(-0.1) in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  3. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

    PubMed Central

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-01-01

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

  4. An analytical model for nanowire junctionless SOI FinFETs with considering three-dimensional coupling effect

    NASA Astrophysics Data System (ADS)

    Fan-Yu, Liu; Heng-Zhu, Liu; Bi-Wei, Liu; Yu-Feng, Guo

    2016-04-01

    In this paper, the three-dimensional (3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator (SOI) FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional (2D) potential model is proposed for the subthreshold region of junctionless SOI FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted. Project supported by the Research Program of the National University of Defense Technology (Grant No. JC 13-06-04).

  5. SOI waveguide based planar reflective grating demultiplexer for FTTH

    NASA Astrophysics Data System (ADS)

    Bidnyk, S.; Feng, D.; Balakrishnan, A.; Pearson, M.; Gao, M.; Liang, H.; Qian, W.; Kung, C.-C.; Fong, J.; Yin, J.; Asghari, M.

    2007-02-01

    Recent deployments of fiber-to-the-home (FTTH) represent the fastest growing sector of the telecommunication industry. The emergence of the silicon-on-insulator (SOI) photonics presents an opportunity to exploit the wide availability of silicon foundries and high-quality low-cost substrates for addressing the FTTH market. We have now demonstrated that a monolithically integrated FTTH demultiplexer can be built using the SOI platform. The SOI filter comprises a monolithically integrated planar reflective grating and a multi-stage Mach-Zehnder interferometer that were fabricated using a CMOS-compatible SOI process with the core thickness of 3.0 μm and optically insulating layer of silica with a thickness of 0.375 μm. The Mach-Zehnder interferometer was used to coarsely separate the 1310 nm channel from 1490 and 1550 nm channels. Subsequently, a planar reflective grating was used to demultiplex the 1490 and 1550 nm channels. The manufactured device showed the 1-dB bandwidth of 110 nm for the 1310 nm channel. For the 1490 nm and 1550 nm channels, the 1-dB bandwidth was measured to be 30 nm. The adjacent channel isolation between the 1490 nm and 1550 nm channels was better than 32 dB. The optical isolation between the 1310 nm and 1490 and 1550 nm channels was better than 45 dB. Applications of the planar reflective gratings in the FTTH networks are discussed.

  6. Building blocks X-FAB SOI 0.18 μm

    NASA Astrophysics Data System (ADS)

    Cizel, J.-B.; Ahmad, S.; Callier, S.; Cornat, R.; Dulucq, F.; Fleury, J.; Martin-Chassard, G.; Raux, L.; de La Taille, C.; Thienpont, D.

    2015-02-01

    This work has been done in order to study a new technology provided by X-FAB named xt018. It is an SOI (Silicon On Insulator) technology with a minimal gate length of 180 nm. Building blocks have been done to test the advantages and drawbacks of this technology compared to the one currently used (AMS SiGe 0.35 μm). These building blocks have been designed to fit in an existing experience housed by the CALICE collaboration: the read-out chip for the Electromagnetic CALorimeter (ECAL) of the foreseen International Linear Collider (ILC). Performances will be compared to those of the SKIROC2 chip designed by the OMEGA laboratory, trying to fit the same requirements. The chip is being manufactured and will be back for measurements in December, the displayed results are only simulation results and thus the conclusions concerning the performances of these building blocks are subject to change.

  7. Analysis of Aluminum-Nitride SOI for High-Temperature Electronics

    NASA Technical Reports Server (NTRS)

    Biegel, Bryan A.; Osman, Mohamed A.; Yu, Zhiping

    2000-01-01

    We use numerical simulation to investigate the high-temperature (up to 500K) operation of SOI MOSFETs with Aluminum-Nitride (AIN) buried insulators, rather than the conventional silicon-dioxide (SiO2). Because the thermal conductivity of AIN is about 100 times that of SiO2, AIN SOI should greatly reduce the often severe self-heating problem of conventional SOI, making SOI potentially suitable for high-temperature applications. A detailed electrothermal transport model is used in the simulations, and solved with a PDE solver called PROPHET In this work, we compare the performance of AIN-based SOI with that of SiO2-based SOI and conventional MOSFETs. We find that AIN SOI does indeed remove the self-heating penalty of SOL However, several device design trade-offs remain, which our simulations highlight.

  8. Double window partial SOI-LDMOSFET: A novel device for breakdown voltage improvement

    NASA Astrophysics Data System (ADS)

    Orouji, Ali A.; Moghadam, Hamid Amini; Dideban, A.

    2010-11-01

    In this paper we propose novel partial silicon on insulator lateral double diffused MOSFET in order to increase breakdown voltage. The key idea in this work is to decrease common peaks near the drain and gate junctions by producing additional peaks. The proposed structure is called double window partial SOI-LDMOSFET (DWP-SOI). The simulation results show that the breakdown voltage of DWP-SOI can be enhanced about two times as compared to conventional SOI-LDMOSFET(C-SOI) and about 70% as compared to conventional SOI-LDMOSFET with a field plate (CF-SOI). The self-heating effect is also improved in the proposed structure because we have used two windows in buried oxide, which provide a heat conduction path from the active region to the substrate.

  9. Rad-Hard 2.5 GBPS SpaceFibre Interface Device

    NASA Astrophysics Data System (ADS)

    Ginosar, Ran; Liran, Tuvia; Alon, Dov; Dobkin, Reuven; Goldberg, Michael; Sokolov, Gal; Burdo, Gennady; Blatt, Nimrod; Parkes, Steve; Rastetter, Paul; Krstic, Milos; Crescenzio, Alberto

    2013-08-01

    Seven partner institutions and companies have been cooperating within the scope of the FP7 Collaborative Project VHiSSI to develop a very high speed serial interface device. The device will include two SpaceFibre serial links capable of data rates up to 2.5 Gbps (3.125 Gbps after 8b/10b encoding). Complete SpaceFibre networking stack is implemented in the device. It also provides a variety of other interfaces including SpaceWire, parallel buses, LVTTL and LVDS signaling. Operating modes include SpaceFibre and SpaceWire bridges and routers, interfaces to instruments, to processors and to mass memory. The device is implemented on IHP 130nm CMOS technology, using RadSafe™ rad-hard-by-design libraries and custom analog circuits. A test chip has recently been fabricated and tested to validate the technology and circuits for the SERDES device.

  10. 3D through silicon via profile metrology based on spectroscopic reflectometry for SOI applications

    NASA Astrophysics Data System (ADS)

    Fursenko, O.; Bauer, J.; Marschmeyer, S.

    2016-04-01

    Through-silicon via (TSV) technology is a key feature for 3D circuit integration. TSVs are formed by etching a vertical via and filling them with a conductive material for creation of interconnections which go through the silicon or silicon-on-insulator (SOI) wafer. The Bosch etch process on Deep Reactive Ion Etching (DRIE) is commonly used for this purpose. The etch profile defined by the critical dimensions (CDs) at the top and at the bottom, by the depth and by the scallop size on the sidewall needs to be monitored and well controlled. In this work a nondestructive 3D metrology of deeply-etched structures with an aspect ratio of more than 10 and patterns with lateral dimensions from 2 to 7 μm in SOI wafer is proposed. Spectroscopic reflectometry in the spectral range of 250-800 nm using a production metrology tool was applied. The depth determinations based on different algorithms are compared. The Pearson correlation coefficient between measured and calculated reflection is suggested as the most appropriate method. A simple method for top CD evaluation is proposed by the measurement of reflection and using the polynomial approximation of reflection versus TSV filling coefficient which is determined as ratio of CD to pitch. The 3D RCWA simulations confirm this dependence.

  11. Experimental characterisation of PD SOI MOSFET devices fabricated with diamond-shaped body contact

    NASA Astrophysics Data System (ADS)

    Daghighi, Arash; Osman, Mohamed A.

    2011-06-01

    The design of diamond-shaped body-contacted (DSBC) devices using standard layers in a 0.35 µm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process is described in this article. The technology is based on a manufacturable partially depleted SOI process targeted for radio frequency applications. The experimental measurements of drain induced barrier lowering for the fabricated DSBC structure showed suppression of floating body effects (FBE) at the promising rate of 24 mV/V. The measurement results confirmed current drive (I DS) improvement by 25% at V DS = 1.5 V and V GS = 1.5 V compared to conventional body-tied-source (BTS) device. A constant and steady output conductance (g DS) in the saturation region was observed for the DSBC structure. The gate trans-conductance (g m) is improved by 34% at V DS = 1.5 V and V GS = 1.5 V compared to conventional BTS device. Three-dimensional device simulation provides insight on FBE suppression and channel current improvement. Experimental results confirmed the area efficiency of the DSBC structure and its excellent current drive performance.

  12. Development and performance of Kyoto's x-ray astronomical SOI pixel (SOIPIX) sensor

    NASA Astrophysics Data System (ADS)

    Tsuru, Takeshi G.; Matsumura, Hideaki; Takeda, Ayaki; Tanaka, Takaaki; Nakashima, Shinya; Arai, Yasuo; Mori, Koji; Takenaka, Ryota; Nishioka, Yusuke; Kohmura, Takayoshi; Hatsui, Takaki; Kameshima, Takashi; Ozaki, Kyosuke; Kohmura, Yoshiki; Wagai, Tatsuya; Takei, Dai; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita; Kamehama, Hiroki

    2014-08-01

    We have been developing monolithic active pixel sensors, known as Kyoto's X-ray SOIPIXs, based on the CMOS SOI (silicon-on-insulator) technology for next-generation X-ray astronomy satellites. The event trigger output function implemented in each pixel offers microsecond time resolution and enables reduction of the non-X-ray background that dominates the high X-ray energy band above 5-10 keV. A fully depleted SOI with a thick depletion layer and back illumination offers wide band coverage of 0.3-40 keV. Here, we report recent progress in the X-ray SOIPIX development. In this study, we achieved an energy resolution of 300 eV (FWHM) at 6 keV and a read-out noise of 33 e- (rms) in the frame readout mode, which allows us to clearly resolve Mn-Kα and Kβ. Moreover, we produced a fully depleted layer with a thickness of 500 μm. The event-driven readout mode has already been successfully demonstrated.

  13. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    NASA Astrophysics Data System (ADS)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  14. Single Event Transient Analysis of an SOI Operational Amplifier for Use in Low-Temperature Martian Exploration

    NASA Technical Reports Server (NTRS)

    Laird, Jamie S.; Scheik, Leif; Vizkelethy, Gyorgy; Mojarradi, Mohammad M; Chen, Yuan; Miyahira, Tetsuo; Blalock, Benjamin; Greenwell, Robert; Doyle, Barney

    2006-01-01

    The next generation of Martian rover#s to be launched by JPL are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients (SET) which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-On-Insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shownto be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xebeams of energy 25MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36MeV O6(+) microbeam. the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern. This is a viewgraph presentation

  15. Single Event Transient Analysis of an SOI Operational Amplifier for Use in Low-Temperature Martian Exploration

    NASA Technical Reports Server (NTRS)

    Laird, Jamie S.; Scheik, Leif; Vizkelethy, Gyorgy; Mojarradi, Mohammad M; Chen, Yuan; Miyahira, Tetsuo; Blalock, Benjamin; Greenwell, Robert; Doyle, Barney

    2006-01-01

    The next generation of Martian rover#s to be launched by JPL are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients (SET) which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-On-Insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shownto be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xebeams of energy 25MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36MeV O6(+) microbeam. the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern. This is a viewgraph presentation

  16. Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature

  17. Benchmark Study and Characterization of European Rad-Hard Power MOSFEts for Space Applications

    NASA Astrophysics Data System (ADS)

    Becherer, J.; Dittrich, R.; Muschitiello, M.; Constantino, A.

    2014-08-01

    Power Field Effect Transistors are an integral part of the electronic equipment of every space vehicle. In order to survive the harsh conditions of space, the transistors have to fulfill rigorous conditions. A number one in the list of space qualification criteria is the guarantee of radiation hardness. Today several radiation hard Power MOSFETs are available from a variety of companies all over the world. A benchmark study of the available Power MOSFETs for space applications has been compiled in this paper. The newly developed European Superjunction Technologies Power MOSFETs from Infineon show the best performance. Therefore, a total ionizing dose characterization of the 250 V and 150 V European MOSFETs have been performed.

  18. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    NASA Astrophysics Data System (ADS)

    Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

    2014-06-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

  19. Metallic behaviour in SOI quantum wells with strong intervalley scattering

    PubMed Central

    Renard, V. T.; Duchemin, I.; Niida, Y.; Fujiwara, A.; Hirayama, Y.; Takashina, K.

    2013-01-01

    The fundamental properties of valleys are recently attracting growing attention due to electrons in new and topical materials possessing this degree-of-freedom and recent proposals for valleytronics devices. In silicon MOSFETs, the interest has a longer history since the valley degree of freedom had been identified as a key parameter in the observation of the controversial “metallic behaviour” in two dimensions. However, while it has been recently demonstrated that lifting valley degeneracy can destroy the metallic behaviour, little is known about the role of intervalley scattering. Here, we show that the metallic behaviour can be observed in the presence of strong intervalley scattering in silicon on insulator (SOI) quantum wells. Analysis of the conductivity in terms of quantum corrections reveals that interactions are much stronger in SOI than in conventional MOSFETs, leading to the metallic behaviour despite the strong intervalley scattering. PMID:23774638

  20. Transport study of ultra-thin SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Naser, B.; Cho, K. H.; Hwang, S. W.; Bird, J. P.; Ferry, D. K.; Goodnick, S. M.; Park, B. G.; Ahn, D.

    2003-07-01

    We present the results of detailed transport measurements on a silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) in a wide range of temperature ( T, 4.2SOI wafer exhibits oscillatory features and the origin is interpreted as the existence of unintentional Coulomb islands created by back interface impurities.

  1. Ultra compact triplexing filters based on SOI nanowire AWGs

    NASA Astrophysics Data System (ADS)

    Jiashun, Zhang; Junming, An; Lei, Zhao; Shijiao, Song; Liangliang, Wang; Jianguang, Li; Hongjie, Wang; Yuanda, Wu; Xiongwei, Hu

    2011-04-01

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion.

  2. Ion implanted integrated Bragg gratings in SOI waveguides

    NASA Astrophysics Data System (ADS)

    Bulk, M. P.; Knights, A. P.; Jessop, P. E.

    2007-06-01

    We report the realization of a Bragg grating optical filter at telecommunication wavelengths in silicon-on-insulator (SOI) through the use of ion implantation induced refractive index modulation. Silicon self-irradiation damage accumulation results in an increase of the refractive index to a saturated value, upon amorphization, of approximately 3.75. This makes it an interesting candidate for passive gratings as the silicon retains a planar surface, making it ideal for further processing. Monte Carlo simulations and coupled mode theory demonstrate the viability of the approach. Planar implanted SOI waveguides showed extinction ratios of -5 dB for TE and -2 dB for TM. An annealing study suggests complete amorphization was not achieved and future results should be improved dramatically.

  3. A comparison between Rad-Hard Standard Float Zone (FZ) and Magnetic Czochralski (MCz) Silicon Diodes in Radiotherapy Electron Beams Dosimetry

    NASA Astrophysics Data System (ADS)

    dos Santos, T. C.; Gonçalves, J. A. C.; Vasques, M. M.; Tobias, C. C. B.; Neves-Junior, W. F. P.; Haddad, C. M. K.; Harkonen, J.

    2011-08-01

    In this work we present the preliminary results obtained with a comparison between rad-hard FZ and MCz silicon diodes as on-line clinical electron beams dosimeters. The dynamic current response of the diodes under irradiation with electron beams within the energy range of 6 MeV up to 21 MeV was investigated. For all energies, data show good instantaneous repeatability of the diodes, characterized by coefficients of variation better than 2.8% and 2.5% to FZ and MCz, respectively. The dose-response curves of both diodes are quite linear with charge sensitivities better than 0.55 μC/Gy and 0.68 μC/Gy to FZ and MCz devices. These results show that MCz diode is more sensitive than FZ diode.

  4. Split gate SOI trench LDMOS with low-resistance channel

    NASA Astrophysics Data System (ADS)

    Ying-Wang; Wang, Yi-fan; Liu, Yan-juan; Yang-Wang

    2017-02-01

    A split gate SOI trench LDMOSFET (SGT-LDMOS) structure is proposed and the low-resistance channel is introduced to further reduces the specific on-state resistance (Ron,sp). The split gate SOI trench LDMOS with low on-resistance channel (SGTL-LDMOS) structure shows a reduction in specific on-state resistance (Ron,sp) compared to that of a conventional SOI trench LDMOS (CT-LDMOS) and SGT-LDMOS structures. This is due to the increased N-type concentration in the drift region and the lower channel resistance. In addition, the split-gate floating structure in the SGTL-LDMOS also reduces the specific gate-charge (Qg,sp) and increases the breakdown voltage as compared to the CT-LDMOS. As a result, the breakdown voltage (BV) of the SGTL-LDMOS increases from 183 V of the CT-LDMOS to 227 V, the Ron,sp decreases from 43.4 mΩ cm2 to 9.3 mΩ cm2, and the Qg,sp decreases from 78.4 nC/cm2 to 50.0 nC/cm2.

  5. Modeling the uniform transport in thin film SOI MOSFETs with a Monte-Carlo simulator for the 2D electron gas

    NASA Astrophysics Data System (ADS)

    Lucci, Luca; Palestri, Pierpaolo; Esseni, David; Selmi, Luca

    2005-09-01

    In this paper, we present simulations of some of the most relevant transport properties of the inversion layer of ultra-thin film SOI devices with a self-consistent Monte-Carlo transport code for a confined electron gas. We show that size induced quantization not only decreases the low-field mobility (as experimentally found in [Uchida K, Koga J, Ohba R, Numata T, Takagi S. Experimental eidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance and threshold voltage of ultrathin body SOI MOSFETs, IEEE IEDM Tech Dig 2001;633-6; Esseni D, Mastrapasqua M, Celler GK, Fiegna C, Selmi L, Sangiorgi E. Low field electron and hole mobility of SOI transistors fabricated on ultra-thin silicon films for deep sub-micron technology application. IEEE Trans Electron Dev 2001;48(12):2842-50; Esseni D, Mastrapasqua M, Celler GK, Fiegna C, Selmi L, Sangiorgi E, An experimental study of mobility enhancement in ultra-thin SOI transistors operated in double-gate mode, IEEE Trans Electron Dev 2003;50(3):802-8. [1-3

  6. Microscopic C-V measurements of SOI wafers by scanning capacitance microscopy

    NASA Astrophysics Data System (ADS)

    Ishida, T.; Yoshida, H.; Kishino, S.

    2004-07-01

    Scanning capacitance microscopy (SCM) has been applied to microscopic characterization of electrical properties of silicon-on-insulator (SOI) wafers. Two kinds of capacitance-voltage (C-V) methods have been proposed for separately characterizing the electrical properties of a gate oxide, an SOI layer, a buried oxide (BOX) layer, a Si substrate, and their interfaces: (i) a front-gate C-V method whereby the electrical properties of the gate oxide and front SOI (the gate oxide/SOI) interface can be characterized, and (ii) a back-gate C-V method for the characterization of the electrical properties of the BOX layer, back SOI (the BOX/SOI) interface, and the BOX/Si substrate interface. Furthermore, SCM images of the sampled SOI wafer have been obtained for visualizing the microscopic spatial distribution of electrical properties of SOI wafers by using the proposed C-V methods. These SCM images revealed the fluctuation in the oxide charges and interface traps. SCM has been demonstrated to be an effective tool for microscopic electrical characterization of SOI wafers.

  7. Development of an X-ray imaging system with SOI pixel detectors

    NASA Astrophysics Data System (ADS)

    Nishimura, Ryutaro; Arai, Yasuo; Miyoshi, Toshinobu; Hirano, Keiichi; Kishimoto, Shunji; Hashimoto, Ryo

    2016-09-01

    An X-ray imaging system employing pixel sensors in silicon-on-insulator technology is currently under development. The system consists of an SOI pixel detector (INTPIX4) and a DAQ system based on a multi-purpose readout board (SEABAS2). To correct a bottleneck in the total throughput of the DAQ of the first prototype, parallel processing of the data taking and storing processes and a FIFO buffer were implemented for the new DAQ release. Due to these upgrades, the DAQ throughput was improved from 6 Hz (41 Mbps) to 90 Hz (613 Mbps). The first X-ray imaging system with the new DAQ software release was tested using 33.3 keV and 9.5 keV mono X-rays for three-dimensional computerized tomography. The results of these tests are presented.

  8. A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer

    NASA Astrophysics Data System (ADS)

    Liaw, Yue-Gie; Liao, Wen-Shiang; Wang, Mu-Chun; Lin, Cheng-Li; Zhou, Bin; Gu, Haoshuang; Li, Deshi; Zou, Xuecheng

    2016-12-01

    Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. The drive current (ION), off current (IOFF), subthreshold swing (SS), drain-induced barrier lowering (DIBL) and transistor gate delay of 30 nm gate length (Lg) of FinFETs illustrate the promising device performance. The TCAD simulations demonstrate that both threshold voltage (Vth) and off current can be adjusted appropriately through the full silicidation (FUSI) of CoSi2 gate engineering. Moreover, the drive currents of n- and p-channel FinFETs are able to be further enhanced once applying the raised Source/Drain (S/D) approach technology for reducing the S/D resistance drastically.

  9. Compact and efficient large cross-section SOI rib waveguide taper optimized by a genetic algorithm

    NASA Astrophysics Data System (ADS)

    Liu, Yujin; Wang, Xi; Dong, Ying; Wang, Xiaohao

    2016-01-01

    A genetic algorithm is applied to optimize a taper between a large cross-section silicon-on-insulator (SOI) rib waveguide and a single-mode fiber to achieve an ultra-compact and highly efficient coupling structure. The coupling efficiency is taken as the objective function of the genetic algorithm in the taper optimization process. To apply the optimization algorithm, the taper is segmented into several sections. Three encoding forms and a two-step optimization strategy are adopted in the optimization process, resulting in a 10μm long taper with a coupling efficiency of 93.30% in quasi-TE mode at 1550nm. The characteristics of the optimized taper including the field profile, spectrum and fabrication tolerances in both horizontal and vertical directions are investigated via a three dimensional eigenmode expansion (EME) method, indicating that the optimized taper is compatible with the prevailing integrated circuit (IC) processing technology.

  10. Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors

    NASA Astrophysics Data System (ADS)

    Cortes, I.; Fernández-Martínez, P.; Flores, D.; Hidalgo, S.; Rebollo, J.

    2008-09-01

    The benefits of applying the shallow trench isolation (STI) concept to a higher voltage thin-SOI laterally diffused metal oxide semiconductor (LDMOS) (in the range of 80 V) are analysed in this paper by means of 2D technology computer-aided design (TCAD) numerical simulations. The TCAD simulation results allow comparing the electrical performance of the studied STI LDMOS structure with that of a conventional LDMOS in terms of the main static (breakdown voltage (VBR) and specific on-state resistance (RON-sp)) and dynamic (gate-drain capacitance (CGD) and cut-off frequency (fT)) characteristics. Moreover, the impact of the STI length (LSTI) and thickness (TSTI), and the N-drift implantation energy on the electrical characteristics is considered in detail. On the other hand, the STI block helps to move the harmful high electric field further away from the silicon surface, thus minimizing gate-oxide degradation by hot carriers.

  11. Monolithic optical phased-array transceiver in a standard SOI CMOS process.

    PubMed

    Abediasl, Hooman; Hashemi, Hossein

    2015-03-09

    Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

  12. An accurate model for predicting high frequency noise of nanoscale NMOS SOI transistors

    NASA Astrophysics Data System (ADS)

    Shen, Yanfei; Cui, Jie; Mohammadi, Saeed

    2017-05-01

    A nonlinear and scalable model suitable for predicting high frequency noise of N-type Metal Oxide Semiconductor (NMOS) transistors is presented. The model is developed for a commercial 45 nm CMOS SOI technology and its accuracy is validated through comparison with measured performance of a microwave low noise amplifier. The model employs the virtual source nonlinear core and adds parasitic elements to accurately simulate the RF behavior of multi-finger NMOS transistors up to 40 GHz. For the first time, the traditional long-channel thermal noise model is supplemented with an injection noise model to accurately represent the noise behavior of these short-channel transistors up to 26 GHz. The developed model is simple and easy to extract, yet very accurate.

  13. A high linearity X-band SOI CMOS digitally-controlled phase shifter

    NASA Astrophysics Data System (ADS)

    Liang, Chen; Xinyu, Chen; Youtao, Zhang; Zhiqun, Li; Lei, Yang

    2015-06-01

    This paper proposed an X-band 6-bit passive phase shifter (PS) designed in 0.18 μm silicon-on-insulator (SOI) CMOS technology, which solves the key problem of high integration degree, low power, and a small size T/R module. The switched-topology is employed to achieve broadband and flat phase shift. The ESD circuit and driver are also integrated in the PS. It covers the frequency band from 7.5 to 10.5 GHz with an EMS phase error less than 7.5°. The input and output VSWRs are less than 2 and the insertion loss (IL) is between 8-14 dB across the 7.5 to 10.5 GHz, with a maximum IL difference of 4 dB. The input 1 dB compression point (IP1dB) is 20 dBm.

  14. Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications

    NASA Astrophysics Data System (ADS)

    Bawedin, M.; Cristoloveanu, S.; Flandre, D.; Udrea, F.

    2010-02-01

    Even in fully-depleted (FD) SOI MOSFETs, the floating-body potential variations may lead to strong transient effects on the current characteristics. A physics-based model, enabling the fast computing of the potential variation with time, is proposed in this paper. The model is validated, for a wide range of technological parameters and biases, by 2D numerical simulations. This model reproduces the experimental data and clarifies the physics mechanisms responsible for the transient variations of gate and drain currents. Relevant applications in the field of EEPROM and capacitorless floating-body DRAM memories are addressed.

  15. Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

  16. Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad; Dones, Keishla Rivera

    2009-01-01

    Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing

  17. SOI CMOS Imager with Suppression of Cross-Talk

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  18. Using SST, PDO and SOI for Streamflow Reconstruction

    NASA Astrophysics Data System (ADS)

    Bukhary, S. S.; Kalra, A.; Ahmad, S.

    2015-12-01

    Recurring droughts in southwestern U.S. particularly California, have strained the existing water reserves of the region. Frequency, severity and duration of these recurring drought events may not be captured by the available instrumental records. Thus streamflow reconstruction becomes imperative to identify the historic hydroclimatic extremes of a region and assists in developing better water management strategies, vital for sustainability of water reserves. Tree ring chronologies (TRC) are conventionally used to reconstruct streamflows, since tree rings are representative of climatic information. Studies have shown that sea surface temperature (SST) and climate indices of southern oscillation index (SOI) and pacific decadal oscillation (PDO) influence U.S. streamflow volumes. The purpose of this study was to improve the traditional reconstruction methodology by incorporating the oceanic-atmospheric variables of PDO, SOI, and Pacific Ocean SST, alongwith TRC as predictors in a step-wise linear regression model. The methodology of singular value decomposition was used to identify teleconnected regions of streamflow and SST. The approach was tested on eleven gage stations in Sacramento River Basin (SRB) and San Joaquin River Basin (JRB). The reconstructions were successfully generated from 1800-1980, having an overlap period of 1932-1980. Improved results were exhibited when using the predictor variable of SST along with TRC (calibration r2=0.6-0.91) compared to when using TRC in combination with SOI and PDO (calibration r2=0.51-0.78) or when using TRC by itself (calibration r2=0.51-0.86). For future work, this approach can be replicated for other watersheds by using the oceanic-atmospheric climate variables influencing that region.

  19. Design, simulation, and fabrication of a 90° SOI optical hybrid based on the self-imaging principle

    NASA Astrophysics Data System (ADS)

    Abdul-Majid, Sawsan; Hasan, Imad I.; Bock, Przemek J.; Hall, Trevor J.

    2010-05-01

    This paper introduces a compact 90º optical hybrid, built on small size SOI waveguide technology .This optical hybrid is a critical component of a potentially low-cost coherent optical receiver design developed within the frame of our Optical Coherent Transmission for Access Network Extensions (OCTANE) project. In previous recent work, 90º optical hybrids were realized in SOI rib waveguide technology with 4 μm top silicon and a rib height of approximately 2 μm. In this paper, we introduce a compact 90º optical hybrid, built on small size SOI waveguide technology (1.5 μm SOI -based rib waveguide, with 0.8μm rib height). The proposed device consists of multimode interferometers (MMIs) connected in such a way that four different vector additions of a reference signal (local oscillator) and the signal to be detected are obtained. At the outputs, the hybrid provides four linear combination of the signal with the reference which differs by a relative phase shift of the reference of 90º. The four output signals are detected by a pair of balanced receivers to provide in-phase and quadrature (I&Q) channels. The phase differences arise naturally from the self imaging property of a MMI. The key elements of the 90º optical hybrid, including a 2×2 MMI, a 4×4 MMI, and polarization diversity configuration have been designed and simulated, using the numerical mode solving tool FIMMPROB. The 2×2 and 4×4 MMI had overall lengths of 701μm and 3712.5μm lengths respectively. Tapers are used to couple adiabatically single mode waveguides to the entrance and exit ports of the MMI to assure correct operation by avoiding coupling to the higher order transverse modes allowed at the entrance and exit ports of the MMI. The simulation results at 1550nm show polarization independence and phase errors between the ports of less than 0.03 degrees. Currently the design is in fabrication at the Canadian Photonics Fabrication Center with the support of CMC Microsystems and experimental

  20. Improvement in thickness uniformity of thick SOI by numerically controlled local wet etching.

    PubMed

    Yamamura, Kazuya; Ueda, Kazuaki; Hosoda, Mao; Zettsu, Nobuyuki

    2011-04-01

    Silicon-on-insulator (SOI) wafers are promising semiconductor materials for high-speed LSIs, low-power-consumption electric devices and micro electro mechanical systems (MEMS). The thickness distribution of an SOI causes the variation of threshold voltage in electronic devices manufactured on the SOI wafer. The thickness distribution of a thin SOI, which is manufactured by applying a smart cut technique, is comparatively uniform. On the other hand, a thick SOI has a large thickness distribution because a bonded wafer is thinned by conventional grinding and polishing. For a thick SOI wafer with a thickness of 1 microm, it is required that the tolerance of thickness variation is less than 50 nm. However, improving the thickness uniformity of a thick SOI layer to a tolerance of +/- 5% is difficult by conventional machining because of the fundamental limitations of these techniques. We have developed numerically controlled local wet etching (NC-LWE) technique as a novel deterministic subaperture figuring and finishing technique, which utilizes a localized chemical reaction between the etchant and the surface of the workpiece. We demonstrated an improvement in the thickness distribution of a thick SOI by NC-LWE using an HF/HNO3 mixture, and thickness variation improved from 480 nm to 200 nm within a diameter of 170 mm.

  1. SOI/MDI studies of active region seismology and evolution

    NASA Technical Reports Server (NTRS)

    Tarbell, Ted D.; Title, Alan; Hoeksema, J. Todd; Scherrer, Phil; Zweibel, Ellen

    1995-01-01

    The solar oscillations investigation (SOI) will study solar active regions using both helioseismic and conventional observation techniques. The Michelson Doppler imager (MDI) can perform Doppler continuum and line depth imagery and can produce longitudinal magnetograms, showing either the full disk or a high resolution field of view. A dynamics program of continuous full disk Doppler observations for two months per year, campaign programs of eight hours of continuous observation per day, and a synoptic magnetic program of about 15 full disk magnetograms per day, are planned. The scientific plans, measurements and observation programs, are described.

  2. Continuously tunable delay line based on SOI tapered Bragg gratings.

    PubMed

    Giuntoni, Ivano; Stolarek, David; Kroushkov, Dimitar I; Bruns, Jürgen; Zimmermann, Lars; Tillack, Bernd; Petermann, Klaus

    2012-05-07

    The realization of an integrated delay line using tapered Bragg gratings in a drop-filter configuration is presented. The device is fabricated on silicon-on-insulator (SOI) rib waveguides using a Deep-UV 248 nm lithography. The continuous delay tunability is achieved using the thermo-optical effect, showing experimentally that a tuning range of 450 ps can be obtained with a tuning coefficient of -51 ps/°C. Furthermore the system performance is considered, showing that an operation at a bit rate of 25 Gbit/s can be achieved, and could be extended to 80 Gbit/s with the addition of a proper dispersion compensation.

  3. Asymmetrically doped stacked channel strained SOI FinFET

    NASA Astrophysics Data System (ADS)

    Dubey, Shashank; Kondekar, Pravin N.

    2017-02-01

    Strained SOI (SSOI) n-channel trigate FinFET is designed with asymmetrically doped stacked channels along the fin height. The OFF current is reduced with respect to lightly doped uniform SSOI FinFET because of band gap modification, originated between highly doped uniaxial strained and lightly doped Si fin. Through TCAD simulation it is observed that for the stacked devices the OFF current is reduced by more than 47%. The performances are also compared with highly doped uniform SSOI FinFETs and the results indicated that these devices have lesser random dopant variation at a moderate cost of ON and OFF current.

  4. SOI/MDI studies of active region seismology and evolution

    NASA Technical Reports Server (NTRS)

    Tarbell, Ted D.; Title, Alan; Hoeksema, J. Todd; Scherrer, Phil; Zweibel, Ellen

    1995-01-01

    The solar oscillations investigation (SOI) will study solar active regions using both helioseismic and conventional observation techniques. The Michelson Doppler imager (MDI) can perform Doppler continuum and line depth imagery and can produce longitudinal magnetograms, showing either the full disk or a high resolution field of view. A dynamics program of continuous full disk Doppler observations for two months per year, campaign programs of eight hours of continuous observation per day, and a synoptic magnetic program of about 15 full disk magnetograms per day, are planned. The scientific plans, measurements and observation programs, are described.

  5. Improving breakdown voltage performance of SOI power device with folded drift region

    NASA Astrophysics Data System (ADS)

    Qi, Li; Hai-Ou, Li; Ping-Jiang, Huang; Gong-Li, Xiao; Nian-Jiong, Yang

    2016-07-01

    A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V. Project supported by the Guangxi Natural Science Foundation of China (Grant Nos. 2013GXNSFAA019335 and 2015GXNSFAA139300), Guangxi Experiment Center of Information Science of China (Grant No. YB1406), Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China, Key Laboratory of Cognitive Radio and Information Processing (Grant No. GXKL061505), Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China (Grant No. 2014KFMS04), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

  6. A novel nanoscale SOI MOSFET with Si embedded layer as an effective heat sink

    NASA Astrophysics Data System (ADS)

    Anvarifard, Mohammad K.; Orouji, Ali A.

    2015-08-01

    A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications.

  7. Single-event-transient effects in sub-70 nm bulk and SOI FinFETs

    NASA Astrophysics Data System (ADS)

    El Mamouni, Farah

    After fourteen years of research and investigations by engineers in the university and industry communities, FinFET devices are finally ready to use in products [1-2]. FinFET technologies have been demonstrated to outperform planar technologies for high speed, low power and high performance applications, while maintaining the shrinking trends of microelectronics (beyond 32 nm) for at least the next two to three technology generations. These promising findings were enough for leading chip manufacturers like Intel to announce their plans to mass-produce FinFETs in the near future [3-4]. However, the device response in extreme environments (i.e., space) is still not well understood. Exploring the behavior of FinFETs in such environments is also important for the aerospace and medical industries, where unhardened commercial off the shelf (COTS) electronics are used. The objective of this work is to explore the transient electrical behavior of FinFET devices in both bulk and SOI technologies in radiation-rich environments through laser and heavy ion testing. A further objective of this work is to contribute to improving the performance of FinFET devices, in particular in harsh environments. Indeed, the new results obtained in this work identify the physical regions in the devices that are most sensitive to radiation effects and how they affect the radiation response. The findings will help engineers to design new generations of FinFET devices with higher tolerance to radiation effects.

  8. SOI back reflector for Tb-doped oxide electroluminescent devices

    NASA Astrophysics Data System (ADS)

    Saini, Harjinder Singh; MacElwee, T. W.; Rankin, A.; Wojcik, J.; Miles, A. M.; Tarr, N. G.; Mascher, P.

    2011-08-01

    Electroluminescent devices based on light emission from Tb-doped SiO2 incorporated in a MOS capacitor structure have been formed on SOI substrates. It is shown that with appropriate choice of Si film and buried oxide thickness the SOI substrate can serve as a quarter-wave high-low-high index back reflector. Analysis predicts this back reflector can boost total light output integrated over the Tb emission spectrum by approximately 35% compared to a bulk substrate control device. Experimental devices using 100 nm thick PECVD SiO2 emitting layers doped with 1% Tb were fabricated on substrates with nominal 32 and 108 nm Si film thickness (corresponding to approximately λ/4 and 3λ/4 at the Tb emission peak). The Si films were doped to 1019 - 1020 cm-3 by As implantation. Uniform bright green electroluminescence was obtained from 250 μm square devices, demonstrating that current crowding is not an issue even with such a thin Si film. The comparison of output spectra for thick and thin Si films demonstrates that optical absorption in the heavily doped Si film does not seriously degrade the light output of the devices.

  9. Contactless electrical characterization of surface and interface of SOI materials

    NASA Astrophysics Data System (ADS)

    Nakamura, S.; Watanabe, D.; En, A.; Suhara, M.; Okumura, T.

    2003-06-01

    Electronic properties of the surface as well as the interface of silicon-on-insulator (SOI) materials have been characterized by the Kelvin method combined with surface photovoltage (SPV) measurements. In order to separate the interface properties from the surface ones, we used the data for the bulk Si surface, which was treated in the same manner, i.e. dipping in a diluted HF solution, as for the SOI surface. From the temperature dependence of the SPV for the bulk Si, the values of the built-in potential, the surface state density and the surface recombination velocity were determined to be about 0.60 eV, 6×10 11 cm -2 and 6×10 3 cm/s, respectively, for the HF-treated Si surface. By taking these values into account, we analyzed the SPV data for separation by implanted oxygen (SIMOX) wafer. The values of the interface state density and the interface recombination velocity at the buried-oxide/SIMOX interface were estimated to be about 3×10 12 cm -2 and 3×10 4 cm/s, respectively.

  10. Parasitic bipolar effect in ultra-thin FD SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Liu, F. Y.; Ionica, I.; Bawedin, M.; Cristoloveanu, S.

    2015-10-01

    The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5-10 nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond VD > 1.0 V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations.

  11. Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

    NASA Astrophysics Data System (ADS)

    Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

    2017-07-01

    Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

  12. Total ionizing dose (TID) effect and single event effect (SEE) in quasi-SOI nMOSFETs

    NASA Astrophysics Data System (ADS)

    Tan, Fei; Huang, Ru; An, Xia; Wu, Weikang; Feng, Hui; Huang, Liangxi; Fan, Jiewen; Zhang, Xing; Wang, Yangyuan

    2014-01-01

    This paper studies the total ionizing dose (TID) and single event effect (SEE) in quasi-SOI nMOSFETs for the first time. After exposure to gamma rays, the off-state leakage current (Ioff) of a quasi-SOI device increases with the accumulating TID, and the on-state bias configuration is shown to be the worst-case bias configuration during irradiation. Although an additional TID-sensitive region is introduced by the unique structure of the quasi-SOI device, the influence of positive charge trapped in L-type oxide layers on the degradation of device performance is neglectable. Since the TID-induced leakage path in the quasi-SOI device is greatly reduced due to the isolation of L-type oxide layers, the TID-induced Ioff degradation in the quasi-SOI device is greatly suppressed. In addition, 3D simulation is performed to investigate the SEE of the quasi-SOI device. The full-width at half-maximum (FWHM) of worst-case drain current transient and collected charges of the quasi-SOI device after single-ion-striking is smaller than in a bulk Si device, indicating that the quasi-SOI device inherits the advantage of an SOI device in single event transient immunity. Therefore, the quasi-SOI device, which has improved electrical properties and radiation-hardened characteristics for both TID and SEE, can be considered as one of the promising candidates for space applications.

  13. Guidance, Navigation and Control Digital Emulation Technology Laboratory

    NASA Astrophysics Data System (ADS)

    Alford, Cecil O.; Chamdani, J. I.; Huang, T. C.; Kubota, T.; Ghannadian, F.

    1994-09-01

    The contract began with seven tasks: (1) Digital Emulation Facility; (2) FPA Seeker Emulator Development; (3) Special Studies; (4) Software Development; (5) Automated Input; (6) PFP Technology; and (7) GN and C Processor Development. These tasks were developed through the first two years of the contract when virtually all funding was removed. Two additional tasks have been developed since the funding cut. The first was a speed test on the rad-hard FPU chip developed by Harris. A summary of this testing and the associated report is given in Section 2. The second task is the development of an FPA Test System.

  14. Heterojunction fully depleted SOI-TFET with oxide/source overlap

    NASA Astrophysics Data System (ADS)

    Chander, Sweta; Bhowmick, B.; Baishya, S.

    2015-10-01

    In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

  15. Temperature analysis of Ge/Si heterojunction SOI-Tunnel FET

    NASA Astrophysics Data System (ADS)

    Chander, Sweta; Sinha, Sanjeet Kumar; Kumar, Sanjay; Singh, Prince Kumar; Baral, Kamalaksha; Singh, Kunal; Jit, Satyabrat

    2017-10-01

    Temperature is a thermal parameter which affects the device performance. This paper presents the impact of the temperature variation on the electrical characteristics such as tunneling width, subthreshold swing, threshold voltage, and ION /IOFF ratio of Ge/Si heterojunction Silicon on Insulator (SOI) Tunnel Field Effect Transistor (TFET) for different drain voltages. The device exhibits better performance in comparison with homojunction of the same device for different temperatures. This study reveals that OFF current of the device is independent of drain voltage variation irrespective of temperature variation. A small change in the subthreshold swing (SS) with temperature variation shows the weaker dependence of SS on temperature. The analog performance parameters such as transconductance, output transconductance, gate capacitance, and transconductance-to-drain-current ratio of the device are also examined. A small variation in analog parameters with temperature variation shows that the device could be used for the high-temperature analog circuit applications. A broad range of temperature from 200 K to 400 K has been used to analyze the performance of the device using Synopsys Technology Computer Aided Design (TCAD) simulation tool.

  16. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

  17. Pulse quenching induced by multi-collection effects in 45 nm silicon-on-insulator technology

    NASA Astrophysics Data System (ADS)

    Artola, L.; Hubert, G.

    2016-12-01

    This paper presents the analysis of pulse quenching effects induced in silicon-on-insulator (SOI) technology. Simulation results emphasize the need to consider multi-collection effects in the occurrence mechanisms of single event transients (SET) in very large scaling integration (VLSI) components even with SOI technologies, which is known to be initially less sensitive to soft errors (SE). The impacts of gate-to-gate spacing and voltage scaling on the SET occurrence and characteristics have been highlighted. The simulations have been performed with the soft error prediction tool MUSCA SEP3 developed for digital complementary metal oxide semiconductor (CMOS) technologies (SOI, Bulk).

  18. Fabrication and characterization of an SOI MEMS gyroscope

    NASA Astrophysics Data System (ADS)

    Weiwei, Zhong; Guowei, Han; Chaowei, Si; Jin, Ning; Fuhua, Yang

    2013-06-01

    This paper presents an SOI (silicon on insulator) MEMS (micro-electro-mechanical systems) vibratory gyroscope that was fabricated using bulk micromachining processes. In the gyroscope architecture, a frame structure that nests the proof mass is used to decouple the drive motion and sense motion. This approach ensures that the drive motion is well aligned with the designed drive axis, and minimizes the actual drive motion component along the sense detection axis. The thickness of the structural layer of the device is 100 μm, which induces a high elastic stiffness in the thickness direction, so it can suppress the high-order out-of-plane resonant modes to reduce deviation. In addition, the dynamics of the gyroscope indicate that higher driving mass brings about higher sensing displacements. The thick structural layer can improve the output of the device by offering a sufficient mass weight and large sensing capacitance. The preliminary test results of the vacuum packaged device under atmospheric pressure will be provided. The scale factor is 1.316 × 10-4 V/(deg/s), the scale factor nonlinearity and asymmetry are 1.87% and 0.36%, the zero-rate offset is 7.74 × 10-4 V, and the zero-rate stability is 404 deg/h, respectively.

  19. High performance SOI microring resonator for biochemical sensing

    NASA Astrophysics Data System (ADS)

    Ciminelli, C.; Dell'Olio, F.; Conteduca, D.; Campanella, C. M.; Armenise, M. N.

    2014-07-01

    In this work we have investigated different silicon-on-insulator (SOI) microcavities based on a planar geometry having a footprint on chip as small as 100 μm2 with a ring, disk and hybrid configurations with the aim of being poorly intrusive for both in-body and out-of-body biosensing purposes. Accurate numerical results have been achieved by using the 3D finite element method and compared to 3D finite discrete time domain ones with a good agreement for both methods. The most promising resonator among the devices we have analyzed shows a Q-factor of the order of 105, that allows a limit of detection for the sensor equal to 10-6 RIU and a sensor sensitivity of 120 nm/RIU. The resonator has been designed for glucose biosensing, considering both the homogeneous sensing and the surface one, that enhances the sensor selectivity by the device functionalization with a glucose-oxidase (GOD) layer. The glucose concentration has been evaluated both with the microcavity surrounded by a water solution and with water only in the inner part of the cavity.

  20. Germanium on double-SOI photodetectors for 1550-nm operation

    NASA Astrophysics Data System (ADS)

    Dosunmu, Olufemi I.; Cannon, Douglas D.; Emsley, Matthew K.; Ghyselen, Bruno; Liu, Jifeng; Kimerling, Lionel C.; Unlu, M. S.

    2004-06-01

    We have fabricated and characterized the first resonant cavity enhanced (RCE) germanium photodetectors on double silicon-on-insulator substrates (Ge/DSOI) for operation around the 1550 nm communication wavelength. The Ge layer is grown through a novel two-step UHV/CVD process, while the underlying double-SOI substrate is formed through an ion-cut process. Absorption measurements of an undoped Ge-on-Si (Ge/Si) structure reveal a red-shift of the Ge absorption edge in the NIR, due primarily to a strain-induced bandgap narrowing within the Ge film. By using the strained-Ge absorption coefficients extracted from the absorption measurements, in conjunction with the known properties of the DSOI substrate, we were able to design strained-Ge/DSOI photodetectors optimized for 1550 nm operation. We predict a quantum efficiency of 76% at 1550 nm for a Ge layer thickness of only 860 nm as a result of both strain-induced and resonant cavity enhancement, compared to 2.3% for the same unstrained Ge thickness in a single-pass configuration. We also estimate a transit-time limited bandwidth of 28 GHz. Although the fabricated Ge/DSOI photodetectors were not optimized for 1550 nm operation, we were able to demonstrate an over four-fold improvement in the quantum efficiency, compared to its single-pass counterpart.

  1. Scaling issues for analogue circuits using Double Gate SOI transistors

    NASA Astrophysics Data System (ADS)

    Lim, Tao Chuan; Armstrong, G. Alastair

    2007-02-01

    This work presents a systematic analysis on the impact of source-drain engineering using gate "non-overlapped" on the RF performance of nano-scaled fully depleted Double Gate SOI transistors, when used in the design of a typical two stage Operational Transconductance Amplifier (OTA). It is evident that for a gate length less than 40 nm, the incorporation of optimal source-drain engineering requiring a spacer length, which may exceed the length of the gate, is particularly beneficial in analogue applications. Lengthening the spacer reduces gate capacitance in the weak/moderate inversion region more than transconductance, improving cut-off frequency fT. This improvement is particularly significant in a circuit application where an optimal spacer of 1.5 times the gate length is proposed. This gate under-lapped concept with extended spacer can also significantly enhance DC gain of the OTA, by increasing the Early Voltage, while maximising the transconductance to current ratio in the weak to moderate inversion, close to threshold voltage. With optimally designed devices, the sensitivity of OTA circuit performance to doping profile is shown to be relatively low.

  2. Compensation for radiation damage of SOI pixel detector via tunneling

    NASA Astrophysics Data System (ADS)

    Yamada, M.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Ikegami, Y.; Kurachi, I.; Miyoshi, T.; Nishimura, R.; Tauchi, K.; Tsuboyama, T.

    2016-09-01

    We are developing a method for removing holes trapped in the oxide layer of a silicon-on-insulator (SOI) monolithic pixel detector after irradiation. Radiation that passes through the detector generates positive charge by trapped holes in the buried oxide layer (BOX) underneath the MOSFET. The positive potential caused by these trapped holes modifies the characteristics of the MOSFET of the signal readout circuit. In order to compensate for the effect of the positive potential, we tried to recombine the trapped holes with electrons via Fowler-Nordheim (FN) tunneling. By applying high voltage to the buried p-well (BPW) under the oxide layer with the MOSFET fixed at 0 V, electrons are injected into the BOX by FN tunneling. X-rays cause a negative shift in the threshold voltage Vth of the MOSFET. We can successfully recover Vth close to its pre-irradiation level after applying VBPW ≥ 120 V. However, the drain leakage current increased after applying VBPW; we find that this can be suppressed by applying a negative voltage to the BPW.

  3. A new latch-free LIGBT on SOI with very high current density and low drive voltage

    NASA Astrophysics Data System (ADS)

    Olsson, J.; Vestling, L.; Eklund, K.-H.

    2016-01-01

    A new latch-free LIGBT on SOI is presented. The new device combines advantages from both LDMOS as well as LIGBT technologies; high breakdown voltage, high drive current density, low control voltages, at the same time eliminating latch-up problems. The new LIGBT has the unique property of independent scaling of the input control device, i.e. LDMOS, and the output part of the device, i.e. the p-n-p part. This allows for additional freedom in designing and optimizing the device properties. Breakdown voltage of over 200 V, on-state current density over 3 A/mm, specific on-resistance below 190 mΩ mm2, and latch-free operation is demonstrated.

  4. SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

    NASA Astrophysics Data System (ADS)

    Hubert, Alexandre; Bawedin, Maryline; Guegan, Georges; Ernst, Thomas; Faynot, Olivier; Cristoloveanu, Sorin

    2011-11-01

    Several concepts of capacitor-less single-transistor (1T) DRAM have recently been proposed to overcome the scaling limitations of bulk DRAMs. In this study, we focus on the comparison of two programming mechanisms of 1T-DRAMs: the impact ionization (II), the most common mechanism to store charges in the body of the cell, and the meta-stable dip (MSD) effect. The impact of the gate length and channel thickness reduction on both the II and the MSD programming mechanisms has been investigated using dynamic measurements on conventional Fully Depleted SOI (FDSOI) transistors. In the absence of any customization of technology and device architecture, it is found that MSD programming is superior and demonstrates higher resilience to the MOSFET scaling. These promising performances arise from the dynamic coupling between the front and back gates and from the use of low drain bias.

  5. A novel low turnoff loss carrier stored SOI LIGBT with trench gate barrier

    NASA Astrophysics Data System (ADS)

    He, Yitao; Qiao, Ming; Zhang, Bo; Li, Zhaoji

    2016-01-01

    A novel low turnoff loss carrier stored (CS) silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with trench gate barrier (CS SOI TGLIGBT) is proposed. The proposed CS SOI TGLIGBT features a trench gate inserted between the pwell and n-drift. Firstly, the trench gate acts as a hole barrier to prevent the hole from injecting directly into pwell in the on-state, which introduces carrier stored effect and realizes a uniform carriers distribution in the n-drift region, resulting in a decrease of the on-state voltage drop (Von). Secondly, due to the carrier stored effect and the assisted depleted effect induced by the trench gate, large number of carriers can be quickly removed at the initial turnoff process, leading to a decrease of turnoff loss (Eoff). The influences of gate trench barrier on Von and Eoff are investigated. Simulation results show that the proposed CS SOI TGLIGBT can achieve a 59% lower Eoff compared with the conventional SOI trench gate LIGBT at the same Von of 1.15 V.

  6. Amended Electric Field Distribution: A Reliable Technique for Electrical Performance Improvement in Nano scale SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Ramezani, Zeinab; Orouji, Ali A.

    2017-04-01

    To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with an amended electric field in the channel for improved electrical and thermal performance, with an emphasis on current leakage improvement. The amended electric field leads to lower electric field crowding and thereby we assume enhanced reliability, leakage current, gate-induced drain leakage (GIDL), and electron temperature. To modify the electric field distribution, an additional rectangular metal region (RMR) is utilized in the buried oxide of the SOI MOSFET. The location and dimensions of the RMR have been carefully optimized to achieve the best results. The electrical, thermal, and radiofrequency characteristics of the proposed structure were analyzed using two-dimensional (2-D) numerical simulations and compared with the characteristics of the conventional, fully depleted SOI MOSFET (C-SOI). Also, critical short-channel effects (SCEs) such as threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope degradation, hot-carrier effect, GIDL, and leakage power consumption are improved. According to the results obtained, the proposed nano SOI MOSFET is a reliable device, especially for use in low-power and high-temperature applications.

  7. Characteristics analysis of SOI waveguide Michelson interferometers for developing biomedical fiber temperature-sensing head

    NASA Astrophysics Data System (ADS)

    Tsao, Shyh-Lin; Lee, Shin-Ge

    2000-07-01

    A new silicon-on-insulator (SOI) waveguide Michelson interferometer with Bragg reflective gratings as a biomedical temperature sensing array head is presented in this paper. The waveguide Bragg reflective gratings work as mirrors for adjusting the transfer function of the Michelson interferometer sensor. We will show the comparison of the temperature sensing accuracies of the fiber Bragg grating and SOI waveguide Michelson interferometers in biomedical applications. The grating length and perturbation period of waveguide Bragg grating in SOI waveguide Michelson interferometer will increase as temperature rises, that is, the thermal effects of the reflective Bragg gratings are considered in our analysis. According to the numerical analysis of power reflective spectra of waveguide Michelson interferometers, the temperature sensing waveguide of the Michelson interferometer can improve at least 20 times than the traditional fiber Bragg grating temperature sensor. Moreover, the SOI waveguide interferometer sensor we designed presents high sensitivity than pure single waveguide Bragg grating sensor and fiber Bragg grating sensor by adjusting the length of the two interferometric arms. The full width of half maximum (FWHM) of the frequency responses of passband of SOI waveguide Michelson interferometer can be designed smaller than fiber and waveguide Bragg grating sensors for sensitivity improvement.

  8. Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Wu, Weimin; Yao, Wei; Gildenblat, Gennady

    2010-05-01

    We present a complete surface-potential-based compact model of dynamically depleted (DD) SOI MOSFETs. The surface potential equation of DD-SOI MOSFETs was reconditioned to avoid the unphysical behaviors near the flat-band voltage. In order to capture the dynamic depletion effect, the coupling equation for the front and back surface potentials was reformulated to include the back gate effect, which is not available in other surface-potential-based DD-SOI compact models. The new formulation of surface potential and coupling equations was verified by comparing with numerical computations combining the Pao-Sah double integral based formulation and the exact coupling equation. To obtain explicit expressions for the terminal charges and drain current, a new symmetric linearization method has been proposed. The complete model, PSP-SOI DD is implemented in the context of the PSP and PSP-SOI PD models and includes all the secondary effects, floating body simulation capability, etc. The new model has been extensively verified with 2D TCAD simulation results and accurately captures the manifestation of the dynamic depletion effect observed in the device characteristics.

  9. Design and implementation of a torque-enhancement 2-axis magnetostatic SOI optical scanner

    NASA Astrophysics Data System (ADS)

    Tang, Tsung-Lin; Hsu, Chia-Pao; Chen, Wen-Chien; Fang, Weileun

    2010-02-01

    This study demonstrates the torque-enhancement design for a 2-axis magnetostatic SOI scanner driven by a double-side electroplating ferromagnetic film. The present design has two merits: (1) the slender ferromagnetic material patterns with higher length-to-width ratio enhance the magnetization, (2) the backside electroplating of the ferromagnetic film increases the volume of the ferromagnetic materials. This study also establishes the fabrication processes to implement the proposed design. The processes also have two merits: (1) the handle-layer of the SOI wafer is exploited as the shadow mask to pattern the seed-layer at the backside of the device layer, (2) the device layer of the SOI wafer acts as the cathode to enable simultaneous double-side electroplating. In applications, a 2-axis SOI scanner was implemented and characterized. Measurements show a 149% torque enhancement from the double-side electroplating design. The vertical slender ferromagnetic material patterns further increase the magnetostatic torque to 211%. This study also successfully demonstrates the Lissajous scanning using the presented 2-axis SOI scanner.

  10. Higher-Order Abilities Conceptualized within Guilford's Structure-of-Intellect (SOI) Model for a Sample of United States Coast Guard Academy Cadets: A Reanalysis of an SOI Data Base.

    ERIC Educational Resources Information Center

    Chen, Chin-Yi; Michael, William B.

    1993-01-01

    Empirical validation of the first-order and higher-order factor structures of the structure-of-intellect (SOI) model was provided by reanalysis of a database of 39 measures administered to 178 Coast Guard Cadets. Results suggest that SOI could be reconceptualized as a pyramid-like hierarchical theory of intelligence. (SLD)

  11. Higher-Order Abilities Conceptualized within Guilford's Structure-of-Intellect (SOI) Model for a Sample of United States Coast Guard Academy Cadets: A Reanalysis of an SOI Data Base.

    ERIC Educational Resources Information Center

    Chen, Chin-Yi; Michael, William B.

    1993-01-01

    Empirical validation of the first-order and higher-order factor structures of the structure-of-intellect (SOI) model was provided by reanalysis of a database of 39 measures administered to 178 Coast Guard Cadets. Results suggest that SOI could be reconceptualized as a pyramid-like hierarchical theory of intelligence. (SLD)

  12. Analysis of subthreshold conduction in short-channel recessed source/drain UTB SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Sviličić, B.; Jovanović, V.; Suligoj, T.

    2010-05-01

    The subthreshold conduction regime in short-channel recessed source/drain (ReS/D) ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFETs is studied. A physics-based model for the subthreshold slope of ReS/D UTB SOI MOSFETs is developed, based on an analytical solution of 2-D Poisson's equation for the front-gate and back-gate potential distributions. In order to verify the accuracy of the model, the calculated subthreshold slope values are compared with the results obtained by Medici 2-D numerical device simulator over a wide range of different device structures, and very good agreement is obtained down to channel lengths of sub-30 nm. The model is given in explicit form without any fitting parameters and requires no iterative calculation, thus making it ideally suitable for fast prediction and evaluation of device design criteria for optimal scaling of the ReS/D UTB SOI MOSFETs.

  13. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    NASA Astrophysics Data System (ADS)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  14. Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Luo, Jie-Xin; Chen, Jing; Zhou, Jian-Hua; Wu, Qing-Qing; Chai, Zhan; Yu, Tao; Wang, Xi

    2012-05-01

    The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. ID hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the ID hysteresis. The experimental results show that the ID hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.

  15. A new fabrication process for the SOI-based miniature electric field sensor

    NASA Astrophysics Data System (ADS)

    Wei, Liu; Pengfei, Yang; Chunrong, Peng; Dongming, Fang; Shanhong, Xia

    2013-08-01

    This paper presents a new fabrication process for the SOI-based novel miniature electric field sensor. This new process uses polyimide film to release the SiO2 layer. Compared with the CO2 critical point release method, it significantly improves the device surface cleanliness and shortens the process flow. The impurity on the base layer is analyzed. The problem of peak and butterfly-type contamination occurring on the base layer of the SOI wafer during the DRIE process is discussed and solved by thickening the photoresist layer and coating with polyimide film twice. This new process could fabricate MEMS sensors and actuators such as SOI-based electric field sensors, gyroscopes, and micro mirrors and can be an alternative fabrication process compared to commercial SOIMUMPS fabrication processes.

  16. A novel high-performance high-frequency SOI MESFET by the damped electric field

    NASA Astrophysics Data System (ADS)

    Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

    2016-06-01

    In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

  17. Development of the Stress of Immigration Survey (SOIS): a Field Test among Mexican Immigrant Women

    PubMed Central

    Sternberg, Rosa Maria; Nápoles, Anna Maria; Gregorich, Steven; Paul, Steven; Lee, Kathryn A.; Stewart, Anita L.

    2016-01-01

    The Stress of Immigration Survey (SOIS) is a screening tool used to assess immigration-related stress. The mixed methods approach included concept development, pretesting, field-testing, and psychometric evaluation in a sample of 131 low-income women of Mexican descent. The 21-item SOIS screens for stress related to language; immigrant status; work issues; yearning for family and home country; and cultural dissonance. Mean scores ranged from 3.6 to 4.4 (1-5 scale, higher is more stress). Cronbach's alphas >.80 for all sub-scales. The SOIS may be a useful screening tool for detecting high levels of immigration-related stress in low-income Mexican immigrant women. PMID:26605954

  18. Novel Applications of a Thermally Tunable Bistable Buckling Silicon-on-Insulator (SOI) Microfabricated Membrane

    DTIC Science & Technology

    2015-09-17

    Starting with a clean silicon-on-insulator (SOI) wafer (1) a layer of photoresist is applied (2). The photoresist is patterned with a mask and UV...clean SOI wafer (1) a layer of photoresist is applied (2). The photoresist is patterned with a mask and UV light (3) and developed (4). A layer of metal...mask pattern illustrated by Figure 8. On a (100) silicon wafer , the (100) crystal plane is parallel to the surface of the wafer . The (111) crystal planes

  19. Modeling, and Experimental Measurements, of the SER Critical Charge (Qcrit) in Scaled, SOI, CMOS Devices

    DTIC Science & Technology

    2014-04-01

    Murray, Michael Gordon, John G. Massey, Kevin Stawiasz and Henry Tang IBM T.J. Watson Research Center P.O. Box 218 Route 134 Yorktown Heights, NY...34 IEEE Transactions on Device and Material Reliablity, vol. 11, no. 4, pp. 551-554, 2011 NSREC 2013 Short Course (Rodbell) IBM TJ Watson Research...upset. P. Oldiges, IBM Figure 1. SOI FinFET inverter modeling (latches) showing good SER immunity. SOI FinFETs should be acceptable for all terrestrial applications. 76

  20. Uniformity of the lasing wavelength of heterogeneously integrated InP microdisk lasers on SOI.

    PubMed

    Mechet, P; Raineri, F; Bazin, A; Halioua, Y; Spuesens, T; Karle, T J; Regreny, P; Monnier, P; Van Thourhout, D; Sagnes, I; Raj, R; Roelkens, G; Morthier, G

    2013-05-06

    We report a high lasing wavelength uniformity of optically pumped InP-based microdisk lasers processed with electron-beam lithography, heterogeneously integrated with adhesive bonding on silicon-on-insulator (SOI) waveguide circuits and evanescently coupled to an underlying waveguide. We study the continuous wave laser emission coupling out of the SOI via a grating coupler etched at one side of the waveguide, and demonstrate a standard deviation in lasing wavelength of nominally identical devices on the same chip lower than 500 pm. The deviation in the diameter of the microdisks as low as a few nanometers makes all-optical signal processing applications requiring cascadability possible.

  1. Body factor conscious modeling of single gate fully depleted SOI MOSFETs for low power applications

    NASA Astrophysics Data System (ADS)

    Kumar, Anil; Nagumo, Toshiharu; Tsutsui, Gen; Ohtou, Tetsu; Hiramoto, Toshiro

    2005-06-01

    Degradation of body factor (γ) and subthreshold factor (S) of single gate fully depleted SOI MOSFETs due to short channel effects has been studied analytically. The effect of source/drain fringing fields in buried oxide is found to play a more significant role in the reduction of body factor at smaller gate lengths. Present work provides the analytical expressions of effective back gate voltage, body factor and subthreshold factor of short channel fully depleted SOI MOSFETs. The results obtained are found in good approximation with 2D simulation.

  2. Simulation of dual-gate SOI MOSFET with different dielectric layers

    NASA Astrophysics Data System (ADS)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  3. Rad-hard vertical JFET switch for the HV-MUX system of the ATLAS upgrade Inner Tracker

    NASA Astrophysics Data System (ADS)

    Fernández-Martínez, P.; Ullán, M.; Flores, D.; Hidalgo, S.; Quirion, D.; Lynn, D.

    2016-01-01

    This work presents a new silicon vertical JFET (V-JFET) device, based on the trenched 3D-detector technology developed at IMB-CNM, to be used as a switch for the High-Voltage powering scheme of the ATLAS upgrade Inner Tracker. The optimization of the device characteristics is performed by 2D and 3D TCAD simulations. Special attention has been paid to the on-resistance and the switch-off and breakdown voltages to meet the specific requirements of the system. In addition, a set of parameter values has been extracted from the simulated curves to implement a SPICE model of the proposed V-JFET transistor. As these devices are expected to operate under very high radiation conditions during the whole experiment life-time, a study of the radiation damage effects and the expected degradation of the device performance is also presented at the end of the paper.

  4. Symmetrical SOI MESFET with a dual cavity region (DCR-SOI MESFET) to promote high-voltage and radio-frequency performances

    NASA Astrophysics Data System (ADS)

    Anvarifard, Mohammad K.

    2016-10-01

    A novel symmetrical SOI-MESFET is reported to enhance high-voltage and radio-frequency performances, successfully. Two p-type cavity regions with certain features are embedded in the proposed structure to control the channel region. The cavity regions absorb the channel potential lines resulting in an evener potential profile throughout the channel region. Hence, the critical electric field at the end of gate edge near the drain will be considerably reduced thus increasing the breakdown voltage, finally. A comprehensive comparison in terms of breakdown voltage, radio-frequency parameters, drain-source conductance and minimum noise figure shows that the reported new device reaches a superior electrical performance when compared with a conventional SOI MESFET.

  5. Cassini-VIMS Observations of Saturn's Rings at SOI

    NASA Astrophysics Data System (ADS)

    Nicholson, P. D.; Clark, R. N.; Cruikshank, D. P.; Showalter, M. R.; Sicardy, B.; Cassini VIMS

    2004-11-01

    Following the Cassini spacecraft's Saturn Orbit Insertion (SOI) burn on 1 July 2004, the Visual and Infrared Mapping Spectrometer (VIMS) obtained near-infrared spectra from 0.9 to 5.1 μ m in two continuous radial scans across the unlit side of the rings, at ranges of ˜30,000 km. The first scan covers the outer C and inner B rings at a phase angle, α = 82o and an emission angle, e = 47o, while the second covers the Cassini Division and entire A ring at α = 59o and e = 63o. The solar incidence angle was 114o and the radial resolution of both scans is 15-20 km, with sampling intervals of 2-3 km. Structurally, the rings appear to have changed little, if at all, since the Voyager observations in 1980/81 and the 28 Sgr occultations in 1989. This similarity extends even to the quasi-irregular structure which characterizes the inner B ring on scales of ˜100 km. Spectrally, all regions of the rings scanned are dominated by water ice, with prominent absorption bands at 1.55, 2.0 and 3.0 μ m, as well as weaker bands at 1.04 and 1.25 μ m seen primarily in the A and B rings. The ice bands are strongest in the middle A ring, somewhat weaker in the B ring, and much weaker in the C ring and Cassini Division. Locally, however, the fractional band depths appear to be independent of optical depth, suggesting that the light diffusely transmitted through the rings at moderate phase angles is dominated by single scattering. Regionally, the transitions between the C and B rings and between the Cassini Division and A ring are marked by gradual changes in band depth over radial distances of a few thousand km, perhaps indicative of ballistic redistribution of material. A broad reflectance maximum at 3.6 μ m, characteristic of ice grain sizes less than 100 μ m, is prominent everywhere but particularly strong in the outermost parts of the A ring, exterior to the Encke Gap. Besides water ice, the most noteworthy spectral feature is a broad, shallow absorption in the 0.9-1.8 μ m

  6. Cassini-VIMS Observations of Saturn's Rings at SOI.

    NASA Astrophysics Data System (ADS)

    Nicholson, P. D.; Brown, R. H.; Clark., R. N.; Cruikshank, D. P.; Showalter, M. R.; Sicardy, B.

    2004-12-01

    Following the Cassini spacecraft's Saturn Orbit Insertion (SOI) burn on 1 July 2004, the Visual and Infrared Mapping Spectrometer (VIMS) obtained near-infrared spectra from 0.9 to 5.1~μ m in two continuous radial scans across the unlit side of the rings, at ranges of ˜30,000~km. The first scan covers the outer C and inner B rings at a phase angle, α = 82o and an emission angle, e = 47o, while the second covers the Cassini Division and entire A ring at α = 59o and e = 63o. The solar incidence angle was 114o and the radial resolution of both scans is 15-20~km, with sampling intervals of 2-3~km. Structurally, the rings appear to have changed little, if at all, since the Voyager observations in 1980/81 and the 28~Sgr occultations in 1989. This similarity extends even to the quasi-irregular structure which characterizes the inner B ring on scales of ˜100~km. Spectrally, all regions of the rings scanned are dominated by water ice, with prominent absorption bands at 1.55, 2.0 and 3.0~μ m, as well as weaker bands at 1.04 and 1.25~μ m seen primarily in the A and B rings. The ice bands are strongest in the middle A ring, somewhat weaker in the B ring, and much weaker in the C ring and Cassini Division. However, the transitions between the C and B rings and between the Cassini Division and A ring are marked by gradual changes in band depth over radial distances of a few thousand km, perhaps indicative of ballistic redistribution of material. Besides water ice, the most noteworthy spectral feature is a broad, shallow absorption in the 0.9-1.8~μ m region which we tentatively attribute to Fe-bearing minerals, most likely silicates. This feature is seen primarily in the outer C ring and the Cassini Division, but like the ice band depths it pays scant attention to structural boundaries. This work was supported by NASA and ESA under contracts with the Cassini-Huygens Project.

  7. Silicon-on-insulator technology

    NASA Astrophysics Data System (ADS)

    Partridge, S. L.

    1986-05-01

    The main fabrication techniques for and the principal advantages of silicon-on-insulator (SOI) technology for advanced integrated circuits are reviewed, placing particular emphasis on CMOS. The origin of the advantages of SOI in comparison to single crystal silicon are considered, and the competing techniques for substrate preparation are described, including epitaxial silicon-on-sapphire, recrystallized polycrystalline silicon, buried dielectric formation by ion implantation, and oxidized porous silicon. The performance attributes to be achieved in a number of different application areas, such as VLSI, high-performance products, and space and defense electronics, are discussed in detail.

  8. GSFC Cutting Edge Avionics Technologies for Spacecraft

    NASA Technical Reports Server (NTRS)

    Luers, Philip J.; Culver, Harry L.; Plante, Jeannette

    1998-01-01

    With the launch of NASA's first fiber optic bus on SAMPEX in 1992, GSFC has ushered in an era of new technology development and insertion into flight programs. Predating such programs the Lewis and Clark missions and the New Millenium Program, GSFC has spearheaded the drive to use cutting edge technologies on spacecraft for three reasons: to enable next generation Space and Earth Science, to shorten spacecraft development schedules, and to reduce the cost of NASA missions. The technologies developed have addressed three focus areas: standard interface components, high performance processing, and high-density packaging techniques enabling lower cost systems. To realize the benefits of standard interface components GSFC has developed and utilized radiation hardened/tolerant devices such as PCI target ASICs, Parallel Fiber Optic Data Bus terminals, MIL-STD-1773 and AS1773 transceivers, and Essential Services Node. High performance processing has been the focus of the Mongoose I and Mongoose V rad-hard 32-bit processor programs as well as the SMEX-Lite Computation Hub. High-density packaging techniques have resulted in 3-D stack DRAM packages and Chip-On-Board processes. Lower cost systems have been demonstrated by judiciously using all of our technology developments to enable "plug and play" scalable architectures. The paper will present a survey of development and insertion experiences for the above technologies, as well as future plans to enable more "better, faster, cheaper" spacecraft. Details of ongoing GSFC programs such as Ultra-Low Power electronics, Rad-Hard FPGAs, PCI master ASICs, and Next Generation Mongoose processors.

  9. Diamond-shaped body contact for on-state breakdown voltage improvement of SOI LDMOSFET

    NASA Astrophysics Data System (ADS)

    Daghighi, Arash; Hematian, Hadi

    2017-03-01

    In this paper, we report a diamond-shaped body contact (DSBC) for silicon-on-insulator (SOI) LDMOSFET. Several DSBC devices along with conventional body contact (CBC) structures are laid out using 0.35 μm SOI MOSFET foundry process. The DSBC device is designed using the same standard layers as in the CBC structure and the contact layout is adapted to process design rules. Experimental characterization of the CBC and DSBC devices in terms of off-state breakdown voltage (BVoff), on-state breakdown voltage (BVon), on-resistance (Ron) and device foot print showed 19% improvement in BVon compared DSBC device with that of the CBC structure. BVoff and Ron of both of the devices are identical. The device foot print is smaller in DSBC device by 11% compared with that of the CBC structure leading to enhanced "On-resistance × Area" figure of merit where smaller high voltage SOI LDMOSEFT reduces the area and cost of power integrated circuits. In order to explain BVon improvement of DSBC structures, three-dimensional (3-D) device simulation is carried out to clarify the lateral BJT action and breakdown mechanism. It is demonstrated that the number of P+ diffusions in DSBC device can be increased to improve BVon without increasing "On-resistance × Area". The on-state breakdown voltage improvement and area efficiency of the diamond-shaped body contact proposes it as a promising candidate for reliable operation of SOI LDMOSFET.

  10. Strained Germanium Quantum Well PMOSFETs on SOI with Mobility Enhancement by External Uniaxial Stress

    NASA Astrophysics Data System (ADS)

    Liu, Yan; Niu, Jiebin; Wang, Hongjuan; Han, Genquan; Zhang, Chunfu; Feng, Qian; Zhang, Jincheng; Hao, Yue

    2017-02-01

    Well-behaved Ge quantum well (QW) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) were fabricated on silicon-on-insulator (SOI) substrate. By optimizing the growth conditions, ultrathin fully strained Ge film was directly epitaxially grown on SOI at about 450 °C using ultra-high vacuum chemical vapor deposition. In situ Si2H6 passivation of Ge was utilized to form a high-quality SiO2/Si interfacial layer between the high-κ dielectric and channels. Strained Ge QW pMOSFETs achieve the significantly improved effective hole mobility μ eff as compared with the relaxed Si and Ge control devices. At an inversion charge density of Q inv of 2 × 1012 cm-2, Ge QW pMOSFETs on SOI exhibit a 104% μ eff enhancement over relaxed Ge control transistors. It is also demonstrated that μ eff of Ge pMOSFETs on SOI can be further boosted by applying an external uniaxial compressive strain.

  11. Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer

    NASA Astrophysics Data System (ADS)

    He, Yi-Tao; Qiao, Ming; Zhang, Bo

    2016-12-01

    A novel ultralow turnoff loss dual-gate silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored (CS) layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the carrier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop (Von). In the off-state, due to the uniform carrier distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss (Eoff). Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoff and Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61376080 and 61674027) and the Natural Science Foundation of Guangdong Province, China (Grant Nos. 2014A030313736 and 2016A030311022).

  12. A novel four-quadrant analog multiplier using SOI four-gate transitors (G4-FETs)

    NASA Technical Reports Server (NTRS)

    Akarvardar, K.; Chen, S.; Blalock, B. J.; Cristoloveanu, S.; Gentil, P.; Mojarradi, M.

    2005-01-01

    A novel analog muliplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers.

  13. Strained Germanium Quantum Well PMOSFETs on SOI with Mobility Enhancement by External Uniaxial Stress.

    PubMed

    Liu, Yan; Niu, Jiebin; Wang, Hongjuan; Han, Genquan; Zhang, Chunfu; Feng, Qian; Zhang, Jincheng; Hao, Yue

    2017-12-01

    Well-behaved Ge quantum well (QW) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) were fabricated on silicon-on-insulator (SOI) substrate. By optimizing the growth conditions, ultrathin fully strained Ge film was directly epitaxially grown on SOI at about 450 °C using ultra-high vacuum chemical vapor deposition. In situ Si2H6 passivation of Ge was utilized to form a high-quality SiO2/Si interfacial layer between the high-κ dielectric and channels. Strained Ge QW pMOSFETs achieve the significantly improved effective hole mobility μ eff as compared with the relaxed Si and Ge control devices. At an inversion charge density of Q inv of 2 × 10(12) cm(-2), Ge QW pMOSFETs on SOI exhibit a 104% μ eff enhancement over relaxed Ge control transistors. It is also demonstrated that μ eff of Ge pMOSFETs on SOI can be further boosted by applying an external uniaxial compressive strain.

  14. Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

    NASA Technical Reports Server (NTRS)

    Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

    2007-01-01

    We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

  15. A novel mechanism of ultrathin SOI synthesis by extremely low-energy hot O+ implantation

    NASA Astrophysics Data System (ADS)

    Hoshino, Yasushi; Yachida, Gosuke; Inoue, Kodai; Toyohara, Taiga; Nakata, Jyoji

    2016-08-01

    Extremely low-energy oxygen implantations at 10 keV in silicon were challengingly performed to directly synthesize ultrathin silicon-on-insulator (SOI) structure separated by a buried oxide (BOX) layer. We quantitatively investigated the optimum condition and the formation mechanism of homogeneous and continuous stoichiometric SOI/BOX structure. In this study, oxygen ions were implanted into Si(0 0 1) substrates with keeping the temperatures at 500, 800, and 1000 °C with ion-fluences from 0.5 to 2.0× {{10}17} ions cm-2. These samples were then postannealed at high temperatures from 950 to 1150 °C in Ar ambient for several hours. We found that ultrathin stoichiometric SOI/BOX structure with less than 20 nm thick was synthesized by oxygen implantation with an ion dose of 1.0× {{10}17} ions cm-2 from 500 °C to 800 °C followed by annealing at a significantly low temperature of 1050 °C for 5 h. According to the RBS-channeling analysis, the crystallinity was excellent as quality as that of the SOI structure formed by a wafer-bonding method. We found that the BOX layer was finally formed around the deeper end of the oxygen distribution in the as-implanted sample, though the depth of the BOX formation was much deeper than the projected range of oxygen and the damage peak of silicon. The formation process of the SOI/BOX structure proposed so far could not be applicable to the present conditions for ultrathin SOI/BOX synthesis by extremely low-energy implantation followed by low-temperature annealing. We thus suggested a novel mechanism of the ultrathin SOI/BOX synthesis as follows. The mechanism during the thermal treatment was demonstrated that the recrystallization of the damaged Si layers induced by ion irradiation took place from the very surface with relatively less irradiation-damages toward deeper layers with sweeping interstitial oxygen atoms, and the condensed oxygen atoms finally synthesized the stoichiometric BOX layer.

  16. Compact non-local modeling of impact ionization in SOI MOSFETs for optimal CMOS device/circuit design

    NASA Astrophysics Data System (ADS)

    Krishnan, S.; Fossum, J. G.

    1996-05-01

    A comprehensive but compact non-local model for impact ionization current in scaled SOI MOSFETs is developed. The model, applicable to both fully depleted and non-fully depleted SOI CMOS, is intended for device/circuit simulation and has been implemented as post-processing in a circuit simulator SOISPICE [J. G. Fossum, SOI-SPICE-4 ( FD/SOI and NFD/SOI MOSFET Models). University of Florida, Gainesville, FL (March 1995)]. The model is based on transforming the empirical field-dependent impact ionization rate into a carrier temperature-dependent one via a quasi-steady-state approximation of the energy balance equation. The model is valid for weak as well as strong inversion. It is verified via predictions of structure-dependent drain-source breakdown and current kinks in a variety of floating-body SOI MOSFETs. SOISPICE simulations reveal insight into the design optimization of scaled SOI CMOS devices and circuits in which the breakdown, due to the parasitic BJT driven by impact ionization, must be controlled.

  17. Swift heavy ion-induced recrysallization of silicon-on-insulator (SOI) structures

    NASA Astrophysics Data System (ADS)

    Virdi, G. S.; Pathak, B. C.; Avasthi, D. K.; Kanjilal, D.

    2002-02-01

    Buried Si 3N 4-Si interfaces and overlayer in silicon-on-insulator (SOI) structures were improved by irradiation with 100 MeV 107Ag after the synthesis of buried silicon nitride layers by high dose nitrogen ion-implantation. Auger electron spectroscopy (AES) depth profile analysis illustrates that the MeV heavy ions irradiation in the SOI structure, modifies the distribution of nitrogen that results in better stoichiometry of the buried silicon nitride layers and abrupt Si 3N 4-Si interfaces. Electron spin resonance (ESR) technique shows the improvement in the crystalline structure of the Si over layer. Current-voltage and high frequency capacitance-voltage ( C- V) characteristics were studied, and electrical breakdown measurements were performed on metal nitride silicon (MNS) structures fabricated after removing the Si over layer in the SOI structure. In the ion-beam irradiated SOI specimens, buried silicon nitride layer show a high breakdown field strength of 4.5-6.5 MV/cm as compared to that of 3.0-3.9 MV/cm in the unirradiated one. The C- V analysis of the MNS capacitors reveals that the buried Si 3N 4-Si substrate interface exhibits a better quality with reduced fixed insulator charge and interface state densities after the ion-beam irradiation. Mid-gap interface state density at the buried Si 3N 4-Si substrate interface was as low as 1.0×10 11 cm-2 V-2 after the ion-beam irradiation, which is comparable to that of silicon nitride films deposited on silicon (Si) by the conventional low pressure chemical vapor deposition technique. The role of MeV ion-beam irradiation in improving the properties of SOI structures has been discussed on the basis of various models.

  18. Improved reverse recovery characteristics of inAlN/GaN schottky barrier diode using a SOI substrate

    NASA Astrophysics Data System (ADS)

    Chiu, Hsien-Chin; Peng, Li-Yi; Wang, Hsiang-Chun; Kao, Hsuan-Ling; Wang, Hou-Yu; Chyi, Jen-Inn

    2017-10-01

    The low-frequency noise (LFN) and reverse recovery charge characteristics of a six-inch InAlN/AlN/GaN Schottky barrier diode (SBD) on the Si-on-insulator (SOI) substrate were demonstrated and investigated for the first time. Raman spectroscopy indicated that using SOI wafers lowered epitaxial stress. According to the DC and LFN measurements at temperatures ranging from 300 to 450 K, the InAlN/GaN SBD on the SOI substrate showed improved forward and reverse currents and achieved a lower reverse recovery charge, compared with a conventional device.

  19. Wafer bonding technology for silicon-on-lnsulator applications: A review

    NASA Astrophysics Data System (ADS)

    Mitani, Kiyoshi; Gösele, Ulrich M.

    1992-07-01

    School of Engineering, Duke University, Durham, North Carolina, 27706. The status of wafer bonding technology especially for silicon-on-insulator (SOI) materials is reviewed. General advantages of wafer bonding as well as specific problems of wafer bonding, such as interface bubble formation, and solutions for these problems are discussed. The specific requirements for SOI materials in terms of SOI layer thickness and the appropriate thinning procedures are dealt with. Interface properties such as bonding strength and electrical properties are also reviewed. Various device results are mentioned.

  20. A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

    PubMed

    Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

    2007-06-01

    waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

  1. Image based overlay measurement improvements of 28nm FD-SOI CMOS front-end critical steps

    NASA Astrophysics Data System (ADS)

    Dettoni, F.; Shapoval, T.; Bouyssou, R.; Itzkovich, T.; Haupt, R.; Dezauzier, C.

    2017-03-01

    Technology shrinkage leads to tight specifications in advanced semiconductor industries. For several years', metrology for lithography has been a key technology to address this challenge and to improve yield. More specifically overlay metrology is the object of special attention for tool suppliers and semiconductor manufacturers. This work focuses on Image Based Overlay (IBO) metrology for 28 nm FD-SOI CMOS front-end critical steps (gate and contact). With Overlay specifications below 10 nm, accuracy of the measurement is critical. In this study we show specific cases where target designs need to be optimized in order to minimize process effects (CMP, etch, deposition, etc.) that could lead to overlay measurement errors. Another important aspect of the metrology target is that its design must be device-like in order to better control and correct overlay errors leading to yield loss. Methodologies to optimize overlay metrology recipes are also presented. If the process effects cannot be removed entirely by target design optimization, recipe parameters have to be carefully chosen and controlled to minimize the influence of the target imperfection on measured overlay. With target asymmetry being one of the main contributors to those residual overlay measurement errors the Qmerit accuracy flag can be used to quantify the measurement error and recipe parameters can be set accordingly in order to minimize the target asymmetry impact. Reference technique measurements (CD-SEM) were used to check accuracy of the optimized overlay measurements.

  2. Bipolar transistor in VESTIC technology: prototype

    NASA Astrophysics Data System (ADS)

    Mierzwiński, Piotr; Kuźmicz, Wiesław; Domański, Krzysztof; Tomaszewski, Daniel; Głuszko, Grzegorz

    2016-12-01

    VESTIC technology is an alternative for traditional CMOS technology. This paper presents first measurement data of prototypes of VES-BJT: bipolar transistors in VESTIC technology. The VES-BJT is a bipolar transistor on the SOI substrate with symmetric lateral structure and both emitter and collector made of polysilicon. The results indicate that VES-BJT can be a device with useful characteristics. Therefore, VESTIC technology has the potential to become a new BiCMOS-type technology with some unique properties.

  3. Steep subthreshold slope characteristics of body tied to gate NMOSFET in partially depleted SOI

    NASA Astrophysics Data System (ADS)

    Song, Lei; Hu, Zhiyuan; Liu, Zhangli; Xin, Haiwei; Zhang, Zhengxuan; Zou, Shichang

    2017-04-01

    A new body tied to gate (BTG) n-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET) with a diode in partially depleted SOI (PD SOI) is proposed and investigated. We first compare the transfer and output characteristics between the regular and BTG NMOSFETs with grounded body and floating body. The steep subthreshold slope (<6 mV/dec) and low OFF current (∼0.01 pA/μm) of the BTG NMOSFET with floating body are observed at VD = 3.3 V. Mechanisms of the floating body effect (FBE) and the diode are analyzed to explain the outstanding performance. The hysteresis characteristics of BTG NMOSFETs are also presented in comparison to regular ones. Finally, the steep subthreshold characteristics of the BTG NMOSFET with floating body at low drain voltage are studied for ultralow power application.

  4. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging.

    PubMed

    Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

    2015-09-21

    This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  5. [SOI-nanowire biosensor for the detection of D-NFAT 1 protein].

    PubMed

    Malsagova, K A; Ivanov, Yu D; Pleshakova, T O; Kozlov, A F; Krohin, N V; Kaysheva, A L; Shumov, I D; Popov, V P; Naumova, O V; Fomin, B I; Nasimov, D A

    2015-01-01

    The nanowire (NW) detection is one of fast-acting and high-sensitive methods allowing to reveal potentially relevant protein molecules. A NW biosensor based on the silicon-on-insulator (SOI)-structures was used for biospecific label-free detection of NFAT 1 (D-NFAT 1) oncomarker in real time. For this purpose, SOI-nanowires (NWs) were modified with aptamers against NFAT 1 used as molecular probes. It was shown that using this biosensor it is possible to reach the sensitivity of ~10(-15) M. This sensitivity was comparable with that of the NW biosensor with immobilized antibodies used as macromolecular probes. The results demonstrate promising approaches used to form the sensor elements for high-sensitive disease diagnostics.

  6. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET

    NASA Astrophysics Data System (ADS)

    Navarenho de Souza Fino, Leonardo; Davini Neto, Enrico; Aparecida Guazzelli da Silveira, Marcilei; Renaux, Christian; Flandre, Denis; Pinillos Gimenez, Salvador

    2015-10-01

    This paper performs an experimental comparative study of the total ionizing dose effects due to the x-ray radiation between the silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) manufactured with octagonal gate geometry and the standard counterpart. Our main focus is on integrated transceivers for wireless communications and smart-power dc/dc converters for mobile electronics, where the transistor is used as the key switching element. It is shown that this innovative layout can reduce the total ionizing dose (TID) effects due to the special characteristics of the OCTO SOI MOSFET bird’s beak regions, where longitudinal electrical field lines in these regions are not parallel to the drain and source regions. Consequently, the parasitic MOSFETs associated with these regions are practically deactivated.

  7. Isolation of gene fusions (soi::lacZ) inducible by oxidative stress in Escherichia coli.

    PubMed Central

    Kogoma, T; Farr, S B; Joyce, K M; Natvig, D O

    1988-01-01

    Mu dX phage was used to isolate three gene fusions to the lacZ gene (soi::lacZ; soi for superoxide radical inducible) that were induced by treatment with superoxide radical anion generators such as paraquat and plumbagin. The induction of beta-galactosidase in these fusion strains with the superoxide radical generating agents required aerobic metabolism. Hyperoxygenation (i.e., bubbling of cultures with oxygen gas) also induced the fusions. On the other hand, hydrogen peroxide did not induce the fusions at concentrations that are known to invoke an adaptive response. Introduction of oxyR, htpR, or recA mutations did not affect the induction. Two of the fusion strains exhibited increased sensitivity to paraquat but not to hydrogen peroxide. The third fusion strain showed no increased sensitivity to either agent. All three fusions were located in the 45- to 61-min region of the Escherichia coli chromosome. PMID:2838846

  8. Design and analysis of a high fill-factor SOI diode uncooled infrared focal plane array

    NASA Astrophysics Data System (ADS)

    Jiang, Wenjing; Ou, Wen; Ming, Anjie; Liu, Zhanfeng; Zhang, Xinwei

    2013-06-01

    A new concept for uncooled infrared (IR) imaging with a high fill-factor SOI diode structure has been proposed. This approach has the potential of reaching a noise equivalent temperature difference (NETD) in the milli-Kelvin range. This detector makes the IR absorbing structure cover almost the entire pixel area, in which the fill factor can reach 80%. Using the multilever structure, thermal isolation can be independently optimized without sacrificing the IR absorption area. The analysis shows that this high fill-factor SOI diode uncooled IR focal plane array can be made without failure of structure breakdown or buckling. The design shows that the sensitivity is of 7.75 × 10-3 V K-1, and the NETD is of 42 mK (f/1.0, 30Hz) which can be achieved in a 35 µm × 35 µm micromachined structure.

  9. Investigation of the chip to photodetector coupler with subwavelength grating on SOI

    NASA Astrophysics Data System (ADS)

    Li, Hongqiang; Cui, Beibei; Liu, Yu; Liu, Hongwei; Zhang, Zanyun; Zhang, Cheng; Tang, Chunxiao; Li, Enbang

    2016-01-01

    We report on two kinds of investigation of the chip to photodetector coupler (CTPC) with uniform and blazed subwavelength grating (SWG) on silicon-on-insulator (SOI) that were conducted for silicon-based hybrid photodetector integration in an arrayed waveguide grating demodulation integrated microsystem. The theoretical model is presented, 3D FDTD and BPM simulations are used to optimize the coupler design. InP/InGaAs photodetector and SOI wafer were integrated through benzocyclobutene bonding. An efficient high-power absorption for TE mode in a broad band is achieved. The power absorption efficiencies of uniform and blazed SWGs in silicon-based hybrid photodetector integration at 1550 nm reach 73% and 75%, respectively in the simulation and it reaches as high as 25% in the measurement when coupling the TE-polarized 1550 nm light.

  10. Design and Characterization of Multiple Coupled Microring Based Wavelength Demultiplexer in Silicon-On (soi)

    NASA Astrophysics Data System (ADS)

    Haroon, Hazura; Shaari, Sahbudin; Menon, P. S.; Mardiana, B.; Hanim, A. R.; Arsad, N.; Majlis, B. Y.; Mukhtar, W. M.; Abdullah, Huda

    We report in this paper, an optimized design and characterization of SOI based single mode, four channels wavelength demultiplexer using microrings. The usage of silicon-on-insulator (SOI) allows a wide free spectral range (FSR) for the device that is crucial in developing ultra-compact integrations of planar lightwave circuits (PLCs). The characterizations are done using Finite-Difference Time-Domain (FDTD) mode simulations from RSOFT. Serially cascaded microring arrays up to the third order are presented to study the design trade-off among the FSR, Q-factor and optical losses of the laterally coupled wavelength demultiplexer. The demultiplexer is expected to be working at C-band region of Wavelength Division Multilplexing (WDM) for a wavelength around 1550 nm. Our proposed demultiplexer has low insertion loss (< 0.5 dB) and a crosstalk around 12 ~ 19 dB.

  11. Optimized sensitivity of Silicon-on-Insulator (SOI) strip waveguide resonator sensor

    PubMed Central

    TalebiFard, Sahba; Schmidt, Shon; Shi, Wei; Wu, WenXuan; Jaeger, Nicolas A. F.; Kwok, Ezra; Ratner, Daniel M.; Chrostowski, Lukas

    2017-01-01

    Evanescent field sensors have shown promise for biological sensing applications. In particular, Silicon-on-Insulator (SOI)-nano-photonic based resonator sensors have many advantages for lab-on-chip diagnostics, including high sensitivity for molecular detection and compatibility with CMOS foundries for high volume manufacturing. We have investigated the optimum design parameters within the fabrication constraints of Multi-Project Wafer (MPW) foundries that result in the highest sensitivity for a resonator sensor. We have demonstrated the optimum waveguide thickness needed to achieve the maximum bulk sensitivity with SOI-based resonator sensors to be 165 nm using the quasi-TM guided mode. The closest thickness offered by MPW foundry services is 150 nm. Therefore, resonators with 150 nm thick silicon waveguides were fabricated resulting in sensitivities as high as 270 nm/RIU, whereas a similar resonator sensor with a 220 nm thick waveguide demonstrated sensitivities of approximately 200 nm/RIU. PMID:28270963

  12. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    PubMed Central

    Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

    2015-01-01

    This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%. PMID:26402679

  13. Electron Pattern Recognition using trigger mode SOI pixel sensor for Advanced Compton Imaging

    NASA Astrophysics Data System (ADS)

    Shimazoe, K.; Yoshihara, Y.; Fairuz, A.; Koyama, A.; Takahashi, H.; Takeda, A.; Tsuru, T.; Arai, Y.

    2016-02-01

    Compton imaging is a useful method for localizing sub MeV to a few MeV gamma-rays and widely used for environmental and medical applications. The direction of recoiled electrons in Compton scattering process provides the additional information to limit the Compton cones and increases the sensitivity in the system. The capability of recoiled electron tracking using trigger-mode Silicon-On-Insulator (SOI) sensor is investigated with various radiation sources. The trigger-mode SOI sensor consists of 144 by 144 active pixels with 30 μm cells and the thickness of sensor is 500 μm. The sensor generates the digital output when it is hit by gamma-rays and 25 by 25 pixel pattern of surrounding the triggered pixel is readout to extract the recoiled electron track. The electron track is successfully observed for 60Co and 137Cs sources, which provides useful information for future electron tracking Compton camera.

  14. Integration of a UV curable polymer lens and MUMPs structures on a SOI optical bench

    NASA Astrophysics Data System (ADS)

    Hsieh, Jerwei; Hsiao, Sheng-Yi; Lai, Chun-Feng; Fang, Weileun

    2007-08-01

    This work presents the design concept of integrating a polymer lens, poly-Si MUMPs and single-crystal-silicon HARM structures on a SOI wafer to form a silicon optical bench. This approach enables the monolithic integration of various optical components on the wafer so as to improve the design flexibility of the silicon optical bench. Fabrication processes, including surface and bulk micromachining on the SOI wafer, have been established to realize bi-convex spherical polymer lenses with in-plane as well as out-of-plane optical axes. In addition, a micro device consisting of an in-plane polymer lens, a thick fiber holder and a mechanical shutter driven by an electrothermal actuator is also demonstrated using the present approach. In summary, this study significantly improves the design flexibility as well as the functions of SiOBs.

  15. Formation of SIMOX-SOI structure by high-temperature oxygen implantation

    NASA Astrophysics Data System (ADS)

    Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

    2015-12-01

    We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 1017-1018 ions/cm2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

  16. Features of SOI substrates heating in MBE growth process obtained by low-coherence tandem interferometry

    NASA Astrophysics Data System (ADS)

    Volkov, P. V.; Goryunov, A.. V.; Lobanov, D. N.; Luk'yanov, A. Yu.; Novikov, A. V.; Tertyshnik, A. D.; Shaleev, M. V.; Yurasov, D. V.

    2016-08-01

    Differences in heating of silicon and silicon-on-insulator (SOI) substrates in molecular beam epitaxy were revealed by low-coherence tandem interferometry. Using this technique the interference effects which impede the correct evaluation of SOI substrate temperature by infrared pyrometers can be eliminated and so the reliable temperature readout can be achieved. It was shown that at the same thermocouple and heater power settings the real temperature of SOI substrates is higher than of silicon ones and the difference may be as high as 40-50 °C at temperatures close to 600 °C. It is supposed that such effect is caused by the additional absorption of heater radiation by the buried oxide layer in the mid-infrared range. Independent proof of this effect was obtained by growing on both types of substrates a series of structures with self-assembled Ge nanoislands whose parameters are known to be very temperature sensitive. The proposed low-coherence interferometry technique provides precise real-time control of the growth temperature and so allows formation of SiGe nanostructures with desired parameters.

  17. Comparative study of NSB and UTB SOI MOSFETs characteristics by extraction of series resistance

    NASA Astrophysics Data System (ADS)

    Karsenty, A.; Chelly, A.

    2014-01-01

    The electrical characteristics of two kinds of n-type SOI-MOSFETs are analyzed and compared in order to build a consistent model. The first kind is an Ultra-Thin Body (UTB) device for which the channel thickness is equal to the initial SOI wafer thickness value (here 46 nm). The second kind is what we refer to Nano-Scale Body (NSB) device for which the initial SOI channel is thinned down to 1.6 nm using a recessed-gate process. The drain current values were found surprisingly different by three orders of magnitude. Such a huge contrast was not found coherent with the literature, reporting the decrease of the electron mobility with the channel thickness. We interpret our result by the probable influence of an extreme drain-to-source series resistance rather than by vanishing carrier mobility. The interpretation is sustained experimentally by the Rm-L and C-V methods. By integrating a gate-voltage dependence to the series resistance, the linear and saturation regions of the output characteristics of the NSB can be analytically derived from the UTB ones. This simple modeling approach may be useful to interpret anomalous electrical behavior of other nano-devices in which series resistance is of a great concern.

  18. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

    2002-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  19. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    NASA Technical Reports Server (NTRS)

    Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

    2005-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  20. Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

    SciTech Connect

    Naumova, O. V. Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P.

    2015-10-15

    The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

  1. Subject order-independent group ICA (SOI-GICA) for functional MRI data analysis.

    PubMed

    Zhang, Han; Zuo, Xi-Nian; Ma, Shuang-Ye; Zang, Yu-Feng; Milham, Michael P; Zhu, Chao-Zhe

    2010-07-15

    Independent component analysis (ICA) is a data-driven approach to study functional magnetic resonance imaging (fMRI) data. Particularly, for group analysis on multiple subjects, temporally concatenation group ICA (TC-GICA) is intensively used. However, due to the usually limited computational capability, data reduction with principal component analysis (PCA: a standard preprocessing step of ICA decomposition) is difficult to achieve for a large dataset. To overcome this, TC-GICA employs multiple-stage PCA data reduction. Such multiple-stage PCA data reduction, however, leads to variable outputs due to different subject concatenation orders. Consequently, the ICA algorithm uses the variable multiple-stage PCA outputs and generates variable decompositions. In this study, a rigorous theoretical analysis was conducted to prove the existence of such variability. Simulated and real fMRI experiments were used to demonstrate the subject-order-induced variability of TC-GICA results using multiple PCA data reductions. To solve this problem, we propose a new subject order-independent group ICA (SOI-GICA). Both simulated and real fMRI data experiments demonstrated the high robustness and accuracy of the SOI-GICA results compared to those of traditional TC-GICA. Accordingly, we recommend SOI-GICA for group ICA-based fMRI studies, especially those with large data sets. Copyright 2010 Elsevier Inc. All rights reserved.

  2. A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

    2008-01-01

    A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

  3. A process for SOI resonators with surface micromachined covers and reduced electrostatic gaps

    NASA Astrophysics Data System (ADS)

    Dekker, James R.; Alastalo, Ari; Kattelus, Hannu

    2010-04-01

    This paper describes work to fabricate resonators on silicon-on-insulator (SOI) wafers with sub-micron gaps and wafer level encapsulation. Non-aligned, high-temperature fusion bonding of a cover wafer over unreleased structures etched into a SOI wafer is followed by cover wafer stripping to reveal etched resonators beneath an oxide membrane. Reliable bonding is assured by bonding unreleased structures which can withstand the appropriate pre-bond cleaning operations. The bonded oxide membrane serves as the basis of a surface micromachined membrane which incorporates silicon nitride and a porous polysilicon layer to facilitate release and supercritical drying. The cavity pressure is estimated to be in the range of 1 Torr. Encapsulated resonators were also made using a gap reduction process. The process is based on sidewall oxidation of an etched sleeve to reduce the linewidth of the patterned electrostatic gaps by 200 nm before the deep trench etch. Encapsulated and electrically active devices with gaps down to 500 nm were obtained and etched through a 5 µm thick SOI device layer. SEM images showed that gaps of 300 nm could reach through the same thickness, though functional devices were not obtained. In addition, limitations on the anti-notching process limited its use during the trench etch and resulted in severe notch damage.

  4. Differentially piezoresistive transduction of high-Q encapsulated SOI-MEMS resonators with sub-100 nm gaps.

    PubMed

    Li, Cheng-Syun; Li, Ming-Huang; Li, Sheng-Shian

    2015-01-01

    A differentially piezoresistive (piezo-R) readout proposed for single-crystal-silicon (SCS) microelectromechanical systems (MEMS) resonators is implemented in a foundrybased resonator platform, demonstrating effective feedthrough cancellation using just simple piezoresistors from the resonator supports while maximizing their capacitively transduced driving areas. The SCS resonators are fabricated by a CMOS foundry using an SOI-MEMS technology together with a polysilicon refill process. A high electromechanical coupling coefficient is attained by the use of 50-nm transducer gap spacing. Moreover, a vacuum package of the fabricated resonators is carried out through wafer-level bonding process. In this work, the corner supporting beams of the resonator serve not only mechanical supports but also piezoresistors for detecting the motional signal, hence substantially simplifying the overall resonator design to realize the piezo-R sensing. In addition, the fabricated resonators are capable of either capacitive sensing or piezo-R detection under the same capacitive drive. To mitigate feedthrough signals from parasitics, a differential measurement configuration of the piezo-R transduction is implemented in this work, featuring more than 30-dB improvement on the feedthrough level as compared with the single-ended piezo-R counterpart and purely capacitive sensing readout. Furthermore, the high-Q design of the mechanical supports is also investigated, offering Q more than 10 000 with efficient piezo-R transduction for MEMS resonators.

  5. Reliable characteristics and stabilization of on-membrane SOI MOSFET-based components heated up to 335 °C

    NASA Astrophysics Data System (ADS)

    Amor, S.; André, N.; Gérard, P.; Ali, S. Z.; Udrea, F.; Tounsi, F.; Mezghani, B.; Francis, L. A.; Flandre, D.

    2017-01-01

    In this work we investigate the characteristics and critical operating temperatures of on-membrane embedded MOSFETs from an experimental and analytical point of view. This study permits us to conclude the possibility of integrating electronic circuitry in the close vicinity of micro-heaters and hot operation transducers. A series of calibrations and measurements has been performed to examine the behaviors of transistors, inverters and diodes, actuated at high temperature, on a membrane equipped with an on-chip integrated micro-heater. The studied n- and p-channel body-tied partially-depleted MOSFETs and CMOS inverter are embedded in a 5 μm-thick membrane fabricated by back-side MEMS micromachining using SOI technology. It has been noted that a pre-stabilization step after the harsh post-CMOS processing, through an in situ high-temperature annealing using the micro-heater, is mandatory in order to stabilize the MOSFETs characteristics. The electrical characteristics and performance of the on-membrane MOS components are discussed when heated up to 335 °C. This study supports the possibility of extending the potential of the micro-hotplate concept, under certain conditions, by embedding more electronic functionalities on the interface of on-membrane-based sensors leading to better sensing and actuation performances and a total area reduction, particularly for environmental or industrial applications.

  6. Improvement of spectroscopic performance using a charge-sensitive amplifier circuit for an X-ray astronomical SOI pixel detector

    NASA Astrophysics Data System (ADS)

    Takeda, A.; Tsuru, T. G.; Tanaka, T.; Uchida, H.; Matsumura, H.; Arai, Y.; Mori, K.; Nishioka, Y.; Takenaka, R.; Kohmura, T.; Nakashima, S.; Kawahito, S.; Kagawa, K.; Yasutomi, K.; Kamehama, H.; Shrestha, S.

    2015-06-01

    We have been developing monolithic active pixel sensors series, named ``XRPIX'', based on the silicon-on-insulator (SOI) pixel technology, for future X-ray astronomical satellites. The XRPIX series offers high coincidence time resolution (~ 1 μs), superior readout time (~ 10 μs), and a wide energy range (0.5-40 keV) . In the previous study, we successfully demonstrated X-ray detection by event-driven readout of XRPIX2b. We here report recent improvements in spectroscopic performance. We successfully increased the gain and reduced the readout noise in XRPIX2b by decreasing the parasitic capacitance of the sense-node originated in the buried p-well (BPW) . On the other hand, we found significant tail structures in the spectral response due to the loss of the charge collection efficiency when a small BPW is employed. Thus, we increased the gain in XRPIX3b by introducing in-pixel charge sensitive amplifiers instead of having even smaller BPW . We finally achieved the readout noise of 35 e- (rms) and the energy resolution of 320 eV (FWHM) at 6 keV without significant loss of the charge collection efficiency.

  7. Improvement of self-heating effect in a novel nanoscale SOI MOSFET with undoped region: A comprehensive investigation on DC and AC operations

    NASA Astrophysics Data System (ADS)

    Anvarifard, Mohammad K.; Orouji, Ali A.

    2013-08-01

    The buried oxide in a SOI MOSFET inhibits heat dissipation in the silicon layer due to low thermal conductivity of the oxide and leads to problematic increase in the device lattice temperature. This work reports a new SOI MOSFET with undoped region (UR-SOI) under the source and channel regions in order to reduce self-heating effect (SHE). The structure has well controlled the lattice temperature and also many improvements are obtained because of the embedded undoped region in the suitable place. Improvements such as increased drain current, reduced maximum lattice temperature, reduced bandgap energy variations, higher DC transconductance and lower DC drain conductance and also increased electron mobility are explored. Also important parameters such as SHE characteristic frequency (fth), thermal resistance (Rth) and thermal capacitance (Cth) have been extracted for accurate modeling of the structure in SPICE tools. Furthermore, all the obtained parameters which are related to AC operation show excellent performance of the UR-SOI device. Comparison of the UR-SOI structure with a conventional-SOI (C-SOI) is done with a two-dimensional and two-carrier simulator SILVACO and all the extracted results promise marvelous superiority of the UR-SOI to the C-SOI device.

  8. Soi3p/Rav1p functions at the early endosome to regulate endocytic trafficking to the vacuole and localization of trans-Golgi network transmembrane proteins.

    PubMed

    Sipos, György; Brickner, Jason H; Brace, E J; Chen, Linyi; Rambourg, Alain; Kepes, Francois; Fuller, Robert S

    2004-07-01

    SOI3 was identified by a mutation, soi3-1, that suppressed a mutant trans-Golgi network (TGN) localization signal in the Kex2p cytosolic tail. SOI3, identical to RAV1, encodes a protein important for regulated assembly of vacuolar ATPase. Here, we show that Soi3/Rav1p is required for transport between the early endosome and the late endosome/prevacuolar compartment (PVC). By electron microscopy, soi3-1 mutants massively accumulated structures that resembled early endosomes. soi3Delta mutants exhibited a kinetic delay in transfer of the endocytic tracer dye FM4-64, from the 14 degrees C endocytic intermediate to the vacuole. The soi3Delta mutation delayed vacuolar degradation but not internalization of the a-factor receptor Ste3p. By density gradient fractionation, Soi3/Rav1p associated as a peripheral protein with membranes of a density characteristic of early endosomes. The soi3 null mutation markedly reduced the rate of Kex2p transport from the TGN to the PVC but had no effect on vacuolar protein sorting or cycling of Vps10p. These results suggest that assembly of vacuolar ATPase at the early endosome is required for transport of both Ste3p and Kex2p from the early endosome to the PVC and support a model in which cycling through the early endosome is part of the normal itinerary of Kex2p and other TGN-resident proteins.

  9. Atomic Precision Donor Devices Fabricated on Strained Silicon on Insulator (sSOI) with SiGe

    NASA Astrophysics Data System (ADS)

    Yitamben, E.; Bussmann, E.; Scrymgeour, D. A.; Rudolph, M.; Carr, S. M.; Ward, D. R.; Carroll, M. S.

    Recently, Si:P donor spin qubits have achieved coherence times (nuclear & e-) that underscore their quantum computing potential. One next major challenge is to integrate donors into a gated structure where electrons can be moved between P, or drawn off of the P to interact, e.g. to an interface as in Kane's proposal. A key constraint is limited thermal budget, to limit P thermal segregation, which precludes typical gate oxidation of Si. We are developing an alternative materials stack utilizing an interfacial barrier layer of relaxed epitaxial SiGe, with donors placed in a strained Si-on-insulator (sSOI) substrate. We fabricate atomic precision donor structures in sSOI via STM hydrogen lithography. Utilizing Si microfabrication and STM in tandem with our Si and Ge molecular beam epitaxy (MBE), we fabricated devices to test our SiGe/sSOI stack concept and atomic-precision fab techniques. To establish our donor-doping capability, we made Hall and Van der Pauw devices in P:sSOI delta-doped layers exhibiting ne >1014/cm2 and mobilities of ~100 cm2/Vs (T =4K) similar to results reported relaxed Si reported elsewhere. Second, we have grown our concept epitaxial SiGe/sSOI stack, evaluated the morphology using STM, and fabricated Hall devices to evaluate low-T transport in our first SiGe/sSOI. Here, we report on these advances in atomic precision donor fab, along with STM analysis our MBE SiGe/sSOI. This work extends STM-based atom precision fab on strained Si toward a vertically gated architecture.

  10. A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications

    NASA Astrophysics Data System (ADS)

    Patil, Ganesh C.; Qureshi, S.

    2011-08-01

    In this paper, a comparative analysis of single-gate dopant-segregated Schottky barrier (DSSB) SOI MOSFET and raised source/drain ultrathin-body SOI MOSFET (RSD UTB) has been carried out to explore the thermal efficiency, scalability and analog/RF performance of these devices. A novel p-type δ-doped partially insulated DSSB SOI MOSFET (DSSB Pi-OX-δ) has been proposed to reduce the self-heating effect and to improve the high-frequency performance of DSSB SOI MOSFET over RSD UTB. The improved analog/RF figures of merit such as transconductance, transconductance generation factor, unity-gain frequency, maximum oscillation frequency, short-circuit current gain and unilateral power gain in DSSB Pi-OX-δ MOSFET show the suitability of this device for analog/RF applications. The reduced drain-induced barrier lowering, subthreshold swing and parasitic capacitances also make this device highly scalable. By using mixed-mode simulation capability of MEDICI simulator a cascode amplifier has been implemented using all the structures (RSD UTB, DSSB SOI and DSSB Pi-OX-δ MOSFETs). The results of this implementation show that the gain-bandwidth product in the case of DSSB Pi-OX-δ MOSFET has improved by 50% as compared to RSD UTB and by 20% as compared to DSSB SOI MOSFET. The detailed fabrication flow of DSSB Pi-OX-δ MOSFET has been proposed which shows that with the bare minimum of steps the performance of DSSB SOI MOSFET can be improved significantly in comparison to RSD UTB.

  11. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

  12. Deeply etched MMI-based components on 4 μm thick SOI for SOA-based optical RAM cell circuits

    NASA Astrophysics Data System (ADS)

    Cherchi, Matteo; Ylinen, Sami; Harjanne, Mikko; Kapulainen, Markku; Aalto, Timo; Kanellos, George T.; Fitsios, Dimitrios; Pleros, Nikos

    2013-02-01

    We present novel deeply etched functional components, fabricated by multi-step patterning in the frame of our 4 μm thick Silicon on Insulator (SOI) platform based on singlemode rib-waveguides and on the previously developed rib-tostrip converter. These novel components include Multi-Mode Interference (MMI) splitters with any desired splitting ratio, wavelength sensitive 50/50 splitters with pre-filtering capability, multi-stage Mach-Zehnder Interferometer (MZI) filters for suppression of Amplified Spontaneous Emission (ASE), and MMI resonator filters. These novel building blocks enable functionalities otherwise not achievable on our SOI platform, and make it possible to integrate optical RAM cell layouts, by resorting to our technology for hybrid integration of Semiconductor Optical Amplifiers (SOAs). Typical SOA-based RAM cell layouts require generic splitting ratios, which are not readily achievable by a single MMI splitter. We present here a novel solution to this problem, which is very compact and versatile and suits perfectly our technology. Another useful functional element when using SOAs is the pass-band filter to suppress ASE. We pursued two complimentary approaches: a suitable interleaved cascaded MZI filter, based on a novel suitably designed MMI coupler with pre-filtering capabilities, and a completely novel MMI resonator concept, to achieve larger free spectral ranges and narrower pass-band response. Simulation and design principles are presented and compared to preliminary experimental functional results, together with scaling rules and predictions of achievable RAM cell densities. When combined with our newly developed ultra-small light-turning concept, these new components are expected to pave the way for high integration density of RAM cells.

  13. Application of Silicon Selective Epitaxial Growth and Chemo-Mechanical Polishing to Bipolar and Soi Mosfet Devices.

    NASA Astrophysics Data System (ADS)

    Nguyen, Cuong Tan

    1994-01-01

    Polished Epitaxy, or the combination of silicon Selective Epitaxial Growth and Chemo-Mechanical Polishing, provides new flexibility in process and device design, including optimized isolation, planar active-area definition, low-capacitance contacts, and SOI thin films. In this work, Polished Epitaxy has been developed with particular effort on overcoming junction leakage problems widely reported in devices fabricated in similar processes. It was found that in addition to careful surface preparation and defect control in the selective epitaxy process, issues such as sidewall orientation, junction passivation, crystal annealing, and surface damage removal were equally important and needed to be addressed. Coupled with the proper processing steps, Polished Epitaxy was able to deliver material of comparable quality to bulk silicon, suitable for device applications. By growing epitaxy laterally over an oxide step followed by polishing, a pedestal structure was created in which a thin film of single-crystal silicon was formed over oxide. Serving as the extrinsic base contact to a T-Pedestal bipolar transistor device, this pedestal helped minimize the parasitic extrinsic-base-collector overlap capacitance. The cut-off frequency (f_ {T}) in a device with a 1.0-mu m wide emitter stripe was found to improve from 17GHz to 22GHz when the contact overlap was reduced from a more conventional, larger size of 1.0 mu m to 0.2 mum. It is expected that the high-frequency performance of this structure can still be improved further in an optimized process with reduced emitter and collector resistances. The same pedestal structure was applied to a Pedestal -SOI (Silicon-On-Insulator) MOSFET device concept. At one extreme, a conventional bulk MOSFET structure is obtained when the pedestal is not utilized; quasi-SOI occurs when the drain and part of the channel overlap with the pedestal over buried oxide; at the other extreme, complete-SOI behavior results when source, channel, and drain

  14. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    NASA Astrophysics Data System (ADS)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  15. Monolithic pixel detectors in silicon on insulator technology

    SciTech Connect

    Bisello, Dario

    2013-05-06

    Silicon On Insulator (SOI) is becoming an attractive technology to fabricate monolithic pixel detectors. The possibility of using the depleted resistive substrate as a drift collection volume and to connect it by means of vias through the buried oxide to the pixel electronic makes this kind of approach interesting both for particle and photon detection. In this paper I report the results obtained in the development of monolithic pixel detectors in an SOI technology by a collaboration between groups from the University and INFN of Padova (Italy) and the LBNL and the SCIPP at UCSC (USA).

  16. Monolithic pixel detectors in silicon on insulator technology

    NASA Astrophysics Data System (ADS)

    Bisello, Dario

    2013-05-01

    Silicon On Insulator (SOI) is becoming an attractive technology to fabricate monolithic pixel detectors. The possibility of using the depleted resistive substrate as a drift collection volume and to connect it by means of vias through the buried oxide to the pixel electronic makes this kind of approach interesting both for particle and photon detection. In this paper I report the results obtained in the development of monolithic pixel detectors in an SOI technology by a collaboration between groups from the University and INFN of Padova (Italy) and the LBNL and the SCIPP at UCSC (USA).

  17. InP-on-SOI electrically injected nanolaser diodes (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Crosnier, Guillaume; Sanchez, Dorian; Monnier, Paul; Sagnes, Isabelle; Bouchoule, Sophie; Beaudoin, Grégoire; Raj, Rama; Raineri, Fabrice

    2017-02-01

    The development of energy-efficient ultra-compact nanolaser diodes integrated in a Silicon photonic platform is of paramount importance for the deployment of optical interconnects for intra-chip communications. In this work, we present our results on InP-based electrically injected photonic crystal (PhC) nanolaser integrated on a SOI waveguide circuitry. The lasers emit at room temperature in a continuous wave regime at 1560nm and exhibit thresholds of 0.1mA at 1V. We measure more than 100μW of light coupled into the SOI waveguides giving a wall-plug efficiency greater than 10%. The principle of the lasers relies on the use of a 1D PhC nanocavity made of InP-based materials positioned on top of a SOI waveguide to enable evanescent wave coupling. More in details, the laser cavity is a 650nm-wide rib waveguide drilled with a single row of equally sized holes (radius 100nm). The distance between the holes is varied to obtain Q-factors larger than 106 for a structure fully encapsulated in silica with material volume of the order of the cubic wavelength. Vertically, the InP heterostructure is a 450nm thick NIP junction embedding 5 strained InGaAsP quantum wells emitting at 1.53μm. By smartly positioning the metallic contacts, this configuration enables the efficient electrical injection of electron-holes pairs within the cavity without inducing optical losses which led us to demonstrate the laser emission coupled ta a Si waveguide.

  18. New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation

    SciTech Connect

    BURNS,J.A.; DODD,PAUL E.; KEAST,C.L.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; WYATT,P.W.

    1999-09-14

    Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.

  19. Low-loss and flatband silicon-nanowire-based 5th-order coupled resonator optical waveguides (CROW) fabricated by ArF-immersion lithography process on a 300-mm SOI wafer

    NASA Astrophysics Data System (ADS)

    Jeong, Seok-Hwan; Shimura, Daisuke; Simoyama, Takasi; Seki, Miyoshi; Yokoyama, Nobuyuki; Ohtsuka, Minoru; Koshino, Keiji; Horikawa, Tsuyoshi; Tanaka, Yu; Morito, Ken

    2014-03-01

    We present flatband, low-loss and low-crosstalk characteristics of Si-nanowire-based 5th-order coupled resonator optical waveguides (CROW) fabricated by ArF-immersion lithography process on a 300-mm silicon-on-insulator (SOI) wafer. We theoretically specified why phase controllability over Si-nanowire waveguides is prerequisite to attain desired spectral response, discussing spectral degradation by random phase errors during fabrication process. It was experimentally demonstrated that advanced patterning technology based on ArF-immersion lithography process showed extremely low phase errors even for Si-nanowire channel waveguides. As a result, the device exhibited extremely low loss of <0.2dB and low crosstalk of <-40dB without any external phase compensation. Furthermore, fairly good spectral uniformity for all fabricated devices was found both in intra-dies and inter-dies. The center wavelengths for box-like drop channel responses were distributed within 0.4 nm in the same die. This tendency was kept nearly constant for other dies on the 300-mm SOI wafer. In the case of the inter-die distribution where each die is spaced by ~3cm, the deviation of the center wavelengths was as low as +/-1.8 nm between the dies separated by up to ~15 cm. The spectral superiority was reconfirmed by measuring 25 Gbps modulation signals launched into the device. Clear eye openings were observed as long as the optical signal wavelengths are stayed within the flat-topped passband of the 5th-order CROW. We believe these high-precision fabrication technologies based on 300-mm SOI wafer scale ArF-immersion lithography would be promising for several kinds of WDM multiplexers/demultiplexers having much complicated configurations and requiring much finer phase controllability.

  20. MOVPE growth of GaN on 6-inch SOI-substrates: effect of substrate parameters on layer quality and strain

    NASA Astrophysics Data System (ADS)

    Lemettinen, J.; Kauppinen, C.; Rudzinski, M.; Haapalinna, A.; Tuomi, T. O.; Suihkonen, S.

    2017-04-01

    We demonstrate that higher crystalline quality, lower strain and improved electrical characteristics can be achieved in gallium nitride (GaN) epitaxy by using a silicon-on-insulator (SOI) substrate compared to a bulk silicon (Si) substrate. GaN layers were grown by metal–organic vapor phase epitaxy on 6-inch bulk Si and SOI wafers using the standard step graded AlGaN and AlN approach. The GaN layers grown on SOI exhibited lower strain according to x-ray diffraction analysis. Defect selective etching measurements suggested that the use of SOI substrate for GaN epitaxy reduces the dislocation density approximately by a factor of two. Furthermore, growth on SOI substrate allows one to use a significantly thinner AlGaN buffer compared to bulk Si. Synchrotron radiation x-ray topography analysis confirmed that the stress relief mechanism in GaN on SOI epitaxy is the formation of a dislocation network to the SOI device Si layer. In addition, the buried oxide layer significantly improves the vertical leakage characteristics as the onset of the breakdown is delayed by approximately 400 V. These results show that the GaN on the SOI platform is promising for power electronics applications.

  1. Source-Bias Dependent Charge Accumulation in P+-Poly Gate SOI Dynamic Random Access Memory Cell Transistors

    NASA Astrophysics Data System (ADS)

    Sim, Jai-hoon; Kim, Kinam

    1998-03-01

    In this paper, we report the dynamic data retention problems caused by the transient leakage current in a cell transistor during the bit-line pull down operation in p+-poly gate fully depleted silicon-on-insulator (FD-SOI) dynamic random access memories (DRAMs) due to the source-induced charge accumulation (SICA) effect in the silicon thin film. Due to the inherent floating body effect in the FD-SOI transistor, charge accumulation in the silicon thin film becomes inevitable when the gate-to-source voltage (VGS) is smaller than the flat-band voltage (VFB). In order to eliminate the transient leakage current problem in p+-poly gate FD-SOI cell transistor, the ground-precharged bit-line (GPB) sensing method is introduced.

  2. Highly efficient CW parametric conversion at 1550 nm in SOI waveguides by reverse biased p-i-n junction.

    PubMed

    Gajda, Andrzej; Zimmermann, Lars; Jazayerifar, Mahmoud; Winzer, Georg; Tian, Hui; Elschner, Robert; Richter, Thomas; Schubert, Colja; Tillack, Bernd; Petermann, Klaus

    2012-06-04

    In this paper we present four-wave mixing (FWM) based parametric conversion experiments in p-i-n diode assisted silicon-on-insulator (SOI) nano-rib waveguides using continuous-wave (CW) light around 1550 nm wavelength. Using a reverse biased p-i-n waveguide diode we observe an increase of the wavelength conversion efficiency of more than 4.5 dB compared to low loss nano-rib waveguides without p-i-n junction, achieving a peak efficiency of -1 dB. Conversion efficiency improves also by more than 7 dB compared to previously reported experiments deploying 1.5 µm SOI waveguides with p-i-n structure. To the best of our knowledge, the observed peak conversion efficiency of -1dB is the highest CW efficiency in SOI reported so far.

  3. Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Hubert, A.; Bawedin, M.; Cristoloveanu, S.; Ernst, T.

    2009-12-01

    The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.

  4. Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

    PubMed

    Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-12-13

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

  5. Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

    PubMed Central

    Boufouss, El Hafed; Francis, Laurent A.; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-01-01

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2. PMID:24351635

  6. Integrated thin-film GaSb-based Fabry-Perot lasers: towards a fully integrated spectrometer on a SOI waveguide circuit

    NASA Astrophysics Data System (ADS)

    Hattasan, N.; Gassenq, A.; Cerutti, L.; Rodriguez, J. B.; Tournié, E.; Roelkens, G.

    2013-01-01

    Several molecules of interest have their absorption signature in the mid-infrared. Spectroscopy is commonly used for the detection of these molecules, especially in the short-wave infrared (SWIR) region due to the low water absorption. Conventional spectroscopic systems consist of a broadband source, detector and dispersive components, making them bulky and difficult to handle. Such systems cannot be used in applications where small footprint and low power consumption is critical, such as portable gas sensors and implantable blood glucose monitors. Silicon-On-Insulator (SOI) offers a compact, low-cost photonic integrated circuit platform realized using CMOS fabrication technology. On the other hand, the GaSb material system allows the realization of high performance SWIR lasers and detectors. Integration of GaSb active components on SOI could therefore result in a compact and low power consumption integrated spectroscopic system. In this paper, we report the study on thin-film GaSb Fabry-Perot lasers integrated on a carrier substrate. The integration is achieved by using an adhesive polymer (DVS-BCB) as the bonding agent. The lasers operate at room temperature at 2.02μm. We obtain a minimum threshold current of 48.9mA in the continuous wave regime and 27.7mA in pulsed regime. This yields a threshold current density of 680A/cm2 and 385A/cm2, respectively. The thermal behaviour of the device is also studied. The lasers operate up to 35 °C, due to a 323 K/W thermal resistance

  7. DETECTORS AND EXPERIMENTAL METHODS: Radiation response of pseudo-MOS transistors fabricated in hardened fully-depleted SIMOX SOI wafers

    NASA Astrophysics Data System (ADS)

    Bi, Da-Wei; Zhang, Zheng-Xuan; Zhang, Shuai; Chen, Ming; Yu, Wen-Jie; Wang, Ru; Tian, Hao; Liu, Zhang-Li

    2009-10-01

    The total dose radiation response of pseudo-MOS transistors fabricated in hardened and unhardened FD (fully-depleted) SIMOX (Separation by Implanted Oxygen) SOI (Silicon-on-insulator) wafers is presented. At 1 Mrad(Si) radiation dose, the threshold voltage shift of the pseudo-MOS transistor is reduced from -115.5 to -1.9 V by the hardening procedure. The centroid location of the net positive charge trapped in BOX, the hole-trap density and the hole capture fraction of BOX are also shown. The results suggest that hardened FD SIMOX SOI wafers can perform well in a radiation environment.

  8. Trigger voltage walk-out phenomenon in SOI lateral insulated gate bipolar transistor under repetitive electrostatic discharge stresses

    NASA Astrophysics Data System (ADS)

    Zhang, Shifeng; Han, Yan; Ma, Fei

    2016-05-01

    Trigger voltage walk-out phenomenon is found in SOI LIGBT's under repetitive ESD stresses. Such a characteristic would cause an IC to be susceptible to the risk of exceeding the ESD design window and thus resulting in core circuit damages when the LIGBT is served as an ESD protection device in the SOI process. This trigger-voltage walk-out phenomenon is investigated in this paper, and both the experimental evidences and device simulation results are presented to offer the insight of the underlying physical mechanism.

  9. Thick-SOI Echelle grating for any-to-any wavelength routing interconnection in multi-socket computing environments

    NASA Astrophysics Data System (ADS)

    Dabos, G.; Pitris, S.; Mitsolidou, C.; Alexoudi, T.; Fitsios, D.; Cherchi, M.; Harjanne, M.; Aalto, T.; Kanellos, G. T.; Pleros, N.

    2017-02-01

    As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption. Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on-chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.

  10. Development of electron-tracking Compton imaging system with 30-μm SOI pixel sensor

    NASA Astrophysics Data System (ADS)

    Yoshihara, Y.; Shimazoe, K.; Mizumachi, Y.; Takahashi, H.; Kamada, K.; Takeda, A.; Tsuru, T.; Arai, Y.

    2017-01-01

    Compton imaging is a useful method to localize gamma sources without using mechanical collimators. In conventional Compton imaging, the incident directions of gamma rays are estimated in a cone for each event by analyzing the sequence of interactions of each gamma ray followed by Compton kinematics. Since the information of the ejection directions of the recoil electrons is lost, many artifacts in the shape of cone traces are generated, which reduces signal-to-noise ratio (SNR) and angular resolution. We have developed an advanced Compton imaging system with the capability of tracking recoil electrons by using a combination of a trigger-mode silicon-on-insulator (SOI) pixel detector and a GAGG detector. This system covers the 660-1330 keV energy range for localization of contamination nuclides such as 137Cs and 134Cs inside the Fukushima Daiichi Nuclear Power Plant in Japan. The ejection directions of recoil electrons caused by Compton scattering are detected on the micro-pixelated SOI detector, which can theoretically be used to determine the incident directions of the gamma rays in a line for each event and can reduce the appearance of artifacts. We obtained 2-D reconstructed images from the first iteration of the proposed system for 137Cs, and the SNR and angular resolution were enhanced compared with those of conventional Compton imaging systems.

  11. High LET Single Event Upset Cross Sections For Bulk and SOI CMOS SRAMs

    SciTech Connect

    McDaniel, F.D.; Doyle, B.L.; Vizkelethy, G.; Dodd, P.E.; Rossi, P.

    2003-08-26

    Electronics in spacecraft and satellites are exposed to high-energy cosmic radiation. In addition, terrestrial radiation can also affect earth-based electronics. To study the effects of radiation upon integrated circuits and to insure the reliability of electronic devices, cosmic and terrestrial radiations are simulated with ion beams from particle accelerators. A new, higher Linear Energy Transfer (LET) acceleration system for heavy ions has been developed at Sandia National Laboratories. Heavy ions from a 6.5 MV EN tandem Van de Graaff accelerator at 0.25 MeV/amu are injected into a two-stage Radio Frequency Quadrupole (RFQ) linac, which accelerates the ions to 1.9 MeV/amu. These ions together with those from the Brookhaven National Laboratory MP Tandem have been used to measure single event upset (SEU) cross sections as a function of LET for both bulk and Silicon on Insulator (SOI) Complementary Metal Oxide Semiconductor, Static Random Access Memories. The magnitudes of these cross sections indicate that the upsets in both the SOI and bulk parts are caused by OFF-drain strikes.

  12. Investigation of temperature-dependent small-signal performances of TB SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Huang, Yuping; Liu, Jun; Lü, Kai; Chen, Jing

    2017-04-01

    This paper investigated the temperature dependence of the cryogenic small-signal ac performances of multi-finger partially depleted (PD) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs), with T-gate body contact (TB) structure. The measurement results show that the cut-off frequency increases from 78 GHz at 300 K to 120 GHz at 77 K and the maximum oscillation frequency increases from 54 GHz at 300 K to 80 GHz at 77 K, and these are mainly due to the effect of negative temperature dependence of threshold voltage and transconductance. By using a simple equivalent circuit model, the temperature-dependent small-signal parameters are discussed in detail. The understanding of cryogenic small-signal performance is beneficial to develop the PD SOI MOSFETs integrated circuits for ultra-low temperature applications. Project supported by the National Natural Science Foundation of China (No. 61331006) and the National Defense Pre-Research Foundation of China (No. 9140A11040114DZ04152).

  13. Defect Characterization in SiGe/SOI Epitaxial Semiconductors by Positron Annihilation

    NASA Astrophysics Data System (ADS)

    Ferragut, R.; Calloni, A.; Dupasquier, A.; Isella, G.

    2010-12-01

    The potential of positron annihilation spectroscopy (PAS) for defect characterization at the atomic scale in semiconductors has been demonstrated in thin multilayer structures of SiGe (50 nm) grown on UTB (ultra-thin body) SOI (silicon-on-insulator). A slow positron beam was used to probe the defect profile. The SiO2/Si interface in the UTB-SOI was well characterized, and a good estimation of its depth has been obtained. The chemical analysis indicates that the interface does not contain defects, but only strongly localized charged centers. In order to promote the relaxation, the samples have been submitted to a post-growth annealing treatment in vacuum. After this treatment, it was possible to observe the modifications of the defect structure of the relaxed film. Chemical analysis of the SiGe layers suggests a prevalent trapping site surrounded by germanium atoms, presumably Si vacancies associated with misfit dislocations and threading dislocations in the SiGe films.

  14. A new high-voltage interconnection shielding method for SOI monolithic ICs

    NASA Astrophysics Data System (ADS)

    Zhang, Long; Zhu, Jing; Sun, Weifeng; Huang, Xuequan; Zhao, Minna; Chen, Jiajun; Shi, Longxing; Chen, Jian; Ding, Desheng

    2017-07-01

    The high-voltage interconnection (HVI) issue becomes severe in the high-voltage monolithic ICs when single-layer metal is used for lowering the cost. This paper proposes a dual deep-oxide trenches (DDOT) structure for 500 V Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) to shield the influence of HVI on the breakdown voltage. Compared with the conventional DDOT structure, HVI region of the proposed DDOT structure is shrunk by employing a shallow trench (T1) and a deep trench (T2). Besides the breakdown mechanism in the off-state, the current density and impact ionization rate distributions in the on-state of the proposed structure are also investigated. The experiments demonstrate that the proposed DDOT structure can fully shield the influence of HVI with significant reduction in the area of silicon region beneath the HVI. With almost the same off-state breakdown voltage (BVoff) of 550 V as the conventional DDOT structure, the length of the silicon region under the HVI in the proposed structure is shortened from 45 μm to 15 μm. Meanwhile, no on-state breakdown voltage (BVon) degradation is observed according to the measured results. The new method proposed in this work can also be used for other types of high-voltage devices such as LDMOS and free-wheeling diode in SOI Monolithic ICs.

  15. Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

    NASA Astrophysics Data System (ADS)

    Zheng, Zhi; Li, Wei; Li, Ping

    2013-04-01

    A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.

  16. Reduction of cross-talks between circuit and sensor layer in the Kyoto's X-ray astronomy SOI pixel sensors with Double-SOI wafer

    NASA Astrophysics Data System (ADS)

    Ohmura, Shunichi; Tsuru, Takeshi Go; Tanaka, Takaaki; Uchida, Hiroyuki; Takeda, Ayaki; Matsumura, Hideaki; Ito, Makoto; Arai, Yasuo; Kurachi, Ikuo; Miyoshi, Toshinobu; Nakashima, Shinya; Mori, Koji; Nishioka, Yusuke; Takebayashi, Nobuaki; Noda, Koki; Kohmura, Takayoshi; Tamasawa, Kouki; Ozawa, Yusuke; Sato, Tadashi; Konno, Takahiro; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita; Kamehama, Hiroki; Shrestha, Sumeet; Hara, Kazuhiko; Honda, Shunsuke

    2016-09-01

    We have been developing silicon-on-insulator pixel sensors, "XRPIXs," for future X-ray astronomy satellites. XRPIXs are equipped with a function of "event-driven readout," with which we can read out only hit pixels by trigger signals and hence realize good time resolution reaching ∼ 10 μs . The current version of XRPIX suffers from a problem that the spectral performance degrades in the event-driven readout mode compared to the frame-readout mode, in which all the pixels are read out serially. Previous studies have clarified that one of the causes is capacitive coupling between the sense node and the trigger signal line in the circuit layer. In order to solve the problem, we adopt the Double SOI structure having a middle silicon layer between the circuit and the sensor layers. We expect the middle silicon layer to work as an electrostatic shield and reduces the capacitive coupling. In this paper, we report the spectroscopic performance of XRPIX with the middle silicon layer. We successfully reduce the capacitive coupling and the readout noise.

  17. SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Almad

    2009-01-01

    Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80

  18. Worst case total dose radiation response of 0.35 {micro}m SOI CMOSFETs

    SciTech Connect

    Liu, S.T.; Balster, S.; Sinha, S.; Jenkins, W.C.

    1999-12-01

    Through experimental results and analysis by TSUPREM4/MEDICI simulations, the worst case back gate total dose bias condition is established for body tied SOI NMOSFETs. Utilizing the worst-case bias condition, a recently proposed model that describes the back n-channel threshold voltage shift as a function of total dose, TSUPREM4/MEDICI simulations, and circuit level SPICE simulations, a methodology to model post-rad standby current is developed and presented. This methodology requires the extraction of fundamental starting material/material preparation constants, and then can be utilized to examine post-rad stand-by current at the device and circuit level as function of total dose. Good agreement between experimental results and simulations is demonstrated.

  19. A new partial SOI power device structure with P-type buried layer

    NASA Astrophysics Data System (ADS)

    Duan, Baoxing; Zhang, Bo; Li, Zhaoji

    2005-12-01

    A new BPSOI (buried layer partial SOI) structure is developed, in which the P-type buried layer is implanted into the P - substrate by silicon window underneath the source of the conventional PSOI. The mechanism of breakdown is that the additional electric field produced by P-type buried layer charges modulates surface electric field, which decreases drastically the electric field peaks near the drain and source junctions. Moreover, the on-resistance of BPSOI is decreased as a result of increasing drift region doping due to neutralism of P-type buried layer. The results indicate that the breakdown voltage of BPSOI is increased by 52-58% and the on-resistance is decreased by 45-48% in comparison to conventional PSOI in virtue of 2-D numerical simulations using MEDICI.

  20. Seismic Study of the Solar Interior: Inferences from SOI/MDI Observations During Solar Activity

    NASA Technical Reports Server (NTRS)

    Korzennik, Sylvain G.; Wagner, William J. (Technical Monitor)

    2005-01-01

    Work on the structure, asphericity and dynamics of the solar interior from p-mode frequencies and frequency splittings was carried out primarily in collaboration with Dr. Eff-Darwich (University of La Laguna, Tenerife). This ongoing collaboration produced new results for the inversion of the internal solar rotation rate and further development in inversion methodologies. It also resulted in inferences on the solar stratification. Substantial progress towards the characterization of high-degree p-modes has been achieved. In collaboration with Drs. Rabello-Soares and Schou (Stanford University), we have gained a clear conceptual understanding of the various elements that affect the leakage matrix of the SOI/MDI instrument. This work has precise implications on the properties and the characterization of the HMI instrument being developed for the SDO mission.

  1. The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

    NASA Astrophysics Data System (ADS)

    Mohapatra, S. K.; Pradhan, K. P.; Sahu, P. K.; Pati, G. S.; Kumar, M. R.

    2014-12-01

    In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™.

  2. Thin SOI lateral IGBT with band-to-band tunneling mechanism

    NASA Astrophysics Data System (ADS)

    Fu, Qiang; Tang, Zhaohuan; Tan, Kaizhou; Wang, Zhikuan; Mei, Yong

    2017-06-01

    In this paper, a novel 200V lateral IGBT on thin SOI layer with a band-to-band tunneling junction near the anode is proposed. The structure and the operating mechanism of the proposed IGBT are described and discussed. Its main feature is that the novel IGBT structure has a unique abrupt doped p++/n++ tunneling junction in the side of the anode. By utilizing the reverse bias characteristics of the tunneling junction, the proposed IGBT can achieve excellent reverse conducting performance. Numerical simulations suggest that a low reverse conduction voltage drop VR=-1.6V at a current density of 100A/cm2 and a soft factor S=0.63 of the build-in diode are achieved.

  3. Design of novel SOI 1 × 4 optical power splitter using seven horizontally slotted waveguides

    NASA Astrophysics Data System (ADS)

    Katz, Oded; Malka, Dror

    2017-07-01

    In this paper, we demonstrate a compact silicon on insulator (SOI) 1 × 4 optical power splitter using seven horizontal slotted waveguides. Aluminum nitride (AIN) surrounded by silicon (Si) was used to confine the optical field in the slot region. All of the power analysis has been done in transverse magnetic (TM) polarization mode and a compact optical power splitter as short as 14.5 μm was demonstrated. The splitter was designed by using full vectorial beam propagation method (FV-BPM) simulations. Numerical investigations show that this device can work across the whole C-band (1530-1565 nm) with excess loss better than 0.23 dB.

  4. MONOLITHIC ACTIVE PIXEL MATRIX WITH BINARY COUNTERS IN AN SOI PROCESS.

    SciTech Connect

    DUPTUCH,G.; YAREMA, R.

    2007-06-07

    The design of a Prototype monolithic active pixel matrix, designed in a 0.15 {micro}m CMOS SOI Process, is presented. The process allowed connection between the electronics and the silicon volume under the layer of buried oxide (BOX). The small size vias traversing through the BOX and implantation of small p-type islands in the n-type bulk result in a monolithic imager. During the acquisition time, all pixels register individual radiation events incrementing the counters. The counting rate is up to 1 MHz per pixel. The contents of counters are shifted out during the readout phase. The designed prototype is an array of 64 x 64 pixels and the pixel size is 26 x 26 {micro}m{sup 2}.

  5. Body charge modelling for accurate simulation of small-signal behaviour in floating body SOI

    NASA Astrophysics Data System (ADS)

    Benson, James; Redman-White, William; D'Halleweyn, Nele V.; Easson, Craig A.; Uren, Michael J.

    2002-04-01

    We show that careful modelling of body node elements in floating body PD-SOI MOSFET compact models is required in order to obtain accurate small-signal simulation results in the saturation region. The body network modifies the saturation output conductance of the device via the body-source transconductance, resulting in a pole/zero pair being introduced in the conductance-frequency response. We show that neglecting the presence of body charge in the saturation region can often yield inaccurate values for the body capacitances, which in turn can adversely affect the modelling of the output conductance above the pole/zero frequency. We conclude that the underlying cause of this problem is the use of separate models for the intrinsic and extrinsic capacitances. Finally, we present a simple saturation body charge model which can greatly improve small-signal simulation accuracy for floating body devices.

  6. Mapping the broadband polarization properties of linear 2D SOI photonic crystal waveguides.

    PubMed

    Canning, John; Skivesen, Nina; Kristensen, Martin; Frandsen, Lars H; Lavrinenko, Andrei; Martelli, Cicero; Tetu, A

    2007-11-12

    Both quasi-TE and TM polarisation spectra for a silicon-on-insulator (SOI) waveguide are recorded over (1100-1700)nm using a broadband supercontinuum source. By studying both the input and output polarisation eigenstates we observe narrowband resonant cross coupling near the lowest quasi-TE mode cut-off. We also observe relatively broadband mixing between the two eigenstates to generate a complete photonic bandgap. By careful analysis of the output polarisation state we report on an inherent non-reciprocity between quasi TE and TM fundamental mode cross coupling. The nature of polarisation distinction in such bandgap structures is discussed in the context of polarisation scattering at an interface.

  7. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    NASA Astrophysics Data System (ADS)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  8. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    SciTech Connect

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  9. Properties of HfLaO MOS capacitor deposited on SOI with plasma enhanced atomic layer deposition

    SciTech Connect

    Wan, Wenyan; Cheng, Xinhong Cao, Duo; Zheng, Li; Xu, Dawei; Wang, Zhongjian; Xia, Chao; Shen, Lingyan; Yu, Yuehui; Shen, DaShen

    2014-01-15

    Amorphous HfLaO dielectric film was successfully deposited on a silicon-on-insulator (SOI) substrate by plasma enhanced atomic layer deposition with in situ plasma treatment. The HfLaO film retained its insulating characteristics and is thermally stable even after annealing at 800 °C. The film has a dielectric constant of 27.3 and leakage of only 0.03 mA/cm{sup 2} at a gate bias of |Vg − V{sub fb}| = 1 V. The capacitance equivalent oxide thickness is 0.7 nm. A new parallel electrode testing structure was applied to measure C–V and J–V characteristics for the SOI samples. This testing method for metal–oxide–semiconductor capacitors has potential uses for measuring other layered substrates.

  10. SOI metal-oxide-semiconductor field-effect transistor photon detector based on single-hole counting.

    PubMed

    Du, Wei; Inokawa, Hiroshi; Satoh, Hiroaki; Ono, Atsushi

    2011-08-01

    In this Letter, a scaled-down silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is characterized as a photon detector, where photogenerated individual holes are trapped below the negatively biased gate and modulate stepwise the electron current flowing in the bottom channel induced by the positive substrate bias. The output waveforms exhibit clear separation of current levels corresponding to different numbers of trapped holes. Considering this capability of single-hole counting, a small dark count of less than 0.02 s(-1) at room temperature, and low operation voltage of 1 V, SOI MOSFET could be a unique photon-number-resolving detector if the small quantum efficiency were improved.

  11. Design of monolithically integrated GeSi electro-absorption modulators and photodetectors on a SOI platform.

    PubMed

    Liu, Jifeng; Pan, Dong; Jongthammanurak, Samerkhae; Wada, Kazumi; Kimerling, Lionel C; Michel, Jurgen

    2007-01-22

    We present a design of monolithically integrated GeSi electroabsorption modulators and photodetectors for electronic-photonic integrated circuits on a silicon-on-insulator (SOI) platform. The GeSi electroabsorption modulator is based on the Franz-Keldysh effect, and the GeSi composition is chosen for optimal performance around 1550 nm. The designed modulator device is butt-coupled to Si(core)/SiO(2)(cladding) high index contrast waveguides, and has a predicted 3 dB bandwidth of >50 GHz and an extinction ratio of 10 dB. The same device structure can also be used for a waveguide-coupled photodetector with a predicted responsivity of > 1 A/W and a 3 dB bandwidth of > 35 GHz. Use of the same GeSi composition and device structure allows efficient monolithic process integration of the modulators and the photodetectors on an SOI platform.

  12. Design of monolithically integrated GeSi electro-absorption modulators and photodetectors on a SOI platform

    NASA Astrophysics Data System (ADS)

    Liu, Jifeng; Pan, Dong; Jongthammanurak, Samerkhae; Wada, Kazumi; Kimerling, Lionel C.; Michel, Jurgen

    2007-01-01

    We present a design of monolithically integrated GeSi electroabsorption modulators and photodetectors for electronic-photonic integrated circuits on a silicon-on-insulator (SOI) platform. The GeSi electroabsorption modulator is based on the Franz-Keldysh effect, and the GeSi composition is chosen for optimal performance around 1550 nm. The designed modulator device is butt-coupled to Si(core)/SiO2(cladding) high index contrast waveguides, and has a predicted 3 dB bandwidth of >50 GHz and an extinction ratio of 10 dB. The same device structure can also be used for a waveguide-coupled photodetector with a predicted responsivity of > 1 A/W and a 3 dB bandwidth of > 35 GHz. Use of the same GeSi composition and device structure allows efficient monolithic process integration of the modulators and the photodetectors on an SOI platform.

  13. Wide bandwidth and high coupling efficiency Si3N4-on-SOI dual-level grating coupler.

    PubMed

    Sacher, Wesley D; Huang, Ying; Ding, Liang; Taylor, Benjamin J F; Jayatilleka, Hasitha; Lo, Guo-Qiang; Poon, Joyce K S

    2014-05-05

    We propose and experimentally demonstrate fiber-to-chip grating couplers with aligned silicon nitride (Si(3)N(4)) and silicon (Si) grating teeth for wide bandwidths and high coupling efficiencies without the use of bottom reflectors. The measured 1-dB bandwidth is a record 80 nm, and the measured peak coupling efficiency is -1.3 dB, which is competitive with the best Si-only grating couplers. The grating couplers are integrated in a Si(3)N(4) on silicon-on-insulator (SOI) integrated optics platform with aligned waveguides in both the Si(3)N(4) and Si, and we demonstrate a 1 × 4 tunable multiplexer/demultiplexer using the Si(3)N(4)-on-SOI dual-level grating couplers and thermally-tuned Si microring resonators.

  14. Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

  15. Scaling of lowered source/drain (LSD) and raised source/drain (RSD) ultra-thin body (UTB) SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    An, Xia; Huang, Ru; Zhang, Xing; Wang, Yangyuan

    2005-03-01

    Ultra-thin body (UTB) SOI MOSFETs are considered as one of most promising candidates for deca-nano-scale regimes. The device characteristics of two different UTB MOSFETs with raised source/drain (RSD) and lowered source/drain (LSD), respectively, are investigated with DC and AC considerations. The results suggest that LSD-UTB SOI MOSFETs show better control of the off-state leakage current, about one order of magnitude lower than that of RSD-UTB MOSFETs. The short-channel effect (SCE) and drain-induced-barrier-lowering (DIBL) effect are more effectively suppressed in LSD-UTB MOSFETs. And the intrinsic delay of LSD-UTB device is smaller than that of RSD-UTB as a result of the greatly reduced parasitic capacitance. In addition, the LSD-UTB MOSFETs demonstrate better scaling capability than RSD-UTB MOSFETs. And LSD-UTB can greatly relax the requirement for silicon body thickness by ˜60%.

  16. Isolation and characterization of Escherichia coli strains containing new gene fusions (soi::lacZ) inducible by superoxide radicals.

    PubMed Central

    Mito, S; Zhang, Q M; Yonei, S

    1993-01-01

    Gene fusions in Escherichia coli that showed increased beta-galactosidase expression in response to treatment with a superoxide radical (O2-) generator, methyl viologen (MV), were obtained. These fusions were constructed by using a Mud(Ap lac) phage to insert the lactose structural genes randomly into the E. coli chromosome. Ampicillin-resistant colonies were screened for increased expression of beta-galactosidase on X-Gal (5-bromo-4-chloro-3-indolyl-beta-D-galactopyranoside) plates containing MV at 1.25 micrograms/ml. Other O2- generators, menadione and plumbagin, also induced beta-galactosidase activity in these fusion strains. The induction by these drugs occurred only under aerobic conditions. Hyperoxygenation also elicited an induction of the fusions. On the other hand, no significant induction was observed with hydrogen peroxide and cumene hydroperoxide. The induction of these fusions by MV was not dependent on the peroxide stress control mediated by the oxyR gene or on the recA-dependent SOS system. These fusions were named soi (superoxide inducible)::lacZ. The induction of beta-galactosidase was significantly reduced by introducing a soxS::Tn10 locus into the fusion strains, indicating that the soi genes are members of the soxRS regulon. Five of the fusions were located in 6 to 26 min of the E. coli genetic map, while three fusions were located in 26 to 36 min, indicating that these fusions are not related to genes already known to be inducible by O2- under the control of soxRS. At least five mutants containing the soi::lacZ fusion were more sensitive to MV and menadione than the wild-type strain, suggesting that the products of these soi genes play an important role in protection against oxidative stress. PMID:8386722

  17. Upper drift region double step partial SOI LDMOSFET: A novel device for enhancing breakdown voltage and output characteristics

    NASA Astrophysics Data System (ADS)

    Jamali Mahabadi, S. E.

    2016-01-01

    A new LDMOSFET structure called upper drift region double step partial silicon on insulator (UDDS-PSOI) is proposed to enhance the breakdown voltage (BV) and output characteristics. The proposed structure contains two vertical steps in the top surface of the drift region. It is demonstrated that in the proposed structure, the lateral electric field distribution is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions. The electric field distribution in the drift region is modulated and that of the buried layer is enhanced by the two steps in the top surface of the drift region, thereby resulting in the enhancement of the BV. The effect of device parameters, such as the step height and length in the top surface of the drift region, the doping concentration in the drift region, and the buried oxide length and thickness, on the electric field distribution and the BV of the proposed structure is studied. Simulation results from two-dimensional ATLAS simulator show that the BV of the UDDS-PSOI structure is 120% and 220% higher than that of conventional partial SOI (C-PSOI) and conventional SOI (C-SOI) structures, respectively. Furthermore, the drain current of the UDDS-PSOI is 11% larger than the C-PSOI structure with a drain-source voltage VDS = 100 V and gate-source voltage VGS = 5 V. Simulation results show that Ron in the proposed structure is 74% and 48% of that in C-PSOI and C-SOI structures, respectively.

  18. Plasmonic nanogratings on MIM and SOI thin-film solar cells: comparison and optimization of optical and electric enhancements.

    PubMed

    Heydari, Mehdi; Sabaeian, Mohammad

    2017-03-01

    In this work, Ag nanogratings comprised of arrays of nanostrips with three different cross sections of triangular, rectangular, and trapezoidal shape were considered and put at the top of the thin-film metal-insulator-metal (MIM) and semiconductor-on-insulator (SOI) solar cells. Then, the optical absorption and the short-circuit current density (JSC) enhancement (relative to a bare cell) were calculated and compared. In addition, the best strip cross section among three types of cross sections and the optimum grating period were found. The results showed that for the transverse electric (TE) mode, only the waveguide modes were excited inside the Si active layer with the assistance of Ag nanogratings. For the transverse magnetic (TM) mode, the waveguide as well as the localized surface plasmonic (LSP) modes were excited. The LSP modes, which were excited at the longer wavelengths centered on ∼600  nm, led to an additional and consequently a larger JSC enhancement. Finally, among the various types of plasmonic SOI and MIM solar cells, a SOI cell with a 300 nm grating period, comprised of rectangular nanostrips, showed a 40% enhancement in JSC, which is the highest possible value achieved in this work.

  19. Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper

    PubMed Central

    Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

    2014-01-01

    A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM0 mode into the TE1 mode, which will output as the TE0 mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < −17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology. PMID:25402029

  20. A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-k dielectric

    NASA Astrophysics Data System (ADS)

    Gopi Krishna, Saramekala; Sarvesh, Dubey; Pramod, Kumar Tiwari

    2015-10-01

    In this paper, a surface potential based threshold voltage model of fully-depleted (FD) recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional (2D) Poisson’s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model’s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters, including the dielectric constant of gate-dielectric material. The author, Pramod Kumar Tiwari, was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology, Ministry of Human Resource and Development, Government of India under Young Scientist Research (Grant No. SB/FTP/ETA-415/2012).

  1. Impact of hot-carrier stress on gate-induced floating body effects and drain current transients of thin gate oxide partially depleted SOI nMOSFETs

    NASA Astrophysics Data System (ADS)

    Rafí, J. M.; Simoen, E.; Mercha, A.; Campabadal, F.; Claeys, C.

    2005-09-01

    The impact of hot-carrier (HC) stress on thin gate oxide PD SOI nMOSFETs is investigated by analyzing the front and back channel current-voltage characteristics and the switch-off drain current transients. A particular hot-carrier degradation mode, characterized by a turn-around behavior for front gate threshold voltage degradation, is analyzed for devices with different geometries, bias conditions and source/drain architecture. A significant positive back gate threshold voltage shift is also observed after long HC stress. The maximum hot-carrier degradation (HCD) is obtained for the highest front gate biases, corresponding to the conditions of maximum electron valence band injection of majority carriers into the floating body. The presence of the HCD is found to reduce both the generation and the recombination switch-off drain current transient times. Unbiased thermal annealing in the range of 200-250 °C significantly reduces the hot-carrier-induced damage affecting the back channel characteristics. Whereas front gate direct tunnel stress is not causing any significant degradation for stress biases up to about two times the power supply for this technology node and reasonably short stress times, for the highest stress conditions the drain current transients are found to be progressively faster till front gate dielectric breakdown occurs.

  2. A technique for simultaneously improving the product of cutoff frequency-breakdown voltage and thermal stability of SOI SiGe HBT

    NASA Astrophysics Data System (ADS)

    Fu, Qiang; Zhang, Wan-Rong; Jin, Dong-Yue; Zhao, Yan-Xiao; Wang, Xiao

    2016-12-01

    The product of the cutoff frequency and breakdown voltage (fT×BVCEO) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (TBOX) on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEO to some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT, BVCEO, and the FOM of fT×BVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEO is improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer

  3. Technology.

    ERIC Educational Resources Information Center

    Giorgis, Cyndi; Johnson, Nancy J.

    2002-01-01

    Presents annotations of 30 works of children's literature that support the topic of technology and its influences on readers' daily lives. Notes some stories tell about a time when simple tools enabled individuals to accomplish tasks, and others feature visionaries who used technology to create buildings, bridges, roads, and inventions. Considers…

  4. Technology

    ERIC Educational Resources Information Center

    Isman, Aytekin

    2003-01-01

    This article begins by drawing on literature to examine the various definitions of "technology" and "technique." Following a discussion of the origin of technology in education, the remaining sections of the article focus on the relationships and interaction between: (1) machines and technique; (2) science and technique; (3)…

  5. Line-edge roughness induced single event transient variation in SOI FinFETs

    NASA Astrophysics Data System (ADS)

    Weikang, Wu; Xia, An; Xiaobo, Jiang; Yehua, Chen; Jingjing, Liu; Xing, Zhang; Ru, Huang

    2015-11-01

    The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (Vgs = 0, Vds = Vdd) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

  6. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    SciTech Connect

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-04-24

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10{sup −9} of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

  7. SOI waveguide fabrication process development using star coupler scattering loss measurements

    NASA Astrophysics Data System (ADS)

    Yap, K. P.; Lapointe, J.; Lamontagne, B.; Delâge, A.; Bogdanov, A.; Janz, S.; Syrett, B.

    2007-12-01

    We show that integrated optical star couplers can be useful characterization devices to measure the sidewall roughness-induced scattering losses of planar waveguides. We describe the detailed fabrication processes of these star couplers on the silicon-on-insulator (SOI) platform and the process improvements implemented to reduce the waveguide sidewall roughness and scattering loss. We report the main process challenges, particularly to assure a clear gap between any adjacent waveguides of the dense and closely spaced output waveguide array. These challenges are addressed by optimizing the exposure dose of the resist and adding an oxygen ashing treatment to eliminate waveguide footings. We demonstrate further improvement on the waveguide profile and sidewall roughness through the use of a thin Cr hardmask for the dry plasma etching. This optimized fabrication process is capable of producing approximately a 3 nm root-mean-square sidewall roughness, measured using both scanning electron microscopy (SEM) and atomic force microscopy (AFM). Using the fabricated star couplers, we manage to measure the relative scattering losses of various waveguides with the width varying from 0.2 to 2.0 μm in a single measurement, and show that the measured losses agree with the measured sidewall roughness.

  8. A novel high breakdown voltage lateral bipolar transistor on SOI with multizone doping and multistep oxide

    NASA Astrophysics Data System (ADS)

    Loan, Sajad A.; Qureshi, S.; Iyer, S. S. Kumar

    2009-02-01

    A novel high breakdown voltage lateral bipolar junction transistor (LBJT) on silicon-on- insulator (SOI) is proposed. The novelty of the device is the use of the combination of multistep-doped drift region and multistep buried oxide. The steps in doping and in oxide thickness have been used as a replacement for much complex linearly varying drift doping and linearly varying oxide thickness. The LBJT structure incorporating the combination of multistep doping and multistep oxide is analyzed for electrical characteristics using a two-dimensional numerical simulator MEDICI. Numerical simulation has demonstrated that the breakdown voltage of the proposed device with a two-zone step doped (TZSD) drift region is >150% higher than the conventional device. It has been observed that increasing the number of doping zones to 3 from 2 results in a >40% rise in breakdown voltage. The proposed device gives high breakdown voltage even at high doping concentration in the collector drift region. This reduces the on-resistance of the device and thus improves its speed. The dependence of breakdown voltage on various device parameters has been extensively studied to achieve optimum device performance. A process flow for the device fabrication is also being proposed.

  9. On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX

    NASA Astrophysics Data System (ADS)

    Hao, Wu; Miao, Xu; Guangxing, Wan; Huilong, Zhu; Lichuan, Zhao; Xiaodong, Tong; Chao, Zhao; Dapeng, Chen; Tianchun, Ye

    2014-11-01

    The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions (LNDD) is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, Vt-roll-off, channel mobility and random dopant fluctuation (RDF) are studied and optimized. Fixing the long channel threshold voltage (Vt) at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing Vt at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated.

  10. Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

    NASA Astrophysics Data System (ADS)

    Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

    2016-09-01

    In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

  11. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    NASA Astrophysics Data System (ADS)

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-04-01

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (˜ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and - 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10-9 of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

  12. Electrical detection of amine ligation to a metalloporphyrin via a hybrid SOI-MOSFET.

    PubMed

    Takulapalli, Bharath R; Laws, Gez M; Liddell, Paul A; Andréasson, Joakim; Erno, Zach; Gust, Devens; Thornton, Trevor J

    2008-02-20

    A close-packed monolayer of zinc 5,10,15,20-tetrakis(3-carboxyphenyl)porphyrin has been prepared and deposited on the thin native oxide covering the surface of an SOI-MOSFET (silicon-on-insulator metal-oxide-semiconductor field effect transistor) using Langmuir-Blodgett techniques. When the device is exposed to amine vapors in a nitrogen atmosphere, the amine coordinates to the zinc atom. The resulting change in electron distribution within the porphyrin leads to a large change in the drain current of the transistor, biased via a back gate. This change is sensitive to both the amount of amine present and the base strength of the amine. Only very small changes in drain current were observed with a monolayer of free base porphyrin or palmitic acid. After exposure to high pyridine concentrations, the device response saturates, but partially recovers after overnight exposure to flowing nitrogen gas. Interestingly, the device response is instantaneously reset by exposure to visible light, suggesting that photode-ligation occurs. An electrical model for the hybrid device that describes its response to ligand binding in terms of a change in the work function of the porphyrin monolayer has been developed. A transistor response to a few hundred attomoles of bound pyridine can be readily detected. This extreme sensitivity, coupled with the ability to reset the device using light, suggests that such systems might be useful as sensors.

  13. SoiLique: A MATLAB® Based Program to analyze soil Liquefaction and some applications/comparisons

    NASA Astrophysics Data System (ADS)

    Bekin, Ekrem; Özçep, Ferhat

    2017-04-01

    Soil liquefaction is one of the ground failures induced by earthquakes. During dynamic loading, i.e. an earthquake, pore water pressure increases in undrained and cohesionless soils. Therefore, soils lose their solid behavior and act as if liquefied materials. In general, the earthquake hazard risk increases because of the liquefied behavior. In order to decrease liquefaction-induced failures and hazards, some empirical formulas have been used over decades. A unitless parameter, the safety factor, can be calculated by the help of these empirical formulas. The safety factor of liquefaction can be calculated from different in-situ tests (i.e. SPT or CPT) and the shear wave velocity of a corresponding research area. In addition to the safety factor, the consolidation depending on soil liquefaction can be calculated. The aim of this study is writing a MATLAB® gui to make soil liquefaction analysis (namely, calculations mentioned above). In other words, SoiLique calculates Cyclic Stress Ratio, Cyclic Resistance Ratio (from SPT, CPT, and shear wave velocity), the safety factor of liquefaction and consolidation depending on liquefaction. Some applications from liquefied sites in Turkey and some comparisons with other liquefaction software will be carried out.

  14. Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

    PubMed

    Takulapalli, Bharath R

    2010-02-23

    Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

  15. A dicing-free SOI process for MEMS devices based on the lag effect

    NASA Astrophysics Data System (ADS)

    Xie, J.; Hao, Y.; Shen, Q.; Chang, H.; Yuan, W.

    2013-12-01

    This paper presents a dicing-free process for silicon-on-insulator (SOI) microelectromechanical systems (MEMS). In the process, the lag effect in deep reactive ion etching (DRIE) is used to form the breaking trenches. In the backside DRIE, the wide backside cavities are etched down to the buried oxide layer. The narrow breaking trenches, in contrast, are not etched to the buried oxide layer. Therefore, the narrow trench can be used to break the wafer after the entire process; in addition, the handle layer can still act as a bracing structure before ‘breaking’. Finally, the device layer is patterned, and a DRIE step is used to form the MEMS devices. In this way, the dicing step can be omitted to prevent further damages from high pressure water jets and silicon dust. Meanwhile, the process can also prevent notching simply because the insulating layer is removed before device etching. To demonstrate the feasibility of the proposed fabrication process, a micromachined gyroscope is designed and fabricated.

  16. Design and test of elementary digital circuits based on monolithic SOI JFET`s

    SciTech Connect

    Fourches, N.

    1998-02-01

    Quite recently, designing circuits for high-energy physics experiments has become of vital importance. Here, silicon on insulator (SOI) junction field effect transistor (JFET`s) are used to develop digital gates for cryogenic applications. Only one type of JFET is necessary to design an NOR gate using a basic inverter circuit and a level shifter. The JFET`s involved in these designs are available in a process radiation hard at room temperature and operate with improved characteristics at cryogenic temperatures (90 K, temperature of liquid Argon calorimeters for high-energy physics). Test circuits have been designed to evaluate their performance. The measured characteristics prove to be satisfactory compared to the simulated ones, although some improvements are still necessary. A propagation delay of 4.4 ns per gate for a power dissipation of {approx}3 mW per gate is obtained. With the present development of cryogenic front end preamplifiers for the readout of calorimeter signals, this study opens some prospects for integrating more mixed digital analog electronics such as pipelines within the detectors.

  17. Low-loss delay lines with small footprint on a micron-scale SOI platform

    NASA Astrophysics Data System (ADS)

    Cherchi, Matteo; Harjanne, Mikko; Vyrsokinos, Konstantinos; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani; Aalto, Timo

    2015-02-01

    Long and yet compact spiral waveguides based on micron-scale silicon strip waveguides has been enabled very recently by the introduction of the Euler bends. By ensuring effective broadband single mode operation of otherwise highly multimodal waveguides, these bends can have very low losses (<0.01 dB/90°) even with effective radii of a few microns. Together with the low propagation losses (< 0.15 dB/cm) of micron-scale strip waveguides, these bends enable centimeter-long delay lines with negligible losses and very small foot-print (< 1 mm2). In particular, interferometers delayed by ≈ 1 cm long spirals on one of the two arms have been fabricated on SOI wafers with both 3 um- and 4 umthick silicon layer, based on the well assessed process developed by VTT. The full devices have footprint smaller than 1.5 mm2, and they have been measured to have extinction ratios < 15 dB (reaching up to 21 dB) and about 3 dB excess losses. Functional characterization of the delayed interferometers at about 10 Gbps through demodulation of pseudorandom Differential Phase Shift Keying signals led to clearly opened eye diagrams with Q factor of 8.6 and bit error rates lower than 10-15.

  18. Results and limits in the 1-D analytical modeling for the asymmetric DG SOI MOSFET

    NASA Astrophysics Data System (ADS)

    Cobianu, O.; Glesner, M.

    2008-05-01

    This paper presents the results and the limits of 1-D analytical modeling of electrostatic potential in the low-doped p type silicon body of the asymmetric n-channel DG SOI MOSFET, where the contribution to the asymmetry comes only from p- and n-type doping of polysilicon used as the gate electrodes. Solving Poisson's equation with boundary conditions based on the continuity of normal electrical displacement at interfaces and the presence of a minimum electrostatic potential by using the Matlab code we have obtained a minimum potential with a slow variation in the central zone of silicon with the value pinned around 0.46 V, where the applied VGS voltage varies from 0.45 V to 0.95 V. The paper states clearly the validity domain of the analytical solution and the important effect of the localization of the minimum electrostatic potential value on the potential variation at interfaces as a function of the applied VGS voltage.

  19. SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

    SciTech Connect

    Trimpl, M.; Deptuch, G.; Yarema, R.; /Fermilab

    2010-11-01

    This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm{sup 2} large detector array with 20 {micro}m and 40 {micro}m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

  20. A band-modulation device in advanced FDSOI technology: Sharp switching characteristics

    NASA Astrophysics Data System (ADS)

    El Dirani, Hassan; Solaro, Yohann; Fonteneau, Pascal; Legrand, Charles-Alex; Marin-Cudraz, David; Golanski, Dominique; Ferrari, Philippe; Cristoloveanu, Sorin

    2016-11-01

    A band-modulation device is demonstrated experimentally in advanced FDSOI (Fully Depleted SOI). The Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a very recent sharp switching device which achieves remarkable performance in terms of leakage current and triggering control. The device is fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator (SOI) technology, features an extremely sharp on-switch, low leakage and an adjustable triggering voltage (VON). The Z2-FET operation relies on the modulation of electrons and holes injection barriers. In this paper, we show, for the first time, experimental data obtained with the most advanced FDSOI node.

  1. Special Technology Area Review on Spintronics. Report of Department of Defense Advisory Group on Electron Devices Working Group B (Microelectronics)

    DTIC Science & Technology

    2004-06-01

    deposited on the CMOS SOI wafer after the third metal level. NVE is developing a magneto- thermal GMR technology that has significantly reduced write...evaluation sensors for faults on airplane wings. "* NVE is developing a magneto- thermal GMR technology that has significantly reduced write current by...for the MTJ-MRAM technology, such as the magneto- thermal technology, should be continued. The all-metal SpinRAM technology is theoretically capable of

  2. An IO block array in a radiation-hardened SOI SRAM-based FPGA

    NASA Astrophysics Data System (ADS)

    Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

    2012-01-01

    We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

  3. Seismic Study of the Solar Interior: Inferences from SOI/MDI Observations During Solar Activity

    NASA Technical Reports Server (NTRS)

    Korzennik, Sylvain G.; Wagner, William J. (Technical Monitor)

    2001-01-01

    We have continued in collaboration with Dr. Eff-Darwich (University of La Laguna, Tenerife, Spain) the study of the structure, asphericity and dynamics of the solar interior from p-mode frequencies and frequency splittings. In March 2001, Dr. Eff-Darwich came for 3 weeks visit to CfA. During this visit we completed our work on the inversion of the internal solar rotation rate, and submitted a paper describing this work to the Astrophysical Journal. This paper has been recently revised in response to the referee comments and I expect that it will be accepted for publication very soon. We also have analyzed helioseismic data looking for temporal variations of the solar stratification near the base of the convection zone. We have expanded on the initial work that was presented at the SOHO-10/GONG-2000 meeting (October 2000, Tenerife), and are in the process of writing this up. Substantial progress towards the characterization of high-degree p-modes has been achieved. Indeed, in collaboration Dr. Rabello-Soares (Stanford University), we have gained a clear conceptual understanding of the various elements that affect the leakage matrix of the SOI/MDI instrument. This was presented in an invited talk at the SOHO-10/GONG-2000 meeting (October 2000, Tenerife). Once we will have successfully migrated from a qualitative to a quantitative assessment of these effects, we should be able to generate high-degree p-modes frequencies so crucial in the diagnostic of the layers just below solar surface.

  4. Seismic Study of the Solar Interior: Inferences from SOI/MDI Observations During Solar Activity

    NASA Technical Reports Server (NTRS)

    Korzennik, Sylvain G.; Wagner, William J. (Technical Monitor)

    2001-01-01

    We have continued in collaboration with Dr. Eff-Darwich (University of La Laguna, Tenerife, Spain) the study of the structure, asphericity and dynamics of the solar interior from p-mode frequencies and frequency splittings. In March 2001, Dr. Eff-Darwich came for 3 weeks visit to CfA. During this visit we completed our work on the inversion of the internal solar rotation rate, and submitted a paper describing this work to the Astrophysical Journal. This paper has been recently revised in response to the referee comments and I expect that it will be accepted for publication very soon. We also have analyzed helioseismic data looking for temporal variations of the solar stratification near the base of the convection zone. We have expanded on the initial work that was presented at the SOHO-10/GONG-2000 meeting (October 2000, Tenerife), and are in the process of writing this up. Substantial progress towards the characterization of high-degree p-modes has been achieved. Indeed, in collaboration Dr. Rabello-Soares (Stanford University), we have gained a clear conceptual understanding of the various elements that affect the leakage matrix of the SOI/MDI instrument. This was presented in an invited talk at the SOHO-10/GONG-2000 meeting (October 2000, Tenerife). Once we will have successfully migrated from a qualitative to a quantitative assessment of these effects, we should be able to generate high-degree p-modes frequencies so crucial in the diagnostic of the layers just below solar surface.

  5. Global and Local Helioseismic Studies of Solar Convection Zone Dynamics Using SOI-MDI on SOHO

    NASA Technical Reports Server (NTRS)

    Toomre, Juri; Haber, Deborah; Hindman, Bradley; Christensen-Dalsgaard, Joergen; Gough, Douglas; Thompson, Michael

    2003-01-01

    Our joint collaborative analyses of global mode data to characterize the solar differential rotation (e.g. Thompson et al. 1996, Schou et al. 1998), and most recently to detect and analyze temporal variations in angular velocity Omega profiles both within the convection zone and in the deeper radiative interior (e.g. Howe et al 2000a,b; Toomre et al. 2000), have led to a series of fascinating discoveries. These should be pursued further as the solar cycle continues. The physical deductions being made from these studies have been greatly strengthened by utilizing both SOI-MDI and GONG data in order to have two independent observational realizations of Doppler images spanning a five-year interval, using two separate procedures to determine global mode splittings, and then analyzing those splitting data sets using both RLS and SOLA inversion procedures. There are considerable subtleties in the effects of instrumental response functions and calibrations, sensitivity of peak finding algorithms and their mode leakage estimates, and stochastic variations in mode amplitudes that can all contribute to apparent changes in the Omega profiles being inferred from sequences of helioseismic data. We have come to understand the implications of many of these calibration and analysis steps, greatly aided by frequent multi-week collaborative working sessions in our Helioseismic Analysis Facility (HAF) at JILA involving many members of the SO1 dynamics and inversion team, including most of our Co-Is during the summer months when we hold intensive working sessions. Considerable further focused attention is required in a collaborative setting on such global mode issues as we continue studying the changing sun.

  6. Technology.

    ERIC Educational Resources Information Center

    Online-Offline, 1998

    1998-01-01

    Focuses on technology, on advances in such areas as aeronautics, electronics, physics, the space sciences, as well as computers and the attendant progress in medicine, robotics, and artificial intelligence. Describes educational resources for elementary and middle school students, including Web sites, CD-ROMs and software, videotapes, books,…

  7. Technology.

    ERIC Educational Resources Information Center

    Online-Offline, 1998

    1998-01-01

    Focuses on technology, on advances in such areas as aeronautics, electronics, physics, the space sciences, as well as computers and the attendant progress in medicine, robotics, and artificial intelligence. Describes educational resources for elementary and middle school students, including Web sites, CD-ROMs and software, videotapes, books,…

  8. Rad-Hard Microcontroller for Space Applications

    NASA Astrophysics Data System (ADS)

    Habinc, Sandi; Johansson, Fredrik; Sturesson, Fredrik; Simlastik, Martin; Hjorth, Magnus; Andersson, Jan; Redant, Steven; Sijbers, Wim; Thys, Geert; Monteleone, Claudio

    2015-09-01

    This paper describes a mixed-signal LEON3FT microcontroller ASIC (Application Specific Integrated Circuit) targeting embedded control applications with hard real-time requirements. The prototype device is currently in development at Cobham Gaisler, Sweden, and IMEC, Belgium, in the activity Microcontroller for embedded space applications, initiated and funded by the European Space Agency (ESA).

  9. A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

    NASA Astrophysics Data System (ADS)

    Jamali Mahabadi, S. E.; Rajabi, Saba; Loiacono, Julian

    2015-09-01

    In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs. Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100 μA), at drain-source voltage of VDS = 100 V and gate-source voltage of VGS = 25 V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87 μA and 51 μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

  10. A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

    NASA Astrophysics Data System (ADS)

    Priya, Anjali; Mishra, Ram Awadh

    2016-04-01

    In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

  11. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    SciTech Connect

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  12. SEMICONDUCTOR DEVICES: A three-dimensional breakdown model of SOI lateral power transistors with a circular layout

    NASA Astrophysics Data System (ADS)

    Yufeng, Guo; Zhigong, Wang; Gene, Sheu

    2009-11-01

    This paper presents an analytical three-dimensional breakdown model of SOI lateral power devices with a circular layout. The Poisson equation is solved in cylindrical coordinates to obtain the radial surface potential and electric field distributions for both fully- and partially-depleted drift regions. The breakdown voltages for N+N and P+N junctions are derived and employed to investigate the impact of cathode region curvature. A modified RESURF criterion is proposed to provide a design guideline for optimizing the breakdown voltage and doping concentration in the drift region in three dimensional space. The analytical results agree well with MEDICI simulation results and experimental data from earlier publications.

  13. Modeling and analysis of surface potential of single gate fully depleted SOI MOSFET using 2D-Poisson's equation

    NASA Astrophysics Data System (ADS)

    Mani, Prashant; Tyagi, Chandra Shekhar; Srivastav, Nishant

    2016-03-01

    In this paper the analytical solution of the 2D Poisson's equation for single gate Fully Depleted SOI (FDSOI) MOSFET's is derived by using a Green's function solution technique. The surface potential is calculated and the threshold voltage of the device is minimized for the low power consumption. Due to minimization of threshold voltage the short channel effect of device is suppressed and after observation we obtain the device is kink free. The structure and characteristics of SingleGate FDSOI MOSFET were matched by using MathCAD and silvaco respectively.

  14. Analysis of the thin-film SOI lateral bipolar transistor and optimization of its output characteristics for high-temperature applications

    NASA Astrophysics Data System (ADS)

    Adriaensen, S.; Flandre, D.

    2002-09-01

    In this paper, we investigate and optimize the static characteristics of NPN lateral bipolar transistors implemented in a thin-film fully-depleted SOI CMOS process for high-temperature analog applications. The basic lateral SOI bipolar device, which shows good behaviour in high-temperature circuits in spite of its relatively poor performances, is firstly described regarding its process and layout parameters. Then the concept of the graded-base bipolar transistor is introduced. This device presents significantly improved output characteristics while preserving standard current gain and CMOS process compatibility. Measurements and simulations are used to demonstrate the improvements of the breakdown voltage and the Early voltage of the bipolar device.

  15. Oxides formation on hydrophilic bonding interface in plasma-assisted InP/Al2O3/SOI direct wafer bonding

    NASA Astrophysics Data System (ADS)

    Gong, Kewei; Sun, Changzheng; Xiong, Bing; Han, Yanjun; Hao, Zhibiao; Wang, Jian; Wang, Lai; Li, Hongtao

    2017-01-01

    Successful direct wafer bonding between InP and silicon-on-insulator (SOI) wafers has been demonstrated by adopting a 20-nm-thick Al2O3 as the intermediate layer. A detailed investigation on the property of the bonding interface is carried out. Water contact angle test reveals an improved hydrophilicity for both the InP and the Al2O3/SOI wafers after oxygen plasma surface activation. X-ray photoelectron spectroscopy is employed to characterize the bonding interface before and after the wafer bonding process. It is found that oxides are formed on the bonding interface during bonding, which helps ensure high quality hydrophilic bonding.

  16. The nature and impact of chronic stressors on refugee children in Ban Mai Nai Soi camp, Thailand.

    PubMed

    Meyer, Sarah; Murray, Laura K; Puffer, Eve S; Larsen, Jillian; Bolton, Paul

    2013-01-01

    Refugee camps are replete with risk factors for mental health problems among children, including poverty, disruption of family structure, family violence and food insecurity. This study, focused on refugee children from Burma, in Ban Mai Nai Soi camp in Thailand, sought to identify the particular risks children are exposed to in this context, and the impacts on their mental health and psychosocial well-being. This study employed two qualitative methods--free list interviews and key informant interviews--to identify the main problems impacting children in Ban Mai Nai Soi camp and to explore the causes of these problems and their impact on children's well-being. Respondents in free list interviews identified a number of problems that impact children in this context, including fighting between adults, alcohol use by adults and children, and child abuse and neglect. Across the issues, the causes included economic and social conditions associated with living in the camp and changes in family structures. Children are chronically exposed to stressors during their growth and development in the camp environment. Policies and interventions in areas of protracted displacement in camp-based settings should work to address these stressors and their impacts at community, household and individual levels.

  17. Comparison of short-circuit characteristics of trench gate and planar gate U-shaped channel SOI-LIGBTs

    NASA Astrophysics Data System (ADS)

    Zhang, Long; Zhu, Jing; Sun, Weifeng; Zhao, Minna; Huang, Xuequan; Chen, Jiajun; Shi, Longxing; Chen, Jian; Ding, Desheng

    2017-09-01

    Comparison of short-circuit (SC) characteristics of 500 V rated trench gate U-shaped channel (TGU) SOI-LIGBT and planar gate U-shaped channel (PGU) SOI-LIGBT is made for the first time in this paper. The on-state carrier profile of the TGU structure is reshaped by the dual trenches (a gate trench G1 and a hole barrier trench G2), which leads to a different conduction behavior from that of the PGU structure. The TGU structure exhibits a higher latchup immunity but a severer self-heating effect. At current density (JC) < 640 A/cm2, the SC destruction is suspected to be latchup-dependent and short-circuit withstand time (tSC) of the TGU structure is much longer than that of the PGU structure. Due to the high lattice temperature rise caused by the high current density at the emitter side in the TGU structure, the PGU exhibits a better JC-tSC trade-off at JC > 640 A/cm2. Comparison of layouts and fabrication processes are also made between the two types of devices.

  18. Impact of Ge profile on the performance of PNP SiGe HBT on thin film SOI

    NASA Astrophysics Data System (ADS)

    Misra, Prasanna K.; Qureshi, S.

    2012-10-01

    The pnp SiGe HBT on thin film SOI is investigated with different Ge profiles using 2D numerical simulations in MEDICI. The base current, collector current, DC current gain, AC voltage gain, unity current gain frequency and breakdown voltage is obtained for a 0.09 × 1.0 μm2 pnp SiGe HBT with triangular (0%-30%), trapezoidal (10%- 20%) and box (15%) Ge profiles in the base layer. The results obtained with the Ge profiles, has been analyzed and compared. The Ft BVCEO product for triangular, trapezoidal and box Ge profiles has been found as 190.8, 401, and 359.6 GHzV respectively. The tradeoff between voltage gain and unity current gain frequency for the Ge profiles has been analyzed. The simulation result suggests that the pnp SiGe HBT on thin film SOI with trapezoidal Ge profile is a potential candidate for the high speed complementary bipolar circuits that can be used in high performance mixed signal applications.

  19. One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

    NASA Astrophysics Data System (ADS)

    Zhang, Jun; Guo, Yu-Feng; Xu, Yue; Lin, Hong; Yang, Hui; Hong, Yang; Yao, Jia-Fei

    2015-02-01

    A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device. Project supported by the National Natural Science Foundation of China (Grant No. 61076073) and the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20133223110003).

  20. Optimal design of an ultrasmall SOI-based 1 × 8 flat-top AWG by using an MMI.

    PubMed

    Li, Hongqiang; Bai, Yaoting; Dong, Xiaye; Li, Enbang; Li, Yang; Liu, Yu; Zhou, Wenqian

    2013-01-01

    Four methods based on a multimode interference (MMI) structure are optimally designed to flatten the spectral response of silicon-on-insulator- (SOI-) based arrayed-waveguide grating (AWG) applied in a demodulation integration microsystem. In the design for each method, SOI is selected as the material, the beam propagation method is used, and the performances (including the 3 dB passband width, the crosstalk, and the insertion loss) of the flat-top AWG are studied. Moreover, the output spectrum responses of AWGs with or without a flattened structure are compared. The results show that low insertion loss, crosstalk, and a flat and efficient spectral response are simultaneously achieved for each kind of structure. By comparing the four designs, the design that combines a tapered MMI with tapered input/output waveguides, which has not been previously reported, was shown to yield better results than others. The optimized design reduced crosstalk to approximately -21.9 dB and had an insertion loss of -4.36 dB and a 3 dB passband width, that is, approximately 65% of the channel spacing.

  1. A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

    NASA Astrophysics Data System (ADS)

    Mert Torunbalci, Mustafa; Emre Alper, Said; Akin, Tayfun

    2015-12-01

    This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au-Si eutectic bonding techniques. The dies sealed with anodic and Au-Si eutectic bonding provide a low vertical feedthrough resistance around 50 Ω. Glass-to-silicon anodically and Au-Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au-Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

  2. A novel BEM-LIGBT with high current density on thin SOI layer for 600 V HVIC

    NASA Astrophysics Data System (ADS)

    Zhu, Jing; Sun, Weifeng; Chen, Jian; Lu, Shengli; Zhang, Sen; Su, Wei

    2014-10-01

    A novel Body Effect Modulation Lateral Insulated Gate Bipolar Transistor (BEM-LIGBT) on the thin SOI layer featuring with a metal resistor connected with the body region and the n plus region without adding extra mask steps is experimentally proposed in this paper. In the proposed device structure, the electron current is the dominant component of the total current and it can be improved by increasing the resistance of the metal resistor, which is verified by the theoretical derivation and numerous TCAD simulations. The total current density of the proposed high voltage (above 690 V) BEM-LIGBT is increased by about 65% at VGE = 5 V, compared with the conventional structure on the same SOI layer. In addition, the BEM-LIGBT is successfully used in the level-shift circuit for 600 V high voltage gate drive integrated circuit (HVIC). The width of the dV/dt noise pulse in the circuit is decreased by about 45% by using the BEM-LIGBT.

  3. Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

    NASA Technical Reports Server (NTRS)

    Tu, Juliana; Smith, Rosemary L.

    1995-01-01

    The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

  4. Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    We report low-energy proton and alpha particle SEE data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) that demonstrates the criticality of understanding and using low-energy protons for SEE testing of highly-scaled technologies

  5. Model of Vernier devices in silicon-on-insulator technology

    NASA Astrophysics Data System (ADS)

    Fan, Guofang; Li, Yuan; Hu, Chunguang; Lei, Lihua; Zhao, Dong; Li, Hongyu; Luo, Yunhan; Zhen, Zhen

    2014-07-01

    In order to increase the number of channels that could be multiplexed or demultiplexed in the dense wavelength division multiplexed (DWDM) system based on the resonators on silicon-on-insulator (SOI) technology, the Vernier effect in the series-coupled racetrack resonators is presented to extend the free spectral range (FSR) of the DWDM systems. A method is developed based on a matrix approach to simulate Vernier devices. A three-dimensional full vectorial finite difference (FVFD) model, specifically suited for high index contrast and smaller size waveguides, for example, a waveguide in SOI technology, is developed to obtain the properties of a waveguide. Finally, the Vernier effect in the two series-coupled racetrack resonators is experimentally verified with an improved FSR and interstitial resonance suppression.

  6. Low-frequency noise in silicon-on-insulator devices and technologies

    NASA Astrophysics Data System (ADS)

    Simoen, E.; Mercha, A.; Claeys, C.; Lukyanchikova, N.

    2007-01-01

    An overview is given on the low-frequency (LF) noise of silicon-on-insulator (SOI) devices and technologies. In the first two parts, noise mechanisms specific for SOI are discussed, namely, the front-back-gate coupling in fully-depleted MOSFETs and the Lorentzian noise overshoot in floating-body operating transistors. In the next part, the impact of the technology (SOI substrate, gate stack processing, isolation module, …) on the LF noise is described. From this, it is derived that scaling below the 0.25 μm CMOS node did not result in the anticipated reduction of the 1/ f noise with tfox or tfox2. This is related to the increasing amount of nitrogen incorporated in the thin SiON front gate oxides with thickness tfox. In the case of high- κ dielectrics it is frequently observed that these have a higher trap density compared to SiO 2. On the other hand, today's multigate SOI transistors seem to give rise to similar gate oxide trap densities and hence, 1/ f noise, than their single-gate counterparts. In the last part, operational and circuit aspects will be discussed, which might have a beneficial impact on the LF noise performance.

  7. A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling

    NASA Astrophysics Data System (ADS)

    Rudenko, T.; Nazarov, A.; Kilchytska, V.; Flandre, D.

    2016-03-01

    The charge coupling between the front and back gates is a fundamental property of any fully-depleted silicon-on-insulator (SOI) MOSFET. It is traditionally described by the classical Lim and Fossum model (Lim and Fossum, 1983). However, in the case of lightly-doped ultra-thin-body (UTB) SOI MOSFETs with ultra-thin gate dielectrics, significant deviations from this model have been observed and analyzed over the years. In this paper, we present a thorough review of special features of gate coupling in such devices, combining a large set of results from one-dimensional numerical simulations in classical and quantum-mechanical modes, experimental data and analytical modeling. We show that UTB SOI MOSFETs with ultra-thin gate dielectrics feature stronger modulation of the threshold voltage at the conduction side with opposite gate bias and much wider range of gate voltages for interface coupling than predicted by the Lim and Fossum model. These differences originate from both electrostatic and quantization effects. A simple analytical model taking into account these effects is presented. The model enables an easy assessment of the quantization-induced threshold voltage increase in a long-channel SOI MOSFET versus opposite gate bias and the electric field in the silicon film associated with gate decoupling.

  8. Structural Make-up, Biopolymer Conformation, and Biodegradation Characteristics of Newly Developed Super Genotype of Oats (CDC SO-I vs. Conventional Varieties): Novel Approach

    SciTech Connect

    Damiran, D.; Yu, P

    2010-01-01

    Recently, a new 'super' genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE{sub L3x}, 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  9. Structural makeup, biopolymer conformation, and biodegradation characteristics of a newly developed super genotype of oats (CDC SO-I versus conventional varieties): a novel approach.

    PubMed

    Damiran, Daalkhaijav; Yu, Peiqiang

    2010-02-24

    Recently, a new "super" genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE(L3x), 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  10. Development FD-SOI MOSFET Amplifiers for Integrated Read-Out Circuit of Superconducting-Tunnel-Junction Single-Photon-Detectors

    SciTech Connect

    Kiuchi, Kenji; et al.

    2015-07-27

    We proposed a new high-resolution single-photon infrared spectrometer for search for radiative decay of cosmic neutrino background (Cν#23;B). The superconducting-tunnel-junctions(STJs) are used as a single-photon counting device. Each STJ consists of Nb/Al/AlxOy/Al/Nb layers, and their thicknesses are optimized for the operation temperature at 370 mK cooled by a 3He sorption refrigerator. Our STJs achieved the leak current 250 pA, and the measured data implies that a smaller area STJ fulfills our requirement. FD-SOI MOSFETs are employed to amplify the STJ signal current in order to increase signal-to-noise ratio (S/N). FD-SOI MOSFETs can be operated at cryogenic temperature of 370 mK, which reduces the noise of the signal amplification system. FD-SOI MOSFET characteristics are measured at cryogenic temperature. The Id-Vgs curve shows a sharper turn on with a higher threshold voltage and the Id-Vds curve shows a nonlinear shape in linear region at cryogenic temperature. Taking into account these effects, FD-SOI MOSFETs are available for read-out circuit of STJ detectors. The bias voltage for STJ detectors is 0.4 mV, and it must be well stabilized to deliver high performance. We proposed an FD-SOI MOSFET-based charge integrated amplifier design as a read-out circuit of STJ detectors. The requirements for an operational amplifier used in the amplifier is estimated using SPICE simulation. The op-amp is required to have a fast response (GBW ≥ #21;100 MHz), and it must have low power dissipation as compared to the cooling power of refrigerator.

  11. A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology.

    PubMed

    Sun, Kexu; Gao, Zheng; Gui, Ping; Wang, Rui; Oguzman, Ismail; Xu, Xiaochen; Vasanth, Karthik; Zhou, Qifa; Shung, K Kirk

    2015-02-01

    This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7-μm CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 Vpp, and a second-order harmonic distortion (HD2) of -56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle.

  12. A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology

    PubMed Central

    Sun, Kexu; Gao, Zheng; Gui, Ping; Wang, Rui; Oguzman, Ismail; Xu, Xiaochen; Vasanth, Karthik; Zhou, Qifa; Shung, K. Kirk

    2015-01-01

    This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7-μm CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 Vpp, and a second-order harmonic distortion (HD2) of −56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle. PMID:25914609

  13. Design of a switch matrix gate/bulk driver controller for thin film lithium microbatteries using microwave SOI technology

    NASA Technical Reports Server (NTRS)

    Whitacre, J.; West, W. C.; Mojarradi, M.; Sukumar, V.; Hess, H.; Li, H.; Buck, K.; Cox, D.; Alahmad, M.; Zghoul, F. N.; Jackson, J.; Terry, S.; Blalock, B.

    2003-01-01

    This paper presents a design approach to help attain any random grouping pattern between the microbatteries. In this case, the result is an ability to charge microbatteries in parallel and to discharge microbatteries in parallel or pairs of microbatteries in series.

  14. Two-way reflector based on two-dimensional sub-wavelength high-index contrast grating on SOI

    NASA Astrophysics Data System (ADS)

    Kaur, Harpinder; Kumar, Mukesh

    2016-05-01

    A two-dimensional (2D) high-index contrast grating (HCG) is proposed as a two-way reflector on Silicon-on-insulator (SOI). The proposed reflector provides high reflectivity over two (practically important) sets of angles of incidence- normal (θ = 0 °) and oblique/grazing (θ = 80 ° - 85 ° / 90 °). Analytical model of 2D HCG is presented using improved Fourier modal method. The vertical incidence is useful for application in VCSEL while oblique/grazing incidence can be utilized in high confinement (HCG mirrors based) hollow waveguides and Bragg reflectors. The proposed two-way reflector also exhibits a large reflection bandwidth (around telecom wavelength) which is an advantage for broadband photonic devices.

  15. A fast SOI-based variable optical attenuator with a p-i-n structure with low polarization dependent loss

    NASA Astrophysics Data System (ADS)

    Yuan, Pei; Wu, Yuan-da; Wang, Yue; An, Jun-ming; Hu, Xiong-wei

    2016-01-01

    According to the plasma dispersion effect of silicon (Si), a silicon-on-insulator (SOI) based variable optical attenuator (VOA) with p-i-n lateral diode structure is demonstrated in this paper. A wire rib waveguide with sub-micrometer cross section is adopted. The device is only about 2 mm long. The power consumption of the VOA is 76.3 mW (0.67 V, 113.9 mA), and due to the carrier absorption, the polarization dependent loss ( PDL) is 0.1 dB at 20 dB attenuation. The raise time of the VOA is 34.5 ns, the fall time is 37 ns, and the response time is 71.5 ns.

  16. Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K

    NASA Astrophysics Data System (ADS)

    Paz, Bruna Cardoso; Cassé, Mikaël; Barraud, Sylvain; Reimbold, Gilles; Vinet, Maud; Faynot, Olivier; Pavanello, Marcelo Antonio

    2017-02-01

    This work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.

  17. 16-channel arrayed waveguide grating (AWG) demultiplexer design on SOI wafer for application in CWDM-PON

    NASA Astrophysics Data System (ADS)

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-01-01

    Arrayed Waveguide Grating (AWG) functioning as a demultiplexer is designed on SOI platform with rib waveguide structure to be utilized in coarse wavelength division multiplexing-passive optical network (CWDM-PON) systems. Two design approaches; conventional and tapered configuration of AWG was developed with channel spacing of 20 nm that covers the standard transmission spectrum of CWDM ranging from 1311 nm to 1611 nm. The performance of insertion loss for tapered configuration offered the lowest insertion loss of 0.77 dB but the adjacent crosstalk gave non-significant relation for both designs. With average channel spacing of 20.4 nm, the nominal central wavelength of this design is close to the standard CWDM wavelength grid over 484 nm free spectrum range (FSR).

  18. Polarization rotator-splitters and controllers in a Si3N4-on-SOI integrated photonics platform.

    PubMed

    Sacher, Wesley D; Huang, Ying; Ding, Liang; Barwicz, Tymon; Mikkelsen, Jared C; Taylor, Benjamin J F; Lo, Guo-Qiang; Poon, Joyce K S

    2014-05-05

    We demonstrate novel polarization management devices in a custom-designed silicon nitride (Si(3)N(4)) on silicon-on-insulator (SOI) integrated photonics platform. In the platform, Si(3)N(4) waveguides are defined atop silicon waveguides. A broadband polarization rotator-splitter using a TM0-TE1 mode converter in a composite Si(3)N(4)-silicon waveguide is demonstrated. The polarization crosstalk, insertion loss, and polarization dependent loss are less than -19 dB, 1.5 dB, and 1.0 dB, respectively, over a bandwidth of 80 nm. A polarization controller composed of polarization rotator-splitters, multimode interference couplers, and thin film heaters is also demonstrated.

  19. Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics

    PubMed Central

    Henkel, C.; Abermann, S.; Bethge, O.; Pozzovivo, G.; Klang, P.; Stöger-Pollach, M.; Bertagnolli, E.

    2011-01-01

    Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 1011 eV−1 cm−2, a low subthreshold slope of 70-80 mV/decade, and an ION/IOFF current ratio greater than 2 × 106 are obtained. PMID:21461054

  20. Group-index independent coupling to band engineered SOI photonic crystal waveguide with large slow-down factor.

    PubMed

    Rahimi, Somayyeh; Hosseini, Amir; Xu, Xiaochuan; Subbaraman, Harish; Chen, Ray T

    2011-10-24

    Group-index independent coupling to a silicon-on-insulator (SOI) based band-engineered photonic crystal (PCW) waveguide is presented. A single hole size is used for designing both the PCW coupler and the band-engineered PCW to improve fabrication yield. Efficiency of several types of PCW couplers is numerically investigated. An on-chip integrated Fourier transform spectral interferometry device is used to experimentally determine the group-index while excluding the effect of the couplers. A low-loss, low-dispersion slow light transmission over 18 nm bandwidth under the silica light line with a group index of 26.5 is demonstrated, that corresponds to the largest slow-down factor of 0.31 ever demonstrated for a PCW with oxide bottom cladding.

  1. Comparison of the radiation hardness of various VLSI technologies for defense applications

    SciTech Connect

    Gibbon, C.F.

    1985-01-01

    In this review the radiation hardness of various potential very large scale (VLSI) IC technologies is evaluated. IC scaling produces several countervailing trends. Reducing vertical dimensions tends to increase total dose hardness, while reducing lateral feature sizes may increase susceptibility to transient radiation effects. It is concluded that during the next decade at least, silicon complimentary MOS (CMOS), perhaps on an insulating substrate (SOI) will be the technology of choice for VLSI in defense systems.

  2. Food security among individuals experiencing homelessness and mental illness in the At Home/Chez Soi Trial.

    PubMed

    O'Campo, Patricia; Hwang, Stephen W; Gozdzik, Agnes; Schuler, Andrée; Kaufman-Shriqui, Vered; Poremski, Daniel; Lazgare, Luis Ivan Palma; Distasio, Jino; Belbraouet, Slimane; Addorisio, Sindi

    2017-08-01

    Individuals experiencing homelessness are particularly vulnerable to food insecurity. The At Home/Chez Soi study provides a unique opportunity to first examine baseline levels of food security among homeless individuals with mental illness and second to evaluate the effect of a Housing First (HF) intervention on food security in this population. At Home/Chez Soi was a 2-year randomized controlled trial comparing the effectiveness of HF compared with usual care among homeless adults with mental illness, stratified by level of need for mental health services (high or moderate). Logistic regressions tested baseline associations between food security (US Food Security Survey Module), study site, sociodemographic variables, duration of homelessness, alcohol/substance use, physical health and service utilization. Negative binomial regression determined the impact of the HF intervention on achieving levels of high or marginal food security over an 18-month follow-up period (6 to 24 months). Community settings at five Canadian sites (Moncton, Montreal, Toronto, Winnipeg and Vancouver). Homeless adults with mental illness (n 2148). Approximately 41 % of our sample reported high or marginal food security at baseline, but this figure varied with gender, age, mental health issues and substance use problems. High need participants who received HF were more likely to achieve marginal or high food security than those receiving usual care, but only at the Toronto and Moncton sites. Our large multi-site study demonstrated low levels of food security among homeless experiencing mental illness. HF showed promise for improving food security among participants with high levels of need for mental health services, with notable site differences.

  3. Advanced microelectronics technologies for future small satellite systems

    NASA Astrophysics Data System (ADS)

    Alkalai, Leon

    2000-03-01

    Future small satellite systems for both Earth observation as well as deep-space exploration are greatly enabled by the technological advances in deep sub-micron microelectronics technologies. Whereas these technological advances are being fueled by the commercial (non-space) industries, more recently there has been an exciting new synergism evolving between the two otherwise disjoint markets. In other words, both the commercial and space industries are enabled by advances in low-power, highly integrated, miniaturized (low-volume), lightweight, and reliable real-time embedded systems. Recent announcements by commercial semiconductor manufacturers to introduce Silicon On Insulator (SOI) technology into their commercial product lines is driven by the need for high-performance low-power integrated devices. Moreover, SOI has been the technology of choice for many space semiconductor manufacturers where radiation requirements are critical. This technology has inherent radiation latch-up immunity built into the process, which makes it very attractive to space applications. In this paper, we describe the advanced microelectronics and avionics technologies under development by NASA's Deep Space Systems Technology Program (also known as X2000). These technologies are of significant benefit to both the commercial satellite as well as the deep-space and Earth orbiting science missions. Such a synergistic technology roadmap may truly enable quick turn-around, low-cost, and highly capable small satellite systems for both Earth observation as well as deep-space missions.

  4. Advanced Microelectronics Technologies for Future Small Satellite Systems

    NASA Technical Reports Server (NTRS)

    Alkalai, Leon

    1999-01-01

    Future small satellite systems for both Earth observation as well as deep-space exploration are greatly enabled by the technological advances in deep sub-micron microelectronics technologies. Whereas these technological advances are being fueled by the commercial (non-space) industries, more recently there has been an exciting new synergism evolving between the two otherwise disjointed markets. In other words, both the commercial and space industries are enabled by advances in low-power, highly integrated, miniaturized (low-volume), lightweight, and reliable real-time embedded systems. Recent announcements by commercial semiconductor manufacturers to introduce Silicon On Insulator (SOI) technology into their commercial product lines is driven by the need for high-performance low-power integrated devices. Moreover, SOI has been the technology of choice for many space semiconductor manufacturers where radiation requirements are critical. This technology has inherent radiation latch-up immunity built into the process, which makes it very attractive to space applications. In this paper, we describe the advanced microelectronics and avionics technologies under development by NASA's Deep Space Systems Technology Program (also known as X2000). These technologies are of significant benefit to both the commercial satellite as well as the deep-space and Earth orbiting science missions. Such a synergistic technology roadmap may truly enable quick turn-around, low-cost, and highly capable small satellite systems for both Earth observation as well as deep-space missions.

  5. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures

    NASA Astrophysics Data System (ADS)

    Oliveira, Alberto Vinicius de; Agopian, Paula Ghedini Der; Martino, Joao Antonio; Simoen, Eddy; Claeys, Cor; Collaert, Nadine; Thean, Aaron

    2016-09-01

    This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25 °C to 150 °C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.

  6. Compact Optical Add-Drop De-Multiplexers with Cascaded Micro-Ring Resonators on SOI

    NASA Astrophysics Data System (ADS)

    Guan, Huan; Li, Zhi-Yong; Shen, Hai-Hua; Yu, Yu-De

    2017-06-01

    Not Available Supported by the National High Technology Research and Development Program of China under Grant No 2015AA016904, the National Key Research and Development Plan of China under Grant No 2016YFB0402502, and the National Natural Science Foundation of China under Grant No 61275065.

  7. Engineered SOI slot waveguide ring resonator V-shape resonance combs for refraction index sensing up to 1300nm/RIU (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Zhang, Weiwei; Serna, Samuel; Le Roux, Xavier; Vivien, Laurent; Cassan, Eric

    2016-05-01

    Bio-detection based on CMOS technology boosts the miniaturization of detection systems and the success on highly efficient, robust, accurate, and low coast Lab-on-Chip detection schemes. Such on chip detection technologies have covered healthy related harmful gases, bio-chemical analytes, genetic micro RNA, etc. Their monitoring accuracy is mainly qualified in terms of sensitivity and limit of the detection (LOD) of the detection system. In this context, recently developed silicon on insulator (SOI) optical devices have displayed highly performant detection abilities that LOD could go beyond 10-8RIU and sensitivity could exceeds 103nm/RIU. The SOI integrated optical sensing devices include strip/slotted waveguide consisting in structures like Mach-Zehnder interferometers (MZI), ring resonators (RR), nano cavities, etc. Typically, hollow core RR and nano-cavities could exhibit higher sensitivity due to their optical mode confinement properties with a partial localization of the electric field in low index sensing regions than devices based on evanescent field tails outside of the optical cores. Furthermore, they also provide larger sensing areas for surface functionalization to reach higher sensitivities and lower LODs. The state of art of hollow core devices, either based on Bragg gratings formed from a slot waveguide cavity or photonic crystal slot cavities, show sensitivities (S) up to 400nm/RIU and Figure of Merit (FOM) around 3,000 in water environment, FOM being defined as the inverse of LOD and precisely as FOM=SQ/λ, with λ the resonance wavelength and Q the quality factor of the considered resonator. Such high achieved FOMs in nano cavities are mainly due to their large Q factors around 15,000. While for mostly used RR, which do not require particular design strategies, relatively low Q factors around 1800 in water are met and moderate sensitivities about 300nm/RIU are found. In this work, we present here a novel slot ring resonator design to make

  8. A National Partnership-Based Summer Learning Initiative to Engage Underrepresented Students with Science, Technology, Engineering and Mathematics

    NASA Technical Reports Server (NTRS)

    Melvin, Leland

    2010-01-01

    In response to the White House Educate to Innovate campaign, NASA developed a new science, technology, engineering, and mathematics (STEM) education program for non-traditional audiences that also focused on public-private partnerships and nationwide participation. NASA recognized that summer break is an often overlooked but opportune time to engage youth in STEM experiences, and elevated its ongoing commitment to the cultivation of diversity. The Summer of Innovation (SoI) is the resulting initiative that uses NASA's unique missions and resources to boost summer learning, particularly for students who are underrepresented, underserved and underperforming in STEM. The SoI pilot, launched in June 2010, is a multi-faceted effort designed to improve STEM teaching and learning through partnership, multi-week summer learning programs, special events, a national concluding event, and teacher development. The SoI pilot features strategic infusion of NASA content and educational resource materials, sustainability through STEM Learning Communities, and assessments of effectiveness of SoI interventions with other pilot efforts. This paper examines the inception and development of the Summer of Innovation pilot project, including achievements and effectiveness, as well as lessons learned for future efforts.

  9. Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

    NASA Astrophysics Data System (ADS)

    Kilchytska, V.; Bol, D.; De Vos, J.; Andrieu, F.; Flandre, D.

    2013-06-01

    This paper investigates both electrostatic control improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing top- and back-gate (substrate or ground plane) as Vbg = k · Vg) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. Improved performance (in terms of transconductance, drive current and early voltage) in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. QDG mode is demonstrated to allow threshold voltage tuning, subthreshold swing reduction and on-current enhancement without off-state current degradation, thus of interest for digital applications. The unique feature of QDG mode is finally exploited to boost the performances of the sleep transistor in the practical use case of a power-gated processor. About 30% reduction of the leakage in stand-by mode is achieved at nominal Vg with a Vbg of 3 V, which can be generated at marginal area/power overheads with an on-chip charge pump with an architecture proposed in this paper.

  10. Collaboration and involvement of persons with lived experience in planning Canada's At Home/Chez Soi project.

    PubMed

    Nelson, Geoffrey; Macnaughton, Eric; Curwood, Susan Eckerle; Egalité, Nathalie; Voronka, Jijian; Fleury, Marie-Josée; Kirst, Maritt; Flowers, Linsay; Patterson, Michelle; Dudley, Michael; Piat, Myra; Goering, Paula

    2016-03-01

    Planning the implementation of evidence-based mental health services entails commitment to both rigour and community relevance, which entails navigating the challenges of collaboration between professionals and community members in a planning environment which is neither 'top-down' nor 'bottom-up'. This research focused on collaboration among different stakeholders (e.g. researchers, service-providers, persons with lived experience [PWLE]) at five project sites across Canada in the planning of At Home/Chez Soi, a Housing First initiative for homeless people with mental health problems. The research addressed the question of what strategies worked well or less well in achieving successful collaboration, given the opportunities and challenges within this complex 'hybrid' planning environment. Using qualitative methods, 131 local stakeholders participated in key informant or focus group interviews between October 2009 and February 2010. Site researchers identified themes in the data, using the constant comparative method. Strategies that enhanced collaboration included the development of a common vision, values and purpose around the Housing First approach, developing a sense of belonging and commitment among stakeholders, bridging strategies employed by Site Co-ordinators and multiple strategies to engage PWLE. At the same time, a tight timeline, initial tensions, questions and resistance regarding project and research parameters, and lack of experience in engaging PWLE challenged collaboration. In a hybrid planning environment, clear communication and specific strategies are required that flow from an understanding that the process is neither fully participatory nor expert-driven, but rather a hybrid of both.

  11. New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

    NASA Astrophysics Data System (ADS)

    Li, Qi; Li, Hai-Ou; Tang, Ning; Zhai, Jiang-Hui; Song, Shu-Xiang

    2015-03-01

    A new SOI power device with multi-region high-concentration fixed charge (MHFC) is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer (BOX), by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS. Project supported by the State Key Laboratory of Electronic Thin Films and Integrated Devices of China (Grant No. KFJJ201205), the Department of Education Project of Guangxi Province, China (Grant No. 201202ZD041), the Postdoctoral Science Foundation Project of China (Grant Nos. 2012M521127 and 2013T60566), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

  12. High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier.

    PubMed

    Pan, Huapu; Assefa, Solomon; Green, William M J; Kuchta, Daniel M; Schow, Clint L; Rylyakov, Alexander V; Lee, Benjamin G; Baks, Christian W; Shank, Steven M; Vlasov, Yurii A

    2012-07-30

    The performance of a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector is characterized at data rates up to 40Gbps. Both chips were fabricated through the IBM Silicon CMOS Integrated Nanophotonics process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of -7.3dBm average optical power is demonstrated with 3.4pJ/bit power-efficiency and 0.6UI horizontal eye opening at a bit-error-rate of 10(-12). The receiver operates error-free (bit-error-rate < 10(-12)) up to 40Gbps with optimized power supply settings demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of -0.8dBm.

  13. DLTS and Dynamic Transconductance Analysis of Deep-Submicron Fully- Depleted SOI MOSFET’s

    DTIC Science & Technology

    1993-12-31

    performed before and after the stress. In most of the cases studied , provided that appropriate care was taken to correctly bias the device for the...OFFICER:Dr. Alvin M. Goodman IPROGRESS THIS PERIOD Progress this period was accomplished (a) in the study of temporal behavior of hot carrier induced...designs. Work was also initiated to carry out similar studies on technologies supplied by Honeywell (poc Dr Bill Jenkins, NRL). Some of the most

  14. Photonic Hilbert transformers based on laterally apodized integrated waveguide Bragg gratings on a SOI wafer.

    PubMed

    Bazargani, Hamed Pishvai; Burla, Maurizio; Chrostowski, Lukas; Azaña, José

    2016-11-01

    We experimentally demonstrate high-performance integer and fractional-order photonic Hilbert transformers based on laterally apodized Bragg gratings in a silicon-on-insulator technology platform. The sub-millimeter-long gratings have been fabricated using single-etch electron beam lithography, and the resulting HT devices offer operation bandwidths approaching the THz range, with time-bandwidth products between 10 and 20.

  15. Stencil mask technology for ion beam lithography

    NASA Astrophysics Data System (ADS)

    Ehrmann, Albrecht; Huber, Sabine; Kaesmaier, Rainer; Oelmann, Andreas B.; Struck, Thomas; Springer, Reinhard; Butschke, Joerg; Letzkus, Florian; Kragler, Karl; Loeschner, Hans; Rangelow, Ivo W.

    1998-12-01

    Ion beam lithography is one of the most promising future lithography technologies. A helium or hydrogen ion beam illuminates a stencil membrane mask and projects the image with 4X reduction to the wafer. The development of stencil masks is considered to be critical for the success of the new technology. Since 1997, within the European Ion Projection Lithography MEDEA (Microelectronic Devices for European Applications) project silicon stencil masks based on a wafer- flow process are developed. They are produced in a conventional wafer line. Six inch SOI (silicon-on-insulator) wafers are patterned with an e-beam wafer writing tool, then trenches are etched by plasma etching. Afterwards, the membrane is etched by wet etch using the SOI-oxide layer as an etch stop. The last step is to add a coating layer, which is sputtered onto the membrane. It protects the mask against ion irradiation damage. For metrology and inspection, methods used for conventional chromium masks as well as new techniques are investigated. Results from placement measurements on the Leica LMS IPRO tool will be presented. Finally, methods for CD measurement, defect inspection, repair and in-situ-cleaning in the stepper will be discussed, including experimental information of first tests.

  16. A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect

    NASA Astrophysics Data System (ADS)

    Ruichao, Tian; Xiaorong, Luo; Kun, Zhou; Qing, Xu; Jie, Wei; Bo, Zhang; Zhaoji, Li

    2015-03-01

    A novel silicon-on-insulator (SOI) super-junction (SJ) LDMOS with an ultra-strong charge accumulation effect is proposed. It has two key features: an assisted-accumulation trench-type extending gate (TEG) with a high-k (HK) dielectric and a step-doped N pillar (TEG-SD SJ LDMOS). In the on-state, electrons accumulate at the sidewall of the HK dielectric from the source to the drain by the TEG. Furthermore, the high permittivity of the HK dielectric leads to an ultra-strong charge accumulation effect. As a result, an ultra-low resistance current path is formed. The specific on-resistance (Ron, sp) is thus greatly reduced and is independent of the drift doping concentration. In the off-state, the step-doped N pillar effectively suppresses the substrate-assisted depletion effect by charge compensation. Moreover, the reshape effect of the HK dielectric and the new electric field (E-field) peak introduced by the step-doped N pillar enhance the drift region E-field. Hence, the BV is improved. Simulation indicates that the TEG-SD SJ LDMOS achieves an extremely low Ron, sp of 1.06 mΩ·cm2 and a BV of 217 V. Compared with the conventional SJ LDMOS, the TEG-SD SJ LDMOS decreases the Ron, sp by 77.5% and increases the BV by 33%, exhibiting a high figure of merits (FOM = BV2/Ron, sp) of 44 MW/cm2. Project supported by the National Natural Science Foundation of China (Nos. 61176069, 61376079) and the Program for New Century Excellent Talents in University of Ministry of Education of China (No. NCET-11-0062).

  17. SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs

    SciTech Connect

    Huque, Mohammad A; Tolbert, Leon M; Blalock, Benjamin; Islam, Syed K

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  18. Evaluation of GaAs low noise and power MMIC technologies to neutron, ionizing dose and dose rate effects

    SciTech Connect

    Derewonko, H.; Bosella, A.; Pataut, G.; Perie, D.; Pinsard, J.L.; Sentubery, C.; Verbeck, C.; Bressy, P.; Augier, P.

    1996-06-01

    An evaluation program of Thomson CSF-TCS GaAs low noise and power MMIC technologies to 1 MeV equivalent neutron fluence levels, up to 1 {times} 10{sup 15} n/cm{sup 2}, ionizing 1.17--1.33 MeV CO{sup 60} dose levels in excess of 200 Mrad(GaAs) and dose rate levels reaching 1.89 {times} 10{sup 11} rad(GaAs)/s is presented in terms of proper components and parameter choices, DC/RF electrical measurements and test methods under irradiation. Experimental results are explained together with drift analyses of electrical parameters that have determined threshold limits of component degradations. Modelling the effects of radiation on GaAs components relies on degradation analysis of active layer which appears to be the most sensitive factor. MMICs degradation under neutron fluence was simulated from irradiated FET data. Finally, based on sensitivity of technological parameters, rad-hard design including material, technology and MMIC design enhancement is discussed.

  19. Preliminary investigation of an SOI-based arrayed waveguide grating demodulation integration microsystem.

    PubMed

    Li, Hongqiang; Zhou, Wenqian; Liu, Yu; Dong, Xiaye; Zhang, Cheng; Miao, Changyun; Zhang, Meiling; Li, Enbang; Tang, Chunxiao

    2014-05-06

    An arrayed waveguide grating (AWG) demodulation integration microsystem is investigated in this study. The system consists of a C-band on-chip LED, a 2 × 2 silicon nanowire-based coupler, a fiber Bragg grating (FBG) array, a 1 × 8 AWG, and a photoelectric detector array. The coupler and AWG are made from silicon-on-insulator wafers using electron beam exposure and response-coupled plasma technology. Experimental results show that the excess loss in the MMI coupler with a footprint of 6 × 100 μm(2) is 0.5423 dB. The 1 × 8 AWG with a footprint of 267 × 381 μm(2) and a waveguide width of 0.4 μm exhibits a central channel loss of -3.18 dB, insertion loss non-uniformity of -1.34 dB, and crosstalk level of -23.1 dB. The entire system is preliminarily tested. Wavelength measurement precision is observed to reach 0.001 nm. The wavelength sensitivity of each FBG is between 0.04 and 0.06 nm/dB.

  20. Preliminary Investigation of an SOI-based Arrayed Waveguide Grating Demodulation Integration Microsystem

    NASA Astrophysics Data System (ADS)

    Li, Hongqiang; Zhou, Wenqian; Liu, Yu; Dong, Xiaye; Zhang, Cheng; Miao, Changyun; Zhang, Meiling; Li, Enbang; Tang, Chunxiao

    2014-05-01

    An arrayed waveguide grating (AWG) demodulation integration microsystem is investigated in this study. The system consists of a C-band on-chip LED, a 2 × 2 silicon nanowire-based coupler, a fiber Bragg grating (FBG) array, a 1 × 8 AWG, and a photoelectric detector array. The coupler and AWG are made from silicon-on-insulator wafers using electron beam exposure and response-coupled plasma technology. Experimental results show that the excess loss in the MMI coupler with a footprint of 6 × 100 μm2 is 0.5423 dB. The 1 × 8 AWG with a footprint of 267 × 381 μm2 and a waveguide width of 0.4 μm exhibits a central channel loss of -3.18 dB, insertion loss non-uniformity of -1.34 dB, and crosstalk level of -23.1 dB. The entire system is preliminarily tested. Wavelength measurement precision is observed to reach 0.001 nm. The wavelength sensitivity of each FBG is between 0.04 and 0.06 nm/dB.

  1. Anodic bonding using SOI wafer for fabrication of capacitive micromachined ultrasonic transducers

    NASA Astrophysics Data System (ADS)

    Bellaredj, M.; Bourbon, G.; Walter, V.; Le Moal, P.; Berthillier, M.

    2014-02-01

    In medical ultrasound imaging, mostly piezoelectric crystals are used as ultrasonic transducers. Capacitive micromachined ultrasonic transducers (CMUTs) introduced around 1994 have been shown to be a good alternative to conventional piezoelectric transducers in various aspects, such as sensitivity, transduction efficiency or bandwidth. This paper focuses on a fabrication process for CMUTs using anodic bonding of a silicon on insulator wafer on a glass wafer. The processing steps are described leading to a good control of the mechanical response of the membrane. This technology makes possible the fabrication of large membranes and can extend the frequency range of CMUTs to lower frequencies of operation. Silicon membranes having radii of 50, 70, 100 and 150 µm and a 1.5 µm thickness are fabricated and electromechanically characterized using an auto-balanced bridge impedance analyzer. Resonant frequencies from 0.6 to 2.3 MHz and an electromechanical coupling coefficient around 55% are reported. The effects of residual stress in the membranes and uncontrolled clamping conditions are clearly responsible for the discrepancies between experimental and theoretical values of the first resonance frequency. The residual stress in the membranes is determined to be between 90 and 110 MPa. The actual boundary conditions are between the clamped condition and the simply supported condition and can be modeled with a torsional stiffness of 2.10-7 Nm rad-1 in the numerical model.

  2. Preliminary Investigation of an SOI-based Arrayed Waveguide Grating Demodulation Integration Microsystem

    PubMed Central

    Li, Hongqiang; Zhou, Wenqian; Liu, Yu; Dong, Xiaye; Zhang, Cheng; Miao, Changyun; Zhang, Meiling; Li, Enbang; Tang, Chunxiao

    2014-01-01

    An arrayed waveguide grating (AWG) demodulation integration microsystem is investigated in this study. The system consists of a C-band on-chip LED, a 2 × 2 silicon nanowire-based coupler, a fiber Bragg grating (FBG) array, a 1 × 8 AWG, and a photoelectric detector array. The coupler and AWG are made from silicon-on-insulator wafers using electron beam exposure and response-coupled plasma technology. Experimental results show that the excess loss in the MMI coupler with a footprint of 6 × 100 μm2 is 0.5423 dB. The 1 × 8 AWG with a footprint of 267 × 381 μm2 and a waveguide width of 0.4 μm exhibits a central channel loss of −3.18 dB, insertion loss non-uniformity of −1.34 dB, and crosstalk level of −23.1 dB. The entire system is preliminarily tested. Wavelength measurement precision is observed to reach 0.001 nm. The wavelength sensitivity of each FBG is between 0.04 and 0.06 nm/dB. PMID:24797561

  3. Recent developments in terahertz sensing technology

    NASA Astrophysics Data System (ADS)

    Shur, Michael

    2016-05-01

    Terahertz technology has found numerous applications for the detection of biological and chemical hazardous agents, medical diagnostics, detection of explosives, providing security in buildings, airports, and other public spaces, shortrange covert communications (in the THz and sub-THz windows), and applications in radio astronomy and space research. The expansion of these applications will depend on the development of efficient electronic terahertz sources and sensitive low-noise terahertz detectors. Schottky diode frequency multipliers have emerged as a viable THz source technology reaching a few THz. High speed three terminal electronic devices (FETs and HBTs) have entered the THz range (with cutoff frequencies and maximum frequencies of operation above 1 THz). A new approach called plasma wave electronics recently demonstrated an efficient terahertz detection in GaAs-based and GaN-based HEMTs and in Si MOS, SOI, FINFETs and in FET arrays. This progress in THz electronic technology has promise for a significant expansion of THz applications.

  4. Characterization of a photonic strain sensor in silicon-on-insulator technology.

    PubMed

    Westerveld, Wouter J; Pozo, Jose; Harmsma, Peter J; Schmits, Ruud; Tabak, Erik; van den Dool, Teun C; Leinders, Suzanne M; van Dongen, Koen W A; Urbach, H Paul; Yousefi, Mirvais

    2012-02-15

    Recently there has been growing interest in sensing by means of optical microring resonators in photonic integrated circuits that are fabricated in silicon-on-insulator (SOI) technology. Taillaert et al. [Proc. SPIE 6619, 661914 (2007)] proposed the use of a silicon-waveguide-based ring resonator as a strain gauge. However, the strong lateral confinement of the light in SOI waveguides and its corresponding modal dispersion where not taken into account. We present a theoretical understanding, as well as experimental results, of strain applied on waveguide-based microresonators, and find that the following effects play important roles: elongation of the racetrack length, modal dispersion of the waveguide, and the strain-induced change in effective refractive index.

  5. Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Saramekala, Gopi Krishna; Dubey, Sarvesh; Tiwari, Pramod Kumar

    2014-12-01

    Ultrathin-body (UTB) SOI MOSFETs, which possess excellent short-channel effect immunity and high current on-off ratio, are expected to put back the conventional MOSFETs in high performance digital integrated circuits by the end of year 2014 to continue the current scaling trend. In this paper, targeting systems-on-a-chip (SOC) applications, a simulation based extensive study is carried out to evaluate the analog and RF performance of source/drain and gate engineered ultrathin body SOI MOSFETs, as both the digital and analog performance of the device must be excellent for SOC applications. The performance evaluation has been done in terms of device parameters like device capacitances (Cgs and Cgd), drain current (Id), transconductance (gm), transconductance generation efficiency (gm/Id), intrinsic gain (gm/gd), cut-off frequency (fT) and the maximum frequency of oscillation (fmax). The RF figures-of-merit (FoM) i.e., fT and fmax have been determined by using H and Y parameters obtained from high frequency simulation of the structure. The numerical simulation is performed using ATLASTM, a 2-D device simulator from SILVACO Inc.

  6. Effects of substrate voltage on noise characteristics and hole lifetime in SOI metal-oxide-semiconductor field-effect transistor photon detector.

    PubMed

    Putranto, Dedy Septono Catur; Priambodo, Purnomo Sidi; Hartanto, Djoko; Du, Wei; Satoh, Hiroaki; Ono, Atsushi; Inokawa, Hiroshi

    2014-09-08

    Low-frequency noise and hole lifetime in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are analyzed, considering their use in photon detection based on single-hole counting. The noise becomes minimum at around the transition point between front- and back-channel operations when the substrate voltage is varied, and increases largely on both negative and positive sides of the substrate voltage showing peculiar Lorentzian (generation-recombination) noise spectra. Hole lifetime is evaluated by the analysis of drain current histogram at different substrate voltages. It is found that the peaks in the histogram corresponding to the larger number of stored holes become higher as the substrate bias becomes larger. This can be attributed to the prolonged lifetime caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small absolute substrate bias is favorable for short lifetime and low noise, leading to high-speed operation.

  7. 1550-nm InGaAsP multi-quantum-well structures selectively grown on v-groove-patterned SOI substrates

    NASA Astrophysics Data System (ADS)

    Megalini, Ludovico; Bonef, Bastien; Cabinian, Brian C.; Zhao, Hongwei; Taylor, Aidan; Speck, James S.; Bowers, John E.; Klamkin, Jonathan

    2017-07-01

    We report direct growth of 1550-nm InGaAsP multi-quantum-well (MQW) structures in densely packed, smooth, highly crystalline, and millimeter-long InP nanoridges grown by metalorganic chemical vapor deposition on silicon-on-insulator (SOI) substrates. Aspect-ratio-trapping and selective area growth techniques were combined with a two-step growth process to obtain good material quality as revealed by photoluminescence, scanning electronic microscopy, and high-resolution X-ray diffraction characterization. Transmission electron microscopy images revealed sharp MQW/InP interfaces as well as thickness variation of the MQW layer. This was confirmed by atom probe tomography analysis, which also suggests homogenous incorporation of the various III-V elements of the MQW structure. This approach is suitable for the integration of InP-based nanoridges in the SOI platform for new classes of ultra-compact, low-power, nano-electronic, and photonic devices for future tele- and data-communications applications.

  8. Low frequency noise and radiation response in the partially depleted SOI MOSFETs with ion implanted buried oxide

    NASA Astrophysics Data System (ADS)

    Liu, Yuan; Chen, Hai-Bo; Liu, Yu-Rong; Wang, Xin; En, Yun-Fei; Li, Bin; Lu, Yu-Dong

    2015-08-01

    Low frequency noise behaviors of partially depleted silicon-on-insulator (PDSOI) n-channel metal-oxide semiconductors (MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from 44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/V·s to 363.65 cm2/V·s. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10-10 V2·Hz-1 and 2.7×10-8 V2·Hz-1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017 cm-3·eV-1 to 6.16×1018 cm-3·eV-1. Based on carrier mobility fluctuation theory, the extracted average Hooge’s parameter in these devices increases from 3.92×10-5 to 1.34×10-2 after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 M·rad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are -10.82 V and -31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed. Project supported by the National Natural Science Foundation of China (Grant Nos. 61204112 and 61204116).

  9. Mourir chez soi

    PubMed Central

    Kiyanda, Brigitte Gagnon; Dechêne, Geneviève; Marchand, Robert

    2015-01-01

    Résumé Objectif Démontrer que des infirmières dédiées en soins palliatifs d’un centre local de services communautaires (CLSC) urbain peuvent garder à domicile jusqu’au décès plus de 50 % de leurs patients en fin de vie et que le suivi médical à domicile est un facteur déterminant du décès à domicile. Type d’étude Analyse du lieu de décès des patients décédés en 2012 et 2013 suivis par les infirmières dédiées (N = 212), en fonction du suivi médical. Contexte Soins palliatifs du CLSC de Verdun, un territoire urbain situé dans le sud-ouest de Montréal. Participants Un total de 212 patients en fin de vie décédés en 2012 et 2013, suivis par 3 infirmières dédiées en soins palliatifs. Principaux paramètres à l’étude Le pourcentage de décès à domicile. Résultats Des 212 patients suivis à domicile par les infirmières en soins palliatifs, 56,6 % sont décédés à domicile, 62,6 % lorsque suivis par des médecins à domicile du CLSC, contre 5,0 % lorsque sans médecin à domicile. Conclusion Le développement des services médicaux à domicile au Québec, couplé à une simple restructuration des services de soins infirmiers des CLSC, permettrait à plus de 50 % des patients en fin de vie à domicile suivis par ces CLSC d’y demeurer jusqu’au décès, le souhait d’une majorité.

  10. Introducing porous silicon as a sacrificial material to obtain cavities in substrate of SOI wafers and a getter material for MEMS devices

    NASA Astrophysics Data System (ADS)

    Mohammad, Wajihuddin

    Microelectromechanical system (MEMS) resonators have been a subject of research for more than four decades. The reason is the huge potential they possess for frequency applications. The use of a MEMS resonator as the timing element has an experimental history and huge progress has been made in this direction. Vacuum encapsulated MEMS resonators are required for high precision frequency control. Hence, a device with a high quality factor and durability is needed. In this effort, a new process for producing a cavity in the substrate of Silicon on insulator (SOI) MEMS devices and augmenting it with a getter using porous silicon is developed. The process involves a mask-less, self-aligned cost effective electrochemical etching process. A 10 mum cavity is introduced in the substrate of SOI dies. This helps in increasing the packaging volume of the SOI resonators along with mitigating the viscous damping effects. The stiction problem in MEMS devices is effectively eliminated and millimeter long slender MEMS structures do not get stuck to the substrate. It also helps in reducing the parasitic capacitance between the device side and the substrate. The porous silicon getter is introduced as a getter material for vacuum encapsulated MEMS devices. This getter needs no external mask and is self-aligned. It requires no external heat or additional materials to operate. The highly reactive porous silicon can readily react with the oxygen gas and form an oxide layer that can trap other gas molecules. This helps in maintaining low pressures in the cavity of the bonded MEMS resonators. A tuning fork resonator with a resonant frequency of 245 kHz was used to realize the benefits of the cavity and the getter. It was observed that the unpackaged device with the cavity in the substrate showed two times better quality factor at different pressures, than the device with no cavity. In order to understand the benefits of porous silicon as a getter, the MEMS devices (one with only a cavity

  11. Determined Initial lead for South Of Isua (SOI) terrain suggests a single homogeneous source for it and possibly other archaean rocks

    NASA Astrophysics Data System (ADS)

    Tera, F.

    2011-12-01

    A Thorogenic-Uranogenic Lead Isotope Plane (TULIP), which entails plotting 206/208 (or its reverse) vs 207/208 (or its reverse), was applied to the Pb data on South of Isua (SOI) by Kamber et al., (1). When the data on 20 samples of these rocks and feldspars are plotted in pairs (each pair is a rock and its feldspar) on TULIP, they fall on 10 mixing lines that converge on a single spot (Fig. 1). This is the end member initial lead (EMIL). The 206/208 & 207/208 so determined are 0.3675 and 0.43525, respectively. From these values one calculates 207/206 = 1.1843 ± 0.0007, for EMIL. This pattern requires either: A) each pair has a singular kappa, K = 232Th/238U, different from others, or B) a pair's in situ decay Pb was homogenized in recent times. On 204/206 vs 207/206 diagram, the whole rocks of SOI define a 3.776 Ga isochron (2). From this and EMIL's 207/206, one obtains: 206/204 = 10.977, 207/204 = 12.974; and 208/204 = 29.756. This singularity of initial Pb contrasts with a deduced variability by the original authors (1). EMIL's radiogenic *(207/206) = 1.6220, gives a single-stage age = 5.9 Ga, indicating inapplicability of its evolution in one stage. Also, the μ calculated from 238U-206Pb for the single stage is different from that inferred from 235U-207Pb, confirming disqualification of this scenario. Reconciliation of the two decay schemes necessitates assumption of EMIL evolution in a minimum of two stages. Starting at 4.563 Ga, five scenarios were assumed: First stage ends and second starts at 4.55, 4.54, 4.53, 4.52 or 4.51 Ga. Second stages end at 3.776 Ga. The calculated μ1 for the first stage are 106, 59.5, 44.6, 36.3 and 30.9 respectively. For μ2 the change is limited, from 5.45 to 5.28. Only an average calculated K for both stages is possible. For the five outlined scenarios it ranges from 1.118 to 1.111. Earlier, Tera (3) observed that initial Pb of the oldest terrestrial reservoir requires evolution in two stages. There too μ1 >> μ2. Data on

  12. Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

    NASA Astrophysics Data System (ADS)

    Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

    2017-08-01

    Two-dimensional (2D) analytical models for the subthreshold current and subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

  13. Investigation of Coulomb scattering on sSi/Si0.5Ge0.5/sSOI quantum-well p-MOSFETs

    NASA Astrophysics Data System (ADS)

    Jiao, Wen; Qiang, Liu; Chang, Liu; Yize, Wang; Bo, Zhang; Zhongying, Xue; Zengfeng, Di; Wenjie, Yu; Qingtai, Zhao

    2016-09-01

    sSi/Si0.5Ge0.5/sSOI quantum-well (QW) p-MOSFETs with HfO2/TiN gate stack were fabricated and characterized. According to the low temperature experimental results, carrier mobility of the strained Si0.5Ge0.5 QW p-MOSFET was mainly governed by phonon scattering from 300 to 150 K and Coulomb scattering below 150 K, respectively. Coulomb scattering was intensified by the accumulated inversion charges in the Si cap layer of this Si/SiGe heterostructure, which led to a degradation of carrier mobility in the SiGe channel, especially at low temperature. Project supported by the National Natural Science Foundation of China (Nos. 61306126, 61306127, 61106015) and the CAS International Collaboration and Innovation Program on High Mobility Materials Engineering.

  14. Label-free antibody detection using band edge fringes in SOI planar photonic crystal waveguides in the slow-light regime.

    PubMed

    García-Rupérez, Jaime; Toccafondo, Veronica; Bañuls, María José; Castelló, Javier García; Griol, Amadeu; Peransi-Llopis, Sergio; Maquieira, Ángel

    2010-11-08

    We report experimental results of label-free anti-bovine serum albumin (anti-BSA) antibody detection using a SOI planar photonic crystal waveguide previously bio-functionalized with complementary BSA antigen probes. Sharp fringes appearing in the slow-light regime near the edge of the guided band are used to perform the sensing. We have modeled the presence of these band edge fringes and demonstrated the possibility of using them for sensing purposes by performing refractive index variations detection, achieving a sensitivity of 174.8 nm/RIU. Then, label-free anti-BSA biosensing experiments have been carried out, estimating a surface mass density detection limit below 2.1 pg/mm2 and a total mass detection limit below 0.2 fg.

  15. Rad-hard electronics study for SSC detectors

    SciTech Connect

    Ekenberg, T.; Dawson, J.; Stevens, A.; Haberichter, W.

    1991-01-01

    The radiation environment in a SSC detector operating at a luminosity of 10{sup 33} cm{sup {minus}2}s{sup {minus}1} will put stringent requirements on radiation hardness of the electronics. Over the expected 10 year life-time of a large detector, ionizing radiation doses of up to 20 MRad and neutron fluences of 10{sup 16} neutrons/cm{sup 2} are projected. At a luminosity of 10{sup 34} cm{sup {minus}2}s{sup {minus}1} even higher total doses are expected. the effect of this environment have been simulated by exposing CMOS/bulk and CMOS/SOS devices from monolithic processes to neutrons and ionizing radiation. leakage currents, noise variations, and DC characteristics have been measured before and after exposure in order to evaluate the effects of the irradiations. As expected the device characteristics remained virtually unchanged by neutron irradiation, while ionizing radiation caused moderate degradation of performance. 5 refs., 6 figs.

  16. Quantum Dots Based Rad-Hard Computing and Sensors

    NASA Technical Reports Server (NTRS)

    Fijany, A.; Klimeck, G.; Leon, R.; Qiu, Y.; Toomarian, N.

    2001-01-01

    Quantum Dots (QDs) are solid-state structures made of semiconductors or metals that confine a small number of electrons into a small space. The confinement of electrons is achieved by the placement of some insulating material(s) around a central, well-conducting region. Thus, they can be viewed as artificial atoms. They therefore represent the ultimate limit of the semiconductor device scaling. Additional information is contained in the original extended abstract.

  17. Quantum Dots Based Rad-Hard Computing and Sensors

    NASA Technical Reports Server (NTRS)

    Fijany, A.; Klimeck, G.; Leon, R.; Qiu, Y.; Toomarian, N.

    2001-01-01

    Quantum Dots (QDs) are solid-state structures made of semiconductors or metals that confine a small number of electrons into a small space. The confinement of electrons is achieved by the placement of some insulating material(s) around a central, well-conducting region. Thus, they can be viewed as artificial atoms. They therefore represent the ultimate limit of the semiconductor device scaling. Additional information is contained in the original extended abstract.

  18. Rad-hard computer elements for space applications

    NASA Technical Reports Server (NTRS)

    Krishnan, G. S.; Longerot, Carl D.; Treece, R. Keith

    1993-01-01

    Space Hardened CMOS computer elements emulating a commercial microcontroller and microprocessor family have been designed, fabricated, qualified, and delivered for a variety of space programs including NASA's multiple launch International Solar-Terrestrial Physics (ISTP) program, Mars Observer, and government and commercial communication satellites. Design techniques and radiation performance of the 1.25 micron feature size products are described.

  19. Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications Rad-Hard, Miniaturized

    NASA Technical Reports Server (NTRS)

    Adell, Philippe C.; Mojarradi, Mohammad; DelCastillo, Linda Y.; Vo, Tuan A.

    2011-01-01

    A paper discusses the successful development of a miniaturized radiation hardened high-voltage switching module operating at 2.5 kV suitable for space application. The high-voltage architecture was designed, fabricated, and tested using a commercial process that uses a unique combination of 0.25 micrometer CMOS (complementary metal oxide semiconductor) transistors and high-voltage lateral DMOS (diffusion metal oxide semiconductor) device with high breakdown voltage (greater than 650 V). The high-voltage requirements are achieved by stacking a number of DMOS devices within one module, while two modules can be placed in series to achieve higher voltages. Besides the high-voltage requirements, a second generation prototype is currently being developed to provide improved switching capabilities (rise time and fall time for full range of target voltages and currents), the ability to scale the output voltage to a desired value with good accuracy (few percent) up to 10 kV, to cover a wide range of high-voltage applications. In addition, to ensure miniaturization, long life, and high reliability, the assemblies will require intensive high-voltage electrostatic modeling (optimized E-field distribution throughout the module) to complete the proposed packaging approach and test the applicability of using advanced materials in a space-like environment (temperature and pressure) to help prevent potential arcing and corona due to high field regions. Finally, a single-event effect evaluation would have to be performed and single-event mitigation methods implemented at the design and system level or developed to ensure complete radiation hardness of the module.

  20. Single Event Upset Sensitivity of D-Flip Flop: Comparison of PDSOI With Bulk Si at 130 nm Technology Node

    NASA Astrophysics Data System (ADS)

    Zhang, Leqing; Xu, Jialing; Fan, Shuang; Dai, Lihua; Bi, Dawei; Lu, Jian; Hu, Zhiyuan; Zhang, Mengying; Zhang, Zhengxuan

    2017-01-01

    Single-event upsets are studied in digital storage cells in 130nm CMOS bulk Si and PDSOI technologies. The sensitivity of SEU to different technologies and hardening approaches is explored by using heavy-ion radiation experiments. Error numbers in D flip-flop chains are used to determine the impact of various cell designs and PDSOI hardening technique on upset sensitivity. Various flip-flops are designed and connected as shift-register chains, and the error numbers induced by irradiation are recorded to examine the effectiveness of the PDSOI technology. It was found that PDSOI technology has better performance in terms of upset robustness versus bulk Si at the 130nm technology node. The same design structure implemented in PDSOI technology has higher SEU threshold LET and much lower saturation cross section due to its full dielectric isolation structure which does not allow the charge generated in the substrate to be collected by the electrically active junctions in the thin top region of the device and reduces the sensitive volume of p-n junctions in the transistor. As shown in the experiment result, NRH_SOI (not radiation hardening SOI) saves about 25% area while having much lower SER versus DICE_Si, which means PDSOI still has obvious advantage at reducing SEU rate, even though its necessary body contact has to consume certain extra area.

  1. Direct measurement and analysis of total ionizing dose effect on 130 nm PD SOI SRAM cell static noise margin

    NASA Astrophysics Data System (ADS)

    Zheng, Qiwen; Cui, Jiangwei; Liu, Mengxin; Su, Dandan; Zhou, Hang; Ma, Teng; Yu, Xuefeng; Lu, Wu; Guo, Qi; Zhao, Fazhan

    2017-08-01

    Not Available Project supported by the National Natural Science Foundation of China (Grant Nos. U1532261 and 11605282) and the Opening Fund of Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences Research Projects (Grant No. KLSDTJJ2016-07)

  2. Influence of the Rashba SOI and LO phonon effects on the interaction energy of the Fröhlich bipolaron in a quantum dot

    NASA Astrophysics Data System (ADS)

    Zhang, Ying; Han, Chao; Eerdunchaolu; Sudu

    2016-10-01

    The influence of the Rashba spin-orbit interaction (SOI) and longitudinal optical (LO) phonon effect on the ground-state properties of the Fröhlich bipolaron in a quantum dot are studied using the Tokuda-modified linear-combination operator method based on the Lee-Low-Pines unitary transformation. The results indicate that, under the condition of strong electron-phonon coupling (coupling strength a > 6), E int < 0, the electron-phonon coupling body in quantum dot is mainly the bipolaron which is in a stably bound state. The bipolaron interaction energy E int increases with increasing confinement strength of the quantum dot ω0, electron-phonon coupling strength α, and polaron velocity u and decreases with increasing Coulomb confinement potential ß and Rashba spinobit coupling strength αR. In the bipolaron interaction energy E int, the electron-phonon coupling energy E e-ph plays the leading role, followed by the confinement potential energy of the quantum dot E coul and the Coulomb interaction energy between two electrons E couf. Though the additional energy E R-ph caused by the phonon effect accounts for a smaller percentage than the previous three, the electron-phonon coupling and the Rashba spin-obit coupling influence and infiltrate each other. Therefore, the influences of the bipolaron effect and the Rashba electron-spin interaction cannot be ignored when studying a quantum dot.

  3. What Happens After the Demonstration Phase? The Sustainability of Canada's At Home/Chez Soi Housing First Programs for Homeless Persons with Mental Illness.

    PubMed

    Nelson, Geoffrey; Caplan, Rachel; MacLeod, Timothy; Macnaughton, Eric; Cherner, Rebecca; Aubry, Tim; Méthot, Christian; Latimer, Eric; Piat, Myra; Plenert, Erin; McCullough, Scott; Zell, Sarah; Patterson, Michelle; Stergiopoulos, Vicky; Goering, Paula

    2017-03-01

    This research examined the sustainability of Canada's At Home/Chez Soi Housing First (HF) programs for homeless persons with mental illness 2 years after the end of the demonstration phase of a large (more than 2000 participants enrolled), five-site, randomized controlled trial. Qualitative interviews were conducted with 142 participants (key informants, HF staff, and persons with lived experience) to understand sustainability outcomes and factors that influenced those outcomes. Also, a self-report HF fidelity measure was completed for nine HF programs that continued after the demonstration project. A cross-site analysis was performed, using the five sites as case studies. The findings revealed that nine of the 12 HF programs (75%) were sustained, and that seven of the nine programs reported a high level of fidelity (achieving an overall score of 3.5 or higher on a 4-point scale). The sites varied in terms of the level of systems integration and expansion of HF that were achieved. Factors that promoted or impeded sustainability were observed at multiple ecological levels: broad contextual (i.e., dissemination of research evidence, the policy context), community (i.e., partnerships, the presence of HF champions), organizational (i.e., leadership, ongoing training, and technical assistance), and individual (i.e., staff turnover, changes, and capacity). The findings are discussed in terms of the implementation science literature and their implications for how evidence-based programs like HF can be sustained.

  4. Photodetectors for 1.3-μm and 1.55-μm wavelengths using SiGe undulating MQWs on SOI substrates

    NASA Astrophysics Data System (ADS)

    Xu, Dan-Xia; Janz, Siegfried; Lafontaine, Hugues; Pearson, Matthew R.

    1999-03-01

    For Si-based photonic integrated circuits (PICs), photodiodes with good responsivity at 1.3 micrometer and 1.55 micrometer wavelengths made of Si-based materials are highly desirable. Previously, work has been reported using epitaxial SiGe planar multiple quantum wells (MQWs) on Si substrates. Since the high lattice mismatch limits the maximum Ge concentration and SiGe layer thickness, responsivity at 1.55 micrometer was limited. Under appropriate growth conditions, strained SiGe QW's grow with periodic thickness variations along the surface plane. Ge tends to migrate towards the thickness maxima. This increase in local Ge concentration and the reduced quantum confinement at the coherent wave crest produces strained QW's with significantly lower band-gaps compared to planar QW's with the same nominal composition. In this paper, we report the first MSM SiGe waveguide photodetectors fabricated using coherent wave growth mode with a band gap below 800 meV. The heterostructures were grown on a SOI substrate by an ultra- high vacuum chemical vapor deposition (UHVCVD) system. The 2 micrometer thick Si/SiGe/Si on oxide structure provides waveguiding for the detector structures and permits effective fiber coupling. Preliminary measurements have demonstrated internal responsivities of approximately 1 A/W at 1.3 micrometer wavelength and 0.1 A/W at 1.55 micrometer wavelength for a 240 micrometer long device.

  5. Housing First for People With Severe Mental Illness Who Are Homeless: A Review of the Research and Findings From the At Home–Chez soi Demonstration Project

    PubMed Central

    Aubry, Tim; Nelson, Geoffrey; Tsemberis, Sam

    2015-01-01

    Objective: To provide a review of the extant research literature on Housing First (HF) for people with severe mental illness (SMI) who are homeless and to describe the findings of the recently completed At Home (AH)–Chez soi (CS) demonstration project. HF represents a paradigm shift in the delivery of community mental health services, whereby people with SMI who are homeless are supported through assertive community treatment or intensive case management to move into regular housing. Method: The AH–CS demonstration project entailed a randomized controlled trial conducted in 5 Canadian cities between 2009 and 2013. Mixed methods were used to examine the implementation of HF programs and participant outcomes, comparing 1158 people receiving HF to 990 people receiving standard care. Results: Initial research conducted in the United States shows HF to be a promising approach, yielding superior outcomes in helping people to rapidly exit homelessness and establish stable housing. Findings from the AH–CS demonstration project reveal that HF can be successfully adapted to different contexts and for different populations without losing its fidelity. People receiving HF achieved superior housing outcomes and showed more rapid improvements in community functioning and quality of life than those receiving treatment as usual. Conclusions: Knowledge translation efforts have been undertaken to disseminate the positive findings and lessons learned from the AH–CS project and to scale up the HF approach across Canada. PMID:26720504

  6. A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) UTB SOI MOSFETs including substrate induced surface potential effects

    NASA Astrophysics Data System (ADS)

    Kumar, Ajit; Tiwari, Pramod Kumar

    2014-05-01

    In this paper, a threshold voltage model of short-channel recessed-source/drain (Re-S/D) ultra-thin body (UTB) SOI MOSFETs has been presented considering the substrate induced surface potential (SISP) to improve the model accuracy over wide ranges of device parameters and substrate bias. The potential distribution of the front and the back surfaces of the Si-body have been derived using the evanescent mode analysis method in which the channel potential is broken into one-dimensional long-channel potential and two-dimensional short-channel potential. A one-dimensional Poisson's equation has also been solved in the substrate region to account the effect of substrate induced surface potential (SISP) at substrate/buried-oxide interface. The minimum front- and back-surface potentials of silicon body have been used to obtain front and back channel threshold voltages, respectively. However, the smaller one between front and back channel threshold voltages is considered to be the threshold voltage of the device. The accuracy of the present model has been extended up to 10 nm channel length by incorporating the quantum effects induced correction term. The model results are verified with simulation results obtained using ATLAS™ from Silvaco.

  7. CMOS device and interconnect technology enhancements for low power/low voltage applications

    NASA Astrophysics Data System (ADS)

    Vasudev, P. K.

    1996-04-01

    This paper reviews current advances and future directions in the development of scaled CMOS device technologies on bulk and SOI substrates, and multilevel interconnect architectures for application to low power/low voltage ULSI. Although traditional device scaling (as per the SIA roadmap) calls for the concomitant reduction in device sizes and power supplies driven by DRAM technology generations, the achievement of ultra-low power dissipation (at Vdd ≈ 1 V or less) and high speed performance (for battery operated portable systems) will accelerate scaling and drive several new engineered structures, such as vertically modulated channel doping profiles, ultra-shallow source/drain junctions and ultra-thin SOI devices that are tailored for low voltages. In addition, the development of novel low temperature processing schemes, such as Damascene, will be accelerated for integrating low K dielectrics with Al or Cu metallizations for multilevel interconnect architectures that are designed for low power. The successful incorporation of these technologies into portable electronics systems of the coming decade will require meeting the timing, manufacturability, cost and performance goals, in concert with the SIA roadmap.

  8. Mechanisms for optical loss in SOI waveguides for mid-infrared wavelengths around 2 μm

    NASA Astrophysics Data System (ADS)

    Hagan, David E.; Knights, Andrew P.

    2017-02-01

    We report the measurement of optical loss in submicron silicon-on-insulator waveguides at a wavelength of 2.02 μm for the fundamental TE mode. Devices were fabricated at IMEC and at A⋆STAR's Institute of Microelectronics (IME) and thus these measurements are applicable to studies which require fabrication using standard foundry technology. Propagation loss for strip and rib waveguides of 3.3 ± 0.5 and 1.9 ± 0.2 dB cm-1 were measured. Waveguide bending loss in strip and rib waveguides was measured to be 0.36 and 0.68 dB per 90° bend for a radius of 3 μm. Doped waveguide loss in rib waveguides was measured for both n-type and p-type species at two doping densities for each doping type. Measured results from propagation, bending, and free-carrier loss were found to be in good agreement with analytical or numerical models. Loss due to lattice defects introduced by ion-implantation is found to be underestimated by a previously proposed empirical model. The thermal annealing of the lattice defects is consistent with removal of the silicon divacancy.

  9. Wafer topography modeling for ionic implantation mask correction dedicated to 2x nm FDSOI technologies

    NASA Astrophysics Data System (ADS)

    Michel, Jean-Christophe; Le Denmat, Jean-Christophe; Sungauer, Elodie; Robert, Frédéric; Yesilada, Emek; Armeanu, Ana-Maria; Entradas, Jorge; Sturtevant, John L.; Do, Thuy; Granik, Yuri

    2013-04-01

    Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist [1]. This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning [2] [3]. For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.

  10. Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

    NASA Astrophysics Data System (ADS)

    Tu, Hongen

    This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high

  11. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  12. The role of advocacy coalitions in a project implementation process: the example of the planning phase of the At Home/Chez Soi project dealing with homelessness in Montreal.

    PubMed

    Fleury, Marie-Josée; Grenier, Guy; Vallée, Catherine; Hurtubise, Roch; Lévesque, Paul-André

    2014-08-01

    This study analyzed the planning process (summer 2008 to fall 2009) of a Montreal project that offers housing and community follow-up to homeless people with mental disorders, with or without substance abuse disorders. With the help of the Advocacy Coalition Framework (ACF), advocacy groups that were able to navigate a complex intervention implementation process were identified. In all, 25 people involved in the Montreal At Home/Chez Soi project were surveyed through interviews (n=18) and a discussion group (n=7). Participant observations and documentation (minutes and correspondence) were also used for the analysis. The start-up phase of the At Home/Chez may be broken down into three separate periods qualified respectively as "honeymoon;" "clash of cultures;" and "acceptance & commitment". In each of the planning phases of the At Home/Chez Soi project in Montreal, at least two advocacy coalitions were in confrontation about their specific belief systems concerning solutions to address the recurring homelessness social problem, while a third, more moderate one contributed in rallying most key actors under specified secondary aspects. The study confirms the importance of policy brokers in achieving compromises acceptable to all advocacy coalitions. Copyright © 2014 Elsevier Ltd. All rights reserved.

  13. Technology Development.

    ERIC Educational Resources Information Center

    Gomory, Ralph E.

    1983-01-01

    The evolutionary character and complexity of technological development is discussed, focusing on the steam engine and computer as examples. Additional topics include characteristics of science/technology, cultural factors in technological development, technology transfer, and problems in technological organization. (JN)

  14. Technology Development.

    ERIC Educational Resources Information Center

    Gomory, Ralph E.

    1983-01-01

    The evolutionary character and complexity of technological development is discussed, focusing on the steam engine and computer as examples. Additional topics include characteristics of science/technology, cultural factors in technological development, technology transfer, and problems in technological organization. (JN)

  15. Advanced TEM Characterization for the Development of 28-14nm nodes based on fully-depleted Silicon-on-Insulator Technology

    NASA Astrophysics Data System (ADS)

    Servanton, G.; Clement, L.; Lepinay, K.; Lorut, F.; Pantel, R.; Pofelski, A.; Bicais, N.

    2013-11-01

    The growing demand for wireless multimedia applications (smartphones, tablets, digital cameras) requires the development of devices combining both high speed performances and low power consumption. A recent technological breakthrough making a good compromise between these two antagonist conditions has been proposed: the 28-14nm CMOS transistor generations based on a fully-depleted Silicon-on-Insulator (FD-SOI) performed on a thin Si film of 5-6nm. In this paper, we propose to review the TEM characterization challenges that are essential for the development of extremely power-efficient System on Chip (SoC).

  16. Laser Technology.

    ERIC Educational Resources Information Center

    Gauger, Robert

    1993-01-01

    Describes lasers and indicates that learning about laser technology and creating laser technology activities are among the teacher enhancement processes needed to strengthen technology education. (JOW)

  17. Laser Technology.

    ERIC Educational Resources Information Center

    Gauger, Robert

    1993-01-01

    Describes lasers and indicates that learning about laser technology and creating laser technology activities are among the teacher enhancement processes needed to strengthen technology education. (JOW)

  18. The Impact of a 24 Month Housing First Intervention on Participants’ Body Mass Index and Waist Circumference: Results from the At Home / Chez Soi Toronto Site Randomized Controlled Trial

    PubMed Central

    Woodhall-Melnik, Julia; Misir, Vachan; Kaufman-Shriqui, Vered; O’Campo, Patricia; Stergiopoulos, Vicky; Hwang, Stephen

    2015-01-01

    Research suggests that individuals experiencing homelessness have high rates of overweight and obesity. Unhealthy weights and homelessness are both associated with increased risk of poor health and mortality. Using longitudinal data from 575 participants at the Toronto site of the At Home/Chez Soi randomized controlled trial, we investigate the impact of receiving a Housing First intervention on the Body Mass Index (BMI) and waist circumference of participants with moderate and high needs for mental health support services. The ANCOVA results indicate that the intervention resulted in no significant change in BMI or waist circumference from baseline to 24 months. The findings suggest a need for a better understanding of factors contributing to overweight, obesity, and high waist circumference in populations who have histories of housing precarity and experience low-income in tandem with other concerns such as mental illness and addictions. Trial Registration International Standard Randomized Control Trial Number Register ISRCTN42520374 PMID:26418677

  19. Si photonics technology for future optical interconnection

    NASA Astrophysics Data System (ADS)

    Zheng, Xuezhe; Krishnamoorthy, Ashok V.

    2011-12-01

    Scaling of computing systems require ultra-efficient interconnects with large bandwidth density. Silicon photonics offers a disruptive solution with advantages in reach, energy efficiency and bandwidth density. We review our progress in developing building blocks for ultra-efficient WDM silicon photonic links. Employing microsolder based hybrid integration with low parasitics and high density, we optimize photonic devices on SOI platforms and VLSI circuits on more advanced bulk CMOS technology nodes independently. Progressively, we successfully demonstrated single channel hybrid silicon photonic transceivers at 5 Gbps and 10 Gbps, and 80 Gbps arrayed WDM silicon photonic transceiver using reverse biased depletion ring modulators and Ge waveguide photo detectors. Record-high energy efficiency of less than 100fJ/bit and 385 fJ/bit were achieved for the hybrid integrated transmitter and receiver, respectively. Waveguide grating based optical proximity couplers were developed with low loss and large optical bandwidth to enable multi-layer intra/inter-chip optical interconnects. Thermal engineering of WDM devices by selective substrate removal, together with WDM link using synthetic wavelength comb, we significantly improved the device tuning efficiency and reduced the tuning range. Using these innovative techniques, two orders of magnitude tuning power reduction was achieved. And tuning cost of only a few 10s of fJ/bit is expected for high data rate WDM silicon photonic links.

  20. Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    We report low-energy proton and low-energy alpha particle single-event effects (SEE) data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latches and static random access memory (SRAM) that demonstrates the criticality of using low-energy protons for SEE testing of highly-scaled technologies. Low-energy protons produced a significantly higher fraction of multi-bit upsets relative to single-bit upsets when compared to similar alpha particle data. This difference highlights the importance of performing hardness assurance testing with protons that include energy distribution components below 2 megaelectron-volt. The importance of low-energy protons to system-level single-event performance is based on the technology under investigation as well as the target radiation environment.

  1. CHP Technologies

    EPA Pesticide Factsheets

    Learn about CHP technologies, including reciprocating engines, combustion turbines, steam turbines, microturbines, fuel cells, and waste heat to power. Access the Catalog of CHP Technologies and the Biomass CHP Catalog of Technologies.

  2. Dimension Technologies

    NASA Image and Video Library

    Command and Control Technologies (CCT) Corporation of Titusville, Florida, a Florida/NASA Business Incubator tenant, is commercializing technology based on Kennedy Space Center's (KSC's) spacecraft...

  3. Polysomnographic Technology

    MedlinePlus

    ... Description and Certification Information / Polysomnographic Technology Polysomnographic Technology Occupational Description Polysomnographic technologists perform sleep tests and work with physicians to provide information needed ...

  4. Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

    NASA Astrophysics Data System (ADS)

    Pengcheng, Huang; Shuming, Chen; Jianjun, Chen

    2016-03-01

    In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D-TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout. Project supported by the National Natural Science Foundation of China (Grant Nos. 61376109, 61434007, and 61176030) and the Advanced Research Project of National University of Defense Technology, China (Grant No. 0100066314001).

  5. Guerilla Technology.

    ERIC Educational Resources Information Center

    Van Horn, Royal

    1999-01-01

    Staff at disadvantaged schools lacking sufficient technology must take matters into their own hands. Guerilla technology tactics include finding all the hidden technology on campus, scanning the school budget carefully, helping others spend their technology money, and scrounging free computers at universities and local businesses. (MLH)

  6. Being technological

    NASA Astrophysics Data System (ADS)

    Denning, Kathryn

    2011-02-01

    SETI's essential premises involve evolution in multiple domains: cosmology, biology, culture and technology. Comparatively little has been written about the last of these, technology, in relation to SETI's targets, but it is a crucial variable and well worth deep examination. In particular, it would seem prudent to consider carefully our assumptions about hypothetical extraterrestrial societies which have developed technology that SETI could detect, or which could detect, at interstellar distances, the existence of intelligent life on Earth. This paper contributes to that effort by reflecting upon our habits of projecting terracentric assumptions onto hypothetical worlds, exploring dominant narratives about technological development and presenting varied philosophical theories about the nature of technology. It highlights the cultural aspects of technology here on Earth, particularly their role in the development of radio technology. In the end, it is clear that technology need not develop along a prescribed, linear path; projections about extraterrestrial societies which rely on this assumption need to be reconsidered.

  7. Casting Technology.

    ERIC Educational Resources Information Center

    Wright, Michael D.; And Others

    1992-01-01

    Three articles discuss (1) casting technology as it relates to industry, with comparisons of shell casting, shell molding, and die casting; (2) evaporative pattern casting for metals; and (3) high technological casting with silicone rubber. (JOW)

  8. Optimization of computer-based technology of creating large reservoir's Digital Elevation Models

    NASA Astrophysics Data System (ADS)

    Shikunova, Ekaterina; Pavlovsky, Andrew; Zemlyanov, Igor; Gorelits, Olga

    2010-05-01

    Using Digital Elevation Model of bottom and coastal zone for large-scale anthropogenic water reservoirs is very important for sustainable water management in actual conditions of Global Climate Change. DEM is unified monitoring base for different types of reservoirs in varied types of ecosystems in various environmental and economical conditions. It may be used for getting current morphometric characteristics, pollution and biodiversity analysis, monitoring bottom relief changing and making management decisions. In 2008-2009 State Oceanography Institute (SOI) carried out the DEMs for reservoirs of Volga river system. In 2008 in SOI was created DEM of Uglichsky reservoir, which is typical Russian reservoir. Methodology and computer-based technology were developed and evaluated. In 2009 in SOI were created DEMs of Gorkovsky, Volgogradsky and six reservoirs of Moscow region. Such result was achieved by optimization of DEM's creating process. Initially we used complex of GIS programs, which include GIS Map-2008 Panorama, ArcMap v.9.3.1, ArcView v.3.2a, Golden Surfer v.8, Global Mapper v.10. The input data are bathymetric survey data, large-scale maps (scale 1:10 000, 1:25 000) and remote sensing data of high resolution. Office analysis consists of several main milestones. 1. Vectorization of coastline and relief data from maps and remote sensing data using GIS Map-2008 by Panorama; ArcView v.3.2a. 2. Maps data elaboration with using bathymetric survey data. Because some maps are longstanding it is necessary to renew them. 3. Creating point's array including all data from maps, RSD and bathymetric survey. 4. Separation small calculation zones including four survey cross-sections. 5. Determine of anisotropy parameters, which depend on channel orientation. 6. Create shapes for clipping of correct grid zones. Each shape includes 2 cross-sections. Milestones 2-6 realize in ArcView v.3.2a. 7. Creating grid's array using Golden Surfer v.8 for each zone by interpolation method

  9. Contemporary Technology.

    ERIC Educational Resources Information Center

    Clark, Gilbert, Ed.

    1999-01-01

    This theme issue of "InSEA News" focuses on contemporary technology and art education. The articles are: "International Travel and Contemporary Technology" (Gilbert Clark); "Recollections and Visions for Electronic Computing in Art Education" (Guy Hubbard); "Using Technologies in Art Education: A Review of…

  10. Assistive Technologies

    ERIC Educational Resources Information Center

    Auat Cheein, Fernando A., Ed.

    2012-01-01

    This book offers the reader new achievements within the Assistive Technology field made by worldwide experts, covering aspects such as assistive technology focused on teaching and education, mobility, communication and social interactivity, among others. Each chapter included in this book covers one particular aspect of Assistive Technology that…

  11. Technology Night.

    ERIC Educational Resources Information Center

    DuPont, Albert P.

    1998-01-01

    A Maryland elementary school enlightened parents and community members about school technology by hosting a technology night showcasing student work. Through staff and community members' cooperative efforts, the technology committee created a comprehensive program composed of several elements: student involvement, district vision,…

  12. Assistive Technologies

    ERIC Educational Resources Information Center

    Auat Cheein, Fernando A., Ed.

    2012-01-01

    This book offers the reader new achievements within the Assistive Technology field made by worldwide experts, covering aspects such as assistive technology focused on teaching and education, mobility, communication and social interactivity, among others. Each chapter included in this book covers one particular aspect of Assistive Technology that…

  13. Technology transfer

    NASA Technical Reports Server (NTRS)

    Penaranda, Frank E.

    1992-01-01

    The topics are presented in viewgraph form and include the following: international comparison of R&D expenditures in 1989; NASA Technology Transfer Program; NASA Technology Utilization Program thrusts for FY 1992 and FY 1993; National Technology Transfer Network; and NTTC roles.

  14. Single crystalline silicon-based surface micromachining for high-precision inertial sensors: technology and design for reliability

    NASA Astrophysics Data System (ADS)

    Knechtel, Roy

    2009-05-01

    In this paper, a foundry process for surface micromachined inertial sensors such as accelerometers or gyroscopes is introduced, with special attention on reliability aspects. Reliability was a major focus during the development phase, leading to the choice of the single crystalline silicon layer of an SOI device wafer as the mechanically active material. Glass frit wafer bonding is used for capping and hermetic sealing, but in addition to these fundamental reliability aspects, many influences on reliability must be considered, such as the risk of sticking, local stress concentration, electrical effects or the defined limitations of the mechanical movement in the interaction of design and technology. Reliability test results, as well as measures for improving the reliability and performance, are discussed in this paper.

  15. Technology Lecturer Turned Technology Teacher

    ERIC Educational Resources Information Center

    Lee, Kerry

    2009-01-01

    This case study outlines a program developed by a group of 6 teachers' college lecturers who volunteered to provide a technology program to year 7 & 8 children (11- and 12-year-olds) for a year. This involved teaching technology once a week. As technology education was a new curriculum area when first introduced to the college, few lecturers…

  16. Appropriate Technology as Indian Technology.

    ERIC Educational Resources Information Center

    Barry, Tom

    1979-01-01

    Describes the mounting enthusiasm of Indian communities for appropriate technology as an inexpensive means of providing much needed energy and job opportunities. Describes the development of several appropriate technology projects, and the goals and activities of groups involved in utilizing low scale solar technology for economic development on…

  17. Technology '90

    SciTech Connect

    Not Available

    1991-01-01

    The US Department of Energy (DOE) laboratories have a long history of excellence in performing research and development in a number of areas, including the basic sciences, applied-energy technology, and weapons-related technology. Although technology transfer has always been an element of DOE and laboratory activities, it has received increasing emphasis in recent years as US industrial competitiveness has eroded and efforts have increased to better utilize the research and development resources the laboratories provide. This document, Technology '90, is the latest in a series that is intended to communicate some of the many opportunities available for US industry and universities to work with the DOE and its laboratories in the vital activity of improving technology transfer to meet national needs. Technology '90 is divided into three sections: Overview, Technologies, and Laboratories. The Overview section describes the activities and accomplishments of the DOE research and development program offices. The Technologies section provides descriptions of new technologies developed at the DOE laboratories. The Laboratories section presents information on the missions, programs, and facilities of each laboratory, along with a name and telephone number of a technology transfer contact for additional information. Separate papers were prepared for appropriate sections of this report.

  18. Research Technology

    NASA Image and Video Library

    2004-04-15

    Pictured is an artist's concept of the Rocket Based Combined Cycle (RBCC) launch. The RBCC's overall objective is to provide a technology test bed to investigate critical technologies associated with opperational usage of these engines. The program will focus on near term technologies that can be leveraged to ultimately serve as the near term basis for Two Stage to Orbit (TSTO) air breathing propulsions systems and ultimately a Single Stage To Orbit (SSTO) air breathing propulsion system.

  19. Technology transfer

    NASA Technical Reports Server (NTRS)

    Handley, Thomas

    1992-01-01

    The requirements for a successful technology transfer program and what such a program would look like are discussed. In particular, the issues associated with technology transfer in general, and within the Jet Propulsion Laboratory (JPL) environment specifically are addressed. The section on background sets the stage, identifies the barriers to successful technology transfer, and suggests actions to address the barriers either generally or specifically. The section on technology transfer presents a process with its supporting management plan that is required to ensure a smooth transfer process. Viewgraphs are also included.

  20. Technological Tyranny

    NASA Astrophysics Data System (ADS)

    Greenwood, Dick

    1984-08-01

    It is implicitly assumed by those who create, develop, control and deploy new technology, as well as by society at-large, that technological innovation always represents progress. Such an unchallenged assumption precludes an examination and evaluation of the interrelationships and impact the development and use of technology have on larger public policy matters, such as preservation of democratic values, national security and military policies, employment, income and tax policies, foreign policy and the accountability of private corporate entities to society. This brief challenges those assumptions and calls for social control of technology.

  1. Healthcare technology and technology assessment.

    PubMed

    Herndon, James H; Hwang, Raymond; Bozic, K J; Bozic, K H

    2007-08-01

    New technology is one of the primary drivers for increased healthcare costs in the United States. Both physician and industry play important roles in the development, adoption, utilization and choice of new technologies. The Federal Drug Administration regulates new drugs and new medical devices, but healthcare technology assessment remains limited. Healthcare technology assessment originated in federal agencies; today it is decentralized with increasing private sector efforts. Innovation is left to free market forces, including direct to consumer marketing and consumer choice. But to be fair to the consumer, he/she must have free knowledge of all the risks and benefits of a new technology in order to make an informed choice. Physicians, institutions and industry need to work together by providing proven, safe, clinically effective and cost effective new technologies, which require valid pre-market clinical trials and post-market continued surveillance with national and international registries allowing full transparency of new products to the consumer--the patient.

  2. Thermally activated technologies: Technology Roadmap

    SciTech Connect

    None, None

    2003-05-01

    The purpose of this Technology Roadmap is to outline a set of actions for government and industry to develop thermally activated technologies for converting America’s wasted heat resources into a reservoir of pollution-free energy for electric power, heating, cooling, refrigeration, and humidity control. Fuel flexibility is important. The actions also cover thermally activated technologies that use fossil fuels, biomass, and ultimately hydrogen, along with waste heat.

  3. Plastics Technology.

    ERIC Educational Resources Information Center

    Barker, Tommy G.

    This curriculum guide is designed to assist junior high schools industrial arts teachers in planning new courses and revising existing courses in plastics technology. Addressed in the individual units of the guide are the following topics: introduction to production technology; history and development of plastics; safety; youth leadership,…

  4. Technology Push

    ERIC Educational Resources Information Center

    Kennedy, Mike

    2008-01-01

    When students, teachers, administrators and others employed in education arrive at work every day on thousands of campuses across the nation, it should come as no surprise that at every step along the way, technology is there to greet them. Technological advancements in education, as well as in facilities operation and management, are not a…

  5. Use Technology

    ERIC Educational Resources Information Center

    Teo, Timothy

    2013-01-01

    Technology acceptance is posited to be influenced by a variety of factors, including individual differences, social influences, beliefs, attitudes and situational influences (Agarwal, 2000; Teo, 2009a). A majority of the conceptualisations of technology acceptance have drawn on theories and models from social psychology, notably the theory of…

  6. Technological Advancements

    ERIC Educational Resources Information Center

    Kennedy, Mike

    2010-01-01

    The influx of technology has brought significant improvements to school facilities. Many of those advancements can be found in classrooms, but when students head down the hall to use the washrooms, they are likely to find a host of technological innovations that have improved conditions in that part of the building. This article describes modern…

  7. Environmental Technology.

    ERIC Educational Resources Information Center

    Columbus State Community Coll., OH.

    This document contains materials developed for and about the environmental technology tech prep program of the South-Western City Schools in Ohio. Part 1 begins with a map of the program, which begins with an environmental science technology program in grades 11 and 12 that leads to entry-level employment or a 2-year environmental technology…

  8. Information Technology.

    ERIC Educational Resources Information Center

    Reynolds, Roger

    1983-01-01

    Describes important information-handling products, predicting future devices in light of convergence and greater flexibility offered through use of microchip technology. Contends that information technology and its impact of privacy depends on how information systems are used, arguing that the privacy issue deals more with moral/physiological…

  9. Woodworking Technology.

    ERIC Educational Resources Information Center

    Kirk, Albert S.; And Others

    1991-01-01

    Three articles discuss the importance of wood processing to manufacturing and construction industries and the need for progressive change in the curriculum; the evolution of wood-based synthetic panel materials; and the technological advances in the computer control of machine tools and their incorporation into wood technology curricula. (JOW)

  10. Technological Advancements

    ERIC Educational Resources Information Center

    Kennedy, Mike

    2010-01-01

    The influx of technology has brought significant improvements to school facilities. Many of those advancements can be found in classrooms, but when students head down the hall to use the washrooms, they are likely to find a host of technological innovations that have improved conditions in that part of the building. This article describes modern…

  11. Use Technology

    ERIC Educational Resources Information Center

    Teo, Timothy

    2013-01-01

    Technology acceptance is posited to be influenced by a variety of factors, including individual differences, social influences, beliefs, attitudes and situational influences (Agarwal, 2000; Teo, 2009a). A majority of the conceptualisations of technology acceptance have drawn on theories and models from social psychology, notably the theory of…

  12. Technology Toolkit.

    ERIC Educational Resources Information Center

    Brooklyn Public Library, NY.

    This reference resource identifies issues concerning technology use in library literacy programs and describes approaches that work at the Brooklyn (New York) Public Library. Section 1 discusses the learning centers at the library, including its mission, philosophy, curriculum, technology, volunteer tutors, and active learning environment. Section…

  13. Technology Transformation

    ERIC Educational Resources Information Center

    Scott, Heather; McGilll, Toria

    2011-01-01

    Social networking and other technologies, if used judiciously, present the means to integrate 21st century skills into the classroom curriculum. But they also introduce challenges that educators must overcome. Increased concerns about plagiarism and access to technology can test educators' creativity and school resources. Air Academy High School,…

  14. Plastics Technology.

    ERIC Educational Resources Information Center

    Barker, Tommy G.

    This curriculum guide is designed to assist junior high schools industrial arts teachers in planning new courses and revising existing courses in plastics technology. Addressed in the individual units of the guide are the following topics: introduction to production technology; history and development of plastics; safety; youth leadership,…

  15. Recycling Technology.

    ERIC Educational Resources Information Center

    Aviation/Space, 1982

    1982-01-01

    In a comprehensive nationwide effort, National Aeronautics and Space Administration (NASA) seeks to increase public and private sector benefits by broadening and accelerating the secondary application of aerospace technology. Discussed are NASA's Applications Centers, publications, technology applications, and Computer Software Management and…

  16. Information Technology.

    ERIC Educational Resources Information Center

    Reynolds, Roger

    1983-01-01

    Describes important information-handling products, predicting future devices in light of convergence and greater flexibility offered through use of microchip technology. Contends that information technology and its impact of privacy depends on how information systems are used, arguing that the privacy issue deals more with moral/physiological…

  17. Technology Transformation

    ERIC Educational Resources Information Center

    Scott, Heather; McGilll, Toria

    2011-01-01

    Social networking and other technologies, if used judiciously, present the means to integrate 21st century skills into the classroom curriculum. But they also introduce challenges that educators must overcome. Increased concerns about plagiarism and access to technology can test educators' creativity and school resources. Air Academy High School,…

  18. Technology Tips

    ERIC Educational Resources Information Center

    Santos-Trigo, Manuel

    2004-01-01

    A dynamic program for geometry called Cabri Geometry II is used to examine properties of figures like triangles and make connections with other mathematical ideas like ellipse. The technology tip includes directions for creating such a problem with technology and suggestions for exploring it.

  19. Technology Integration

    ERIC Educational Resources Information Center

    T.H.E. Journal, 2004

    2004-01-01

    The use of instructional technology has evolved over the last two decades, initially, instructional technology had two uses: learning about computers and using computers to increase basic skills. Learning about computers morphed into computer literacy, which is typically defined as the history, terminology and background of computing, using…

  20. Woodworking Technology.

    ERIC Educational Resources Information Center

    Kirk, Albert S.; And Others

    1991-01-01

    Three articles discuss the importance of wood processing to manufacturing and construction industries and the need for progressive change in the curriculum; the evolution of wood-based synthetic panel materials; and the technological advances in the computer control of machine tools and their incorporation into wood technology curricula. (JOW)

  1. Technology Tips

    ERIC Educational Resources Information Center

    Santos-Trigo, Manuel

    2004-01-01

    A dynamic program for geometry called Cabri Geometry II is used to examine properties of figures like triangles and make connections with other mathematical ideas like ellipse. The technology tip includes directions for creating such a problem with technology and suggestions for exploring it.

  2. Sensor technology

    NASA Technical Reports Server (NTRS)

    Sokoloski, Martin M.

    1988-01-01

    The objective is to provide necessary expertise and technology to advance space remote sensing of terrestrial, planetary, and galactic phenomena through the use of electromagnetic and electro-optic properties of gas, liquid, and solid state materials technology. The Sensor Technology Program is divided into two subprograms: a base research and development part and a Civil Space Technology Initiative (CSTI) part. The base research and development consists of research on artificially grown materials such as quantum well and superlattice structure with the potential for new and efficient means for detecting electromagnetic phenomena. Research is also being done on materials and concepts for detector components and devices for measuring high energy phenomena such as UV, X-, and gamma rays that are required observables in astrophysis and solar physics missions. The CSTI program is more mission driven and is balanced among four major disciplines: detector sensors; submillimeter wave sensors; LIDAR/DIAL sensors; and cooler technology.

  3. Functional characteristics and radiation tolerance of AToM, the front-end chip of BaBar silicon vertex tracker

    SciTech Connect

    Manfredi, P.F.; Abbott, B.; Clark, A.

    1999-12-01

    The readout chip designed to process the microstrip signals in the BaBar Silicon Vertex Tracker (SVT), after being realized twice in a radsoft technology has been transferred into the final radhard process. So far the circuit has gone through four different radhard submissions, one aiming at providing a preliminary insight into the characteristics of the radhard chip, the other ones constituting pre-production and production runs. Chips from these submissions have undergone a thorough set of tests addressing functional aspects, noise parameters and effects of radiation on signal and noise behavior. The present paper discusses the results of these tests and describes the final version of the circuit which has been proven to successfully meet the experiment requirements.

  4. Technology development.

    PubMed

    Gomory, R E

    1983-05-06

    In technology development significant advances are as often the result of a series of evolutionary steps as they are of breakthroughs. This is illustrated by the examples of the steam engine and the computer. Breakthroughs, such as the transistor, are relatively rare, and are often the result of the introduction of new knowledge coming from a quite different area. Technology development is often difficult to predict because of its complexity; practical considerations may far outweigh apparent scientific advantages, and cultural factors enter in at many levels. In a large technological organization problems exist in bringing scientific knowledge to bear on development, but much can be done to obviate these difficulties.

  5. Ergonomics technology

    NASA Technical Reports Server (NTRS)

    Jones, W. L.

    1977-01-01

    Major areas of research and development in ergonomics technology for space environments are discussed. Attention is given to possible applications of the technology developed by NASA in industrial settings. A group of mass spectrometers for gas analysis capable of fully automatic operation has been developed for atmosphere control on spacecraft; a version for industrial use has been constructed. Advances have been made in personal cooling technology, remote monitoring of medical information, and aerosol particle control. Experience gained by NASA during the design and development of portable life support units has recently been applied to improve breathing equipment used by fire fighters.

  6. Ergonomics technology

    NASA Technical Reports Server (NTRS)

    Jones, W. L.

    1977-01-01

    Major areas of research and development in ergonomics technology for space environments are discussed. Attention is given to possible applications of the technology developed by NASA in industrial settings. A group of mass spectrometers for gas analysis capable of fully automatic operation has been developed for atmosphere control on spacecraft; a version for industrial use has been constructed. Advances have been made in personal cooling technology, remote monitoring of medical information, and aerosol particle control. Experience gained by NASA during the design and development of portable life support units has recently been applied to improve breathing equipment used by fire fighters.

  7. Twenty Years of Rad-Hard K14 SPAD in Space Projects

    PubMed Central

    Michálek, Vojtěch; Procházka, Ivan; Blažej, Josef

    2015-01-01

    During last two decades, several photon counting detectors have been developed in our laboratory. One of the most promising detector coming from our group silicon K14 Single Photon Avalanche Diode (SPAD) is presented with its valuable features and space applications. Based on the control electronics, it can be operated in both gated and non-gated mode. Although it was designed for photon counting detection, it can be employed for multiphoton detection as well. With respect to control electronics employed, the timing jitter can be as low as 20 ps RMS. Detection efficiency is about 40 % in range of 500 nm to 800 nm. The detector including gating and quenching circuitry has outstanding timing stability. Due to its radiation resistivity, the diode withstands 100 krad gamma ray dose without parameters degradation. Single photon detectors based on K14 SPAD were used for planetary altimeter and atmospheric lidar in MARS92/96 and Mars Surveyor ’98 space projects, respectively. Recent space applications of K14 SPAD comprises LIDAR and mainly time transfer between ground stations and artificial satellites. These include Laser Time Transfer, Time Transfer by Laser Link, and European Laser Timing projects. PMID:26213945

  8. GR740: Rad-Hard Quad-Core LEON4FT System-on-Chip

    NASA Astrophysics Data System (ADS)

    Hijorth, Magnus; Aberg, Martin; Wessman, Nils-Johan; Andersson, Jan; Chevallier, Remy; Forsyth, Russel; Weigand, Rolad; Fossati, Luca

    2015-09-01

    The GR740 microprocessor device is a SPARC V8(E) based multi-core architecture that provides a significant performance increase compared to earlier generations of European space processors. The GR740 is currently in development at Cobham Gaisler, Sweden, and STMicroelectronics, France, in activities to develop the Next Generation Microprocessor (NGMP) initiated and funded by the European Space Agency (ESA).

  9. Twenty Years of Rad-Hard K14 SPAD in Space Projects.

    PubMed

    Michálek, Vojtěch; Procházka, Ivan; Blažej, Josef

    2015-07-24

    During last two decades, several photon counting detectors have been developed in our laboratory. One of the most promising detector coming from our group silicon K14 Single Photon Avalanche Diode (SPAD) is presented with its valuable features and space applications. Based on the control electronics, it can be operated in both gated and non-gated mode. Although it was designed for photon counting detection, it can be employed for multiphoton detection as well. With respect to control electronics employed, the timing jitter can be as low as 20 ps RMS. Detection efficiency is about 40%in range of 500 nm to 800 nm. The detector including gating and quenching circuitry has outstanding timing stability. Due to its radiation resistivity, the diode withstands 100 krad gamma ray dose without parameters degradation. Single photon detectors based on K14 SPAD were used for planetary altimeter and atmospheric lidar in MARS92/96 and Mars Surveyor '98 space projects, respectively. Recent space applications of K14 SPAD comprises LIDAR and mainly time transfer between ground stations and artificial satellites. These include Laser Time Transfer, Time Transfer by Laser Link, and European Laser Timing projects.

  10. Rad-hard electronics development program for SSC liquid-argon calorimeters

    SciTech Connect

    Stevens, A.; Dawson, J. . High Energy Physics Div.); Kraner, H.; Radeka, V.; Rescia, S. )

    1990-01-01

    The development program for radiation-hard low-noise low-power front-end electronics for SSC calorimetry is described. Radiation doses of up to 20 MRad and neutron fluences of 10{sup 14} neutrons/cm{sup 2} are expected over ten years of operation. These effects are simulated by exposing JFETs to neutrons and ionizing radiation and measuring the resulting bias, leakage current and noise variations. In the case of liquid-argon calorimeters, a large part of the front-end circuitry may be located directly within the low-temperature environment (90 K), placing additional constraints on the choice of components and on the design. This approach minimizes the noise and the response time. The radiation damage test facilities at Argonne will also be described. These include sources of neutrons, electrons, and gamma radiation. 8 refs., 9 figs.

  11. Radiation damage effects in Si materials and detectors and rad-hard Si detectors for SLHC

    NASA Astrophysics Data System (ADS)

    Li, Z.

    2009-03-01

    Silicon sensors, widely used in high energy and nuclear physics experiments, suffer severe radiation damage that leads to degradations in sensor performance. These degradations include significant increases in leakage current, bulk resistivity, space charge concentration, and free carrier trapping. For LHC applications, where the total fluence is in the order of 1 × 1015 neq/cm2 for 10 years, the increase in space charge concentration has been the main problem since it can significantly increase the sensor full depletion voltage, causing either breakdown if operated at high biases or charge collection loss if operated at lower biases than full depletion. For LHC Upgrade, or the SLHC, however, whit an increased total fluence up to 1 × 1016 neq/cm2, the main limiting factor for Si detector operation is the severe trapping of free carriers by radiation-induced defect levels. Several new approaches have been developed to make Si detector more radiation hard/tolerant to such ultra-high radiation, including 3D Si detectors, Current-Injected-Diodes (CID) detectors, and Elevated temperature annealing.

  12. III-V/Ge MOS device technologies for low power integrated systems

    NASA Astrophysics Data System (ADS)

    Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

    2016-11-01

    CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

  13. Videodisc technology

    SciTech Connect

    Marsh, F.E. Jr.

    1981-03-01

    An overview of the technology of videodiscs is given. The emphasis is on systems that use reflection or transmission of laser light. Possible use of videodiscs for storage of bibliographic information is considered. 6 figures, 3 tables. (RWR)

  14. Technology Innovation

    EPA Pesticide Factsheets

    EPA produces innovative technologies and facilitates their creation in line with the Agency mission to create products such as the stormwater calculator, remote sensing, innovation clusters, and low-cost air sensors.

  15. Electrosynthesis Technology.

    ERIC Educational Resources Information Center

    Weinberg, Norman L.

    1983-01-01

    Provides a prospective on electrosynthesis technology for chemical educators and students by discussing electrosynthesis reactions and experiments. Includes tables illustrating some electrochemical products, variables to consider in electrochemical reactions, indirect electrolysis of organic compounds, examples of direct/indirect electrochemical…

  16. Strategic Technology

    DTIC Science & Technology

    2012-03-11

    of massive multi-player gaming environments to facilitate expert education, collaboration, and experimentation. Finally, it recommends a focus on red ... team analysis and experimentation as a means of minimizing strategic surprise from technological sources. To fully explore potential strategic

  17. Assistive Technology

    MedlinePlus

    ... at3center.net/home . Some Area Agencies on Aging (AAA) have programs or link to services that assist ... obtain low-cost assistive technology. To locate your AAA, call the Eldercare Locator at 1-800-677- ...

  18. Electrosynthesis Technology.

    ERIC Educational Resources Information Center

    Weinberg, Norman L.

    1983-01-01

    Provides a prospective on electrosynthesis technology for chemical educators and students by discussing electrosynthesis reactions and experiments. Includes tables illustrating some electrochemical products, variables to consider in electrochemical reactions, indirect electrolysis of organic compounds, examples of direct/indirect electrochemical…

  19. Aerocapture Technologies

    NASA Technical Reports Server (NTRS)

    Keys, Andrew S.

    2006-01-01

    Aeroassist technology development is a vital part of the NASA In-Space Propulsion Technology (ISPT) Program. One of the main focus areas of ISPT is aeroassist technologies through the Aerocapture Technology (AT) Activity. Within the ISPT, the current aeroassist technology development focus is aerocapture. Aerocapture relies on the exchange of momentum with an atmosphere to achieve thrust, in this case a decelerating thrust leading to orbit capture. Without aerocapture, a substantial propulsion system would be needed on the spacecraft to perform the same reduction of velocity. This could cause reductions in the science payload delivered to the destination, increases in the size of the launch vehicle (to carry the additional fuel required for planetary capture) or could simply make the mission impossible due to additional propulsion requirements. The AT is advancing each technology needed for the successful implementation of aerocapture in future missions. The technology development focuses on both rigid aeroshell systems as well as the development of inflatable aerocapture systems, advanced aeroshell performance sensors, lightweight structure and higher temperature adhesives. Inflatable systems such as tethered trailing ballutes ('balloon parachutes'), clamped ballutes, and inflatable aeroshells are also under development. Aerocapture-specific computational tools required to support future aerocapture missions are also an integral part of the ATP. Tools include: engineering reference atmosphere models, guidance and navigation, aerothermodynamic modeling, radiation modeling and flight simulation. Systems analysis plays a key role in the AT development process. The NASA in-house aerocapture systems analysis team has been taken with multiple systems definition and concept studies to complement the technology development tasks. The team derives science requirements, develops guidance and navigation algorithms, as well as engineering reference atmosphere models and

  20. Technology Report

    NASA Technical Reports Server (NTRS)

    Repucci, George

    1996-01-01

    This is the fourth report of a series of semi-annual reports that describe the technology areas being advanced under this contract and the progress achieved to date. The most significant technical event this period was the successful completion of the Lewis spacecraft in 2 years (contract award date was June 1994). In August of 1996 we held a program-wide Technology Workshop which covered all aspects of the Lewis payload. A copy of the Workshop proceedings is attached.

  1. Radiator technology

    NASA Technical Reports Server (NTRS)

    Juhasz, Albert J.

    1993-01-01

    Radiator technology is discussed in the context of the Civilian Space Technology Initiative's (CSTI's) high capacity power-thermal management project. The CSTI project is a subset of a project to develop a piloted Mars nuclear electric propulsion (NEP) vehicle. The following topics are presented in vugraph form: advanced radiator concepts; heat pipe codes and testing; composite materials; radiator design and integration; and surface morphology.

  2. Fabrication Technology

    SciTech Connect

    Blaedel, K.L.

    1993-03-01

    The mission of the Fabrication Technology thrust area is to have an adequate base of manufacturing technology, not necessarily resident at Lawrence Livermore National Laboratory (LLNL), to conduct the future business of LLNL. The specific goals continue to be to (1) develop an understanding of fundamental fabrication processes; (2) construct general purpose process models that will have wide applicability; (3) document findings and models in journals; (4) transfer technology to LLNL programs, industry, and colleagues; and (5) develop continuing relationships with the industrial and academic communities to advance the collective understanding of fabrication processes. The strategy to ensure success is changing. For technologies in which they are expert and which will continue to be of future importance to LLNL, they can often attract outside resources both to maintain their expertise by applying it to a specific problem and to help fund further development. A popular vehicle to fund such work is the Cooperative Research and Development Agreement with industry. For technologies needing development because of their future critical importance and in which they are not expert, they use internal funding sources. These latter are the topics of the thrust area. Three FY-92 funded projects are discussed in this section. Each project clearly moves the Fabrication Technology thrust area towards the goals outlined above. They have also continued their membership in the North Carolina State University Precision Engineering Center, a multidisciplinary research and graduate program established to provide the new technologies needed by high-technology institutions in the US. As members, they have access to and use of the results of their research projects, many of which parallel the precision engineering efforts at LLNL.

  3. Emerging technologies

    SciTech Connect

    Hodson, C.O.; Williams, D.

    1996-07-01

    Among the emerging technologies for air, hazardous waste and water come new ways of looking at pollution, in both the figurative and quite literal sense. The use of microbes for remediation and pollution control is a component in many of the technologies in this report and is the focus of environmental research at many university and industry labs. Bacteria are the engines driving one featured emissions control technology: the air biofilter. Biofilters are probably more acceptable to most engineers as a soil remediation technology--such as the innovative method described in the hazardous waste section--rather than as means of cleaning off-gases, but in many cases bugs can perform the function inexpensively. The authors give the basics on this available technology. A more experimental application of microbes is being investigated as a potential quantum leap in heavy metals removal technology: bio-engineered, metal consuming plants. The effort to genetically engineer a green remediation tool is detailed in the hazardous waste section.

  4. Advanced manufacturing of SIMOX for low power electronics

    NASA Astrophysics Data System (ADS)

    Alles, Michael; Krull, Wade

    1996-04-01

    Silicon-on-insulator (SOI) has emerged as a key technology for low power electronics. The merits of SOI technology have been demonstrated, and are gaining acceptance in the semiconductor industry. In order for the SOI approach to be viable, several factors must converge, including the availability of SOI substrates in sufficient quantity, of acceptable quality, and at a competitive price. This work describes developments in SIMOX manufacturing technology and summarizes progress in each of these areas.

  5. Radiation Effects and Hardening Techniques for Spacecraft Microelectronics

    NASA Astrophysics Data System (ADS)

    Gambles, J. W.; Maki, G. K.

    2002-01-01

    The natural radiation from the Van Allen belts, solar flares, and cosmic rays found outside of the protection of the earth's atmosphere can produce deleterious effects on microelectronics used in space systems. Historically civil space agencies and the commercial satellite industry have been able to utilize components produced in special radiation hardened fabrication process foundries that were developed during the 1970s and 1980s under sponsorship of the Departments of Defense (DoD) and Energy (DoE). In the post--cold war world the DoD and DoE push to advance the rad--hard processes has waned. Today the available rad--hard components lag two-plus technology node generations behind state- of-the-art commercial technologies. As a result space craft designers face a large performance gap when trying to utilize available rad--hard components. Compounding the performance gap problems, rad--hard components are becoming increasingly harder to get. Faced with the economic pitfalls associated with low demand versus the ever increasing investment required for integrated circuit manufacturing equipment most sources of rad--hard parts have simply exited this market in recent years, leaving only two domestic US suppliers of digital rad--hard components. This paper summarizes the radiation induced mechanisms that can cause digital microelectronics to fail in space, techniques that can be applied to mitigate these failure mechanisms, and ground based testing used to validate radiation hardness/tolerance. The radiation hardening techniques can be broken down into two classes, Hardness By Process (HBP) and Hardness By Design (HBD). Fortunately many HBD techniques can be applied to commercial fabrication processes providing space craft designer with radiation tolerant Application Specific Integrated Circuits (ASICs) that can bridge the performance gap between the special HBP foundries and the commercial state-of-the-art performance.

  6. Healthcare technology and technology assessment

    PubMed Central

    Hwang, Raymond; Bozic, K. H.

    2007-01-01

    New technology is one of the primary drivers for increased healthcare costs in the United States. Both physician and industry play important roles in the development, adoption, utilization and choice of new technologies. The Federal Drug Administration regulates new drugs and new medical devices, but healthcare technology assessment remains limited. Healthcare technology assessment originated in federal agencies; today it is decentralized with increasing private sector efforts. Innovation is left to free market forces, including direct to consumer marketing and consumer choice. But to be fair to the consumer, he/she must have free knowledge of all the risks and benefits of a new technology in order to make an informed choice. Physicians, institutions and industry need to work together by providing proven, safe, clinically effective and cost effective new technologies, which require valid pre-market clinical trials and post-market continued surveillance with national and international registries allowing full transparency of new products to the consumer—the patient. PMID:17426985

  7. Diabetes Technology.

    PubMed

    Pfützner, Andreas

    2016-01-01

    Diabetes technology is an evolving field. The research started with the development of blood glucose meters for patient self-testing and the introduction of insulin pen injection devices. Modern devices employ new technological features, such as the use of computer simulations and mathematical algorithms, connectivity and signal transfer, and the use of modern (space research-derived) materials. With these innovations, the goal to develop an artificial pancreas by closing the loop between a continuous glucose sensor and a continuous insulin-delivering device via insulin delivery algorithms is coming closer to reality. As a consequence, interim achievements on this way result in the commercialization of innovative new diabetes technology devices, which help to facilitate the daily life of the affected people with diabetes. © 2016 S. Karger AG, Basel.

  8. Research Technology

    NASA Image and Video Library

    2001-08-06

    The test of twin Linear Aerospike XRS-2200 engines, originally built for the X-33 program, was performed on August 6, 2001 at NASA's Sternis Space Center, Mississippi. The engines were fired for the planned 90 seconds and reached a planned maximum power of 85 percent. NASA's Second Generation Reusable Launch Vehicle Program , also known as the Space Launch Initiative (SLI), is making advances in propulsion technology with this third and final successful engine hot fire, designed to test electro-mechanical actuators. Information learned from this hot fire test series about new electro-mechanical actuator technology, which controls the flow of propellants in rocket engines, could provide key advancements for the propulsion systems for future spacecraft. The Second Generation Reusable Launch Vehicle Program, led by NASA's Marshall Space Flight Center in Huntsville, Alabama, is a technology development program designed to increase safety and reliability while reducing costs for space travel. The X-33 program was cancelled in March 2001.

  9. Technology Transfer

    NASA Technical Reports Server (NTRS)

    Smith, Nanette R.

    1995-01-01

    The objective of this summer's work was to attempt to enhance Technology Application Group (TAG) ability to measure the outcomes of its efforts to transfer NASA technology. By reviewing existing literature, by explaining the economic principles involved in evaluating the economic impact of technology transfer, and by investigating the LaRC processes our William & Mary team has been able to lead this important discussion. In reviewing the existing literature, we identified many of the metrics that are currently being used in the area of technology transfer. Learning about the LaRC technology transfer processes and the metrics currently used to track the transfer process enabled us to compare other R&D facilities to LaRC. We discuss and diagram impacts of technology transfer in the short run and the long run. Significantly, it serves as the basis for analysis and provides guidance in thinking about what the measurement objectives ought to be. By focusing on the SBIR Program, valuable information regarding the strengths and weaknesses of this LaRC program are to be gained. A survey was developed to ask probing questions regarding SBIR contractors' experience with the program. Specifically we are interested in finding out whether the SBIR Program is accomplishing its mission, if the SBIR companies are providing the needed innovations specified by NASA and to what extent those innovations have led to commercial success. We also developed a survey to ask COTR's, who are NASA employees acting as technical advisors to the SBIR contractors, the same type of questions, evaluating the successes and problems with the SBIR Program as they see it. This survey was developed to be implemented interactively on computer. It is our hope that the statistical and econometric studies that can be done on the data collected from all of these sources will provide insight regarding the direction to take in developing systematic evaluations of programs like the SBIR Program so that they can

  10. Technology Benefits

    NASA Technical Reports Server (NTRS)

    Haller, William

    2001-01-01

    An assessment was recently performed by NASA s Inter-Center Systems Analysis Team to quantify the potential emission reduction benefits from technologies being developed under UEET. The CO2 and LTO NO, reductions were estimated for 4 vehicles: a 50-passenger regional jet, a twin-engine, long-range subsonic transport, a high-speed (Mach 2.4) civil transport and a supersonic (Mach 2) business jet. The results of the assessment confirm that the current portfolio of technologies within the UEET program provides an opportunity for substantial reductions in CO2 and NO, emissions.

  11. Manufacturing technologies

    NASA Astrophysics Data System (ADS)

    The Manufacturing Technologies Center is at the core of Sandia National Laboratories' advanced manufacturing effort which spans the entire product realization process. The center's capabilities in product and process development are summarized in the following disciplines: (1) mechanical - rapid prototyping, manufacturing engineering, machining and computer-aided manufacturing, measurement and calibration, and mechanical and electronic manufacturing liaison; (2) electronics - advanced packaging for microelectronics, printed circuits, and electronic fabrication; and (3) materials - ceramics, glass, thin films, vacuum technology, brazing, polymers, adhesives, composite materials, and process analysis.

  12. Mirror Technology

    NASA Technical Reports Server (NTRS)

    1992-01-01

    Under a NASA contract, MI-CVD developed a process for producing bulk silicon carbide by means of a chemical vapor deposition process. The technology allows growth of a high purity material with superior mechanical/thermal properties and high polishability - ideal for mirror applications. The company employed the technology to develop three research mirrors for NASA Langley and is now marketing it as CVD SILICON CARBIDE. Its advantages include light weight, thermal stability and high reflectivity. The material has nuclear research facility applications and is of interest to industrial users of high power lasers.

  13. Technology applications

    NASA Technical Reports Server (NTRS)

    Anuskiewicz, T.; Johnston, J.; Leavitt, W.; Zimmerman, R. R.

    1972-01-01

    A summary of NASA Technology Utilization programs for the period of 1 December 1971 through 31 May 1972 is presented. An abbreviated description of the overall Technology Utilization Applications Program is provided as a background for the specific applications examples. Subjects discussed are in the broad headings of: (1) cancer, (2) cardiovascular disease, (2) medical instrumentation, (4) urinary system disorders, (5) rehabilitation medicine, (6) air and water pollution, (7) housing and urban construction, (8) fire safety, (9) law enforcement and criminalistics, (10) transportation, and (11) mine safety.

  14. Manufacturing technology

    SciTech Connect

    Blaedel, K.L.

    1997-02-01

    The specific goals of the Manufacturing Technology thrust area are to develop an understanding of fundamental fabrication processes, to construct general purpose process models that will have wide applicability, to document our findings and models in journals, to transfer technology to LLNL programs, industry, and colleagues, and to develop continuing relationships with industrial and academic communities to advance our collective understanding of fabrication processes. Advances in four projects are described here, namely Design of a Precision Saw for Manufacturing, Deposition of Boron Nitride Films via PVD, Manufacturing and Coating by Kinetic Energy Metallization, and Magnet Design and Application.

  15. SUPERFUND INNOVATIVE TECHNOLOGY EVALUATION - TECHNOLOGY PROFILES

    EPA Science Inventory

    This document is intended as a reference guide for EPA Regional decision makers and others interested in technologies in the SITE Demonstration and Emerging Technologies programs. The Technologies are described in technology profiles, presented in alphabetical order by developer ...

  16. SUPERFUND INNOVATIVE TECHNOLOGY EVALUATION - TECHNOLOGY PROFILES

    EPA Science Inventory

    This document is intended as a reference guide for EPA Regional decision makers and others interested in technologies in the SITE Demonstration and Emerging Technologies programs. The Technologies are described in technology profiles, presented in alphabetical order by developer ...

  17. Technology Transfer: Marketing Tomorrow's Technology

    NASA Technical Reports Server (NTRS)

    Tcheng, Erene

    1995-01-01

    The globalization of the economy and the end of the Cold War have triggered many changes in the traditional practices of U.S. industry. To effectively apply the resources available to the United States, the federal government has firmly advocated a policy of technology transfer between private industry and government labs, in this case the National Aeronautics and Space Administration (NASA). NASA Administrator Daniel Goldin is a strong proponent of this policy and has organized technology transfer or commercialization programs at each of the NASA field centers. Here at Langley Research Center, the Technology Applications Group (TAG) is responsible for facilitating the transfer of Langley developed research and technology to U.S. industry. Entering the program, I had many objectives for my summer research with TAG. Certainly, I wanted to gain a more thorough understanding of the concept of technology transfer and Langley's implementation of a system to promote it to both the Langley community and the community at large. Also, I hoped to become more familiar with Langley's research capabilities and technology inventory available to the public. More specifically, I wanted to learn about the technology transfer process at Langley. Because my mentor is a member of Materials and Manufacturing marketing sector of the Technology Transfer Team, another overriding objective for my research was to take advantage of his work and experience in materials research to learn about the Advanced Materials Research agency wide and help market these developments to private industry. Through the various projects I have been assigned to work on in TAG, I have successfully satisfied the majority of these objectives. Work on the Problem Statement Process for TAG as well as the development of the Advanced Materials Research Brochure have provided me with the opportunity to learn about the technology transfer process from the outside looking in and the inside looking out. Because TAG covers

  18. Technology Theme.

    ERIC Educational Resources Information Center

    Garrahy, Dennis J.

    One of a series of social studies units designed to develop the reading and writing skills of low achievers, this student activity book focuses on the theme of technology. The unit can be used for high school classes, individual study in alternative and continuing high schools, and adult education classes. Material is divided into four sections.…

  19. Technology Theme.

    ERIC Educational Resources Information Center

    Garrahy, Dennis J.

    One of a series of social studies units designed to develop the reading and writing skills of low achievers, this student activity book focuses on the theme of technology. The unit can be used for high school classes, individual study in alternative and continuing high schools, and adult education classes. Material is divided into four sections.…

  20. Research Technology

    NASA Image and Video Library

    1999-10-21

    Pictured is an artist's concept of an advanced chemical propulsion system called Pulse Detonation. Long term technology research in this advanced propulsion system has the potential to dramatically change the way we think about space propulsion systems. This research is expected to significantly reduce the cost of space travel within the next 25 years.