Radiation Effects of Commercial Resistive Random Access Memories

NASA Technical Reports Server (NTRS)

Chen, Dakai; LaBel, Kenneth A.; Berg, Melanie; Wilcox, Edward; Kim, Hak; Phan, Anthony; Figueiredo, Marco; Buchner, Stephen; Khachatrian, Ani; Roche, Nicolas

2014-01-01

We present results for the single-event effect response of commercial production-level resistive random access memories. We found that the resistive memory arrays are immune to heavy ion-induced upsets. However, the devices were susceptible to single-event functional interrupts, due to upsets from the control circuits. The intrinsic radiation tolerant nature of resistive memory makes the technology an attractive consideration for future space applications.

BCH codes for large IC random-access memory systems

NASA Technical Reports Server (NTRS)

Lin, S.; Costello, D. J., Jr.

1983-01-01

In this report some shortened BCH codes for possible applications to large IC random-access memory systems are presented. These codes are given by their parity-check matrices. Encoding and decoding of these codes are discussed.

76 FR 35238 - Notice of Receipt of Complaint; Solicitation of Comments Relating to the Public Interest

Federal Register 2010, 2011, 2012, 2013, 2014

2011-06-16

... Static Random Access Memories and Products Containing Same, DN 2816; the Commission is soliciting... importation of certain static random access memories and products containing same. The complaint names as...

Integrated semiconductor-magnetic random access memory system

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Blaes, Brent R. (Inventor)

2001-01-01

The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.

Making working memory work: the effects of extended practice on focus capacity and the processes of updating, forward access, and random access.

PubMed

Price, John M; Colflesh, Gregory J H; Cerella, John; Verhaeghen, Paul

2014-05-01

We investigated the effects of 10h of practice on variations of the N-Back task to investigate the processes underlying possible expansion of the focus of attention within working memory. Using subtractive logic, we showed that random access (i.e., Sternberg-like search) yielded a modest effect (a 50% increase in speed) whereas the processes of forward access (i.e., retrieval in order, as in a standard N-Back task) and updating (i.e., changing the contents of working memory) were executed about 5 times faster after extended practice. We additionally found that extended practice increased working memory capacity as measured by the size of the focus of attention for the forward-access task, but not for variations where probing was in random order. This suggests that working memory capacity may depend on the type of search process engaged, and that certain working-memory-related cognitive processes are more amenable to practice than others. Copyright © 2014 Elsevier B.V. All rights reserved.

A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy

NASA Astrophysics Data System (ADS)

Han, Runze; Shen, Wensheng; Huang, Peng; Zhou, Zheng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

2018-04-01

A novel ternary content addressable memory (TCAM) design based on resistive random access memory (RRAM) is presented. Each TCAM cell consists of two parallel RRAM to both store and search for ternary data. The cell size of the proposed design is 8F2, enable a ∼60× cell area reduction compared with the conventional static random access memory (SRAM) based implementation. Simulation results also show that the search delay and energy consumption of the proposed design at the 64-bit word search are 2 ps and 0.18 fJ/bit/search respectively at 22 nm technology node, where significant improvements are achieved compared to previous works. The desired characteristics of RRAM for implementation of the high performance TCAM search chip are also discussed.

Temperature dependent characteristics of the random telegraph noise on contact resistive random access memory

NASA Astrophysics Data System (ADS)

Chang, Liang-Shun; Lin, Chrong Jung; King, Ya-Chin

2014-01-01

The temperature dependent characteristics of the random telegraphic noise (RTN) on contact resistive random access memory (CRRAM) are studied in this work. In addition to the bi-level switching, the occurrences of the middle states in the RTN signal are investigated. Based on the unique its temperature dependent characteristics, a new temperature sensing scheme is proposed for applications in ultra-low power sensor modules.

Physical principles and current status of emerging non-volatile solid state memories

NASA Astrophysics Data System (ADS)

Wang, L.; Yang, C.-H.; Wen, J.

2015-07-01

Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for the next generation of data-storage devices based on a comparison of their performance. [Figure not available: see fulltext.

Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.

2014-04-01

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

Paging memory from random access memory to backing storage in a parallel computer

DOEpatents

Archer, Charles J; Blocksome, Michael A; Inglett, Todd A; Ratterman, Joseph D; Smith, Brian E

2013-05-21

Paging memory from random access memory (`RAM`) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

Effect of Atomic Layer Depositions (ALD)-Deposited Titanium Oxide (TiO2) Thickness on the Performance of Zr40Cu35Al15Ni10 (ZCAN)/TiO2/Indium (In)-Based Resistive Random Access Memory (RRAM) Structures

DTIC Science & Technology

2015-08-01

metal structures, memristors, resistive random access memory, RRAM, titanium dioxide, Zr40Cu35Al15Ni10, ZCAN, resistive memory, tunnel junction 16...TiO2 thickness ........................6 1 1. Introduction Resistive-switching memory elements based on metal-insulator-metal (MIM) diodes ...have attracted great interest due to their potential as components for simple, inexpensive, and high-density non-volatile storage devices. MIM diodes

Non-volatile magnetic random access memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

1994-01-01

Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

Optical mass memories

NASA Technical Reports Server (NTRS)

Bailey, G. A.

1976-01-01

Optical and magnetic variants in the design of trillion-bit read/write memories are compared and tabulated. Components and materials suitable for a random access read/write nonmoving memory system are examined, with preference given to holography and photoplastic materials. Advantages and deficiencies of photoplastics are reviewed. Holographic page composer design, essential features of an optical memory with no moving parts, fiche-oriented random access memory design, and materials suitable for an efficient photoplastic fiche are considered. The optical variants offer advantages in lower volume and weight at data transfer rates near 1 Mbit/sec, but power drain is of the same order as for the magnetic variants (tape memory, disk memory). The mechanical properties of photoplastic film materials still leave much to be desired.

Magnet/Hall-Effect Random-Access Memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1991-01-01

In proposed magnet/Hall-effect random-access memory (MHRAM), bits of data stored magnetically in Perm-alloy (or equivalent)-film memory elements and read out by using Hall-effect sensors to detect magnetization. Value of each bit represented by polarity of magnetization. Retains data for indefinite time or until data rewritten. Speed of Hall-effect sensors in MHRAM results in readout times of about 100 nanoseconds. Other characteristics include high immunity to ionizing radiation and storage densities of order 10(Sup6)bits/cm(Sup 2) or more.

Electrical Evaluation of RCA MWS5501D Random Access Memory, Volume 2, Appendix a

NASA Technical Reports Server (NTRS)

Klute, A.

1979-01-01

The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. The address access time, address readout time, the data hold time, and the data setup time are some of the results surveyed.

76 FR 45295 - In the Matter of Certain Static Random Access Memories and Products Containing Same; Notice of...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-28

... supplementing the amended complaint was filed on June 28, 2011. A second amended complaint was filed on July 13... of certain static random access memories and products containing same by reason of infringement of... 13 of the `937 patent, and whether an industry in the United States exists as required by subsection...

Vertical Launch System Loadout Planner

DTIC Science & Technology

2015-03-01

United States Navy USS United States’ Ship VBA Visual Basic for Applications VLP VLS Loadout Planner VLS Vertical Launch System...with 32 gigabytes of random access memory and eight processors, General Algebraic Modeling System (GAMS) CPLEX version 24 (GAMS, 2015) solves this...problem in ten minutes to an integer tolerance of 10%. The GAMS interpreter and CPLEX solver require 75 Megabytes of random access memory for this

Nonvolatile GaAs Random-Access Memory

NASA Technical Reports Server (NTRS)

Katti, Romney R.; Stadler, Henry L.; Wu, Jiin-Chuan

1994-01-01

Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

Application of phase-change materials in memory taxonomy.

PubMed

Wang, Lei; Tu, Liang; Wen, Jing

2017-01-01

Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other types of memory devices are rarely reported. Here we review the physical principles of phase-change materials and devices aiming to help researchers understand the concept of phase-change memory. We classify phase-change memory devices into phase-change optical disc, phase-change scanning probe memory, phase-change random access memory, and phase-change nanophotonic device, according to their locations in memory hierarchy. For each device type we discuss the physical principles in conjunction with merits and weakness for data storage applications. We also outline state-of-the-art technologies and future prospects.

A Cerebellar-model Associative Memory as a Generalized Random-access Memory

NASA Technical Reports Server (NTRS)

Kanerva, Pentti

1989-01-01

A versatile neural-net model is explained in terms familiar to computer scientists and engineers. It is called the sparse distributed memory, and it is a random-access memory for very long words (for patterns with thousands of bits). Its potential utility is the result of several factors: (1) a large pattern representing an object or a scene or a moment can encode a large amount of information about what it represents; (2) this information can serve as an address to the memory, and it can also serve as data; (3) the memory is noise tolerant--the information need not be exact; (4) the memory can be made arbitrarily large and hence an arbitrary amount of information can be stored in it; and (5) the architecture is inherently parallel, allowing large memories to be fast. Such memories can become important components of future computers.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Vortex-Core Reversal Dynamics: Towards Vortex Random Access Memory

NASA Astrophysics Data System (ADS)

Kim, Sang-Koog

2011-03-01

An energy-efficient, ultrahigh-density, ultrafast, and nonvolatile solid-state universal memory is a long-held dream in the field of information-storage technology. The magnetic random access memory (MRAM) along with a spin-transfer-torque switching mechanism is a strong candidate-means of realizing that dream, given its nonvolatility, infinite endurance, and fast random access. Magnetic vortices in patterned soft magnetic dots promise ground-breaking applications in information-storage devices, owing to the very stable twofold ground states of either their upward or downward core magnetization orientation and plausible core switching by in-plane alternating magnetic fields or spin-polarized currents. However, two technologically most important but very challenging issues --- low-power recording and reliable selection of each memory cell with already existing cross-point architectures --- have not yet been resolved for the basic operations in information storage, that is, writing (recording) and readout. Here, we experimentally demonstrate a magnetic vortex random access memory (VRAM) in the basic cross-point architecture. This unique VRAM offers reliable cell selection and low-power-consumption control of switching of out-of-plane core magnetizations using specially designed rotating magnetic fields generated by two orthogonal and unipolar Gaussian-pulse currents along with optimized pulse width and time delay. Our achievement of a new device based on a new material, that is, a medium composed of patterned vortex-state disks, together with the new physics on ultrafast vortex-core switching dynamics, can stimulate further fruitful research on MRAMs that are based on vortex-state dot arrays.

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

NASA Astrophysics Data System (ADS)

Ando, K.; Fujita, S.; Ito, J.; Yuasa, S.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.; Yoda, H.

2014-05-01

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

Boosting the FM-Index on the GPU: Effective Techniques to Mitigate Random Memory Access.

PubMed

Chacón, Alejandro; Marco-Sola, Santiago; Espinosa, Antonio; Ribeca, Paolo; Moure, Juan Carlos

2015-01-01

The recent advent of high-throughput sequencing machines producing big amounts of short reads has boosted the interest in efficient string searching techniques. As of today, many mainstream sequence alignment software tools rely on a special data structure, called the FM-index, which allows for fast exact searches in large genomic references. However, such searches translate into a pseudo-random memory access pattern, thus making memory access the limiting factor of all computation-efficient implementations, both on CPUs and GPUs. Here, we show that several strategies can be put in place to remove the memory bottleneck on the GPU: more compact indexes can be implemented by having more threads work cooperatively on larger memory blocks, and a k-step FM-index can be used to further reduce the number of memory accesses. The combination of those and other optimisations yields an implementation that is able to process about two Gbases of queries per second on our test platform, being about 8 × faster than a comparable multi-core CPU version, and about 3 × to 5 × faster than the FM-index implementation on the GPU provided by the recently announced Nvidia NVBIO bioinformatics library.

Tuning resistance states by thickness control in an electroforming-free nanometallic complementary resistance random access memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Xiang; Lu, Yang; Lee, Jongho

2016-01-04

Tuning low resistance state is crucial for resistance random access memory (RRAM) that aims to achieve optimal read margin and design flexibility. By back-to-back stacking two nanometallic bipolar RRAMs with different thickness into a complementary structure, we have found that its low resistance can be reliably tuned over several orders of magnitude. Such high tunability originates from the exponential thickness dependence of the high resistance state of nanometallic RRAM, in which electron wave localization in a random network gives rise to the unique scaling behavior. The complementary nanometallic RRAM provides electroforming-free, multi-resistance-state, sub-100 ns switching capability with advantageous characteristics formore » memory arrays.« less

Application of phase-change materials in memory taxonomy

PubMed Central

Wang, Lei; Tu, Liang; Wen, Jing

2017-01-01

Abstract Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other types of memory devices are rarely reported. Here we review the physical principles of phase-change materials and devices aiming to help researchers understand the concept of phase-change memory. We classify phase-change memory devices into phase-change optical disc, phase-change scanning probe memory, phase-change random access memory, and phase-change nanophotonic device, according to their locations in memory hierarchy. For each device type we discuss the physical principles in conjunction with merits and weakness for data storage applications. We also outline state-of-the-art technologies and future prospects. PMID:28740557

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 5, Appendix D

NASA Technical Reports Server (NTRS)

Klute, A.

1979-01-01

The electrical characterization and qualification test results are presented for the RCA MWS 5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Average input high current, worst case input high current, output low current, and data setup time are some of the results presented.

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 4, Appendix C

NASA Technical Reports Server (NTRS)

Klute, A.

1979-01-01

The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Statistical analysis data is supplied along with write pulse width, read cycle time, write cycle time, and chip enable time data.

Random Access Memories: A New Paradigm for Target Detection in High Resolution Aerial Remote Sensing Images.

PubMed

Zou, Zhengxia; Shi, Zhenwei

2018-03-01

We propose a new paradigm for target detection in high resolution aerial remote sensing images under small target priors. Previous remote sensing target detection methods frame the detection as learning of detection model + inference of class-label and bounding-box coordinates. Instead, we formulate it from a Bayesian view that at inference stage, the detection model is adaptively updated to maximize its posterior that is determined by both training and observation. We call this paradigm "random access memories (RAM)." In this paradigm, "Memories" can be interpreted as any model distribution learned from training data and "random access" means accessing memories and randomly adjusting the model at detection phase to obtain better adaptivity to any unseen distribution of test data. By leveraging some latest detection techniques e.g., deep Convolutional Neural Networks and multi-scale anchors, experimental results on a public remote sensing target detection data set show our method outperforms several other state of the art methods. We also introduce a new data set "LEarning, VIsion and Remote sensing laboratory (LEVIR)", which is one order of magnitude larger than other data sets of this field. LEVIR consists of a large set of Google Earth images, with over 22 k images and 10 k independently labeled targets. RAM gives noticeable upgrade of accuracy (an mean average precision improvement of 1% ~ 4%) of our baseline detectors with acceptable computational overhead.

Fast Magnetoresistive Random-Access Memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1991-01-01

Magnetoresistive binary digital memories of proposed new type expected to feature high speed, nonvolatility, ability to withstand ionizing radiation, high density, and low power. In memory cell, magnetoresistive effect exploited more efficiently by use of ferromagnetic material to store datum and adjacent magnetoresistive material to sense datum for readout. Because relative change in sensed resistance between "zero" and "one" states greater, shorter sampling and readout access times achievable.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Cerebellar models of associative memory: Three papers from IEEE COMPCON spring 1989

NASA Technical Reports Server (NTRS)

Raugh, Michael R. (Editor)

1989-01-01

Three papers are presented on the following topics: (1) a cerebellar-model associative memory as a generalized random-access memory; (2) theories of the cerebellum - two early models of associative memory; and (3) intelligent network management and functional cerebellum synthesis.

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Integrated, nonvolatile, high-speed analog random access memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

1994-01-01

This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

Optical memory development. Volume 2: Gain-assisted holographic storage media

NASA Technical Reports Server (NTRS)

Gange, R. A.; Mezrich, R. S.

1972-01-01

Thin deformable films were investigated for use as the storage medium in a holographic optical memory. The research was directed toward solving the problems of material fatigue, selective heat addressing, electrical charging of the film surface and charge patterning by light. A number of solutions to these problems were found but the main conclusion to be drawn from the work is that deformable media which employ heat in the recording process are not satisfactory for use in a high-speed random-access read/write holographic memory. They are, however, a viable approach in applications where either high speed or random-access is not required.

Nanoscale CuO solid-electrolyte-based conductive-bridging, random-access memory cell with a TiN liner

NASA Astrophysics Data System (ADS)

Lee, Jong-Sun; Kim, Dong-Won; Kim, Hea-Jee; Jin, Soo-Min; Song, Myung-Jin; Kwon, Ki-Hyun; Park, Jea-Gun; Jalalah, Mohammed; Al-Hajry, Ali

2018-01-01

The Conductive-bridge random-access memory (CBRAM) cell is a promising candidate for a terabit-level non-volatile memory due to its remarkable advantages. We present for the first time TiN as a diffusion barrier in CBRAM cells for enhancing their reliability. CuO solid-electrolyte-based CBRAM cells implemented with a 0.1-nm TiN liner demonstrated better non-volatile memory characteristics such as 106 AC write/erase endurance cycles with 100-μs AC pulse width and a long retention time of 7.4-years at 85 °C. In addition, the analysis of Ag diffusion in the CBRAM cell suggests that the morphology of the Ag filaments in the electrolyte can be effectively controlled by tuning the thickness of the TiN liner. These promising results pave the way for faster commercialization of terabit-level non-volatile memories.

On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

NASA Astrophysics Data System (ADS)

Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

2018-02-01

In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

Application of holographic optical techniques to bulk memory.

NASA Technical Reports Server (NTRS)

Anderson, L. K.

1971-01-01

Current efforts to exploit the spatial redundancy and built-in imaging of holographic optical techniques to provide high information densities without critical alignment and tight mechanical tolerances are reviewed. Read-write-erase in situ operation is possible but is presently impractical because of limitations in available recording media. As these are overcome, it should prove feasible to build holographic bulk memories with mechanically replaceable hologram plates featuring very fast (less than 2 microsec) random access to large (greater than 100 million bit) data blocks and very high throughput (greater than 500 Mbit/sec). Using volume holographic storage it may eventually be possible to realize random-access mass memories which require no mechanical motion and yet provide very high capacity.

Low power consumption resistance random access memory with Pt/InOx/TiN structure

NASA Astrophysics Data System (ADS)

Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.; Tsai, Ming-Jinn

2013-09-01

In this study, the resistance switching characteristics of a resistive random access memory device with Pt/InOx/TiN structure is investigated. Unstable bipolar switching behavior is observed during the initial switching cycle, which then stabilizes after several switching cycles. Analyses indicate that the current conduction mechanism in the resistance state is dominated by Ohmic conduction. The decrease in electrical conductance can be attributed to the reduction of the cross-sectional area of the conduction path. Furthermore, the device exhibits low operation voltage and power consumption.

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

NASA Astrophysics Data System (ADS)

Mizutani, Tomoko; Takeuchi, Kiyoshi; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-04-01

We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

NASA Astrophysics Data System (ADS)

Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2014-01-01

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

NASA Astrophysics Data System (ADS)

Natsui, Masanori; Hanyu, Takahiro

2018-04-01

In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

NASA Astrophysics Data System (ADS)

Sawada, Takuya; Takata, Hidehiro; Nii, Koji; Nagata, Makoto

2013-04-01

Static random access memory (SRAM) cores exhibit susceptibility against power supply voltage variation. False operation is investigated among SRAM cells under sinusoidal voltage variation on power lines introduced by direct RF power injection. A standard SRAM core of 16 kbyte in a 90 nm 1.5 V technology is diagnosed with built-in self test and on-die noise monitor techniques. The sensitivity of bit error rate is shown to be high against the frequency of injected voltage variation, while it is not greatly influenced by the difference in frequency and phase against SRAM clocking. It is also observed that the distribution of false bits is substantially random in a cell array.

A random access memory immune to single event upset using a T-Resistor

DOEpatents

Ochoa, A. Jr.

1987-10-28

In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

Random access memory immune to single event upset using a T-resistor

DOEpatents

Ochoa, Jr., Agustin

1989-01-01

In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

Implementation of nitrogen-doped titanium-tungsten tunable heater in phase change random access memory and its effects on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tan, Chun Chia; Zhao, Rong, E-mail: zhao-rong@sutd.edu.sg; Chong, Tow Chong

2014-10-13

Nitrogen-doped titanium-tungsten (N-TiW) was proposed as a tunable heater in Phase Change Random Access Memory (PCRAM). By tuning N-TiW's material properties through doping, the heater can be tailored to optimize the access speed and programming current of PCRAM. Experiments reveal that N-TiW's resistivity increases and thermal conductivity decreases with increasing nitrogen-doping ratio, and N-TiW devices displayed (∼33% to ∼55%) reduced programming currents. However, there is a tradeoff between the current and speed for heater-based PCRAM. Analysis of devices with different N-TiW heaters shows that N-TiW doping levels could be optimized to enable low RESET currents and fast access speeds.

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

NASA Astrophysics Data System (ADS)

Shih, Yi-Hong; Hsu, Meng-Yin; King, Ya-Chin; Lin, Chrong Jung

2018-04-01

A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

Soft errors in commercial off-the-shelf static random access memories

NASA Astrophysics Data System (ADS)

Dilillo, L.; Tsiligiannis, G.; Gupta, V.; Bosser, A.; Saigne, F.; Wrobel, F.

2017-01-01

This article reviews state-of-the-art techniques for the evaluation of the effect of radiation on static random access memory (SRAM). We detailed irradiation test techniques and results from irradiation experiments with several types of particles. Two commercial SRAMs, in 90 and 65 nm technology nodes, were considered as case studies. Besides the basic static and dynamic test modes, advanced stimuli for the irradiation tests were introduced, as well as statistical post-processing techniques allowing for deeper analysis of the correlations between bit-flip cross-sections and design/architectural characteristics of the memory device. Further insight is provided on the response of irradiated stacked layer devices and on the use of characterized SRAM devices as particle detectors.

Aspects of GPU perfomance in algorithms with random memory access

NASA Astrophysics Data System (ADS)

Kashkovsky, Alexander V.; Shershnev, Anton A.; Vashchenkov, Pavel V.

2017-10-01

The numerical code for solving the Boltzmann equation on the hybrid computational cluster using the Direct Simulation Monte Carlo (DSMC) method showed that on Tesla K40 accelerators computational performance drops dramatically with increase of percentage of occupied GPU memory. Testing revealed that memory access time increases tens of times after certain critical percentage of memory is occupied. Moreover, it seems to be the common problem of all NVidia's GPUs arising from its architecture. Few modifications of the numerical algorithm were suggested to overcome this problem. One of them, based on the splitting the memory into "virtual" blocks, resulted in 2.5 times speed up.

Long-term reliable physically unclonable function based on oxide tunnel barrier breakdown on two-transistors two-magnetic-tunnel-junctions cell-based embedded spin transfer torque magnetoresistive random access memory

NASA Astrophysics Data System (ADS)

Takaya, Satoshi; Tanamoto, Tetsufumi; Noguchi, Hiroki; Ikegami, Kazutaka; Abe, Keiko; Fujita, Shinobu

2017-04-01

Among the diverse applications of spintronics, security for internet-of-things (IoT) devices is one of the most important. A physically unclonable function (PUF) with a spin device (spin transfer torque magnetoresistive random access memory, STT-MRAM) is presented. Oxide tunnel barrier breakdown is used to realize long-term stability for PUFs. A secure PUF has been confirmed by evaluating the Hamming distance of a 32-bit STT-MRAM-PUF fabricated using 65 nm CMOS technology.

Enhancement of Speed Margins for 16× Digital Versatile Disc-Random Access Memory

NASA Astrophysics Data System (ADS)

Watanabe, Koichi; Minemura, Hiroyuki; Miyamoto, Makoto; Iimura, Makoto

2006-02-01

We have evaluated the speed margins of write/read 16× digital versatile disc-random access memory (DVD-RAM) test discs using write strategies for 6--16× constant angular velocity (CAV) control. Our approach is to determine the writing parameters for the middle zones by interpolating the zone numbers. Using this interpolation strategy, we successfully obtained overwrite jitter values of less than 8% and bit error rates of less than 10-5 in 6--16× DVD-RAM. Moreover, we confirmed that the speed margins were ± 20% for a 6--16× CAV.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Conceptual design and feasibility evaluation model of a 10 to the 8th power bit oligatomic mass memory. Volume 1: Conceptual design

NASA Technical Reports Server (NTRS)

Recksiedler, A. L.; Lutes, C. L.

1972-01-01

The oligatomic (mirror) thin film memory technology is a suitable candidate for general purpose spaceborne applications in the post-1975 time frame. Capacities of around 10 to the 8th power bits can be reliably implemented with systems designed around a 335 million bit module. The recommended mode was determined following an investigation of implementation sizes ranging from an 8,000,000 to 100,000,000 bits per module. Cost, power, weight, volume, reliability, maintainability and speed were investigated. The memory includes random access, NDRO, SEC-DED, nonvolatility, and dual interface characteristics. The applications most suitable for the technology are those involving a large capacity with high speed (no latency), nonvolatility, and random accessing.

Set statistics in conductive bridge random access memory device with Cu/HfO{sub 2}/Pt structure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Meiyun; Long, Shibing, E-mail: longshibing@ime.ac.cn; Wang, Guoming

2014-11-10

The switching parameter variation of resistive switching memory is one of the most important challenges in its application. In this letter, we have studied the set statistics of conductive bridge random access memory with a Cu/HfO{sub 2}/Pt structure. The experimental distributions of the set parameters in several off resistance ranges are shown to nicely fit a Weibull model. The Weibull slopes of the set voltage and current increase and decrease logarithmically with off resistance, respectively. This experimental behavior is perfectly captured by a Monte Carlo simulator based on the cell-based set voltage statistics model and the Quantum Point Contact electronmore » transport model. Our work provides indications for the improvement of the switching uniformity.« less

High-density magnetoresistive random access memory operating at ultralow voltage at room temperature.

PubMed

Hu, Jia-Mian; Li, Zheng; Chen, Long-Qing; Nan, Ce-Wen

2011-11-22

The main bottlenecks limiting the practical applications of current magnetoresistive random access memory (MRAM) technology are its low storage density and high writing energy consumption. Although a number of proposals have been reported for voltage-controlled memory device in recent years, none of them simultaneously satisfy the important device attributes: high storage capacity, low power consumption and room temperature operation. Here we present, using phase-field simulations, a simple and new pathway towards high-performance MRAMs that display significant improvements over existing MRAM technologies or proposed concepts. The proposed nanoscale MRAM device simultaneously exhibits ultrahigh storage capacity of up to 88 Gb inch(-2), ultralow power dissipation as low as 0.16 fJ per bit and room temperature high-speed operation below 10 ns.

High-density magnetoresistive random access memory operating at ultralow voltage at room temperature

PubMed Central

Hu, Jia-Mian; Li, Zheng; Chen, Long-Qing; Nan, Ce-Wen

2011-01-01

The main bottlenecks limiting the practical applications of current magnetoresistive random access memory (MRAM) technology are its low storage density and high writing energy consumption. Although a number of proposals have been reported for voltage-controlled memory device in recent years, none of them simultaneously satisfy the important device attributes: high storage capacity, low power consumption and room temperature operation. Here we present, using phase-field simulations, a simple and new pathway towards high-performance MRAMs that display significant improvements over existing MRAM technologies or proposed concepts. The proposed nanoscale MRAM device simultaneously exhibits ultrahigh storage capacity of up to 88 Gb inch−2, ultralow power dissipation as low as 0.16 fJ per bit and room temperature high-speed operation below 10 ns. PMID:22109527

Ames Lab 101: Ultrafast Magnetic Switching

ScienceCinema

Wang; Jigang

2018-01-01

Ames Laboratory physicists have found a new way to switch magnetism that is at least 1000 times faster than currently used in magnetic memory technologies. Magnetic switching is used to encode information in hard drives, magnetic random access memory and other computing devices. The discovery potentially opens the door to terahertz and faster memory speeds.

Soft-error tolerance and energy consumption evaluation of embedded computer with magnetic random access memory in practical systems using computer simulations

NASA Astrophysics Data System (ADS)

Nebashi, Ryusuke; Sakimura, Noboru; Sugibayashi, Tadahiko

2017-08-01

We evaluated the soft-error tolerance and energy consumption of an embedded computer with magnetic random access memory (MRAM) using two computer simulators. One is a central processing unit (CPU) simulator of a typical embedded computer system. We simulated the radiation-induced single-event-upset (SEU) probability in a spin-transfer-torque MRAM cell and also the failure rate of a typical embedded computer due to its main memory SEU error. The other is a delay tolerant network (DTN) system simulator. It simulates the power dissipation of wireless sensor network nodes of the system using a revised CPU simulator and a network simulator. We demonstrated that the SEU effect on the embedded computer with 1 Gbit MRAM-based working memory is less than 1 failure in time (FIT). We also demonstrated that the energy consumption of the DTN sensor node with MRAM-based working memory can be reduced to 1/11. These results indicate that MRAM-based working memory enhances the disaster tolerance of embedded computers.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Microcontroller for automation application

NASA Technical Reports Server (NTRS)

Cooper, H. W.

1975-01-01

The description of a microcontroller currently being developed for automation application was given. It is basically an 8-bit microcomputer with a 40K byte random access memory/read only memory, and can control a maximum of 12 devices through standard 15-line interface ports.

An amorphous titanium dioxide metal insulator metal selector device for resistive random access memory crossbar arrays with tunable voltage margin

NASA Astrophysics Data System (ADS)

Cortese, Simone; Khiat, Ali; Carta, Daniela; Light, Mark E.; Prodromakis, Themistoklis

2016-01-01

Resistive random access memory (ReRAM) crossbar arrays have become one of the most promising candidates for next-generation non volatile memories. To become a mature technology, the sneak path current issue must be solved without compromising all the advantages that crossbars offer in terms of electrical performances and fabrication complexity. Here, we present a highly integrable access device based on nickel and sub-stoichiometric amorphous titanium dioxide (TiO2-x), in a metal insulator metal crossbar structure. The high voltage margin of 3 V, amongst the highest reported for monolayer selector devices, and the good current density of 104 A/cm2 make it suitable to sustain ReRAM read and write operations, effectively tackling sneak currents in crossbars without compromising fabrication complexity in a 1 Selector 1 Resistor (1S1R) architecture. Furthermore, the voltage margin is found to be tunable by an annealing step without affecting the device's characteristics.

Unexpected surface implanted layer in static random access memory devices observed by microwave impedance microscope

NASA Astrophysics Data System (ADS)

Kundhikanjana, W.; Yang, Y.; Tanga, Q.; Zhang, K.; Lai, K.; Ma, Y.; Kelly, M. A.; Li, X. X.; Shen, Z.-X.

2013-02-01

Real-space mapping of doping concentration in semiconductor devices is of great importance for the microelectronics industry. In this work, a scanning microwave impedance microscope (MIM) is employed to resolve the local conductivity distribution of a static random access memory sample. The MIM electronics can also be adjusted to the scanning capacitance microscopy (SCM) mode, allowing both measurements on the same region. Interestingly, while the conventional SCM images match the nominal device structure, the MIM results display certain unexpected features, which originate from a thin layer of the dopant ions penetrating through the protective layers during the heavy implantation steps.

Hydrogen doping in HfO{sub 2} resistance change random access memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Duncan, D.; Magyari-Köpe, B.; Nishi, Y.

2016-01-25

The structures and energies of hydrogen-doped monoclinic hafnium dioxide were calculated using density-functional theory. The electronic interactions are described within the LDA + U formalism, where on-site Coulomb corrections are applied to the 5d orbital electrons of Hf atoms and 2p orbital electrons of the O atoms. The effects of charge state, defect-defect interactions, and hydrogenation are investigated and compared with experiment. It is found that hydrogenation of HfO{sub 2} resistance-change random access memory devices energetically stabilizes the formation of oxygen vacancies and conductive vacancy filaments through multiple mechanisms, leading to improved switching characteristic and device yield.

A stochastic simulation method for the assessment of resistive random access memory retention reliability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berco, Dan, E-mail: danny.barkan@gmail.com; Tseng, Tseung-Yuen, E-mail: tseng@cc.nctu.edu.tw

This study presents an evaluation method for resistive random access memory retention reliability based on the Metropolis Monte Carlo algorithm and Gibbs free energy. The method, which does not rely on a time evolution, provides an extremely efficient way to compare the relative retention properties of metal-insulator-metal structures. It requires a small number of iterations and may be used for statistical analysis. The presented approach is used to compare the relative robustness of a single layer ZrO{sub 2} device with a double layer ZnO/ZrO{sub 2} one, and obtain results which are in good agreement with experimental data.

More than a feeling: Emotional cues impact the access and experience of autobiographical memories.

PubMed

Sheldon, Signy; Donahue, Julia

2017-07-01

Remembering is impacted by several factors of retrieval, including the emotional content of a memory cue. Here we tested how musical retrieval cues that differed on two dimensions of emotion-valence (positive and negative) and arousal (high and low)-impacted the following aspects of autobiographical memory recall: the response time to access a past personal event, the experience of remembering (ratings of memory vividness), the emotional content of a cued memory (ratings of event arousal and valence), and the type of event recalled (ratings of event energy, socialness, and uniqueness). We further explored how cue presentation affected autobiographical memory retrieval by administering cues of similar arousal and valence levels in a blocked fashion to one half of the tested participants, and randomly to the other half. We report three main findings. First, memories were accessed most quickly in response to musical cues that were highly arousing and positive in emotion. Second, we observed a relation between a cue and the elicited memory's emotional valence but not arousal; however, both the cue valence and arousal related to the nature of the recalled event. Specifically, high cue arousal led to lower memory vividness and uniqueness ratings, but cues with both high arousal and positive valence were associated with memories rated as more social and energetic. Finally, cue presentation impacted both how quickly and specifically memories were accessed and how cue valence affected the memory vividness ratings. The implications of these findings for views of how emotion directs the access to memories and the experience of remembering are discussed.

Active non-volatile memory post-processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

Cost aware cache replacement policy in shared last-level cache for hybrid memory based fog computing

NASA Astrophysics Data System (ADS)

Jia, Gangyong; Han, Guangjie; Wang, Hao; Wang, Feng

2018-04-01

Fog computing requires a large main memory capacity to decrease latency and increase the Quality of Service (QoS). However, dynamic random access memory (DRAM), the commonly used random access memory, cannot be included into a fog computing system due to its high consumption of power. In recent years, non-volatile memories (NVM) such as Phase-Change Memory (PCM) and Spin-transfer torque RAM (STT-RAM) with their low power consumption have emerged to replace DRAM. Moreover, the currently proposed hybrid main memory, consisting of both DRAM and NVM, have shown promising advantages in terms of scalability and power consumption. However, the drawbacks of NVM, such as long read/write latency give rise to potential problems leading to asymmetric cache misses in the hybrid main memory. Current last level cache (LLC) policies are based on the unified miss cost, and result in poor performance in LLC and add to the cost of using NVM. In order to minimize the cache miss cost in the hybrid main memory, we propose a cost aware cache replacement policy (CACRP) that reduces the number of cache misses from NVM and improves the cache performance for a hybrid memory system. Experimental results show that our CACRP behaves better in LLC performance, improving performance up to 43.6% (15.5% on average) compared to LRU.

Empirical Modeling Of Single-Event Upset

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.; Smith, Lawrence S.; Soli, George A.; Thieberger, Peter; Smith, Stephen L.; Atwood, Gregory E.

1988-01-01

Experimental study presents examples of empirical modeling of single-event upset in negatively-doped-source/drain metal-oxide-semiconductor static random-access memory cells. Data supports adoption of simplified worst-case model in which cross sectionof SEU by ion above threshold energy equals area of memory cell.

Ga-doped indium oxide nanowire phase change random access memory cells

NASA Astrophysics Data System (ADS)

Jin, Bo; Lim, Taekyung; Ju, Sanghyun; Latypov, Marat I.; Kim, Hyoung Seop; Meyyappan, M.; Lee, Jeong-Soo

2014-02-01

Phase change random access memory (PCRAM) devices are usually constructed using tellurium based compounds, but efforts to seek other materials providing desirable memory characteristics have continued. We have fabricated PCRAM devices using Ga-doped In2O3 nanowires with three different Ga compositions (Ga/(In+Ga) atomic ratio: 2.1%, 11.5% and 13.0%), and investigated their phase switching properties. The nanowires (˜40 nm in diameter) can be repeatedly switched between crystalline and amorphous phases, and Ga concentration-dependent memory switching behavior in the nanowires was observed with ultra-fast set/reset rates of 80 ns/20 ns, which are faster than for other competitive phase change materials. The observations of fast set/reset rates and two distinct states with a difference in resistance of two to three orders of magnitude appear promising for nonvolatile information storage. Moreover, we found that increasing the Ga concentration can reduce the power consumption and resistance drift; however, too high a level of Ga doping may cause difficulty in achieving the phase transition.

SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

NASA Astrophysics Data System (ADS)

Choi, Shinhyun; Tan, Scott H.; Li, Zefan; Kim, Yunjo; Choi, Chanyeol; Chen, Pai-Yu; Yeon, Hanwool; Yu, Shimeng; Kim, Jeehwan

2018-01-01

Although several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on—formation of filaments in an amorphous medium—is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.

The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7

NASA Astrophysics Data System (ADS)

Appeltans, Raf; Weckx, Pieter; Raghavan, Praveen; Kim, Ryoung-Han; Kar, Gouri Sankar; Furnémont, Arnaud; Van der Perre, Liesbet; Dehaene, Wim

2017-03-01

Static Random Access Memory (SRAM) cells are used together with logic standard cells as the benchmark to develop the process flow for new logic technologies. In order to achieve successful integration of Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as area efficient higher level embedded cache, it also needs to be included as a benchmark. The simple cell structure of STT-MRAM brings extra patterning challenges to achieve high density. The two memory types are compared in terms of minimum area and critical design rules in both the iN10 and iN7 node, with an extra focus on patterning options in iN7. Both the use of Self-Aligned Quadruple Patterning (SAQP) mandrel and spacer engineering, as well as multi-level via's are explored. These patterning options result in large area gains for the STT-MRAM cell and moreover determine which cell variant is the smallest.

On the mechanisms of cation injection in conducting bridge memories: The case of HfO{sub 2} in contact with noble metal anodes (Au, Cu, Ag)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saadi, M.; CNRS, LTM, F-38000 Grenoble; El Manar University, LMOP, 2092 Tunis

Resistance switching is studied in HfO{sub 2} as a function of the anode metal (Au, Cu, and Ag) in view of its application to resistive memories (resistive random access memories, RRAM). Current-voltage (I-V) and current-time (I-t) characteristics are presented. For Au anodes, resistance transition is controlled by oxygen vacancies (oxygen-based resistive random access memory, OxRRAM). For Ag anodes, resistance switching is governed by cation injection (Conducting Bridge random access memory, CBRAM). Cu anodes lead to an intermediate case. I-t experiments are shown to be a valuable tool to distinguish between OxRRAM and CBRAM behaviors. A model is proposed to explainmore » the high-to-low resistance transition in CBRAMs. The model is based on the theory of low-temperature oxidation of metals (Cabrera-Mott theory). Upon electron injection, oxygen vacancies and oxygen ions are generated in the oxide. Oxygen ions are drifted to the anode, and an interfacial oxide is formed at the HfO{sub 2}/anode interface. If oxygen ion mobility is low in the interfacial oxide, a negative space charge builds-up at the HfO{sub 2}/oxide interface. This negative space charge is the source of a strong electric field across the interfacial oxide thickness, which pulls out cations from the anode (CBRAM case). Inversely, if oxygen ions migration through the interfacial oxide is important (or if the anode does not oxidize such as Au), bulk oxygen vacancies govern resistance transition (OxRRAM case).« less

Plated wire memory subsystem

NASA Technical Reports Server (NTRS)

Reynolds, L.; Tweed, H.

1972-01-01

The work performed entailed the design, development, construction and testing of a 4000 word by 18 bit random access, NDRO plated wire memory for use in conjunction with a spacecraft imput/output unit and central processing unit. The primary design parameters, in order of importance, were high reliability, low power, volume and weight. A single memory unit, referred to as a qualification model, was delivered.

Particle sensor array

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor); Blaes, Brent R. (Inventor); Lieneweg, Udo (Inventor)

1994-01-01

A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.

Eight microprocessor-based instrument data systems in the Galileo Orbiter spacecraft

NASA Technical Reports Server (NTRS)

Barry, R. C.

1980-01-01

Instrument data systems consist of a microprocessor, 3K bytes of Read Only Memory and 3K bytes of Random Access Memory. It interfaces with the spacecraft data bus through an isolated user interface with a direct memory access bus adaptor, and/or parallel data from instrument devices such as registers, buffers, analog to digital converters, multiplexers, and solid state sensors. These data systems support the spacecraft hardware and software communication protocol, decode and process instrument commands, generate continuous instrument operating modes, control the instrument mechanisms, acquire, process, format, and output instrument science data.

A Hardware Platform for Characterizing and Validating 1-Dimensional Optical Systems

DTIC Science & Technology

2014-09-01

principle laboratory experiments, a bread -board sensor and data collection system was created to gather fuze data to postprocess after the event...merely differentiates this bistable memory category from dynamic random access memory [RAM], which must be periodically refreshed to retain data.) A

Non-Volatile Memory Technology Symposium 2001: Proceedings

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Daud, Taher; Strauss, Karl

2001-01-01

This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2001 that was held on November 7-8, 2001 in San Diego, CA. The proceedings contains a a wide range of papers that cover current and new memory technologies including Flash memories, Magnetic Random Access Memories (MRAM and GMRAM), Ferro-electric RAM (FeRAM), and Chalcogenide RAM (CRAM). The papers presented in the proceedings address the use of these technologies for space applications as well as radiation effects and packaging issues.

Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array.

PubMed

Zhou, Ya-Xiong; Li, Yi; Su, Yu-Ting; Wang, Zhuo-Rui; Shih, Ling-Yi; Chang, Ting-Chang; Chang, Kuan-Chang; Long, Shi-Bing; Sze, Simon M; Miao, Xiang-Shui

2017-05-25

Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO 2 -based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

Dynamics of the stress-mediated magnetoelectric memory cell N×(TbCo2/FeCo)/PMN-PT

NASA Astrophysics Data System (ADS)

Preobrazhensky, Vladimir; Klimov, Alexey; Tiercelin, Nicolas; Dusch, Yannick; Giordano, Stefano; Churbanov, Anton; Mathurin, Theo; Pernod, Philippe; Sigov, Alexander

2018-08-01

Stress-mediated magnetoelectric heterostructures represent a very promising approach for the realization of ultra-low energy Random Access Memories. The magnetoelectric writing of information has been extensively studied in the past, but it was demonstrated only recently that the magnetoelectric effect can also provide means for reading the stored information. We hereby theoretically study the dynamic behaviour of a magnetoelectric random access memory cell (MELRAM) typically composed of a magnetostrictive multilayer N × (TbCo2 / FeCo) that is elastically coupled with a 〈0 1 1〉 PMN-PT ferroelectric crystal and placed in a Wheatstone bridge-like configuration. The numerical resolution of the LLG and electrodynamics equation system demonstrates high speed write and read operations with an associated extra-low energy consumption. In this model, the reading energy for a 50 nm cell size is estimated to be less than 5 aJ/bit.

Single Event Upset in Static Random Access Memories in Atmospheric Neutron Environments

NASA Astrophysics Data System (ADS)

Arita, Yutaka; Takai, Mikio; Ogawa, Izumi; Kishimoto, Tadafumi

2003-07-01

Single-event upsets (SEUs) in a 0.4 μm 4 Mbit complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) were investigated in various atmospheric neutron environments at sea level, at an altitude of 2612 m mountain, at an altitude of commercial airplane, and at an underground depth of 476 m. Neutron-induced SEUs increase with the increase in altitude. For a device with a borophosphosilicate glass (BPSG) film, SEU rates induced by thermal neutrons increase with the decrease in the cell charge of a memory cell. A thermal neutron-induced SEU is significant in SRAMs with a small cell charge. With the conditions of small cell charge, thermal neutron-induced SEUs account for 60% or more of the total neutron-induced SEUs. The SEU rate induced by atmospheric thermal neutrons can be estimated by an acceleration test using 252Cf.

Quantifying data retention of perpendicular spin-transfer-torque magnetic random access memory chips using an effective thermal stability factor method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Thomas, Luc, E-mail: luc.thomas@headway.com; Jan, Guenole; Le, Son

The thermal stability of perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) devices is investigated at chip level. Experimental data are analyzed in the framework of the Néel-Brown model including distributions of the thermal stability factor Δ. We show that in the low error rate regime important for applications, the effect of distributions of Δ can be described by a single quantity, the effective thermal stability factor Δ{sub eff}, which encompasses both the median and the standard deviation of the distributions. Data retention of memory chips can be assessed accurately by measuring Δ{sub eff} as a function of device diameter andmore » temperature. We apply this method to show that 54 nm devices based on our perpendicular STT-MRAM design meet our 10 year data retention target up to 120 °C.« less

Sub-1-V-60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

NASA Astrophysics Data System (ADS)

Ogasawara, Ryosuke; Endoh, Tetsuo

2018-04-01

In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

Implementation of Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.; Kamp, David A.; Isaacson, Alan F.

2000-01-01

Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications.

32-Bit-Wide Memory Tolerates Failures

NASA Technical Reports Server (NTRS)

Buskirk, Glenn A.

1990-01-01

Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

Rutger's CAM2000 chip architecture

NASA Technical Reports Server (NTRS)

Smith, Donald E.; Hall, J. Storrs; Miyake, Keith

1993-01-01

This report describes the architecture and instruction set of the Rutgers CAM2000 memory chip. The CAM2000 combines features of Associative Processing (AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying simple massively parallel operations to memory. This document reflects the current status of the CAM2000 architecture and is continually updated to reflect the current state of the architecture and instruction set.

Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

DOEpatents

Blocksome, Michael A.; Mamidala, Amith R.

2013-09-03

Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

DOEpatents

Blocksome, Michael A; Mamidala, Amith R

2014-02-11

Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

The storage system of PCM based on random access file system

NASA Astrophysics Data System (ADS)

Han, Wenbing; Chen, Xiaogang; Zhou, Mi; Li, Shunfen; Li, Gezi; Song, Zhitang

2016-10-01

Emerging memory technologies such as Phase change memory (PCM) tend to offer fast, random access to persistent storage with better scalability. It's a hot topic of academic and industrial research to establish PCM in storage hierarchy to narrow the performance gap. However, the existing file systems do not perform well with the emerging PCM storage, which access storage medium via a slow, block-based interface. In this paper, we propose a novel file system, RAFS, to bring about good performance of PCM, which is built in the embedded platform. We attach PCM chips to the memory bus and build RAFS on the physical address space. In the proposed file system, we simplify traditional system architecture to eliminate block-related operations and layers. Furthermore, we adopt memory mapping and bypassed page cache to reduce copy overhead between the process address space and storage device. XIP mechanisms are also supported in RAFS. To the best of our knowledge, we are among the first to implement file system on real PCM chips. We have analyzed and evaluated its performance with IOZONE benchmark tools. Our experimental results show that the RAFS on PCM outperforms Ext4fs on SDRAM with small record lengths. Based on DRAM, RAFS is significantly faster than Ext4fs by 18% to 250%.

Spin-transfer-torque efficiency enhanced by edge-damage of perpendicular magnetic random access memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Song, Kyungmi; Lee, Kyung-Jin, E-mail: kj-lee@korea.ac.kr; Department of Materials Science and Engineering, Korea University, Seoul 136-713

2015-08-07

We numerically investigate the effect of magnetic and electrical damages at the edge of a perpendicular magnetic random access memory (MRAM) cell on the spin-transfer-torque (STT) efficiency that is defined by the ratio of thermal stability factor to switching current. We find that the switching mode of an edge-damaged cell is different from that of an undamaged cell, which results in a sizable reduction in the switching current. Together with a marginal reduction of the thermal stability factor of an edge-damaged cell, this feature makes the STT efficiency large. Our results suggest that a precise edge control is viable formore » the optimization of STT-MRAM.« less

Multi-step resistive switching behavior of Li-doped ZnO resistance random access memory device controlled by compliance current

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lin, Chun-Cheng; Department of Mathematic and Physical Sciences, R.O.C. Air Force Academy, Kaohsiung 820, Taiwan; Tang, Jian-Fu

2016-06-28

The multi-step resistive switching (RS) behavior of a unipolar Pt/Li{sub 0.06}Zn{sub 0.94}O/Pt resistive random access memory (RRAM) device is investigated. It is found that the RRAM device exhibits normal, 2-, 3-, and 4-step RESET behaviors under different compliance currents. The transport mechanism within the device is investigated by means of current-voltage curves, in-situ transmission electron microscopy, and electrochemical impedance spectroscopy. It is shown that the ion transport mechanism is dominated by Ohmic behavior under low electric fields and the Poole-Frenkel emission effect (normal RS behavior) or Li{sup +} ion diffusion (2-, 3-, and 4-step RESET behaviors) under high electric fields.

Comparison and statistical analysis of four write stability metrics in bulk CMOS static random access memory cells

NASA Astrophysics Data System (ADS)

Qiu, Hao; Mizutani, Tomoko; Saraya, Takuya; Hiramoto, Toshiro

2015-04-01

The commonly used four metrics for write stability were measured and compared based on the same set of 2048 (2k) six-transistor (6T) static random access memory (SRAM) cells by the 65 nm bulk technology. The preferred one should be effective for yield estimation and help predict edge of stability. Results have demonstrated that all metrics share the same worst SRAM cell. On the other hand, compared to butterfly curve with non-normality and write N-curve where no cell state flip happens, bit-line and word-line margins have good normality as well as almost perfect correlation. As a result, both bit line method and word line method prove themselves preferred write stability metrics.

Parallel Optical Random Access Memory (PORAM)

NASA Technical Reports Server (NTRS)

Alphonse, G. A.

1989-01-01

It is shown that the need to minimize component count, power and size, and to maximize packing density require a parallel optical random access memory to be designed in a two-level hierarchy: a modular level and an interconnect level. Three module designs are proposed, in the order of research and development requirements. The first uses state-of-the-art components, including individually addressed laser diode arrays, acousto-optic (AO) deflectors and magneto-optic (MO) storage medium, aimed at moderate size, moderate power, and high packing density. The next design level uses an electron-trapping (ET) medium to reduce optical power requirements. The third design uses a beam-steering grating surface emitter (GSE) array to reduce size further and minimize the number of components.

Ferroelectric tunneling element and memory applications which utilize the tunneling element

DOEpatents

Kalinin, Sergei V [Knoxville, TN; Christen, Hans M [Knoxville, TN; Baddorf, Arthur P [Knoxville, TN; Meunier, Vincent [Knoxville, TN; Lee, Ho Nyung [Oak Ridge, TN

2010-07-20

A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when the tunneling element is below the Curie temperature of the layer of ferroelectric material. The element can be used as a basis of compact 1R type non-volatile random access memory (RAM). The advantages include extremely simple architecture, ultimate scalability and fast access times generic for all ferroelectric memories.

Deviation from the law of energy equipartition in a small dynamic-random-access memory

NASA Astrophysics Data System (ADS)

Carles, Pierre-Alix; Nishiguchi, Katsuhiko; Fujiwara, Akira

2015-06-01

A small dynamic-random-access memory (DRAM) coupled with a high charge sensitivity electrometer based on a silicon field-effect transistor is used to study the law of equipartition of energy. By statistically analyzing the movement of single electrons in the DRAM at various temperature and voltage conditions in thermal equilibrium, we are able to observe a behavior that differs from what is predicted by the law of equipartition energy: when the charging energy of the capacitor of the DRAM is comparable to or smaller than the thermal energy kBT/2, random electron motion is ruled perfectly by thermal energy; on the other hand, when the charging energy becomes higher in relation to the thermal energy kBT/2, random electron motion is suppressed which indicates a deviation from the law of equipartition of energy. Since the law of equipartition is analyzed using the DRAM, one of the most familiar devices, we believe that our results are perfectly universal among all electronic devices.

Low-power resistive random access memory by confining the formation of conducting filaments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang, Yi-Jen; Lee, Si-Chen, E-mail: sclee@ntu.edu.tw; Shen, Tzu-Hsien

2016-06-15

Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiO{sub x}/silver nanoparticles/TiO{sub x}/AlTiO{sub x}, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistancemore » state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiO{sub x} layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.« less

Spin-transfer torque switched magnetic tunnel junctions in magnetic random access memory

NASA Astrophysics Data System (ADS)

Sun, Jonathan Z.

2016-10-01

Spin-transfer torque (or spin-torque, or STT) based magnetic tunnel junction (MTJ) is at the heart of a new generation of magnetism-based solid-state memory, the so-called spin-transfer-torque magnetic random access memory, or STT-MRAM. Over the past decades, STT-based switchable magnetic tunnel junction has seen progress on many fronts, including the discovery of (001) MgO as the most favored tunnel barrier, which together with (bcc) Fe or FeCo alloy are yielding best demonstrated tunnel magneto-resistance (TMR); the development of perpendicularly magnetized ultrathin CoFeB-type of thin films sufficient to support high density memories with junction sizes demonstrated down to 11nm in diameter; and record-low spin-torque switching threshold current, giving best reported switching efficiency over 5 kBT/μA. Here we review the basic device properties focusing on the perpendicularly magnetized MTJs, both in terms of switching efficiency as measured by sub-threshold, quasi-static methods, and of switching speed at super-threshold, forced switching. We focus on device behaviors important for memory applications that are rooted in fundamental device physics, which highlights the trade-off of device parameters for best suitable system integration.

Effect of embedded metal nanocrystals on the resistive switching characteristics in NiN-based resistive random access memory cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yun, Min Ju; Kim, Hee-Dong; Man Hong, Seok

2014-03-07

The metal nanocrystals (NCs) embedded-NiN-based resistive random access memory cells are demonstrated using several metal NCs (i.e., Pt, Ni, and Ti) with different physical parameters in order to investigate the metal NC's dependence on resistive switching (RS) characteristics. First, depending on the electronegativity of metal, the size of metal NCs is determined and this affects the operating current of memory cells. If metal NCs with high electronegativity are incorporated, the size of the NCs is reduced; hence, the operating current is reduced owing to the reduced density of the electric field around the metal NCs. Second, the potential wells aremore » formed by the difference of work function between the metal NCs and active layer, and the barrier height of the potential wells affects the level of operating voltage as well as the conduction mechanism of metal NCs embedded memory cells. Therefore, by understanding these correlations between the active layer and embedded metal NCs, we can optimize the RS properties of metal NCs embedded memory cells as well as predict their conduction mechanisms.« less

Multilevel resistive information storage and retrieval

DOEpatents

Lohn, Andrew; Mickel, Patrick R.

2016-08-09

The present invention relates to resistive random-access memory (RRAM or ReRAM) systems, as well as methods of employing multiple state variables to form degenerate states in such memory systems. The methods herein allow for precise write and read steps to form multiple state variables, and these steps can be performed electrically. Such an approach allows for multilevel, high density memory systems with enhanced information storage capacity and simplified information retrieval.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Plated wire memory subsystem

NASA Technical Reports Server (NTRS)

Carpenter, K. H.

1974-01-01

The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.

Kanerva's sparse distributed memory: An associative memory algorithm well-suited to the Connection Machine

NASA Technical Reports Server (NTRS)

Rogers, David

1988-01-01

The advent of the Connection Machine profoundly changes the world of supercomputers. The highly nontraditional architecture makes possible the exploration of algorithms that were impractical for standard Von Neumann architectures. Sparse distributed memory (SDM) is an example of such an algorithm. Sparse distributed memory is a particularly simple and elegant formulation for an associative memory. The foundations for sparse distributed memory are described, and some simple examples of using the memory are presented. The relationship of sparse distributed memory to three important computational systems is shown: random-access memory, neural networks, and the cerebellum of the brain. Finally, the implementation of the algorithm for sparse distributed memory on the Connection Machine is discussed.

Optoelectronic-cache memory system architecture.

PubMed

Chiarulli, D M; Levitan, S P

1996-05-10

We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free-space optical input-output to-and-from optical memory with conventional electronic communication to the processor caches. This cache and the optical memory system to which it will interface provide a large random-access memory space that has a lower overall latency than that of magnetic disks and disk arrays. In addition, as a consequence of the high-bandwidth parallel input-output capabilities of optical memories, fault service times for the optoelectronic cache are substantially less than those currently achievable with any rotational media.

Dual representation of item positions in verbal short-term memory: Evidence for two access modes.

PubMed

Lange, Elke B; Verhaeghen, Paul; Cerella, John

Memory sets of N = 1~5 digits were exposed sequentially from left-to-right across the screen, followed by N recognition probes. Probes had to be compared to memory list items on identity only (Sternberg task) or conditional on list position. Positions were probed randomly or in left-to-right order. Search functions related probe response times to set size. Random probing led to ramped, "Sternbergian" functions whose intercepts were elevated by the location requirement. Sequential probing led to flat search functions-fast responses unaffected by set size. These results suggested that items in STM could be accessed either by a slow search-on-identity followed by recovery of an associated location tag, or in a single step by following item-to-item links in study order. It is argued that this dual coding of location information occurs spontaneously at study, and that either code can be utilised at retrieval depending on test demands.

Role of Al2O3 thin layer on improving the resistive switching properties of Ta5Si3-based conductive bridge random accesses memory device

NASA Astrophysics Data System (ADS)

Kumar, Dayanand; Aluguri, Rakesh; Chand, Umesh; Tseng, Tseung-Yuen

2018-04-01

Ta5Si3-based conductive bridge random access memory (CBRAM) devices have been investigated to improve their resistive switching characteristics for their application in future nonvolatile memory technology. Changes in the switching characteristics by the addition of a thin Al2O3 layer of different thicknesses at the bottom electrode interface of a Ta5Si3-based CBRAM devices have been studied. The double-layer device with a 1 nm Al2O3 layer has shown improved resistive switching characteristics over the single layer one with a high on/off resistance ratio of 102, high endurance of more than 104 cycles, and good retention for more than 105 s at the temperature of 130 °C. The higher thermal conductivity of Al2O3 over Ta5Si3 has been attributed to the enhanced switching properties of the double-layer devices.

Influence of Thermal Annealing Treatment on Bipolar Switching Properties of Vanadium Oxide Thin-Film Resistance Random-Access Memory Devices

NASA Astrophysics Data System (ADS)

Chen, Kai-Huang; Cheng, Chien-Min; Kao, Ming-Cheng; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Wu, Sean; Su, Feng-Yi

2017-04-01

The bipolar switching properties and electrical conduction mechanism of vanadium oxide thin-film resistive random-access memory (RRAM) devices obtained using a rapid thermal annealing (RTA) process have been investigated in high-resistive status/low-resistive status (HRS/LRS) and are discussed herein. In addition, the resistance switching properties and quality improvement of the vanadium oxide thin-film RRAM devices were measured by x-ray diffraction (XRD) analysis, x-ray photoelectron spectrometry (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM), and current-voltage ( I- V) measurements. The activation energy of the hopping conduction mechanism in the devices was investigated based on Arrhenius plots in HRS and LRS. The hopping conduction distance and activation energy barrier were obtained as 12 nm and 45 meV, respectively. The thermal annealing process is recognized as a candidate method for fabrication of thin-film RRAM devices, being compatible with integrated circuit technology for nonvolatile memory devices.

Plastic Deformation and Failure Analysis of Phase Change Random Access Memory

NASA Astrophysics Data System (ADS)

Yang; Hongxin; Shi; Luping; Lee; Koon, Hock; Zhao; Rong; Li; Jianming; Lim; Guan, Kian; Chong; Chong, Tow

2009-04-01

Although lateral phase change random access memory (PCRAM) has attracted a lot of interest due to its simpler fabrication process and lower current compared to ovonic unified memory (OUM), it faces a problem of poor lifetime. This paper studied relation between plastic deformation and the failure of PCRAM through both experiment and simulation. OUM and lateral PCRAM incorporating Ge2Sb2Te5 were fabricated and tested. The overwriting test showed that lifetime of OUM exceeded 106 while that of lateral PCRAM was only about 100. Using atomic force microscopy (AFM), it was found that the plastic deformation after 106 overwriting reached several tens of nm for lateral PCRAM while it was negligible for OUM. The thermo-mechanical simulation results confirmed the similar results on larger plastic deformation of lateral PCRAM than that of OUM during overwriting. As plastic deformation involves of atomic bonds breaking and reforming in phase change material, the plastic deformation may be one main reason for the failure of lateral PCRAM.

Influence of ultraviolet irradiation on data retention characteristics in resistive random access memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kimura, K.; Ohmi, K.; Tottori University Electronic Display Research Center, 101 Minami4-chome, Koyama-cho, Tottori-shi, Tottori 680-8551

With increasing density of memory devices, the issue of generating soft errors by cosmic rays is becoming more and more serious. Therefore, the irradiation resistance of resistance random access memory (ReRAM) to cosmic radiation has to be elucidated for practical use. In this paper, we investigated the data retention characteristics of ReRAM against ultraviolet irradiation with a Pt/NiO/ITO structure. Soft errors were confirmed to be caused by ultraviolet irradiation in both low- and high-resistance states. An analysis of the wavelength dependence of light irradiation on data retention characteristics suggested that electronic excitation from the valence to the conduction band andmore » to the energy level generated due to the introduction of oxygen vacancies caused the errors. Based on a statistically estimated soft error rates, the errors were suggested to be caused by the cohesion and dispersion of oxygen vacancies owing to the generation of electron-hole pairs and valence changes by the ultraviolet irradiation.« less

Random-access technique for modular bathymetry data storage in a continental shelf wave refraction program

NASA Technical Reports Server (NTRS)

Poole, L. R.

1974-01-01

A study was conducted of an alternate method for storage and use of bathymetry data in the Langley Research Center and Virginia Institute of Marine Science mid-Atlantic continental-shelf wave-refraction computer program. The regional bathymetry array was divided into 105 indexed modules which can be read individually into memory in a nonsequential manner from a peripheral file using special random-access subroutines. In running a sample refraction case, a 75-percent decrease in program field length was achieved by using the random-access storage method in comparison with the conventional method of total regional array storage. This field-length decrease was accompanied by a comparative 5-percent increase in central processing time and a 477-percent increase in the number of operating-system calls. A comparative Langley Research Center computer system cost savings of 68 percent was achieved by using the random-access storage method.

An energy efficient and high speed architecture for convolution computing based on binary resistive random access memory

NASA Astrophysics Data System (ADS)

Liu, Chen; Han, Runze; Zhou, Zheng; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

2018-04-01

In this work we present a novel convolution computing architecture based on metal oxide resistive random access memory (RRAM) to process the image data stored in the RRAM arrays. The proposed image storage architecture shows performances of better speed-device consumption efficiency compared with the previous kernel storage architecture. Further we improve the architecture for a high accuracy and low power computing by utilizing the binary storage and the series resistor. For a 28 × 28 image and 10 kernels with a size of 3 × 3, compared with the previous kernel storage approach, the newly proposed architecture shows excellent performances including: 1) almost 100% accuracy within 20% LRS variation and 90% HRS variation; 2) more than 67 times speed boost; 3) 71.4% energy saving.

Simulation of Voltage SET Operation in Phase-Change Random Access Memories with Heater Addition and Ring-Type Contactor for Low-Power Consumption by Finite Element Modeling

NASA Astrophysics Data System (ADS)

Gong, Yue-Feng; Song, Zhi-Tang; Ling, Yun; Liu, Yan; Li, Yi-Jin

2010-06-01

A three-dimensional finite element model for phase change random access memory is established to simulate electric, thermal and phase state distribution during (SET) operation. The model is applied to simulate the SET behaviors of the heater addition structure (HS) and the ring-type contact in the bottom electrode (RIB) structure. The simulation results indicate that the small bottom electrode contactor (BEC) is beneficial for heat efficiency and reliability in the HS cell, and the bottom electrode contactor with size Fx = 80 nm is a good choice for the RIB cell. Also shown is that the appropriate SET pulse time is 100 ns for the low power consumption and fast operation.

Simulation study on heat conduction of a nanoscale phase-change random access memory cell.

PubMed

Kim, Junho; Song, Ki-Bong

2006-11-01

We have investigated heat transfer characteristics of a nano-scale phase-change random access memory (PRAM) cell using finite element method (FEM) simulation. Our PRAM cell is based on ternary chalcogenide alloy, Ge2Sb2Te5 (GST), which is used as a recording layer. For contact area of 100 x 100 nm2, simulations of crystallization and amorphization processes were carried out. Physical quantities such as electric conductivity, thermal conductivity, and specific heat were treated as temperature-dependent parameters. Through many simulations, it is concluded that one can reduce set current by decreasing both electric conductivities of amorphous GST and crystalline GST, and in addition to these conditions by decreasing electric conductivity of molten GST one can also reduce reset current significantly.

Monitoring oxygen movement by Raman spectroscopy of resistive random access memory with a graphene-inserted electrode.

PubMed

Tian, He; Chen, Hong-Yu; Gao, Bin; Yu, Shimeng; Liang, Jiale; Yang, Yi; Xie, Dan; Kang, Jinfeng; Ren, Tian-Ling; Zhang, Yuegang; Wong, H-S Philip

2013-02-13

In this paper, we employed Ramen spectroscopy to monitor oxygen movement at the electrode/oxide interface by inserting single-layer graphene (SLG). Raman area mapping and single-point measurements show noticeable changes in the D-band, G-band, and 2D-band signals of the SLG during consecutive electrical programming repeated for nine cycles. In addition, the inserted SLG enables the reduction of RESET current by 22 times and programming power consumption by 47 times. Collectively, our results show that monitoring the oxygen movement by Raman spectroscopy for a resistive random access memory (RRAM) is made possible by inserting a single-layer graphene at electrode/oxide interface. This may open up an important analysis tool for investigation of switching mechanism of RRAM.

Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blocksome, Michael A.; Mamidala, Amith R.

2013-09-03

Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segmentmore » of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.« less

Organic Ferroelectric-Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half-Selection Problem.

PubMed

Zhao, Qiang; Wang, Hanlin; Ni, Zhenjie; Liu, Jie; Zhen, Yonggang; Zhang, Xiaotao; Jiang, Lang; Li, Rongjin; Dong, Huanli; Hu, Wenping

2017-09-01

Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF-TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low-cost and easy-fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half-selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm 2 V -1 s -1 (average) for 2,6-diphenylanthracene (DPA) and electron mobility of 0.124 cm 2 V -1 s -1 (average) for N,N'-1H,1H-perfluorobutyl dicyanoperylenecarboxydiimide (PDI-FCN 2 ) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric-based pixelated memory module fabrication. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and Implementation of an MC68020-Based Educational Computer Board

DTIC Science & Technology

1989-12-01

device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to initialize...MHz. It includes four * Static Random Access Memory (SRAM) chips which provide a storage of 32K bytes. Two Programmable Array Logic (PAL) chips...device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to

TiO2-based memristors and ReRAM: materials, mechanisms and models (a review)

NASA Astrophysics Data System (ADS)

Gale, Ella

2014-10-01

The memristor is the fundamental nonlinear circuit element, with uses in computing and computer memory. Resistive Random Access Memory (ReRAM) is a resistive switching memory proposed as a non-volatile memory. In this review we shall summarize the state of the art for these closely-related fields, concentrating on titanium dioxide, the well-utilized and archetypal material for both. We shall cover material properties, switching mechanisms and models to demonstrate what ReRAM and memristor scientists can learn from each other and examine the outlook for these technologies.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

50 CFR 660.15 - Equipment requirements.

Code of Federal Regulations, 2014 CFR

2014-10-01

... water, slime, mud, debris, or other materials. Scale printouts must show: (A) The vessel name and...; (ii) Random Access Memory (RAM): 256 megabytes (MB) or higher; (iii) Hard disk space: (A) If already...

50 CFR 660.15 - Equipment requirements.

Code of Federal Regulations, 2012 CFR

2012-10-01

... water, slime, mud, debris, or other materials. Scale printouts must show: (A) The vessel name and...; (ii) Random Access Memory (RAM): 256 megabytes (MB) or higher; (iii) Hard disk space: (A) If already...

50 CFR 660.15 - Equipment requirements.

Code of Federal Regulations, 2013 CFR

2013-10-01

... water, slime, mud, debris, or other materials. Scale printouts must show: (A) The vessel name and...; (ii) Random Access Memory (RAM): 256 megabytes (MB) or higher; (iii) Hard disk space: (A) If already...

77 FR 74222 - Certain Dynamic Random Access Memory and NAND Flash Memory Devices and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-12-13

..., California; Kingston Technology Co., Inc. of Fountain Valley, California; Logitek International S.A. (``LISA...: Clint Gerdine, Esq., Office of the General Counsel, U.S. International Trade Commission, 500 E Street SW....m. to 5:15 p.m.) in the Office of the Secretary, U.S. International Trade Commission, 500 E Street...

Gas-Sensing Flip-Flop Circuits

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Williams, Roger; Ryan, Margaret A.

1995-01-01

Gas-sensing integrated circuits consisting largely of modified static random-access memories (SRAMs) undergoing development, building on experience gained in use of modified SRAMs as radiation sensors. Each SRAM memory cell includes flip-flop circuit; sensors exploit metastable state that lies between two stable states (corresponding to binary logic states) of flip-flop circuit. Voltages of metastable states vary with exposures of gas-sensitive resistors.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Improved characteristics of amorphous indium-gallium-zinc-oxide-based resistive random access memory using hydrogen post-annealing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kang, Dae Yun; Lee, Tae-Ho; Kim, Tae Geun, E-mail: tgkim1@korea.ac.kr

The authors report an improvement in resistive switching (RS) characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO)-based resistive random access memory devices using hydrogen post-annealing. Because this a-IGZO thin film has oxygen off-stoichiometry in the form of deficient and excessive oxygen sites, the film properties can be improved by introducing hydrogen atoms through the annealing process. After hydrogen post-annealing, the device exhibited a stable bipolar RS, low-voltage set and reset operation, long retention (>10{sup 5 }s), good endurance (>10{sup 6} cycles), and a narrow distribution in each current state. The effect of hydrogen post-annealing is also investigated by analyzing the sample surface using X-raymore » photon spectroscopy and atomic force microscopy.« less

Elevated-Confined Phase-Change Random Access Memory Cells

NASA Astrophysics Data System (ADS)

Lee; Koon, Hock; Shi; Luping; Zhao; Rong; Yang; Hongxin; Lim; Guan, Kian; Li; Jianming; Chong; Chong, Tow

2010-04-01

A new elevated-confined phase-change random access memory (PCRAM) cell structure to reduce power consumption was proposed. In this proposed structure, the confined phase-change region is sitting on top of a small metal column enclosed by a dielectric at the sides. Hence, more heat can be effectively sustained underneath the phase-change region. As for the conventional structure, the confined phase-change region is sitting directly above a large planar bottom metal electrode, which can easily conduct most of the induced heat away. From simulations, a more uniform temperature profile around the active region and a higher peak temperature at the phase-change layer (PCL) in an elevated-confined structure were observed. Experimental results showed that the elevated-confined PCRAM cell requires a lower programming power and has a better scalability than a conventional confined PCRAM cell.

Electrical characteristics of paraelectric lead lanthanum zirconium titanate thin films for dynamic random access memory applications

NASA Astrophysics Data System (ADS)

Jones, R. E., Jr.; Maniar, P. D.; Olowolafe, J. O.; Campbell, A. C.; Mogab, C. J.

1992-02-01

Paraelectric lead lanthanum zirconium titanate (PLZT) films, 150 nm thick, were deposited using a spin-coat, sol-gel process followed by a 650 °C oxygen anneal. X-ray diffraction indicated complete conversion to the perovskite phase. Sputter-deposited platinum electrodes were employed with the PLZT films to form thin-film capacitors with the best combination of high charge storage density (26.1 μC/cm2 at 3 V and 36.4 μC/cm2 at 5 V) and leakage current density (0.2 μA/cm2 at 3 V and 0.5 μA/cm2 at 5 V ) reported to date. The electrical characteristics of these thin-film capacitors meet the requirements for a planar bit cell capacitor for 64-Mbit dynamic random access memories.

Multi-port, optically addressed RAM

NASA Technical Reports Server (NTRS)

Johnston, Alan R. (Inventor); Nixon, Robert H. (Inventor); Bergman, Larry A. (Inventor); Esener, Sadik (Inventor)

1989-01-01

A random access memory addressing system utilizing optical links between memory and the read/write logic circuits comprises addressing circuits including a plurality of light signal sources, a plurality of optical gates including optical detectors associated with the memory cells, and a holographic optical element adapted to reflect and direct the light signals to the desired memory cell locations. More particularly, it is a multi-port, binary computer memory for interfacing with a plurality of computers. There are a plurality of storage cells for containing bits of binary information, the storage cells being disposed at the intersections of a plurality of row conductors and a plurality of column conductors. There is interfacing logic for receiving information from the computers directing access to ones of the storage cells. There are first light sources associated with the interfacing logic for transmitting a first light beam with the access information modulated thereon. First light detectors are associated with the storage cells for receiving the first light beam, for generating an electrical signal containing the access information, and for conducting the electrical signal to the one of the storage cells to which it is directed. There are holographic optical elements for reflecting the first light beam from the first light sources to the first light detectors.

Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

NASA Technical Reports Server (NTRS)

Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

1991-01-01

The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

The differential effects of ecstasy/polydrug use on executive components: shifting, inhibition, updating and access to semantic memory.

PubMed

Montgomery, Catharine; Fisk, John E; Newcombe, Russell; Murphy, Phillip N

2005-10-01

Recent theoretical models suggest that the central executive may not be a unified structure. The present study explored the nature of central executive deficits in ecstasy users. In study 1, 27 ecstasy users and 34 non-users were assessed using tasks to tap memory updating (computation span; letter updating) and access to long-term memory (a semantic fluency test and the Chicago Word Fluency Test). In study 2, 51 ecstasy users and 42 non-users completed tasks that assess mental set switching (number/letter and plus/minus) and inhibition (random letter generation). MANOVA revealed that ecstasy users performed worse on both tasks used to assess memory updating and on tasks to assess access to long-term memory (C- and S-letter fluency). However, notwithstanding the significant ecstasy group-related effects, indices of cocaine and cannabis use were also significantly correlated with most of the executive measures. Unexpectedly, in study 2, ecstasy users performed significantly better on the inhibition task, producing more letters than non-users. No group differences were observed on the switching tasks. Correlations between indices of ecstasy use and number of letters produced were significant. The present study provides further support for ecstasy/polydrug-related deficits in memory updating and in access to long-term memory. The surplus evident on the inhibition task should be treated with some caution, as this was limited to a single measure and has not been supported by our previous work.

Switching behavior of resistive change memory using oxide nanowires

NASA Astrophysics Data System (ADS)

Aono, Takashige; Sugawa, Kosuke; Shimizu, Tomohiro; Shingubara, Shoso; Takase, Kouichi

2018-06-01

Resistive change random access memory (ReRAM), which is expected to be the next-generation nonvolatile memory, often has wide switching voltage distributions due to many kinds of conductive filaments. In this study, we have tried to suppress the distribution through the structural restriction of the filament-forming area using NiO nanowires. The capacitor with Ni metal nanowires whose surface is oxidized showed good switching behaviors with narrow distributions. The knowledge gained from our study will be very helpful in producing practical ReRAM devices.

Test Procedures for Semiconductor Random Access Memories

DTIC Science & Technology

1979-11-01

of each cell exactly complement to each other, the read operations on the base cell in (g) of step 2 following operations ko S odd and in (p) of step...contents of Sko (these cells this address. Furthermore, when more than one contained I at test time and even if the con- cell is accessed then the output

Designing Programs for Multiple Configurations: "You Mean Everyone Doesn't Have a Pentium or Better!"

ERIC Educational Resources Information Center

Conkright, Thomas D.; Joliat, Judy

1996-01-01

Discusses the challenges, solutions, and compromises involved in creating computer-delivered training courseware for Apollo Travel Services, a company whose 50,000 agents must access a mainframe from many different computing configurations. Initial difficulties came in trying to manage random access memory and quicken response time, but the future…

Single event upset in avionics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taber, A.; Normand, E.

1993-04-01

Data from military/experimental flights and laboratory testing indicate that typical non radiation-hardened 64K and 256K static random access memories (SRAMs) can experience a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere. It is suggested that error detection and correction (EDAC) circuitry be considered for all avionics designs containing large amounts of semi-conductor memory.

MRAM Technology Status

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2013-01-01

Magnetoresistive Random Access Memory (MRAM) is much different from conventional types of memory like SRAM, DRAM, and Flash, where electric charge is used to store information. Instead of exploiting the charge of an electron, MRAM uses its spin to store data. This new type of electronics is known as "spintronics." The primary focus of this report is the current generation of MRAM technology, and its reliability, vendors, and space-readiness.

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

Pressure-induced reversible amorphization and an amorphous–amorphous transition in Ge2Sb2Te5 phase-change memory material

PubMed Central

Sun, Zhimei; Zhou, Jian; Pan, Yuanchun; Song, Zhitang; Mao, Ho-Kwang; Ahuja, Rajeev

2011-01-01

Ge2Sb2Te5 (GST) is a technologically very important phase-change material that is used in digital versatile disks-random access memory and is currently studied for the use in phase-change random access memory devices. This type of data storage is achieved by the fast reversible phase transition between amorphous and crystalline GST upon heat pulse. Here we report pressure-induced reversible crystalline-amorphous and polymorphic amorphous transitions in NaCl structured GST by ab initio molecular dynamics calculations. We have showed that the onset amorphization of GST starts at approximately 18 GPa and the system become completely random at approximately 22 GPa. This amorphous state has a cubic framework (c-amorphous) of sixfold coordinations. With further increasing pressure, the c-amorphous transforms to a high-density amorphous structure with trigonal framework (t-amorphous) and an average coordination number of eight. The pressure-induced amorphization is investigated to be due to large displacements of Te atoms for which weak Te–Te bonds exist or vacancies are nearby. Upon decompressing to ambient conditions, the original cubic crystalline structure is restored for c-amorphous, whereas t-amorphous transforms to another amorphous phase that is similar to the melt-quenched amorphous GST. PMID:21670255

Pressure-induced reversible amorphization and an amorphous-amorphous transition in Ge₂Sb₂Te₅ phase-change memory material.

PubMed

Sun, Zhimei; Zhou, Jian; Pan, Yuanchun; Song, Zhitang; Mao, Ho-Kwang; Ahuja, Rajeev

2011-06-28

Ge(2)Sb(2)Te(5) (GST) is a technologically very important phase-change material that is used in digital versatile disks-random access memory and is currently studied for the use in phase-change random access memory devices. This type of data storage is achieved by the fast reversible phase transition between amorphous and crystalline GST upon heat pulse. Here we report pressure-induced reversible crystalline-amorphous and polymorphic amorphous transitions in NaCl structured GST by ab initio molecular dynamics calculations. We have showed that the onset amorphization of GST starts at approximately 18 GPa and the system become completely random at approximately 22 GPa. This amorphous state has a cubic framework (c-amorphous) of sixfold coordinations. With further increasing pressure, the c-amorphous transforms to a high-density amorphous structure with trigonal framework (t-amorphous) and an average coordination number of eight. The pressure-induced amorphization is investigated to be due to large displacements of Te atoms for which weak Te-Te bonds exist or vacancies are nearby. Upon decompressing to ambient conditions, the original cubic crystalline structure is restored for c-amorphous, whereas t-amorphous transforms to another amorphous phase that is similar to the melt-quenched amorphous GST.

Conductance Quantization in Resistive Random Access Memory

NASA Astrophysics Data System (ADS)

Li, Yang; Long, Shibing; Liu, Yang; Hu, Chen; Teng, Jiao; Liu, Qi; Lv, Hangbing; Suñé, Jordi; Liu, Ming

2015-10-01

The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects.

Conductance Quantization in Resistive Random Access Memory.

PubMed

Li, Yang; Long, Shibing; Liu, Yang; Hu, Chen; Teng, Jiao; Liu, Qi; Lv, Hangbing; Suñé, Jordi; Liu, Ming

2015-12-01

The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects.

Radiation Test Challenges for Scaled Commerical Memories

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Ladbury, Ray L.; Cohn, Lewis M.; Oldham, Timothy

2007-01-01

As sub-100nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this talk, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art Flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this presentation, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

The relationships of 'ecstasy' (MDMA) and cannabis use to impaired executive inhibition and access to semantic long-term memory.

PubMed

Murphy, Philip N; Erwin, Philip G; Maciver, Linda; Fisk, John E; Larkin, Derek; Wareing, Michelle; Montgomery, Catharine; Hilton, Joanne; Tames, Frank J; Bradley, Belinda; Yanulevitch, Kate; Ralley, Richard

2011-10-01

This study aimed to examine the relationship between the consumption of ecstasy (3,4-methylenedioxymethamphetamine (MDMA)) and cannabis, and performance on the random letter generation task which generates dependent variables drawing upon executive inhibition and access to semantic long-term memory (LTM). The participant group was a between-participant independent variable with users of both ecstasy and cannabis (E/C group, n = 15), users of cannabis but not ecstasy (CA group, n = 13) and controls with no exposure to these drugs (CO group, n = 12). Dependent variables measured violations of randomness: number of repeat sequences, number of alphabetical sequences (both drawing upon inhibition) and redundancy (drawing upon access to semantic LTM). E/C participants showed significantly higher redundancy than CO participants but did not differ from CA participants. There were no significant effects for the other dependent variables. A regression model comprising intelligence measures and estimates of ecstasy and cannabis consumption predicted redundancy scores, but only cannabis consumption contributed significantly to this prediction. Impaired access to semantic LTM may be related to cannabis consumption, although the involvement of ecstasy and other stimulant drugs cannot be excluded here. Executive inhibitory functioning, as measured by the random letter generation task, is unrelated to ecstasy and cannabis consumption. Copyright © 2011 John Wiley & Sons, Ltd.

75 FR 44989 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-07-30

... following respondents: NVIDIA Corporation of Santa Clara, California; Asustek Computer, Inc. of Taipei... exclusion order and cease- and-desist orders against respondents NVIDIA Corp.; Hewlett-Packard Co.; ASUS...

Realization of the Switching Mechanism in Resistance Random Access Memory™ Devices: Structural and Electronic Properties Affecting Electron Conductivity in a Hafnium Oxide-Electrode System Through First-Principles Calculations

NASA Astrophysics Data System (ADS)

Aspera, Susan Meñez; Kasai, Hideaki; Kishi, Hirofumi; Awaya, Nobuyoshi; Ohnishi, Shigeo; Tamai, Yukio

2013-01-01

The resistance random access memory (RRAM™) device, with its electrically induced nanoscale resistive switching capacity, has attracted considerable attention as a future nonvolatile memory device. Here, we propose a mechanism of switching based on an oxygen vacancy migration-driven change in the electronic properties of the transition-metal oxide film stimulated by set pulse voltages. We used density functional theory-based calculations to account for the effect of oxygen vacancies and their migration on the electronic properties of HfO2 and Ta/HfO2 systems, thereby providing a complete explanation of the RRAM™ switching mechanism. Furthermore, computational results on the activation energy barrier for oxygen vacancy migration were found to be consistent with the set and reset pulse voltage obtained from experiments. Understanding this mechanism will be beneficial to effectively realizing the materials design in these devices.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Combinatorial Investigation of ZrO2-Based Dielectric Materials for Dynamic Random-Access Memory Capacitors

NASA Astrophysics Data System (ADS)

Kiyota, Yuji; Itaka, Kenji; Iwashita, Yuta; Adachi, Tetsuya; Chikyow, Toyohiro; Ogura, Atsushi

2011-06-01

We investigated zirconia (ZrO2)-based material libraries in search of new dielectric materials for dynamic random-access memory (DRAM) by combinatorial-pulsed laser deposition (combi-PLD). We found that the substitution of yttrium (Y) to Zr sites in the ZrO2 system suppressed the leakage current effectively. The metal-insulator-metal (MIM) capacitor property of this system showed a leakage current density of less than 5×10-7 A/cm2 and the dielectric constant was 20. Moreover, the addition of titanium (Ti) or tantalum (Ta) to this system caused the dielectric constant to increase to ˜25 within the allowed leakage level of 5×10-7 A/cm2. Therefore, Zr-Y-Ti-O and Zr-Y-Ta-O systems have good potentials for use as new materials with high dielectric constants of DRAM capacitors instead of silicon dioxides (SiO2).

All-optical clocked flip-flops and random access memory cells using the nonlinear polarization rotation effect of low-polarization-dependent semiconductor optical amplifiers

NASA Astrophysics Data System (ADS)

Wang, Yongjun; Liu, Xinyu; Tian, Qinghua; Wang, Lina; Xin, Xiangjun

2018-03-01

Basic configurations of various all-optical clocked flip-flops (FFs) and optical random access memory (RAM) based on the nonlinear polarization rotation (NPR) effect of low-polarization-dependent semiconductor optical amplifiers (SOA) are proposed. As the constituent elements, all-optical logic gates and all-optical SR latches are constructed by taking advantage of the SOA's NPR switch. Different all-optical FFs (AOFFs), including SR-, D-, T-, and JK-types as well as an optical RAM cell were obtained by the combination of the proposed all-optical SR latches and logic gates. The effectiveness of the proposed schemes were verified by simulation results and demonstrated by a D-FF and 1-bit RAM cell experimental system. The proposed all-optical clocked FFs and RAM cell are significant to all-optical signal processing.

CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Simulation of SET Operation in Phase-Change Random Access Memories with Heater Addition and Ring-Type Contactor for Low-Power Consumption by Finite Element Modeling

NASA Astrophysics Data System (ADS)

Gong, Yue-Feng; Song, Zhi-Tang; Ling, Yun; Liu, Yan; Feng, Song-Lin

2009-11-01

A three-dimensional finite element model for phase change random access memory (PCRAM) is established for comprehensive electrical and thermal analysis during SET operation. The SET behaviours of the heater addition structure (HS) and the ring-type contact in bottom electrode (RIB) structure are compared with each other. There are two ways to reduce the RESET current, applying a high resistivity interfacial layer and building a new device structure. The simulation results indicate that the variation of SET current with different power reduction ways is little. This study takes the RESET and SET operation current into consideration, showing that the RIB structure PCRAM cell is suitable for future devices with high heat efficiency and high-density, due to its high heat efficiency in RESET operation.

Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Popovici, M., E-mail: Mihaela.Ioana.Popovici@imec.be; Swerts, J.; Redolfi, A.

2014-02-24

Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20 nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (J{sub g}) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO{sub 2}/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electricallymore » active defects and is essential to achieve a low leakage current in the MIM capacitor.« less

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

NASA Astrophysics Data System (ADS)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems

NASA Astrophysics Data System (ADS)

Wang, Yongkun; Goda, Kazuo; Kitsuregawa, Masaru

Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been widely deployed in consumer electronics even partly in mobile computing environments. For enterprise systems, the deployment has been studied by many researchers and developers. In terms of the access performance characteristics, flash memory is quite different from disk drives. Without the mechanical components, flash memory has very high random read performance, whereas it has a limited random write performance because of the erase-before-write design. The random write performance of flash memory is comparable with or even worse than that of disk drives. Due to such a performance asymmetry, naive deployment to enterprise systems may not exploit the potential performance of flash memory at full blast. This paper studies the effectiveness of using non-in-place-update (NIPU) techniques through the IO path of flash-based transaction processing systems. Our deliberate experiments using both open-source DBMS and commercial DBMS validated the potential benefits; x3.0 to x6.6 performance improvement was confirmed by incorporating non-in-place-update techniques into file system without any modification of applications or storage devices.

Improving Unipolar Resistive Switching Uniformity with Cone-Shaped Conducting Filaments and Its Logic-In-Memory Application.

PubMed

Gao, Shuang; Liu, Gang; Chen, Qilai; Xue, Wuhong; Yang, Huali; Shang, Jie; Chen, Bin; Zeng, Fei; Song, Cheng; Pan, Feng; Li, Run-Wei

2018-02-21

Resistive random access memory (RRAM) with inherent logic-in-memory capability exhibits great potential to construct beyond von-Neumann computers. Particularly, unipolar RRAM is more promising because its single polarity operation enables large-scale crossbar logic-in-memory circuits with the highest integration density and simpler peripheral control circuits. However, unipolar RRAM usually exhibits poor switching uniformity because of random activation of conducting filaments and consequently cannot meet the strict uniformity requirement for logic-in-memory application. In this contribution, a new methodology that constructs cone-shaped conducting filaments by using chemically a active metal cathode is proposed to improve unipolar switching uniformity. Such a peculiar metal cathode will react spontaneously with the oxide switching layer to form an interfacial layer, which together with the metal cathode itself can act as a load resistor to prevent the overgrowth of conducting filaments and thus make them more cone-like. In this way, the rupture of conducting filaments can be strictly limited to the tip region, making their residual parts favorable locations for subsequent filament growth and thus suppressing their random regeneration. As such, a novel "one switch + one unipolar RRAM cell" hybrid structure is capable to realize all 16 Boolean logic functions for large-scale logic-in-memory circuits.

Advanced Simulation in Undergraduate Pilot Training: Automatic Instructional System

DTIC Science & Technology

1975-10-01

an addressable reel-to--reel audio tape recorder, a random access audio memory drum , and an interactive software package which permits the user to...audio memory drum , and an interactive software package which permits the user to develop preptogtahmed exercises. Figure 2 illustrates overall...Data Recprding System consists of two elements; an overlay program which performs the real-time sampling of specified variables and stores data to disc

a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths

PubMed Central

Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

2015-01-01

The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p+-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I–V ) curves combined with the temperature dependence of the I–V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole–Frenkel (P–F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM. PMID:26508086

a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths.

PubMed

Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

2015-10-28

The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p(+)-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I-V) curves combined with the temperature dependence of the I-V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole-Frenkel (P-F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM.

Investigation of resistive switching behaviours in WO3-based RRAM devices

NASA Astrophysics Data System (ADS)

Li, Ying-Tao; Long, Shi-Bing; Lü, Hang-Bing; Liu, Qi; Wang, Qin; Wang, Yan; Zhang, Sen; Lian, Wen-Tai; Liu, Su; Liu, Ming

2011-01-01

In this paper, a WO3-based resistive random access memory device composed of a thin film of WO3 sandwiched between a copper top and a platinum bottom electrodes is fabricated by electron beam evaporation at room temperature. The reproducible resistive switching, low power consumption, multilevel storage possibility, and good data retention characteristics demonstrate that the Cu/WO3/Pt memory device is very promising for future nonvolatile memory applications. The formation and rupture of localised conductive filaments is suggested to be responsible for the observed resistive switching behaviours.

Development of bubble memory recorder onboard Japan Earth Resources Satellite-1

NASA Astrophysics Data System (ADS)

Araki, Tsunehiko; Ishida, Chu; Ochiai, Kiyoshi; Nozue, Tatsuhiro; Tachibana, Kyozo; Yoshida, Kazutoshi

The Bubble Memory Recorder (BMR) developed for use on the Earth Resources Satellite is described in terms of its design, capabilities, and functions. The specifications of the BMR are given listing memory capacity, functions, and interface types for data, command, and telemetry functions. The BMR has an emergency signal interface to provide contingency recording, and a satellite-separation signal interface can be turned on automatically by signal input. Data are stored in a novolatile memory device so that the memory is retained during power outages. The BMR is characterized by a capability for random access, nonvolatility, and a solid-state design that is useful for space operations since it does not disturb spacecraft attitude.

RAPID: A random access picture digitizer, display, and memory system

NASA Technical Reports Server (NTRS)

Yakimovsky, Y.; Rayfield, M.; Eskenazi, R.

1976-01-01

RAPID is a system capable of providing convenient digital analysis of video data in real-time. It has two modes of operation. The first allows for continuous digitization of an EIA RS-170 video signal. Each frame in the video signal is digitized and written in 1/30 of a second into RAPID's internal memory. The second mode leaves the content of the internal memory independent of the current input video. In both modes of operation the image contained in the memory is used to generate an EIA RS-170 composite video output signal representing the digitized image in the memory so that it can be displayed on a monitor.

An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

NASA Technical Reports Server (NTRS)

Rao, Vikram; Patel, Jagdish; Patel, Janak; Namkung, Jeffrey

2001-01-01

Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

Solution-processed flexible NiO resistive random access memory device

NASA Astrophysics Data System (ADS)

Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

2018-04-01

Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

High Speed Oblivious Random Access Memory (HS-ORAM)

DTIC Science & Technology

2015-09-01

Bryan Parno, “Non-interactive verifiable computing: Outsourcing computation to untrusted workers”, 30th International Cryptology Conference, pp. 465...holder or any other person or corporation; or convey any rights or permission to manufacture , use, or sell any patented invention that may relate to...secure outsourced data access protocols. HS-ORAM deploys a number of server- side software components running inside tamper-proof secure coprocessors

Ease of Access to List Items in Short-Term Memory Depends on the Order of the Recognition Probes

ERIC Educational Resources Information Center

Lange, Elke B.; Cerella, John; Verhaeghen, Paul

2011-01-01

We report data from 4 experiments using a recognition design with multiple probes to be matched to specific study positions. Items could be accessed rapidly, independent of set size, when the test order matched the study order (forward condition). When the order of testing was random, backward, or in a prelearned irregular sequence (reordered…

Physics Notes.

ERIC Educational Resources Information Center

School Science Review, 1979

1979-01-01

Included is information regarding: fabrication of light emitting diodes, their operation as semiconductors, and an experiment demonstrating electroluminescence; experimenting with Random Access Memory (RAM) circuits; demonstrating Coriolis effect; measuring the diameter of an electron beam, E.H.T. meters; launching a trolley by catapult; a "random…

The Matter with Listening Comprehension Isn't the Ear: Hardware and Software.

ERIC Educational Resources Information Center

Harvey, T. Edward

1978-01-01

Reviews some technological advances and classroom games which may be used to increase listening comprehension skills in the foreign language classroom. These include the Random Access Memory (RAM), the Sens-it-Cell, and the SCUCHO game. (AM)

Jargon that Computes: Today's PC Terminology.

ERIC Educational Resources Information Center

Crawford, Walt

1997-01-01

Discusses PC (personal computer) and telecommunications terminology in context: Integrated Services Digital Network (ISDN); Asymmetric Digital Subscriber Line (ADSL); cable modems; satellite downloads; T1 and T3 lines; magnitudes ("giga-,""nano-"); Central Processing Unit (CPU); Random Access Memory (RAM); Universal Serial Bus…

Evaluation of Recent Technologies of Nonvolatile RAM

NASA Astrophysics Data System (ADS)

Nuns, Thierry; Duzellier, Sophie; Bertrand, Jean; Hubert, Guillaume; Pouget, Vincent; Darracq, FrÉdÉric; David, Jean-Pierre; Soonckindt, Sabine

2008-08-01

Two types of recent nonvolatile random access memories (NVRAM) were evaluated for radiation effects: total dose and single event upset and latch-up under heavy ions and protons. Complementary irradiation with a laser beam provides information on sensitive areas of the devices.

Dynamic-RAM Data Storage Unit

NASA Technical Reports Server (NTRS)

Sturman, J. C.

1985-01-01

Dynamic random-access-memory (RAM) data delay and storage unit developed to insure data received from satellite is stored and not lost when satellite is not within range of ground station. Stores 256K of serial data, with independent read and write capability.

SRAM As An Array Of Energetic-Ion Detectors

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Lieneweg, Udo; Nixon, Robert H.

1993-01-01

Static random-access memory (SRAM) designed for use as array of energetic-ion detectors. Exploits well-known tendency of incident energetic ions to cause bit flips in cells of electronic memories. Design of ion-detector SRAM involves modifications of standard SRAM design to increase sensitivity to ions. Device fabricated by use of conventional complementary metal oxide/semiconductor (CMOS) processes. Potential uses include gas densimetry, position sensing, and measurement of cosmic-ray spectrum.

Asymmetric Memory Circuit Would Resist Soft Errors

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Perlman, Marvin

1990-01-01

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology.

PubMed

Tian, He; Chen, Hong-Yu; Ren, Tian-Ling; Li, Cheng; Xue, Qing-Tang; Mohammad, Mohammad Ali; Wu, Can; Yang, Yi; Wong, H-S Philip

2014-06-11

Laser scribing is an attractive reduced graphene oxide (rGO) growth and patterning technology because the process is low-cost, time-efficient, transfer-free, and flexible. Various laser-scribed rGO (LSG) components such as capacitors, gas sensors, and strain sensors have been demonstrated. However, obstacles remain toward practical application of the technology where all the components of a system are fabricated using laser scribing. Memory components, if developed, will substantially broaden the application space of low-cost, flexible electronic systems. For the first time, a low-cost approach to fabricate resistive random access memory (ReRAM) using laser-scribed rGO as the bottom electrode is experimentally demonstrated. The one-step laser scribing technology allows transfer-free rGO synthesis directly on flexible substrates or non-flat substrates. Using this time-efficient laser-scribing technology, the patterning of a memory-array area up to 100 cm(2) can be completed in 25 min. Without requiring the photoresist coating for lithography, the surface of patterned rGO remains as clean as its pristine state. Ag/HfOx/LSG ReRAM using laser-scribing technology is fabricated in this work. Comprehensive electrical characteristics are presented including forming-free behavior, stable switching, reasonable reliability performance and potential for 2-bit storage per memory cell. The results suggest that laser-scribing technology can potentially produce more cost-effective and time-effective rGO-based circuits and systems for practical applications.

Portable and Error-Free DNA-Based Data Storage.

PubMed

Yazdi, S M Hossein Tabatabaei; Gabrys, Ryan; Milenkovic, Olgica

2017-07-10

DNA-based data storage is an emerging nonvolatile memory technology of potentially unprecedented density, durability, and replication efficiency. The basic system implementation steps include synthesizing DNA strings that contain user information and subsequently retrieving them via high-throughput sequencing technologies. Existing architectures enable reading and writing but do not offer random-access and error-free data recovery from low-cost, portable devices, which is crucial for making the storage technology competitive with classical recorders. Here we show for the first time that a portable, random-access platform may be implemented in practice using nanopore sequencers. The novelty of our approach is to design an integrated processing pipeline that encodes data to avoid costly synthesis and sequencing errors, enables random access through addressing, and leverages efficient portable sequencing via new iterative alignment and deletion error-correcting codes. Our work represents the only known random access DNA-based data storage system that uses error-prone nanopore sequencers, while still producing error-free readouts with the highest reported information rate/density. As such, it represents a crucial step towards practical employment of DNA molecules as storage media.

77 FR 11486 - Fresh Garlic From the People's Republic of China: Partial Final Results and Partial Final...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-02-27

... between grades are based on color, size, sheathing, and level of decay. The scope of the order does not... Less than Fair Value: Static Random Access Memory Semiconductors From Taiwan, 63 FR 8909, 8911...

Preparation of School District Budgets with Microcomputer Electronic Spreadsheets.

ERIC Educational Resources Information Center

Hinitz, Herman J.

1996-01-01

Preparing a microcomputer electronic spreadsheet containing all relevant school district budgetary information is possible with currently available hardware and software (such as Lotus 1-2-3), despite random-access-memory limitations. Spreadsheets can provide financial summaries, inventory-control listings, scheduling alternatives,…

High density submicron magnetoresistive random access memory (invited)

NASA Astrophysics Data System (ADS)

Tehrani, S.; Chen, E.; Durlam, M.; DeHerrera, M.; Slaughter, J. M.; Shi, J.; Kerszykowski, G.

1999-04-01

Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal-oxide-semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

Non-volatile memory based on the ferroelectric photovoltaic effect

PubMed Central

Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

2013-01-01

The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fang, Runchen; Yu, Shimeng, E-mail: shimengy@asu.edu; School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, Arizona 85287

The total ionizing dose (TID) effect of gamma-ray (γ-ray) irradiation on HfOx based resistive random access memory was investigated by electrical and material characterizations. The memory states can sustain TID level ∼5.2 Mrad (HfO{sub 2}) without significant change in the functionality or the switching characteristics under pulse cycling. However, the stability of the filament is weakened after irradiation as memory states are more vulnerable to flipping under the electrical stress. X-ray photoelectron spectroscopy was performed to ascertain the physical mechanism of the stability degradation, which is attributed to the Hf-O bond breaking by the high-energy γ-ray exposure.

Spin torque switching of 20 nm magnetic tunnel junctions with perpendicular anisotropy

NASA Astrophysics Data System (ADS)

Gajek, M.; Nowak, J. J.; Sun, J. Z.; Trouilloud, P. L.; O'Sullivan, E. J.; Abraham, D. W.; Gaidis, M. C.; Hu, G.; Brown, S.; Zhu, Y.; Robertazzi, R. P.; Gallagher, W. J.; Worledge, D. C.

2012-03-01

Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising emerging non-volatile memory technologies. MRAM has so far been demonstrated with a unique combination of density, speed, and non-volatility in a single chip, however, without the capability to replace any single mainstream memory. In this paper, we demonstrate the basic physics of spin torque switching in 20 nm diameter magnetic tunnel junctions with perpendicular magnetic anisotropy materials. This deep scaling capability clearly indicates the STT MRAM device itself may be suitable for integration at much higher densities than previously proven.

Bistable resistive memory behavior in gelatin-CdTe quantum dot composite film

NASA Astrophysics Data System (ADS)

Vallabhapurapu, Sreedevi; Rohom, Ashwini; Chaure, N. B.; Du, Shengzhi; Srinivasan, Ananthakrishnan

2018-05-01

Bistable memory behavior has been observed for the first time in gelatin type A thin film dispersed with functionalized CdTe quantum dots. The two terminal device with the polymer nanocomposite layer sandwiched between an indium tin oxide coated glass plate and an aluminium top electrode performs as a bistable resistive random access memory module. Butterfly shaped (O-shaped with a hysteresis in forward and reverse sweeps) current-voltage response is observed in this device. The conduction mechanism leading to the bistable electrical switching has been deduced to be a combination of ohmic and electron hopping.

Investigating the origins of high multilevel resistive switching in forming free Ti/TiO2-x-based memory devices through experiments and simulations

NASA Astrophysics Data System (ADS)

Bousoulas, P.; Giannopoulos, I.; Asenov, P.; Karageorgiou, I.; Tsoukalas, D.

2017-03-01

Although multilevel capability is probably the most important property of resistive random access memory (RRAM) technology, it is vulnerable to reliability issues due to the stochastic nature of conducting filament (CF) creation. As a result, the various resistance states cannot be clearly distinguished, which leads to memory capacity failure. In this work, due to the gradual resistance switching pattern of TiO2-x-based RRAM devices, we demonstrate at least six resistance states with distinct memory margin and promising temporal variability. It is shown that the formation of small CFs with high density of oxygen vacancies enhances the uniformity of the switching characteristics in spite of the random nature of the switching effect. Insight into the origin of the gradual resistance modulation mechanisms is gained by the application of a trap-assisted-tunneling model together with numerical simulations of the filament formation physical processes.

Signal and noise extraction from analog memory elements for neuromorphic computing.

PubMed

Gong, N; Idé, T; Kim, S; Boybat, I; Sebastian, A; Narayanan, V; Ando, T

2018-05-29

Dense crossbar arrays of non-volatile memory (NVM) can potentially enable massively parallel and highly energy-efficient neuromorphic computing systems. The key requirements for the NVM elements are continuous (analog-like) conductance tuning capability and switching symmetry with acceptable noise levels. However, most NVM devices show non-linear and asymmetric switching behaviors. Such non-linear behaviors render separation of signal and noise extremely difficult with conventional characterization techniques. In this study, we establish a practical methodology based on Gaussian process regression to address this issue. The methodology is agnostic to switching mechanisms and applicable to various NVM devices. We show tradeoff between switching symmetry and signal-to-noise ratio for HfO 2 -based resistive random access memory. Then, we characterize 1000 phase-change memory devices based on Ge 2 Sb 2 Te 5 and separate total variability into device-to-device variability and inherent randomness from individual devices. These results highlight the usefulness of our methodology to realize ideal NVM devices for neuromorphic computing.

System for loading executable code into volatile memory in a downhole tool

DOEpatents

Hall, David R.; Bartholomew, David B.; Johnson, Monte L.

2007-09-25

A system for loading an executable code into volatile memory in a downhole tool string component comprises a surface control unit comprising executable code. An integrated downhole network comprises data transmission elements in communication with the surface control unit and the volatile memory. The executable code, stored in the surface control unit, is not permanently stored in the downhole tool string component. In a preferred embodiment of the present invention, the downhole tool string component comprises boot memory. In another embodiment, the executable code is an operating system executable code. Preferably, the volatile memory comprises random access memory (RAM). A method for loading executable code to volatile memory in a downhole tool string component comprises sending the code from the surface control unit to a processor in the downhole tool string component over the network. A central processing unit writes the executable code in the volatile memory.

Nanoscale chemical state analysis of resistance random access memory device reacting with Ti

NASA Astrophysics Data System (ADS)

Shima, Hisashi; Nakano, Takashi; Akinaga, Hiro

2010-05-01

The thermal stability of the resistance random access memory material in the reducing atmosphere at the elevated temperature was improved by the addition of Ti. The unipolar resistance switching before and after the postdeposition annealing (PDA) process at 400 °C was confirmed in Pt/CoO/Ti(5 nm)/Pt device, while the severe degradation of the initial resistance occurs in the Pt/CoO/Pt and Pt/CoO/Ti(50 nm)/Pt devices. By investigating the chemical bonding states of Co, O, and Ti using electron energy loss spectroscopy combined with transmission electron microscopy, it was revealed that excess Ti induces the formation of metallic Co, while the thermal stability was improved by trace Ti. Moreover, it was indicated that the filamentary conduction path can be thermally induced after PDA in the oxide layer by analyzing electrical properties of the degraded devices. The adjustment of the reducing elements is quite essential in order to participate in their profits.

A Novel Ni/WOX/W Resistive Random Access Memory with Excellent Retention and Low Switching Current

NASA Astrophysics Data System (ADS)

Chien, Wei-Chih; Chen, Yi-Chou; Lee, Feng-Ming; Lin, Yu-Yu; Lai, Erh-Kun; Yao, Yeong-Der; Gong, Jeng; Horng, Sheng-Fu; Yeh, Chiao-Wen; Tsai, Shih-Chang; Lee, Ching-Hsiung; Huang, Yu-Kai; Chen, Chun-Fu; Kao, Hsiao-Feng; Shih, Yen-Hao; Hsieh, Kuang-Yeu; Lu, Chih-Yuan

2011-04-01

The behavior of WOX resistive random access memory (ReRAM) is a strong function of the top electrode material, which controls the conduction mechanism and the forming process. When using a top electrode with low work function, the current conduction is limited by space charges. On the other hand, the mechanism becomes thermionic emission for devices with a high work function top electrode. These (thermionic) devices are also found to have higher initial resistance, reduced forming current, and larger resistance window. Based on these insights and considering the compatibility to complementary metal-oxide-semiconductor (CMOS) process, we proposed to use Ni as the top electrode for high performance WOX ReRAM devices. The new Ni/WOX/W device can be switched at a low current density less than 8×105 A/cm2, with RESET/SET resistance ratio greater than 100, and extremely good data retention of more than 300 years at 85 °C.

Forming-free, bipolar resistivity switching characteristics of fully transparent resistive random access memory with IZO/α-IGZO/ITO structure

NASA Astrophysics Data System (ADS)

Lo, Chun-Chieh; Hsieh, Tsung-Eong

2016-09-01

Fully transparent resistive random access memory (TRRAM) containing amorphous indium gallium zinc oxide as the resistance switching (RS) layer and transparent conducting oxides (indium zinc oxide and indium tin oxide) as the electrodes was prepared. Optical measurement indicated the transmittance of device exceeds 80% in visible-light wavelength range. TRRAM samples exhibited the forming-free feature and the best electrical performance (V SET  =  0.61 V V RESET  =  -0.76 V R HRS/R LRS (i.e. the R-ratio)  >103) was observed in the device subject to a post-annealing at 300 °C for 1 hr in atmospheric ambient. Such a sample also exhibited satisfactory endurance and retention properties at 85 °C as revealed by the reliability tests. Electrical measurement performed in vacuum ambient indicated that the RS mechanism correlates with the charge trapping/de-trapping process associated with oxygen defects in the RS layer.

Dynamic-load-enabled ultra-low power multiple-state RRAM devices.

PubMed

Yang, Xiang; Chen, I-Wei

2012-01-01

Bipolar resistance-switching materials allowing intermediate states of wide-varying resistance values hold the potential of drastically reduced power for non-volatile memory. To exploit this potential, we have introduced into a nanometallic resistance-random-access-memory (RRAM) device an asymmetric dynamic load, which can reliably lower switching power by orders of magnitude. The dynamic load is highly resistive during on-switching allowing access to the highly resistive intermediate states; during off-switching the load vanishes to enable switching at low voltage. This approach is entirely scalable and applicable to other bipolar RRAM with intermediate states. The projected power is 12 nW for a 100 × 100 nm(2) device and 500 pW for a 10 × 10 nm(2) device. The dynamic range of the load can be increased to allow power to be further decreased by taking advantage of the exponential decay of wave-function in a newly discovered nanometallic random material, reaching possibly 1 pW for a 10×10 nm(2) nanometallic RRAM device.

Electrical Characterization of the RCA CDP1822SD Random Access Memory, Volume 1, Appendix a

NASA Technical Reports Server (NTRS)

Klute, A.

1979-01-01

Electrical characteristization tests were performed on 35 RCA CDP1822SD, 256-by-4-bit, CMOS, random access memories. The tests included three functional tests, AC and DC parametric tests, a series of schmoo plots, rise/fall time screening, and a data retention test. All tests were performed on an automated IC test system with temperatures controlled by a thermal airstream unit. All the functional tests, the data retention test, and the AC and DC parametric tests were performed at ambient temperatures of 25 C, -20 C, -55 C, 85 C, and 125 C. The schmoo plots were performed at ambient temperatures of 25 C, -55 C, and 125 C. The data retention test was performed at 25 C. Five devices failed one or more functional tests and four of these devices failed to meet the expected limits of a number of AC parametric tests. Some of the schmoo plots indicated a small degree of interaction between parameters.

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 1

NASA Technical Reports Server (NTRS)

Klute, A.

1979-01-01

Electrical characterization and qualification tests were performed on the RCA MWS5001D, 1024 by 1-bit, CMOS, random access memory. Characterization tests were performed on five devices. The tests included functional tests, AC parametric worst case pattern selection test, determination of worst-case transition for setup and hold times and a series of schmoo plots. The qualification tests were performed on 32 devices and included a 2000 hour burn in with electrical tests performed at 0 hours and after 168, 1000, and 2000 hours of burn in. The tests performed included functional tests and AC and DC parametric tests. All of the tests in the characterization phase, with the exception of the worst-case transition test, were performed at ambient temperatures of 25, -55 and 125 C. The worst-case transition test was performed at 25 C. The preburn in electrical tests were performed at 25, -55, and 125 C. All burn in endpoint tests were performed at 25, -40, -55, 85, and 125 C.

Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs)

NASA Technical Reports Server (NTRS)

Sharma, Ashok K.; Teverovsky, Alexander

2001-01-01

Data retention and fatigue characteristics of 64 Kb lead zirconate titanate (PZT)-based Ferroelectric Random Access Memories (FRAMs) microcircuits manufactured by Ramtron were examined over temperature range from -85 C to +310 C for ceramic packaged parts and from -85 C to +175 C for plastic parts, during retention periods up to several thousand hours. Intrinsic failures, which were caused by a thermal degradation of the ferroelectric cells, occurred in ceramic parts after tens or hundreds hours of aging at temperatures above 200 C. The activation energy of the retention test failures was 1.05 eV and the extrapolated mean-time-to-failure (MTTF) at room temperature was estimated to be more than 280 years. Multiple write-read cycling (up to 3x10(exp 7)) during the fatigue testing of plastic and ceramic parts did not result in any parametric or functional failures. However, operational currents linearly decreased with the logarithm of number of cycles thus indicating fatigue process in PZT films. Plastic parts, that had more recent date code as compared to ceramic parts, appeared to be using die with improved process technology and showed significantly smaller changes in operational currents and data access times.

Solving large test-day models by iteration on data and preconditioned conjugate gradient.

PubMed

Lidauer, M; Strandén, I; Mäntysaari, E A; Pösö, J; Kettunen, A

1999-12-01

A preconditioned conjugate gradient method was implemented into an iteration on a program for data estimation of breeding values, and its convergence characteristics were studied. An algorithm was used as a reference in which one fixed effect was solved by Gauss-Seidel method, and other effects were solved by a second-order Jacobi method. Implementation of the preconditioned conjugate gradient required storing four vectors (size equal to number of unknowns in the mixed model equations) in random access memory and reading the data at each round of iteration. The preconditioner comprised diagonal blocks of the coefficient matrix. Comparison of algorithms was based on solutions of mixed model equations obtained by a single-trait animal model and a single-trait, random regression test-day model. Data sets for both models used milk yield records of primiparous Finnish dairy cows. Animal model data comprised 665,629 lactation milk yields and random regression test-day model data of 6,732,765 test-day milk yields. Both models included pedigree information of 1,099,622 animals. The animal model ¿random regression test-day model¿ required 122 ¿305¿ rounds of iteration to converge with the reference algorithm, but only 88 ¿149¿ were required with the preconditioned conjugate gradient. To solve the random regression test-day model with the preconditioned conjugate gradient required 237 megabytes of random access memory and took 14% of the computation time needed by the reference algorithm.

Data storage technology comparisons

NASA Technical Reports Server (NTRS)

Katti, Romney R.

1990-01-01

The role of data storage and data storage technology is an integral, though conceptually often underestimated, portion of data processing technology. Data storage is important in the mass storage mode in which generated data is buffered for later use. But data storage technology is also important in the data flow mode when data are manipulated and hence required to flow between databases, datasets and processors. This latter mode is commonly associated with memory hierarchies which support computation. VLSI devices can reasonably be defined as electronic circuit devices such as channel and control electronics as well as highly integrated, solid-state devices that are fabricated using thin film deposition technology. VLSI devices in both capacities play an important role in data storage technology. In addition to random access memories (RAM), read-only memories (ROM), and other silicon-based variations such as PROM's, EPROM's, and EEPROM's, integrated devices find their way into a variety of memory technologies which offer significant performance advantages. These memory technologies include magnetic tape, magnetic disk, magneto-optic disk, and vertical Bloch line memory. In this paper, some comparison between selected technologies will be made to demonstrate why more than one memory technology exists today, based for example on access time and storage density at the active bit and system levels.

Radiation immune RAM semiconductor technology for the 80's. [Random Access Memory

NASA Technical Reports Server (NTRS)

Hanna, W. A.; Panagos, P.

1983-01-01

This paper presents current and short term future characteristics of RAM semiconductor technologies which were obtained by literature survey and discussions with cognizant Government and industry personnel. In particular, total ionizing dose tolerance and high energy particle susceptibility of the technologies are addressed. Technologies judged compatible with spacecraft applications are ranked to determine the best current and future technology for fast access (less than 60 ns), radiation tolerant RAM.

Static RAM data recorder for flight tests

NASA Astrophysics Data System (ADS)

Stoner, D. C.; Eklund, T. F. F.

A static random access memory (RAM) data recorder has been developed to recover strain and acceleration data during development tests of high-speed earth penetrating vehicles. Bilevel inputs are also available for continuity measurements. An iteration of this system was modified for use on water entry evaluations.

Template Based Low Data Rate Speech Encoder

DTIC Science & Technology

1993-09-30

Nasality Distinguishes In/ from d/ 95.6 96.9 1m/ from /b/, etc. Sustention Distinguishes /f/ from /p/, $7.5 88.3 ibi from N/, Al from /0 8. etc. Sibilation...processor performs mainly Processor Workstation input/output (I/O) operations. The dynamic random access memory (DRAM) has 16 million bytes of...storage capacity. To execute the 800-b/s voice algorithm, the following amount of memory is needed: 5 MB for tables, 1.5 MB for it "program, and 30 KB for

Hidden long evolutionary memory in a model biochemical network

NASA Astrophysics Data System (ADS)

Ali, Md. Zulfikar; Wingreen, Ned S.; Mukhopadhyay, Ranjan

2018-04-01

We introduce a minimal model for the evolution of functional protein-interaction networks using a sequence-based mutational algorithm, and apply the model to study neutral drift in networks that yield oscillatory dynamics. Starting with a functional core module, random evolutionary drift increases network complexity even in the absence of specific selective pressures. Surprisingly, we uncover a hidden order in sequence space that gives rise to long-term evolutionary memory, implying strong constraints on network evolution due to the topology of accessible sequence space.

Skilled memory in expert figure skaters.

PubMed

Deakin, J M; Allard, F

1991-01-01

The present studies extend skilled-memory theory to a domain involving the performance of motor sequences. Skilled figure skaters were better able than their less skilled counterparts to perform short skating sequences that were choreographed, rather than randomly constructed. Expert skaters encoded sequences for performance very differently from the way in which they encoded sequences that were verbally presented for verbal recall. Tasks interpolated between sequence and recall showed no significant influence on recall accuracy, implicating long-term memory in skating memory. There was little evidence for the use of retrieval structures when skaters learned the brief sequences used throughout these studies. Finally, expert skaters were able to judge the similarity of two skating elements faster than less skilled skaters, indicating a faster access to semantic memory for experts. The data indicate that skaters show many of the same skilled-memory characteristics as have been described in other skill domains involving memorization, such as digit span and memory for dinner orders.

One bipolar transistor selector - One resistive random access memory device for cross bar memory array

NASA Astrophysics Data System (ADS)

Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

2017-09-01

A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

A wide bandwidth CCD buffer memory system

NASA Technical Reports Server (NTRS)

Siemens, K.; Wallace, R. W.; Robinson, C. R.

1978-01-01

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

An experimental distributed microprocessor implementation with a shared memory communications and control medium

NASA Technical Reports Server (NTRS)

Mejzak, R. S.

1980-01-01

The distributed processing concept is defined in terms of control primitives, variables, and structures and their use in performing a decomposed discrete Fourier transform (DET) application function. The design assumes interprocessor communications to be anonymous. In this scheme, all processors can access an entire common database by employing control primitives. Access to selected areas within the common database is random, enforced by a hardware lock, and determined by task and subtask pointers. This enables the number of processors to be varied in the configuration without any modifications to the control structure. Decompositional elements of the DFT application function in terms of tasks and subtasks are also described. The experimental hardware configuration consists of IMSAI 8080 chassis which are independent, 8 bit microcomputer units. These chassis are linked together to form a multiple processing system by means of a shared memory facility. This facility consists of hardware which provides a bus structure to enable up to six microcomputers to be interconnected. It provides polling and arbitration logic so that only one processor has access to shared memory at any one time.

A study on carbon nanotube bridge as a electromechanical memory device

NASA Astrophysics Data System (ADS)

Kang, Jeong Won; Ha Lee, Jun; Joo Lee, Hoong; Hwang, Ho Jung

2005-04-01

A nanoelectromechanical (NEM) nanotube random access memory (NRAM) device based on carbon nanotube (CNT) was investigated using atomistic simulations. For the CNT-based NEM memory, the mechanical properties of the CNT-bridge and van der Waals interactions between the CNT-bridge and substrate were very important. The critical amplitude of the CNT-bridge was 16% of the length of the CNT-bridge. As molecular dynamics time increased, the CNT-bridge went to the steady state under the electrostatic force with the damping of the potential and the kinetic energies of the CNT-bridge. The interatomic interaction between the CNT-bridge and substrate, value of the CNT-bridge slack, and damping rate of the CNT-bridge were very important for the operation of the NEM memory device as a nonvolatile memory.

Atomic memory access hardware implementations

DOEpatents

Ahn, Jung Ho; Erez, Mattan; Dally, William J

2015-02-17

Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

50 CFR 660.15 - Equipment requirements.

Code of Federal Regulations, 2011 CFR

2011-10-01

... perceived weight of water, slime, mud, debris, or other materials. Scale printouts must show: (A) The vessel... with Pentium 75-MHz or higher. Random Access Memory (RAM) must have sufficient megabyte (MB) space to... space of 217 MB or greater. A CD-ROM drive with a Video Graphics Adapter (VGA) or higher resolution...

77 FR 26789 - Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-07

... patents. 73 FR 75131. The principal respondent was NVIDIA Corporation of Santa Clara, California (``NVIDIA''). Joining NVIDIA as respondents were approximately twenty of NVIDIA's customers. The Commission found a... accused products in the United States: NVIDIA; Hewlett-Packard Co. of Palo Alto, California; ASUS Computer...

61 FR 41385 - Notice of Government-Owned Inventions; Availability for Licensing

Federal Register 2010, 2011, 2012, 2013, 2014

1996-08-08

... PRESSURE VESSEL; filed 24 February 1995; patented 21 November 1995.// Patent 5,468,356: LARGE SCALE...,477,482: ULTRA HIGH DENSITY, NON- VOLATILE FERROMAGNETIC RANDOM ACCESS MEMORY; filed 1 October 1993....// Patent 5,483,017: HIGH TEMPERATURE THERMOSETS AND CERAMICS DERIVED FROM LINEAR CARBORANE-(SILOXANE OR...

New Mode For Single-Event Upsets

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.; Smith, Lawrence S.; Soli, George A.; Lo, Roger Y.

1988-01-01

Report presents theory and experimental data regarding newly discovered mode for single-event upsets, (SEU's) in complementary metal-oxide/semiconductor, static random-access memories, CMOS SRAM's. SEU cross sections larger than those expected from previously known modes given rise to speculation regarding additional mode, and subsequent cross-section measurements appear to confirm speculation.

Radiation-Tolerant Intelligent Memory Stack - RTIMS

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2011-01-01

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

Evaluation of Magnetoresistive RAM for Space Applications

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2014-01-01

Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.

Memory interface simulator: A computer design aid

NASA Technical Reports Server (NTRS)

Taylor, D. S.; Williams, T.; Weatherbee, J. E.

1972-01-01

Results are presented of a study conducted with a digital simulation model being used in the design of the Automatically Reconfigurable Modular Multiprocessor System (ARMMS), a candidate computer system for future manned and unmanned space missions. The model simulates the activity involved as instructions are fetched from random access memory for execution in one of the system central processing units. A series of model runs measured instruction execution time under various assumptions pertaining to the CPU's and the interface between the CPU's and RAM. Design tradeoffs are presented in the following areas: Bus widths, CPU microprogram read only memory cycle time, multiple instruction fetch, and instruction mix.

Ion beam synthesis of indium-oxide nanocrystals for improvement of oxide resistive random-access memories

NASA Astrophysics Data System (ADS)

Bonafos, C.; Benassayag, G.; Cours, R.; Pécassou, B.; Guenery, P. V.; Baboux, N.; Militaru, L.; Souifi, A.; Cossec, E.; Hamga, K.; Ecoffey, S.; Drouin, D.

2018-01-01

We report on the direct ion beam synthesis of a delta-layer of indium oxide nanocrystals (In2O3-NCs) in silica matrices by using ultra-low energy ion implantation. The formation of the indium oxide phase can be explained by (i) the affinity of indium with oxygen, (ii) the generation of a high excess of oxygen recoils generated by the implantation process in the region where the nanocrystals are formed and (iii) the proximity of the indium-based nanoparticles with the free surface and oxidation from the air. Taking advantage of the selective diffusivity of implanted indium in SiO2 with respect to Si3N4, In2O3-NCs have been inserted in the SiO2 switching oxide of micrometric planar oxide-based resistive random access memory (OxRAM) devices fabricated using the nanodamascene process. Preliminary electrical measurements show switch voltage from high to low resistance state. The devices with In2O3-NCs have been cycled 5 times with identical operating voltages and RESET current meanwhile no switch has been observed for non implanted devices. This first measurement of switching is very promising for the concept of In2O3-NCs based OxRAM memories.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

NASA Astrophysics Data System (ADS)

Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

2009-03-01

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

Demonstration of holographic smart card system using the optical memory technology

NASA Astrophysics Data System (ADS)

Kim, JungHoi; Choi, JaeKwang; An, JunWon; Kim, Nam; Lee, KwonYeon; Jeon, SeckHee

2003-05-01

In this paper, we demonstrate the holographic smart card system using digital holographic memory technique that uses reference beam encrypted by the random phase mask to prevent unauthorized users from accessing the stored digital page. The input data that include document data, a picture of face, and a fingerprint for identification is encoded digitally and then coupled with the reference beam modulated by a random phase mask. Therefore, this proposed system can execute recording in the order of MB~GB and readout all personal information from just one card without any additional database system. Also, recorded digital holograms can't be reconstructed without a phase key and can't be copied by using computers, scanners, or photography.

Threshold-voltage modulated phase change heterojunction for application of high density memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yan, Baihan; Tong, Hao, E-mail: tonghao@hust.edu.cn; Qian, Hang

2015-09-28

Phase change random access memory is one of the most important candidates for the next generation non-volatile memory technology. However, the ability to reduce its memory size is compromised by the fundamental limitations inherent in the CMOS technology. While 0T1R configuration without any additional access transistor shows great advantages in improving the storage density, the leakage current and small operation window limit its application in large-scale arrays. In this work, phase change heterojunction based on GeTe and n-Si is fabricated to address those problems. The relationship between threshold voltage and doping concentration is investigated, and energy band diagrams and X-raymore » photoelectron spectroscopy measurements are provided to explain the results. The threshold voltage is modulated to provide a large operational window based on this relationship. The switching performance of the heterojunction is also tested, showing a good reverse characteristic, which could effectively decrease the leakage current. Furthermore, a reliable read-write-erase function is achieved during the tests. Phase change heterojunction is proposed for high-density memory, showing some notable advantages, such as modulated threshold voltage, large operational window, and low leakage current.« less

Radiation Tolerant Intelligent Memory Stack (RTIMS)

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2006-01-01

The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

Impacts of Co doping on ZnO transparent switching memory device characteristics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Simanjuntak, Firman Mangasa; Wei, Kung-Hwa; Prasad, Om Kumar

2016-05-02

The resistive switching characteristics of indium tin oxide (ITO)/Zn{sub 1−x}Co{sub x}O/ITO transparent resistive memory devices were investigated. An appropriate amount of cobalt dopant in ZnO resistive layer demonstrated sufficient memory window and switching stability. In contrast, pure ZnO devices demonstrated a poor memory window, and using an excessive dopant concentration led to switching instability. To achieve suitable memory performance, relying only on controlling defect concentrations is insufficient; the grain growth orientation of the resistive layer must also be considered. Stable endurance with an ON/OFF ratio of more than one order of magnitude during 5000 cycles confirmed that the Co-doped ZnOmore » device is a suitable candidate for resistive random access memory application. Additionally, fully transparent devices with a high transmittance of up to 90% at wavelength of 550 nm have been fabricated.« less

Sparse distributed memory prototype: Principles of operation

NASA Technical Reports Server (NTRS)

Flynn, Michael J.; Kanerva, Pentti; Ahanin, Bahram; Bhadkamkar, Neal; Flaherty, Paul; Hickey, Philip

1988-01-01

Sparse distributed memory is a generalized random access memory (RAM) for long binary words. Such words can be written into and read from the memory, and they can be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original right address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech and scene analysis, in signal detection and verification, and in adaptive control of automated equipment. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. The research is aimed at resolving major design issues that have to be faced in building the memories. The design of a prototype memory with 256-bit addresses and from 8K to 128K locations for 256-bit words is described. A key aspect of the design is extensive use of dynamic RAM and other standard components.

Making A D-Latch Sensitive To Alpha Particles

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Nixon, Robert H.

1994-01-01

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

A Comparison of the Two Leading Electronic Braille Notetakers.

ERIC Educational Resources Information Center

Leventhal, J. D.; Uslan, M. M.

1992-01-01

Comparison of two electronic braille notetakers found that the Braille 'n Speak was less expensive, easier to learn, and easier for both experienced users and beginners to operate than the BrailleMate, though the BrailleMate offers a unique alternative by including a braille display and a Random Access Memory card storage system. (JDD)

75 FR 55764 - Dynamic Random Access Memory Semiconductors From the Republic of Korea: Preliminary Results of...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-09-14

... lending rates published by the IMF for each year. For countervailable short-term and long-term foreign... administrative reviews. For long-term, won-denominated loans originating in 1986 through 1995, we used the... International Monetary Fund's (``IMF's'') International Financial Statistics Yearbook. For long-term won...

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

NASA Technical Reports Server (NTRS)

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

Switching characteristics for ferroelectric random access memory based on RC model in poly(vinylidene fluoride-trifluoroethylene) ultrathin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, ChangLi; Complex and Intelligent System Research Center, East China University of Science and Technology, Shanghai 200237; Wang, XueJun

2016-05-15

The switching characteristic of the poly(vinylidene fluoride-trifluoroethlene) (P(VDF-TrFE)) films have been studied at different ranges of applied electric field. It is suggest that the increase of the switching speed upon nucleation protocol and the deceleration of switching could be related to the presence of a non-ferroelectric layer. Remarkably, a capacitor and resistor (RC) links model plays significant roles in the polarization switching dynamics of the thin films. For P(VDF-TrFE) ultrathin films with electroactive interlayer, it is found that the switching dynamic characteristics are strongly affected by the contributions of resistor and non-ferroelectric (non-FE) interface factors. A corresponding experiment is designedmore » using poly(3,4-ethylene dioxythiophene):poly(styrene sulfonic) (PEDOT-PSSH) as interlayer with different proton concentrations, and the testing results show that the robust switching is determined by the proton concentration in interlayer and lower leakage current in circuit to reliable applications of such polymer films. These findings provide a new feasible method to enhance the polarization switching for the ferroelectric random access memory.« less

Resistive switching mechanism of ZnO/ZrO2-stacked resistive random access memory device annealed at 300 °C by sol-gel method with forming-free operation

NASA Astrophysics Data System (ADS)

Jian, Wen-Yi; You, Hsin-Chiang; Wu, Cheng-Yen

2018-01-01

In this work, we used a sol-gel process to fabricate a ZnO-ZrO2-stacked resistive switching random access memory (ReRAM) device and investigated its switching mechanism. The Gibbs free energy in ZnO, which is higher than that in ZrO2, facilitates the oxidation and reduction reactions of filaments in the ZnO layer. The current-voltage (I-V) characteristics of the device revealed a forming-free operation because of nonlattice oxygen in the oxide layer. In addition, the device can operate under bipolar or unipolar conditions with a reset voltage of 0 to ±2 V, indicating that in this device, Joule heating dominates at reset and the electric field dominates in the set process. Furthermore, the characteristics reveal why the fabricated device exhibits a greater discrete distribution phenomenon for the set voltage than for the reset voltage. These results will enable the fabrication of future ReRAM devices with double-layer oxide structures with improved characteristics.

Scanning transmission X-ray microscopy probe for in situ mechanism study of graphene-oxide-based resistive random access memory.

PubMed

Nho, Hyun Woo; Kim, Jong Yun; Wang, Jian; Shin, Hyun-Joon; Choi, Sung-Yool; Yoon, Tae Hyun

2014-01-01

Here, an in situ probe for scanning transmission X-ray microscopy (STXM) has been developed and applied to the study of the bipolar resistive switching (BRS) mechanism in an Al/graphene oxide (GO)/Al resistive random access memory (RRAM) device. To perform in situ STXM studies at the C K- and O K-edges, both the RRAM junctions and the I0 junction were fabricated on a single Si3N4 membrane to obtain local XANES spectra at these absorption edges with more delicate I0 normalization. Using this probe combined with the synchrotron-based STXM technique, it was possible to observe unique chemical changes involved in the BRS process of the Al/GO/Al RRAM device. Reversible oxidation and reduction of GO induced by the externally applied bias voltages were observed at the O K-edge XANES feature located at 538.2 eV, which strongly supported the oxygen ion drift model that was recently proposed from ex situ transmission electron microscope studies.

Energetics of intrinsic defects in NiO and the consequences for its resistive random access memory performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dawson, J. A., E-mail: jad95@cam.ac.uk; Guo, Y.; Robertson, J.

2015-09-21

Energetics for a variety of intrinsic defects in NiO are calculated using state-of-the-art ab initio hybrid density functional theory calculations. At the O-rich limit, Ni vacancies are the lowest cost defect for all Fermi energies within the gap, in agreement with the well-known p-type behaviour of NiO. However, the ability of the metal electrode in a resistive random access memory metal-oxide-metal setup to shift the oxygen chemical potential towards the O-poor limit results in unusual NiO behaviour and O vacancies dominating at lower Fermi energy levels. Calculated band diagrams show that O vacancies in NiO are positively charged at themore » operating Fermi energy giving it the advantage of not requiring a scavenger metal layer to maximise drift. Ni and O interstitials are generally found to be higher in energy than the respective vacancies suggesting that significant recombination of O vacancies and interstitials does not take place as proposed in some models of switching behaviour.« less

Error free physically unclonable function with programmed resistive random access memory using reliable resistance states by specific identification-generation method

NASA Astrophysics Data System (ADS)

Tseng, Po-Hao; Hsu, Kai-Chieh; Lin, Yu-Yu; Lee, Feng-Min; Lee, Ming-Hsiu; Lung, Hsiang-Lan; Hsieh, Kuang-Yeu; Chung Wang, Keh; Lu, Chih-Yuan

2018-04-01

A high performance physically unclonable function (PUF) implemented with WO3 resistive random access memory (ReRAM) is presented in this paper. This robust ReRAM-PUF can eliminated bit flipping problem at very high temperature (up to 250 °C) due to plentiful read margin by using initial resistance state and set resistance state. It is also promised 10 years retention at the temperature range of 210 °C. These two stable resistance states enable stable operation at automotive environments from -40 to 125 °C without need of temperature compensation circuit. The high uniqueness of PUF can be achieved by implementing a proposed identification (ID)-generation method. Optimized forming condition can move 50% of the cells to low resistance state and the remaining 50% remain at initial high resistance state. The inter- and intra-PUF evaluations with unlimited separation of hamming distance (HD) are successfully demonstrated even under the corner condition. The number of reproduction was measured to exceed 107 times with 0% bit error rate (BER) at read voltage from 0.4 to 0.7 V.

Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO2 Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

NASA Astrophysics Data System (ADS)

Higuchi, Kazuhide; Miyaji, Kousuke; Johguchi, Koh; Takeuchi, Ken

2012-02-01

This paper proposes a verify-programming method for the resistive random access memory (ReRAM) cell which achieves a 50-times higher endurance and a fast set and reset compared with the conventional method. The proposed verify-programming method uses the incremental pulse width with turnback (IPWWT) for the reset and the incremental voltage with turnback (IVWT) for the set. With the combination of IPWWT reset and IVWT set, the endurance-cycle increases from 48 ×103 to 2444 ×103 cycles. Furthermore, the measured data retention-time after 20 ×103 set/reset cycles is estimated to be 10 years. Additionally, the filamentary based physical model is proposed to explain the set/reset failure mechanism with various set/reset pulse shapes. The reset pulse width and set voltage correspond to the width and length of the conductive-filament, respectively. Consequently, since the proposed IPWWT and IVWT recover set and reset failures of ReRAM cells, the endurance-cycles are improved.

Cross-point-type spin-transfer-torque magnetoresistive random access memory cell with multi-pillar vertical body channel MOSFET

NASA Astrophysics Data System (ADS)

Sasaki, Taro; Endoh, Tetsuo

2018-04-01

In this paper, from the viewpoint of cell size and sensing margin, the impact of a novel cross-point-type one transistor and one magnetic tunnel junction (1T–1MTJ) spin-transfer-torque magnetoresistive random access memory (STT-MRAM) cell with a multi-pillar vertical body channel (BC) MOSFET is shown for high density and wide sensing margin STT-MRAM, with a 10 ns writing period and 1.2 V V DD. For that purpose, all combinations of n/p-type MOSFETs and bottom/top-pin MTJs are compared, where the diameter of MTJ (D MTJ) is scaled down from 55 to 15 nm and the tunnel magnetoresistance (TMR) ratio is increased from 100 to 200%. The results show that, benefiting from the proposed STT-MRAM cell with no back bias effect, the MTJ with a high TMR ratio (200%) can be used in the design of smaller STT-MRAM cells (over 72.6% cell size reduction), which is a difficult task for conventional planar MOSFET based design.

Performance analysis of replication ALOHA for fading mobile communications channels

NASA Technical Reports Server (NTRS)

Yan, Tsun-Yee; Clare, Loren P.

1986-01-01

This paper describes an ALOHA random access protocol for fading communications channels. A two-state Markov model is used for the channel error process to account for the channel fading memory. The ALOHA protocol is modified to send multiple contiguous copies of a message at each transmission attempt. Both pure and slotted ALOHA channels are considered. The analysis is applicable to fading environments where the channel memory is short compared to the propagation delay. It is shown that smaller delay may be achieved using replications and, in noisy conditions, can also improve throughput.

Mitigating Upsets in SRAM-Based FPGAs from the Xilinx Virtex 2 Family

NASA Technical Reports Server (NTRS)

Swift, G. M.; Yui, C. C.; Carmichael, C.; Koga, R.; George, J. S.

2003-01-01

Static random access memory (SRAM) upset rates in field programmable gate arrays (FPGAs) from the Xilinx Virtex 2 family have been tested for radiation effects on configuration memory, block RAM and the power-on-reset (POR) and SelectMAP single event functional interrupts (SEFIs). Dynamic testing has shown the effectiveness and value of Triple Module Redundancy (TMR) and partial reconfiguration when used in conjunction. Continuing dynamic testing for more complex designs and other Virtex 2 capabilities (i.e., I/O standards, digital clock managers (DCM), etc.) is scheduled.

Highly uniform and reliable resistive switching characteristics of a Ni/WOx/p+-Si memory device

NASA Astrophysics Data System (ADS)

Kim, Tae-Hyeon; Kim, Sungjun; Kim, Hyungjin; Kim, Min-Hwi; Bang, Suhyun; Cho, Seongjae; Park, Byung-Gook

2018-02-01

In this paper, we investigate the resistive switching behavior of a bipolar resistive random-access memory (RRAM) in a Ni/WOx/p+-Si RRAM with CMOS compatibility. Highly unifrom and reliable bipolar resistive switching characteristics are observed by a DC voltage sweeping and its switching mechanism can be explained by SCLC model. As a result, the possibility of metal-insulator-silicon (MIS) structural WOx-based RRAM's application to Si-based 1D (diode)-1R (RRAM) or 1T (transistor)-1R (RRAM) structure is demonstrated.

Scalable quantum memory in the ultrastrong coupling regime.

PubMed

Kyaw, T H; Felicetti, S; Romero, G; Solano, E; Kwek, L-C

2015-03-02

Circuit quantum electrodynamics, consisting of superconducting artificial atoms coupled to on-chip resonators, represents a prime candidate to implement the scalable quantum computing architecture because of the presence of good tunability and controllability. Furthermore, recent advances have pushed the technology towards the ultrastrong coupling regime of light-matter interaction, where the qubit-resonator coupling strength reaches a considerable fraction of the resonator frequency. Here, we propose a qubit-resonator system operating in that regime, as a quantum memory device and study the storage and retrieval of quantum information in and from the Z2 parity-protected quantum memory, within experimentally feasible schemes. We are also convinced that our proposal might pave a way to realize a scalable quantum random-access memory due to its fast storage and readout performances.

Scalable quantum memory in the ultrastrong coupling regime

PubMed Central

Kyaw, T. H.; Felicetti, S.; Romero, G.; Solano, E.; Kwek, L.-C.

2015-01-01

Circuit quantum electrodynamics, consisting of superconducting artificial atoms coupled to on-chip resonators, represents a prime candidate to implement the scalable quantum computing architecture because of the presence of good tunability and controllability. Furthermore, recent advances have pushed the technology towards the ultrastrong coupling regime of light-matter interaction, where the qubit-resonator coupling strength reaches a considerable fraction of the resonator frequency. Here, we propose a qubit-resonator system operating in that regime, as a quantum memory device and study the storage and retrieval of quantum information in and from the Z2 parity-protected quantum memory, within experimentally feasible schemes. We are also convinced that our proposal might pave a way to realize a scalable quantum random-access memory due to its fast storage and readout performances. PMID:25727251

Emerging Applications for High K Materials in VLSI Technology

PubMed Central

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

Detrimental effect of interfacial Dzyaloshinskii-Moriya interaction on perpendicular spin-transfer-torque magnetic random access memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jang, Peong-Hwa; Lee, Seo-Won, E-mail: swlee-sci@korea.ac.kr, E-mail: kj-lee@korea.ac.kr; Song, Kyungmi

2015-11-16

Interfacial Dzyaloshinskii-Moriya interaction in ferromagnet/heavy metal bilayers is recently of considerable interest as it offers an efficient control of domain walls and the stabilization of magnetic skyrmions. However, its effect on the performance of perpendicular spin transfer torque memory has not been explored yet. We show based on numerical studies that the interfacial Dzyaloshinskii-Moriya interaction decreases the thermal energy barrier while increases the switching current. As high thermal energy barrier as well as low switching current is required for the commercialization of spin torque memory, our results suggest that the interfacial Dzyaloshinskii-Moriya interaction should be minimized for spin torque memorymore » applications.« less

Rendering of 3D-wavelet-compressed concentric mosaic scenery with progressive inverse wavelet synthesis (PIWS)

NASA Astrophysics Data System (ADS)

Wu, Yunnan; Luo, Lin; Li, Jin; Zhang, Ya-Qin

2000-05-01

The concentric mosaics offer a quick solution to the construction and navigation of a virtual environment. To reduce the vast data amount of the concentric mosaics, a compression scheme based on 3D wavelet transform has been proposed in a previous paper. In this work, we investigate the efficient implementation of the renderer. It is preferable not to expand the compressed bitstream as a whole, so that the memory consumption of the renderer can be reduced. Instead, only the data necessary to render the current view are accessed and decoded. The progressive inverse wavelet synthesis (PIWS) algorithm is proposed to provide the random data access and to reduce the calculation for the data access requests to a minimum. A mixed cache is used in PIWS, where the entropy decoded wavelet coefficient, intermediate result of lifting and fully synthesized pixel are all stored at the same memory unit because of the in- place calculation property of the lifting implementation. PIWS operates with a finite state machine, where each memory unit is attached with a state to indicate what type of content is currently stored. The computational saving achieved by PIWS is demonstrated with extensive experiment results.

Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order

NASA Technical Reports Server (NTRS)

Schwab, Andrew J. (Inventor); Aylor, James (Inventor); Hitchcock, Charles Young (Inventor); Wulf, William A. (Inventor); McKee, Sally A. (Inventor); Moyer, Stephen A. (Inventor); Klenke, Robert (Inventor)

2000-01-01

A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

Solution-processed Al-chelated gelatin for highly transparent non-volatile memory applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, Yu-Chi; Wang, Yeong-Her, E-mail: yhw@ee.ncku.edu.tw

2015-03-23

Using the biomaterial of Al-chelated gelatin (ACG) prepared by sol-gel method in the ITO/ACG/ITO structure, a highly transparent resistive random access memory (RRAM) was obtained. The transmittance of the fabricated device is approximately 83% at 550 nm while that of Al/gelatin/ITO is opaque. As to the ITO/gelatin/ITO RRAM, no resistive switching behavior can be seen. The ITO/ACG/ITO RRAM shows high ON/OFF current ratio (>10{sup 5}), low operation voltage, good uniformity, and retention characteristics at room temperature and 85 °C. The mechanism of the ACG-based memory devices is presented. The enhancement of these electrical properties can be attributed to the chelate effect ofmore » Al ions with gelatin. Results show that transparent ACG-based memory devices possess the potential for next-generation resistive memories and bio-electronic applications.« less

Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor

NASA Astrophysics Data System (ADS)

González, Diego; Botella, Guillermo; García, Carlos; Prieto, Manuel; Tirado, Francisco

2013-12-01

This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, and afterward, creates a custom instruction set, which is then added to the specific design, enhancing the original system. As well, every possible memory combination between on-chip memory and SDRAM has been tested to achieve the best performance. The final throughput of the complete designs are shown. This manuscript outlines a low-cost system, mapped using very large scale integration technology, which accelerates software algorithms by converting them into custom hardware logic blocks and showing the best combination between on-chip memory and SDRAM for the Nios II processor.

Low-power, high-uniform, and forming-free resistive memory based on Mg-deficient amorphous MgO film with rough surface

NASA Astrophysics Data System (ADS)

Guo, Jiajun; Ren, Shuxia; Wu, Liqian; Kang, Xin; Chen, Wei; Zhao, Xu

2018-03-01

Saving energy and reducing operation parameter fluctuations remain crucial for enabling resistive random access memory (RRAM) to emerge as a universal memory. In this work, we report a resistive memory device based on an amorphous MgO (a-MgO) film that not only exhibits ultralow programming voltage (just 0.22 V) and low power consumption (less than 176.7 μW) but also shows excellent operative uniformity (the coefficient of variation is only 1.7% and 2.2% for SET and RESET voltage, respectively). Moreover, it also shows a forming-free characteristic. Further analysis indicates that these distinctive properties can be attributed to the unstable local structures and the rough surface of the Mg-deficient a-MgO film. These findings show the potential of using a-MgO in high-performance nonvolatile memory applications.

Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

NASA Astrophysics Data System (ADS)

Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

2016-04-01

The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

76 FR 66903 - Steel Wire Garment Hangers From the People's Republic of China: Preliminary Results and...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-28

..., Philippines, Peru, Ukraine and Thailand are countries comparable to the PRC in terms of economic development... Random Access Memory Semiconductors from Taiwan, 63 FR 8909, 8932 (February 23, 1998). \\43\\ See, e.g....S. sales of subject merchandise made during the POR, the material terms of sale were established...

System and method for cognitive processing for data fusion

NASA Technical Reports Server (NTRS)

Duong, Tuan A. (Inventor); Duong, Vu A. (Inventor)

2012-01-01

A system and method for cognitive processing of sensor data. A processor array receiving analog sensor data and having programmable interconnects, multiplication weights, and filters provides for adaptive learning in real-time. A static random access memory contains the programmable data for the processor array and the stored data is modified to provide for adaptive learning.

Hybrid computing using a neural network with dynamic external memory.

PubMed

Graves, Alex; Wayne, Greg; Reynolds, Malcolm; Harley, Tim; Danihelka, Ivo; Grabska-Barwińska, Agnieszka; Colmenarejo, Sergio Gómez; Grefenstette, Edward; Ramalho, Tiago; Agapiou, John; Badia, Adrià Puigdomènech; Hermann, Karl Moritz; Zwols, Yori; Ostrovski, Georg; Cain, Adam; King, Helen; Summerfield, Christopher; Blunsom, Phil; Kavukcuoglu, Koray; Hassabis, Demis

2016-10-27

Artificial neural networks are remarkably adept at sensory processing, sequence learning and reinforcement learning, but are limited in their ability to represent variables and data structures and to store data over long timescales, owing to the lack of an external memory. Here we introduce a machine learning model called a differentiable neural computer (DNC), which consists of a neural network that can read from and write to an external memory matrix, analogous to the random-access memory in a conventional computer. Like a conventional computer, it can use its memory to represent and manipulate complex data structures, but, like a neural network, it can learn to do so from data. When trained with supervised learning, we demonstrate that a DNC can successfully answer synthetic questions designed to emulate reasoning and inference problems in natural language. We show that it can learn tasks such as finding the shortest path between specified points and inferring the missing links in randomly generated graphs, and then generalize these tasks to specific graphs such as transport networks and family trees. When trained with reinforcement learning, a DNC can complete a moving blocks puzzle in which changing goals are specified by sequences of symbols. Taken together, our results demonstrate that DNCs have the capacity to solve complex, structured tasks that are inaccessible to neural networks without external read-write memory.

Sparse distributed memory: Principles and operation

NASA Technical Reports Server (NTRS)

Flynn, M. J.; Kanerva, P.; Bhadkamkar, N.

1989-01-01

Sparse distributed memory is a generalized random access memory (RAM) for long (1000 bit) binary words. Such words can be written into and read from the memory, and they can also be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original write address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech recognition and scene analysis, in signal detection and verification, and in adaptive control of automated equipment, in general, in dealing with real world information in real time. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. Major design issues were resolved which were faced in building the memories. The design is described of a prototype memory with 256 bit addresses and from 8 to 128 K locations for 256 bit words. A key aspect of the design is extensive use of dynamic RAM and other standard components.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Better Organic Ternary Memory Performance through Self-Assembled Alkyltrichlorosilane Monolayers on Indium Tin Oxide (ITO) Surfaces.

PubMed

Hou, Xiang; Cheng, Xue-Feng; Zhou, Jin; He, Jing-Hui; Xu, Qing-Feng; Li, Hua; Li, Na-Jun; Chen, Dong-Yun; Lu, Jian-Mei

2017-11-16

Recently, surface engineering of the indium tin oxide (ITO) electrode of sandwich-like organic electric memory devices was found to effectively improve their memory performances. However, there are few methods to modify the ITO substrates. In this paper, we have successfully prepared alkyltrichlorosilane self-assembled monolayers (SAMs) on ITO substrates, and resistive random access memory devices are fabricated on these surfaces. Compared to the unmodified ITO substrates, organic molecules (i.e., 2-((4-butylphenyl)amino)-4-((4-butylphenyl)iminio)-3-oxocyclobut-1-en-1-olate, SA-Bu) grown on these SAM-modified ITO substrates have rougher surface morphologies but a smaller mosaicity. The organic layer on the SAM-modified ITO further aged to eliminate the crystalline phase diversity. In consequence, the ternary memory yields are effectively improved to approximately 40-47 %. Our results suggest that the insertion of alkyltrichlorosilane self-assembled monolayers could be an efficient method to improve the performance of organic memory devices. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Improvement of Bipolar Switching Properties of Gd:SiOx RRAM Devices on Indium Tin Oxide Electrode by Low-Temperature Supercritical CO2 Treatment.

PubMed

Chen, Kai-Huang; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Liang, Shu-Ping; Young, Tai-Fa; Syu, Yong-En; Sze, Simon M

2016-12-01

Bipolar switching resistance behaviors of the Gd:SiO2 resistive random access memory (RRAM) devices on indium tin oxide electrode by the low-temperature supercritical CO2-treated technology were investigated. For physical and electrical measurement results obtained, the improvement on oxygen qualities, properties of indium tin oxide electrode, and operation current of the Gd:SiO2 RRAM devices were also observed. In addition, the initial metallic filament-forming model analyses and conduction transferred mechanism in switching resistance properties of the RRAM devices were verified and explained. Finally, the electrical reliability and retention properties of the Gd:SiO2 RRAM devices for low-resistance state (LRS)/high-resistance state (HRS) in different switching cycles were also measured for applications in nonvolatile random memory devices.

Fast decoding techniques for extended single-and-double-error-correcting Reed Solomon codes

NASA Technical Reports Server (NTRS)

Costello, D. J., Jr.; Deng, H.; Lin, S.

1984-01-01

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.

INM. Integrated Noise Model Version 4.11. User’s Guide - Supplement

DTIC Science & Technology

1993-12-01

KB of Random Access Memory (RAM) or 3 MB of RAM, if operating the INM from a RAM disk, as discussed in Section 1.2.1 below; 0 Math co-processor, Series... accessible from the Data Base using the ACDB11.EXE computer program, supplied with the Version 4.11 release. With the exception of INM airplane numbers 1, 6...9214 10760 -- -.-- 27 7053 6215 9470 10703 --- --- - 28 SS7 5940 SS94 729S . ... ... 29 4223 4884 7897 9214 10760 ..... 30 sots 6474 7939 8774

Efficient Graph Based Assembly of Short-Read Sequences on Hybrid Core Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sczyrba, Alex; Pratap, Abhishek; Canon, Shane

2011-03-22

Advanced architectures can deliver dramatically increased throughput for genomics and proteomics applications, reducing time-to-completion in some cases from days to minutes. One such architecture, hybrid-core computing, marries a traditional x86 environment with a reconfigurable coprocessor, based on field programmable gate array (FPGA) technology. In addition to higher throughput, increased performance can fundamentally improve research quality by allowing more accurate, previously impractical approaches. We will discuss the approach used by Convey?s de Bruijn graph constructor for short-read, de-novo assembly. Bioinformatics applications that have random access patterns to large memory spaces, such as graph-based algorithms, experience memory performance limitations on cache-based x86more » servers. Convey?s highly parallel memory subsystem allows application-specific logic to simultaneously access 8192 individual words in memory, significantly increasing effective memory bandwidth over cache-based memory systems. Many algorithms, such as Velvet and other de Bruijn graph based, short-read, de-novo assemblers, can greatly benefit from this type of memory architecture. Furthermore, small data type operations (four nucleotides can be represented in two bits) make more efficient use of logic gates than the data types dictated by conventional programming models.JGI is comparing the performance of Convey?s graph constructor and Velvet on both synthetic and real data. We will present preliminary results on memory usage and run time metrics for various data sets with different sizes, from small microbial and fungal genomes to very large cow rumen metagenome. For genomes with references we will also present assembly quality comparisons between the two assemblers.« less

Impact of AlO x layer on resistive switching characteristics and device-to-device uniformity of bilayered HfO x -based resistive random access memory devices

NASA Astrophysics Data System (ADS)

Chuang, Kai-Chi; Chung, Hao-Tung; Chu, Chi-Yan; Luo, Jun-Dao; Li, Wei-Shuo; Li, Yi-Shao; Cheng, Huang-Chung

2018-06-01

An AlO x layer was deposited on HfO x , and bilayered dielectric films were found to confine the formation locations of conductive filaments (CFs) during the forming process and then improve device-to-device uniformity. In addition, the Ti interposing layer was also adopted to facilitate the formation of oxygen vacancies. As a result, the resistive random access memory (RRAM) device with TiN/Ti/AlO x (1 nm)/HfO x (6 nm)/TiN stack layers demonstrated excellent device-to-device uniformity although it achieved slightly larger resistive switching characteristics, which were forming voltage (V Forming) of 2.08 V, set voltage (V Set) of 1.96 V, and reset voltage (V Reset) of ‑1.02 V, than the device with TiN/Ti/HfO x (6 nm)/TiN stack layers. However, the device with a thicker 2-nm-thick AlO x layer showed worse uniformity than the 1-nm-thick one. It was attributed to the increased oxygen atomic percentage in the bilayered dielectric films of the 2-nm-thick one. The difference in oxygen content showed that there would be less oxygen vacancies to form CFs. Therefore, the random growth of CFs would become severe and the device-to-device uniformity would degrade.

77 FR 46058 - Utility Scale Wind Towers From the Socialist Republic of Vietnam: Preliminary Determination of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-08-02

... Sale, Comment 1. Sales during the POI were made pursuant to long-term contracts, and/or purchase orders..., the material terms appear to be fixed, pursuant to the long-term agreement, and are reflected in the...: Dynamic Random Access Memory Semiconductors of One Megabit and Above From the Republic of Korea, 57 FR...

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Analysis of the Bipolar Resistive Switching Behavior of a Biocompatible Glucose Film for Resistive Random Access Memory.

PubMed

Park, Sung Pyo; Tak, Young Jun; Kim, Hee Jun; Lee, Jin Hyeok; Yoo, Hyukjoon; Kim, Hyun Jae

2018-06-01

Resistive random access memory (RRAM) devices are fabricated through a simple solution process using glucose, which is a natural biomaterial for the switching layer of RRAM. The fabricated glucose-based RRAM device shows nonvolatile bipolar resistive switching behavior, with a switching window of 10 3 . In addition, the endurance and data retention capability of glucose-based RRAM exhibit stable characteristics up to 100 consecutive cycles and 10 4 s under constant voltage stress at 0.3 V. The interface between the top electrode and the glucose film is carefully investigated to demonstrate the bipolar switching mechanism of the glucose-based RRAM device. The glucose based-RRAM is also evaluated on a polyimide film to verify the possibility of a flexible platform. Additionally, a cross-bar array structure with a magnesium electrode is prepared on various substrates to assess the degradability and biocompatibility for the implantable bioelectronic devices, which are harmless and nontoxic to the human body. It is expected that this research can provide meaningful insights for developing the future bioelectronic devices. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Full-switching FSF-type superconducting spin-triplet magnetic random access memory element

NASA Astrophysics Data System (ADS)

Lenk, D.; Morari, R.; Zdravkov, V. I.; Ullrich, A.; Khaydukov, Yu.; Obermeier, G.; Müller, C.; Sidorenko, A. S.; von Nidda, H.-A. Krug; Horn, S.; Tagirov, L. R.; Tidecks, R.

2017-11-01

In the present work a superconducting Co/CoOx/Cu41Ni59 /Nb/Cu41Ni59 nanoscale thin film heterostructure is investigated, which exhibits a superconducting transition temperature, Tc, depending on the history of magnetic field applied parallel to the film plane. In more detail, around zero applied field, Tc is lower when the field is changed from negative to positive polarity (with respect to the cooling field), compared to the opposite case. We interpret this finding as the result of the generation of the odd-in-frequency triplet component of superconductivity arising at noncollinear orientation of the magnetizations in the Cu41Ni59 layer adjacent to the CoOx layer. This interpretation is supported by superconducting quantum interference device magnetometry, which revealed a correlation between details of the magnetic structure and the observed superconducting spin-valve effects. Readout of information is possible at zero applied field and, thus, no permanent field is required to stabilize both states. Consequently, this system represents a superconducting magnetic random access memory element for superconducting electronics. By applying increased transport currents, the system can be driven to the full switching mode between the completely superconducting and the normal state.

Switching characteristics in Cu:SiO2 by chemical soak methods for resistive random access memory (ReRAM)

NASA Astrophysics Data System (ADS)

Chin, Fun-Tat; Lin, Yu-Hsien; Yang, Wen-Luh; Liao, Chin-Hsuan; Lin, Li-Min; Hsiao, Yu-Ping; Chao, Tien-Sheng

2015-01-01

A limited copper (Cu)-source Cu:SiO2 switching layer composed of various Cu concentrations was fabricated using a chemical soaking (CS) technique. The switching layer was then studied for developing applications in resistive random access memory (ReRAM) devices. Observing the resistive switching mechanism exhibited by all the samples suggested that Cu conductive filaments formed and ruptured during the set/reset process. The experimental results indicated that the endurance property failure that occurred was related to the joule heating effect. Moreover, the endurance switching cycle increased as the Cu concentration decreased. In high-temperature tests, the samples demonstrated that the operating (set/reset) voltages decreased as the temperature increased, and an Arrhenius plot was used to calculate the activation energy of the set/reset process. In addition, the samples demonstrated stable data retention properties when baked at 85 °C, but the samples with low Cu concentrations exhibited short retention times in the low-resistance state (LRS) during 125 °C tests. Therefore, Cu concentration is a crucial factor in the trade-off between the endurance and retention properties; furthermore, the Cu concentration can be easily modulated using this CS technique.

Thermal characterization and analysis of phase change random access memory

NASA Astrophysics Data System (ADS)

Giraud, V.; Cluzel, J.; Sousa, V.; Jacquot, A.; Dauscher, A.; Lenoir, B.; Scherrer, H.; Romer, S.

2005-07-01

The cross-plane thermal conductivity of Ge2Sb2Te5, either in its amorphous state or fcc crystallized state, and titanium nitride (TiN) thin films has been measured at room temperature by the 3ω method. These materials are involved in the fabrication of phase change random access memory (PC-RAM), Ge2Sb2Te5 and TiN being the PC and pseudoelectrode materials, respectively. The thermal conductivity of insulating SiO2 and ZnS :SiO2 layers was determined too. Each thermal conductivity measurement was performed by the means of at least two strip widths in order to check both the measurement self-consistency and the measurement accuracy. The performance of PC-RAM cells, i.e., the time needed to reach the melting temperature of the PC material and the cooling speed, has been evaluated as a function of both the measured thermal conductivity of the PC material and the reset current intensity independently of the thermal properties of the pseudoelectrodes by the way of analytical formula. The influence of the thickness and the thermal properties of the pseudoelectrodes on the performances have been determined by numerical simulations.

Breaking the current density threshold in spin-orbit-torque magnetic random access memory

NASA Astrophysics Data System (ADS)

Zhang, Yin; Yuan, H. Y.; Wang, X. S.; Wang, X. R.

2018-04-01

Spin-orbit-torque magnetic random access memory (SOT-MRAM) is a promising technology for the next generation of data storage devices. The main bottleneck of this technology is the high reversal current density threshold. This outstanding problem is now solved by a new strategy in which the magnitude of the driven current density is fixed while the current direction varies with time. The theoretical limit of minimal reversal current density is only a fraction (the Gilbert damping coefficient) of the threshold current density of the conventional strategy. The Euler-Lagrange equation for the fastest magnetization reversal path and the optimal current pulse is derived for an arbitrary magnetic cell and arbitrary spin-orbit torque. The theoretical limit of minimal reversal current density and current density for a GHz switching rate of the new reversal strategy for CoFeB/Ta SOT-MRAMs are, respectively, of the order of 105 A/cm 2 and 106 A/cm 2 far below 107 A/cm 2 and 108 A/cm 2 in the conventional strategy. Furthermore, no external magnetic field is needed for a deterministic reversal in the new strategy.

Hf layer thickness dependence of resistive switching characteristics of Ti/Hf/HfO2/Au resistive random access memory device

NASA Astrophysics Data System (ADS)

Nakajima, Ryo; Azuma, Atsushi; Yoshida, Hayato; Shimizu, Tomohiro; Ito, Takeshi; Shingubara, Shoso

2018-06-01

Resistive random access memory (ReRAM) devices with a HfO2 dielectric layer have been studied extensively owing to the good reproducibility of their SET/RESET switching properties. Furthermore, it was reported that a thin Hf layer next to a HfO2 layer stabilized switching properties because of the oxygen scavenging effect. In this work, we studied the Hf thickness dependence of the resistance switching characteristics of a Ti/Hf/HfO2/Au ReRAM device. It is found that the optimum Hf thickness is approximately 10 nm to obtain good reproducibility of SET/RESET voltages with a small RESET current. However, when the Hf thickness was very small (∼2 nm), the device failed after the first RESET process owing to the very large RESET current. In the case of a very thick Hf layer (∼20 nm), RESET did not occur owing to the formation of a leaky dielectric layer. We observed the occurrence of multiple resistance states in the RESET process of the device with a Hf thickness of 10 nm by increasing the RESET voltage stepwise.

Plasma-Assisted Dry Etching of Ferroelectric Capacitor Modules and Application to a 32M Ferroelectric Random Access Memory Devices with Submicron Feature Sizes

NASA Astrophysics Data System (ADS)

Lee, Sang-Woo; Joo, Suk-Ho; Cho, Sung Lae; Son, Yoon-Ho; Lee, Kyu-Mann; Nam, Sang-Don; Park, Kun-Sang; Lee, Yong-Tak; Seo, Jung-Suk; Kim, Young-Dae; An, Hyeong-Geun; Kim, Hyoung-Joon; Jung, Yong-Ju; Heo, Jang-Eun; Lee, Moon-Sook; Park, Soon-Oh; Chung, U-In; Moon, Joo-Tae

2002-11-01

In the manufacturing of a 32M ferroelectric random access memory (FRAM) device on the basis of 0.25 design rule (D/R), one of the most difficult processes is to pattern a submicron capacitor module while retaining good ferroelectric properties. In this paper, we report the ferroelectric property of patterned submicron capacitor modules with a stack height of 380 nm, where the 100 nm-thick Pb(Zr, Ti)O3 (PZT) films were prepared by the sol-gel method. After patterning, overall sidewall slope was approximately 70° and cell-to-cell node separation was made to be 80 nm to prevent possible twin-bit failure in the device. Finally, several heat treatment conditions were investigated to retain the ferroelectric property of the patterned capacitor. It was found that rapid thermal processing (RTP) treatment yields better properties than conventional furnace annealing. This result is directly related to the near-surface chemistry of the PZT films, as confirmed by X-ray photoelectron spectroscopy (XPS) analysis. The resultant switching polarization value of the submicron capacitor was approximately 30 μC/cm2 measured at 3 V.

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell

NASA Astrophysics Data System (ADS)

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-06-01

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr03169b

Light sensitivity of a one transistor-one capacitor memory cell when used as a micromirror actuator in projector applications

NASA Astrophysics Data System (ADS)

Huffman, James Douglas

2001-11-01

The most important issue facing the future business success of the Digital Micromirror Device or DMD™ produced by Texas Instruments is the cost of the actual device. As the business and consumer markets call for higher resolution displays, the array size will have to be increased to incorporate more pixels. The manufacturing costs associated with building these higher resolution displays follow an exponential relation with the number of pixels due to yield loss and reduced number of chips per silicon wafer. Each pixel is actuated by electrostatics that are provided by a memory cell that is built in the underlying silicon substrate. One way to decrease cost of the wafer is to change the memory cell architecture from a static random access configuration or SRAM to a dynamic random access configuration or DRAM. This change has the benefits of having fewer components per area and a lower metal density. This reduction in the component count and metal density has a dramatic effect on the yield of the memory array by reducing the particle sensitivity of the underlying cell. The main drawback to using a DRAM configuration in a display application is the light sensitivity of a charge storage device built in the silicon substrate. As the photons pass through the mechanical micromirrors and illuminate the DRAM cell, the effective electrostatic potential of the memory element used for the mirror actuation is reduced. This dissertation outlines the issues associated with the light sensitivity of a DRAM memory cell as the actuation element for a micromirror. The concept of charge depletion on a silicon capacitor due to recombination of photogenerated carriers is explored and experimentally verified. The effects of the reduced potential on the capacitor on the micromirror are also explored. Optical modeling is used to determine the incoming photon flux to determine the benefits of adding a charge recombination region as part of the DRAM memory cell. Several options are explored to reduce the effect of the incoming photons on the potential of the memory cell. The results will show that a 1T1C memory cell with N-type recombination regions and maximum light shielding is sufficient for a projector application.

Exercise reduces diet-induced cognitive decline and increases hippocampal brain-derived neurotrophic factor in CA3 neurons

PubMed Central

Noble, Emily E.; Mavanji, Vijayakumar; Little, Morgan R.; Billington, Charles J.; Kotz, Catherine M.; Wang, ChuanFeng

2014-01-01

Background Previous studies have shown that a western diet impairs, whereas physical exercise enhances hippocampus-dependent learning and memory. Both diet and exercise influence expression of hippocampal brain-derived neurotrophic factor (BDNF), which is associated with improved cognition. We hypothesized that exercise reverses diet-induced cognitive decline while increasing hippocampal BDNF. Methods To test the effects of exercise on hippocampal-dependent memory, we compared cognitive scores of Sprague-Dawley rats exercised by voluntary running wheel (RW) access or forced treadmill (TM) to sedentary (Sed) animals. Memory was tested by two-way active avoidance test (TWAA), in which animals are exposed to a brief shock in a specific chamber area. When an animal avoids, escapes or has reduced latency to do either, this is considered a measure of memory. In a second experiment, rats were fed either a high-fat diet or control diet for 16 weeks, then randomly assigned to running wheel access or sedentary condition, and TWAA memory was tested once a week for seven weeks of exercise intervention. Results Both groups of exercised animals had improved memory as indicated by reduced latency to avoid and escape shock, and increased avoid and escape episodes (p<0.05). Exposure to a high-fat diet resulted in poor performance during both the acquisition and retrieval phases of the memory test as compared to controls. Exercise reversed high-fat diet-induced memory impairment, and increased brain-derived neurotrophic factor (BDNF) in neurons of the hippocampal CA3 region. Conclusions These data suggest that exercise improves memory retrieval, particularly with respect to avoiding aversive stimuli, and may be beneficial in protecting against diet induced cognitive decline, likely via elevated BDNF in neurons of the CA3 region. PMID:24755094

Exercise reduces diet-induced cognitive decline and increases hippocampal brain-derived neurotrophic factor in CA3 neurons.

PubMed

Noble, Emily E; Mavanji, Vijayakumar; Little, Morgan R; Billington, Charles J; Kotz, Catherine M; Wang, ChuanFeng

2014-10-01

Previous studies have shown that a western diet impairs, whereas physical exercise enhances hippocampus-dependent learning and memory. Both diet and exercise influence expression of hippocampal brain-derived neurotrophic factor (BDNF), which is associated with improved cognition. We hypothesized that exercise reverses diet-induced cognitive decline while increasing hippocampal BDNF. To test the effects of exercise on hippocampal-dependent memory, we compared cognitive scores of Sprague-Dawley rats exercised by voluntary running wheel (RW) access or forced treadmill (TM) to sedentary (Sed) animals. Memory was tested by two-way active avoidance test (TWAA), in which animals are exposed to a brief shock in a specific chamber area. When an animal avoids, escapes or has reduced latency to do either, this is considered a measure of memory. In a second experiment, rats were fed either a high-fat diet or control diet for 16 weeks, then randomly assigned to running wheel access or sedentary condition, and TWAA memory was tested once a week for 7 weeks of exercise intervention. Both groups of exercised animals had improved memory as indicated by reduced latency to avoid and escape shock, and increased avoid and escape episodes (p<0.05). Exposure to a high-fat diet resulted in poor performance during both the acquisition and retrieval phases of the memory test as compared to controls. Exercise reversed high-fat diet-induced memory impairment, and increased brain-derived neurotrophic factor (BDNF) in neurons of the hippocampal CA3 region. These data suggest that exercise improves memory retrieval, particularly with respect to avoiding aversive stimuli, and may be beneficial in protecting against diet induced cognitive decline, likely via elevated BDNF in neurons of the CA3 region. Published by Elsevier Inc.

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

NASA Technical Reports Server (NTRS)

1972-01-01

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

A new approach for implementation of associative memory using volume holographic materials

NASA Astrophysics Data System (ADS)

Habibi, Mohammad; Pashaie, Ramin

2012-02-01

Associative memory, also known as fault tolerant or content-addressable memory, has gained considerable attention in last few decades. This memory possesses important advantages over the more common random access memories since it provides the capability to correct faults and/or partially missing information in a given input pattern. There is general consensus that optical implementation of connectionist models and parallel processors including associative memory has a better record of success compared to their electronic counterparts. In this article, we describe a novel optical implementation of associative memory which not only has the advantage of all optical learning and recalling capabilities, it can also be realized easily. We present a new approach, inspired by tomographic imaging techniques, for holographic implementation of associative memories. In this approach, a volume holographic material is sandwiched within a matrix of inputs (optical point sources) and outputs (photodetectors). The memory capacity is realized by the spatial modulation of refractive index of the holographic material. Constructing the spatial distribution of the refractive index from an array of known inputs and outputs is formulated as an inverse problem consisting a set of linear integral equations.

Holographic memories with encryption-selectable function

NASA Astrophysics Data System (ADS)

Su, Wei-Chia; Lee, Xuan-Hao

2006-03-01

Volume holographic storage has received increasing attention owing to its potential high storage capacity and access rate. In the meanwhile, encrypted holographic memory using random phase encoding technique is attractive for an optical community due to growing demand for protection of information. In this paper, encryption-selectable holographic storage algorithms in LiNbO 3 using angular multiplexing are proposed and demonstrated. Encryption-selectable holographic memory is an advance concept of security storage for content protection. It offers more flexibility to encrypt the data or not optionally during the recording processes. In our system design, the function of encryption and non-encryption storage is switched by a random phase pattern and a uniform phase pattern. Based on a 90-degree geometry, the input patterns including the encryption and non-encryption storage are stored via angular multiplexing with reference plane waves at different incident angles. Image is encrypted optionally by sliding the ground glass into one of the recording waves or removing it away in each exposure. The ground glass is a key for encryption. Besides, it is also an important key available for authorized user to decrypt the encrypted information.

Face classification using electronic synapses

NASA Astrophysics Data System (ADS)

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H.-S. Philip; Qian, He

2017-05-01

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

Face classification using electronic synapses.

PubMed

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H-S Philip; Qian, He

2017-05-12

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

High speed magneto-resistive random access memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

1992-01-01

A high speed read MRAM memory element is configured from a sandwich of magnetizable, ferromagnetic film surrounding a magneto-resistive film which may be ferromagnetic or not. One outer ferromagnetic film has a higher coercive force than the other and therefore remains magnetized in one sense while the other may be switched in sense by a switching magnetic field. The magneto-resistive film is therefore sensitive to the amplitude of the resultant field between the outer ferromagnetic films and may be constructed of a high resistivity, high magneto-resistive material capable of higher sensing currents. This permits higher read voltages and therefore faster read operations. Alternate embodiments with perpendicular anisotropy, and in-plane anisotropy are shown, including an embodiment which uses high permeability guides to direct the closing flux path through the magneto-resistive material. High density, high speed, radiation hard, memory matrices may be constructed from these memory elements.

Memory-based frame synchronizer. [for digital communication systems

NASA Technical Reports Server (NTRS)

Stattel, R. J.; Niswander, J. K. (Inventor)

1981-01-01

A frame synchronizer for use in digital communications systems wherein data formats can be easily and dynamically changed is described. The use of memory array elements provide increased flexibility in format selection and sync word selection in addition to real time reconfiguration ability. The frame synchronizer comprises a serial-to-parallel converter which converts a serial input data stream to a constantly changing parallel data output. This parallel data output is supplied to programmable sync word recognizers each consisting of a multiplexer and a random access memory (RAM). The multiplexer is connected to both the parallel data output and an address bus which may be connected to a microprocessor or computer for purposes of programming the sync word recognizer. The RAM is used as an associative memory or decorder and is programmed to identify a specific sync word. Additional programmable RAMs are used as counter decoders to define word bit length, frame word length, and paragraph frame length.

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

DOEpatents

Ohmacht, Martin

2017-08-15

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

DOEpatents

Ohmacht, Martin

2014-09-09

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Fast and Efficient XML Data Access for Next-Generation Mass Spectrometry.

PubMed

Röst, Hannes L; Schmitt, Uwe; Aebersold, Ruedi; Malmström, Lars

2015-01-01

In mass spectrometry-based proteomics, XML formats such as mzML and mzXML provide an open and standardized way to store and exchange the raw data (spectra and chromatograms) of mass spectrometric experiments. These file formats are being used by a multitude of open-source and cross-platform tools which allow the proteomics community to access algorithms in a vendor-independent fashion and perform transparent and reproducible data analysis. Recent improvements in mass spectrometry instrumentation have increased the data size produced in a single LC-MS/MS measurement and put substantial strain on open-source tools, particularly those that are not equipped to deal with XML data files that reach dozens of gigabytes in size. Here we present a fast and versatile parsing library for mass spectrometric XML formats available in C++ and Python, based on the mature OpenMS software framework. Our library implements an API for obtaining spectra and chromatograms under memory constraints using random access or sequential access functions, allowing users to process datasets that are much larger than system memory. For fast access to the raw data structures, small XML files can also be completely loaded into memory. In addition, we have improved the parsing speed of the core mzML module by over 4-fold (compared to OpenMS 1.11), making our library suitable for a wide variety of algorithms that need fast access to dozens of gigabytes of raw mass spectrometric data. Our C++ and Python implementations are available for the Linux, Mac, and Windows operating systems. All proposed modifications to the OpenMS code have been merged into the OpenMS mainline codebase and are available to the community at https://github.com/OpenMS/OpenMS.

Fast and Efficient XML Data Access for Next-Generation Mass Spectrometry

PubMed Central

Röst, Hannes L.; Schmitt, Uwe; Aebersold, Ruedi; Malmström, Lars

2015-01-01

Motivation In mass spectrometry-based proteomics, XML formats such as mzML and mzXML provide an open and standardized way to store and exchange the raw data (spectra and chromatograms) of mass spectrometric experiments. These file formats are being used by a multitude of open-source and cross-platform tools which allow the proteomics community to access algorithms in a vendor-independent fashion and perform transparent and reproducible data analysis. Recent improvements in mass spectrometry instrumentation have increased the data size produced in a single LC-MS/MS measurement and put substantial strain on open-source tools, particularly those that are not equipped to deal with XML data files that reach dozens of gigabytes in size. Results Here we present a fast and versatile parsing library for mass spectrometric XML formats available in C++ and Python, based on the mature OpenMS software framework. Our library implements an API for obtaining spectra and chromatograms under memory constraints using random access or sequential access functions, allowing users to process datasets that are much larger than system memory. For fast access to the raw data structures, small XML files can also be completely loaded into memory. In addition, we have improved the parsing speed of the core mzML module by over 4-fold (compared to OpenMS 1.11), making our library suitable for a wide variety of algorithms that need fast access to dozens of gigabytes of raw mass spectrometric data. Availability Our C++ and Python implementations are available for the Linux, Mac, and Windows operating systems. All proposed modifications to the OpenMS code have been merged into the OpenMS mainline codebase and are available to the community at https://github.com/OpenMS/OpenMS. PMID:25927999

Multi-wavelength access gate for WDM-formatted words in optical RAM row architectures

NASA Astrophysics Data System (ADS)

Fitsios, D.; Alexoudi, T.; Vagionas, C.; Miliou, A.; Kanellos, G. T.; Pleros, N.

2013-03-01

Optical RAM has emerged as a promising solution for overcoming the "Memory Wall" of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.

Resistance controllability and variability improvement in a TaO{sub x}-based resistive memory for multilevel storage application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Prakash, A., E-mail: amitknp@postech.ac.kr, E-mail: amit.knp02@gmail.com, E-mail: hwanghs@postech.ac.kr; Song, J.; Hwang, H., E-mail: amitknp@postech.ac.kr, E-mail: amit.knp02@gmail.com, E-mail: hwanghs@postech.ac.kr

In order to obtain reliable multilevel cell (MLC) characteristics, resistance controllability between the different resistance levels is required especially in resistive random access memory (RRAM), which is prone to resistance variability mainly due to its intrinsic random nature of defect generation and filament formation. In this study, we have thoroughly investigated the multilevel resistance variability in a TaO{sub x}-based nanoscale (<30 nm) RRAM operated in MLC mode. It is found that the resistance variability not only depends on the conductive filament size but also is a strong function of oxygen vacancy concentration in it. Based on the gained insights through experimentalmore » observations and simulation, it is suggested that forming thinner but denser conductive filament may greatly improve the temporal resistance variability even at low operation current despite the inherent stochastic nature of resistance switching process.« less

Poly(3,4-ethylenedioxythiophene)-Poly(styrenesulfonate) Interlayer Insertion Enables Organic Quaternary Memory.

PubMed

Cheng, Xue-Feng; Hou, Xiang; Qian, Wen-Hu; He, Jing-Hui; Xu, Qing-Feng; Li, Hua; Li, Na-Jun; Chen, Dong-Yun; Lu, Jian-Mei

2017-08-23

Herein, for the first time, quaternary resistive memory based on an organic molecule is achieved via surface engineering. A layer of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT-PSS) was inserted between the indium tin oxide (ITO) electrode and the organic layer (squaraine, SA-Bu) to form an ITO/PEDOT-PSS/SA-Bu/Al architecture. The modified resistive random-access memory (RRAM) devices achieve quaternary memory switching with the highest yield (∼41%) to date. Surface morphology, crystallinity, and mosaicity of the deposited organic grains are greatly improved after insertion of a PEDOT-PSS interlayer, which provides better contacts at the grain boundaries as well as the electrode/active layer interface. The PEDOT-PSS interlayer also reduces the hole injection barrier from the electrode to the active layer. Thus, the threshold voltage of each switching is greatly reduced, allowing for more quaternary switching in a certain voltage window. Our results provide a simple yet powerful strategy as an alternative to molecular design to achieve organic quaternary resistive memory.

Electrically-controlled nonlinear switching and multi-level storage characteristics in WOx film-based memory cells

NASA Astrophysics Data System (ADS)

Duan, W. J.; Wang, J. B.; Zhong, X. L.

2018-05-01

Resistive switching random access memory (RRAM) is considered as a promising candidate for the next generation memory due to its scalability, high integration density and non-volatile storage characteristics. Here, the multiple electrical characteristics in Pt/WOx/Pt cells are investigated. Both of the nonlinear switching and multi-level storage can be achieved by setting different compliance current in the same cell. The correlations among the current, time and temperature are analyzed by using contours and 3D surfaces. The switching mechanism is explained in terms of the formation and rupture of conductive filament which is related to oxygen vacancies. The experimental results show that the non-stoichiometric WOx film-based device offers a feasible way for the applications of oxide-based RRAMs.

Advanced Compact Holographic Data Storage System

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin; Zhou, Hanying; Reyes, George

2000-01-01

JPL, under current sponsorship from NASA Space Science and Earth Science Programs, is developing a high-density, nonvolatile and rad-hard Advanced Holographic Memory (AHM) system to enable large-capacity, high-speed, low power consumption, and read/write of data in a space environment. The entire read/write operation will be controlled with electro-optic mechanism without any moving parts. This CHDS will consist of laser diodes, photorefractive crystal, spatial light modulator, photodetector array, and I/O electronic interface. In operation, pages of information would be recorded and retrieved with random access and highspeed. The nonvolatile, rad-hard characteristics of the holographic memory will provide a revolutionary memory technology to enhance mission capabilities for all NASA's Earth Science Mission. In this paper, recent technology progress in developing this CHDS at JPL will be presented.

Hydrocarbon-Fueled Scramjet Research at Hypersonic Mach Numbers

DTIC Science & Technology

2005-03-31

oxide O atomic oxygen 02 molecular oxygen OH hydroxyl radical ppm parts per million PD photodiode PLLF planar laser-induced fluorescence PMT...photomultiplier tube RAM random access memory RANS Reynolds-averaged Navier-Stokes RET rotational energy transfer TDLAS tunable diode laser absorption...here extend this knowledge base to flight at Mach 11.5. Griffiths (2004) used a tunable diode laser absorption spectroscopy ( TDLAS ) system to measure

Application of RADSAFE to Model Single Event Upset Response of a 0.25 micron CMOS SRAM

NASA Technical Reports Server (NTRS)

Warren, Kevin M.; Weller, Robert A.; Sierawski, Brian; Reed, Robert A.; Mendenhall, Marcus H.; Schrimpf, Ronald D.; Massengill, Lloyd; Porter, Mark; Wilkerson, Jeff; LaBel, Kenneth A.;

Radiation Response of Emerging FeRAM Technology

NASA Technical Reports Server (NTRS)

Nguyen, D. N.; Scheick, L. Z.

2001-01-01

The test results of measurements performed on two different sizes of ferroelectric random access memory (FeRAM) suggest the degradation is due to the low radiation tolerance of sense amplifiers and reference voltage generators which are based on commercial complementary metal oxide semiconductor (CMOS) technology. This paper presents total ionizing dose (TID) testing of 64Kb Ramtron FM1608 and 256Kb Ramtron FM1808.

Characterization and Physics-Based Modeling of Electrochemical Memristors

DTIC Science & Technology

2015-11-16

conducting films that result from electrical or optical stress. Model parameters and electrical characteristics were obtained from and validated...x- ray scattering, Conductive Bridge Random Access Memory 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT 18. NUMBER OF PAGES 19a. NAME...Calculated DOS for GeSe2 in valence band and (b) conduction band .................. 43  Figure 45. DFT band structure for crystalline GeSe2

Method and apparatus for managing access to a memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeBenedictis, Erik

A method and apparatus for managing access to a memory of a computing system. A controller transforms a plurality of operations that represent a computing job into an operational memory layout that reduces a size of a selected portion of the memory that needs to be accessed to perform the computing job. The controller stores the operational memory layout in a plurality of memory cells within the selected portion of the memory. The controller controls a sequence by which a processor in the computing system accesses the memory to perform the computing job using the operational memory layout. The operationalmore » memory layout reduces an amount of energy consumed by the processor to perform the computing job.« less

Experimental realization of a multiplexed quantum memory with 225 individually accessible memory cells.

PubMed

Pu, Y-F; Jiang, N; Chang, W; Yang, H-X; Li, C; Duan, L-M

2017-05-08

To realize long-distance quantum communication and quantum network, it is required to have multiplexed quantum memory with many memory cells. Each memory cell needs to be individually addressable and independently accessible. Here we report an experiment that realizes a multiplexed DLCZ-type quantum memory with 225 individually accessible memory cells in a macroscopic atomic ensemble. As a key element for quantum repeaters, we demonstrate that entanglement with flying optical qubits can be stored into any neighboring memory cells and read out after a programmable time with high fidelity. Experimental realization of a multiplexed quantum memory with many individually accessible memory cells and programmable control of its addressing and readout makes an important step for its application in quantum information technology.

On the origin of resistive switching volatility in Ni/TiO{sub 2}/Ni stacks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cortese, Simone, E-mail: simone.cortese@soton.ac.uk; Trapatseli, Maria; Khiat, Ali

2016-08-14

Resistive switching and resistive random access memories have attracted huge interest for next generation nonvolatile memory applications, also thought to be able to overcome flash memories limitations when arranged in crossbar arrays. A cornerstone of their potential success is that the toggling between two distinct resistance states, usually a High Resistive State (HRS) and a Low Resistive State (LRS), is an intrinsic non-volatile phenomenon with the two states being thermodynamically stable. TiO{sub 2} is one of the most common materials known to support non-volatile RS. In this paper, we report a volatile resistive switching in a titanium dioxide thin filmmore » sandwiched by two nickel electrodes. The aim of this work is to understand the underlying physical mechanism that triggers the volatile effect, which is ascribed to the presence of a NiO layer at the bottom interface. The NiO layer alters the equilibrium between electric field driven filament formation and thermal enhanced ion diffusion, resulting in the volatile behaviour. Although the volatility is not ideal for non-volatile memory applications, it shows merit for access devices in crossbar arrays due to its high LRS/HRS ratio, which are also briefly discussed.« less

Analysis of power gating in different hierarchical levels of 2MB cache, considering variation

NASA Astrophysics Data System (ADS)

Jafari, Mohsen; Imani, Mohsen; Fathipour, Morteza

2015-09-01

This article reintroduces power gating technique in different hierarchical levels of static random-access memory (SRAM) design including cell, row, bank and entire cache memory in 16 nm Fin field effect transistor. Different structures of SRAM cells such as 6T, 8T, 9T and 10T are used in design of 2MB cache memory. The power reduction of the entire cache memory employing cell-level optimisation is 99.7% with the expense of area and other stability overheads. The power saving of the cell-level optimisation is 3× (1.2×) higher than power gating in cache (bank) level due to its superior selectivity. The access delay times are allowed to increase by 4% in the same energy delay product to achieve the best power reduction for each supply voltages and optimisation levels. The results show the row-level power gating is the best for optimising the power of the entire cache with lowest drawbacks. Comparisons of cells show that the cells whose bodies have higher power consumption are the best candidates for power gating technique in row-level optimisation. The technique has the lowest percentage of saving in minimum energy point (MEP) of the design. The power gating also improves the variation of power in all structures by at least 70%.

Resistive RAMs as analog trimming elements

NASA Astrophysics Data System (ADS)

Aziza, H.; Perez, A.; Portal, J. M.

2018-04-01

This work investigates the use of Resistive Random Access Memory (RRAM) as an analog trimming device. The analog storage feature of the RRAM cell is evaluated and the ability of the RRAM to hold several resistance states is exploited to propose analog trim elements. To modulate the memory cell resistance, a series of short programming pulses are applied across the RRAM cell allowing a fine calibration of the RRAM resistance. The RRAM non volatility feature makes the analog device powers up already calibrated for the system in which the analog trimmed structure is embedded. To validate the concept, a test structure consisting of a voltage reference is evaluated.

Microcontroller-based binary integrator for millimeter-wave radar experiments.

PubMed

Eskelinen, Pekka; Ruoskanen, Jukka; Peltonen, Jouni

2010-05-01

An easily on-site reconfigurable multiple binary integrator for millimeter radar experiments has been constructed of static random access memories, an eight bit microcontroller, and high speed video operational amplifiers. The design uses a raw comparator path and two adjustable m-out-of-n chains in a wired-OR configuration. Standard high speed memories allow the use of pulse widths below 100 ns. For eight pulse repetition intervals it gives a maximum improvement of 6.6 dB for stationary low-level target echoes. The doubled configuration enhances the capability against fluctuating targets. Because of the raw comparator path, also single return pulses of relatively high amplitude are processed.

Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array

NASA Astrophysics Data System (ADS)

Chen, Zhe; Li, Haitong; Chen, Hong-Yu; Chen, Bing; Liu, Rui; Huang, Peng; Zhang, Feifei; Jiang, Zizhen; Ye, Hongfei; Gao, Bin; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng; Wong, H.-S. Philip; Yu, Shimeng

2016-05-01

Disturbance characteristics of cross-point resistive random access memory (RRAM) arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.

A floating-point/multiple-precision processor for airborne applications

NASA Technical Reports Server (NTRS)

Yee, R.

1982-01-01

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

The robot's eyes - Stereo vision system for automated scene analysis

NASA Technical Reports Server (NTRS)

Williams, D. S.

1977-01-01

Attention is given to the robot stereo vision system which maintains the image produced by solid-state detector television cameras in a dynamic random access memory called RAPID. The imaging hardware consists of sensors (two solid-state image arrays using a charge injection technique), a video-rate analog-to-digital converter, the RAPID memory, and various types of computer-controlled displays, and preprocessing equipment (for reflexive actions, processing aids, and object detection). The software is aimed at locating objects and transversibility. An object-tracking algorithm is discussed and it is noted that tracking speed is in the 50-75 pixels/s range.

A multilevel nonvolatile magnetoelectric memory

NASA Astrophysics Data System (ADS)

Shen, Jianxin; Cong, Junzhuang; Shang, Dashan; Chai, Yisheng; Shen, Shipeng; Zhai, Kun; Sun, Young

2016-09-01

The coexistence and coupling between magnetization and electric polarization in multiferroic materials provide extra degrees of freedom for creating next-generation memory devices. A variety of concepts of multiferroic or magnetoelectric memories have been proposed and explored in the past decade. Here we propose a new principle to realize a multilevel nonvolatile memory based on the multiple states of the magnetoelectric coefficient (α) of multiferroics. Because the states of α depends on the relative orientation between magnetization and polarization, one can reach different levels of α by controlling the ratio of up and down ferroelectric domains with external electric fields. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure confirm that the states of α can be well controlled between positive and negative by applying selective electric fields. Consequently, two-level, four-level, and eight-level nonvolatile memory devices are demonstrated at room temperature. This kind of multilevel magnetoelectric memory retains all the advantages of ferroelectric random access memory but overcomes the drawback of destructive reading of polarization. In contrast, the reading of α is nondestructive and highly efficient in a parallel way, with an independent reading coil shared by all the memory cells.

Direct Observation of a Carbon Filament in Water-Resistant Organic Memory.

PubMed

Lee, Byung-Hyun; Bae, Hagyoul; Seong, Hyejeong; Lee, Dong-Il; Park, Hongkeun; Choi, Young Joo; Im, Sung-Gap; Kim, Sang Ouk; Choi, Yang-Kyu

2015-07-28

The memory for the Internet of Things (IoT) requires versatile characteristics such as flexibility, wearability, and stability in outdoor environments. Resistive random access memory (RRAM) to harness a simple structure and organic material with good flexibility can be an attractive candidate for IoT memory. However, its solution-oriented process and unclear switching mechanism are critical problems. Here we demonstrate iCVD polymer-intercalated RRAM (i-RRAM). i-RRAM exhibits robust flexibility and versatile wearability on any substrate. Stable operation of i-RRAM, even in water, is demonstrated, which is the first experimental presentation of water-resistant organic memory without any waterproof protection package. Moreover, the direct observation of a carbon filament is also reported for the first time using transmission electron microscopy, which puts an end to the controversy surrounding the switching mechanism. Therefore, reproducibility is feasible through comprehensive modeling. Furthermore, a carbon filament is superior to a metal filament in terms of the design window and selection of the electrode material. These results suggest an alternative to solve the critical issues of organic RRAM and an optimized memory type suitable for the IoT era.

Forced Ion Migration for Chalcogenide Phase Change Memory Device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A (Inventor)

2013-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Forced ion migration for chalcogenide phase change memory device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A. (Inventor)

2011-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states.

Forced ion migration for chalcogenide phase change memory device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A. (Inventor)

2012-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Experimental realization of a multiplexed quantum memory with 225 individually accessible memory cells

PubMed Central

Pu, Y-F; Jiang, N.; Chang, W.; Yang, H-X; Li, C.; Duan, L-M

2017-01-01

To realize long-distance quantum communication and quantum network, it is required to have multiplexed quantum memory with many memory cells. Each memory cell needs to be individually addressable and independently accessible. Here we report an experiment that realizes a multiplexed DLCZ-type quantum memory with 225 individually accessible memory cells in a macroscopic atomic ensemble. As a key element for quantum repeaters, we demonstrate that entanglement with flying optical qubits can be stored into any neighboring memory cells and read out after a programmable time with high fidelity. Experimental realization of a multiplexed quantum memory with many individually accessible memory cells and programmable control of its addressing and readout makes an important step for its application in quantum information technology. PMID:28480891

Deflate decompressor

DOEpatents

Hamlet, Jason R [Albuquerque, NM; Robertson, Perry J [Albuquerque, NM; Pierson, Lyndon G [Albuquerque, NM; Olsberg, Ronald R [Albuquerque, NM

2012-02-28

A deflate decompressor includes at least one decompressor unit, a memory access controller, a feedback path, and an output buffer unit. The memory access controller is coupled to the decompressor unit via a data path and includes a data buffer to receive the data stream and temporarily buffer a first portion the data stream. The memory access controller transfers fixed length data units of the data stream from the data buffer to the decompressor unit with reference to a memory pointer pointing into the memory buffer. The feedback path couples the decompressor unit to the memory access controller to feed back decrement values to the memory access controller for updating the memory pointer. The decrement values each indicate a number of bits unused by the decompressor unit when decoding the fixed length data units. The output buffer unit buffers a second portion of the data stream after decompression.

Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

DTIC Science & Technology

2013-12-01

Prototype Board SBU single bit upset SDK software development kit SDRAM synchronous dynamic random-access memory SEB single-event burnout ...current VHDL VHSIC hardware description language VHSIC very-high-speed integrated circuits VLSI very-large- scale integration VQFP very...transient pulse, called a single-event transient (SET), or even cause permanent damage to the device in the form of a burnout or gate rupture. The SEE

Initiation Mechanisms of Low-loss Swept-ramp Obstacles for Deflagration to Detonation Transition in Pulse Detonation Combustors

DTIC Science & Technology

2009-12-01

minimal pressure losses. 15. NUMBER OF PAGES 113 14. SUBJECT TERMS Pulse Detonation Combustors, PDC, Pulse Detonation Engines, PDE , PDE ...Postgraduate School PDC Pulse Detonation Combustor PDE Pulse Detonation Engine RAM Random Access Memory RDT Research, Design and Test RPL...inhibiting the implementation of this advanced propulsion system. The primary advantage offered by pulse detonation engines ( PDEs ) is the high efficiency

A Design Methodology for Optoelectronic VLSI

DTIC Science & Technology

2007-01-01

current gets converted to a CMOS voltage level through a transimpedance amplifier circuit called a receiver. The output of the receiver is then...change the current flowing from the diode to a voltage that the logic inputs can use. That circuit is called a receiver. It is a transimpedance amplifier ...incorpo- rate random access memory circuits, SRAM or dynamic RAM (DRAM). These circuits use weak internal analog signals that are amplified by sense

Deployment of 802.15.4 Sensor Networks for C4ISR Operations

DTIC Science & Technology

2006-06-01

43 Figure 20.MSP410CA Dense Grid Monitoring (Crossbow User’s Manual, 2005). ....................................44 Figure 21.(a)MICA2 without...Deployment of Sensor Grid (COASTS OPORD, 2006). ...56 Figure 27.Topology View of Two Nodes and Base Station .......57 Figure 28.Nodes Employing Multi...Random Access Memory TCP/IP Transmission Control Protocol/Internet Protocol TinyOS Tiny Micro Threading Operating System UARTs Universal

Studies Of Single-Event-Upset Models

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.

1988-01-01

Report presents latest in series of investigations of "soft" bit errors known as single-event upsets (SEU). In this investigation, SEU response of low-power, Schottky-diode-clamped, transistor/transistor-logic (TTL) static random-access memory (RAM) observed during irradiation by Br and O ions in ranges of 100 to 240 and 20 to 100 MeV, respectively. Experimental data complete verification of computer model used to simulate SEU in this circuit.

Effect of Pulse and dc Formation on the Performance of One-Transistor and One-Resistor Resistance Random Access Memory Devices

NASA Astrophysics Data System (ADS)

Liu, Hong-Tao; Yang, Bao-He; Lv, Hang-Bing; Xu, Xiao-Xin; Luo, Qing; Wang, Guo-Ming; Zhang, Mei-Yun; Long, Shi-Bing; Liu, Qi; Liu, Ming

2015-02-01

We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor (1T1R) resistance random access memory (RRAM) device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state (HRS) under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament (CF) formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state (LRS) can be easily changed by removing a few trapping states from the conducting path. Hence, a higher HRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.

Radiation dosimetry using three-dimensional optical random access memories

NASA Technical Reports Server (NTRS)

Moscovitch, M.; Phillips, G. W.

2001-01-01

Three-dimensional optical random access memories (3D ORAMs) are a new generation of high-density data storage devices. Binary information is stored and retrieved via a light induced reversible transformation of an ensemble of bistable photochromic molecules embedded in a polymer matrix. This paper describes the application of 3D ORAM materials to radiation dosimetry. It is shown both theoretically and experimentally, that ionizing radiation in the form of heavy charged particles is capable of changing the information originally stored on the ORAM material. The magnitude and spatial distribution of these changes are used as a measure of the absorbed dose, particle type and energy. The effects of exposure on 3D ORAM materials have been investigated for a variety of particle types and energies, including protons, alpha particles and 12C ions. The exposed materials are observed to fluoresce when exposed to laser light. The intensity and the depth of the fluorescence is dependent on the type and energy of the particle to which the materials were exposed. It is shown that these effects can be modeled using Monte Carlo calculations. The model provides a better understanding of the properties of these materials. which should prove useful for developing systems for charged particle and neutron dosimetry/detector applications. c2001 Published by Elsevier Science B.V.

Tri-state resistive switching characteristics of MnO/Ta2O5 resistive random access memory device by a controllable reset process

NASA Astrophysics Data System (ADS)

Lee, N. J.; Kang, T. S.; Hu, Q.; Lee, T. S.; Yoon, T.-S.; Lee, H. H.; Yoo, E. J.; Choi, Y. J.; Kang, C. J.

2018-06-01

Tri-state resistive switching characteristics of bilayer resistive random access memory devices based on manganese oxide (MnO)/tantalum oxide (Ta2O5) have been studied. The current–voltage (I–V) characteristics of the Ag/MnO/Ta2O5/Pt device show tri-state resistive switching (RS) behavior with a high resistance state (HRS), intermediate resistance state (IRS), and low resistance state (LRS), which are controlled by the reset process. The MnO/Ta2O5 film shows bipolar RS behavior through the formation and rupture of conducting filaments without the forming process. The device shows reproducible and stable RS both from the HRS to the LRS and from the IRS to the LRS. In order to elucidate the tri-state RS mechanism in the Ag/MnO/Ta2O5/Pt device, transmission electron microscope (TEM) images are measured in the LRS, IRS and HRS. White lines like dendrites are observed in the Ta2O5 film in both the LRS and the IRS. Poole–Frenkel conduction, space charge limited conduction, and Ohmic conduction are proposed as the dominant conduction mechanisms for the Ag/MnO/Ta2O5/Pt device based on the obtained I–V characteristics and TEM images.

Sustained Resistive Switching in a Single Cu:7,7,8,8-tetracyanoquinodimethane Nanowire: A Promising Material for Resistive Random Access Memory

PubMed Central

Basori, Rabaya; Kumar, Manoranjan; Raychaudhuri, Arup K.

2016-01-01

We report a new type of sustained and reversible unipolar resistive switching in a nanowire device made from a single strand of Cu:7,7,8,8-tetracyanoquinodimethane (Cu:TCNQ) nanowire (diameter <100 nm) that shows high ON/OFF ratio (~103), low threshold voltage of switching (~3.5 V) and large cycling endurance (>103). This indicates a promising material for high density resistive random access memory (ReRAM) device integration. Switching is observed in Cu:TCNQ single nanowire devices with two different electrode configuration: symmetric (C-Pt/Cu:TCNQ/C-Pt) and asymmetric (Cu/Cu:TCNQ/C-Pt), where contacts connecting the nanowire play an important role. This report also developed a method of separating out the electrode and material contributions in switching using metal-semiconductor-metal (MSM) device model along with a direct 4-probe resistivity measurement of the nanowire in the OFF as well as ON state. The device model was followed by a phenomenological model of current transport through the nanowire device which shows that lowering of potential barrier at the contacts likely occur due to formation of Cu filaments in the interface between nanowire and contact electrodes. We obtain quantitative agreement of numerically analyzed results with the experimental switching data. PMID:27245099

High-performance flexible resistive memory devices based on Al2O3:GeOx composite

NASA Astrophysics Data System (ADS)

Behera, Bhagaban; Maity, Sarmistha; Katiyar, Ajit K.; Das, Samaresh

2018-05-01

In this study a resistive switching random access memory device using Al2O3:GeOx composite thin films on flexible substrate is presented. A bipolar switching characteristic was observed for the co-sputter deposited Al2O3:GeOx composite thin films. Al/Al2O3:GeOx/ITO/PET memory device shows excellent ON/OFF ratio (∼104) and endurance (>500 cycles). GeOx nanocrystals embedded in the Al2O3 matrix have been found to play a significant role in enhancing the switching characteristics by facilitating oxygen vacancy formation. Mechanical endurance was retained even after several bending. The conduction mechanism of the device was qualitatively discussed by considering Ohmic and SCLC conduction. This flexible device is a potential candidate for next-generation electronics device.

Internal filament modulation in low-dielectric gap design for built-in selector-less resistive switching memory application

NASA Astrophysics Data System (ADS)

Chen, Ying-Chen; Lin, Chih-Yang; Huang, Hui-Chun; Kim, Sungjun; Fowler, Burt; Chang, Yao-Feng; Wu, Xiaohan; Xu, Gaobo; Chang, Ting-Chang; Lee, Jack C.

2018-02-01

Sneak path current is a severe hindrance for the application of high-density resistive random-access memory (RRAM) array designs. In this work, we demonstrate nonlinear (NL) resistive switching characteristics of a HfO x /SiO x -based stacking structure as a realization for selector-less RRAM devices. The NL characteristic was obtained and designed by optimizing the internal filament location with a low effective dielectric constant in the HfO x /SiO x structure. The stacking HfO x /SiO x -based RRAM device as the one-resistor-only memory cell is applicable without needing an additional selector device to solve the sneak path issue with a switching voltage of ~1 V, which is desirable for low-power operating in built-in nonlinearity crossbar array configurations.

Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tomczak, Y., E-mail: Yoann.Tomczak@imec.be; Department of Chemistry, KU Leuven; Swerts, J.

2016-01-25

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. Amore » stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm{sup 2} after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.« less

Electric-Field-Driven Dual Vacancies Evolution in Ultrathin Nanosheets Realizing Reversible Semiconductor to Half-Metal Transition.

PubMed

Lyu, Mengjie; Liu, Youwen; Zhi, Yuduo; Xiao, Chong; Gu, Bingchuan; Hua, Xuemin; Fan, Shaojuan; Lin, Yue; Bai, Wei; Tong, Wei; Zou, Youming; Pan, Bicai; Ye, Bangjiao; Xie, Yi

2015-12-02

Fabricating a flexible room-temperature ferromagnetic resistive-switching random access memory (RRAM) device is of fundamental importance to integrate nonvolatile memory and spintronics both in theory and practice for modern information technology and has the potential to bring about revolutionary new foldable information-storage devices. Here, we show that a relatively low operating voltage (+1.4 V/-1.5 V, the corresponding electric field is around 20,000 V/cm) drives the dual vacancies evolution in ultrathin SnO2 nanosheets at room temperature, which causes the reversible transition between semiconductor and half-metal, accompanyied by an abrupt conductivity change up to 10(3) times, exhibiting room-temperature ferromagnetism in two resistance states. Positron annihilation spectroscopy and electron spin resonance results show that the Sn/O dual vacancies in the ultrathin SnO2 nanosheets evolve to isolated Sn vacancy under electric field, accounting for the switching behavior of SnO2 ultrathin nanosheets; on the other hand, the different defect types correspond to different conduction natures, realizing the transition between semiconductor and half-metal. Our result represents a crucial step to create new a information-storage device realizing the reversible transition between semiconductor and half-metal with flexibility and room-temperature ferromagnetism at low energy consumption. The as-obtained half-metal in the low-resistance state broadens the application of the device in spintronics and the semiconductor to half-metal transition on the basis of defects evolution and also opens up a new avenue for exploring random access memory mechanisms and finding new half-metals for spintronics.

What does visual suffix interference tell us about spatial location in working memory?

PubMed

Allen, Richard J; Castellà, Judit; Ueno, Taiji; Hitch, Graham J; Baddeley, Alan D

2015-01-01

A visual object can be conceived of as comprising a number of features bound together by their joint spatial location. We investigate the question of whether the spatial location is automatically bound to the features or whether the two are separable, using a previously developed paradigm whereby memory is disrupted by a visual suffix. Participants were shown a sample array of four colored shapes, followed by a postcue indicating the target for recall. On randomly intermixed trials, a to-be-ignored suffix array consisting of two different colored shapes was presented between the sample and the postcue. In a random half of suffix trials, one of the suffix items overlaid the location of the target. If location was automatically encoded, one might expect the colocation of target and suffix to differentially impair performance. We carried out three experiments, cuing for recall by spatial location (Experiment 1), color or shape (Experiment 2), or both randomly intermixed (Experiment 3). All three studies showed clear suffix effects, but the colocation of target and suffix was differentially disruptive only when a spatial cue was used. The results suggest that purely visual shape-color binding can be retained and accessed without requiring information about spatial location, even when task demands encourage the encoding of location, consistent with the idea of an abstract and flexible visual working memory system.

Interference control in working memory: comparing groups of children with atypical development.

PubMed

Palladino, Paola; Ferrari, Marcella

2013-01-01

The study aimed to test whether working memory deficits in children at risk of Learning Disabilities (LD) and/or attention deficit/hyperactivity disorder (ADHD) can be attributed to deficits in interference control, thereby implicating prefrontal systems. Two groups of children known for showing poor working memory (i.e., children with poor comprehension and children with ADHD) were compared to a group of children with specific reading decoding problems (i.e., having severe problems in phonological rather than working memory) and to a control group. All children were tested with a verbal working memory task. Interference control of irrelevant items was examined by a lexical decision task presented immediately after the final recall in about half the trials, selected at random. The interference control measure was therefore directly related to working memory performance. Results confirmed deficient working memory performance in poor comprehenders and children at risk of ADHD + LD. More interestingly, this working memory deficit was associated with greater activation of irrelevant information than in the control group. Poor decoders showed more efficient interference control, in contrast to poor comprehenders and ADHD + LD children. These results indicated that interfering items were still highly accessible to working memory in children who fail the working memory task. In turn, these findings strengthen and clarify the role of interference control, one of the most critical prefrontal functions, in working memory.

Acoustically assisted spin-transfer-torque switching of nanomagnets: An energy-efficient hybrid writing scheme for non-volatile memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Biswas, Ayan K.; Bandyopadhyay, Supriyo; Atulasimha, Jayasimha

We show that the energy dissipated to write bits in spin-transfer-torque random access memory can be reduced by an order of magnitude if a surface acoustic wave (SAW) is launched underneath the magneto-tunneling junctions (MTJs) storing the bits. The SAW-generated strain rotates the magnetization of every MTJs' soft magnet from the easy towards the hard axis, whereupon passage of a small spin-polarized current through a target MTJ selectively switches it to the desired state with > 99.99% probability at room temperature, thereby writing the bit. The other MTJs return to their original states at the completion of the SAW cycle.

Programmable data communications controller requirements

NASA Technical Reports Server (NTRS)

1977-01-01

The design requirements for a Programmable Data Communications Controller (PDCC) that reduces the difficulties in attaching data terminal equipment to a computer are presented. The PDCC is an interface between the computer I/O channel and the bit serial communication lines. Each communication line is supported by a communication port that handles all line control functions and performs most terminal control functions. The port is fabricated on a printed circuit board that plugs into a card chassis, mating with a connector that is joined to all other card stations by a data bus. Ports are individually programmable; each includes a microprocessor, a programmable read-only memory for instruction storage, and a random access memory for data storage.

Self-Compliant Bipolar Resistive Switching in SiN-Based Resistive Switching Memory

PubMed Central

Kim, Sungjun; Chang, Yao-Feng; Kim, Min-Hwi; Kim, Tae-Hyeon; Kim, Yoon; Park, Byung-Gook

2017-01-01

Here, we present evidence of self-compliant and self-rectifying bipolar resistive switching behavior in Ni/SiNx/n+ Si and Ni/SiNx/n++ Si resistive-switching random access memory devices. The Ni/SiNx/n++ Si device’s Si bottom electrode had a higher dopant concentration (As ion > 1019 cm−3) than the Ni/SiNx/n+ Si device; both unipolar and bipolar resistive switching behaviors were observed for the higher dopant concentration device owing to a large current overshoot. Conversely, for the device with the lower dopant concentration (As ion < 1018 cm−3), self-rectification and self-compliance were achieved owing to the series resistance of the Si bottom electrode. PMID:28772819

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Ultra-low power, highly uniform polymer memory by inserted multilayer graphene electrode

NASA Astrophysics Data System (ADS)

Jang, Byung Chul; Seong, Hyejeong; Kim, Jong Yun; Koo, Beom Jun; Kim, Sung Kyu; Yang, Sang Yoon; Gap Im, Sung; Choi, Sung-Yool

2015-12-01

Filament type resistive random access memory (RRAM) based on polymer thin films is a promising device for next generation, flexible nonvolatile memory. However, the resistive switching nonuniformity and the high power consumption found in the general filament type RRAM devices present critical issues for practical memory applications. Here, we introduce a novel approach not only to reduce the power consumption but also to improve the resistive switching uniformity in RRAM devices based on poly(1,3,5-trimethyl-3,4,5-trivinyl cyclotrisiloxane) by inserting multilayer graphene (MLG) at the electrode/polymer interface. The resistive switching uniformity was thereby significantly improved, and the power consumption was markedly reduced by 250 times. Furthermore, the inserted MLG film enabled a transition of the resistive switching operation from unipolar resistive switching to bipolar resistive switching and induced self-compliance behavior. The findings of this study can pave the way toward a new area of application for graphene in electronic devices.

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell.

PubMed

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-07-07

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.

Accessing memory

DOEpatents

Yoon, Doe Hyun; Muralimanohar, Naveen; Chang, Jichuan; Ranganthan, Parthasarathy

2017-09-26

A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

Composition-dependent nanoelectronics of amido-phenazines: non-volatile RRAM and WORM memory devices.

PubMed

Maiti, Dilip K; Debnath, Sudipto; Nawaz, Sk Masum; Dey, Bapi; Dinda, Enakhi; Roy, Dipanwita; Ray, Sudipta; Mallik, Abhijit; Hussain, Syed A

2017-10-17

A metal-free three component cyclization reaction with amidation is devised for direct synthesis of DFT-designed amido-phenazine derivative bearing noncovalent gluing interactions to fabricate organic nanomaterials. Composition-dependent organic nanoelectronics for nonvolatile memory devices are discovered using mixed phenazine-stearic acid (SA) nanomaterials. We discovered simultaneous two different types of nonmagnetic and non-moisture sensitive switching resistance properties of fabricated devices utilizing mixed organic nanomaterials: (a) sample-1(8:SA = 1:3) is initially off, turning on at a threshold, but it does not turn off again with the application of any voltage, and (b) sample-2 (8:SA = 3:1) is initially off, turning on at a sharp threshold and off again by reversing the polarity. No negative differential resistance is observed in either type. These samples have different device implementations: sample-1 is attractive for write-once-read-many-times memory devices, such as novel non-editable database, archival memory, electronic voting, radio frequency identification, sample-2 is useful for resistive-switching random access memory application.

The impact of interference on short-term memory for visual orientation.

PubMed

Rademaker, Rosanne L; Bloem, Ilona M; De Weerd, Peter; Sack, Alexander T

2015-12-01

Visual short-term memory serves as an efficient buffer for maintaining no longer directly accessible information. How robust are visual memories against interference? Memory for simple visual features has proven vulnerable to distractors containing conflicting information along the relevant stimulus dimension, leading to the idea that interacting feature-specific channels at an early stage of visual processing support memory for simple visual features. Here we showed that memory for a single randomly orientated grating was susceptible to interference from a to-be-ignored distractor grating presented midway through a 3-s delay period. Memory for the initially presented orientation became noisier when it differed from the distractor orientation, and response distributions were shifted toward the distractor orientation (by ∼3°). Interestingly, when the distractor was rendered task-relevant by making it a second memory target, memory for both retained orientations showed reduced reliability as a function of increased orientation differences between them. However, the degree to which responses to the first grating shifted toward the orientation of the task-relevant second grating was much reduced. Finally, using a dichoptic display, we demonstrated that these systematic biases caused by a consciously perceived distractor disappeared once the distractor was presented outside of participants' awareness. Together, our results show that visual short-term memory for orientation can be systematically biased by interfering information that is consciously perceived. (c) 2015 APA, all rights reserved).

Asynchronous Communication Scheme For Hypercube Computer

NASA Technical Reports Server (NTRS)

Madan, Herb S.

1988-01-01

Scheme devised for asynchronous-message communication system for Mark III hypercube concurrent-processor network. Network consists of up to 1,024 processing elements connected electrically as though were at corners of 10-dimensional cube. Each node contains two Motorola 68020 processors along with Motorola 68881 floating-point processor utilizing up to 4 megabytes of shared dynamic random-access memory. Scheme intended to support applications requiring passage of both polled or solicited and unsolicited messages.

Methods for resistive switching of memristors

DOEpatents

Mickel, Patrick R.; James, Conrad D.; Lohn, Andrew; Marinella, Matthew; Hsia, Alexander H.

2016-05-10

The present invention is directed generally to resistive random-access memory (RRAM or ReRAM) devices and systems, as well as methods of employing a thermal resistive model to understand and determine switching of such devices. In particular example, the method includes generating a power-resistance measurement for the memristor device and applying an isothermal model to the power-resistance measurement in order to determine one or more parameters of the device (e.g., filament state).

I-V Characteristics of a Static Random Access Memory Cell Utilizing Ferroelectric Transistors

NASA Technical Reports Server (NTRS)

Laws, Crystal; Mitchell, Cody; Hunt, Mitchell; Ho, Fat D.; MacLeod, Todd C.

2012-01-01

I-V characteristics for FeFET different than that of MOSFET Ferroelectric layer features hysteresis trend whereas MOSFET behaves same for both increasing and decreasing VGS FeFET I-V characteristics doesn't show dependence on VDS A Transistor with different channel length and width as well as various resistance and input voltages give different results As resistance values increased, the magnitude of the drain current decreased.

Inverse Resistance Change Cr2Ge2Te6-Based PCRAM Enabling Ultralow-Energy Amorphization.

PubMed

Hatayama, Shogo; Sutou, Yuji; Shindo, Satoshi; Saito, Yuta; Song, Yun-Heub; Ando, Daisuke; Koike, Junichi

2018-01-24

Phase-change random access memory (PCRAM) has attracted much attention for next-generation nonvolatile memory that can replace flash memory and can be used for storage-class memory. Generally, PCRAM relies on the change in the electrical resistance of a phase-change material between high-resistance amorphous (reset) and low-resistance crystalline (set) states. Herein, we present an inverse resistance change PCRAM with Cr 2 Ge 2 Te 6 (CrGT) that shows a high-resistance crystalline reset state and a low-resistance amorphous set state. The inverse resistance change was found to be due to a drastic decrease in the carrier density upon crystallization, which causes a large increase in contact resistivity between CrGT and the electrode. The CrGT memory cell was demonstrated to show fast reversible resistance switching with a much lower operating energy for amorphization than a Ge 2 Sb 2 Te 5 memory cell. This low operating energy in CrGT should be due to a small programmed amorphous volume, which can be realized by a high-resistance crystalline matrix and a dominant contact resistance. Simultaneously, CrGT can break the trade-off relationship between the crystallization temperature and operating speed.

Working memory capacity and retrieval limitations from long-term memory: an examination of differences in accessibility.

PubMed

Unsworth, Nash; Spillers, Gregory J; Brewer, Gene A

2012-01-01

In two experiments, the locus of individual differences in working memory capacity and long-term memory recall was examined. Participants performed categorical cued and free recall tasks, and individual differences in the dynamics of recall were interpreted in terms of a hierarchical-search framework. The results from this study are in accordance with recent theorizing suggesting a strong relation between working memory capacity and retrieval from long-term memory. Furthermore, the results also indicate that individual differences in categorical recall are partially due to differences in accessibility. In terms of accessibility of target information, two important factors drive the difference between high- and low-working-memory-capacity participants. Low-working-memory-capacity participants fail to utilize appropriate retrieval strategies to access cues, and they also have difficulty resolving cue overload. Thus, when low-working-memory-capacity participants were given specific cues that activated a smaller set of potential targets, their recall performance was the same as that of high-working-memory-capacity participants.

Memory availability and referential access

PubMed Central

Johns, Clinton L.; Gordon, Peter C.; Long, Debra L.; Swaab, Tamara Y.

2013-01-01

Most theories of coreference specify linguistic factors that modulate antecedent accessibility in memory; however, whether non-linguistic factors also affect coreferential access is unknown. Here we examined the impact of a non-linguistic generation task (letter transposition) on the repeated-name penalty, a processing difficulty observed when coreferential repeated names refer to syntactically prominent (and thus more accessible) antecedents. In Experiment 1, generation improved online (event-related potentials) and offline (recognition memory) accessibility of names in word lists. In Experiment 2, we manipulated generation and syntactic prominence of antecedent names in sentences; both improved online and offline accessibility, but only syntactic prominence elicited a repeated-name penalty. Our results have three important implications: first, the form of a referential expression interacts with an antecedent’s status in the discourse model during coreference; second, availability in memory and referential accessibility are separable; and finally, theories of coreference must better integrate known properties of the human memory system. PMID:24443621

Influence of carbon content on the copper-telluride phase formation and on the resistive switching behavior of carbon alloyed Cu-Te conductive bridge random access memory cells

NASA Astrophysics Data System (ADS)

Devulder, Wouter; Opsomer, Karl; Franquet, Alexis; Meersschaut, Johan; Belmonte, Attilio; Muller, Robert; De Schutter, Bob; Van Elshocht, Sven; Jurczak, Malgorzata; Goux, Ludovic; Detavernier, Christophe

2014-02-01

In this paper, we investigate the influence of the carbon content on the Cu-Te phase formation and on the resistive switching behavior in carbon alloyed Cu0.6Te0.4 based conductive bridge random access memory (CBRAM) cells. Carbon alloying of copper-tellurium inhibits the crystallization, while attractive switching behavior is preserved when using the material as Cu-supply layer in CBRAM cells. The phase formation is first investigated in a combinatorial way. With increasing carbon content, an enlargement of the temperature window in which the material stays amorphous was observed. Moreover, if crystalline phases are formed, subsequent phase transformations are inhibited. The electrical switching behavior of memory cells with different carbon contents is then investigated by implementing them in 580 μm diameter dot TiN/Cu0.6Te0.4-C/Al2O3/Si memory cells. Reliable switching behavior is observed for carbon contents up to 40 at. %, with a resistive window of more than 2 orders of magnitude, whereas for 50 at. % carbon, a higher current in the off state and only a small resistive window are present after repeated cycling. This degradation can be ascribed to the higher thermal and lower drift contribution to the reset operation due to a lower Cu affinity towards the supply layer, leading cycle-after-cycle to an increasing amount of Cu in the switching layer, which contributes to the current. The thermal diffusion of Cu into Al2O3 under annealing also gives an indication of the Cu affinity of the source layer. Time of flight secondary ion mass spectroscopy was used to investigate this migration depth in Al2O3 before and after annealing, showing a higher Cu, Te, and C migration for high carbon contents.

Cognitive training on stroke patients via virtual reality-based serious games.

PubMed

Gamito, Pedro; Oliveira, Jorge; Coelho, Carla; Morais, Diogo; Lopes, Paulo; Pacheco, José; Brito, Rodrigo; Soares, Fabio; Santos, Nuno; Barata, Ana Filipa

2017-02-01

Use of virtual reality environments in cognitive rehabilitation offers cost benefits and other advantages. In order to test the effectiveness of a virtual reality application for neuropsychological rehabilitation, a cognitive training program using virtual reality was applied to stroke patients. A virtual reality-based serious games application for cognitive training was developed, with attention and memory tasks consisting of daily life activities. Twenty stroke patients were randomly assigned to two conditions: exposure to the intervention, and waiting list control. The results showed significant improvements in attention and memory functions in the intervention group, but not in the controls. Overall findings provide further support for the use of VR cognitive training applications in neuropsychological rehabilitation. Implications for Rehabilitation Improvements in memory and attention functions following a virtual reality-based serious games intervention. Training of daily-life activities using a virtual reality application. Accessibility to training contents.

A graphene integrated highly transparent resistive switching memory device

NASA Astrophysics Data System (ADS)

Dugu, Sita; Pavunny, Shojan P.; Limbu, Tej B.; Weiner, Brad R.; Morell, Gerardo; Katiyar, Ram S.

2018-05-01

We demonstrate the hybrid fabrication process of a graphene integrated highly transparent resistive random-access memory (TRRAM) device. The indium tin oxide (ITO)/Al2O3/graphene nonvolatile memory device possesses a high transmittance of >82% in the visible region (370-700 nm) and exhibits stable and non-symmetrical bipolar switching characteristics with considerably low set and reset voltages (<±1 V). The vertical two-terminal device shows an excellent resistive switching behavior with a high on-off ratio of ˜5 × 103. We also fabricated a ITO/Al2O3/Pt device and studied its switching characteristics for comparison and a better understanding of the ITO/Al2O3/graphene device characteristics. The conduction mechanisms in high and low resistance states were analyzed, and the observed polarity dependent resistive switching is explained based on electro-migration of oxygen ions.

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

NASA Astrophysics Data System (ADS)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

Filamentary model in resistive switching materials

NASA Astrophysics Data System (ADS)

Jasmin, Alladin C.

2017-12-01

The need for next generation computer devices is increasing as the demand for efficient data processing increases. The amount of data generated every second also increases which requires large data storage devices. Oxide-based memory devices are being studied to explore new research frontiers thanks to modern advances in nanofabrication. Various oxide materials are studied as active layers for non-volatile memory. This technology has potential application in resistive random-access-memory (ReRAM) and can be easily integrated in CMOS technologies. The long term perspective of this research field is to develop devices which mimic how the brain processes information. To realize such application, a thorough understanding of the charge transport and switching mechanism is important. A new perspective in the multistate resistive switching based on current-induced filament dynamics will be discussed. A simple equivalent circuit of the device gives quantitative information about the nature of the conducting filament at different resistance states.

Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing

NASA Astrophysics Data System (ADS)

Rao, Feng; Ding, Keyuan; Zhou, Yuxing; Zheng, Yonghui; Xia, Mengjiao; Lv, Shilong; Song, Zhitang; Feng, Songlin; Ronneberger, Ider; Mazzarello, Riccardo; Zhang, Wei; Ma, Evan

2017-12-01

Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge2Sb2Te5). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc0.2Sb2Te3) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems.

Fabrication of cross-shaped Cu-nanowire resistive memory devices using a rapid, scalable, and designable inorganic-nanowire-digital-alignment technique (Conference Presentation)

NASA Astrophysics Data System (ADS)

Xu, Wentao; Lee, Yeongjun; Min, Sung-Yong; Park, Cheolmin; Lee, Tae-Woo

2016-09-01

Resistive random-access memory (RRAM) is a candidate next generation nonvolatile memory due to its high access speed, high density and ease of fabrication. Especially, cross-point-access allows cross-bar arrays that lead to high-density cells in a two-dimensional planar structure. Use of such designs could be compatible with the aggressive scaling down of memory devices, but existing methods such as optical or e-beam lithographic approaches are too complicated. One-dimensional inorganic nanowires (i-NWs) are regarded as ideal components of nanoelectronics to circumvent the limitations of conventional lithographic approaches. However, post-growth alignment of these i-NWs precisely on a large area with individual control is still a difficult challenge. Here, we report a simple, inexpensive, and rapid method to fabricate two-dimensional arrays of perpendicularly-aligned, individually-conductive Cu-NWs with a nanometer-scale CuxO layer sandwiched at each cross point, by using an inorganic-nanowire-digital-alignment technique (INDAT) and a one-step reduction process. In this approach, the oxide layer is self-formed and patterned, so conventional deposition and lithography are not necessary. INDAT eliminates the difficulties of alignment and scalable fabrication that are encountered when using currently-available techniques that use inorganic nanowires. This simple process facilitates fabrication of cross-point nonvolatile memristor arrays. Fabricated arrays had reproducible resistive switching behavior, high on/off current ratio (Ion/Ioff) 10 6 and extensive cycling endurance. This is the first report of memristors with the resistive switching oxide layer self-formed, self-patterned and self-positioned; we envision that the new features of the technique will provide great opportunities for future nano-electronic circuits.

jmzIdentML API: A Java interface to the mzIdentML standard for peptide and protein identification data.

PubMed

Reisinger, Florian; Krishna, Ritesh; Ghali, Fawaz; Ríos, Daniel; Hermjakob, Henning; Vizcaíno, Juan Antonio; Jones, Andrew R

2012-03-01

We present a Java application programming interface (API), jmzIdentML, for the Human Proteome Organisation (HUPO) Proteomics Standards Initiative (PSI) mzIdentML standard for peptide and protein identification data. The API combines the power of Java Architecture of XML Binding (JAXB) and an XPath-based random-access indexer to allow a fast and efficient mapping of extensible markup language (XML) elements to Java objects. The internal references in the mzIdentML files are resolved in an on-demand manner, where the whole file is accessed as a random-access swap file, and only the relevant piece of XMLis selected for mapping to its corresponding Java object. The APIis highly efficient in its memory usage and can handle files of arbitrary sizes. The APIfollows the official release of the mzIdentML (version 1.1) specifications and is available in the public domain under a permissive licence at http://www.code.google.com/p/jmzidentml/. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

DTIC Science & Technology

2010-07-22

dependent , providing a natural bandwidth match between compute cores and the memory subsystem. • High Bandwidth Dcnsity. Waveguides crossing the chip...simulate this memory access architecture on a 2S6-core chip with a concentrated 64-node network lIsing detailed traces of high-performance embedded...memory modulcs, wc placc memory access poi nts (MAPs) around the pcriphery of the chip connected to thc nctwork. These MAPs, shown in Figure 4, contain

Effectiveness of Working Memory Training among Subjects Currently on Sick Leave Due to Complex Symptoms.

PubMed

Aasvik, Julie K; Woodhouse, Astrid; Stiles, Tore C; Jacobsen, Henrik B; Landmark, Tormod; Glette, Mari; Borchgrevink, Petter C; Landrø, Nils I

2016-01-01

Introduction: The current study examined if adaptive working memory training (Cogmed QM) has the potential to improve inhibitory control, working memory capacity, and perceptions of memory functioning in a group of patients currently on sick leave due to symptoms of pain, insomnia, fatigue, depression and anxiety. Participants who were referred to a vocational rehabilitation center volunteered to take part in the study. Methods: Participants were randomly assigned to either a training condition ( N = 25) or a control condition ( N = 29). Participants in the training condition received working memory training in addition to the clinical intervention offered as part of the rehabilitation program, while participants in the control condition received treatment as usual i.e., the rehabilitation program only. Inhibitory control was measured by The Stop Signal Task, working memory was assessed by the Spatial Working Memory Test, while perceptions of memory functioning were assessed by The Everyday Memory Questionnaire-Revised. Results: Participants in the training group showed a significant improvement on the post-tests of inhibitory control when compared with the comparison group ( p = 0.025). The groups did not differ on the post-tests of working memory. Both groups reported less memory problems at post-testing, but there was no sizeable difference between the two groups. Conclusions: Results indicate that working memory training does not improve general working memory capacity per se . Nor does it seem to give any added effects in terms of targeting and improving self-perceived memory functioning. Results do, however, provide evidence to suggest that inhibitory control is accessible and susceptible to modification by adaptive working memory training.

The dynamic interplay between acute psychosocial stress, emotion and autobiographical memory.

PubMed

Sheldon, Signy; Chu, Sonja; Nitschke, Jonas P; Pruessner, Jens C; Bartz, Jennifer A

2018-06-06

Although acute psychosocial stress can impact autobiographical memory retrieval, the nature of this effect is not entirely clear. One reason for this ambiguity is because stress can have opposing effects on the different stages of autobiographical memory retrieval. We addressed this issue by testing how acute stress affects three stages of the autobiographical memory retrieval - accessing, recollecting and reconsolidating a memory. We also investigate the influence of emotion valence on this effect. In a between-subjects design, participants were first exposed to an acute psychosocial stressor or a control task. Next, the participants were shown positive, negative or neutral retrieval cues and asked to access and describe autobiographical memories. After a three to four day delay, participants returned for a second session in which they described these autobiographical memories. During initial retrieval, stressed participants were slower to access memories than were control participants; moreover, cortisol levels were positively associated with response times to access positively-cued memories. There were no effects of stress on the amount of details used to describe memories during initial retrieval, but stress did influence memory detail during session two. During session two, stressed participants recovered significantly more details, particularly emotional ones, from the remembered events than control participants. Our results indicate that the presence of stress impairs the ability to access consolidated autobiographical memories; moreover, although stress has no effect on memory recollection, stress alters how recollected experiences are reconsolidated back into memory traces.

Computer hardware for radiologists: Part I

PubMed Central

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration. PMID:21042437

Accessing Information in Working Memory: Can the Focus of Attention Grasp Two Elements at the Same Time?

ERIC Educational Resources Information Center

Oberauer, Klaus; Bialkova, Svetlana

2009-01-01

Processing information in working memory requires selective access to a subset of working-memory contents by a focus of attention. Complex cognition often requires joint access to 2 items in working memory. How does the focus select 2 items? Two experiments with an arithmetic task and 1 with a spatial task investigate time demands for successive…

Integration of SrBi2Ta2O9 thin films for high density ferroelectric random access memory

NASA Astrophysics Data System (ADS)

Wouters, D. J.; Maes, D.; Goux, L.; Lisoni, J. G.; Paraschiv, V.; Johnson, J. A.; Schwitters, M.; Everaert, J.-L.; Boullart, W.; Schaekers, M.; Willegems, M.; Vander Meeren, H.; Haspeslagh, L.; Artoni, C.; Caputa, C.; Casella, P.; Corallo, G.; Russo, G.; Zambrano, R.; Monchoix, H.; Vecchio, G.; Van Autryve, L.

2006-09-01

Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35μm CMOS technology. In a second phase, then, possibility of scaling of our cell is demonstrated in 0.18μm technology. The excellent electrical and reliability properties of the small integrated ferroelectric capacitors prove the feasibility of the technology, while the verification of the potential 3D effect confirms the basic scaling potential of our concept beyond that of the single-mask capacitor. The paper outlines the different material and technological challenges, and working solutions are demonstrated. While some issues are specific to our own cell, many are applicable to different stacked FeRAM cell concepts, or will become more general concerns when more developments are moving into 3D structures.

Resistive switching mechanisms in random access memory devices incorporating transition metal oxides: TiO2, NiO and Pr0.7Ca0.3MnO3.

PubMed

Magyari-Köpe, Blanka; Tendulkar, Mihir; Park, Seong-Geon; Lee, Hyung Dong; Nishi, Yoshio

2011-06-24

Resistance change random access memory (RRAM) cells, typically built as MIM capacitor structures, consist of insulating layers I sandwiched between metal layers M, where the insulator performs the resistance switching operation. These devices can be electrically switched between two or more stable resistance states at a speed of nanoseconds, with long retention times, high switching endurance, low read voltage, and large switching windows. They are attractive candidates for next-generation non-volatile memory, particularly as a flash successor, as the material properties can be scaled to the nanometer regime. Several resistance switching models have been suggested so far for transition metal oxide based devices, such as charge trapping, conductive filament formation, Schottky barrier modulation, and electrochemical migration of point defects. The underlying fundamental principles of the switching mechanism still lack a detailed understanding, i.e. how to control and modulate the electrical characteristics of devices incorporating defects and impurities, such as oxygen vacancies, metal interstitials, hydrogen, and other metallic atoms acting as dopants. In this paper, state of the art ab initio theoretical methods are employed to understand the effects that filamentary types of stable oxygen vacancy configurations in TiO(2) and NiO have on the electronic conduction. It is shown that strong electronic interactions between metal ions adjacent to oxygen vacancy sites results in the formation of a conductive path and thus can explain the 'ON' site conduction in these materials. Implication of hydrogen doping on electroforming is discussed for Pr(0.7)Ca(0.3)MnO(3) devices based on electrical characterization and FTIR measurements.

Exploration of perpendicular magnetic anisotropy material system for application in spin transfer torque - Random access memory

NASA Astrophysics Data System (ADS)

Natarajarathinam, Anusha

Perpendicular magnetic anisotropy (PMA) materials have unique advantages when used in magnetic tunnel junctions (MTJ) which are the most critical part of spin-torque transfer random access memory devices (STT-RAMs) that are being researched intensively as future non-volatile memory technology. They have high magnetoresistance which improves their sensitivity. The STT-RAM has several advantages over competing technologies, for instance, low power consumption, non-volatility, ultra-fast read and write speed and high endurance. In personal computers, it can replace SRAM for high-speed applications, Flash for non-volatility, and PSRAM and DRAM for high-speed program execution. The main aim of this research is to identify and optimize the best perpendicular magnetic anisotropy (PMA) material system for application to STT-RAM technology. Preliminary search for perpendicular magnetic anisotropy (PMA) materials for pinned layer for MTJs started with the exploration and optimization of crystalline alloys such as Co50Pd50 alloy, Mn50Al50 and amorphous alloys such as Tb21Fe72Co7 and are first presented in this work. Further optimization includes the study of Co/[Pd/Pt]x multilayers (ML), and the development of perpendicular synthetic antiferromagnets (SAF) utilizing these multilayers. Focused work on capping and seed layers to evaluate interfacial perpendicular anisotropy in free layers for pMTJs is then discussed. Optimization of the full perpendicular magnetic tunnel junction (pMTJ) includes the CoFeB/MgO/CoFeB trilayer coupled to a pinned/pinning layer with perpendicular Co/[Pd/Pt]x SAF and a thin Ta seeded CoFeB free layer. Magnetometry, simulations, annealing studies, transport measurements and TEM analysis on these samples will then be presented.

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Power- and Low-Resistance-State-Dependent, Bipolar Reset-Switching Transitions in SiN-Based Resistive Random-Access Memory

NASA Astrophysics Data System (ADS)

Kim, Sungjun; Park, Byung-Gook

2016-08-01

A study on the bipolar-resistive switching of an Ni/SiN/Si-based resistive random-access memory (RRAM) device shows that the influences of the reset power and the resistance value of the low-resistance state (LRS) on the reset-switching transitions are strong. For a low LRS with a large conducting path, the sharp reset switching, which requires a high reset power (>7 mW), was observed, whereas for a high LRS with small multiple-conducting paths, the step-by-step reset switching with a low reset power (<7 mW) was observed. The attainment of higher nonlinear current-voltage ( I-V) characteristics in terms of the step-by-step reset switching is due to the steep current-increased region of the trap-controlled space charge-limited current (SCLC) model. A multilevel cell (MLC) operation, for which the reset stop voltage ( V STOP) is used in the DC sweep mode and an incremental amplitude is used in the pulse mode for the step-by-step reset switching, is demonstrated here. The results of the present study suggest that well-controlled conducting paths in a SiN-based RRAM device, which are not too strong and not too weak, offer considerable potential for the realization of low-power and high-density crossbar-array applications.

Correlation of anomalous write error rates and ferromagnetic resonance spectrum in spin-transfer-torque-magnetic-random-access-memory devices containing in-plane free layers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evarts, Eric R.; Rippard, William H.; Pufall, Matthew R.

In a small fraction of magnetic-tunnel-junction-based magnetic random-access memory devices with in-plane free layers, the write-error rates (WERs) are higher than expected on the basis of the macrospin or quasi-uniform magnetization reversal models. In devices with increased WERs, the product of effective resistance and area, tunneling magnetoresistance, and coercivity do not deviate from typical device properties. However, the field-swept, spin-torque, ferromagnetic resonance (FS-ST-FMR) spectra with an applied DC bias current deviate significantly for such devices. With a DC bias of 300 mV (producing 9.9 × 10{sup 6} A/cm{sup 2}) or greater, these anomalous devices show an increase in the fraction of the power presentmore » in FS-ST-FMR modes corresponding to higher-order excitations of the free-layer magnetization. As much as 70% of the power is contained in higher-order modes compared to ≈20% in typical devices. Additionally, a shift in the uniform-mode resonant field that is correlated with the magnitude of the WER anomaly is detected at DC biases greater than 300 mV. These differences in the anomalous devices indicate a change in the micromagnetic resonant mode structure at high applied bias.« less

Nonvolatile random access memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

1994-01-01

A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

A Collective Study on Modeling and Simulation of Resistive Random Access Memory

NASA Astrophysics Data System (ADS)

Panda, Debashis; Sahu, Paritosh Piyush; Tseng, Tseung Yuen

2018-01-01

In this work, we provide a comprehensive discussion on the various models proposed for the design and description of resistive random access memory (RRAM), being a nascent technology is heavily reliant on accurate models to develop efficient working designs and standardize its implementation across devices. This review provides detailed information regarding the various physical methodologies considered for developing models for RRAM devices. It covers all the important models reported till now and elucidates their features and limitations. Various additional effects and anomalies arising from memristive system have been addressed, and the solutions provided by the models to these problems have been shown as well. All the fundamental concepts of RRAM model development such as device operation, switching dynamics, and current-voltage relationships are covered in detail in this work. Popular models proposed by Chua, HP Labs, Yakopcic, TEAM, Stanford/ASU, Ielmini, Berco-Tseng, and many others have been compared and analyzed extensively on various parameters. The working and implementations of the window functions like Joglekar, Biolek, Prodromakis, etc. has been presented and compared as well. New well-defined modeling concepts have been discussed which increase the applicability and accuracy of the models. The use of these concepts brings forth several improvements in the existing models, which have been enumerated in this work. Following the template presented, highly accurate models would be developed which will vastly help future model developers and the modeling community.

Solving the integration problem of one transistor one memristor architecture with a Bi-layer IGZO film through synchronous process

NASA Astrophysics Data System (ADS)

Chang, Che-Chia; Liu, Po-Tsun; Chien, Chen-Yu; Fan, Yang-Shun

2018-04-01

This study demonstrates the integration of a thin film transistor (TFT) and resistive random-access memory (RRAM) to form a one-transistor-one-resistor (1T1R) configuration. With the concept of the current conducting direction in RRAM and TFT, a triple-layer stack design of Pt/InGaZnO/Al2O3 is proposed for both the switching layer of RRAM and the channel layer of TFT. This proposal decreases the complexity of fabrication and the numbers of photomasks required. Also, the robust endurance and stable retention characteristics are exhibited by the 1T1R architecture for promising applications in memory-embedded flat panel displays.

Organic nonvolatile resistive memory devices based on thermally deposited Au nanoparticle

NASA Astrophysics Data System (ADS)

Jin, Zhiwen; Liu, Guo; Wang, Jizheng

2013-05-01

Uniform Au nanoparticles (NPs) are formed by thermally depositing nominal 2-nm thick Au film on a 10-nm thick polyimide film formed on a Al electrode, and then covered by a thin polymer semiconductor film, which acts as an energy barrier for electrons to be injected from the other Al electrode (on top of polymer film) into the Au NPs, which are energetically electron traps in such a resistive random access memory (RRAM) device. The Au NPs based RRAM device exhibits estimated retention time of 104 s, cycle times of more than 100, and ON-OFF ratio of 102 to 103. The carrier transport properties are also analyzed by fitting the measured I-V curves with several conduction models.

An automatic analyzer of solid state nuclear track detectors using an optic RAM as image sensor

NASA Astrophysics Data System (ADS)

Staderini, Enrico Maria; Castellano, Alfredo

1986-02-01

An optic RAM is a conventional digital random access read/write dynamic memory device featuring a quartz windowed package and memory cells regularly ordered on the chip. Such a device is used as an image sensor because each cell retains data stored in it for a time depending on the intensity of the light incident on the cell itself. The authors have developed a system which uses an optic RAM to acquire and digitize images from electrochemically etched CR39 solid state nuclear track detectors (SSNTD) in the track count rate up to 5000 cm -2. On the digital image so obtained, a microprocessor, with appropriate software, performs image analysis, filtering, tracks counting and evaluation.

Magnetic field dependence of spin torque switching in nanoscale magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Yang, Liu; Rowlands, Graham; Katine, Jordan; Langer, Juergen; Krivorotov, Ilya

2012-02-01

Magnetic random access memory based on spin transfer torque effect in nanoscale magnetic tunnel junctions (STT-RAM) is emerging as a promising candidate for embedded and stand-alone computer memory. An important performance parameter of STT-RAM is stability of its free magnetic layer against thermal fluctuations. Measurements of the free layer switching probability as a function of sub-critical voltage at zero effective magnetic field (read disturb rate or RDR measurements) have been proposed as a method for quantitative evaluation of the free layer thermal stability at zero voltage. In this presentation, we report RDR measurement as a function of external magnetic field, which provide a test of the RDR method self-consistency and reliability.

Low latency and persistent data storage

DOEpatents

Fitch, Blake G; Franceschini, Michele M; Jagmohan, Ashish; Takken, Todd E

2014-02-18

Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

System and method for programmable bank selection for banked memory subsystems

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Microscopic origin of read current noise in TaOx-based resistive switching memory by ultra-low temperature measurement

NASA Astrophysics Data System (ADS)

Pan, Yue; Cai, Yimao; Liu, Yefan; Fang, Yichen; Yu, Muxi; Tan, Shenghu; Huang, Ru

2016-04-01

TaOx-based resistive random access memory (RRAM) attracts considerable attention for the development of next generation nonvolatile memories. However, read current noise in RRAM is one of the critical concerns for storage application, and its microscopic origin is still under debate. In this work, the read current noise in TaOx-based RRAM was studied thoroughly. Based on a noise power spectral density analysis at room temperature and at ultra-low temperature of 25 K, discrete random telegraph noise (RTN) and continuous average current fluctuation (ACF) are identified and decoupled from the total read current noise in TaOx RRAM devices. A statistical comparison of noise amplitude further reveals that ACF depends strongly on the temperature, whereas RTN is independent of the temperature. Measurement results combined with conduction mechanism analysis show that RTN in TaOx RRAM devices arises from electron trapping/detrapping process in the hopping conduction, and ACF is originated from the thermal activation of conduction centers that form the percolation network. At last, a unified model in the framework of hopping conduction is proposed to explain the underlying mechanism of both RTN and ACF noise, which can provide meaningful guidelines for designing noise-immune RRAM devices.

Accessibility versus Accuracy in Retrieving Spatial Memory: Evidence for Suboptimal Assumed Headings

ERIC Educational Resources Information Center

Yerramsetti, Ashok; Marchette, Steven A.; Shelton, Amy L.

2013-01-01

Orientation dependence in spatial memory has often been interpreted in terms of accessibility: Object locations are encoded relative to a reference orientation that affords the most accurate access to spatial memory. An open question, however, is whether people naturally use this "preferred" orientation whenever recalling the space. We…

Current-limiting and ultrafast system for the characterization of resistive random access memories.

PubMed

Diaz-Fortuny, J; Maestro, M; Martin-Martinez, J; Crespo-Yepes, A; Rodriguez, R; Nafria, M; Aymerich, X

2016-06-01

A new system for the ultrafast characterization of resistive switching phenomenon is developed to acquire the current during the Set and Reset process in a microsecond time scale. A new electronic circuit has been developed as a part of the main setup system, which is capable of (i) applying a hardware current limit ranging from nanoampers up to miliampers and (ii) converting the Set and Reset exponential gate current range into an equivalent linear voltage. The complete system setup allows measuring with a microsecond resolution. Some examples demonstrate that, with the developed setup, an in-depth analysis of resistive switching phenomenon and random telegraph noise can be made.

Low latency and persistent data storage

DOEpatents

Fitch, Blake G; Franceschini, Michele M; Jagmohan, Ashish; Takken, Todd

2014-11-04

Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Optical memories in digital computing

NASA Technical Reports Server (NTRS)

Alford, C. O.; Gaylord, T. K.

1979-01-01

High capacity optical memories with relatively-high data-transfer rate and multiport simultaneous access capability may serve as basis for new computer architectures. Several computer structures that might profitably use memories are: a) simultaneous record-access system, b) simultaneously-shared memory computer system, and c) parallel digital processing structure.

Design, processing, and testing of lsi arrays for space station

NASA Technical Reports Server (NTRS)

Lile, W. R.; Hollingsworth, R. J.

1972-01-01

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Total Ionizing Dose Influence on the Single-Event Upset Sensitivity of 130-nm PD SOI SRAMs

NASA Astrophysics Data System (ADS)

Zheng, Qiwen; Cui, Jiangwei; Liu, Mengxin; Zhou, Hang; Liu, Mohan; Wei, Ying; Su, Dandan; Ma, Teng; Lu, Wu; Yu, Xuefeng; Guo, Qi; He, Chengfa

2017-07-01

Effect of total ionizing dose (TID) on single-event upset (SEU) hardness of 130 nm partially depleted (PD) silicon-on-insulator (SOI) static random access memories (SRAMs) is investigated in this paper. The measurable synergistic effect of TID on SEU sensitivity of 130-nm PD SOI SRAM was observed in our experiment, even though that is far less than micrometer and submicrometer devices. Moreover, SEU cross section after TID irradiation has no dependence on the data pattern that was applied during TID exposure: SEU cross sections are characterized by TID data pattern and its complement data pattern are decreased consistently rather than a preferred state and a nonpreferred state as micrometer and sub-micrometer SRAMs. The memory cell test structure allowing direct measurement of static noise margin (SNM) under standby operation was designed using identical memory cell layout of SRAM. Direct measurement of the memory cell SNM shows that both data sides' SNM is decreased by TID, indicating that SEU cross section of 130-nm PD SOI SRAM will be increased by TID. And, the decreased SNM is caused by threshold shift in memory cell transistors induced by “radiation-induced narrow channel effect”.

How intention and monitoring your thoughts influence characteristics of autobiographical memories.

PubMed

Barzykowski, Krystian; Staugaard, Søren Risløv

2018-05-01

Involuntary autobiographical memories come to mind effortlessly and unintended, but the mechanisms of their retrieval are not fully understood. We hypothesize that involuntary retrieval depends on memories that are highly accessible (e.g., intense, unusual, recent, rehearsed), while the elaborate search that characterizes voluntary retrieval also produces memories that are mundane, repeated or distant - memories with low accessibility. Previous research provides some evidence for this 'threshold hypothesis'. However, in almost every prior study, participants have been instructed to report only memories while ignoring other thoughts. It is possible that such an instruction can modify the phenomenological characteristics of involuntary memories. This study aimed to investigate the effects of retrieval intentionality (i.e., wanting to retrieve a memory) and selective monitoring (i.e., instructions to report only memories) on the phenomenology of autobiographical memories. Participants were instructed to (1) intentionally retrieve autobiographical memories, (2) intentionally retrieve any type of thought (3) wait for an autobiographical memory to spontaneously appear, or (4) wait for any type of thought to spontaneously appear. They rated the mental content on a number of phenomenological characteristics both during retrieval and retrospectively following retrieval. The results support the prediction that highly accessible memories mostly enter awareness unintended and without selective monitoring, while memories with low accessibility rely on intention and selective monitoring. We discuss the implications of these effects. © 2017 The British Psychological Society.

ASPEN Version 3.0

NASA Technical Reports Server (NTRS)

Rabideau, Gregg; Chien, Steve; Knight, Russell; Schaffer, Steven; Tran, Daniel; Cichy, Benjamin; Sherwood, Robert

2006-01-01

The Automated Scheduling and Planning Environment (ASPEN) computer program has been updated to version 3.0. ASPEN is a modular, reconfigurable, application software framework for solving batch problems that involve reasoning about time, activities, states, and resources. Applications of ASPEN can include planning spacecraft missions, scheduling of personnel, and managing supply chains, inventories, and production lines. ASPEN 3.0 can be customized for a wide range of applications and for a variety of computing environments that include various central processing units and random access memories.

Multiple channel programmable coincidence counter

DOEpatents

Arnone, Gaetano J.

1990-01-01

A programmable digital coincidence counter having multiple channels and featuring minimal dead time. Neutron detectors supply electrical pulses to a synchronizing circuit which in turn inputs derandomized pulses to an adding circuit. A random access memory circuit connected as a programmable length shift register receives and shifts the sum of the pulses, and outputs to a serializer. A counter is input by the adding circuit and downcounted by the seralizer, one pulse at a time. The decoded contents of the counter after each decrement is output to scalers.

Operating System For Numerically Controlled Milling Machine

NASA Technical Reports Server (NTRS)

Ray, R. B.

1992-01-01

OPMILL program is operating system for Kearney and Trecker milling machine providing fast easy way to program manufacture of machine parts with IBM-compatible personal computer. Gives machinist "equation plotter" feature, which plots equations that define movements and converts equations to milling-machine-controlling program moving cutter along defined path. System includes tool-manager software handling up to 25 tools and automatically adjusts to account for each tool. Developed on IBM PS/2 computer running DOS 3.3 with 1 MB of random-access memory.

An Embedded Fusion Processor

DTIC Science & Technology

2000-10-01

available from rooksj~,rl.af.mil [4] J. Lyke and G. Forman "Microengineering Aerospace Systems" H . Helvajian editor, The Aerospace Press 1999, Chapter 8...e h I O iinterface chip, and Synchronous Dynamic Random 1K-byte. The only consequence is that after the FIFO is Access Memory (SDRAM). Each interface...shown in figure 4a, that will be used for the 1/O interconnects in place of the perimeter bond pads used in the MCM3A. The 6’ h layer is used to

A Study of a Standard BIT Circuit.

DTIC Science & Technology

1977-02-01

IENDED BIT APPROACHES FOR QED MODULES AND APPLICATION OF THE ANALYTIC MEASURES 36 4.1 Built-In-Test for Memory Class Modules 37 4.1.1 Random Access...Implementation 68 4.1.5.5 Criti cal Parameters 68 4.1.5.6 QED Module Test Equipment Requirements 68 4.1.6 Application of Analytic Measures to the...Microprocessor BIT Techniques.. 121 4.2.9 Application of Analytic Measures to the Recommended BIT App roaches 125 4.2.10 Process Class BIT by Partial

On VLSI Design of Rank-Order Filtering using DCRAM Architecture

PubMed Central

Lin, Meng-Chun; Dung, Lan-Rong

2009-01-01

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply. PMID:19865599

The Shark Random Swim - (Lévy Flight with Memory)

NASA Astrophysics Data System (ADS)

Businger, Silvia

2018-05-01

The Elephant Random Walk (ERW), first introduced by Schütz and Trimper (Phys Rev E 70:045101, 2004), is a one-dimensional simple random walk on Z having a memory about the whole past. We study the Shark Random Swim, a random walk with memory about the whole past, whose steps are α -stable distributed with α \\in (0,2] . Our aim in this work is to study the impact of the heavy tailed step distributions on the asymptotic behavior of the random walk. We shall see that, as for the ERW, the asymptotic behavior of the Shark Random Swim depends on its memory parameter p, and that a phase transition can be observed at the critical value p=1/α.

Automatic disease diagnosis using optimised weightless neural networks for low-power wearable devices

PubMed Central

Edla, Damodar Reddy; Kuppili, Venkatanareshbabu; Dharavath, Ramesh; Beechu, Nareshkumar Reddy

2017-01-01

Low-power wearable devices for disease diagnosis are used at anytime and anywhere. These are non-invasive and pain-free for the better quality of life. However, these devices are resource constrained in terms of memory and processing capability. Memory constraint allows these devices to store a limited number of patterns and processing constraint provides delayed response. It is a challenging task to design a robust classification system under above constraints with high accuracy. In this Letter, to resolve this problem, a novel architecture for weightless neural networks (WNNs) has been proposed. It uses variable sized random access memories to optimise the memory usage and a modified binary TRIE data structure for reducing the test time. In addition, a bio-inspired-based genetic algorithm has been employed to improve the accuracy. The proposed architecture is experimented on various disease datasets using its software and hardware realisations. The experimental results prove that the proposed architecture achieves better performance in terms of accuracy, memory saving and test time as compared to standard WNNs. It also outperforms in terms of accuracy as compared to conventional neural network-based classifiers. The proposed architecture is a powerful part of most of the low-power wearable devices for the solution of memory, accuracy and time issues. PMID:28868148

A DNA-based pattern classifier with in vitro learning and associative recall for genomic characterization and biosensing without explicit sequence knowledge.

PubMed

Lee, Ju Seok; Chen, Junghuei; Deaton, Russell; Kim, Jin-Woo

2014-01-01

Genetic material extracted from in situ microbial communities has high promise as an indicator of biological system status. However, the challenge is to access genomic information from all organisms at the population or community scale to monitor the biosystem's state. Hence, there is a need for a better diagnostic tool that provides a holistic view of a biosystem's genomic status. Here, we introduce an in vitro methodology for genomic pattern classification of biological samples that taps large amounts of genetic information from all genes present and uses that information to detect changes in genomic patterns and classify them. We developed a biosensing protocol, termed Biological Memory, that has in vitro computational capabilities to "learn" and "store" genomic sequence information directly from genomic samples without knowledge of their explicit sequences, and that discovers differences in vitro between previously unknown inputs and learned memory molecules. The Memory protocol was designed and optimized based upon (1) common in vitro recombinant DNA operations using 20-base random probes, including polymerization, nuclease digestion, and magnetic bead separation, to capture a snapshot of the genomic state of a biological sample as a DNA memory and (2) the thermal stability of DNA duplexes between new input and the memory to detect similarities and differences. For efficient read out, a microarray was used as an output method. When the microarray-based Memory protocol was implemented to test its capability and sensitivity using genomic DNA from two model bacterial strains, i.e., Escherichia coli K12 and Bacillus subtilis, results indicate that the Memory protocol can "learn" input DNA, "recall" similar DNA, differentiate between dissimilar DNA, and detect relatively small concentration differences in samples. This study demonstrated not only the in vitro information processing capabilities of DNA, but also its promise as a genomic pattern classifier that could access information from all organisms in a biological system without explicit genomic information. The Memory protocol has high potential for many applications, including in situ biomonitoring of ecosystems, screening for diseases, biosensing of pathological features in water and food supplies, and non-biological information processing of memory devices, among many.

UPC++ Programmer’s Guide (v1.0 2017.9)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bachan, J.; Baden, S.; Bonachea, D.

UPC++ is a C++11 library that provides Asynchronous Partitioned Global Address Space (APGAS) programming. It is designed for writing parallel programs that run efficiently and scale well on distributed-memory parallel computers. The APGAS model is single program, multiple-data (SPMD), with each separate thread of execution (referred to as a rank, a term borrowed from MPI) having access to local memory as it would in C++. However, APGAS also provides access to a global address space, which is allocated in shared segments that are distributed over the ranks. UPC++ provides numerous methods for accessing and using global memory. In UPC++, allmore » operations that access remote memory are explicit, which encourages programmers to be aware of the cost of communication and data movement. Moreover, all remote-memory access operations are by default asynchronous, to enable programmers to write code that scales well even on hundreds of thousands of cores.« less

UPC++ Programmer’s Guide, v1.0-2018.3.0

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bachan, J.; Baden, S.; Bonachea, Dan

UPC++ is a C++11 library that provides Partitioned Global Address Space (PGAS) programming. It is designed for writing parallel programs that run efficiently and scale well on distributed-memory parallel computers. The PGAS model is single program, multiple-data (SPMD), with each separate thread of execution (referred to as a rank, a term borrowed from MPI) having access to local memory as it would in C++. However, PGAS also provides access to a global address space, which is allocated in shared segments that are distributed over the ranks. UPC++ provides numerous methods for accessing and using global memory. In UPC++, all operationsmore » that access remote memory are explicit, which encourages programmers to be aware of the cost of communication and data movement. Moreover, all remote-memory access operations are by default asynchronous, to enable programmers to write code that scales well even on hundreds of thousands of cores.« less

Genetic algorithms with memory- and elitism-based immigrants in dynamic environments.

PubMed

Yang, Shengxiang

2008-01-01

In recent years the genetic algorithm community has shown a growing interest in studying dynamic optimization problems. Several approaches have been devised. The random immigrants and memory schemes are two major ones. The random immigrants scheme addresses dynamic environments by maintaining the population diversity while the memory scheme aims to adapt genetic algorithms quickly to new environments by reusing historical information. This paper investigates a hybrid memory and random immigrants scheme, called memory-based immigrants, and a hybrid elitism and random immigrants scheme, called elitism-based immigrants, for genetic algorithms in dynamic environments. In these schemes, the best individual from memory or the elite from the previous generation is retrieved as the base to create immigrants into the population by mutation. This way, not only can diversity be maintained but it is done more efficiently to adapt genetic algorithms to the current environment. Based on a series of systematically constructed dynamic problems, experiments are carried out to compare genetic algorithms with the memory-based and elitism-based immigrants schemes against genetic algorithms with traditional memory and random immigrants schemes and a hybrid memory and multi-population scheme. The sensitivity analysis regarding some key parameters is also carried out. Experimental results show that the memory-based and elitism-based immigrants schemes efficiently improve the performance of genetic algorithms in dynamic environments.

A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Graham, Paul S; Morgan, Keith S

2008-01-01

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA usermore » designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.« less

Vividness of visual imagery and incidental recall of verbal cues, when phenomenological availability reflects long-term memory accessibility.

PubMed

D'Angiulli, Amedeo; Runge, Matthew; Faulkner, Andrew; Zakizadeh, Jila; Chan, Aldrich; Morcos, Selvana

2013-01-01

The relationship between vivid visual mental images and unexpected recall (incidental recall) was replicated, refined, and extended. In Experiment 1, participants were asked to generate mental images from imagery-evoking verbal cues (controlled on several verbal properties) and then, on a trial-by-trial basis, rate the vividness of their images; 30 min later, participants were surprised with a task requiring free recall of the cues. Higher vividness ratings predicted better incidental recall of the cues than individual differences (whose effect was modest). Distributional analysis of image latencies through ex-Gaussian modeling showed an inverse relation between vividness and latency. However, recall was unrelated to image latency. The follow-up Experiment 2 showed that the processes underlying trial-by-trial vividness ratings are unrelated to the Vividness of Visual Imagery Questionnaire (VVIQ), as further supported by a meta-analysis of a randomly selected sample of relevant literature. The present findings suggest that vividness may act as an index of availability of long-term sensory traces, playing a non-epiphenomenal role in facilitating the access of those memories.

Vividness of Visual Imagery and Incidental Recall of Verbal Cues, When Phenomenological Availability Reflects Long-Term Memory Accessibility

PubMed Central

D’Angiulli, Amedeo; Runge, Matthew; Faulkner, Andrew; Zakizadeh, Jila; Chan, Aldrich; Morcos, Selvana

2013-01-01

The relationship between vivid visual mental images and unexpected recall (incidental recall) was replicated, refined, and extended. In Experiment 1, participants were asked to generate mental images from imagery-evoking verbal cues (controlled on several verbal properties) and then, on a trial-by-trial basis, rate the vividness of their images; 30 min later, participants were surprised with a task requiring free recall of the cues. Higher vividness ratings predicted better incidental recall of the cues than individual differences (whose effect was modest). Distributional analysis of image latencies through ex-Gaussian modeling showed an inverse relation between vividness and latency. However, recall was unrelated to image latency. The follow-up Experiment 2 showed that the processes underlying trial-by-trial vividness ratings are unrelated to the Vividness of Visual Imagery Questionnaire (VVIQ), as further supported by a meta-analysis of a randomly selected sample of relevant literature. The present findings suggest that vividness may act as an index of availability of long-term sensory traces, playing a non-epiphenomenal role in facilitating the access of those memories. PMID:23382719

Grouper: A Compact, Streamable Triangle Mesh Data Structure.

PubMed

Luffel, Mark; Gurung, Topraj; Lindstrom, Peter; Rossignac, Jarek

2013-05-08

We present Grouper: an all-in-one compact file format, random-access data structure, and streamable representation for large triangle meshes. Similarly to the recently published SQuad representation, Grouper represents the geometry and connectivity of a mesh by grouping vertices and triangles into fixed-size records, most of which store two adjacent triangles and a shared vertex. Unlike SQuad, however, Grouper interleaves geometry with connectivity and uses a new connectivity representation to ensure that vertices and triangles can be stored in a coherent order that enables memory-efficient sequential stream processing. We present a linear-time construction algorithm that allows streaming out Grouper meshes using a small memory footprint while preserving the initial ordering of vertices. As part of this construction, we show how the problem of assigning vertices and triangles to groups reduces to a well-known NP-hard optimization problem, and present a simple yet effective heuristic solution that performs well in practice. Our array-based Grouper representation also doubles as a triangle mesh data structure that allows direct access to vertices and triangles. Storing only about two integer references per triangle, Grouper answers both incidence and adjacency queries in amortized constant time. Our compact representation enables data-parallel processing on multicore computers, instant partitioning and fast transmission for distributed processing, as well as efficient out-of-core access.

Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, Alan; Ohmacht, Martin

A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memorymore » access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Braiman, Yehuda; Neschke, Brendan; Nair, Niketh S.

Here, we study memory states of a circuit consisting of a small inductively coupled Josephson junction array and introduce basic (write, read, and reset) memory operations logics of the circuit. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics. We calculate stability diagrams of the zero-voltage states and outline memory states of the circuit. We also calculate access times and access energies for basic memory operations.

SIERRA - A 3-D device simulator for reliability modeling

NASA Astrophysics Data System (ADS)

Chern, Jue-Hsien; Arledge, Lawrence A., Jr.; Yang, Ping; Maeda, John T.

1989-05-01

SIERRA is a three-dimensional general-purpose semiconductor-device simulation program which serves as a foundation for investigating integrated-circuit (IC) device and reliability issues. This program solves the Poisson and continuity equations in silicon under dc, transient, and small-signal conditions. Executing on a vector/parallel minisupercomputer, SIERRA utilizes a matrix solver which uses an incomplete LU (ILU) preconditioned conjugate gradient square (CGS, BCG) method. The ILU-CGS method provides a good compromise between memory size and convergence rate. The authors have observed a 5x to 7x speedup over standard direct methods in simulations of transient problems containing highly coupled Poisson and continuity equations such as those found in reliability-oriented simulations. The application of SIERRA to parasitic CMOS latchup and dynamic random-access memory single-event-upset studies is described.

Digital correlation detector for low-cost Omega navigation

NASA Technical Reports Server (NTRS)

Chamberlin, K. A.

1976-01-01

Techniques to lower the cost of using the Omega global navigation network with phase-locked loops (PLL) were developed. The technique that was accepted as being "optimal" is called the memory-aided phase-locked loop (MAPLL) since it allows operation on all eight Omega time slots with one PLL through the implementation of a random access memory. The receiver front-end and the signals that it transmits to the PLL were first described. A brief statistical analysis of these signals was then made to allow a rough comparison between the front-end presented in this work and a commercially available front-end to be made. The hardware and theory of application of the MAPLL were described, ending with an analysis of data taken with the MAPLL. Some conclusions and recommendations were also given.

Development of non-volatile semiconductor memory

NASA Technical Reports Server (NTRS)

Heikkila, W. W.

1979-01-01

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Oxygen-ion-migration-modulated bipolar resistive switching and complementary resistive switching in tungsten/indium tin oxide/gold memory device

NASA Astrophysics Data System (ADS)

Wu, Xinghui; Zhang, Qiuhui; Cui, Nana; Xu, Weiwei; Wang, Kefu; Jiang, Wei; Xu, Qixing

2018-06-01

In this paper, we report our investigation of room-temperature-fabricated tungsten/indium tin oxide/gold (W/ITO/Au) resistive random access memory (RRAM), which exhibits asymmetric bipolar resistive switching (BRS) behavior. The device displays good write/erase endurance and data retention properties. The device shows complementary resistive switching (CRS) characteristics after controlling the compliance current. A WO x layer electrically formed at the W/ITO in the forming process. Mobile oxygen ions within ITO migrate toward the electrode/ITO interface and produce a semiconductor-like layer that acts as a free-carrier barrier. The CRS characteristic here can be elucidated in light of the evolution of an asymmetric free-carrier blocking layer at the electrode/ITO interface.

Distributed multiport memory architecture

NASA Technical Reports Server (NTRS)

Kohl, W. H. (Inventor)

1983-01-01

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

A memory and organizational aid improves Alzheimer disease research consent capacity: results of a randomized, controlled trial.

PubMed

Rubright, Jonathan; Sankar, Pamela; Casarett, David J; Gur, Ruben; Xie, Sharon X; Karlawish, Jason

2010-12-01

Early and progressive cognitive impairments of patients with Alzheimer disease (AD) hinder their capacity to provide informed consent. Unfortunately, the limited research on techniques to improve capacity has shown mixed results. Therefore, the authors tested whether a memory and organizational aid improves the performance of patients with AD on measures of capacity and competency to give informed consent. Patients with AD randomly assigned to standard consent or standard plus a memory and organizational aid. Memory and organizational aid summarized the content of information mandated under the informed consent disclosure requirements of the Common Rule at a sixth grade reading level. Three psychiatrists without access to patient data independently reviewed MacArthur Competence Assessment Tool for Clinical Research (MacCAT-CR) interview transcripts to judge whether the patient was capable of providing informed consent. The agreement of at least two of the three experts defined a participant as capable of providing informed consent. Secondary outcomes are MacCAT-CR measures of understanding, appreciation and reasoning, and comparison with cognitively normal older adult norms. AD intervention and control groups were similar in terms of age, education, and cognitive status. The intervention group was more likely to be judged competent than control group and had higher scores on MacCAT-CR measure of understanding. The intervention had no effect on the measures of appreciation or reasoning. A consent process that addresses the deficits in memory and attention of a patient with AD can improve capacity to give informed consent for early phase AD research. The results also validate the MacCAT-CR as an instrument to measure capacity, especially the understanding subscale. ClinicalTrials.Gov#NCT00105612, http://clinicaltrials.gov/show/NCT00105612.

A memory and organizational aid improves AD research consent capacity: Results of a randomized, controlled trial

PubMed Central

Rubright, Jonathan; Sankar, Pamela; Casarett, David J; Gur, Ruben; Xie, Sharon X; Karlawish, Jason

2010-01-01

Objectives AD patients' early and progressive cognitive impairments hinder their capacity to provide informed consent. Unfortunately, the limited research on techniques to improve capacity has shown mixed results. Therefore, we tested whether a memory and organizational aid improves AD patient performance on measures of capacity and competency to give informed consent. Design, Setting, and Participants AD patients randomly assigned to standard consent, or standard plus a memory and organizational aid. Intervention Memory and organizational aid summarized at a 6th grade reading level the content of information mandated under the Common Rule's informed consent disclosure requirements. Measurements Three psychiatrists without access to patient data independently reviewed MacArthur Competence Assessment Tool for Clinical Research (MacCAT-CR) interview transcripts to judge whether the patient was capable of providing informed consent. The agreement of at least two of three experts defined a participant as capable of providing informed consent. Secondary outcomes are MacCAT-CR measures of understanding, appreciation and reasoning, and comparison to cognitively normal older adult norms. Results AD intervention and control groups were similar in terms of age, education, and cognitive status. The intervention group was more likely to be judged competent than control group and had higher scores on MacCAT-CR measure of understanding. The intervention had no effect on measures of appreciation or reasoning. Conclusions A consent process that addresses an AD patients' deficits in memory and attention can improve capacity to give informed consent for early phase AD research. The results also validate the MacCAT-CR as an instrument to measure capacity, especially the understanding subscale. PMID:20808101

CMOS-compatible spintronic devices: a review

NASA Astrophysics Data System (ADS)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Resistive switching mechanism in the one diode-one resistor memory based on p+-Si/n-ZnO heterostructure revealed by in-situ TEM

NASA Astrophysics Data System (ADS)

Zhang, Lei; Zhu, Liang; Li, Xiaomei; Xu, Zhi; Wang, Wenlong; Bai, Xuedong

2017-03-01

One diode-one resistor (1D1R) memory is an effective architecture to suppress the crosstalk interference, realizing the crossbar network integration of resistive random access memory (RRAM). Herein, we designed a p+-Si/n-ZnO heterostructure with 1D1R function. Compared with the conventional multilayer 1D1R devices, the structure and fabrication technique can be largely simplified. The real-time imaging of formation/rupture process of conductive filament (CF) process demonstrated the RS mechanism by in-situ transmission electron microscopy (TEM). Meanwhile, we observed that the formed CF is only confined to the outside of depletion region of Si/ZnO pn junction, and the formation of CF does not degrade the diode performance, which allows the coexistence of RS and rectifying behaviors, revealing the 1D1R switching model. Furthermore, it has been confirmed that the CF is consisting of the oxygen vacancy by in-situ TEM characterization.

A new non-destructive readout by using photo-recovered surface potential contrast

NASA Astrophysics Data System (ADS)

Wang, Le; Jin, Kui-Juan; Gu, Jun-Xing; Ma, Chao; He, Xu; Zhang, Jiandi; Wang, Can; Feng, Yu; Wan, Qian; Shi, Jin-An; Gu, Lin; He, Meng; Lu, Hui-Bin; Yang, Guo-Zhen

2014-11-01

Ferroelectric random access memory is still challenging in the feature of combination of room temperature stability, non-destructive readout and high intensity storage. As a non-contact and non-destructive information readout method, surface potential has never been paid enough attention because of the unavoidable decay of the surface potential contrast between oppositely polarized domains. That is mainly due to the recombination of the surface movable charges around the domain walls. Here, by introducing a laser beam into the combination of piezoresponse force microscopy and Kelvin probe force microscopy, we demonstrate that the surface potential contrast of BiFeO3 films can be recovered under light illumination. The recovering mechanism is understood based on the redistribution of the photo-induced charges driven by the internal electric field. Furthermore, we have created a 12-cell memory pattern based on BiFeO3 films to show the feasibility of such photo-assisted non-volatile and non-destructive readout of the ferroelectric memory.

Forming free and ultralow-power erase operation in atomically crystal TiO2 resistive switching

NASA Astrophysics Data System (ADS)

Dai, Yawei; Bao, Wenzhong; Hu, Linfeng; Liu, Chunsen; Yan, Xiao; Chen, Lin; Sun, Qingqing; Ding, Shijin; Zhou, Peng; Zhang, David Wei

2017-06-01

Two-dimensional layered materials (2DLMs) have attracted broad interest from fundamental sciences to industrial applications. Their applications in memory devices have been demonstrated, yet much still remains to explore optimal materials and device structure for practical application. In this work, a forming-free, bipolar resistive switching behavior are demonstrated in 2D TiO2-based resistive random access memory (RRAM). Physical adsorption method is adopted to achieve high quality, continuous 2D TiO2 network efficiently. The 2D TiO2 RRAM devices exhibit superior properties such as fast switching capability (20 ns of erase operation) and extremely low erase energy consumption (0.16 fJ). Furthermore, the resistive switching mechanism is attributed to the formation and rupture of oxygen vacancies-based percolation path in 2D TiO2 crystals. Our results pave the way for the implementation of high performance 2DLMs-based RRAM in the next generation non-volatile memory (NVM) application.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

PubMed Central

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-01-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced. PMID:27834352

Super non-linear RRAM with ultra-low power for 3D vertical nano-crossbar arrays.

PubMed

Luo, Qing; Xu, Xiaoxin; Liu, Hongtao; Lv, Hangbing; Gong, Tiancheng; Long, Shibing; Liu, Qi; Sun, Haitao; Banerjee, Writam; Li, Ling; Gao, Jianfeng; Lu, Nianduan; Liu, Ming

2016-08-25

Vertical crossbar arrays provide a cost-effective approach for high density three-dimensional (3D) integration of resistive random access memory. However, an individual selector device is not allowed to be integrated with the memory cell separately. The development of V-RRAM has impeded the lack of satisfactory self-selective cells. In this study, we have developed a high performance bilayer self-selective device using HfO2 as the memory switching layer and a mixed ionic and electron conductor as the selective layer. The device exhibits high non-linearity (>10(3)) and ultra-low half-select leakage (<0.1 pA). A four layer vertical crossbar array was successfully demonstrated based on the developed self-selective device. High uniformity, ultra-low leakage, sub-nA operation, self-compliance, and excellent read/write disturbance immunity were achieved. The robust array level performance shows attractive potential for low power and high density 3D data storage applications.

Capacitorless 1T-DRAM on crystallized poly-Si TFT.

PubMed

Kim, Min Soo; Cho, Won Ju

2011-07-01

The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic.

PubMed

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-11

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

NASA Astrophysics Data System (ADS)

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Metal-ferroelectric-metal capacitor based persistent memory for electronic product code class-1 generation-2 uhf passive radio-frequency identification tag

NASA Astrophysics Data System (ADS)

Yoon, Bongno; Sung, Man Young; Yeon, Sujin; Oh, Hyun S.; Kwon, Yoonjoo; Kim, Chuljin; Kim, Kyung-Ho

2009-03-01

With the circuits using metal-ferroelectric-metal (MFM) capacitor, rf operational signal properties are almost the same or superior to those of polysilicon-insulator-polysilicon, metal-insulator-metal, and metal-oxide-semiconductor (MOS) capacitors. In electronic product code global class-1 generation-2 uhf radio-frequency identification (RFID) protocols, the MFM can play a crucial role in satisfying the specifications of the inventoried flag's persistence times (Tpt) for each session (S0-S3, SL). In this paper, we propose and design a new MFM capacitor based memory scheme of which persistence time for S1 flag is measured at 2.2 s as well as indefinite for S2, S3, and SL flags during the period of power-on. A ferroelectric random access memory embedded RFID tag chip is fabricated with an industry-standard complementary MOS process. The chip size is around 500×500 μm2 and the measured power consumption is about 10 μW.

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

PubMed Central

Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

2016-01-01

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption. PMID:27312225

Synchrotron radiation x-ray photoelectron spectroscopy study on the interface chemistry of high-k PrxAl2-xO3 (x=0-2) dielectrics on TiN for dynamic random access memory applications

NASA Astrophysics Data System (ADS)

Schroeder, T.; Lupina, G.; Sohal, R.; Lippert, G.; Wenger, Ch.; Seifarth, O.; Tallarida, M.; Schmeisser, D.

2007-07-01

Engineered dielectrics combined with compatible metal electrodes are important materials science approaches to scale three-dimensional trench dynamic random access memory (DRAM) cells. Highly insulating dielectrics with high dielectric constants were engineered in this study on TiN metal electrodes by partly substituting Al in the wide band gap insulator Al2O3 by Pr cations. High quality PrAlO3 metal-insulator-metal capacitors were processed with a dielectric constant of 19, three times higher than in the case of Al2O3 reference cells. As a parasitic low dielectric constant interface layer between PrAlO3 and TiN limits the total performance gain, a systematic nondestructive synchrotron x-ray photoelectron spectroscopy study on the interface chemistry of PrxAl2-xO3 (x =0-2) dielectrics on TiN layers was applied to unveil its chemical origin. The interface layer results from the decreasing chemical reactivity of PrxAl2-xO3 dielectrics with increasing Pr content x to reduce native Ti oxide compounds present on unprotected TiN films. Accordingly, PrAlO3 based DRAM capacitors require strict control of the surface chemistry of the TiN electrode, a parameter furthermore of importance to engineer the band offsets of PrxAl2-xO3/TiN heterojunctions.

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

NASA Astrophysics Data System (ADS)

Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

2016-06-01

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

Optimization of Ferroelectric Ceramics by Design at the Microstructure Level

NASA Astrophysics Data System (ADS)

Jayachandran, K. P.; Guedes, J. M.; Rodrigues, H. C.

2010-05-01

Ferroelectric materials show remarkable physical behaviors that make them essential for many devices and have been extensively studied for their applications of nonvolatile random access memory (NvRAM) and high-speed random access memories. Although ferroelectric ceramics (polycrystals) present ease in manufacture and in compositional modifications and represent the widest application area of materials, computational and theoretical studies are sparse owing to many reasons including the large number of constituent atoms. Macroscopic properties of ferroelectric polycrystals are dominated by the inhomogeneities at the crystallographic domain/grain level. Orientation of grains/domains is critical to the electromechanical response of the single crystalline and polycrystalline materials. Polycrystalline materials have the potential of exhibiting better performance at a macroscopic scale by design of the domain/grain configuration at the domain-size scale. This suggests that piezoelectric properties can be optimized by a proper choice of the parameters which control the distribution of grain orientations. Nevertheless, this choice is complicated and it is impossible to analyze all possible combinations of the distribution parameters or the angles themselves. Hence we have implemented the stochastic optimization technique of simulated annealing combined with the homogenization for the optimization problem. The mathematical homogenization theory of a piezoelectric medium is implemented in the finite element method (FEM) by solving the coupled equilibrium electrical and mechanical fields. This implementation enables the study of the dependence of the macroscopic electromechanical properties of a typical crystalline and polycrystalline ferroelectric ceramic on the grain orientation.

Conductive bridging random access memory—materials, devices and applications

NASA Astrophysics Data System (ADS)

Kozicki, Michael N.; Barnaby, Hugh J.

2016-11-01

We present a review and primer on the subject of conductive bridging random access memory (CBRAM), a metal ion-based resistive switching technology, in the context of current research and the near-term requirements of the electronics industry in ultra-low energy devices and new computing paradigms. We include extensive discussions of the materials involved, the underlying physics and electrochemistry, the critical roles of ion transport and electrode reactions in conducting filament formation and device switching, and the electrical characteristics of the devices. Two general cation material systems are given—a fast ion chacogenide electrolyte and a lower ion mobility oxide ion conductor, and numerical examples are offered to enhance understanding of the operation of devices based on these. The effect of device conditioning on the activation energy for ion transport and consequent switching speed is discussed, as well as the mechanisms involved in the removal of the conducting bridge. The morphology of the filament and how this could be influenced by the solid electrolyte structure is described, and the electrical characteristics of filaments with atomic-scale constrictions are discussed. Consideration is also given to the thermal and mechanical environments within the devices. Finite element and compact modelling illustrations are given and aspects of CBRAM storage elements in memory circuits and arrays are included. Considerable emphasis is placed on the effects of ionizing radiation on CBRAM since this is important in various high reliability applications, and the potential uses of the devices in reconfigurable logic and neuromorphic systems is also discussed.

Programmable DMA controller

NASA Technical Reports Server (NTRS)

Hendry, David F. (Inventor)

1993-01-01

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

zorder-lib: Library API for Z-Order Memory Layout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nowell, Lucy; Edward W. Bethel

2015-04-01

This document describes the motivation for, elements of, and use of the zorder-lib, a library API that implements organization of and access to data in memory using either a-order (also known as "row-major" order) or z-order memory layouts. The primary motivation for this work is to improve the performance of many types of data- intensive codes by increasing both spatial and temporal locality of memory accesses. The basic idea is that the cost associated with accessing a datum is less when it is nearby in either space or time.

Efficient accesses of data structures using processing near memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jayasena, Nuwan S.; Zhang, Dong Ping; Diez, Paula Aguilera

Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory wheremore » the atomic queue is allocated.« less

PCM-Based Durable Write Cache for Fast Disk I/O

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Zhuo; Wang, Bin; Carpenter, Patrick

2012-01-01

Flash based solid-state devices (FSSDs) have been adopted within the memory hierarchy to improve the performance of hard disk drive (HDD) based storage system. However, with the fast development of storage-class memories, new storage technologies with better performance and higher write endurance than FSSDs are emerging, e.g., phase-change memory (PCM). Understanding how to leverage these state-of-the-art storage technologies for modern computing systems is important to solve challenging data intensive computing problems. In this paper, we propose to leverage PCM for a hybrid PCM-HDD storage architecture. We identify the limitations of traditional LRU caching algorithms for PCM-based caches, and develop amore » novel hash-based write caching scheme called HALO to improve random write performance of hard disks. To address the limited durability of PCM devices and solve the degraded spatial locality in traditional wear-leveling techniques, we further propose novel PCM management algorithms that provide effective wear-leveling while maximizing access parallelism. We have evaluated this PCM-based hybrid storage architecture using applications with a diverse set of I/O access patterns. Our experimental results demonstrate that the HALO caching scheme leads to an average reduction of 36.8% in execution time compared to the LRU caching scheme, and that the SFC wear leveling extends the lifetime of PCM by a factor of 21.6.« less

Working memory capacity and controlled serial memory search.

PubMed

Mızrak, Eda; Öztekin, Ilke

2016-08-01

The speed-accuracy trade-off (SAT) procedure was used to investigate the relationship between working memory capacity (WMC) and the dynamics of temporal order memory retrieval. High- and low-span participants (HSs, LSs) studied sequentially presented five-item lists, followed by two probes from the study list. Participants indicated the more recent probe. Overall, accuracy was higher for HSs compared to LSs. Crucially, in contrast to previous investigations that observed no impact of WMC on speed of access to item information in memory (e.g., Öztekin & McElree, 2010), recovery of temporal order memory was slower for LSs. While accessing an item's representation in memory can be direct, recovery of relational information such as temporal order information requires a more controlled serial memory search. Collectively, these data indicate that WMC effects are particularly prominent during high demands of cognitive control, such as serial search operations necessary to access temporal order information from memory. Copyright © 2016 Elsevier B.V. All rights reserved.

The potential of multi-port optical memories in digital computing

NASA Technical Reports Server (NTRS)

Alford, C. O.; Gaylord, T. K.

1975-01-01

A high-capacity memory with a relatively high data transfer rate and multi-port simultaneous access capability may serve as the basis for new computer architectures. The implementation of a multi-port optical memory is discussed. Several computer structures are presented that might profitably use such a memory. These structures include (1) a simultaneous record access system, (2) a simultaneously shared memory computer system, and (3) a parallel digital processing structure.

Saying what’s on your mind: Working memory effects on sentence production

PubMed Central

Slevc, L. Robert

2011-01-01

The role of working memory (WM) in sentence comprehension has received considerable interest, but little work has investigated how sentence production relies on memory mechanisms. These three experiments investigated speakers’ tendency to produce syntactic structures that allow for early production of material that is accessible in memory. In Experiment 1, speakers produced accessible information early less often when under a verbal WM load than when under no load. Experiment 2 found the same pattern for given-new ordering, i.e., when accessibility was manipulated by making information given. Experiment 3 addressed the possibility that these effects do not reflect WM mechanisms but rather increased task difficulty by relying on the distinction between verbal and spatial WM: Speakers’ tendency to produce sentences respecting given-new ordering was reduced more by a verbal than by a spatial WM load. These patterns show that accessibility effects do in fact reflect accessibility in verbal WM, and that representations in sentence production are vulnerable to interference from other information in memory. PMID:21767058

Working memory at work: how the updating process alters the nature of working memory transfer.

PubMed

Zhang, Yanmin; Verhaeghen, Paul; Cerella, John

2012-01-01

In three N-Back experiments, we investigated components of the process of working memory (WM) updating, more specifically access to items stored outside the focus of attention and transfer from the focus to the region of WM outside the focus. We used stimulus complexity as a marker. We found that when WM transfer occurred under full attention, it was slow and highly sensitive to stimulus complexity, much more so than WM access. When transfer occurred in conjunction with access, however, it was fast and no longer sensitive to stimulus complexity. Thus the updating context altered the nature of WM processing: The dual-task situation (transfer in conjunction with access) drove memory transfer into a more efficient mode, indifferent to stimulus complexity. In contrast, access times consistently increased with complexity, unaffected by the processing context. This study reinforces recent reports that retrieval is a (perhaps the) key component of working memory functioning. Copyright © 2011 Elsevier B.V. All rights reserved.

Working Memory at Work: How the Updating Process Alters the Nature of Working Memory Transfer

PubMed Central

Zhang, Yanmin; Verhaeghen, Paul; Cerella, John

2011-01-01

In three N-Back experiments, we investigated components of the process of working memory (WM) updating, more specifically access to items stored outside the focus of attention and transfer from the focus to the region of WM outside the focus. We used stimulus complexity as a marker. We found that when WM transfer occurred under full attention, it was slow and highly sensitive to stimulus complexity, much more so than WM access. When transfer occurred in conjunction with access, however, it was fast and no longer sensitive to stimulus complexity. Thus the updating context altered the nature of WM processing: The dual-task situation (transfer in conjunction with access) drove memory transfer into a more efficient mode, indifferent to stimulus complexity. In contrast, access times consistently increased with complexity, unaffected by the processing context. This study reinforces recent reports that retrieval is a (perhaps the) key component of working memory functioning. PMID:22105718

Children's Access to Public Library Services: Prince George's County Memorial Public Library, Maryland, 1980.

ERIC Educational Resources Information Center

Gerhardt, Lillian N.

1981-01-01

Evaluates the Prince George's County Memorial Public Library's approach to providing access to its services for children, and examines policies, regulations, practices, and conditions that affect such access. Six references are cited. (FM)

The Effect of Interference on Temporal Order Memory for Random and Fixed Sequences in Nondemented Older Adults

ERIC Educational Resources Information Center

Tolentino, Jerlyn C.; Pirogovsky, Eva; Luu, Trinh; Toner, Chelsea K.; Gilbert, Paul E.

2012-01-01

Two experiments tested the effect of temporal interference on order memory for fixed and random sequences in young adults and nondemented older adults. The results demonstrate that temporal order memory for fixed and random sequences is impaired in nondemented older adults, particularly when temporal interference is high. However, temporal order…

What versus where: Investigating how autobiographical memory retrieval differs when accessed with thematic versus spatial information.

PubMed

Sheldon, Signy; Chu, Sonja

2017-09-01

Autobiographical memory research has investigated how cueing distinct aspects of a past event can trigger different recollective experiences. This research has stimulated theories about how autobiographical knowledge is accessed and organized. Here, we test the idea that thematic information organizes multiple autobiographical events whereas spatial information organizes individual past episodes by investigating how retrieval guided by these two forms of information differs. We used a novel autobiographical fluency task in which participants accessed multiple memory exemplars to event theme and spatial (location) cues followed by a narrative description task in which they described the memories generated to these cues. Participants recalled significantly more memory exemplars to event theme than to spatial cues; however, spatial cues prompted faster access to past memories. Results from the narrative description task revealed that memories retrieved via event theme cues compared to spatial cues had a higher number of overall details, but those recalled to the spatial cues were recollected with a greater concentration on episodic details than those retrieved via event theme cues. These results provide evidence that thematic information organizes and integrates multiple memories whereas spatial information prompts the retrieval of specific episodic content from a past event.

The effect of interference on temporal order memory for random and fixed sequences in nondemented older adults.

PubMed

Tolentino, Jerlyn C; Pirogovsky, Eva; Luu, Trinh; Toner, Chelsea K; Gilbert, Paul E

2012-05-21

Two experiments tested the effect of temporal interference on order memory for fixed and random sequences in young adults and nondemented older adults. The results demonstrate that temporal order memory for fixed and random sequences is impaired in nondemented older adults, particularly when temporal interference is high. However, temporal order memory for fixed sequences is comparable between older adults and young adults when temporal interference is minimized. The results suggest that temporal order memory is less efficient and more susceptible to interference in older adults, possibly due to impaired temporal pattern separation.

Memory-efficient table look-up optimized algorithm for context-based adaptive variable length decoding in H.264/advanced video coding

NASA Astrophysics Data System (ADS)

Wang, Jianhua; Cheng, Lianglun; Wang, Tao; Peng, Xiaodong

2016-03-01

Table look-up operation plays a very important role during the decoding processing of context-based adaptive variable length decoding (CAVLD) in H.264/advanced video coding (AVC). However, frequent table look-up operation can result in big table memory access, and then lead to high table power consumption. Aiming to solve the problem of big table memory access of current methods, and then reduce high power consumption, a memory-efficient table look-up optimized algorithm is presented for CAVLD. The contribution of this paper lies that index search technology is introduced to reduce big memory access for table look-up, and then reduce high table power consumption. Specifically, in our schemes, we use index search technology to reduce memory access by reducing the searching and matching operations for code_word on the basis of taking advantage of the internal relationship among length of zero in code_prefix, value of code_suffix and code_lengh, thus saving the power consumption of table look-up. The experimental results show that our proposed table look-up algorithm based on index search can lower about 60% memory access consumption compared with table look-up by sequential search scheme, and then save much power consumption for CAVLD in H.264/AVC.

Microscopic origin of read current noise in TaO{sub x}-based resistive switching memory by ultra-low temperature measurement

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pan, Yue; Cai, Yimao, E-mail: caiyimao@pku.edu.cn; Liu, Yefan

TaO{sub x}-based resistive random access memory (RRAM) attracts considerable attention for the development of next generation nonvolatile memories. However, read current noise in RRAM is one of the critical concerns for storage application, and its microscopic origin is still under debate. In this work, the read current noise in TaO{sub x}-based RRAM was studied thoroughly. Based on a noise power spectral density analysis at room temperature and at ultra-low temperature of 25 K, discrete random telegraph noise (RTN) and continuous average current fluctuation (ACF) are identified and decoupled from the total read current noise in TaO{sub x} RRAM devices. A statisticalmore » comparison of noise amplitude further reveals that ACF depends strongly on the temperature, whereas RTN is independent of the temperature. Measurement results combined with conduction mechanism analysis show that RTN in TaO{sub x} RRAM devices arises from electron trapping/detrapping process in the hopping conduction, and ACF is originated from the thermal activation of conduction centers that form the percolation network. At last, a unified model in the framework of hopping conduction is proposed to explain the underlying mechanism of both RTN and ACF noise, which can provide meaningful guidelines for designing noise-immune RRAM devices.« less

Individual differences in memory span: the contribution of rehearsal, access to lexical memory, and output speed.

PubMed

Tehan, G; Lalor, D M

2000-11-01

Rehearsal speed has traditionally been seen to be the prime determinant of individual differences in memory span. Recent studies, in the main using young children as the subject population, have suggested other contributors to span performance, notably contributions from long-term memory and forgetting and retrieval processes occurring during recall. In the current research we explore individual differences in span with respect to measures of rehearsal, output time, and access to lexical memory. We replicate standard short-term phenomena; we show that the variables that influence children's span performance influence adult performance in the same way; and we show that lexical memory access appears to be a more potent source of individual differences in span than either rehearsal speed or output factors.

A New Random Walk for Replica Detection in WSNs.

PubMed

Aalsalem, Mohammed Y; Khan, Wazir Zada; Saad, N M; Hossain, Md Shohrab; Atiquzzaman, Mohammed; Khan, Muhammad Khurram

2016-01-01

Wireless Sensor Networks (WSNs) are vulnerable to Node Replication attacks or Clone attacks. Among all the existing clone detection protocols in WSNs, RAWL shows the most promising results by employing Simple Random Walk (SRW). More recently, RAND outperforms RAWL by incorporating Network Division with SRW. Both RAND and RAWL have used SRW for random selection of witness nodes which is problematic because of frequently revisiting the previously passed nodes that leads to longer delays, high expenditures of energy with lower probability that witness nodes intersect. To circumvent this problem, we propose to employ a new kind of constrained random walk, namely Single Stage Memory Random Walk and present a distributed technique called SSRWND (Single Stage Memory Random Walk with Network Division). In SSRWND, single stage memory random walk is combined with network division aiming to decrease the communication and memory costs while keeping the detection probability higher. Through intensive simulations it is verified that SSRWND guarantees higher witness node security with moderate communication and memory overheads. SSRWND is expedient for security oriented application fields of WSNs like military and medical.

A New Random Walk for Replica Detection in WSNs

PubMed Central

Aalsalem, Mohammed Y.; Saad, N. M.; Hossain, Md. Shohrab; Atiquzzaman, Mohammed; Khan, Muhammad Khurram

2016-01-01

Wireless Sensor Networks (WSNs) are vulnerable to Node Replication attacks or Clone attacks. Among all the existing clone detection protocols in WSNs, RAWL shows the most promising results by employing Simple Random Walk (SRW). More recently, RAND outperforms RAWL by incorporating Network Division with SRW. Both RAND and RAWL have used SRW for random selection of witness nodes which is problematic because of frequently revisiting the previously passed nodes that leads to longer delays, high expenditures of energy with lower probability that witness nodes intersect. To circumvent this problem, we propose to employ a new kind of constrained random walk, namely Single Stage Memory Random Walk and present a distributed technique called SSRWND (Single Stage Memory Random Walk with Network Division). In SSRWND, single stage memory random walk is combined with network division aiming to decrease the communication and memory costs while keeping the detection probability higher. Through intensive simulations it is verified that SSRWND guarantees higher witness node security with moderate communication and memory overheads. SSRWND is expedient for security oriented application fields of WSNs like military and medical. PMID:27409082

Adult Age Differences in Accessing and Retrieving Information from Long-Term Memory.

ERIC Educational Resources Information Center

Petros, Thomas V.; And Others

1983-01-01

Investigated adult age differences in accessing and retrieving information from long-term memory. Results showed that older adults (N=26) were slower than younger adults (N=35) at feature extraction, lexical access, and accessing category information. The age deficit was proportionally greater when retrieval of category information was required.…

Asymmetrical access to color and location in visual working memory.

PubMed

Rajsic, Jason; Wilson, Daryl E

2014-10-01

Models of visual working memory (VWM) have benefitted greatly from the use of the delayed-matching paradigm. However, in this task, the ability to recall a probed feature is confounded with the ability to maintain the proper binding between the feature that is to be reported and the feature (typically location) that is used to cue a particular item for report. Given that location is typically used as a cue-feature, we used the delayed-estimation paradigm to compare memory for location to memory for color, rotating which feature was used as a cue and which was reported. Our results revealed several novel findings: 1) the likelihood of reporting a probed object's feature was superior when reporting location with a color cue than when reporting color with a location cue; 2) location report errors were composed entirely of swap errors, with little to no random location reports; and 3) both colour and location reports greatly benefitted from the presence of nonprobed items at test. This last finding suggests that it is uncertainty over the bindings between locations and colors at memory retrieval that drive swap errors, not at encoding. We interpret our findings as consistent with a representational architecture that nests remembered object features within remembered locations.

Bubble memory module for spacecraft application

NASA Technical Reports Server (NTRS)

Hayes, P. J.; Looney, K. T.; Nichols, C. D.

1985-01-01

Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

Wide-Range Motion Estimation Architecture with Dual Search Windows for High Resolution Video Coding

NASA Astrophysics Data System (ADS)

Dung, Lan-Rong; Lin, Meng-Chun

This paper presents a memory-efficient motion estimation (ME) technique for high-resolution video compression. The main objective is to reduce the external memory access, especially for limited local memory resource. The reduction of memory access can successfully save the notorious power consumption. The key to reduce the memory accesses is based on center-biased algorithm in that the center-biased algorithm performs the motion vector (MV) searching with the minimum search data. While considering the data reusability, the proposed dual-search-windowing (DSW) approaches use the secondary windowing as an option per searching necessity. By doing so, the loading of search windows can be alleviated and hence reduce the required external memory bandwidth. The proposed techniques can save up to 81% of external memory bandwidth and require only 135 MBytes/sec, while the quality degradation is less than 0.2dB for 720p HDTV clips coded at 8Mbits/sec.

Gift from statistical learning: Visual statistical learning enhances memory for sequence elements and impairs memory for items that disrupt regularities.

PubMed

Otsuka, Sachio; Saiki, Jun

2016-02-01

Prior studies have shown that visual statistical learning (VSL) enhances familiarity (a type of memory) of sequences. How do statistical regularities influence the processing of each triplet element and inserted distractors that disrupt the regularity? Given that increased attention to triplets induced by VSL and inhibition of unattended triplets, we predicted that VSL would promote memory for each triplet constituent, and degrade memory for inserted stimuli. Across the first two experiments, we found that objects from structured sequences were more likely to be remembered than objects from random sequences, and that letters (Experiment 1) or objects (Experiment 2) inserted into structured sequences were less likely to be remembered than those inserted into random sequences. In the subsequent two experiments, we examined an alternative account for our results, whereby the difference in memory for inserted items between structured and random conditions is due to individuation of items within random sequences. Our findings replicated even when control letters (Experiment 3A) or objects (Experiment 3B) were presented before or after, rather than inserted into, random sequences. Our findings suggest that statistical learning enhances memory for each item in a regular set and impairs memory for items that disrupt the regularity. Copyright © 2015 Elsevier B.V. All rights reserved.

A Randomized Controlled Trial of the Group-Based Modified Story Memory Technique in TBI

DTIC Science & Technology

2017-10-01

AWARD NUMBER: W81XWH-16-1-0726 TITLE: A Randomized Controlled Trial of the Group -Based Modified Story Memory Technique in TBI PRINCIPAL...2017 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER A Randomized Controlled Trial of the Group -Based Modified Story Memory Technique in TBI 5b. GRANT...forthcoming, The current study addresses this need through a double blind, placebo- controlled , randomized clinical trial (RCT) of a group

Room-temperature antiferromagnetic memory resistor.

PubMed

Marti, X; Fina, I; Frontera, C; Liu, Jian; Wadley, P; He, Q; Paull, R J; Clarkson, J D; Kudrnovský, J; Turek, I; Kuneš, J; Yi, D; Chu, J-H; Nelson, C T; You, L; Arenholz, E; Salahuddin, S; Fontcuberta, J; Jungwirth, T; Ramesh, R

2014-04-01

The bistability of ordered spin states in ferromagnets provides the basis for magnetic memory functionality. The latest generation of magnetic random access memories rely on an efficient approach in which magnetic fields are replaced by electrical means for writing and reading the information in ferromagnets. This concept may eventually reduce the sensitivity of ferromagnets to magnetic field perturbations to being a weakness for data retention and the ferromagnetic stray fields to an obstacle for high-density memory integration. Here we report a room-temperature bistable antiferromagnetic (AFM) memory that produces negligible stray fields and is insensitive to strong magnetic fields. We use a resistor made of a FeRh AFM, which orders ferromagnetically roughly 100 K above room temperature, and therefore allows us to set different collective directions for the Fe moments by applied magnetic field. On cooling to room temperature, AFM order sets in with the direction of the AFM moments predetermined by the field and moment direction in the high-temperature ferromagnetic state. For electrical reading, we use an AFM analogue of the anisotropic magnetoresistance. Our microscopic theory modelling confirms that this archetypical spintronic effect, discovered more than 150 years ago in ferromagnets, is also present in AFMs. Our work demonstrates the feasibility of fabricating room-temperature spintronic memories with AFMs, which in turn expands the base of available magnetic materials for devices with properties that cannot be achieved with ferromagnets.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kan, Jimmy J.; Gottwald, Matthias; Fullerton, Eric E.

We describe low-temperature characterization of magnetic tunnel junctions (MTJs) patterned by reactive ion etching for spin-transfer-torque magnetic random access memory. Magnetotransport measurements of typical MTJs show increasing tunneling magnetoresistance (TMR) and larger coercive fields as temperature is decreased down to 10 K. However, MTJs selected from the high-resistance population of an MTJ array exhibit stable intermediate magnetic states when measured at low temperature and show TMR roll-off below 100 K. These non-ideal low-temperature behaviors arise from edge damage during the etch process and can have negative impacts on thermal stability of the MTJs.

jmzML, an open-source Java API for mzML, the PSI standard for MS data.

PubMed

Côté, Richard G; Reisinger, Florian; Martens, Lennart

2010-04-01

We here present jmzML, a Java API for the Proteomics Standards Initiative mzML data standard. Based on the Java Architecture for XML Binding and XPath-based XML indexer random-access XML parser, jmzML can handle arbitrarily large files in minimal memory, allowing easy and efficient processing of mzML files using the Java programming language. jmzML also automatically resolves internal XML references on-the-fly. The library (which includes a viewer) can be downloaded from http://jmzml.googlecode.com.

The Characteristics of Binary Spike-Time-Dependent Plasticity in HfO2-Based RRAM and Applications for Pattern Recognition

NASA Astrophysics Data System (ADS)

Zhou, Zheng; Liu, Chen; Shen, Wensheng; Dong, Zhen; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

2017-04-01

A binary spike-time-dependent plasticity (STDP) protocol based on one resistive-switching random access memory (RRAM) device was proposed and experimentally demonstrated in the fabricated RRAM array. Based on the STDP protocol, a novel unsupervised online pattern recognition system including RRAM synapses and CMOS neurons is developed. Our simulations show that the system can efficiently compete the handwritten digits recognition task, which indicates the feasibility of using the RRAM-based binary STDP protocol in neuromorphic computing systems to obtain good performance.

Polymorphous computing fabric

DOEpatents

Wolinski, Christophe Czeslaw [Los Alamos, NM; Gokhale, Maya B [Los Alamos, NM; McCabe, Kevin Peter [Los Alamos, NM

2011-01-18

Fabric-based computing systems and methods are disclosed. A fabric-based computing system can include a polymorphous computing fabric that can be customized on a per application basis and a host processor in communication with said polymorphous computing fabric. The polymorphous computing fabric includes a cellular architecture that can be highly parameterized to enable a customized synthesis of fabric instances for a variety of enhanced application performances thereof. A global memory concept can also be included that provides the host processor random access to all variables and instructions associated with the polymorphous computing fabric.

Multiferroic YCrO3 thin films grown on glass substrate: Resistive switching characteristics

NASA Astrophysics Data System (ADS)

Seo, Jeongdae; Ahn, Yoonho; Son, Jong Yeog

2016-01-01

Polycrystalline YCrO3 thin films were deposited on (111) Pt/Ta/glass substrates by pulsed laser deposition. The YCrO3 thin films exhibited good ferroelectric properties with remnant polarization of about 5 µC/cm2. Large leakage current was observed by I- V curve and ferroelectric hysteresis loop. The YCrO3 resistive random access memory (RRAM) capacitor showed unipolar switching behaviors with SET and RESET voltages higher than those of general NiO RRAM capacitors. [Figure not available: see fulltext.

Single Event Upset Rate Estimates for a 16-K CMOS (Complementary Metal Oxide Semiconductor) SRAM (Static Random Access Memory).

DTIC Science & Technology

1986-09-30

4 . ~**..ft.. ft . - - - ft SI TABLES 9 I. SA32~40 Single Event Upset Test, 1140-MeV Krypton, 9/l8/8~4. . .. .. .. .. .. .16 II. CRUP Simulation...cosmic ray interaction analysis described in the remainder of this report were calculated using the CRUP computer code 3 modified for funneling. The... CRUP code requires, as inputs, the size of a depletion region specified as a retangular parallel piped with dimensions a 9 b S c, the effective funnel

LLB simulation of the temperature dependent switching critical curve of a Stoner-Wohlfarth macrospin in the presence of a polarized current

NASA Astrophysics Data System (ADS)

Oniciuc, E.; Stoleriu, L.; Stancu, A.

2014-02-01

An extension of Landau-Lifshitz-Bloch (LLB) equation is used to describe the behavior of single-domain particles under the influence of magnetic fields and polarized currents at elevated temperatures. We prove that using such a model, which takes into account the longitudinal magnetization relaxation, together with the consideration of the quartic crystalline anisotropy term, a number of recent experimental results can be explained concerning the free layer characteristic critical curves of spin valves commonly used in spin electronics. These results are of paramount importance for heat assisted magnetic recording (HAMR) processes in hard-drives or in new memory systems like the spin-transfer-torque magnetic random access memory (HA-STTMRAM) with the aim of increasing data density writing while avoiding superparamagnetic limit.

Accessibility Limits Recall from Visual Working Memory

ERIC Educational Resources Information Center

Rajsic, Jason; Swan, Garrett; Wilson, Daryl E.; Pratt, Jay

2017-01-01

In this article, we demonstrate limitations of accessibility of information in visual working memory (VWM). Recently, cued-recall has been used to estimate the fidelity of information in VWM, where the feature of a cued object is reproduced from memory (Bays, Catalao, & Husain, 2009; Wilken & Ma, 2004; Zhang & Luck, 2008). Response…

Organic-Inorganic Hybrid Halide Perovskites for Memories, Transistors, and Artificial Synapses.

PubMed

Choi, Jaeho; Han, Ji Su; Hong, Kootak; Kim, Soo Young; Jang, Ho Won

2018-05-30

Fascinating characteristics of halide perovskites (HPs), which cannot be seen in conventional semiconductors and metal oxides, have boosted the application of HPs in electronic devices beyond optoelectronics such as solar cells, photodetectors, and light-emitting diodes. Here, recent advances in HP-based memory and logic devices such as resistive-switching memories (i.e., resistive random access memory (RRAM) or memristors), transistors, and artificial synapses are reviewed, focusing on inherently exotic properties of HPs: i) tunable bandgap, ii) facile majority carrier control, iii) fast ion migration, and iv) superflexibility. Various fabrication techniques of HP thin films from solution-based methods to vacuum processes are introduced. Up-to-date work in the field, emphasizing the compositional flexibility of HPs, suggest that HPs are promising candidates for next-generation electronic devices. Taking advantages of their unique electrical properties, low-cost and low-temperature synthesis, and compositional and mechanical flexibility, HPs have enormous potential to provide a new platform for future electronic devices and explosively intensive studies will pave the way in finding new HP materials beyond conventional silicon-based semiconductors to keep up with "More-than-Moore" times. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Analysis of SEL on Commercial SRAM Memories and Mixed-Field Characterization of a Latchup Detection Circuit for LEO Space Applications

NASA Astrophysics Data System (ADS)

Secondo, R.; Alía, R. Garcia; Peronnard, P.; Brugger, M.; Masi, A.; Danzeca, S.; Merlenghi, A.; Vaillé, J.-R.; Dusseau, L.

2017-08-01

A single event latchup (SEL) experiment based on commercial static random access memory (SRAM) memories has recently been proposed in the framework of the European Organization for Nuclear Research (CERN) Latchup Experiment and Student Satellite nanosatellite low Earth orbit (LEO) space mission. SEL characterization of three commercial SRAM memories has been carried out at the Paul Scherrer Institut (PSI) facility, using monoenergetic focused proton beams and different acquisition setups. The best target candidate was selected and a circuit for SEL detection has been proposed and tested at CERN, in the CERN High Energy AcceleRator Mixed-field facility (CHARM). Experimental results were carried out at test locations representative of the LEO environment, thus providing a full characterization of the SRAM cross sections, together with the analysis of the single-event effect and total ionizing dose of the latchup detection circuit in relation to the particle spectra expected during mission. The setups used for SEL monitoring are described, and details of the proposed circuit components and topology are presented. Experimental results obtained both at PSI and at CHARM facilities are discussed.

Review of radiation effects on ReRAM devices and technology

NASA Astrophysics Data System (ADS)

Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

2017-08-01

A review of the ionizing radiation effects on resistive random access memory (ReRAM) technology and devices is presented in this article. The review focuses on vertical devices exhibiting bipolar resistance switching, devices that have already exhibited interesting properties and characteristics for memory applications and, in particular, for non-volatile memory applications. Non-volatile memories are important devices for any type of electronic and embedded system, as they are for space applications. In such applications, specific environmental issues related to the existence of cosmic rays and Van Allen radiation belts around the Earth contribute to specific failure mechanisms related to the energy deposition induced by such ionizing radiation. Such effects are important in non-volatile memory as the current leading technology, i.e. flash-based technology, is sensitive to the total ionizing dose (TID) and single-event effects. New technologies such as ReRAM, if competing with or complementing the existing non-volatile area of memories from the point of view of performance, also have to exhibit great reliability for use in radiation environments such as space. This has driven research on the radiation effects of such ReRAM technology, on both the conductive-bridge RAM as well as the valence-change memories, or OxRAM variants of the technology. Initial characterizations of ReRAM technology showed a high degree of resilience to TID, developing researchers’ interest in characterizing such resilience as well as investigating the cause of such behavior. The state of the art of such research is reviewed in this article.

Non-tables look-up search algorithm for efficient H.264/AVC context-based adaptive variable length coding decoding

NASA Astrophysics Data System (ADS)

Han, Yishi; Luo, Zhixiao; Wang, Jianhua; Min, Zhixuan; Qin, Xinyu; Sun, Yunlong

2014-09-01

In general, context-based adaptive variable length coding (CAVLC) decoding in H.264/AVC standard requires frequent access to the unstructured variable length coding tables (VLCTs) and significant memory accesses are consumed. Heavy memory accesses will cause high power consumption and time delays, which are serious problems for applications in portable multimedia devices. We propose a method for high-efficiency CAVLC decoding by using a program instead of all the VLCTs. The decoded codeword from VLCTs can be obtained without any table look-up and memory access. The experimental results show that the proposed algorithm achieves 100% memory access saving and 40% decoding time saving without degrading video quality. Additionally, the proposed algorithm shows a better performance compared with conventional CAVLC decoding, such as table look-up by sequential search, table look-up by binary search, Moon's method, and Kim's method.

Petabyte mass memory system using the Newell Opticel(TM)

NASA Technical Reports Server (NTRS)

Newell, Chester W.

1994-01-01

A random access system is proposed for digital storage and retrieval of up to a Petabyte of user data. The system is comprised of stacked memory modules using laser heads writing to an optical medium, in a new shirt-pocket-sized optical storage device called the Opticel. The Opticel described is a completely sealed 'black box' in which an optical medium is accelerated and driven at very high rates to accommodate the desired transfer rates, yet in such a manner that wear is virtually eliminated. It essentially emulates a disk, but with storage area up to several orders of magnitude higher. Access time to the first bit can range from a few milliseconds to a fraction of a second, with time to the last bit within a fraction of a second to a few seconds. The actual times are dependent on the capacity of each Opticel, which ranges from 72 Gigabytes to 1.25 Terabytes. Data transfer rate is limited strictly by the head and electronics, and is 15 Megabits per second in the first version. Independent parallel write/read access to each Opticel is provided using dedicated drives and heads. A Petabyte based on the present Opticel and drive design would occupy 120 cubic feet on a footprint of 45 square feet; with further development, it could occupy as little as 9 cubic feet.

The two faces of selective memory retrieval: recall specificity of the detrimental but not the beneficial effect.

PubMed

Bäuml, Karl-Heinz T; Dobler, Ina M

2015-01-01

Depending on the degree to which the original study context is accessible, selective memory retrieval can be detrimental or beneficial for the recall of other memories (Bäuml & Samenieh, 2012). Prior work has shown that the detrimental effect of memory retrieval is typically recall specific and does not arise after restudy trials, whereas recall specificity of the beneficial effect has not been examined to date. Addressing the issue, we compared in 2 experiments the effects of retrieval and restudy on recall of other items, when access to the study context was (largely) maintained and when access to the study context was impaired (in Experiment 1 by using the listwise directed-forgetting task, in Experiment 2 by using a prolonged retention interval). In both experiments, selective retrieval but not restudy induced forgetting of other items when context access was maintained, which replicates prior work. In contrast, when context access was impaired, both selective retrieval and restudy induced beneficial effects on other memories. These findings suggest that the detrimental but not the beneficial effect of selective memory retrieval is recall specific. The results are consistent with a recent 2-factor account of selective memory retrieval that attributes the detrimental effect to inhibition or blocking but the beneficial effect to context reactivation processes. PsycINFO Database Record (c) 2015 APA, all rights reserved.

Low latency memory access and synchronization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.« less

Low latency memory access and synchronization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.« less

Limited capacity of working memory in unihemispheric random walks implies conceivable slow dispersal.

PubMed

Wei, Kun; Zhong, Suchuan

2017-08-01

Phenomenologically inspired by dolphins' unihemispheric sleep, we introduce a minimal model for random walks with physiological memory. The physiological memory consists of long-term memory which includes unconscious implicit memory and conscious explicit memory, and working memory which serves as a multi-component system for integrating, manipulating and managing short-term storage. The model assumes that the sleeping state allows retrievals of episodic objects merely from the episodic buffer where these memory objects are invoked corresponding to the ambient objects and are thus object-oriented, together with intermittent but increasing use of implicit memory in which decisions are unconsciously picked up from historical time series. The process of memory decay and forgetting is constructed in the episodic buffer. The walker's risk attitude, as a product of physiological heuristics according to the performance of objected-oriented decisions, is imposed on implicit memory. The analytical results of unihemispheric random walks with the mixture of object-oriented and time-oriented memory, as well as the long-time behavior which tends to the use of implicit memory, are provided, indicating the common sense that a conservative risk attitude is inclinable to slow movement.

Solution-Processed Carbon Nanotube True Random Number Generator.

PubMed

Gaviria Rojas, William A; McMorrow, Julian J; Geier, Michael L; Tang, Qianying; Kim, Chris H; Marks, Tobin J; Hersam, Mark C

2017-08-09

With the growing adoption of interconnected electronic devices in consumer and industrial applications, there is an increasing demand for robust security protocols when transmitting and receiving sensitive data. Toward this end, hardware true random number generators (TRNGs), commonly used to create encryption keys, offer significant advantages over software pseudorandom number generators. However, the vast network of devices and sensors envisioned for the "Internet of Things" will require small, low-cost, and mechanically flexible TRNGs with low computational complexity. These rigorous constraints position solution-processed semiconducting single-walled carbon nanotubes (SWCNTs) as leading candidates for next-generation security devices. Here, we demonstrate the first TRNG using static random access memory (SRAM) cells based on solution-processed SWCNTs that digitize thermal noise to generate random bits. This bit generation strategy can be readily implemented in hardware with minimal transistor and computational overhead, resulting in an output stream that passes standardized statistical tests for randomness. By using solution-processed semiconducting SWCNTs in a low-power, complementary architecture to achieve TRNG, we demonstrate a promising approach for improving the security of printable and flexible electronics.

The Dynamics of Access to Groups in Working Memory

ERIC Educational Resources Information Center

Farrell, Simon; Lelievre, Anna

2012-01-01

The finding that participants leave a pause between groups when attempting serial recall of temporally grouped lists has been taken to indicate access to a hierarchical representation of the list in working memory. An alternative explanation is that the dynamics of serial recall solely reflect output (rather than memorial) processes, with the…

Photon-counting intensified random-access charge injection device

NASA Astrophysics Data System (ADS)

Norton, Timothy J.; Morrissey, Patrick F.; Haas, Patrick; Payne, Leslie J.; Carbone, Joseph; Kimble, Randy A.

1999-11-01

At NASA GSFC we are developing a high resolution solar-blind photon counting detector system for UV space based astronomy. The detector comprises a high gain MCP intensifier fiber- optically coupled to a charge injection device (CID). The detector system utilizes an FPGA based centroiding system to locate the center of photon events from the intensifier to high accuracy. The photon event addresses are passed via a PCI interface with a GPS derived time stamp inserted per frame to an integrating memory. Here we present imaging performance data which show resolution of MCP tube pore structure at an MCP pore diameter of 8 micrometer. This data validates the ICID concept for intensified photon counting readout. We also discuss correction techniques used in the removal of fixed pattern noise effects inherent in the centroiding algorithms used and present data which shows the local dynamic range of the device. Progress towards development of a true random access CID (RACID 810) is also discussed and astronomical data taken with the ICID detector system demonstrating the photon event time-tagging mode of the system is also presented.

Performance of FORTRAN floating-point operations on the Flex/32 multicomputer

NASA Technical Reports Server (NTRS)

Crockett, Thomas W.

1987-01-01

A series of experiments has been run to examine the floating-point performance of FORTRAN programs on the Flex/32 (Trademark) computer. The experiments are described, and the timing results are presented. The time required to execute a floating-point operation is found to vary considerbaly depending on a number of factors. One factor of particular interest from an algorithm design standpoint is the difference in speed between common memory accesses and local memory accesses. Common memory accesses were found to be slower, and guidelines are given for determinig when it may be cost effective to copy data from common to local memory.

Fixed-Rate Compressed Floating-Point Arrays.

PubMed

Lindstrom, Peter

2014-12-01

Current compression schemes for floating-point data commonly take fixed-precision values and compress them to a variable-length bit stream, complicating memory management and random access. We present a fixed-rate, near-lossless compression scheme that maps small blocks of 4(d) values in d dimensions to a fixed, user-specified number of bits per block, thereby allowing read and write random access to compressed floating-point data at block granularity. Our approach is inspired by fixed-rate texture compression methods widely adopted in graphics hardware, but has been tailored to the high dynamic range and precision demands of scientific applications. Our compressor is based on a new, lifted, orthogonal block transform and embedded coding, allowing each per-block bit stream to be truncated at any point if desired, thus facilitating bit rate selection using a single compression scheme. To avoid compression or decompression upon every data access, we employ a software write-back cache of uncompressed blocks. Our compressor has been designed with computational simplicity and speed in mind to allow for the possibility of a hardware implementation, and uses only a small number of fixed-point arithmetic operations per compressed value. We demonstrate the viability and benefits of lossy compression in several applications, including visualization, quantitative data analysis, and numerical simulation.

Effect of random phase mask on input plane in photorefractive authentic memory with two-wave encryption method

NASA Astrophysics Data System (ADS)

Mita, Akifumi; Okamoto, Atsushi; Funakoshi, Hisatoshi

2004-06-01

We have proposed an all-optical authentic memory with the two-wave encryption method. In the recording process, the image data are encrypted to a white noise by the random phase masks added on the input beam with the image data and the reference beam. Only reading beam with the phase-conjugated distribution of the reference beam can decrypt the encrypted data. If the encrypted data are read out with an incorrect phase distribution, the output data are transformed into a white noise. Moreover, during read out, reconstructions of the encrypted data interfere destructively resulting in zero intensity. Therefore our memory has a merit that we can detect unlawful accesses easily by measuring the output beam intensity. In our encryption method, the random phase mask on the input plane plays important roles in transforming the input image into a white noise and prohibiting to decrypt a white noise to the input image by the blind deconvolution method. Without this mask, when unauthorized users observe the output beam by using CCD in the readout with the plane wave, the completely same intensity distribution as that of Fourier transform of the input image is obtained. Therefore the encrypted image will be decrypted easily by using the blind deconvolution method. However in using this mask, even if unauthorized users observe the output beam using the same method, the encrypted image cannot be decrypted because the observed intensity distribution is dispersed at random by this mask. Thus it can be said the robustness is increased by this mask. In this report, we compare two correlation coefficients, which represents the degree of a white noise of the output image, between the output image and the input image in using this mask or not. We show that the robustness of this encryption method is increased as the correlation coefficient is improved from 0.3 to 0.1 by using this mask.

Phase Change Characteristics of InxSb40-xTe60 Chalcogenide Alloy for Phase Change Random Access Memory

NASA Astrophysics Data System (ADS)

Yun, Jae-Jin; Lee, Won-Jong

2011-07-01

The InxSb40-xTe60 alloy was selected as a new alternative phase change material for Ge2Sb2Te5 (GST) for phase change random access memory (PRAM). The crystal structure of InxSb40-xTe60 was an α(Sb2Te3) rhombohedral (a=b=c, α=β=γ≠90°) single phase with identical lattice parameters in a wide composition range of In (0-28 at. %). The crystallization temperature and melting point of InxSb40-xTe60 were in the ranges of 149-219 °C and 608-614 °C, respectively, and similar to those of GST. The electric properties of InxSb40-xTe60 with a wide composition range of In contents showed the typical PRAM properties such as current-voltage (I-V), resistance-voltage (R-V), and switching behavior. The reset current of InxSb40-xTe60 decreased with increasing In content and the low power consumption and good retention can be realized by controlling In content. The ratio of the cell resistance and sheet resistance of amorphous InxSb40-xTe60 to those crystalline InxSb40-xTe60 were almost the same as or larger than those of GST. The cycling endurance test of InxSb40-xTe60 with a wide range of In contents showed the comparable results to GST. InxSb40-xTe60 was concluded to be a very promising phase change material for PRAM.

Atomic Layer Deposited Oxide-Based Nanocomposite Structures with Embedded CoPtx Nanocrystals for Resistive Random Access Memory Applications.

PubMed

Wang, Lai-Guo; Cao, Zheng-Yi; Qian, Xu; Zhu, Lin; Cui, Da-Peng; Li, Ai-Dong; Wu, Di

2017-02-22

Al 2 O 3 - or HfO 2 -based nanocomposite structures with embedded CoPt x nanocrystals (NCs) on TiN-coated Si substrates have been prepared by combination of thermal atomic layer deposition (ALD) and plasma-enhanced ALD for resistive random access memory (RRAM) applications. The impact of CoPt x NCs and their average size/density on the resistive switching properties has been explored. Compared to the control sample without CoPt x NCs, ALD-derived Pt/oxide/100 cycle-CoPt x NCs/TiN/SiO 2 /Si exhibits a typical bipolar, reliable, and reproducible resistive switching behavior, such as sharp distribution of RRAM parameters, smaller set/reset voltages, stable resistance ratio (≥10 2 ) of OFF/ON states, better switching endurance up to 10 4 cycles, and longer data retention over 10 5 s. The possible resistive switching mechanism based on nanocomposite structures of oxide/CoPt x NCs has been proposed. The dominant conduction mechanisms in low- and high-resistance states of oxide-based device units with embedded CoPt x NCs are Ohmic behavior and space-charge-limited current, respectively. The insertion of CoPt x NCs can effectively improve the formation of conducting filaments due to the CoPt x NC-enhanced electric field intensity. Besides excellent resistive switching performances, the nanocomposite structures also simultaneously present ferromagnetic property. This work provides a flexible pathway by combining PEALD and TALD compatible with state-of-the-art Si-based technology for multifunctional electronic devices applications containing RRAM.

Improving the effectiveness of an interruption lag by inducing a memory-based strategy.

PubMed

Morgan, Phillip L; Patrick, John; Tiley, Leyanne

2013-01-01

The memory for goals model (Altmann & Trafton, 2002) posits the importance of a short delay (the 'interruption lag') before an interrupting task to encode suspended goals for retrieval post-interruption. Two experiments used the theory of soft constraints (Gray, Simms, Fu & Schoelles, 2006) to investigate whether the efficacy of an interruption lag could be improved by increasing goal-state access cost to induce a more memory-based encoding strategy. Both experiments used a copying task with three access cost conditions (Low, Medium, and High) and a 5-s interruption lag with a no lag control condition. Experiment 1 found that the participants in the High access cost condition resumed more interrupted trials and executed more actions correctly from memory when coupled with an interruption lag. Experiment 2 used a prospective memory test post-interruption and an eyetracker recorded gaze activity during the interruption lag. The participants in the High access cost condition with an interruption lag were best at encoding target information during the interruption lag, evidenced by higher scores on the prospective memory measure and more gaze activity on the goal-state during the interruption lag. Theoretical and practical issues regarding the use of goal-state access cost and an interruption lag are discussed. Copyright © 2012. Published by Elsevier B.V.

Controllable Organic Resistive Switching Achieved by One-Step Integration of Cone-Shaped Contact.

PubMed

Ling, Haifeng; Yi, Mingdong; Nagai, Masaru; Xie, Linghai; Wang, Laiyuan; Hu, Bo; Huang, Wei

2017-09-01

Conductive filaments (CFs)-based resistive random access memory possesses the ability of scaling down to sub-nanoscale with high-density integration architecture, making it the most promising nanoelectronic technology for reclaiming Moore's law. Compared with the extensive study in inorganic switching medium, the scientific challenge now is to understand the growth kinetics of nanoscale CFs in organic polymers, aiming to achieve controllable switching characteristics toward flexible and reliable nonvolatile organic memory. Here, this paper systematically investigates the resistive switching (RS) behaviors based on a widely adopted vertical architecture of Al/organic/indium-tin-oxide (ITO), with poly(9-vinylcarbazole) as the case study. A nanoscale Al filament with a dynamic-gap zone (DGZ) is directly observed using in situ scanning transmission electron microscopy (STEM) , which demonstrates that the RS behaviors are related to the random formation of spliced filaments consisting of Al and oxygen vacancy dual conductive channels growing through carbazole groups. The randomicity of the filament formation can be depressed by introducing a cone-shaped contact via a one-step integration method. The conical electrode can effectively shorten the DGZ and enhance the localized electric field, thus reducing the switching voltage and improving the RS uniformity. This study provides a deeper insight of the multiple filamentary mechanisms for organic RS effect. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Programmable Direct-Memory-Access Controller

NASA Technical Reports Server (NTRS)

Hendry, David F.

1990-01-01

Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines

NASA Technical Reports Server (NTRS)

Biswas, Rupak; Gaeke, Brian R.; Husbands, Parry; Li, Xiaoye S.; Oliker, Leonid; Yelick, Katherine A.; Biegel, Bryan (Technical Monitor)

2002-01-01

The increasing gap between processor and memory performance has lead to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory access patterns, their basic control structures, and the ratio of computation to memory operation.

Correlative transmission electron microscopy and electrical properties study of switchable phase-change random access memory line cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oosthoek, J. L. M.; Kooi, B. J., E-mail: B.J.Kooi@rug.nl; Voogt, F. C.

2015-02-14

Phase-change memory line cells, where the active material has a thickness of 15 nm, were prepared for transmission electron microscopy (TEM) observation such that they still could be switched and characterized electrically after the preparation. The result of these observations in comparison with detailed electrical characterization showed (i) normal behavior for relatively long amorphous marks, resulting in a hyperbolic dependence between SET resistance and SET current, indicating a switching mechanism based on initially long and thin nanoscale crystalline filaments which thicken gradually, and (ii) anomalous behavior, which holds for relatively short amorphous marks, where initially directly a massive crystalline filament ismore » formed that consumes most of the width of the amorphous mark only leaving minor residual amorphous regions at its edges. The present results demonstrate that even in (purposely) thick TEM samples, the TEM sample preparation hampers the probability to observe normal behavior and it can be debated whether it is possible to produce electrically switchable TEM specimen in which the memory cells behave the same as in their original bulk embedded state.« less

Correlative transmission electron microscopy and electrical properties study of switchable phase-change random access memory line cells

NASA Astrophysics Data System (ADS)

Oosthoek, J. L. M.; Voogt, F. C.; Attenborough, K.; Verheijen, M. A.; Hurkx, G. A. M.; Gravesteijn, D. J.; Kooi, B. J.

2015-02-01

Phase-change memory line cells, where the active material has a thickness of 15 nm, were prepared for transmission electron microscopy (TEM) observation such that they still could be switched and characterized electrically after the preparation. The result of these observations in comparison with detailed electrical characterization showed (i) normal behavior for relatively long amorphous marks, resulting in a hyperbolic dependence between SET resistance and SET current, indicating a switching mechanism based on initially long and thin nanoscale crystalline filaments which thicken gradually, and (ii) anomalous behavior, which holds for relatively short amorphous marks, where initially directly a massive crystalline filament is formed that consumes most of the width of the amorphous mark only leaving minor residual amorphous regions at its edges. The present results demonstrate that even in (purposely) thick TEM samples, the TEM sample preparation hampers the probability to observe normal behavior and it can be debated whether it is possible to produce electrically switchable TEM specimen in which the memory cells behave the same as in their original bulk embedded state.

Temperature induced complementary switching in titanium oxide resistive random access memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Panda, D., E-mail: dpanda@nist.edu; Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan; Simanjuntak, F. M.

2016-07-15

On the way towards high memory density and computer performance, a considerable development in energy efficiency represents the foremost aspiration in future information technology. Complementary resistive switch consists of two antiserial resistive switching memory (RRAM) elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption. Here we present a titanium oxide based complementary RRAM (CRRAM) device with Pt top and TiN bottom electrode. A subsequent post metal annealing at 400°C induces CRRAM. Forming voltage of 4.3 V is required for this device tomore » initiate switching process. The same device also exhibiting bipolar switching at lower compliance current, Ic <50 μA. The CRRAM device have high reliabilities. Formation of intermediate titanium oxi-nitride layer is confirmed from the cross-sectional HRTEM analysis. The origin of complementary switching mechanism have been discussed with AES, HRTEM analysis and schematic diagram. This paper provides valuable data along with analysis on the origin of CRRAM for the application in nanoscale devices.« less

A Review on Resistive Switching in High-k Dielectrics: A Nanoscale Point of View Using Conductive Atomic Force Microscope

PubMed Central

Lanza, Mario

2014-01-01

Metal-Insulator-Metal (MIM) structures have raised as the most promising configuration for next generation information storage, leading to great performance and fabrication-friendly Resistive Random Access Memories (RRAM). In these cells, the memory concept is no more based on the charge storage, but on tuning the electrical resistance of the insulating layer by applying electrical stresses to reach a high resistive state (HRS or “0”) and a low resistive state (LRS or “1”), which makes the memory point. Some high-k dielectrics show this unusual property and in the last years high-k based RRAM have been extensively analyzed, especially at the device level. However, as resistance switching (in the most promising cells) is a local phenomenon that takes place in areas of ~100 nm2, the use of characterization tools with high lateral spatial resolution is necessary. In this paper the status of resistive switching in high-k materials is reviewed from a nanoscale point of view by means of conductive atomic force microscope analyses. PMID:28788561

Implementation of real-time digital signal processing systems

NASA Technical Reports Server (NTRS)

Narasimha, M.; Peterson, A.; Narayan, S.

1978-01-01

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct implementation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

Tightening the entropic uncertainty bound in the presence of quantum memory

NASA Astrophysics Data System (ADS)

Adabi, F.; Salimi, S.; Haseli, S.

2016-06-01

The uncertainty principle is a fundamental principle in quantum physics. It implies that the measurement outcomes of two incompatible observables cannot be predicted simultaneously. In quantum information theory, this principle can be expressed in terms of entropic measures. M. Berta et al. [Nat. Phys. 6, 659 (2010), 10.1038/nphys1734] have indicated that uncertainty bound can be altered by considering a particle as a quantum memory correlating with the primary particle. In this article, we obtain a lower bound for entropic uncertainty in the presence of a quantum memory by adding an additional term depending on the Holevo quantity and mutual information. We conclude that our lower bound will be tightened with respect to that of Berta et al. when the accessible information about measurements outcomes is less than the mutual information about the joint state. Some examples have been investigated for which our lower bound is tighter than Berta et al.'s lower bound. Using our lower bound, a lower bound for the entanglement of formation of bipartite quantum states has been obtained, as well as an upper bound for the regularized distillable common randomness.

Resistive switching characteristics of HfO2-based memory devices on flexible plastics.

PubMed

Han, Yong; Cho, Kyoungah; Park, Sukhyung; Kim, Sangsig

2014-11-01

In this study, we examine the characteristics of HfO2-based resistive switching random access memory (ReRAM) devices on flexible plastics. The Pt/HfO2/Au ReRAM devices exhibit the unipolar resistive switching behaviors caused by the conducting filaments. From the Auger depth profiles of the HfO2 thin film, it is confirmed that the relatively lower oxygen content in the interface of the bottom electrode is responsible for the resistive switching by oxygen vacancies. And the unipolar resistive switching behaviors are analyzed from the C-V characteristics in which negative and positive capacitances are measured in the low-resistance state and the high-resistance state, respectively. The devices have a high on/off ratio of 10(4) and the excellent retention properties even after a continuous bending test of two thousand cycles. The correlation between the device size and the memory characteristics is investigated as well. A relatively smaller-sized device having a higher on/off ratio operates at a higher voltage than a relatively larger-sized device.

Resistive switching characteristics of solution-processed Al-Zn-Sn-O films annealed by microwave irradiation

NASA Astrophysics Data System (ADS)

Kim, Tae-Wan; Baek, Il-Jin; Cho, Won-Ju

2018-02-01

In this study, we employed microwave irradiation (MWI) at low temperature in the fabrication of solution-processed AlZnSnO (AZTO) resistive random access memory (ReRAM) devices with a structure of Ti/AZTO/Pt and compared the memory characteristics with the conventional thermal annealing (CTA) process. Typical bipolar resistance switching (BRS) behavior was observed in AZTO ReRAM devices treated with as-deposited (as-dep), CTA and MWI. In the low resistance state, the Ohmic conduction mechanism describes the dominant conduction of these devices. On the other hand, the trap-controlled space charge limited conduction (SCLC) mechanism predominates in the high resistance state. The AZTO ReRAM devices processed with MWI showed larger memory windows, uniform distribution of resistance state and operating voltage, stable DC durability (>103 cycles) and stable retention characteristics (>104 s). In addition, the AZTO ReRAM devices treated with MWI exhibited multistage storage characteristics by modulating the amplitude of the reset bias, and eight distinct resistance levels were obtained with stable retention capability.

Resistive Switching of Ta2O5-Based Self-Rectifying Vertical-Type Resistive Switching Memory

NASA Astrophysics Data System (ADS)

Ryu, Sungyeon; Kim, Seong Keun; Choi, Byung Joon

2018-01-01

To efficiently increase the capacity of resistive switching random-access memory (RRAM) while maintaining the same area, a vertical structure similar to a vertical NAND flash structure is needed. In addition, the sneak-path current through the half-selected neighboring memory cell should be mitigated by integrating a selector device with each RRAM cell. In this study, an integrated vertical-type RRAM cell and selector device was fabricated and characterized. Ta2O5 as the switching layer and TaOxNy as the selector layer were used to preliminarily study the feasibility of such an integrated device. To make the side contact of the bottom electrode with active layers, a thick Al2O3 insulating layer was placed between the Pt bottom electrode and the Ta2O5/TaOxNy stacks. Resistive switching phenomena were observed under relatively low currents (below 10 μA) in this vertical-type RRAM device. The TaOxNy layer acted as a nonlinear resistor with moderate nonlinearity. Its low-resistance-state and high-resistance-state were well retained up to 1000 s.

Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing.

PubMed

Rao, Feng; Ding, Keyuan; Zhou, Yuxing; Zheng, Yonghui; Xia, Mengjiao; Lv, Shilong; Song, Zhitang; Feng, Songlin; Ronneberger, Ider; Mazzarello, Riccardo; Zhang, Wei; Ma, Evan

2017-12-15

Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge 2 Sb 2 Te 5 ). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc 0.2 Sb 2 Te 3 ) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Demystifying the memory effect: A geometrical approach to understanding speckle correlations

NASA Astrophysics Data System (ADS)

Prunty, Aaron C.; Snieder, Roel K.

2017-05-01

The memory effect has seen a surge of research into its fundamental properties and applications since its discovery by Feng et al. [Phys. Rev. Lett. 61, 834 (1988)]. While the wave trajectories for which the memory effect holds are hidden implicitly in the diffusion probability function [Phys. Rev. B 40, 737 (1989)], the physical intuition of why these trajectories satisfy the memory effect has often been masked by the derivation of the memory correlation function itself. In this paper, we explicitly derive the specific trajectories through a random medium for which the memory effect holds. Our approach shows that the memory effect follows from a simple conservation argument, which imposes geometrical constraints on the random trajectories that contribute to the memory effect. We illustrate the time-domain effects of these geometrical constraints with numerical simulations of pulse transmission through a random medium. The results of our derivation and numerical simulations are consistent with established theory and experimentation.

Some pitfalls in measuring memory in animals.

PubMed

Thorpe, Christina M; Jacova, Claudia; Wilkie, Donald M

2004-11-01

Because the presence or absence of memories in the brain cannot be directly observed, scientists must rely on indirect measures and use inferential reasoning to make statements about the status of memories. In humans, memories are often accessed through spoken or written language. In animals, memory is accessed through overt behaviours such as running down an arm in a maze, pressing a lever, or visiting a food cache site. Because memory is measured by these indirect methods, errors in the veracity of statements about memory can occur. In this brief paper, we identify three areas that may serve as pitfalls in reasoning about memory in animals: (1) the presence of 'silent associations', (2) intrusions of species-typical behaviours on memory tasks, and (3) improper mapping between human and animals memory tasks. There are undoubtedly other areas in which scientists should act cautiously when reasoning about the status of memory.

A Decision Model for Selection of Microcomputers and Operating Systems.

DTIC Science & Technology

1984-06-01

is resilting in application software (for microccmputers) being developed almost exclu- sively tor the IBM PC and compatiole systems. NAVDAC ielt that...location can be indepen- dently accessed. RAN memory is also often called read/ write memory, hecause new information can be written into and read from...when power is lost; this is also read/ write memory. Bubble memory, however, has significantly slower access times than RAM or RON and also is not preva

Photonic Potential of Haloarchaeal Pigment Bacteriorhodopsin for Future Electronics: A Review.

PubMed

Ashwini, Ravi; Vijayanand, S; Hemapriya, J

2017-08-01

Haloarchaea are known for its adaptation in extreme saline environment. Halophilic archaea produces carotenoid pigments and proton pumps to protect them from extremes of salinity. Bacteriorhodopsin (bR) is a light-driven proton pump that resides in the membrane of haloarchaea Halobacterium salinarum. The photocycle of Bacteriorhodopsin passes through several states from K to O, finally liberating ATP for host's survival. Extensive studies on Bacteriorhodopsin photocycle has provided in depth knowledge on their sequential mechanism of converting solar energy into chemical energy inside the cell. This ability of Bacteriorhodopsin to harvest sunlight has now been experimented to exploit the unexplored and extensively available solar energy in various biotechnological applications. Currently, bacteriorhodopsin finds its importance in dye-sensitized solar cell (DSSC), logic gates (integrated circuits, IC's), optical switching, optical memories, storage devices (random access memory, RAM), biosensors, electronic sensors and optical microcavities. This review deals with the optical and electrical applications of the purple pigment Bacteriorhodopsin.

Impulse voltage control of continuously tunable bipolar resistive switching in Pt/Bi0.9Eu0.1FeO3/Nb-doped SrTiO3 heterostructures

NASA Astrophysics Data System (ADS)

Wei, Maocai; Liu, Meifeng; Wang, Xiuzhang; Li, Meiya; Zhu, Yongdan; Zhao, Meng; Zhang, Feng; Xie, Shuai; Hu, Zhongqiang; Liu, Jun-Ming

2017-03-01

Epitaxial Bi0.9Eu0.1FeO3 (BEFO) thin films are deposited on Nb-doped SrTiO3 (NSTO) substrates by pulsed laser deposition to fabricate the Pt/BEFO/NSTO (001) heterostructures. These heterostructures possess bipolar resistive switching, where the resistances versus writing voltage exhibits a distinct hysteresis loop and a memristive behavior with good retention and anti-fatigue characteristics. The local resistive switching is confirmed by the conductive atomic force microscopy (C-AFM), suggesting the possibility to scale down the memory cell size. The observed memristive behavior could be attributed to the ferroelectric polarization effect, which modulates the height of potential barrier and width of depletion region at the BEFO/NSTO interface. The continuously tunable resistive switching behavior could be useful to achieve non-volatile, high-density, multilevel random access memory with low energy consumption.

Stress-based control of magnetic nanowire domain walls in artificial multiferroic systems

NASA Astrophysics Data System (ADS)

Dean, J.; Bryan, M. T.; Schrefl, T.; Allwood, D. A.

2011-01-01

Artificial multiferroic systems, which combine piezoelectric and piezomagnetic materials, offer novel methods of controlling material properties. Here, we use combined structural and magnetic finite element models to show how localized strains in a piezoelectric film coupled to a piezomagnetic nanowire can attract and pin magnetic domain walls. Synchronous switching of addressable contacts enables the controlled movement of pinning sites, and hence domain walls, in the nanowire without applied magnetic field or spin-polarized current, irrespective of domain wall structure. Conversely, domain wall-induced strain in the piezomagnetic material induces a local potential difference in the piezoelectric, providing a mechanism for sensing domain walls. This approach overcomes the problems in magnetic nanowire memories of domain wall structure-dependent behavior and high power consumption. Nonvolatile random access or shift register memories based on these effects can achieve storage densities >1 Gbit/In2, sub-10 ns switching times, and power consumption <100 keV per operation.

Resistive switching characteristics and mechanisms in silicon oxide memory devices

NASA Astrophysics Data System (ADS)

Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Wu, Xiaohan; Chen, Yen-Ting; Wang, Yanzhen; Xue, Fei; Lee, Jack C.

2016-05-01

Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)-compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

Design of the Wind Tunnel Model Communication Controller Board. Degree awarded by Christopher Newport Univ. on Dec. 1998

NASA Technical Reports Server (NTRS)

Wilson, William C.

1999-01-01

The NASA Langley Research Center's Wind Tunnel Reinvestment project plans to shrink the existing data acquisition electronics to fit inside a wind tunnel model. Space limitations within a model necessitate a distributed system of Application Specific Integrated Circuits (ASICs) rather than a centralized system based on PC boards. This thesis will focus on the design of the prototype of the communication Controller board. A portion of the communication Controller board is to be used as the basis of an ASIC design. The communication Controller board will communicate between the internal model modules and the external data acquisition computer. This board is based around an Field Programmable Gate Array (FPGA), to allow for reconfigurability. In addition to the FPGA, this board contains buffer Random Access Memory (RAM), configuration memory (EEPROM), drivers for the communications ports, and passive components.

Application of a microcomputer-based system to control and monitor bacterial growth.

PubMed

Titus, J A; Luli, G W; Dekleva, M L; Strohl, W R

1984-02-01

A modular microcomputer-based system was developed to control and monitor various modes of bacterial growth. The control system was composed of an Apple II Plus microcomputer with 64-kilobyte random-access memory; a Cyborg ISAAC model 91A multichannel analog-to-digital and digital-to-analog converter; paired MRR-1 pH, pO(2), and foam control units; and in-house-designed relay, servo control, and turbidimetry systems. To demonstrate the flexibility of the system, we grew bacteria under various computer-controlled and monitored modes of growth, including batch, turbidostat, and chemostat systems. The Apple-ISAAC system was programmed in Labsoft BASIC (extended Applesoft) with an average control program using ca. 6 to 8 kilobytes of memory and up to 30 kilobytes for datum arrays. This modular microcomputer-based control system was easily coupled to laboratory scale fermentors for a variety of fermentations.

Application of a Microcomputer-Based System to Control and Monitor Bacterial Growth

PubMed Central

Titus, Jeffrey A.; Luli, Gregory W.; Dekleva, Michael L.; Strohl, William R.

1984-01-01

A modular microcomputer-based system was developed to control and monitor various modes of bacterial growth. The control system was composed of an Apple II Plus microcomputer with 64-kilobyte random-access memory; a Cyborg ISAAC model 91A multichannel analog-to-digital and digital-to-analog converter; paired MRR-1 pH, pO2, and foam control units; and in-house-designed relay, servo control, and turbidimetry systems. To demonstrate the flexibility of the system, we grew bacteria under various computer-controlled and monitored modes of growth, including batch, turbidostat, and chemostat systems. The Apple-ISAAC system was programmed in Labsoft BASIC (extended Applesoft) with an average control program using ca. 6 to 8 kilobytes of memory and up to 30 kilobytes for datum arrays. This modular microcomputer-based control system was easily coupled to laboratory scale fermentors for a variety of fermentations. PMID:16346462

Resistive switching properties and physical mechanism of cobalt ferrite thin films

NASA Astrophysics Data System (ADS)

Hu, Wei; Zou, Lilan; Chen, Ruqi; Xie, Wei; Chen, Xinman; Qin, Ni; Li, Shuwei; Yang, Guowei; Bao, Dinghua

2014-04-01

We report reproducible resistive switching performance and relevant physical mechanism of sandwiched Pt/CoFe2O4/Pt structures in which the CoFe2O4 thin films were fabricated by a chemical solution deposition method. Uniform switching voltages, good endurance, and long retention have been demonstrated in the Pt/CoFe2O4/Pt memory cells. On the basis of the analysis of current-voltage characteristic and its temperature dependence, we suggest that the carriers transport through the conducting filaments in low resistance state with Ohmic conduction behavior, and the Schottky emission and Poole-Frenkel emission dominate the conduction mechanism in high resistance state. From resistance-temperature dependence of resistance states, we believe that the physical origin of the resistive switching refers to the formation and rupture of the oxygen vacancies related filaments. The nanostructured CoFe2O4 thin films can find applications in resistive random access memory.