A CCD experimental platform for large telescope in Antarctica based on FPGA

NASA Astrophysics Data System (ADS)

Zhu, Yuhua; Qi, Yongjun

2014-07-01

The CCD , as a detector , is one of the important components of astronomical telescopes. For a large telescope in Antarctica, a set of CCD detector system with large size, high sensitivity and low noise is indispensable. Because of the extremely low temperatures and unattended, system maintenance and software and hardware upgrade become hard problems. This paper introduces a general CCD controller experiment platform, using Field programmable gate array FPGA, which is, in fact, a large-scale field reconfigurable array. Taking the advantage of convenience to modify the system, construction of driving circuit, digital signal processing module, network communication interface, control algorithm validation, and remote reconfigurable module may realize. With the concept of integrated hardware and software, the paper discusses the key technology of building scientific CCD system suitable for the special work environment in Antarctica, focusing on the method of remote reconfiguration for controller via network and then offering a feasible hardware and software solution.

High-Performance, Radiation-Hardened Electronics for Space Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.; Frazier, Donald O.; Adams, James H.; Johnson, Michael A.; Kolawa, Elizabeth A.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project endeavors to advance the current state-of-the-art in high-performance, radiation-hardened electronics and processors, ensuring successful performance of space systems required to operate within extreme radiation and temperature environments. Because RHESE is a project within the Exploration Technology Development Program (ETDP), RHESE's primary customers will be the human and robotic missions being developed by NASA's Exploration Systems Mission Directorate (ESMD) in partial fulfillment of the Vision for Space Exploration. Benefits are also anticipated for NASA's science missions to planetary and deep-space destinations. As a technology development effort, RHESE provides a broad-scoped, full spectrum of approaches to environmentally harden space electronics, including new materials, advanced design processes, reconfigurable hardware techniques, and software modeling of the radiation environment. The RHESE sub-project tasks are: SelfReconfigurable Electronics for Extreme Environments, Radiation Effects Predictive Modeling, Radiation Hardened Memory, Single Event Effects (SEE) Immune Reconfigurable Field Programmable Gate Array (FPGA) (SIRF), Radiation Hardening by Software, Radiation Hardened High Performance Processors (HPP), Reconfigurable Computing, Low Temperature Tolerant MEMS by Design, and Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments. These nine sub-project tasks are managed by technical leads as located across five different NASA field centers, including Ames Research Center, Goddard Space Flight Center, the Jet Propulsion Laboratory, Langley Research Center, and Marshall Space Flight Center. The overall RHESE integrated project management responsibility resides with NASA's Marshall Space Flight Center (MSFC). Initial technology development emphasis within RHESE focuses on the hardening of Field Programmable Gate Arrays (FPGA)s and Field Programmable Analog Arrays (FPAA)s for use in reconfigurable architectures. As these component/chip level technologies mature, the RHESE project emphasis shifts to focus on efforts encompassing total processor hardening techniques and board-level electronic reconfiguration techniques featuring spare and interface modularity. This phased approach to distributing emphasis between technology developments provides hardened FPGA/FPAAs for early mission infusion, then migrates to hardened, board-level, high speed processors with associated memory elements and high density storage for the longer duration missions encountered for Lunar Outpost and Mars Exploration occurring later in the Constellation schedule.

Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Supinski, B.; Caliga, D.

2017-09-28

The primary objective of this project was to develop memory optimization technology to efficiently deliver data to, and distribute data within, the SRC-6's Field Programmable Gate Array- ("FPGA") based Multi-Adaptive Processors (MAPs). The hardware/software approach was to explore efficient MAP configurations and generate the compiler technology to exploit those configurations. This memory accessing technology represents an important step towards making reconfigurable symmetric multi-processor (SMP) architectures that will be a costeffective solution for large-scale scientific computing.

Dual-Gated Active Metasurface at 1550 nm with Wide (>300°) Phase Tunability.

PubMed

Kafaie Shirmanesh, Ghazaleh; Sokhoyan, Ruzan; Pala, Ragip A; Atwater, Harry A

2018-05-09

Active metasurfaces composed of electrically reconfigurable nanoscale subwavelength antenna arrays can enable real-time control of scattered light amplitude and phase. Achievement of widely tunable phase and amplitude in chip-based active metasurfaces operating at or near 1550 nm wavelength has considerable potential for active beam steering, dynamic hologram rendition, and realization of flat optics with reconfigurable focal lengths. Previously, electrically tunable conducting oxide-based reflectarray metasurfaces have demonstrated dynamic phase control of reflected light with a maximum phase shift of 184° ( Nano Lett. 2016 , 16 , 5319 ). Here, we introduce a dual-gated reflectarray metasurface architecture that enables much wider (>300°) phase tunability. We explore light-matter interactions with dual-gated metasurface elements that incorporate two independent voltage-controlled MOS field effect channels connected in series to form a single metasurface element that enables wider phase tunability. Using indium tin oxide (ITO) as the active metasurface material and a composite hafnia/alumina gate dielectric, we demonstrate a prototype dual-gated metasurface with a continuous phase shift from 0 to 303° and a relative reflectance modulation of 89% under applied voltage bias of 6.5 V.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Realization of the manipulation of ultracold atoms with a reconfigurable nanomagnetic system of domain walls.

PubMed

West, Adam D; Weatherill, Kevin J; Hayward, Thomas J; Fry, Paul W; Schrefl, Thomas; Gibbs, Mike R J; Adams, Charles S; Allwood, Dan A; Hughes, Ifan G

2012-08-08

Planar magnetic nanowires have been vital to the development of spintronic technology. They provide an unparalleled combination of magnetic reconfigurability, controllability, and scalability, which has helped to realize such applications as racetrack memory and novel logic gates. Microfabricated atom optics benefit from all of these properties, and we present the first demonstration of the amalgamation of spintronic technology with ultracold atoms. A magnetic interaction is exhibited through the reflection of a cloud of (87)Rb atoms at a temperature of 10 μK, from a 2 mm × 2 mm array of nanomagnetic domain walls. In turn, the incident atoms approach the array at heights of the order of 100 nm and are thus used to probe magnetic fields at this distance.

Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Darrin, Ann Garrison; Conde, Richard; Chern, Bobbie; Luers, Phil; Jurczyk, Steve; Mills, Carl; Day, John H. (Technical Monitor)

2001-01-01

The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of radiation tolerant RAM-based field programmable gate array (FPGA) technology to develop a reconfigurable processor that combines the flexibility of a general purpose processor running software with the performance of application specific processing hardware for a variety of high performance computing applications.

The IMPACT Common Module - A Low Cost, Reconfigurable Building Block for Next Generation Phased Arrays

DTIC Science & Technology

2016-03-31

The SiGe receiver has two stages of programmable RF filtering and one stage of IF filtering. Each filter can be tuned in center frequency and...distribution unlimited. transmit, with an IF to RF upconversion chain that is split to programmable phase shifters and VGAs at each output port. Figure 2...These are optimized to run on medium grade Field Programmable Gate Arrays (FPGAs), such as the Altera Arria 10, and represent a few of the many

Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin

Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sourcesmore » and detectors through an external clock with adjustable delay.« less

A reconfigurable continuous-flow fluidic routing fabric using a modular, scalable primitive.

PubMed

Silva, Ryan; Bhatia, Swapnil; Densmore, Douglas

2016-07-05

Microfluidic devices, by definition, are required to move liquids from one physical location to another. Given a finite and frequently fixed set of physical channels to route fluids, a primitive design element that allows reconfigurable routing of that fluid from any of n input ports to any n output ports will dramatically change the paradigms by which these chips are designed and applied. Furthermore, if these elements are "regular" regarding their design, the programming and fabrication of these elements becomes scalable. This paper presents such a design element called a transposer. We illustrate the design, fabrication and operation of a single transposer. We then scale this design to create a programmable fabric towards a general-purpose, reconfigurable microfluidic platform analogous to the Field Programmable Gate Array (FPGA) found in digital electronics.

Reconfigurable, Cognitive Software-Defined Radio

NASA Technical Reports Server (NTRS)

Bhat, Arvind

2015-01-01

Software-defined radio (SDR) technology allows radios to be reconfigured to perform different communication functions without using multiple radios to accomplish each task. Intelligent Automation, Inc., has developed SDR platforms that switch adaptively between different operation modes. The innovation works by modifying both transmit waveforms and receiver signal processing tasks. In Phase I of the project, the company developed SDR cognitive capabilities, including adaptive modulation and coding (AMC), automatic modulation recognition (AMR), and spectrum sensing. In Phase II, these capabilities were integrated into SDR platforms. The reconfigurable transceiver design employs high-speed field-programmable gate arrays, enabling multimode operation and scalable architecture. Designs are based on commercial off-the-shelf (COTS) components and are modular in nature, making it easier to upgrade individual components rather than redesigning the entire SDR platform as technology advances.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

NASA Technical Reports Server (NTRS)

French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

2005-01-01

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

NASA Astrophysics Data System (ADS)

Mar, Jeich; Kuo, Chi-Cheng; Wu, Shin-Ru; Lin, You-Rong

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

PubMed Central

García, Gabriel J.; Jara, Carlos A.; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M.; Torres, Fernando

2014-01-01

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field. PMID:24691100

A survey on FPGA-based sensor systems: towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing.

PubMed

García, Gabriel J; Jara, Carlos A; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M; Torres, Fernando

2014-03-31

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

Software-Reconfigurable Processors for Spacecraft

NASA Technical Reports Server (NTRS)

Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

2005-01-01

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

FPGA-based gating and logic for multichannel single photon counting

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G

2012-01-01

We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidencemore » measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)« less

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Charge reconfiguration in arrays of quantum dots

NASA Astrophysics Data System (ADS)

Bayer, Johannes C.; Wagner, Timo; Rugeramigabo, Eddy P.; Haug, Rolf J.

2017-12-01

Semiconductor quantum dots are potential building blocks for scalable qubit architectures. Efficient control over the exchange interaction and the possibility of coherently manipulating electron states are essential ingredients towards this goal. We studied experimentally the shuttling of electrons trapped in serial quantum dot arrays isolated from the reservoirs. The isolation hereby enables a high degree of control over the tunnel couplings between the quantum dots, while electrons can be transferred through the array by gate voltage variations. Model calculations are compared with our experimental results for double, triple, and quadruple quantum dot arrays. We are able to identify all transitions observed in our experiments, including cotunneling transitions between distant quantum dots. The shuttling of individual electrons between quantum dots along chosen paths is demonstrated.

A Gigabit-per-Second Ka-Band Demonstration Using a Reconfigurable FPGA Modulator

NASA Technical Reports Server (NTRS)

Lee, Dennis; Gray, Andrew A.; Kang, Edward C.; Tsou, Haiping; Lay, Norman E.; Fong, Wai; Fisher, Dave; Hoy, Scott

2005-01-01

Gigabit-per-second communications have been a desired target for future NASA Earth science missions, and for potential manned lunar missions. Frequency bandwidth at S-band and X-band is typically insufficient to support missions at these high data rates. In this paper, we present the results of a 1 Gbps 32-QAM end-to-end experiment at Ka-band using a reconfigurable Field Programmable Gate Array (FPGA) baseband modulator board. Bit error rate measurements of the received signal using a software receiver demonstrate the feasibility of using ultra-high data rates at Ka-band, although results indicate that error correcting coding and/or modulator predistortion must be implemented in addition. Also, results of the demonstration validate the low-cost, MOS-based reconfigurable modulator approach taken to development of a high rate modulator, as opposed to more expensive ASIC or pure analog approaches.

Radiation Hardened Electronics for Extreme Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches.

Low-Cost Space Hardware and Software

NASA Technical Reports Server (NTRS)

Shea, Bradley Franklin

2013-01-01

The goal of this project is to demonstrate and support the overall vision of NASA's Rocket University (RocketU) through the design of an electrical power system (EPS) monitor for implementation on RUBICS (Rocket University Broad Initiatives CubeSat), through the support for the CHREC (Center for High-Performance Reconfigurable Computing) Space Processor, and through FPGA (Field Programmable Gate Array) design. RocketU will continue to provide low-cost innovations even with continuous cuts to the budget.

Spacecube V2.0 Micro Single Board Computer

NASA Technical Reports Server (NTRS)

Petrick, David J. (Inventor); Geist, Alessandro (Inventor); Lin, Michael R. (Inventor); Crum, Gary R. (Inventor)

2017-01-01

A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm.times.7 cm.

An acceleration framework for synthetic aperture radar algorithms

NASA Astrophysics Data System (ADS)

Kim, Youngsoo; Gloster, Clay S.; Alexander, Winser E.

2017-04-01

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.

A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs

NASA Astrophysics Data System (ADS)

Sterpone, L.; Violante, M.

2007-08-01

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing complex system. Unfortunately, SRAM-based FPGAs are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to successfully deploy safety- or mission-critical applications, designer need to validate the correctness of the obtained designs. In this paper we describe a system based on partial-reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs. The proposed fault-injection system uses the internal configuration capabilities that modern FPGAs offer in order to inject SEU within the configuration memory. Detailed experimental results show that the technique is orders of magnitude faster than previously proposed ones.

Exploiting the chaotic behaviour of atmospheric models with reconfigurable architectures

NASA Astrophysics Data System (ADS)

Russell, Francis P.; Düben, Peter D.; Niu, Xinyu; Luk, Wayne; Palmer, T. N.

2017-12-01

Reconfigurable architectures are becoming mainstream: Amazon, Microsoft and IBM are supporting such architectures in their data centres. The computationally intensive nature of atmospheric modelling is an attractive target for hardware acceleration using reconfigurable computing. Performance of hardware designs can be improved through the use of reduced-precision arithmetic, but maintaining appropriate accuracy is essential. We explore reduced-precision optimisation for simulating chaotic systems, targeting atmospheric modelling, in which even minor changes in arithmetic behaviour will cause simulations to diverge quickly. The possibility of equally valid simulations having differing outcomes means that standard techniques for comparing numerical accuracy are inappropriate. We use the Hellinger distance to compare statistical behaviour between reduced-precision CPU implementations to guide reconfigurable designs of a chaotic system, then analyse accuracy, performance and power efficiency of the resulting implementations. Our results show that with only a limited loss in accuracy corresponding to less than 10% uncertainty in input parameters, the throughput and energy efficiency of a single-precision chaotic system implemented on a Xilinx Virtex-6 SX475T Field Programmable Gate Array (FPGA) can be more than doubled.

A Reconfigurable Instrument System for Nuclear and Particle Physics Experiments

NASA Astrophysics Data System (ADS)

Sang, Ziru; Li, Feng; Jiang, Xiao; Jin, Ge

2014-04-01

We developed a reconfigurable nuclear instrument system (RNIS) that could satisfy the requirements of diverse nuclear and particle physics experiments, and the inertial confinement fusion diagnostic. Benefiting from the reconfigurable hardware structure and digital pulse processing technology, RNIS shakes off the restrictions of cumbersome crates and miscellaneous modules. It retains all the advantages of conventional nuclear instruments and is more flexible and portable. RNIS is primarily composed of a field programmable hardware board and relevant PC software. Separate analog channels are designed to provide different functions, such as amplifiers, ADC, fast discriminators and Schmitt discriminators for diverse experimental purposes. The high-performance field programmable gate array could complete high-precision time interval measurement, histogram accumulation, counting, and coincidence anticoincidence measurement. To illustrate the prospects of RNIS, a series of applications to the experiments are described in this paper. The first, for which RNIS was originally developed, involves nuclear energy spectrum measurement with a scintillation detector and photomultiplier. The second experiment applies RNIS to a G-M tube counting experiment, and in the third, it is applied to a quantum communication experiment through reconfiguration.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge

The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memoriesmore » for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)« less

A Plug and Play GNC Architecture Using FPGA Components

NASA Technical Reports Server (NTRS)

KrishnaKumar, K.; Kaneshige, J.; Waterman, R.; Pires, C.; Ippoloito, C.

2005-01-01

The goal of Plug and Play, or PnP, is to allow hardware and software components to work together automatically, without requiring manual setup procedures. As a result, new or replacement hardware can be plugged into a system and automatically configured with the appropriate resource assignments. However, in many cases it may not be practical or even feasible to physically replace hardware components. One method for handling these types of situations is through the incorporation of reconfigurable hardware such as Field Programmable Gate Arrays, or FPGAs. This paper describes a phased approach to developing a Guidance, Navigation, and Control (GNC) architecture that expands on the traditional concepts of PnP, in order to accommodate hardware reconfiguration without requiring detailed knowledge of the hardware. This is achieved by establishing a functional based interface that defines how the hardware will operate, and allow the hardware to reconfigure itself. The resulting system combines the flexibility of manipulating software components with the speed and efficiency of hardware.

Colt: an experiment in wormhole run-time reconfiguration

NASA Astrophysics Data System (ADS)

Bittner, Ray; Athanas, Peter M.; Musgrove, Mark

1996-10-01

Wormhole run-time reconfiguration (RTR) is an attempt to create a refined computing paradigm for high performance computational tasks. By combining concepts from field programmable gate array (FPGA) technologies with data flow computing, the Colt/Stallion architecture achieves high utilization of hardware resources, and facilitates rapid run-time reconfiguration. Targeted mainly at DSP-type operations, the Colt integrated circuit -- a prototype wormhole RTR device -- compares favorably to contemporary DSP alternatives in terms of silicon area consumed per unit computation and in computing performance. Although emphasis has been placed on signal processing applications, general purpose computation has not been overlooked. Colt is a prototype that defines an architecture not only at the chip level but also in terms of an overall system design. As this system is realized, the concept of wormhole RTR will be applied to numerical computation and DSP applications including those common to image processing, communications systems, digital filters, acoustic processing, real-time control systems and simulation acceleration.

Radiation effects in reconfigurable FPGAs

NASA Astrophysics Data System (ADS)

Quinn, Heather

2017-04-01

Field-programmable gate arrays (FPGAs) are co-processing hardware used in image and signal processing. FPGA are programmed with custom implementations of an algorithm. These algorithms are highly parallel hardware designs that are faster than software implementations. This flexibility and speed has made FPGAs attractive for many space programs that need in situ, high-speed signal processing for data categorization and data compression. Most commercial FPGAs are affected by the space radiation environment, though. Problems with TID has restricted the use of flash-based FPGAs. Static random access memory based FPGAs must be mitigated to suppress errors from single-event upsets. This paper provides a review of radiation effects issues in reconfigurable FPGAs and discusses methods for mitigating these problems. With careful design it is possible to use these components effectively and resiliently.

Asymmetric Core Computing for U.S. Army High-Performance Computing Applications

DTIC Science & Technology

2009-04-01

Playstation 4 (should one be announced). 8 4.2 FPGAs Reconfigurable computing refers to performing computations using Field Programmable Gate Arrays...2008 4 . TITLE AND SUBTITLE Asymmetric Core Computing for U.S. Army High-Performance Computing Applications 5a. CONTRACT NUMBER 5b. GRANT NUMBER...Acknowledgments vi  1.  Introduction 1  2.  Relevant Technologies 2  3.  Technical Approach 5  4 .  Research and Development Highlights 7  4.1  Cell

Radiation Tolerant, FPGA-Based SmallSat Computer System

NASA Technical Reports Server (NTRS)

LaMeres, Brock J.; Crum, Gary A.; Martinez, Andres; Petro, Andrew

2015-01-01

The Radiation Tolerant, FPGA-based SmallSat Computer System (RadSat) computing platform exploits a commercial off-the-shelf (COTS) Field Programmable Gate Array (FPGA) with real-time partial reconfiguration to provide increased performance, power efficiency and radiation tolerance at a fraction of the cost of existing radiation hardened computing solutions. This technology is ideal for small spacecraft that require state-of-the-art on-board processing in harsh radiation environments but where using radiation hardened processors is cost prohibitive.

Technology Developments in Radiation-Hardened Electronics for Space Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Howell, Joe T.

2008-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS, Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches. System level applications for the RHESE technology products are discussed.

Direction of Arrival Estimation Using a Reconfigurable Array

DTIC Science & Technology

2005-05-06

civilian world. Keywords: Direction-of-arrival Estimation MUSIC algorithm Reconfigurable Array Experimental Created by Neevia Personal...14. SUBJECT TERMS: Direction-of-arrival ; Estimation ; MUSIC algorithm ; Reconfigurable ; Array ; Experimental 16. PRICE CODE 17...9 1.5 MuSiC Algorithm

Reconfigurable Diodes Based on Vertical WSe2 Transistors with van der Waals Bonded Contacts.

PubMed

Avsar, Ahmet; Marinov, Kolyo; Marin, Enrique Gonzalez; Iannaccone, Giuseppe; Watanabe, Kenji; Taniguchi, Takashi; Fiori, Gianluca; Kis, Andras

2018-05-01

New device concepts can increase the functionality of scaled electronic devices, with reconfigurable diodes allowing the design of more compact logic gates being one of the examples. In recent years, there has been significant interest in creating reconfigurable diodes based on ultrathin transition metal dichalcogenide crystals due to their unique combination of gate-tunable charge carriers, high mobility, and sizeable band gap. Thanks to their large surface areas, these devices are constructed under planar geometry and the device characteristics are controlled by electrostatic gating through rather complex two independent local gates or ionic-liquid gating. In this work, similar reconfigurable diode action is demonstrated in a WSe 2 transistor by only utilizing van der Waals bonded graphene and Co/h-BN contacts. Toward this, first the charge injection efficiencies into WSe 2 by graphene and Co/h-BN contacts are characterized. While Co/h-BN contact results in nearly Schottky-barrier-free charge injection, graphene/WSe 2 interface has an average barrier height of ≈80 meV. By taking the advantage of the electrostatic transparency of graphene and the different work-function values of graphene and Co/h-BN, vertical devices are constructed where different gate-tunable diode actions are demonstrated. This architecture reveals the opportunities for exploring new device concepts. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Spaceborne Hybrid-FPGA System for Processing FTIR Data

NASA Technical Reports Server (NTRS)

Bekker, Dmitriy; Blavier, Jean-Francois L.; Pingree, Paula J.; Lukowiak, Marcin; Shaaban, Muhammad

2008-01-01

Progress has been made in a continuing effort to develop a spaceborne computer system for processing readout data from a Fourier-transform infrared (FTIR) spectrometer to reduce the volume of data transmitted to Earth. The approach followed in this effort, oriented toward reducing design time and reducing the size and weight of the spectrometer electronics, has been to exploit the versatility of recently developed hybrid field-programmable gate arrays (FPGAs) to run diverse software on embedded processors while also taking advantage of the reconfigurable hardware resources of the FPGAs.

Mitigating Upsets in SRAM-Based FPGAs from the Xilinx Virtex 2 Family

NASA Technical Reports Server (NTRS)

Swift, G. M.; Yui, C. C.; Carmichael, C.; Koga, R.; George, J. S.

2003-01-01

Static random access memory (SRAM) upset rates in field programmable gate arrays (FPGAs) from the Xilinx Virtex 2 family have been tested for radiation effects on configuration memory, block RAM and the power-on-reset (POR) and SelectMAP single event functional interrupts (SEFIs). Dynamic testing has shown the effectiveness and value of Triple Module Redundancy (TMR) and partial reconfiguration when used in conjunction. Continuing dynamic testing for more complex designs and other Virtex 2 capabilities (i.e., I/O standards, digital clock managers (DCM), etc.) is scheduled.

Reconfigurable and non-volatile vertical magnetic logic gates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Butler, J., E-mail: jbutl001@ucr.edu; Lee, B.; Shachar, M.

2014-04-28

In this paper, we discuss the concept and prototype fabrication of reconfigurable and non-volatile vertical magnetic logic gates. These gates consist of two input layers and a RESET layer. The RESET layer allows the structure to be used as either an AND or an OR gate, depending on its magnetization state. To prove this concept, the gates were fabricated using a multi-layered patterned magnetic media, in which three magnetic layers are stacked and exchange-decoupled via non-magnetic interlayers. We demonstrate the functionality of these logic gates by conducting atomic force microscopy and magnetic force microscopy (MFM) analysis of the multi-layered patternedmore » magnetic media. The logic gates operation mechanism and fabrication feasibility are both validated by the MFM imaging results.« less

Active vibration control of a full scale aircraft wing using a reconfigurable controller

NASA Astrophysics Data System (ADS)

Prakash, Shashikala; Renjith Kumar, T. G.; Raja, S.; Dwarakanathan, D.; Subramani, H.; Karthikeyan, C.

2016-01-01

This work highlights the design of a Reconfigurable Active Vibration Control (AVC) System for aircraft structures using adaptive techniques. The AVC system with a multichannel capability is realized using Filtered-X Least Mean Square algorithm (FxLMS) on Xilinx Virtex-4 Field Programmable Gate Array (FPGA) platform in Very High Speed Integrated Circuits Hardware Description Language, (VHDL). The HDL design is made based on Finite State Machine (FSM) model with Floating point Intellectual Property (IP) cores for arithmetic operations. The use of FPGA facilitates to modify the system parameters even during runtime depending on the changes in user's requirements. The locations of the control actuators are optimized based on dynamic modal strain approach using genetic algorithm (GA). The developed system has been successfully deployed for the AVC testing of the full-scale wing of an all composite two seater transport aircraft. Several closed loop configurations like single channel and multi-channel control have been tested. The experimental results from the studies presented here are very encouraging. They demonstrate the usefulness of the system's reconfigurability for real time applications.

An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.

PubMed

Kazemi, Mohammad

2017-11-10

The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.

The trigger system for the external target experiment in the HIRFL cooling storage ring

NASA Astrophysics Data System (ADS)

Li, Min; Zhao, Lei; Liu, Jin-Xin; Lu, Yi-Ming; Liu, Shu-Bin; An, Qi

2016-08-01

A trigger system was designed for the external target experiment in the Cooling Storage Ring (CSR) of the Heavy Ion Research Facility in Lanzhou (HIRFL). Considering that different detectors are scattered over a large area, the trigger system is designed based on a master-slave structure and fiber-based serial data transmission technique. The trigger logic is organized in hierarchies, and flexible reconfiguration of the trigger function is achieved based on command register access or overall field-programmable gate array (FPGA) logic on-line reconfiguration controlled by remote computers. We also conducted tests to confirm the function of the trigger electronics, and the results indicate that this trigger system works well. Supported by the National Natural Science Foundation of China (11079003), the Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27), and the CAS Center for Excellence in Particle Physics (CCEPP).

Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems.

PubMed

Park, Jongkil; Yu, Theodore; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

2017-10-01

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at 3.6×10 7 synaptic events per second per 16k-neuron node in the hierarchy.

Radiation Tolerant Intelligent Memory Stack (RTIMS)

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2006-01-01

The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

Toward a Dynamically Reconfigurable Computing and Communication System for Small Spacecraft

NASA Technical Reports Server (NTRS)

Kifle, Muli; Andro, Monty; Tran, Quang K.; Fujikawa, Gene; Chu, Pong P.

2003-01-01

Future science missions will require the use of multiple spacecraft with multiple sensor nodes autonomously responding and adapting to a dynamically changing space environment. The acquisition of random scientific events will require rapidly changing network topologies, distributed processing power, and a dynamic resource management strategy. Optimum utilization and configuration of spacecraft communications and navigation resources will be critical in meeting the demand of these stringent mission requirements. There are two important trends to follow with respect to NASA's (National Aeronautics and Space Administration) future scientific missions: the use of multiple satellite systems and the development of an integrated space communications network. Reconfigurable computing and communication systems may enable versatile adaptation of a spacecraft system's resources by dynamic allocation of the processor hardware to perform new operations or to maintain functionality due to malfunctions or hardware faults. Advancements in FPGA (Field Programmable Gate Array) technology make it possible to incorporate major communication and network functionalities in FPGA chips and provide the basis for a dynamically reconfigurable communication system. Advantages of higher computation speeds and accuracy are envisioned with tremendous hardware flexibility to ensure maximum survivability of future science mission spacecraft. This paper discusses the requirements, enabling technologies, and challenges associated with dynamically reconfigurable space communications systems.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations.

PubMed

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-27

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

NASA Astrophysics Data System (ADS)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Synchronized operation by field programmable gate array based signal controller for the Thomson scattering diagnostic system in KSTAR.

PubMed

Lee, W R; Kim, H S; Park, M K; Lee, J H; Kim, K H

2012-09-01

The Thomson scattering diagnostic system is successfully installed in the Korea Superconducting Tokamak Advanced Research (KSTAR) facility. We got the electron temperature and electron density data for the first time in 2011, 4th campaign using a field programmable gate array (FPGA) based signal control board. It operates as a signal generator, a detector, a controller, and a time measuring device. This board produces two configurable trigger pulses to operate Nd:YAG laser system and receives a laser beam detection signal from a photodiode detector. It allows a trigger pulse to be delivered to a time delay module to make a scattered signal measurement, measuring an asynchronous time value between the KSTAR timing board and the laser system injection signal. All functions are controlled by the embedded processor running on operating system within a single FPGA. It provides Ethernet communication interface and is configured with standard middleware to integrate with KSTAR. This controller has operated for two experimental campaigns including commissioning and performed the reconfiguration of logic designs to accommodate varying experimental situation without hardware rebuilding.

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

Coherent Addressing of Individual Neutral Atoms in a 3D Optical Lattice.

PubMed

Wang, Yang; Zhang, Xianli; Corcovilos, Theodore A; Kumar, Aishwarya; Weiss, David S

2015-07-24

We demonstrate arbitrary coherent addressing of individual neutral atoms in a 5×5×5 array formed by an optical lattice. Addressing is accomplished using rapidly reconfigurable crossed laser beams to selectively ac Stark shift target atoms, so that only target atoms are resonant with state-changing microwaves. The effect of these targeted single qubit gates on the quantum information stored in nontargeted atoms is smaller than 3×10^{-3} in state fidelity. This is an important step along the path of converting the scalability promise of neutral atoms into reality.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

PubMed

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-05-25

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0 dBm and -25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10(-9) ) with an energy efficiency of 2 pJ/bit.

Field-programmable beam reconfiguring based on digitally-controlled coding metasurface

NASA Astrophysics Data System (ADS)

Wan, Xiang; Qi, Mei Qing; Chen, Tian Yi; Cui, Tie Jun

2016-02-01

Digital phase shifters have been applied in traditional phased array antennas to realize beam steering. However, the phase shifter deals with the phase of the induced current; hence, it has to be in the path of each element of the antenna array, making the phased array antennas very expensive. Metamaterials and/or metasurfaces enable the direct modulation of electromagnetic waves by designing subwavelength structures, which opens a new way to control the beam scanning. Here, we present a direct digital mechanism to control the scattered electromagnetic waves using coding metasurface, in which each unit cell loads a pin diode to produce binary coding states of “1” and “0”. Through data lines, the instant communications are established between the coding metasurface and the internal memory of field-programmable gate arrays (FPGA). Thus, we realize the digital modulation of electromagnetic waves, from which we present the field-programmable reflective antenna with good measurement performance. The proposed mechanism and functional device have great application potential in new-concept radar and communication systems.

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Wang, Xiao

2005-01-01

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

Reconfigurable Wave Velocity Transmission Lines for Phased Arrays

NASA Technical Reports Server (NTRS)

Host, Nick; Chen, Chi-Chih; Volakis, John L.; Miranda, Felix

2013-01-01

Phased array antennas showcase many advantages over mechanically steered systems. However, they are also more complex, heavy and most importantly costly. This presentation paper presents a concept which overcomes these detrimental attributes by eliminating all of the phase array backend (including phase shifters). Instead, a wave velocity reconfigurable transmission line is used in a series fed array arrangement to allow phase shifting with one small (100mil) mechanical motion. Different configurations of the reconfigurable wave velocity transmission line are discussed and simulated and experimental results are presented.

A Fixed Point VHDL Component Library for a High Efficiency Reconfigurable Radio Design Methodology

NASA Technical Reports Server (NTRS)

Hoy, Scott D.; Figueiredo, Marco A.

2006-01-01

Advances in Field Programmable Gate Array (FPGA) technologies enable the implementation of reconfigurable radio systems for both ground and space applications. The development of such systems challenges the current design paradigms and requires more robust design techniques to meet the increased system complexity. Among these techniques is the development of component libraries to reduce design cycle time and to improve design verification, consequently increasing the overall efficiency of the project development process while increasing design success rates and reducing engineering costs. This paper describes the reconfigurable radio component library developed at the Software Defined Radio Applications Research Center (SARC) at Goddard Space Flight Center (GSFC) Microwave and Communications Branch (Code 567). The library is a set of fixed-point VHDL components that link the Digital Signal Processing (DSP) simulation environment with the FPGA design tools. This provides a direct synthesis path based on the latest developments of the VHDL tools as proposed by the BEE VBDL 2004 which allows for the simulation and synthesis of fixed-point math operations while maintaining bit and cycle accuracy. The VHDL Fixed Point Reconfigurable Radio Component library does not require the use of the FPGA vendor specific automatic component generators and provide a generic path from high level DSP simulations implemented in Mathworks Simulink to any FPGA device. The access to the component synthesizable, source code provides full design verification capability:

Implementation of Multispectral Image Classification on a Remote Adaptive Computer

NASA Technical Reports Server (NTRS)

Figueiredo, Marco A.; Gloster, Clay S.; Stephens, Mark; Graves, Corey A.; Nakkar, Mouna

1999-01-01

As the demand for higher performance computers for the processing of remote sensing science algorithms increases, the need to investigate new computing paradigms its justified. Field Programmable Gate Arrays enable the implementation of algorithms at the hardware gate level, leading to orders of m a,gnitude performance increase over microprocessor based systems. The automatic classification of spaceborne multispectral images is an example of a computation intensive application, that, can benefit from implementation on an FPGA - based custom computing machine (adaptive or reconfigurable computer). A probabilistic neural network is used here to classify pixels of of a multispectral LANDSAT-2 image. The implementation described utilizes Java client/server application programs to access the adaptive computer from a remote site. Results verify that a remote hardware version of the algorithm (implemented on an adaptive computer) is significantly faster than a local software version of the same algorithm implemented on a typical general - purpose computer).

Reconfigurable fault tolerant avionics system

NASA Astrophysics Data System (ADS)

Ibrahim, M. M.; Asami, K.; Cho, Mengu

This paper presents the design of a reconfigurable avionics system based on modern Static Random Access Memory (SRAM)-based Field Programmable Gate Array (FPGA) to be used in future generations of nano satellites. A major concern in satellite systems and especially nano satellites is to build robust systems with low-power consumption profiles. The system is designed to be flexible by providing the capability of reconfiguring itself based on its orbital position. As Single Event Upsets (SEU) do not have the same severity and intensity in all orbital locations, having the maximum at the South Atlantic Anomaly (SAA) and the polar cusps, the system does not have to be fully protected all the time in its orbit. An acceptable level of protection against high-energy cosmic rays and charged particles roaming in space is provided within the majority of the orbit through software fault tolerance. Check pointing and roll back, besides control flow assertions, is used for that level of protection. In the minority part of the orbit where severe SEUs are expected to exist, a reconfiguration for the system FPGA is initiated where the processor systems are triplicated and protection through Triple Modular Redundancy (TMR) with feedback is provided. This technique of reconfiguring the system as per the level of the threat expected from SEU-induced faults helps in reducing the average dynamic power consumption of the system to one-third of its maximum. This technique can be viewed as a smart protection through system reconfiguration. The system is built on the commercial version of the (XC5VLX50) Xilinx Virtex5 FPGA on bulk silicon with 324 IO. Simulations of orbit SEU rates were carried out using the SPENVIS web-based software package.

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

Spacecube: A Family of Reconfigurable Hybrid On-Board Science Data Processors

NASA Technical Reports Server (NTRS)

Flatley, Thomas P.

2015-01-01

SpaceCube is a family of Field Programmable Gate Array (FPGA) based on-board science data processing systems developed at the NASA Goddard Space Flight Center (GSFC). The goal of the SpaceCube program is to provide 10x to 100x improvements in on-board computing power while lowering relative power consumption and cost. SpaceCube is based on the Xilinx Virtex family of FPGAs, which include processor, FPGA logic and digital signal processing (DSP) resources. These processing elements are leveraged to produce a hybrid science data processing platform that accelerates the execution of algorithms by distributing computational functions to the most suitable elements. This approach enables the implementation of complex on-board functions that were previously limited to ground based systems, such as on-board product generation, data reduction, calibration, classification, eventfeature detection, data mining and real-time autonomous operations. The system is fully reconfigurable in flight, including data parameters, software and FPGA logic, through either ground commanding or autonomously in response to detected eventsfeatures in the instrument data stream.

A Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

NASA Technical Reports Server (NTRS)

White, Michael J.

2004-01-01

This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.

Remotely Powered Reconfigurable Receiver for Extreme Environment Sensing Platforms

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2012-01-01

Wireless sensors connected in a local network offer revolutionary exploration capabilities, but the current solutions do not work in extreme environments of low temperatures (200K) and low to moderate radiation levels (<50 krad). These sensors (temperature, radiation, infrared, etc.) would need to operate outside the spacecraft/ lander and be totally independent of power from the spacecraft/lander. Flash memory field-programmable gate arrays (FPGAs) are being used as the main signal processing and protocol generation platform in a new receiver. Flash-based FPGAs have been shown to have at least 100 reduced standby power and 10 reduction operating power when compared to normal SRAM-based FPGA technology.

Radiation-Tolerant Intelligent Memory Stack - RTIMS

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2011-01-01

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

PubMed Central

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-01-01

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit. PMID:27231915

Applying a Genetic Algorithm to Reconfigurable Hardware

NASA Technical Reports Server (NTRS)

Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

2004-01-01

This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation

NASA Astrophysics Data System (ADS)

Kyrkou, Christos; Theocharides, Theocharis

2016-07-01

Object detection is a major step in several computer vision applications and a requirement for most smart camera systems. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware [field programmable gate arrays (FPGAs)], and relevant research has produced quite fascinating results, in both the accuracy of the detection algorithms as well as the performance in terms of frames per second (fps) for use in embedded smart camera systems. Detecting objects in images, however, is a daunting task and often involves hardware-inefficient steps, both in terms of the datapath design and in terms of input/output and memory access patterns. We present how a visual-feature-directed search cascade composed of motion detection, depth computation, and edge detection, can have a significant impact in reducing the data that needs to be examined by the classification engine for the presence of an object of interest. Experimental results on a Spartan 6 FPGA platform for face detection indicate data search reduction of up to 95%, which results in the system being able to process up to 50 1024×768 pixels images per second with a significantly reduced number of false positives.

SWARM: A 32 GHz Correlator and VLBI Beamformer for the Submillimeter Array

NASA Astrophysics Data System (ADS)

Primiani, Rurik A.; Young, Kenneth H.; Young, André; Patel, Nimesh; Wilson, Robert W.; Vertatschitsch, Laura; Chitwood, Billie B.; Srinivasan, Ranjani; MacMahon, David; Weintroub, Jonathan

2016-03-01

A 32GHz bandwidth VLBI capable correlator and phased array has been designed and deployeda at the Smithsonian Astrophysical Observatory’s Submillimeter Array (SMA). The SMA Wideband Astronomical ROACH2 Machine (SWARM) integrates two instruments: a correlator with 140kHz spectral resolution across its full 32GHz band, used for connected interferometric observations, and a phased array summer used when the SMA participates as a station in the Event Horizon Telescope (EHT) very long baseline interferometry (VLBI) array. For each SWARM quadrant, Reconfigurable Open Architecture Computing Hardware (ROACH2) units shared under open-source from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) are equipped with a pair of ultra-fast analog-to-digital converters (ADCs), a field programmable gate array (FPGA) processor, and eight 10 Gigabit Ethernet (GbE) ports. A VLBI data recorder interface designated the SWARM digital back end, or SDBE, is implemented with a ninth ROACH2 per quadrant, feeding four Mark6 VLBI recorders with an aggregate recording rate of 64 Gbps. This paper describes the design and implementation of SWARM, as well as its deployment at SMA with reference to verification and science data.

A reconfigurable gate architecture for Si/SiGe quantum dots

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zajac, D. M.; Hazard, T. M.; Mi, X.

2015-06-01

We demonstrate a reconfigurable quantum dot gate architecture that incorporates two interchangeable transport channels. One channel is used to form quantum dots, and the other is used for charge sensing. The quantum dot transport channel can support either a single or a double quantum dot. We demonstrate few-electron occupation in a single quantum dot and extract charging energies as large as 6.6 meV. Magnetospectroscopy is used to measure valley splittings in the range of 35–70 μeV. By energizing two additional gates, we form a few-electron double quantum dot and demonstrate tunable tunnel coupling at the (1,0) to (0,1) interdot charge transition.

Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems

PubMed Central

Atoche, Alejandro Castillo; Castillo, Javier Vázquez

2012-01-01

A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor systems. The selected reconstructive SP algorithms are efficiently transformed in their parallel representation and then, they are mapped into an efficient high performance embedded computing (HPEC) architecture in reconfigurable Xilinx field programmable gate array (FPGA) platforms. As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) from a remotely sensed scene. We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode. PMID:22736964

Rapidly reconfigurable all-optical universal logic gate

DOEpatents

Goddard, Lynford L.; Bond, Tiziana C.; Kallman, Jeffrey S.

2010-09-07

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

Reconfigurable Fault Tolerance for FPGAs

NASA Technical Reports Server (NTRS)

Shuler, Robert, Jr.

2010-01-01

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

Temperature-Adaptive Circuits on Reconfigurable Analog Arrays

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo S.; Keymeulen, Didier; Ramesham, Rajeshuni; Neff, Joseph; Katkoori, Srinivas

2006-01-01

Demonstration of a self-reconfigurable Integrated Circuit (IC) that would operate under extreme temperature (-180 C and 120 C) and radiation (300krad), without the protection of thermal controls and radiation shields. Self-Reconfigurable Electronics platform: a) Evolutionary Processor (EP) to run reconfiguration mechanism; b) Reconfigurable chip (FPGA, FPAA, etc).

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

PubMed Central

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

Metamaterial-inspired reconfigurable series-fed arrays

NASA Astrophysics Data System (ADS)

Ijaz, Bilal

One of the biggest challenges in modern day wireless communication systems is to attain agility and provide more degrees of freedom in parameters such as frequency, radiation pattern and polarization. Existing phased array antenna technology has limitations in frequency bandwidth and scan angle. So it is important to design frequency reconfigurable antenna arrays which can provide two different frequency bandwidths with a broadside radiation pattern having a lower sidelobe and reduced frequency scanning. The reconfigurable antenna array inspired by the properties of metamaterials presented here provides a solution to attain frequency agility in a wireless communication system. The adaptive change in operating frequency is attained by using RF p-i-n diodes on the antenna array. The artificially made materials having properties of negative permeability and negative permittivity have antiparallel group and phase velocities, and, in consequence of that, they support backward wave propagation. The key idea of this work is to demonstrate that the properties of metamaterial non-radiating phase shifting transmission lines can be utilized to design a series-fed antenna array to operate at two different frequency bands with a broadside radiation pattern in both configurations. In this research, first, a design of a series-fed microstrip array with composite right/left-handed transmission lines (CRLH-TLs) is proposed. To ensure that each element in the array is driven with the same voltage phase, dual-band CRLH-TLs are adopted instead of meander-line microstrip lines to provide a compact interconnect with a zero phase-constant at the frequency of operation. Next, the work is extended to design a reconfigurable series-fed antenna array with reconfigurable metamaterial interconnects, and the expressions for array factor are derived for both switching bands.

STRS Compliant FPGA Waveform Development

NASA Technical Reports Server (NTRS)

Nappier, Jennifer; Downey, Joseph; Mortensen, Dale

2008-01-01

The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. The extension of STRS to the SSP hardware will promote easier waveform reconfiguration and reuse. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. A FPGA-based transmit waveform implementation of the proposed standard interfaces on a laboratory breadboard SDR will be discussed.

Reconfigurable, Intelligently-Adaptive, Communication System, an SDR Platform

NASA Technical Reports Server (NTRS)

Roche, Rigoberto

2016-01-01

The Space Telecommunications Radio System (STRS) provides a common, consistent framework to abstract the application software from the radio platform hardware. STRS aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. The Glenn Research Center (GRC) team made a software-defined radio (SDR) platform STRS compliant by adding an STRS operating environment and a field programmable gate array (FPGA) wrapper, capable of implementing each of the platforms interfaces, as well as a test waveform to exercise those interfaces. This effort serves to provide a framework toward waveform development on an STRS compliant platform to support future space communication systems for advanced exploration missions. Validated STRS compliant applications provided tested code with extensive documentation to potentially reduce risk, cost and efforts in development of space-deployable SDRs. This paper discusses the advantages of STRS, the integration of STRS onto a Reconfigurable, Intelligently-Adaptive, Communication System (RIACS) SDR platform, the sample waveform, and wrapper development efforts. The paper emphasizes the infusion of the STRS Architecture onto the RIACS platform for potential use in next generation SDRs for advance exploration missions.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

NASA Astrophysics Data System (ADS)

Chappanda, K. N.; Ilyas, S.; Younis, M. I.

2018-05-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

On-Orbit Reconfigurable Solar Array

NASA Technical Reports Server (NTRS)

Levy, Robert K. (Inventor)

2017-01-01

In one or more embodiments, the present disclosure teaches a method for reconfiguring a solar array. The method involves providing, for the solar array, at least one string of solar cells. The method further involves deactivating at least a portion of at least one of the strings of solar cells of the solar array when power produced by the solar array reaches a maximum power allowance threshold. In addition, the method involves activating at least a portion of at least one of the strings of the solar cells in the solar array when the power produced by the solar array reaches a minimum power allowance threshold.

Soft-core processor study for node-based architectures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James

2008-09-01

Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor builtmore » out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.« less

Field Programmable Gate Array (FPGA) Respiratory Monitoring System Using a Flow Microsensor and an Accelerometer

NASA Astrophysics Data System (ADS)

Mellal, Idir; Laghrouche, Mourad; Bui, Hung Tien

2017-04-01

This paper describes a non-invasive system for respiratory monitoring using a Micro Electro Mechanical Systems (MEMS) flow sensor and an IMU (Inertial Measurement Unit) accelerometer. The designed system is intended to be wearable and used in a hospital or at home to assist people with respiratory disorders. To ensure the accuracy of our system, we proposed a calibration method based on ANN (Artificial Neural Network) to compensate the temperature drift of the silicon flow sensor. The sigmoid activation functions used in the ANN model were computed with the CORDIC (COordinate Rotation DIgital Computer) algorithm. This algorithm was also used to estimate the tilt angle in body position. The design was implemented on reconfigurable platform FPGA.

Reconfigurable Gabor Filter For Fingerprint Recognition Using FPGA Verilog

NASA Astrophysics Data System (ADS)

Rosshidi, H. T.; Hadi, A. R.

2009-06-01

This paper present the implementations of Gabor filter for fingerprint recognition using Verilog HDL. This work demonstrates the application of Gabor Filter technique to enhance the fingerprint image. The incoming signal in form of image pixel will be filter out or convolute by the Gabor filter to define the ridge and valley regions of fingerprint. This is done with the application of a real time convolve based on Field Programmable Gate Array (FPGA) to perform the convolution operation. The main characteristic of the proposed approach are the usage of memory to store the incoming image pixel and the coefficient of the Gabor filter before the convolution matrix take place. The result was the signal convoluted with the Gabor coefficient.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

2000-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing: Digital Timing Analysis Tools and Techniques. Articles in this issue include: SX and SX-A Series Devices Power Sequencing; JTAG and SXISX-AISX-S Series Devices; Analysis Techniques (i.e., notes on digital timing analysis tools and techniques); Status of the Radiation Hard reconfigurable Field Programmable Gate Array Program, Input Transition Times; Apollo Guidance Computer Logic Study; RT54SX32S Prototype Data Sets; A54SX32A - 0.22 micron/UMC Test Results; Ramtron FM1608 FRAM; and Analysis of VHDL Code and Synthesizer Output.

Mechanically Reconfigurable Single-Arm Spiral Antenna Array for Generation of Broadband Circularly Polarized Orbital Angular Momentum Vortex Waves.

PubMed

Li, Long; Zhou, Xiaoxiao

2018-03-23

In this paper, a mechanically reconfigurable circular array with single-arm spiral antennas (SASAs) is designed, fabricated, and experimentally demonstrated to generate broadband circularly polarized orbital angular momentum (OAM) vortex waves in radio frequency domain. With the symmetrical and broadband properties of single-arm spiral antennas, the vortex waves with different OAM modes can be mechanically reconfigurable generated in a wide band from 3.4 GHz to 4.7 GHz. The prototype of the circular array is proposed, conducted, and fabricated to validate the theoretical analysis. The simulated and experimental results verify that different OAM modes can be effectively generated by rotating the spiral arms of single-arm spiral antennas with corresponding degrees, which greatly simplify the feeding network. The proposed method paves a reconfigurable way to generate multiple OAM vortex waves with spin angular momentum (SAM) in radio and microwave satellite communication applications.

Reconfigurable antenna pattern verification

NASA Technical Reports Server (NTRS)

Drexler, Jerome P. (Inventor); Becker, Robert C. (Inventor); Meyers, David W. (Inventor); Muldoon, Kelly P. (Inventor)

2013-01-01

A method of verifying programmable antenna configurations is disclosed. The method comprises selecting a desired antenna configuration from a plurality of antenna configuration patterns, with the selected antenna configuration forming at least one reconfigurable antenna from reconfigurable antenna array elements. The method validates the formation of the selected antenna configuration to determine antenna performance of the at least one reconfigurable antenna.

Reconfigurable Antennas for High Data Rate Multi-beam Communication Systems

NASA Technical Reports Server (NTRS)

Bernhard, Jennifer T.; Michielssen, Eric

2005-01-01

High-speed (2-100 Mb/sec) wireless data communication - whether land- or satellite-based - faces a major challenge: high error rates caused by interference and unpredictable environments. A planar antenna system that can be reconfigured to respond to changing conditions has the potential to dramatically improve data throughput and system reliability. Moreover, new planar antenna designs that reduce array size, weight, and cost can have a significant impact on terrestrial and satellite communication system performance. This research developed new individually-reconfigurable planar antenna array elements that can be adjusted to provide multiple beams while providing increased scan angles and higher aperture efficiency than traditional diffraction-limited arrays. These new elements are microstrip spiral antennas with specialized tuning mechanisms that provide adjustable radiation patterns. We anticipate that these new elements can be used in both large and small arrays for inter-satellite communication as well as tracking of multiple mobile surface-based units. Our work has developed both theoretical descriptions as well as experimental prototypes of the antennas in both single element and array embodiments. The technical summary of the results of this work is divided into six sections: A. Cavity model for analysis and design of pattern reconfigurable antennas; B. Performance of antenna in array configurations for broadside and endfire operation; C. Performance of antenna in array configurations for beam scanning operation; D. Simulation of antennas in infinite phased arrays; E. Demonstration of antenna with commercially-available RF MEMS switches; F. Design of antenna MEMS switch combinations for direct simultaneous fabrication.

Impact: a low cost, reconfigurable, digital beamforming common module building block for next generation phased arrays

NASA Astrophysics Data System (ADS)

Paulsen, Lee; Hoffmann, Ted; Fulton, Caleb; Yeary, Mark; Saunders, Austin; Thompson, Dan; Chen, Bill; Guo, Alex; Murmann, Boris

2015-05-01

Phased array systems offer numerous advantages to the modern warfighter in multiple application spaces, including Radar, Electronic Warfare, Signals Intelligence, and Communications. However, a lack of commonality in the underlying technology base for DoD Phased Arrays has led to static systems with long development cycles, slow technology refreshes in response to emerging threats, and expensive, application-specific sub-components. The IMPACT module (Integrated Multi-use Phased Array Common Tile) is a multi-channel, reconfigurable, cost-effective beamformer that provides a common building block for multiple, disparate array applications.

Electrically reconfigurable logic array

NASA Technical Reports Server (NTRS)

Agarwal, R. K.

1982-01-01

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors

PubMed Central

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C. P.; Gelinck, Gerwin H.; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-01-01

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics. PMID:27762321

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Two dimensional analytical model for a reconfigurable field effect transistor

NASA Astrophysics Data System (ADS)

Ranjith, R.; Jayachandran, Remya; Suja, K. J.; Komaragiri, Rama S.

2018-02-01

This paper presents two-dimensional potential and current models for a reconfigurable field effect transistor (RFET). Two potential models which describe subthreshold and above-threshold channel potentials are developed by solving two-dimensional (2D) Poisson's equation. In the first potential model, 2D Poisson's equation is solved by considering constant/zero charge density in the channel region of the device to get the subthreshold potential characteristics. In the second model, accumulation charge density is considered to get above-threshold potential characteristics of the device. The proposed models are applicable for the device having lightly doped or intrinsic channel. While obtaining the mathematical model, whole body area is divided into two regions: gated region and un-gated region. The analytical models are compared with technology computer-aided design (TCAD) simulation results and are in complete agreement for different lengths of the gated regions as well as at various supply voltage levels.

Code generator for implementing dual tree complex wavelet transform on reconfigurable architectures for mobile applications

PubMed Central

Canbay, Ferhat; Levent, Vecdi Emre; Serbes, Gorkem; Ugurdag, H. Fatih; Goren, Sezer

2016-01-01

The authors aimed to develop an application for producing different architectures to implement dual tree complex wavelet transform (DTCWT) having near shift-invariance property. To obtain a low-cost and portable solution for implementing the DTCWT in multi-channel real-time applications, various embedded-system approaches are realised. For comparison, the DTCWT was implemented in C language on a personal computer and on a PIC microcontroller. However, in the former approach portability and in the latter desired speed performance properties cannot be achieved. Hence, implementation of the DTCWT on a reconfigurable platform such as field programmable gate array, which provides portable, low-cost, low-power, and high-performance computing, is considered as the most feasible solution. At first, they used the system generator DSP design tool of Xilinx for algorithm design. However, the design implemented by using such tools is not optimised in terms of area and power. To overcome all these drawbacks mentioned above, they implemented the DTCWT algorithm by using Verilog Hardware Description Language, which has its own difficulties. To overcome these difficulties, simplify the usage of proposed algorithms and the adaptation procedures, a code generator program that can produce different architectures is proposed. PMID:27733925

Code generator for implementing dual tree complex wavelet transform on reconfigurable architectures for mobile applications.

PubMed

Canbay, Ferhat; Levent, Vecdi Emre; Serbes, Gorkem; Ugurdag, H Fatih; Goren, Sezer; Aydin, Nizamettin

2016-09-01

The authors aimed to develop an application for producing different architectures to implement dual tree complex wavelet transform (DTCWT) having near shift-invariance property. To obtain a low-cost and portable solution for implementing the DTCWT in multi-channel real-time applications, various embedded-system approaches are realised. For comparison, the DTCWT was implemented in C language on a personal computer and on a PIC microcontroller. However, in the former approach portability and in the latter desired speed performance properties cannot be achieved. Hence, implementation of the DTCWT on a reconfigurable platform such as field programmable gate array, which provides portable, low-cost, low-power, and high-performance computing, is considered as the most feasible solution. At first, they used the system generator DSP design tool of Xilinx for algorithm design. However, the design implemented by using such tools is not optimised in terms of area and power. To overcome all these drawbacks mentioned above, they implemented the DTCWT algorithm by using Verilog Hardware Description Language, which has its own difficulties. To overcome these difficulties, simplify the usage of proposed algorithms and the adaptation procedures, a code generator program that can produce different architectures is proposed.

Reconfigurable, Intelligently-Adaptive, Communication System, an SDR Platform

NASA Technical Reports Server (NTRS)

Roche, Rigoberto J.; Shalkhauser, Mary Jo; Hickey, Joseph P.; Briones, Janette C.

2016-01-01

The Space Telecommunications Radio System (STRS) provides a common, consistent framework to abstract the application software from the radio platform hardware. STRS aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. The NASA Glenn Research Center (GRC) team made a software defined radio (SDR) platform STRS compliant by adding an STRS operating environment and a field programmable gate array (FPGA) wrapper, capable of implementing each of the platforms interfaces, as well as a test waveform to exercise those interfaces. This effort serves to provide a framework toward waveform development onto an STRS compliant platform to support future space communication systems for advanced exploration missions. The use of validated STRS compliant applications provides tested code with extensive documentation to potentially reduce risk, cost and e ort in development of space-deployable SDRs. This paper discusses the advantages of STRS, the integration of STRS onto a Reconfigurable, Intelligently-Adaptive, Communication System (RIACS) SDR platform, and the test waveform and wrapper development e orts. The paper emphasizes the infusion of the STRS Architecture onto the RIACS platform for potential use in next generation flight system SDRs for advanced exploration missions.

Remote hardware-reconfigurable robotic camera

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

2001-10-01

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

Charge Neutralization Drives the Shape Reconfiguration of DNA Nanotubes.

PubMed

Liu, Pi; Zhao, Yan; Liu, Xiaoguo; Sun, Jixue; Xu, Dede; Li, Yang; Li, Qian; Wang, Lihua; Yang, Sichun; Fan, Chunhai; Lin, Jianping

2018-05-04

Reconfiguration of membrane protein channels for gated transport is highly regulated under physiological conditions. However, a mechanistic understanding of such channels remains challenging owing to the difficulty in probing subtle gating-associated structural changes. Herein, we show that charge neutralization can drive the shape reconfiguration of a biomimetic 6-helix bundle DNA nanotube (6HB). Specifically, 6HB adopts a compact state when its charge is neutralized by Mg 2+ ; whereas Na + switches it to the expanded state, as revealed by MD simulations, small-angle X-ray scattering (SAXS), and FRET characterization. Furthermore, partial neutralization of the DNA backbone charges by chemical modification renders 6HB compact and insensitive to ions, suggesting an interplay between electrostatic and hydrophobic forces in the channels. This system provides a platform for understanding the structure-function relationship of biological channels and designing rules for the shape control of DNA nanostructures in biomedical applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ambipolar Barristors for Reconfigurable Logic Circuits.

PubMed

Liu, Yuan; Zhang, Guo; Zhou, Hailong; Li, Zheng; Cheng, Rui; Xu, Yang; Gambin, Vincent; Huang, Yu; Duan, Xiangfeng

2017-03-08

Vertical heterostructures based on graphene have emerged as a unique architecture for novel electronic devices with unusual characteristics. Here we report a new design of vertical ambipolar barristors based on metal-graphene-silicon-graphene sandwich structure, using the bottom graphene as a gate-tunable "active contact", the top graphene as an adaptable Ohmic contact, and the low doping thin silicon layer as the switchable channel. Importantly, with finite density of states and weak screening effect of graphene, we demonstrate, for the first time, that both the carrier concentration and majority carrier type in the sandwiched silicon can be readily modulated by gate potential penetrating through graphene. It can thus enable a new type of ambipolar barristors with an ON-OFF ratio exceeding 10 3 . Significantly, these ambipolar barristors can be flexibly configured into either p-type or n-type transistors and used to create integrated circuits with reconfigurable logic functions. This unconventional device structure and ambipolar reconfigurable characteristics can open up exciting opportunities in future electronics based on graphene or two-dimensional van der Waals heterostructures.

Flexible and re-configurable optical three-input XOR logic gate of phase-modulated signals with multicast functionality for potential application in optical physical-layer network coding.

PubMed

Lu, Guo-Wei; Qin, Jun; Wang, Hongxiang; Ji, XuYuefeng; Sharif, Gazi Mohammad; Yamaguchi, Shigeru

2016-02-08

Optical logic gate, especially exclusive-or (XOR) gate, plays important role in accomplishing photonic computing and various network functionalities in future optical networks. On the other hand, optical multicast is another indispensable functionality to efficiently deliver information in optical networks. In this paper, for the first time, we propose and experimentally demonstrate a flexible optical three-input XOR gate scheme for multiple input phase-modulated signals with a 1-to-2 multicast functionality for each XOR operation using four-wave mixing (FWM) effect in single piece of highly-nonlinear fiber (HNLF). Through FWM in HNLF, all of the possible XOR operations among input signals could be simultaneously realized by sharing a single piece of HNLF. By selecting the obtained XOR components using a followed wavelength selective component, the number of XOR gates and the participant light in XOR operations could be flexibly configured. The re-configurability of the proposed XOR gate and the function integration of the optical logic gate and multicast in single device offer the flexibility in network design and improve the network efficiency. We experimentally demonstrate flexible 3-input XOR gate for four 10-Gbaud binary phase-shift keying signals with a multicast scale of 2. Error-free operations for the obtained XOR results are achieved. Potential application of the integrated XOR and multicast function in network coding is also discussed.

Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

NASA Astrophysics Data System (ADS)

Chen, Paul; Butts, Mike; Budlong, Brad; Wasson, Paul

2008-04-01

This paper introduces a novel computing architecture that can be reconfigured in real time to adapt on demand to multi-mode sensor platforms' dynamic computational and functional requirements. This 1 teraOPS reconfigurable Massively Parallel Processor Array (MPPA) has 336 32-bit processors. The programmable 32-bit communication fabric provides streamlined inter-processor connections with deterministically high performance. Software programmability, scalability, ease of use, and fast reconfiguration time (ranging from microseconds to milliseconds) are the most significant advantages over FPGAs and DSPs. This paper introduces the MPPA architecture, its programming model, and methods of reconfigurability. An MPPA platform for reconfigurable computing is based on a structural object programming model. Objects are software programs running concurrently on hundreds of 32-bit RISC processors and memories. They exchange data and control through a network of self-synchronizing channels. A common application design pattern on this platform, called a work farm, is a parallel set of worker objects, with one input and one output stream. Statically configured work farms with homogeneous and heterogeneous sets of workers have been used in video compression and decompression, network processing, and graphics applications.

Study of the characteristics of reconfigurable plasma antenna array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alias, Nur Salihah; Dagang, Ahmad Nazri; Ali, Mohd Tarmizi

This paper presents a design and simulation of a reconfigurable array of plasma antenna. The plasma column is used as radiating elements instead of metal to create an antenna. The advantages of the plasma antenna over the conventional antenna are its possible to change the operating parameters, such as the working pressure, input power, radius of the discharge tube, resonant frequency, and length of the plasma column. In addition, plasma antenna can be reconfigurable with respect to shape, frequency and radiation parameters in a very short time. The plasma discharge tube was designed with a length of 200 mm, the radiusmore » of the plasma column was 2.5 mm and the coupling sleeve was connected to the SMA as the ground. This simulation was performed by using the simulation software Computer Simulation Technology (CST). The frequency is set in the range of 1 GHz to 10 GHz. The performance of the designed antenna was analyzed in term of return loss, gain and radiation pattern. For reconfigurable plasma antenna array, it shows that the gain is increase when the number of antenna element is increase. The combination of the discharge tube and metal rod as an antenna array has been done, and the result shows that an array with the plasma element can achieve higher gain.« less

Adaptive and mobile ground sensor array.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holzrichter, Michael Warren; O'Rourke, William T.; Zenner, Jennifer

The goal of this LDRD was to demonstrate the use of robotic vehicles for deploying and autonomously reconfiguring seismic and acoustic sensor arrays with high (centimeter) accuracy to obtain enhancement of our capability to locate and characterize remote targets. The capability to accurately place sensors and then retrieve and reconfigure them allows sensors to be placed in phased arrays in an initial monitoring configuration and then to be reconfigured in an array tuned to the specific frequencies and directions of the selected target. This report reviews the findings and accomplishments achieved during this three-year project. This project successfully demonstrated autonomousmore » deployment and retrieval of a payload package with an accuracy of a few centimeters using differential global positioning system (GPS) signals. It developed an autonomous, multisensor, temporally aligned, radio-frequency communication and signal processing capability, and an array optimization algorithm, which was implemented on a digital signal processor (DSP). Additionally, the project converted the existing single-threaded, monolithic robotic vehicle control code into a multi-threaded, modular control architecture that enhances the reuse of control code in future projects.« less

Acoustic Wave Guiding by Reconfigurable Tessellated Arrays

NASA Astrophysics Data System (ADS)

Zou, Chengzhe; Lynd, Danielle T.; Harne, Ryan L.

2018-01-01

The reconfiguration of origami tessellations is a prime vehicle to harness for adapting system properties governed by a structural form. While the knowledge of mechanical property changes associated with origami tessellation folding has been extensively built up, the opportunities to integrate other physics into a framework of tessellated, adaptive structures remain to be fully exploited. Acoustics appears to be a prime domain to marry with origami science. Specifically, deep technical analogies are revealed between wave-guiding properties achieved via digital methods that virtually reposition array elements and the actual repositioning of facets by folding origami-inspired tessellations. Here we capitalize on this analogy to investigate acoustic arrays established upon facet layouts of origami-inspired tessellations. We show that a concept of reconfigurable tessellated arrays may guide waves more effectively than traditional digitally phased arrays using fewer transducer elements. Moreover, we show that the refinement of tessellated arrays trends to the ideal case of classical wave radiators or receivers grounded in principles of geometrical acoustics. By linear wave physics shared among myriad scientific disciplines and across orders of magnitude in length scale, these discoveries may cultivate numerous opportunities for wave-guiding adaptive structures inspired by low-dimensional origami tessellations.

Reconfigurable Array Antenna Using Microelectromechanical Systems (MEMS) Actuators

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Chun, Donghoon; Katehi, Linda P. B.

2001-01-01

The paper demonstrates a patch antenna integrated with a novel microelectromechanical systems (MEMS) actuator for reconfiguring the operating frequency. Experimental results demonstrate that the center frequency can be reconfigured by as much as 1.6 percent of the nominal operating frequency at K-Band In addition, a novel on-wafer antenna pattern measurement technique is demonstrated.

Reconfigurable electro-optical directed-logic circuit using carrier-depletion micro-ring resonators.

PubMed

Qiu, Ciyuan; Gao, Weilu; Soref, Richard; Robinson, Jacob T; Xu, Qianfan

2014-12-15

Here we demonstrate a reconfigurable electro-optical directed-logic circuit based on a regular array of integrated optical switches. Each 1×1 optical switch consists of a micro-ring resonator with an embedded lateral p-n junction and a micro-heater. We achieve high-speed on-off switching by applying electrical logic signals to the p-n junction. We can configure the operation mode of each switch by thermal tuning the resonance wavelength. The result is an integrated optical circuit that can be reconfigured to perform any combinational logic operation. As a proof-of-principle, we fabricated a multi-spectral directed-logic circuit based on a fourfold array of switches and showed that this circuit can be reconfigured to perform arbitrary two-input logic functions with speeds up to 3  GB/s.

Wideband Monolithic Tile for Reconfigurable Phased Arrays

DTIC Science & Technology

2017-03-01

has been developed for Reconfigurable Phased Array applications. Low loss and high isolation interconnection of switches within the radiating...there is no ground to connect shunt elements to. An integral part of the design was bias control. Mesa resistors are used for biasing. MIM...highest in resistance had the best performance over bandwidth because of reduced capacitive loading of the “off” arms of the Quad Switch on the central

A reconfigurable NAND/NOR genetic logic gate

PubMed Central

2012-01-01

Background Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. Results We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. Conclusions We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications. PMID:22989145

A reconfigurable NAND/NOR genetic logic gate.

PubMed

Goñi-Moreno, Angel; Amos, Martyn

2012-09-18

Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.

Pre-Hardware Optimization of Spacecraft Image Processing Algorithms and Hardware Implementation

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Petrick, David J.; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Day, John H. (Technical Monitor)

2002-01-01

Spacecraft telemetry rates and telemetry product complexity have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image data processing and color picture generation application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The proposed solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms, and reconfigurable computing hardware (RC) technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processors (DSP). It has been shown that this approach can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft.

Collision management utilizing CCD and remote sensing technology

NASA Technical Reports Server (NTRS)

Mcdaniel, Harvey E., Jr.

1995-01-01

With the threat of damage to aerospace systems (space station, shuttle, hypersonic a/c, solar power satellites, loss of life, etc.) from collision with debris (manmade/artificial), there exists an opportunity for the design of a novel system (collision avoidance) to be incorporated into the overall design. While incorporating techniques from ccd and remote sensing technologies, an integrated system utilized in the infrared/visible spectrum for detection, tracking, localization, and maneuvering from doppler shift measurements is achievable. Other analysis such as impact assessment, station keeping, chemical, and optical tracking/fire control solutions are possible through this system. Utilizing modified field programmable gated arrays (software reconfiguring the hardware) the mission and mission effectiveness can be varied. This paper outlines the theoretical operation of a prototype system as it applies to collision avoidance (to be followed up by research).

A Frequency Agile, Self-Adaptive Serial Link on Xilinx FPGAs

NASA Astrophysics Data System (ADS)

Aloisio, A.; Giordano, R.; Izzo, V.; Perrella, S.

2015-06-01

In this paper, we focused on the GTX transceiver modules of Xilinx Kintex 7 field-programmable gate arrays (FPGAs), which provide high bandwidth, low jitter on the recovered clock, and an equalization system on the transmitter and the receiver. We present a frequency agile, auto-adaptive serial link. The link is able to take care of the reconfiguration of the GTX parameters in order to fully benefit from the available link bandwidth, by setting the highest line rate. It is designed around an FPGA-embedded microprocessor, which drives the programmable ports of the GTX in order to control the quality of the received data and to easily calculate the bit-error rate in each sampling point of the eye diagram. We present the self-adaptive link project, the description of the test system, and the main results.

Interlaced photoacoustic and ultrasound imaging system with real-time coregistration for ovarian tissue characterization

NASA Astrophysics Data System (ADS)

Alqasemi, Umar; Li, Hai; Yuan, Guangqian; Kumavor, Patrick; Zanganeh, Saeid; Zhu, Quing

2014-07-01

Coregistered ultrasound (US) and photoacoustic imaging are emerging techniques for mapping the echogenic anatomical structure of tissue and its corresponding optical absorption. We report a 128-channel imaging system with real-time coregistration of the two modalities, which provides up to 15 coregistered frames per second limited by the laser pulse repetition rate. In addition, the system integrates a compact transvaginal imaging probe with a custom-designed fiber optic assembly for in vivo detection and characterization of human ovarian tissue. We present the coregistered US and photoacoustic imaging system structure, the optimal design of the PC interfacing software, and the reconfigurable field programmable gate array operation and optimization. Phantom experiments of system lateral resolution and axial sensitivity evaluation, examples of the real-time scanning of a tumor-bearing mouse, and ex vivo human ovaries studies are demonstrated.

Design techniques for a stable operation of cryogenic field-programmable gate arrays.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Design techniques for a stable operation of cryogenic field-programmable gate arrays

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Reconfigurable OR and XOR logic gates based on dual responsive on-off-on micromotors.

PubMed

Dong, Yonggang; Liu, Mei; Zhang, Hui; Dong, Bin

2016-04-21

In this study, we report a hemisphere-like micromotor. Intriguingly, the micromotor exhibits controllable on-off-on motion, which can be actuated by two different external stimuli (UV and NH3). Moreover, the moving direction of the micromotor can be manipulated by the direction in which UV and NH3 are applied. As a result, the motion accelerates when both stimuli are applied in the same direction and decelerates when the application directions are opposite to each other. More interestingly, the dual stimuli responsive micromotor can be utilized as a reconfigurable logic gate with UV and NH3 as the inputs and the motion of the micromotor as the output. By controlling the direction of the external stimuli, OR and XOR dual logic functions can be realized.

FPGA-Based Reconfigurable Processor for Ultrafast Interlaced Ultrasound and Photoacoustic Imaging

PubMed Central

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2016-01-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models. PMID:22828830

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

PubMed

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2012-07-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array.

PubMed

Zhou, Ya-Xiong; Li, Yi; Su, Yu-Ting; Wang, Zhuo-Rui; Shih, Ling-Yi; Chang, Ting-Chang; Chang, Kuan-Chang; Long, Shi-Bing; Sze, Simon M; Miao, Xiang-Shui

2017-05-25

Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO 2 -based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

A reconfigurable cryogenic platform for the classical control of quantum processors

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

A reconfigurable cryogenic platform for the classical control of quantum processors.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

HALO: a reconfigurable image enhancement and multisensor fusion system

NASA Astrophysics Data System (ADS)

Wu, F.; Hickman, D. L.; Parker, Steve J.

2014-06-01

Contemporary high definition (HD) cameras and affordable infrared (IR) imagers are set to dramatically improve the effectiveness of security, surveillance and military vision systems. However, the quality of imagery is often compromised by camera shake, or poor scene visibility due to inadequate illumination or bad atmospheric conditions. A versatile vision processing system called HALO™ is presented that can address these issues, by providing flexible image processing functionality on a low size, weight and power (SWaP) platform. Example processing functions include video distortion correction, stabilisation, multi-sensor fusion and image contrast enhancement (ICE). The system is based around an all-programmable system-on-a-chip (SoC), which combines the computational power of a field-programmable gate array (FPGA) with the flexibility of a CPU. The FPGA accelerates computationally intensive real-time processes, whereas the CPU provides management and decision making functions that can automatically reconfigure the platform based on user input and scene content. These capabilities enable a HALO™ equipped reconnaissance or surveillance system to operate in poor visibility, providing potentially critical operational advantages in visually complex and challenging usage scenarios. The choice of an FPGA based SoC is discussed, and the HALO™ architecture and its implementation are described. The capabilities of image distortion correction, stabilisation, fusion and ICE are illustrated using laboratory and trials data.

Leveraging FPGAs for Accelerating Short Read Alignment.

PubMed

Arram, James; Kaplan, Thomas; Luk, Wayne; Jiang, Peiyong

2017-01-01

One of the key challenges facing genomics today is how to efficiently analyze the massive amounts of data produced by next-generation sequencing platforms. With general-purpose computing systems struggling to address this challenge, specialized processors such as the Field-Programmable Gate Array (FPGA) are receiving growing interest. The means by which to leverage this technology for accelerating genomic data analysis is however largely unexplored. In this paper, we present a runtime reconfigurable architecture for accelerating short read alignment using FPGAs. This architecture exploits the reconfigurability of FPGAs to allow the development of fast yet flexible alignment designs. We apply this architecture to develop an alignment design which supports exact and approximate alignment with up to two mismatches. Our design is based on the FM-index, with optimizations to improve the alignment performance. In particular, the n-step FM-index, index oversampling, a seed-and-compare stage, and bi-directional backtracking are included. Our design is implemented and evaluated on a 1U Maxeler MPC-X2000 dataflow node with eight Altera Stratix-V FPGAs. Measurements show that our design is 28 times faster than Bowtie2 running with 16 threads on dual Intel Xeon E5-2640 CPUs, and nine times faster than Soap3-dp running on an NVIDIA Tesla C2070 GPU.

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

NASA Astrophysics Data System (ADS)

Hamada, Tsuyoshi; Fukushige, Toshiyuki; Kawai, Atsushi; Makino, Junichiro

2000-10-01

We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and ``traditional'' GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydro\\-dynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

Ultrasound beam characteristics of a symmetric nodal origami based array

NASA Astrophysics Data System (ADS)

Bilgunde, Prathamesh N.; Bond, Leonard J.

2018-04-01

Origami-the ancient art of paper folding-is being explored in acoustics for effective focusing of sound. In this short communication, we present a numerical investigation of beam characteristics for an origami based ultrasound array. A spatial re-configuration of array elements is performed based upon the symmetric nodal origami. The effect of fold angle on the ultrasound beam is evaluated using frequency domain and transient finite element analysis. It was found that increase in the fold angle reduces near field length by 58% and also doubles the beam intensity as compared to the linear array. Transient analysis also indicated 80% reduction in the -6dB beam width, which can improve the lateral resolution of phased array. Such a spatially re-configurable array could potentially be used in the future to reduce the cost of electronics in the phased array instrumentation.

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

A reconfigurable computing platform for plume tracking with mobile sensor networks

NASA Astrophysics Data System (ADS)

Kim, Byung Hwa; D'Souza, Colin; Voyles, Richard M.; Hesch, Joel; Roumeliotis, Stergios I.

2006-05-01

Much work has been undertaken recently toward the development of low-power, high-performance sensor networks. There are many static remote sensing applications for which this is appropriate. The focus of this development effort is applications that require higher performance computation, but still involve severe constraints on power and other resources. Toward that end, we are developing a reconfigurable computing platform for miniature robotic and human-deployed sensor systems composed of several mobile nodes. The system provides static and dynamic reconfigurability for both software and hardware by the combination of CPU (central processing unit) and FPGA (field-programmable gate array) allowing on-the-fly reprogrammability. Static reconfigurability of the hardware manifests itself in the form of a "morphing bus" architecture that permits the modular connection of various sensors with no bus interface logic. Dynamic hardware reconfigurability provides for the reallocation of hardware resources at run-time as the mobile, resource-constrained nodes encounter unknown environmental conditions that render various sensors ineffective. This computing platform will be described in the context of work on chemical/biological/radiological plume tracking using a distributed team of mobile sensors. The objective for a dispersed team of ground and/or aerial autonomous vehicles (or hand-carried sensors) is to acquire measurements of the concentration of the chemical agent from optimal locations and estimate its source and spread. This requires appropriate distribution, coordination and communication within the team members across a potentially unknown environment. The key problem is to determine the parameters of the distribution of the harmful agent so as to use these values for determining its source and predicting its spread. The accuracy and convergence rate of this estimation process depend not only on the number and accuracy of the sensor measurements but also on their spatial distribution over time (the sampling strategy). For the safety of a human-deployed distribution of sensors, optimized trajectories to minimize human exposure are also of importance. The systems described in this paper are currently being developed. Parts of the system are already in existence and some results from these are described.

Invited Article: Digital beam-forming imaging riometer systems

NASA Astrophysics Data System (ADS)

Honary, Farideh; Marple, Steve R.; Barratt, Keith; Chapman, Peter; Grill, Martin; Nielsen, Erling

2011-03-01

The design and operation of a new generation of digital imaging riometer systems developed by Lancaster University are presented. In the heart of the digital imaging riometer is a field-programmable gate array (FPGA), which is used for the digital signal processing and digital beam forming, completely replacing the analog Butler matrices which have been used in previous designs. The reconfigurable nature of the FPGA has been exploited to produce tools for remote system testing and diagnosis which have proven extremely useful for operation in remote locations such as the Arctic and Antarctic. Different FPGA programs enable different instrument configurations, including a 4 × 4 antenna filled array (producing 4 × 4 beams), an 8 × 8 antenna filled array (producing 7 × 7 beams), and a Mills cross system utilizing 63 antennas producing 556 usable beams. The concept of using a Mills cross antenna array for riometry has been successfully demonstrated for the first time. The digital beam forming has been validated by comparing the received signal power from cosmic radio sources with results predicted from the theoretical beam radiation pattern. The performances of four digital imaging riometer systems are compared against each other and a traditional imaging riometer utilizing analog Butler matrices. The comparison shows that digital imaging riometer systems, with independent receivers for each antenna, can obtain much better measurement precision for filled arrays or much higher spatial resolution for the Mills cross configuration when compared to existing imaging riometer systems.

Use of Patterned CNT Arrays for Display Purposes

NASA Technical Reports Server (NTRS)

Delzeit, Lance D. (Inventor); Schipper, John F. (Inventor)

2009-01-01

Method and system for providing a dynamically reconfigurable display having nanometer-scale resolution, using a patterned array of multi-wall carbon nanotube (MWCNT) clusters. A diode, phosphor or other light source on each MWCNT cluster is independently activated, and different color light sources (e.g., red, green, blue, grey scale, infrared) can be mixed if desired. Resolution is estimated to be 40-100 nm, and reconfiguration time for each MWCNT cluster is no greater than one microsecond.

Simultaneous control of magnetic topologies for reconfigurable vortex arrays

DOE PAGES

Im, Mi-Young; Fischer, Peter; Han, Hee-Sung; ...

2017-02-10

The topological spin textures in magnetic vortices in confined magnetic elements offer a platform for understanding the fundamental physics of nanoscale spin behavior and the potential of harnessing their unique spin structures for advanced magnetic technologies. For magnetic vortices to be practical, an effective reconfigurability of the two topologies of magnetic vortices, that is, the circularity and the polarity, is an essential prerequisite. The reconfiguration issue is highly relevant to the question of whether both circularity and polarity are reliably and efficiently controllable. In this work, we report the first direct observation of simultaneous control of both circularity and polaritymore » by the sole application of an in-plane magnetic field to arrays of asymmetrically shaped permalloy disks. Our investigation demonstrates that a high degree of reliability for control of both topologies can be achieved by tailoring the geometry of the disk arrays. We also propose a new approach to control the vortex structures by manipulating the effect of the stray field on the dynamics of vortex creation. The current study is expected to facilitate complete and effective reconfiguration of magnetic vortex structures, thereby enhancing the prospects for technological applications of magnetic vortices.« less

Simultaneous control of magnetic topologies for reconfigurable vortex arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Im, Mi-Young; Fischer, Peter; Han, Hee-Sung

The topological spin textures in magnetic vortices in confined magnetic elements offer a platform for understanding the fundamental physics of nanoscale spin behavior and the potential of harnessing their unique spin structures for advanced magnetic technologies. For magnetic vortices to be practical, an effective reconfigurability of the two topologies of magnetic vortices, that is, the circularity and the polarity, is an essential prerequisite. The reconfiguration issue is highly relevant to the question of whether both circularity and polarity are reliably and efficiently controllable. In this work, we report the first direct observation of simultaneous control of both circularity and polaritymore » by the sole application of an in-plane magnetic field to arrays of asymmetrically shaped permalloy disks. Our investigation demonstrates that a high degree of reliability for control of both topologies can be achieved by tailoring the geometry of the disk arrays. We also propose a new approach to control the vortex structures by manipulating the effect of the stray field on the dynamics of vortex creation. The current study is expected to facilitate complete and effective reconfiguration of magnetic vortex structures, thereby enhancing the prospects for technological applications of magnetic vortices.« less

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for the Federal fiscal year of 2010 are: Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments, Modeling of Radiation Effects on Electronics, Radiation Hardened High Performance Processors (HPP), and and Reconfigurable Computing.

ALI (Autonomous Lunar Investigator): Revolutionary Approach to Exploring the Moon with Addressable Reconfigurable Technology

NASA Technical Reports Server (NTRS)

Clark, P. E.; Curtis, S. A.; Rilee, M. L.; Floyd, S. R.

2005-01-01

Addressable Reconfigurable Technology (ART) based structures: Mission Concepts based on Addressable Reconfigurable Technology (ART), originally studied for future ANTS (Autonomous Nanotechnology Swarm) Space Architectures, are now being developed as rovers for nearer term use in lunar and planetary surface exploration. The architecture is based on the reconfigurable tetrahedron as a building block. Tetrahedra are combined to form space-filling networks, shaped for the required function. Basic structural components are highly modular, addressable arrays of robust nodes (tetrahedral apices) from which highly reconfigurable struts (tetrahedral edges), acting as supports or tethers, are efficiently reversibly deployed/stowed, transforming and reshaping the structures as required.

A fast adaptive convex hull algorithm on two-dimensional processor arrays with a reconfigurable BUS system

NASA Technical Reports Server (NTRS)

Olariu, S.; Schwing, J.; Zhang, J.

1991-01-01

A bus system that can change dynamically to suit computational needs is referred to as reconfigurable. We present a fast adaptive convex hull algorithm on a two-dimensional processor array with a reconfigurable bus system (2-D PARBS, for short). Specifically, we show that computing the convex hull of a planar set of n points taken O(log n/log m) time on a 2-D PARBS of size mn x n with 3 less than or equal to m less than or equal to n. Our result implies that the convex hull of n points in the plane can be computed in O(1) time in a 2-D PARBS of size n(exp 1.5) x n.

Adaptive reconfigurable V-BLAST type equalizer for cognitive MIMO-OFDM radios

NASA Astrophysics Data System (ADS)

Ozden, Mehmet Tahir

2015-12-01

An adaptive channel shortening equalizer design for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) radio receivers is considered in this presentation. The proposed receiver has desirable features for cognitive and software defined radio implementations. It consists of two sections: MIMO decision feedback equalizer (MIMO-DFE) and adaptive multiple Viterbi detection. In MIMO-DFE section, a complete modified Gram-Schmidt orthogonalization of multichannel input data is accomplished using sequential processing multichannel Givens lattice stages, so that a Vertical Bell Laboratories Layered Space Time (V-BLAST) type MIMO-DFE is realized at the front-end section of the channel shortening equalizer. Matrix operations, a major bottleneck for receiver operations, are accordingly avoided, and only scalar operations are used. A highly modular and regular radio receiver architecture that has a suitable structure for digital signal processing (DSP) chip and field programable gate array (FPGA) implementations, which are important for software defined radio realizations, is achieved. The MIMO-DFE section of the proposed receiver can also be reconfigured for spectrum sensing and positioning functions, which are important tasks for cognitive radio applications. In connection with adaptive multiple Viterbi detection section, a systolic array implementation for each channel is performed so that a receiver architecture with high computational concurrency is attained. The total computational complexity is given in terms of equalizer and desired response filter lengths, alphabet size, and number of antennas. The performance of the proposed receiver is presented for two-channel case by means of mean squared error (MSE) and probability of error evaluations, which are conducted for time-invariant and time-variant channel conditions, orthogonal and nonorthogonal transmissions, and two different modulation schemes.

Hardware Architecture Study for NASA's Space Software Defined Radios

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

2008-01-01

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Hardware for dynamic quantum computing.

PubMed

Ryan, Colm A; Johnson, Blake R; Ristè, Diego; Donovan, Brian; Ohki, Thomas A

2017-10-01

We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

Radiation Effects on Current Field Programmable Technologies

NASA Technical Reports Server (NTRS)

Katz, R.; LaBel, K.; Wang, J. J.; Cronquist, B.; Koga, R.; Penzin, S.; Swift, G.

1997-01-01

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Design of the Wind Tunnel Model Communication Controller Board. Degree awarded by Christopher Newport Univ. on Dec. 1998

NASA Technical Reports Server (NTRS)

Wilson, William C.

1999-01-01

The NASA Langley Research Center's Wind Tunnel Reinvestment project plans to shrink the existing data acquisition electronics to fit inside a wind tunnel model. Space limitations within a model necessitate a distributed system of Application Specific Integrated Circuits (ASICs) rather than a centralized system based on PC boards. This thesis will focus on the design of the prototype of the communication Controller board. A portion of the communication Controller board is to be used as the basis of an ASIC design. The communication Controller board will communicate between the internal model modules and the external data acquisition computer. This board is based around an Field Programmable Gate Array (FPGA), to allow for reconfigurability. In addition to the FPGA, this board contains buffer Random Access Memory (RAM), configuration memory (EEPROM), drivers for the communications ports, and passive components.

Experiments with arbitrary networks in time-multiplexed delay systems

NASA Astrophysics Data System (ADS)

Hart, Joseph D.; Schmadel, Don C.; Murphy, Thomas E.; Roy, Rajarshi

2017-12-01

We report a new experimental approach using an optoelectronic feedback loop to investigate the dynamics of oscillators coupled on large complex networks with arbitrary topology. Our implementation is based on a single optoelectronic feedback loop with time delays. We use the space-time interpretation of systems with time delay to create large networks of coupled maps. Others have performed similar experiments using high-pass filters to implement the coupling; this restricts the network topology to the coupling of only a few nearest neighbors. In our experiment, the time delays and coupling are implemented on a field-programmable gate array, allowing the creation of networks with arbitrary coupling topology. This system has many advantages: the network nodes are truly identical, the network is easily reconfigurable, and the network dynamics occur at high speeds. We use this system to study cluster synchronization and chimera states in both small and large networks of different topologies.

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

2008-01-01

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Implementation of a Multichannel Serial Data Streaming Algorithm using the Xilinx Serial RapidIO Solution

NASA Technical Reports Server (NTRS)

Doxley, Charles A.

2016-01-01

In the current world of applications that use reconfigurable technology implemented on field programmable gate arrays (FPGAs), there is a need for flexible architectures that can grow as the systems evolve. A project has limited resources and a fixed set of requirements that development efforts are tasked to meet. Designers must develop robust solutions that practically meet the current customer demands and also have the ability to grow for future performance. This paper describes the development of a high speed serial data streaming algorithm that allows for transmission of multiple data channels over a single serial link. The technique has the ability to change to meet new applications developed for future design considerations. This approach uses the Xilinx Serial RapidIO LOGICORE Solution to implement a flexible infrastructure to meet the current project requirements with the ability to adapt future system designs.

Stego on FPGA: An IWT Approach

PubMed Central

Ramalingam, Balakrishnan

2014-01-01

A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8 × 8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk's verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA). PMID:24723794

Petri net-based dependability modeling methodology for reconfigurable field programmable gate arrays

NASA Astrophysics Data System (ADS)

Graczyk, Rafał; Orleański, Piotr; Poźniak, Krzysztof

2015-09-01

Dependability modeling is an important issue for aerospace and space equipment designers. From system level perspective, one has to choose from multitude of possible architectures, redundancy levels, component combinations in a way to meet desired properties and dependability and finally fit within required cost and time budgets. Modeling of such systems is getting harder as its levels of complexity grow together with demand for more functional and flexible, yet more available systems that govern more and more crucial parts of our civilization's infrastructure (aerospace transport systems, telecommunications, exploration probes). In this article promising method of modeling complex systems using Petri networks is introduced in context of qualitative and quantitative dependability analysis. This method, although with some limitation and drawback offer still convenient visual formal method of describing system behavior on different levels (functional, timing, random events) and offers straight correspondence to underlying mathematical engine, perfect for simulations and engineering support.

A FPGA Implementation of the CAR-FAC Cochlear Model.

PubMed

Xu, Ying; Thakur, Chetan S; Singh, Ram K; Hamilton, Tara Julia; Wang, Runchun M; van Schaik, André

2018-01-01

This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

A FPGA Implementation of the CAR-FAC Cochlear Model

PubMed Central

Xu, Ying; Thakur, Chetan S.; Singh, Ram K.; Hamilton, Tara Julia; Wang, Runchun M.; van Schaik, André

2018-01-01

This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on. PMID:29692700

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

Design of an FPGA-based electronic flow regulator (EFR) for spacecraft propulsion system

NASA Astrophysics Data System (ADS)

Manikandan, J.; Jayaraman, M.; Jayachandran, M.

2011-02-01

This paper describes a scheme for electronically regulating the flow of propellant to the thruster from a high-pressure storage tank used in spacecraft application. Precise flow delivery of propellant to thrusters ensures propulsion system operation at best efficiency by maximizing the propellant and power utilization for the mission. The proposed field programmable gate array (FPGA) based electronic flow regulator (EFR) is used to ensure precise flow of propellant to the thrusters from a high-pressure storage tank used in spacecraft application. This paper presents hardware and software design of electronic flow regulator and implementation of the regulation logic onto an FPGA.Motivation for proposed FPGA-based electronic flow regulation is on the disadvantages of conventional approach of using analog circuits. Digital flow regulation overcomes the analog equivalent as digital circuits are highly flexible, are not much affected due to noise, accurate performance is repeatable, interface is easier to computers, storing facilities are possible and finally failure rate of digital circuits is less. FPGA has certain advantages over ASIC and microprocessor/micro-controller that motivated us to opt for FPGA-based electronic flow regulator. Also the control algorithm being software, it is well modifiable without changing the hardware. This scheme is simple enough to adopt for a wide range of applications, where the flow is to be regulated for efficient operation.The proposed scheme is based on a space-qualified re-configurable field programmable gate arrays (FPGA) and hybrid micro circuit (HMC). A graphical user interface (GUI) based application software is also developed for debugging, monitoring and controlling the electronic flow regulator from PC COM port.

Electromagnetic energy coupling mechanism with matrix architecture control

NASA Technical Reports Server (NTRS)

Hughes, Eli (Inventor); Knowles, Gareth (Inventor)

2006-01-01

The present invention relates generally to reconfigurable, solid-state matrix arrays comprising multiple rows and columns of reconfigurable secondary mechanisms that are independently tuned. Specifically, the invention relates to reconfigurable devices comprising multiple, solid-state mechanisms characterized by at least one voltage-varied parameter disposed within a flexible, multi-laminate film, which are suitable for use as magnetic conductors, ground surfaces, antennas, varactors, ferrotunable substrates, or other active or passive electronic mechanisms.

37 CFR 211.4 - Registration of claims of protection in mask works.

Code of Federal Regulations, 2010 CFR

2010-07-01

... adding metal-connection layers to unpersonalized gate arrays may separately register the entire unpersonalized gate array and the custom metallization layers. Applicants seeking to register separately entire unpersonalized gate arrays or custom metallization layers should make the nature of their claim clear at Space 8...

Reconfigurable all-optical NOT, XOR, and NOR logic gates based on two dimensional photonic crystals

NASA Astrophysics Data System (ADS)

Parandin, Fariborz; Malmir, M. Reza; Naseri, Mosayeb; Zahedi, Abdulhamid

2018-01-01

Photonic crystals can be considered as one of the most important basis for designing optical devices. In this research, using two-dimensional photonic crystals with triangular lattices, ultra-compact logic gates are designed and simulated. The intended structure has the capability to be used as three logical gates (NOT, XOR, and NOR). The designed structures not only have characteristics of small dimensions which make them suitable for integrated optical circuits, but also exhibit very low power transfer delay which makes it possible to design high speed gates. On comparison with the previous works, our simulations show that at a wavelength of 1.55 μm , the gates indicate a time delay of about 0.1 ps and the contrast ratio for the XOR gate is about 30 dB, i.e., the proposed structures are more applicable in designing low error optical logic gates.

A modular design for rapid-response telecoms and navigation missions

NASA Astrophysics Data System (ADS)

Davies, P.; Liddle, D.; Buckley, John; Sweeting, M.; Roussel-Dupre, Diane; Caffrey, Michael

2004-11-01

Surrey Satellite Technology Ltd and Los Alamos National Laboratory are together building the Cibola Flight Experiment (CFESat), a mission with the aim of flight-proving a reconfigurable processor payload intended for a Low Earth Orbit system. The mission will survey portions of the VHF and UHF radio spectra. The satellite will be launched by the Space Test Program in September 2006 on the USAF Evolved Expendable Launch Vehicle (EELV) using the EELV's Secondary Payload Adapter (ESPA) that allows up to six small satellites to be launched as "piggyback" passengers with larger spacecraft. The payload is based on networks of reprogrammable, Field Programmable Gate Arrays (FPGAs) to process the received signals for ionospheric and lightning studies. The objective is to validate the on-orbit use of commercial, reconfigurable FPGA technology utilizing several different single-event upset mitigation schemes. It will also detect and measure impulsive events that occur in a complex background. SSTL's satellite platform is based on a new, ESPA- compatible, structure housing subsystems and equipments with proven flight heritage from SSTL's disaster monitoring constellation (DMC) and the Topsat mission satellite due for launch in 2005. The structure is mechanically quite complex for a microsatellite having both deployed solar panels and a pair of long booms as part of the payload. The satellite design is highly constrained by the mass and volume requirements of the EELV/EPSA.

An information-theoretic approach to motor action decoding with a reconfigurable parallel architecture.

PubMed

Craciun, Stefan; Brockmeier, Austin J; George, Alan D; Lam, Herman; Príncipe, José C

2011-01-01

Methods for decoding movements from neural spike counts using adaptive filters often rely on minimizing the mean-squared error. However, for non-Gaussian distribution of errors, this approach is not optimal for performance. Therefore, rather than using probabilistic modeling, we propose an alternate non-parametric approach. In order to extract more structure from the input signal (neuronal spike counts) we propose using minimum error entropy (MEE), an information-theoretic approach that minimizes the error entropy as part of an iterative cost function. However, the disadvantage of using MEE as the cost function for adaptive filters is the increase in computational complexity. In this paper we present a comparison between the decoding performance of the analytic Wiener filter and a linear filter trained with MEE, which is then mapped to a parallel architecture in reconfigurable hardware tailored to the computational needs of the MEE filter. We observe considerable speedup from the hardware design. The adaptation of filter weights for the multiple-input, multiple-output linear filters, necessary in motor decoding, is a highly parallelizable algorithm. It can be decomposed into many independent computational blocks with a parallel architecture readily mapped to a field-programmable gate array (FPGA) and scales to large numbers of neurons. By pipelining and parallelizing independent computations in the algorithm, the proposed parallel architecture has sublinear increases in execution time with respect to both window size and filter order.

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

DOEpatents

Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A

2014-01-28

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

Fault-Tolerant, Radiation-Hard DSP

NASA Technical Reports Server (NTRS)

Czajkowski, David

2011-01-01

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Measurement of high-voltage and radiation-damage limitations to advanced solar array performance

NASA Technical Reports Server (NTRS)

Guidice, D. A.; Severance, P. S.; Keinhardt, K. C.

1991-01-01

A description is given of the reconfigured Photovoltaic Array Space Power (PASP) Plus experiment: its objectives, solar-array complement, and diagnostic sensors. Results from a successful spaceflight will lead to a better understanding of high-voltage and radiation-damage limitations in the operation of new-technology solar arrays.

Modeling and reconfiguration of solar photovoltaic arrays under non-uniform shadow conditions

NASA Astrophysics Data System (ADS)

Nguyen, Dung Duc

Mass production and use of electricity generated from solar energy has become very common recently because of the environmental threats arising from the production of electricity from fossil fuels and nuclear power. The obvious benefits of solar energy are clean energy production and infinite supply of daylight. The main disadvantage is the high cost. In these photovoltaic systems, semiconductor materials convert the solar light into electrical energy. Current versus voltage characteristics of the solar cells are nonlinear, thus leading to technical control challenges. In the first order approximation, output power of a solar array is proportional to the irradiance of sunlight. However, in many applications, such as solar power plants, building integrated photovoltaic or solar tents, the solar photovoltaic arrays might be illuminated non-uniformly. The cause of non-uniform illumination may be the shadow of clouds, the trees, booms, neighbor's houses, or the shadow of one solar array on the other, etc. This further leads to nonlinearities in characteristics. Because of the nature of the electrical characteristics of solar cells, the maximum power losses are not proportional to the shadow, but magnify nonlinearly [1]. Further, shadows of solar PV array can cause other undesired effects: (1) The power actually generated from the solar PV array is much less than designed. At some systems, the annual losses because of the shadow effects can be reached 10%. Thus, the probability for "loss of load" increases [2]. (2) The local hot spot in the shaded part of the solar PV array can damage the solar cells. The shaded solar cells may be work on the negative voltage region and become a resistive load and absorb power. Bypass diodes are sometimes connected parallel to solar cells to protect them from damage. However, in most cases, just one diode is connected in parallel to group of solar cells [3], and this hidden the potential power output of the array. This proposed research will focus on the development of an adaptable solar array that is able to optimize power output, reconfigure itself when solar cells are damaged and create controllable output voltages and currents. This study will be a technological advancement over the existing technology of solar PV. Presently solar arrays are fixed arrays that require external device to control their output. In this research, the solar array will be able to self-reconfigure, leading to the following advantages: (1) Higher efficiency because no external devices are used. (2) Can reach maximum possible output power that is much higher than the maximum power of fixed solar arrays by arranging the solar cells in optimized connections. (3) Elimination of the hot spot effects. The proposed research has the following goals: First, to create a modeling and computing algorithm, which is able to simulate and analyze the effects of non-uniform changing shadows on the output power of solar PV arrays. Our model will be able to determine the power losses in each solar cell and the collective hot spots of an array. Second, to propose new methods, which are able to predict the performance of solar PV arrays under shadow conditions for long term (days, months, years). Finally, to develop adaptive reconfiguration algorithms to reconfigure connections within solar PV arrays in real time, under shadow conditions, in order to optimize output power.

Advanced RF and microwave functions based on an integrated optical frequency comb source.

PubMed

Xu, Xingyuan; Wu, Jiayang; Nguyen, Thach G; Shoeiby, Mehrdad; Chu, Sai T; Little, Brent E; Morandotti, Roberto; Mitchell, Arnan; Moss, David J

2018-02-05

We demonstrate advanced transversal radio frequency (RF) and microwave functions based on a Kerr optical comb source generated by an integrated micro-ring resonator. We achieve extremely high performance for an optical true time delay aimed at tunable phased array antenna applications, as well as reconfigurable microwave photonic filters. Our results agree well with theory. We show that our true time delay would yield a phased array antenna with features that include high angular resolution and a wide range of beam steering angles, while the microwave photonic filters feature high Q factors, wideband tunability, and highly reconfigurable filtering shapes. These results show that our approach is a competitive solution to implementing reconfigurable, high performance and potentially low cost RF and microwave signal processing functions for applications including radar and communication systems.

Reconfigurable optical interconnection network for multimode optical fiber sensor arrays

NASA Technical Reports Server (NTRS)

Chen, R. T.; Robinson, D.; Lu, H.; Wang, M. R.; Jannson, T.; Baumbick, R.

1992-01-01

A single-source, single-detector architecture has been developed to implement a reconfigurable optical interconnection network multimode optical fiber sensor arrays. The network was realized by integrating LiNbO3 electrooptic (EO) gratings working at the Raman Na regime and a massive fan-out waveguide hologram (WH) working at the Bragg regime onto a multimode glass waveguide. The glass waveguide utilized the whole substrate as a guiding medium. A 1-to-59 massive waveguide fan-out was demonstrated using a WH operating at 514 nm. Measured diffraction efficiency of 59 percent was experimentally confirmed. Reconfigurability of the interconnection was carried out by generating an EO grating through an externally applied electric field. Unlike conventional single-mode integrated optical devices, the guided mode demonstrated has an azimuthal symmetry in mode profile which is the same as that of a fiber mode.

Tunable and reconfigurable microwave filter by use of a Bragg-grating-based acousto-optic superlattice modulator.

PubMed

Delgado-Pinar, M; Mora, J; Díez, A; Andrés, M V; Ortega, B; Capmany, J

2005-01-01

We present an all-optical novel configuration for implementing multitap transversal filters by use of a broadband source sliced by fiber Bragg grating arrays generated by propagating an acoustic wave along a strong uniform fiber Bragg grating. The tunability and reconfigurability of the microwave filter are demonstrated.

Application-specific coarse-grained reconfigurable array: architecture and design methodology

NASA Astrophysics Data System (ADS)

Zhou, Li; Liu, Dongpei; Zhang, Jianfeng; Liu, Hengzhu

2015-06-01

Coarse-grained reconfigurable arrays (CGRAs) have shown potential for application in embedded systems in recent years. Numerous reconfigurable processing elements (PEs) in CGRAs provide flexibility while maintaining high performance by exploring different levels of parallelism. However, a difference remains between the CGRA and the application-specific integrated circuit (ASIC). Some application domains, such as software-defined radios (SDRs), require flexibility with performance demand increases. More effective CGRA architectures are expected to be developed. Customisation of a CGRA according to its application can improve performance and efficiency. This study proposes an application-specific CGRA architecture template composed of generic PEs (GPEs) and special PEs (SPEs). The hardware of the SPE can be customised to accelerate specific computational patterns. An automatic design methodology that includes pattern identification and application-specific function unit generation is also presented. A mapping algorithm based on ant colony optimisation is provided. Experimental results on the SDR target domain show that compared with other ordinary and application-specific reconfigurable architectures, the CGRA generated by the proposed method performs more efficiently for given applications.

A novel optogenetically tunable frequency modulating oscillator

PubMed Central

2018-01-01

Synthetic biology has enabled the creation of biological reconfigurable circuits, which perform multiple functions monopolizing a single biological machine; Such a system can switch between different behaviours in response to environmental cues. Previous work has demonstrated switchable dynamical behaviour employing reconfigurable logic gate genetic networks. Here we describe a computational framework for reconfigurable circuits in E.coli using combinations of logic gates, and also propose the biological implementation. The proposed system is an oscillator that can exhibit tunability of frequency and amplitude of oscillations. Further, the frequency of operation can be changed optogenetically. Insilico analysis revealed that two-component light systems, in response to light within a frequency range, can be used for modulating the frequency of the oscillator or stopping the oscillations altogether. Computational modelling reveals that mixing two colonies of E.coli oscillating at different frequencies generates spatial beat patterns. Further, we show that these oscillations more robustly respond to input perturbations compared to the base oscillator, to which the proposed oscillator is a modification. Compared to the base oscillator, the proposed system shows faster synchronization in a colony of cells for a larger region of the parameter space. Additionally, the proposed oscillator also exhibits lesser synchronization error in the transient period after input perturbations. This provides a strong basis for the construction of synthetic reconfigurable circuits in bacteria and other organisms, which can be scaled up to perform functions in the field of time dependent drug delivery with tunable dosages, and sets the stage for further development of circuits with synchronized population level behaviour. PMID:29389936

A novel optogenetically tunable frequency modulating oscillator.

PubMed

Mahajan, Tarun; Rai, Kshitij

2018-01-01

Synthetic biology has enabled the creation of biological reconfigurable circuits, which perform multiple functions monopolizing a single biological machine; Such a system can switch between different behaviours in response to environmental cues. Previous work has demonstrated switchable dynamical behaviour employing reconfigurable logic gate genetic networks. Here we describe a computational framework for reconfigurable circuits in E.coli using combinations of logic gates, and also propose the biological implementation. The proposed system is an oscillator that can exhibit tunability of frequency and amplitude of oscillations. Further, the frequency of operation can be changed optogenetically. Insilico analysis revealed that two-component light systems, in response to light within a frequency range, can be used for modulating the frequency of the oscillator or stopping the oscillations altogether. Computational modelling reveals that mixing two colonies of E.coli oscillating at different frequencies generates spatial beat patterns. Further, we show that these oscillations more robustly respond to input perturbations compared to the base oscillator, to which the proposed oscillator is a modification. Compared to the base oscillator, the proposed system shows faster synchronization in a colony of cells for a larger region of the parameter space. Additionally, the proposed oscillator also exhibits lesser synchronization error in the transient period after input perturbations. This provides a strong basis for the construction of synthetic reconfigurable circuits in bacteria and other organisms, which can be scaled up to perform functions in the field of time dependent drug delivery with tunable dosages, and sets the stage for further development of circuits with synchronized population level behaviour.

Field Programmable Gate Array Control of Power Systems in Graduate Student Laboratories

DTIC Science & Technology

2008-03-01

NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS Approved for public release; distribution is unlimited FIELD PROGRAMMABLE...REPORT TYPE AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Field Programmable Gate Array Control of Power Systems in Graduate Student...Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA) control of power electronics

High throughput reconfigurable data analysis system

NASA Technical Reports Server (NTRS)

Bearman, Greg (Inventor); Pelletier, Michael J. (Inventor); Seshadri, Suresh (Inventor); Pain, Bedabrata (Inventor)

2008-01-01

The present invention relates to a system and method for performing rapid and programmable analysis of data. The present invention relates to a reconfigurable detector comprising at least one array of a plurality of pixels, where each of the plurality of pixels can be selected to receive and read-out an input. The pixel array is divided into at least one pixel group for conducting a common predefined analysis. Each of the pixels has a programmable circuitry programmed with a dynamically configurable user-defined function to modify the input. The present detector also comprises a summing circuit designed to sum the modified input.

Reconfigurable OR and XOR logic gates based on dual responsive on-off-on micromotors

NASA Astrophysics Data System (ADS)

Dong, Yonggang; Liu, Mei; Zhang, Hui; Dong, Bin

2016-04-01

In this study, we report a hemisphere-like micromotor. Intriguingly, the micromotor exhibits controllable on-off-on motion, which can be actuated by two different external stimuli (UV and NH3). Moreover, the moving direction of the micromotor can be manipulated by the direction in which UV and NH3 are applied. As a result, the motion accelerates when both stimuli are applied in the same direction and decelerates when the application directions are opposite to each other. More interestingly, the dual stimuli responsive micromotor can be utilized as a reconfigurable logic gate with UV and NH3 as the inputs and the motion of the micromotor as the output. By controlling the direction of the external stimuli, OR and XOR dual logic functions can be realized.In this study, we report a hemisphere-like micromotor. Intriguingly, the micromotor exhibits controllable on-off-on motion, which can be actuated by two different external stimuli (UV and NH3). Moreover, the moving direction of the micromotor can be manipulated by the direction in which UV and NH3 are applied. As a result, the motion accelerates when both stimuli are applied in the same direction and decelerates when the application directions are opposite to each other. More interestingly, the dual stimuli responsive micromotor can be utilized as a reconfigurable logic gate with UV and NH3 as the inputs and the motion of the micromotor as the output. By controlling the direction of the external stimuli, OR and XOR dual logic functions can be realized. Electronic supplementary information (ESI) available: Fig. S1-S6 and Videos S1-S5. See DOI: 10.1039/c6nr00752j

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Field ion source development for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Holland, C. E.; Resnick, P. J.; Hertz, K. L.; Chichester, D. L.

2012-01-01

An ion source based on the principles of electrostatic field desorption is being developed to improve the performance of existing compact neutron generators. The ion source is an array of gated metal tips derived from field electron emitter array microfabrication technology. A comprehensive summary of development and experimental activities is presented. Many structural modifications to the arrays have been incorporated to achieve higher tip operating fields, while lowering fields at the gate electrode to prevent gate field electron emission which initiates electrical breakdown in the array. The latest focus of fabrication activities has been on rounding the gate electrode edge and surrounding the gate electrode with dielectric material. Array testing results have indicated a steady progression of increased array tip operating fields with each new design tested. The latest arrays have consistently achieved fields beyond those required for the onset of deuterium desorption (˜20 V/nm), and have demonstrated the desorption of deuterium at fields up to 36 V/nm. The number of ions desorbed from an array has been quantified, and field desorption of metal tip substrate material from array tips has been observed for the first time. Gas-phase field ionization studies with ˜10,000 tip arrays have achieved deuterium ion currents of ˜50 nA. Neutron production by field ionization has yielded ˜10 2 n/s from ˜1 mm 2 of array area using the deuterium-deuterium fusion reaction at 90 kV.

Microwave photonic filters using low-cost sources featuring tunability, reconfigurability and negative coefficients.

PubMed

Capmany, José; Mora, José; Ortega, Beatriz; Pastor, Daniel

2005-03-07

We propose and experimentally demonstrate two configurations of photonic filters for the processing of microwave signals featuring tunability, reconfigurability and negative coefficients based on the use of low cost optical sources. The first option is a low power configuration based on spectral slicing of a broadband source. The second is a high power configuration based on fixed lasers. Tunability, reconfigurability and negative coefficients are achieved by means of a MEMS cross-connect, a variable optical attenuator array and simple 2x2 switches respectively.

Application of Reconfigurable Computing Technology to Multi-KiloHertz Micro-Laser Altimeter (MMLA) Data Processing

NASA Technical Reports Server (NTRS)

Powell, Wesley; Dabney, Philip; Hicks, Edward; Pinchinat, Maxime; Day, John H. (Technical Monitor)

2002-01-01

The Multi-KiloHertz Micro-Laser Altimeter (MMLA) is an aircraft based instrument developed by NASA Goddard Space Flight Center with several potential spaceflight applications. This presentation describes how reconfigurable computing technology was employed to perform MMLA signal extraction in real-time under realistic operating constraints. The MMLA is a "single-photon-counting" airborne laser altimeter that is used to measure land surface features such as topography and vegetation canopy height. This instrument has to date flown a number of times aboard the NASA P3 aircraft acquiring data at a number of sites in the Mid-Atlantic region. This instrument pulses a relatively low-powered laser at a very high rate (10 kHz) and then measures the time-of-flight of discrete returns from the target surface. The instrument then bins these measurements into a two-dimensional array (vertical height vs. horizontal ground track) and selects the most likely signal path through the array. Return data that does not correspond to the selected signal path are classified as noise returns and are then discarded. The MMLA signal extraction algorithm is very compute intensive in that a score must be computed for every possible path through the two dimensional array in order to select the most likely signal path. Given a typical array size with 50 x 6, up to 33 arrays must be processed per second. And for each of these arrays, roughly 12,000 individual paths must be scored. Furthermore, the number of paths increases exponentially with the horizontal size of the array, and linearly with the vertical size. Yet, increasing the horizontal and vertical sizes of the array offer science advantages such as improved range, resolution, and noise rejection. Due to the volume of return data and the compute intensive signal extraction algorithm, the existing PC-based MMLA data system has been unable to perform signal extraction in real-time unless the array is limited in size to one column, This limits the ability of the MMLA to operate in environments with sparse signal returns and a high number of noise return. However, under an IR&D project, an FPGA-based, reconfigurable computing data system has been developed that has been demonstrated to perform real-time signal extraction under realistic operating constraints. This reconfigurable data system is based on the commercially available Firebird Board from Annapolis Microsystems. This PCI board consists of a Xilinx Virtex 2000E FPGA along with 36 MB of SRAM arranged in five separately addressable banks. This board is housed in a rackmount PC with dual 850MHz Pentium processors running the Windows 2000 operating system. This data system performs all signal extraction in hardware on the Firebird, but also runs the existing "software based" signal extraction in tandem for comparison purposes. Using a relatively small amount of the Virtex XCV2000E resources, the reconfigurable data system has demonstrated to improve performance improvement over the existing software based data system by an order of magnitude. Performance could be further improved by employing parallelism. Ground testing and a preliminary engineering test flight aboard the NASA P3 has been performed, during which the reconfigurable data system has been demonstrated to match the results of the existing data system.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

A Modular Approach to Arithmetic and Logic Unit Design on a Reconfigurable Hardware Platform for Educational Purpose

NASA Astrophysics Data System (ADS)

Oztekin, Halit; Temurtas, Feyzullah; Gulbag, Ali

The Arithmetic and Logic Unit (ALU) design is one of the important topics in Computer Architecture and Organization course in Computer and Electrical Engineering departments. There are ALU designs that have non-modular nature to be used as an educational tool. As the programmable logic technology has developed rapidly, it is feasible that ALU design based on Field Programmable Gate Array (FPGA) is implemented in this course. In this paper, we have adopted the modular approach to ALU design based on FPGA. All the modules in the ALU design are realized using schematic structure on Altera's Cyclone II Development board. Under this model, the ALU content is divided into four distinct modules. These are arithmetic unit except for multiplication and division operations, logic unit, multiplication unit and division unit. User can easily design any size of ALU unit since this approach has the modular nature. Then, this approach was applied to microcomputer architecture design named BZK.SAU.FPGA10.0 instead of the current ALU unit.

Digitally balanced detection for optical tomography.

PubMed

Hafiz, Rehan; Ozanyan, Krikor B

2007-10-01

Analog balanced Photodetection has found extensive usage for sensing of a weak absorption signal buried in laser intensity noise. This paper proposes schemes for compact, affordable, and flexible digital implementation of the already established analog balanced detection, as part of a multichannel digital tomography system. Variants of digitally balanced detection (DBD) schemes, suitable for weak signals on a largely varying background or weakly varying envelopes of high frequency carrier waves, are introduced analytically and elaborated in terms of algorithmic and hardware flow. The DBD algorithms are implemented on a low-cost general purpose reconfigurable hardware (field-programmable gate array), utilizing less than half of its resources. The performance of the DBD schemes compare favorably with their analog counterpart: A common mode rejection ratio of 50 dB was observed over a bandwidth of 300 kHz, limited mainly by the host digital hardware. The close relationship between the DBD outputs and those of known analog balancing circuits is discussed in principle and shown experimentally in the example case of propane gas detection.

STRS Compliant FPGA Waveform Development

NASA Technical Reports Server (NTRS)

Nappier, Jennifer; Downey, Joseph

2008-01-01

The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. Current standards were researched and new standard interfaces were proposed. The implementation of the proposed standard interfaces on a laboratory breadboard SDR will be presented.

FPGA-Based Smart Sensor for Online Displacement Measurements Using a Heterodyne Interferometer

PubMed Central

Vera-Salas, Luis Alberto; Moreno-Tapia, Sandra Veronica; Garcia-Perez, Arturo; de Jesus Romero-Troncoso, Rene; Osornio-Rios, Roque Alfredo; Serroukh, Ibrahim; Cabal-Yepez, Eduardo

2011-01-01

The measurement of small displacements on the nanometric scale demands metrological systems of high accuracy and precision. In this context, interferometer-based displacement measurements have become the main tools used for traceable dimensional metrology. The different industrial applications in which small displacement measurements are employed requires the use of online measurements, high speed processes, open architecture control systems, as well as good adaptability to specific process conditions. The main contribution of this work is the development of a smart sensor for large displacement measurement based on phase measurement which achieves high accuracy and resolution, designed to be used with a commercial heterodyne interferometer. The system is based on a low-cost Field Programmable Gate Array (FPGA) allowing the integration of several functions in a single portable device. This system is optimal for high speed applications where online measurement is needed and the reconfigurability feature allows the addition of different modules for error compensation, as might be required by a specific application. PMID:22164040

A Lithography-Free and Field-Programmable Photonic Metacanvas.

PubMed

Dong, Kaichen; Hong, Sukjoon; Deng, Yang; Ma, He; Li, Jiachen; Wang, Xi; Yeo, Junyeob; Wang, Letian; Lou, Shuai; Tom, Kyle B; Liu, Kai; You, Zheng; Wei, Yang; Grigoropoulos, Costas P; Yao, Jie; Wu, Junqiao

2018-02-01

The unique correspondence between mathematical operators and photonic elements in wave optics enables quantitative analysis of light manipulation with individual optical devices. Phase-transition materials are able to provide real-time reconfigurability of these devices, which would create new optical functionalities via (re)compilation of photonic operators, as those achieved in other fields such as field-programmable gate arrays (FPGA). Here, by exploiting the hysteretic phase transition of vanadium dioxide, an all-solid, rewritable metacanvas on which nearly arbitrary photonic devices can be rapidly and repeatedly written and erased is presented. The writing is performed with a low-power laser and the entire process stays below 90 °C. Using the metacanvas, dynamic manipulation of optical waves is demonstrated for light propagation, polarization, and reconstruction. The metacanvas supports physical (re)compilation of photonic operators akin to that of FPGA, opening up possibilities where photonic elements can be field programmed to deliver complex, system-level functionalities. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A reconfigurable, wearable, wireless ECG system.

PubMed

Borromeo, S; Rodriguez-Sanchez, C; Machado, F; Hernandez-Tamames, J A; de la Prieta, R

2007-01-01

New emerging concepts as "wireless hospital", "mobile healthcare" or "wearable telemonitoring" require the development of bio-signal acquisition devices to be easily integrated into the clinical routine. In this work, we present a new system for Electrocardiogram (ECG) acquisition and its processing, with wireless transmission on demand (either the complete ECG or only one alarm message, just in case a pathological heart rate detected). Size and power consumption are optimized in order to provide mobility and comfort to the patient. We have designed a modular hardware system and an autonomous platform based on a Field-Programmable Gate Array (FPGA) for developing and debugging. The modular approach allows to redesign the system in an easy way. Its adaptation to a new biomedical signal would only need small changes on it. The hardware system is composed of three layers that can be plugged/unplugged: communication layer, processing layer and sensor layer. In addition, we also present a general purpose end-user application developed for mobile phones or Personal Digital Assistant devices (PDAs).

A memory efficient implementation scheme of Gauss error function in a Laguerre-Volterra network for neuroprosthetic devices

NASA Astrophysics Data System (ADS)

Li, Will X. Y.; Cui, Ke; Zhang, Wei

2017-04-01

Cognitive neural prosthesis is a manmade device which can be used to restore or compensate for lost human cognitive modalities. The generalized Laguerre-Volterra (GLV) network serves as a robust mathematical underpinning for the development of such prosthetic instrument. In this paper, a hardware implementation scheme of Gauss error function for the GLV network targeting reconfigurable platforms is reported. Numerical approximations are formulated which transform the computation of nonelementary function into combinational operations of elementary functions, and memory-intensive look-up table (LUT) based approaches can therefore be circumvented. The computational precision can be made adjustable with the utilization of an error compensation scheme, which is proposed based on the experimental observation of the mathematical characteristics of the error trajectory. The precision can be further customizable by exploiting the run-time characteristics of the reconfigurable system. Compared to the polynomial expansion based implementation scheme, the utilization of slice LUTs, occupied slices, and DSP48E1s on a Xilinx XC6VLX240T field-programmable gate array has decreased by 94.2%, 94.1%, and 90.0%, respectively. While compared to the look-up table based scheme, 1.0 ×1017 bits of storage can be spared under the maximum allowable error of 1.0 ×10-3 . The proposed implementation scheme can be employed in the study of large-scale neural ensemble activity and in the design and development of neural prosthetic device.

A high-speed, reconfigurable, channel- and time-tagged photon arrival recording system for intensity-interferometry and quantum optics experiments

NASA Astrophysics Data System (ADS)

Girish, B. S.; Pandey, Deepak; Ramachandran, Hema

2017-08-01

We present a compact, inexpensive multichannel module, APODAS (Avalanche Photodiode Output Data Acquisition System), capable of detecting 0.8 billion photons per second and providing real-time recording on a computer hard-disk, of channel- and time-tagged information of the arrival of upto 0.4 billion photons per second. Built around a Virtex-5 Field Programmable Gate Array (FPGA) unit, APODAS offers a temporal resolution of 5 nanoseconds with zero deadtime in data acquisition, utilising an efficient scheme for time and channel tagging and employing Gigabit ethernet for the transfer of data. Analysis tools have been developed on a Linux platform for multi-fold coincidence studies and time-delayed intensity interferometry. As illustrative examples, the second-order intensity correlation function ( g 2) of light from two commonly used sources in quantum optics —a coherent laser source and a dilute atomic vapour emitting spontaneously, constituting a thermal source— are presented. With easy reconfigurability and with no restriction on the total record length, APODAS can be readily used for studies over various time scales. This is demonstrated by using APODAS to reveal Rabi oscillations on nanosecond time scales in the emission of ultracold atoms, on the one hand, and, on the other hand, to measure the second-order correlation function on the millisecond time scales from tailored light sources. The efficient and versatile performance of APODAS promises its utility in diverse fields, like quantum optics, quantum communication, nuclear physics, astrophysics and biology.

Novel processor architecture for onboard infrared sensors

NASA Astrophysics Data System (ADS)

Hihara, Hiroki; Iwasaki, Akira; Tamagawa, Nobuo; Kuribayashi, Mitsunobu; Hashimoto, Masanori; Mitsuyama, Yukio; Ochi, Hiroyuki; Onodera, Hidetoshi; Kanbara, Hiroyuki; Wakabayashi, Kazutoshi; Tada, Munehiro

2016-09-01

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

FPGA implementation of sparse matrix algorithm for information retrieval

NASA Astrophysics Data System (ADS)

Bojanic, Slobodan; Jevtic, Ruzica; Nieto-Taladriz, Octavio

2005-06-01

Information text data retrieval requires a tremendous amount of processing time because of the size of the data and the complexity of information retrieval algorithms. In this paper the solution to this problem is proposed via hardware supported information retrieval algorithms. Reconfigurable computing may adopt frequent hardware modifications through its tailorable hardware and exploits parallelism for a given application through reconfigurable and flexible hardware units. The degree of the parallelism can be tuned for data. In this work we implemented standard BLAS (basic linear algebra subprogram) sparse matrix algorithm named Compressed Sparse Row (CSR) that is showed to be more efficient in terms of storage space requirement and query-processing timing over the other sparse matrix algorithms for information retrieval application. Although inverted index algorithm is treated as the de facto standard for information retrieval for years, an alternative approach to store the index of text collection in a sparse matrix structure gains more attention. This approach performs query processing using sparse matrix-vector multiplication and due to parallelization achieves a substantial efficiency over the sequential inverted index. The parallel implementations of information retrieval kernel are presented in this work targeting the Virtex II Field Programmable Gate Arrays (FPGAs) board from Xilinx. A recent development in scientific applications is the use of FPGA to achieve high performance results. Computational results are compared to implementations on other platforms. The design achieves a high level of parallelism for the overall function while retaining highly optimised hardware within processing unit.

Parallel Processing of Broad-Band PPM Signals

NASA Technical Reports Server (NTRS)

Gray, Andrew; Kang, Edward; Lay, Norman; Vilnrotter, Victor; Srinivasan, Meera; Lee, Clement

2010-01-01

A parallel-processing algorithm and a hardware architecture to implement the algorithm have been devised for timeslot synchronization in the reception of pulse-position-modulated (PPM) optical or radio signals. As in the cases of some prior algorithms and architectures for parallel, discrete-time, digital processing of signals other than PPM, an incoming broadband signal is divided into multiple parallel narrower-band signals by means of sub-sampling and filtering. The number of parallel streams is chosen so that the frequency content of the narrower-band signals is low enough to enable processing by relatively-low speed complementary metal oxide semiconductor (CMOS) electronic circuitry. The algorithm and architecture are intended to satisfy requirements for time-varying time-slot synchronization and post-detection filtering, with correction of timing errors independent of estimation of timing errors. They are also intended to afford flexibility for dynamic reconfiguration and upgrading. The architecture is implemented in a reconfigurable CMOS processor in the form of a field-programmable gate array. The algorithm and its hardware implementation incorporate three separate time-varying filter banks for three distinct functions: correction of sub-sample timing errors, post-detection filtering, and post-detection estimation of timing errors. The design of the filter bank for correction of timing errors, the method of estimating timing errors, and the design of a feedback-loop filter are governed by a host of parameters, the most critical one, with regard to processing very broadband signals with CMOS hardware, being the number of parallel streams (equivalently, the rate-reduction parameter).

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Evolution of a designless nanoparticle network into reconfigurable Boolean logic

NASA Astrophysics Data System (ADS)

Bose, S. K.; Lawrence, C. P.; Liu, Z.; Makarenko, K. S.; van Damme, R. M. J.; Broersma, H. J.; van der Wiel, W. G.

2015-12-01

Natural computers exploit the emergent properties and massive parallelism of interconnected networks of locally active components. Evolution has resulted in systems that compute quickly and that use energy efficiently, utilizing whatever physical properties are exploitable. Man-made computers, on the other hand, are based on circuits of functional units that follow given design rules. Hence, potentially exploitable physical processes, such as capacitive crosstalk, to solve a problem are left out. Until now, designless nanoscale networks of inanimate matter that exhibit robust computational functionality had not been realized. Here we artificially evolve the electrical properties of a disordered nanomaterials system (by optimizing the values of control voltages using a genetic algorithm) to perform computational tasks reconfigurably. We exploit the rich behaviour that emerges from interconnected metal nanoparticles, which act as strongly nonlinear single-electron transistors, and find that this nanoscale architecture can be configured in situ into any Boolean logic gate. This universal, reconfigurable gate would require about ten transistors in a conventional circuit. Our system meets the criteria for the physical realization of (cellular) neural networks: universality (arbitrary Boolean functions), compactness, robustness and evolvability, which implies scalability to perform more advanced tasks. Our evolutionary approach works around device-to-device variations and the accompanying uncertainties in performance. Moreover, it bears a great potential for more energy-efficient computation, and for solving problems that are very hard to tackle in conventional architectures.

Noise-aided computation within a synthetic gene network through morphable and robust logic gates

NASA Astrophysics Data System (ADS)

Dari, Anna; Kia, Behnam; Wang, Xiao; Bulsara, Adi R.; Ditto, William

2011-04-01

An important goal for synthetic biology is to build robust and tunable genetic regulatory networks that are capable of performing assigned operations, usually in the presence of noise. In this work, a synthetic gene network derived from the bacteriophage λ underpins a reconfigurable logic gate wherein we exploit noise and nonlinearity through the application of the logical stochastic resonance paradigm. This biological logic gate can emulate or “morph” the AND and OR operations through varying internal system parameters in a noisy background. Such genetic circuits can afford intriguing possibilities in the realization of engineered genetic networks in which the actual function of the gate can be changed after the network has been built, via an external control parameter. In this article, the full system characterization is reported, with the logic gate performance studied in the presence of external and internal noise. The robustness of the gate, to noise, is studied and illustrated through numerical simulations.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L.; Holland, Christopher; Chichester, David

2016-08-23

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L; Holland, Christopher; Chichester, David; Schwoebel, Paul

2013-09-17

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

NASA Astrophysics Data System (ADS)

Rosky, David S.; Coy, Bruce H.; Friedmann, Marc D.

1992-03-01

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

FPGA implementation of a biological neural network based on the Hodgkin-Huxley neuron model.

PubMed

Yaghini Bonabi, Safa; Asgharian, Hassan; Safari, Saeed; Nili Ahmadabadi, Majid

2014-01-01

A set of techniques for efficient implementation of Hodgkin-Huxley-based (H-H) model of a neural network on FPGA (Field Programmable Gate Array) is presented. The central implementation challenge is H-H model complexity that puts limits on the network size and on the execution speed. However, basics of the original model cannot be compromised when effect of synaptic specifications on the network behavior is the subject of study. To solve the problem, we used computational techniques such as CORDIC (Coordinate Rotation Digital Computer) algorithm and step-by-step integration in the implementation of arithmetic circuits. In addition, we employed different techniques such as sharing resources to preserve the details of model as well as increasing the network size in addition to keeping the network execution speed close to real time while having high precision. Implementation of a two mini-columns network with 120/30 excitatory/inhibitory neurons is provided to investigate the characteristic of our method in practice. The implementation techniques provide an opportunity to construct large FPGA-based network models to investigate the effect of different neurophysiological mechanisms, like voltage-gated channels and synaptic activities, on the behavior of a neural network in an appropriate execution time. Additional to inherent properties of FPGA, like parallelism and re-configurability, our approach makes the FPGA-based system a proper candidate for study on neural control of cognitive robots and systems as well.

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

NASA Astrophysics Data System (ADS)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

Developing a gate-array capability at a research and development laboratory

NASA Astrophysics Data System (ADS)

Balch, J. W.; Current, K. W.; Magnuson, W. G., Jr.; Pocha, M. D.

1983-03-01

Experiences in developing a gate array capability for low volume applications in a research and development (R and D) laboratory are described. By purchasing unfinished wafers and doing the customization steps in-house. Turnaround time was shortened to as little as one week and the direct costs reduced to as low as $5K per design. Designs generally require fast turnaround (a few weeks to a few months) and very low volumes (1 to 25). Design costs must be kept at a minimum. After reviewing available commercial gate array design and fabrication services, it was determined that objectives would best be met by using existing internal integrated circuit fabrication facilities, the COMPUTERVISION interactive graphics layout system, and extensive computational capabilities. The reasons and the approach taken for; selection for a particular gate array wafer, adapting a particular logic simulation program, and how layout aids were enhanced are discussed. Testing of the customized chips is described. The content, schedule, and results of the internal gate array course recently completed are discussed. Finally, problem areas and near term plans are presented.

Reconfigurable Hardware for Compressing Hyperspectral Image Data

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

2010-01-01

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of the FPGAs makes it possible to effectively alter the design to some extent to satisfy different requirements without adding hardware. The implementation could be easily propagated to future FPGA generations and/or to custom application-specific integrated circuits.

Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits.

PubMed

Larentis, Stefano; Fallahazad, Babak; Movva, Hema C P; Kim, Kyounghwan; Rai, Amritesh; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; Tutuc, Emanuel

2017-05-23

Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary field-effect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe 2 field-effect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications.

An Embedded Reconfigurable Logic Module

NASA Technical Reports Server (NTRS)

Tucker, Jerry H.; Klenke, Robert H.; Shams, Qamar A. (Technical Monitor)

2002-01-01

A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

A dynamically reconfigurable logic cell: from artificial neural networks to quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Naqvi, Syed Rameez; Akram, Tallha; Iqbal, Saba; Haider, Sajjad Ali; Kamran, Muhammad; Muhammad, Nazeer

2018-02-01

Considering the lack of optimization support for Quantum-dot Cellular Automata, we propose a dynamically reconfigurable logic cell capable of implementing various logic operations by means of artificial neural networks. The cell can be reconfigured to any 2-input combinational logic gate by altering the strength of connections, called weights and biases. We demonstrate how these cells may appositely be organized to perform multi-bit arithmetic and logic operations. The proposed work is important in that it gives a standard implementation of an 8-bit arithmetic and logic unit for quantum-dot cellular automata with minimal area and latency overhead. We also compare the proposed design with a few existing arithmetic and logic units, and show that it is more area efficient than any equivalent available in literature. Furthermore, the design is adaptable to 16, 32, and 64 bit architectures.

Reconfigurable Cellular Photonic Crystal Arrays (RCPA)

DTIC Science & Technology

2013-03-01

signal processing based on reconfigurable integrated optics devices. This technology has the potential to revolutionize the design circle of optical...Accomplishments III.A. Design and fabrication of an accumulation-mode modulator Figure 1(a) shows the schematic of a compact resonator on the double-Si... integration of silicon nitride on silicon-on-insulator platform to enhance the arsenal of photonic circuit designers . The coherent integration of

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Multiplexed charge-locking device for large arrays of quantum devices

NASA Astrophysics Data System (ADS)

Puddy, R. K.; Smith, L. W.; Al-Taie, H.; Chong, C. H.; Farrer, I.; Griffiths, J. P.; Ritchie, D. A.; Kelly, M. J.; Pepper, M.; Smith, C. G.

2015-10-01

We present a method of forming and controlling large arrays of gate-defined quantum devices. The method uses an on-chip, multiplexed charge-locking system and helps to overcome the restraints imposed by the number of wires available in cryostat measurement systems. The device architecture that we describe here utilises a multiplexer-type scheme to lock charge onto gate electrodes. The design allows access to and control of gates whose total number exceeds that of the available electrical contacts and enables the formation, modulation and measurement of large arrays of quantum devices. We fabricate such devices on n-type GaAs/AlGaAs substrates and investigate the stability of the charge locked on to the gates. Proof-of-concept is shown by measurement of the Coulomb blockade peaks of a single quantum dot formed by a floating gate in the device. The floating gate is seen to drift by approximately one Coulomb oscillation per hour.

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

PubMed Central

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R.J. Dwayne

2016-01-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence. PMID:28008918

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

NASA Astrophysics Data System (ADS)

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R. J. Dwayne

2016-12-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence.

Plasmonic phased array feeder enabling ultra-fast beam steering at millimeter waves.

PubMed

Bonjour, R; Burla, M; Abrecht, F C; Welschen, S; Hoessbacher, C; Heni, W; Gebrewold, S A; Baeuerle, B; Josten, A; Salamin, Y; Haffner, C; Johnston, P V; Elder, D L; Leuchtmann, P; Hillerkuss, D; Fedoryshyn, Y; Dalton, L R; Hafner, C; Leuthold, J

2016-10-31

In this paper, we demonstrate an integrated microwave phoneeded for beamtonics phased array antenna feeder at 60 GHz with a record-low footprint. Our design is based on ultra-compact plasmonic phase modulators (active area <2.5µm²) that not only provide small size but also ultra-fast tuning speed. In our design, the integrated circuit footprint is in fact only limited by the contact pads of the electrodes and by the optical feeding waveguides. Using the high speed of the plasmonic modulators, we demonstrate beam steering with less than 1 ns reconfiguration time, i.e. the beam direction is reconfigured in-between 1 GBd transmitted symbols.

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Oxide-based platform for reconfigurable superconducting nanoelectronics.

PubMed

Veazey, Joshua P; Cheng, Guanglei; Irvin, Patrick; Cen, Cheng; Bogorin, Daniela F; Bi, Feng; Huang, Mengchen; Bark, Chung-Wung; Ryu, Sangwoo; Cho, Kwang-Hwan; Eom, Chang-Beom; Levy, Jeremy

2013-09-20

We report quasi-1D superconductivity at the interface of LaAlO3 and SrTiO3. The material system and nanostructure fabrication method supply a new platform for superconducting nanoelectronics. Nanostructures having line widths w ~ 10 nm are formed from the parent two-dimensional electron liquid using conductive atomic force microscope lithography. Nanowire cross-sections are small compared to the superconducting coherence length in LaAlO3/SrTiO3, placing them in the quasi-1D regime. Broad superconducting transitions versus temperature and finite resistances in the superconducting state well below Tc ≈ 200 mK are observed, suggesting the presence of fluctuation- and heating-induced resistance. The superconducting resistances and V-I characteristics are tunable through the use of a back gate. Four-terminal resistances in the superconducting state show an unusual dependence on the current path, varying by as much as an order of magnitude. This new technology, i.e., the ability to 'write' gate-tunable superconducting nanostructures on an insulating LaAlO3/SrTiO3 'canvas', opens possibilities for the development of new families of reconfigurable superconducting nanoelectronics.

Highly Reconfigurable Beamformer Stimulus Generator

NASA Astrophysics Data System (ADS)

Vaviļina, E.; Gaigals, G.

2018-02-01

The present paper proposes a highly reconfigurable beamformer stimulus generator of radar antenna array, which includes three main blocks: settings of antenna array, settings of objects (signal sources) and a beamforming simulator. Following from the configuration of antenna array and object settings, different stimulus can be generated as the input signal for a beamformer. This stimulus generator is developed under a greater concept with two utterly independent paths where one is the stimulus generator and the other is the hardware beamformer. Both paths can be complemented in final and in intermediate steps as well to check and improve system performance. This way the technology development process is promoted by making each of the future hardware steps more substantive. Stimulus generator configuration capabilities and test results are presented proving the application of the stimulus generator for FPGA based beamforming unit development and tuning as an alternative to an actual antenna system.

IEEE Radio and Wireless Symposium Student Awards Support Request: 2010-2012

DTIC Science & Technology

2012-01-01

Reconfigurable Architecture Enabling All-Digital Transmission for Cognitive Radios ……..3 Ultra-Wide Band Vivaldi Antenna Array using Low Loss SIW Power...1431714191, Iran 2University of Tennessee, Knoxville, TN, 37996, US Ultra-Wide Band Vivaldi Antenna Array using Low Loss SIW Power Divider and GCPW Wide

Wire like link for cycle reproducible and cycle accurate hardware accelerator

DOEpatents

Asaad, Sameh; Kapur, Mohit; Parker, Benjamin D

2015-04-07

First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

Reconfigurable Transceiver and Software-Defined Radio Architecture and Technology Evaluated for NASA Space Communications

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Kacpura, Thomas J.

2004-01-01

The NASA Glenn Research Center is investigating the development and suitability of a software-based open-architecture for space-based reconfigurable transceivers (RTs) and software-defined radios (SDRs). The main objectives of this project are to enable advanced operations and reduce mission costs. SDRs are becoming more common because of the capabilities of reconfigurable digital signal processing technologies such as field programmable gate arrays and digital signal processors, which place radio functions in firmware and software that were traditionally performed with analog hardware components. Features of interest of this communications architecture include nonproprietary open standards and application programming interfaces to enable software reuse and portability, independent hardware and software development, and hardware and software functional separation. The goals for RT and SDR technologies for NASA space missions include prelaunch and on-orbit frequency and waveform reconfigurability and programmability, high data rate capability, and overall communications and processing flexibility. These operational advances over current state-of-art transceivers will be provided to reduce the power, mass, and cost of RTs and SDRs for space communications. The open architecture for NASA communications will support existing (legacy) communications needs and capabilities while providing a path to more capable, advanced waveform development and mission concepts (e.g., ad hoc constellations with self-healing networks and high-rate science data return). A study was completed to assess the state of the art in RT architectures, implementations, and technologies. In-house researchers conducted literature searches and analysis, interviewed Government and industry contacts, and solicited information and white papers from industry on space-qualifiable RTs and SDRs and their associated technologies for space-based NASA applications. The white papers were evaluated, compiled, and used to assess RT and SDR system architectures and core technology elements to determine an appropriate investment strategy to advance these technologies to meet future mission needs. The use of these radios in the space environment represents a challenge because of the space radiation suitability of the components, which drastically reduces the processing capability. The radios available for space are considered to be RTs (as opposed to SDRs), which are digitally programmable radios with selectable changes from an architecture combining analog and digital components. The limited flexibility of this design contrasts against the desire to have a power-efficient solution and open architecture.

Radiography by selective detection of scatter field velocity components

NASA Technical Reports Server (NTRS)

Dugan, Edward T. (Inventor); Jacobs, Alan M. (Inventor); Shedlock, Daniel (Inventor)

2007-01-01

A reconfigurable collimated radiation detector, system and related method includes at least one collimated radiation detector. The detector has an adjustable collimator assembly including at least one feature, such as a fin, optically coupled thereto. Adjustments to the adjustable collimator selects particular directions of travel of scattered radiation emitted from an irradiated object which reach the detector. The collimated detector is preferably a collimated detector array, where the collimators are independently adjustable. The independent motion capability provides the capability to focus the image by selection of the desired scatter field components. When an array of reconfigurable collimated detectors is provided, separate image data can be obtained from each of the detectors and the respective images cross-correlated and combined to form an enhanced image.

Rapid evolution of analog circuits configured on a field programmable transistor array

NASA Technical Reports Server (NTRS)

Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

2002-01-01

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Reconfigurable mask for adaptive coded aperture imaging (ACAI) based on an addressable MOEMS microshutter array

NASA Astrophysics Data System (ADS)

McNie, Mark E.; Combes, David J.; Smith, Gilbert W.; Price, Nicola; Ridley, Kevin D.; Brunson, Kevin M.; Lewis, Keith L.; Slinger, Chris W.; Rogers, Stanley

2007-09-01

Coded aperture imaging has been used for astronomical applications for several years. Typical implementations use a fixed mask pattern and are designed to operate in the X-Ray or gamma ray bands. More recent applications have emerged in the visible and infra red bands for low cost lens-less imaging systems. System studies have shown that considerable advantages in image resolution may accrue from the use of multiple different images of the same scene - requiring a reconfigurable mask. We report on work to develop a novel, reconfigurable mask based on micro-opto-electro-mechanical systems (MOEMS) technology employing interference effects to modulate incident light in the mid-IR band (3-5μm). This is achieved by tuning a large array of asymmetric Fabry-Perot cavities by applying an electrostatic force to adjust the gap between a moveable upper polysilicon mirror plate supported on suspensions and underlying fixed (electrode) layers on a silicon substrate. A key advantage of the modulator technology developed is that it is transmissive and high speed (e.g. 100kHz) - allowing simpler imaging system configurations. It is also realised using a modified standard polysilicon surface micromachining process (i.e. MUMPS-like) that is widely available and hence should have a low production cost in volume. We have developed designs capable of operating across the entire mid-IR band with peak transmissions approaching 100% and high contrast. By using a pixelated array of small mirrors, a large area device comprising individually addressable elements may be realised that allows reconfiguring of the whole mask at speeds in excess of video frame rates.

Trigger design for a gamma ray detector of HIRFL-ETF

NASA Astrophysics Data System (ADS)

Du, Zhong-Wei; Su, Hong; Qian, Yi; Kong, Jie

2013-10-01

The Gamma Ray Array Detector (GRAD) is one subsystem of HIRFL-ETF (the External Target Facility (ETF) of the Heavy Ion Research Facility in Lanzhou (HIRFL)). It is capable of measuring the energy of gamma-rays with 1024 CsI scintillators in in-beam nuclear experiments. The GRAD trigger should select the valid events and reject the data from the scintillators which are not hit by the gamma-ray. The GRAD trigger has been developed based on the Field Programmable Gate Array (FPGAs) and PXI interface. It makes prompt trigger decisions to select valid events by processing the hit signals from the 1024 CsI scintillators. According to the physical requirements, the GRAD trigger module supplies 12-bit trigger information for the global trigger system of ETF and supplies a trigger signal for data acquisition (DAQ) system of GRAD. In addition, the GRAD trigger generates trigger data that are packed and transmitted to the host computer via PXI bus to be saved for off-line analysis. The trigger processing is implemented in the front-end electronics of GRAD and one FPGA of the GRAD trigger module. The logic of PXI transmission and reconfiguration is implemented in another FPGA of the GRAD trigger module. During the gamma-ray experiments, the GRAD trigger performs reliably and efficiently. The function of GRAD trigger is capable of satisfying the physical requirements.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Localized Defect Modes in a Two-Dimensional Array of Magnetic Nanodots

DTIC Science & Technology

2013-06-22

number of defects it is possible to obtain the information about the entire spin-wave spectrum of the array. Index Terms—Spin waves, magnonic crystal...multistability opens a way for the development of a novel type of artificial materials with tunable microwave properties – reconfigurable magnonic ...information about the entire spin-wave spectrum of the array. 15. SUBJECT TERMS Spin waves, magnonic crystal, magnetic dot, ferromagnetic resonance

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Real-time dual-polarization transmission based on hybrid optical wireless communications

NASA Astrophysics Data System (ADS)

Sousa, Artur N.; Alimi, Isiaka A.; Ferreira, Ricardo M.; Shahpari, Ali; Lima, Mário; Monteiro, Paulo P.; Teixeira, António L.

2018-01-01

We present experimental work on a gigabit-capable and long-reach hybrid coherent UWDM-PON plus FSO system for supporting different applications over the same fiber infrastructure in the mobile backhaul (MBH) networks. Also, for the first time, we demonstrate a reconfigurable real-time DSP transmission/reception of DP-QPSK signals over standard single-mode fiber (SSMF) and FSO links. The receiver presented is based on a commercial field-programmable gate array (FPGA). The considered communication links are based on 20 UDWDM channels with 625 Mbaud and 2.5 GHz channel spacing. We are able to demonstrate the lowest sampling rate required for digital coherent PON by employing four 1.25 Gsa/s ADCs using an electrical front-end receiver that offers only 1 GHz analog bandwidth. We achieved this by implementing a phase and polarization diversity coherent receiver combined with the DP-QPSK modulation formats. The system performance is estimated in terms of receiver sensitivity. The results show the viability of coherent PON and flexible dual-polarization supported by software-defined transceivers for the MBH.

Design and Testing of Space Telemetry SCA Waveform

NASA Technical Reports Server (NTRS)

Mortensen, Dale J.; Handler, Louis M.; Quinn, Todd M.

2006-01-01

A Software Communications Architecture (SCA) Waveform for space telemetry is being developed at the NASA Glenn Research Center (GRC). The space telemetry waveform is implemented in a laboratory testbed consisting of general purpose processors, field programmable gate arrays (FPGAs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). The radio hardware is integrated with an SCA Core Framework and other software development tools. The waveform design is described from both the bottom-up signal processing and top-down software component perspectives. Simulations and model-based design techniques used for signal processing subsystems are presented. Testing with legacy hardware-based modems verifies proper design implementation and dynamic waveform operations. The waveform development is part of an effort by NASA to define an open architecture for space based reconfigurable transceivers. Use of the SCA as a reference has increased understanding of software defined radio architectures. However, since space requirements put a premium on size, mass, and power, the SCA may be impractical for today s space ready technology. Specific requirements for an SCA waveform and other lessons learned from this development are discussed.

A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Graham, Paul S; Morgan, Keith S

2008-01-01

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA usermore » designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.« less

The dynamical analysis of modified two-compartment neuron model and FPGA implementation

NASA Astrophysics Data System (ADS)

Lin, Qianjin; Wang, Jiang; Yang, Shuangming; Yi, Guosheng; Deng, Bin; Wei, Xile; Yu, Haitao

2017-10-01

The complexity of neural models is increasing with the investigation of larger biological neural network, more various ionic channels and more detailed morphologies, and the implementation of biological neural network is a task with huge computational complexity and power consumption. This paper presents an efficient digital design using piecewise linearization on field programmable gate array (FPGA), to succinctly implement the reduced two-compartment model which retains essential features of more complicated models. The design proposes an approximate neuron model which is composed of a set of piecewise linear equations, and it can reproduce different dynamical behaviors to depict the mechanisms of a single neuron model. The consistency of hardware implementation is verified in terms of dynamical behaviors and bifurcation analysis, and the simulation results including varied ion channel characteristics coincide with the biological neuron model with a high accuracy. Hardware synthesis on FPGA demonstrates that the proposed model has reliable performance and lower hardware resource compared with the original two-compartment model. These investigations are conducive to scalability of biological neural network in reconfigurable large-scale neuromorphic system.

Volumetric visualization algorithm development for an FPGA-based custom computing machine

NASA Astrophysics Data System (ADS)

Sallinen, Sami J.; Alakuijala, Jyrki; Helminen, Hannu; Laitinen, Joakim

1998-05-01

Rendering volumetric medical images is a burdensome computational task for contemporary computers due to the large size of the data sets. Custom designed reconfigurable hardware could considerably speed up volume visualization if an algorithm suitable for the platform is used. We present an algorithm and speedup techniques for visualizing volumetric medical CT and MR images with a custom-computing machine based on a Field Programmable Gate Array (FPGA). We also present simulated performance results of the proposed algorithm calculated with a software implementation running on a desktop PC. Our algorithm is capable of generating perspective projection renderings of single and multiple isosurfaces with transparency, simulated X-ray images, and Maximum Intensity Projections (MIP). Although more speedup techniques exist for parallel projection than for perspective projection, we have constrained ourselves to perspective viewing, because of its importance in the field of radiotherapy. The algorithm we have developed is based on ray casting, and the rendering is sped up by three different methods: shading speedup by gradient precalculation, a new generalized version of Ray-Acceleration by Distance Coding (RADC), and background ray elimination by speculative ray selection.

Fault-Tolerant Software-Defined Radio on Manycore

NASA Technical Reports Server (NTRS)

Ricketts, Scott

2015-01-01

Software-defined radio (SDR) platforms generally rely on field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), but such architectures require significant software development. In addition, application demands for radiation mitigation and fault tolerance exacerbate programming challenges. MaXentric Technologies, LLC, has developed a manycore-based SDR technology that provides 100 times the throughput of conventional radiationhardened general purpose processors. Manycore systems (30-100 cores and beyond) have the potential to provide high processing performance at error rates that are equivalent to current space-deployed uniprocessor systems. MaXentric's innovation is a highly flexible radio, providing over-the-air reconfiguration; adaptability; and uninterrupted, real-time, multimode operation. The technology is also compliant with NASA's Space Telecommunications Radio System (STRS) architecture. In addition to its many uses within NASA communications, the SDR can also serve as a highly programmable research-stage prototyping device for new waveforms and other communications technologies. It can also support noncommunication codes on its multicore processor, collocated with the communications workload-reducing the size, weight, and power of the overall system by aggregating processing jobs to a single board computer.

Construction of a versatile SNP array for pyramiding useful genes of rice.

PubMed

Kurokawa, Yusuke; Noda, Tomonori; Yamagata, Yoshiyuki; Angeles-Shim, Rosalyn; Sunohara, Hidehiko; Uehara, Kanako; Furuta, Tomoyuki; Nagai, Keisuke; Jena, Kshirod Kumar; Yasui, Hideshi; Yoshimura, Atsushi; Ashikari, Motoyuki; Doi, Kazuyuki

2016-01-01

DNA marker-assisted selection (MAS) has become an indispensable component of breeding. Single nucleotide polymorphisms (SNP) are the most frequent polymorphism in the rice genome. However, SNP markers are not readily employed in MAS because of limitations in genotyping platforms. Here the authors report a Golden Gate SNP array that targets specific genes controlling yield-related traits and biotic stress resistance in rice. As a first step, the SNP genotypes were surveyed in 31 parental varieties using the Affymetrix Rice 44K SNP microarray. The haplotype information for 16 target genes was then converted to the Golden Gate platform with 143-plex markers. Haplotypes for the 14 useful allele are unique and can discriminate among all other varieties. The genotyping consistency between the Affymetrix microarray and the Golden Gate array was 92.8%, and the accuracy of the Golden Gate array was confirmed in 3 F2 segregating populations. The concept of the haplotype-based selection by using the constructed SNP array was proofed. Copyright © 2015 The Authors. Published by Elsevier Ireland Ltd.. All rights reserved.

Automatic Digital Hardware Synthesis

DTIC Science & Technology

1990-09-01

VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGAI using...process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate...allows the engineer to use VHDL to create and validate a design, and then to implement it in a gate array. The development of software o translate VHDL

FPGA implementation of a biological neural network based on the Hodgkin-Huxley neuron model

PubMed Central

Yaghini Bonabi, Safa; Asgharian, Hassan; Safari, Saeed; Nili Ahmadabadi, Majid

2014-01-01

A set of techniques for efficient implementation of Hodgkin-Huxley-based (H-H) model of a neural network on FPGA (Field Programmable Gate Array) is presented. The central implementation challenge is H-H model complexity that puts limits on the network size and on the execution speed. However, basics of the original model cannot be compromised when effect of synaptic specifications on the network behavior is the subject of study. To solve the problem, we used computational techniques such as CORDIC (Coordinate Rotation Digital Computer) algorithm and step-by-step integration in the implementation of arithmetic circuits. In addition, we employed different techniques such as sharing resources to preserve the details of model as well as increasing the network size in addition to keeping the network execution speed close to real time while having high precision. Implementation of a two mini-columns network with 120/30 excitatory/inhibitory neurons is provided to investigate the characteristic of our method in practice. The implementation techniques provide an opportunity to construct large FPGA-based network models to investigate the effect of different neurophysiological mechanisms, like voltage-gated channels and synaptic activities, on the behavior of a neural network in an appropriate execution time. Additional to inherent properties of FPGA, like parallelism and re-configurability, our approach makes the FPGA-based system a proper candidate for study on neural control of cognitive robots and systems as well. PMID:25484854

Reconfigurable Transmission Line for a Series-Fed Ku-Band Phased Array Using a Single Feed

NASA Technical Reports Server (NTRS)

Host, Nicholas K.; Chen, Chi-Chih; Volakis, John L.; Miranda. Felix, A.

2013-01-01

The paper presents a novel approach to realize a lowcost phased array using a simple feeding mechanism. Specifically, a single coplanar stripline (CPS) transmission line is used to feed the antenna array elements. By controlling the CPS's dielectric properties using a movable dielectric plunger, scanning is achieved. Due to its simplicity, single feed, and no phase shifters, this approach leads to a dramatic reduction in cost which does not scale for larger arrays.

Integration of reconfigurable potentiometric electrochemical sensors into a digital microfluidic platform.

PubMed

Farzbod, Ali; Moon, Hyejin

2018-05-30

This paper presents the demonstration of on-chip fabrication of a potassium-selective sensor array enabled by electrowetting on dielectric digital microfluidics for the first time. This demonstration proves the concept that electrochemical sensors can be seamlessly integrated with sample preparation units in a digital microfluidic platform. More significantly, the successful on-chip fabrication of a sensor array indicates that sensors become reconfigurable and have longer lifetime in a digital microfluidic platform. The on-chip fabrication of ion-selective electrodes includes electroplating Ag followed by forming AgCl layer by chemical oxidation and depositing a thin layer of desired polymer-based ion selective membrane on one of the sensor electrodes. In this study, potassium ionophores work as potassium ion channels and make the membrane selective to potassium ions. This selectiveness results in the voltage difference across the membrane layer, which is correlated with potassium ion concentration. The calibration curve of the fabricated potassium-selective electrode demonstrates the slope of 58 mV/dec for potassium concentration in KCl sample solutions and shows good agreement with the ideal Nernstian response. The proposed sensor platform is an outstanding candidate for a portable home-use for continuous monitoring of ions thanks to its advantages such as easy automation of sample preparation and detection processes, elongated sensor lifetime, minimal membrane and sample consumption, and user-definable/reconfigurable sensor array. Copyright © 2018 Elsevier B.V. All rights reserved.

Reconfigurable Embedded System for Electrocardiogram Acquisition.

PubMed

Kay, Marcel Seiji; Iaione, Fábio

2015-01-01

Smartphones include features that offers the chance to develop mobile systems in medical field, resulting in an area called mobile-health. One of the most common medical examinations is the electrocardiogram (ECG), which allows the diagnosis of various heart diseases, leading to preventative measures and preventing more serious problems. The objective of this study was to develop a wireless reconfigurable embedded system using a FPAA (Field Programmable Analog Array), for the acquisition of ECG signals, and an application showing and storing these signals on Android smartphones. The application also performs the partial FPAA reconfiguration in real time (adjustable gain). Previous studies using FPAA usually use the development boards provided by the manufacturer (high cost), do not allow the reconfiguration in real time, use no smartphone and communicate via cables. The parameters tested in the acquisition circuit and the quality of ECGs registered in an individual were satisfactory.

Evaluation of a reconfigurable portable instrument for copper determination based on luminescent carbon dots.

PubMed

Salinas-Castillo, Alfonso; Morales, Diego P; Lapresta-Fernández, Alejandro; Ariza-Avidad, María; Castillo, Encarnación; Martínez-Olmos, Antonio; Palma, Alberto J; Capitan-Vallvey, Luis Fermin

2016-04-01

A portable reconfigurable platform for copper (Cu(II)) determination based on luminescent carbon dot (Cdots) quenching is described. The electronic setup consists of a light-emitting diode (LED) as the carbon dot optical exciter and a photodiode as a light-to-current converter integrated in the same instrument. Moreover, the overall analog conditioning is simply performed with one integrated solution, a field-programmable analog array (FPAA), which makes it possible to reconfigure the filter and gain stages in real time. This feature provides adaptability to use the platform as an analytical probe for carbon dots coming from different batches with some variations in luminescence characteristics. The calibration functions obtained that fit a modified Stern-Volmer equation were obtained using luminescence signals from Cdots quenching by Cu(II). The analytical applicability of the reconfigurable portable instrument for Cu(II) using Cdots has been successfully demonstrated in tap water analysis.

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Characterization of a piezoelectric MEMS actuator surface toward motion-enabled reconfigurable RF circuits

NASA Astrophysics Data System (ADS)

Tellers, M. C.; Pulskamp, J. S.; Bedair, S. S.; Rudy, R. Q.; Kierzewski, I. M.; Polcawich, R. G.; Bergbreiter, S. E.

2018-03-01

As an alternative to highly constrained hard-wired reconfigurable RF circuits, a motion-enabled reconfigurable circuit (MERC) offers freedom from transmission line losses and homogeneous materials selection. The creation of a successful MERC requires a precise mechanical mechanism for relocating components. In this work, a piezoelectric MEMS actuator array is modeled and experimentally characterized to assess its viability as a solution to the MERC concept. Actuation and design parameters are evaluated, and the repeatability of high quality on-axis motion at greater than 1 mm s-1 is demonstrated with little positional error. Finally, an initial proof-of-concept circuit reconfiguration has been demonstrated using off-the-shelf RF filter components. Although initial feasibility tests show filter performance degradation with an additional insertion loss of 0.3 dB per contact, out-of-band rejection degradation as high as 10 dB, and ripple performance reduction from 0.25 dB to 1.5 dB, MERC is proven here as an alternative to traditional approaches used in reconfigurable RF circuit applications.

2D Traveling Wave Array Employing a Trapezoidal Dielectric Wedge for Beam Steering

NASA Technical Reports Server (NTRS)

Host, Nicholas K.; Chen, Chi-Chih; Volakis, John L.; Miranada, Felix A.

2014-01-01

This presentation addresses the progress made so far in the development of an antenna array with reconfigurable transmission line feeds connecting each element in series. In particular, 2D traveling wave array employing trapezoidal Dielectric Wedge for Beam Steering will be discussed. The presentation includes current status of the effort and suggested future work. The work is being done as part of the NASA Office of the Chief Technologist's Space Technology Research Fellowship (NSTRF).

Dynamically Reconfigurable Systolic Array Accelorators

NASA Technical Reports Server (NTRS)

Dasu, Aravind (Inventor); Barnes, Robert C. (Inventor)

2014-01-01

A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

Real-time windowing in imaging radar using FPGA technique

NASA Astrophysics Data System (ADS)

Ponomaryov, Volodymyr I.; Escamilla-Hernandez, Enrique

2005-02-01

The imaging radar uses the high frequency electromagnetic waves reflected from different objects for estimating of its parameters. Pulse compression is a standard signal processing technique used to minimize the peak transmission power and to maximize SNR, and to get a better resolution. Usually the pulse compression can be achieved using a matched filter. The level of the side-lobes in the imaging radar can be reduced using the special weighting function processing. There are very known different weighting functions: Hamming, Hanning, Blackman, Chebyshev, Blackman-Harris, Kaiser-Bessel, etc., widely used in the signal processing applications. Field Programmable Gate Arrays (FPGAs) offers great benefits like instantaneous implementation, dynamic reconfiguration, design, and field programmability. This reconfiguration makes FPGAs a better solution over custom-made integrated circuits. This work aims at demonstrating a reasonably flexible implementation of FM-linear signal and pulse compression using Matlab, Simulink, and System Generator. Employing FPGA and mentioned software we have proposed the pulse compression design on FPGA using classical and novel windows technique to reduce the side-lobes level. This permits increasing the detection ability of the small or nearly placed targets in imaging radar. The advantage of FPGA that can do parallelism in real time processing permits to realize the proposed algorithms. The paper also presents the experimental results of proposed windowing procedure in the marine radar with such the parameters: signal is linear FM (Chirp); frequency deviation DF is 9.375MHz; the pulse width T is 3.2μs taps number in the matched filter is 800 taps; sampling frequency 253.125*106 MHz. It has been realized the reducing of side-lobes levels in real time permitting better resolution of the small targets.

HDL Based FPGA Interface Library for Data Acquisition and Multipurpose Real Time Algorithms

NASA Astrophysics Data System (ADS)

Fernandes, Ana M.; Pereira, R. C.; Sousa, J.; Batista, A. J. N.; Combo, A.; Carvalho, B. B.; Correia, C. M. B. A.; Varandas, C. A. F.

2011-08-01

The inherent parallelism of the logic resources, the flexibility in its configuration and the performance at high processing frequencies makes the field programmable gate array (FPGA) the most suitable device to be used both for real time algorithm processing and data transfer in instrumentation modules. Moreover, the reconfigurability of these FPGA based modules enables exploiting different applications on the same module. When using a reconfigurable module for various applications, the availability of a common interface library for easier implementation of the algorithms on the FPGA leads to more efficient development. The FPGA configuration is usually specified in a hardware description language (HDL) or other higher level descriptive language. The critical paths, such as the management of internal hardware clocks that require deep knowledge of the module behavior shall be implemented in HDL to optimize the timing constraints. The common interface library should include these critical paths, freeing the application designer from hardware complexity and able to choose any of the available high-level abstraction languages for the algorithm implementation. With this purpose a modular Verilog code was developed for the Virtex 4 FPGA of the in-house Transient Recorder and Processor (TRP) hardware module, based on the Advanced Telecommunications Computing Architecture (ATCA), with eight channels sampling at up to 400 MSamples/s (MSPS). The TRP was designed to perform real time Pulse Height Analysis (PHA), Pulse Shape Discrimination (PSD) and Pile-Up Rejection (PUR) algorithms at a high count rate (few Mevent/s). A brief description of this modular code is presented and examples of its use as an interface with end user algorithms, including a PHA with PUR, are described.

Evolution of Analog Circuits on Field Programmable Transistor Arrays

NASA Technical Reports Server (NTRS)

Stoica, A.; Keymeulen, D.; Zebulum, R.; Thakoor, A.; Daud, T.; Klimeck, G.; Jin, Y.; Tawel, R.; Duong, V.

2000-01-01

Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications.

Multiple Solutions for Reconfiguration to Address Partial Shading Losses in Solar Photovoltaic Arrays

NASA Astrophysics Data System (ADS)

Sharma, Nikesh; Pareek, Smita; Chaturvedi, Nitin; Dahiya, Ratna

2018-03-01

Solar photovoltaic (SPV) systems are steadily rising and considered as the best alternatives to meet the rising demand of energy. In developing countries like India, SPV’s contribution being a clean energy is the most favourable. However, experiences have shown that produced power of these systems is usually affected due to day, night, seasonal variations, insolation, partial shading conditions etc. Among these parameters, partial shading causes a huge reduction in output power of PV systems. This results in lack of confidence for this technology among users. Thus, it is important and a major challenge in PV systems to minimize the effect of partial shading on their energy production. The work in this paper aims to propose solutions for reconfiguration of solar photovoltaic arrays in order to reduce partial shading losses and thus to enhance power generation.

A simple laser locking system based on a field-programmable gate array.

PubMed

Jørgensen, N B; Birkmose, D; Trelborg, K; Wacker, L; Winter, N; Hilliard, A J; Bason, M G; Arlt, J J

2016-07-01

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The locking system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.

A simple laser locking system based on a field-programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jørgensen, N. B.; Birkmose, D.; Trelborg, K.

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The lockingmore » system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.« less

Spatial mapping and statistical reproducibility of an array of 256 one-dimensional quantum wires

NASA Astrophysics Data System (ADS)

Al-Taie, H.; Smith, L. W.; Lesage, A. A. J.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2015-08-01

We utilize a multiplexing architecture to measure the conductance properties of an array of 256 split gates. We investigate the reproducibility of the pinch off and one-dimensional definition voltage as a function of spatial location on two different cooldowns, and after illuminating the device. The reproducibility of both these properties on the two cooldowns is high, the result of the density of the two-dimensional electron gas returning to a similar state after thermal cycling. The spatial variation of the pinch-off voltage reduces after illumination; however, the variation of the one-dimensional definition voltage increases due to an anomalous feature in the center of the array. A technique which quantifies the homogeneity of split-gate properties across the array is developed which captures the experimentally observed trends. In addition, the one-dimensional definition voltage is used to probe the density of the wafer at each split gate in the array on a micron scale using a capacitive model.

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

NASA Astrophysics Data System (ADS)

Butta, Mattia; Janosek, Michal; Ripka, Pavel

2010-05-01

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

Pseudo-diode based on protonic/electronic hybrid oxide transistor

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

ASRC Aerospace Corporation Selects Dynamically Reconfigurable Anadigm(Registered Trademark) FPAA For Advanced Data Acquisition System

NASA Technical Reports Server (NTRS)

Mata, Carlos T.

2003-01-01

Anadigm(registered trademark) today announced that ASRC Aerospace Corporation has designed Anadigm's dynamically reconfigurable Field Programmable Analog Array (FPAA) technology into an advanced data acquisition system developed under contract for NASA. ASRC Aerospace designed in the Anadigm(registered trademark) FPAA to provide complex analog signal conditioning in its intelligent, self-calibrating, and self-healing advanced data acquisition system (ADAS). The ADAS has potential applications in industrial, manufacturing, and aerospace markets. This system offers highly reliable operation while reducing the need for user interaction. Anadigm(registered trademark)'s dynamically reconfigurable FPAAs can be reconfigured in-system by the designer or on the fly by a microprocessor. A single device can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to maintain precision operation despite system degradation and aging. In the case of the ASRC advanced data acquisition system, the FPAA helps ensure that the system will continue to operating at 100% functionality despite changes in the environment, component degradation, and/or component failures.

Rapidly reconfigurable high-fidelity optical arbitrary waveform generation in heterogeneous photonic integrated circuits.

PubMed

Feng, Shaoqi; Qin, Chuan; Shang, Kuanping; Pathak, Shibnath; Lai, Weicheng; Guan, Binbin; Clements, Matthew; Su, Tiehui; Liu, Guangyao; Lu, Hongbo; Scott, Ryan P; Ben Yoo, S J

2017-04-17

This paper demonstrates rapidly reconfigurable, high-fidelity optical arbitrary waveform generation (OAWG) in a heterogeneous photonic integrated circuit (PIC). The heterogeneous PIC combines advantages of high-speed indium phosphide (InP) modulators and low-loss, high-contrast silicon nitride (Si₃N₄) arrayed waveguide gratings (AWGs) so that high-fidelity optical waveform syntheses with rapid waveform updates are possible. The generated optical waveforms spanned a 160 GHz spectral bandwidth starting from an optical frequency comb consisting of eight comb lines separated by 20 GHz channel spacing. The Error Vector Magnitude (EVM) values of the generated waveforms were approximately 16.4%. The OAWG module can rapidly and arbitrarily reconfigure waveforms upon every pulse arriving at 2 ns repetition time. The result of this work indicates the feasibility of truly dynamic optical arbitrary waveform generation where the reconfiguration rate or the modulator bandwidth must exceed the channel spacing of the AWG and the optical frequency comb.

Dynamically reconfigurable optical packet switch (DROPS)

NASA Astrophysics Data System (ADS)

Huang, Chi-Heng; Chou, Hsu-Feng; Bowers, John E.; Toudeh-Fallah, Farzam; Gyurek, Russ

2006-12-01

A novel Dynamically Reconfigurable Optical Packet Switch (DROPS) that combines both spectral and spatial switching capabilities is proposed and experimentally demonstrated for the first time. Compared with an Arrayed Waveguide Grating Router (AWGR), the added spatial switching capability provided by the microelectromechanical systems (MEMS) enables dynamically reconfigurable routing that is not possible with an AWGR alone. This methodology has several advantages over an AWGR including scalability, additional degrees of freedom in routing a packet from an ingress port to an egress port and more flexibility in path or line card recovery. The experimental demonstration implemented with 10-Gb/s packets shows that the added spatial switching does not degrade the bit-error-rate performance, indicating the promising potential of DROPS as a versatile and ultra-high capacity switch for optical packet-switched networks.

Efficient Graph Based Assembly of Short-Read Sequences on Hybrid Core Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sczyrba, Alex; Pratap, Abhishek; Canon, Shane

2011-03-22

Advanced architectures can deliver dramatically increased throughput for genomics and proteomics applications, reducing time-to-completion in some cases from days to minutes. One such architecture, hybrid-core computing, marries a traditional x86 environment with a reconfigurable coprocessor, based on field programmable gate array (FPGA) technology. In addition to higher throughput, increased performance can fundamentally improve research quality by allowing more accurate, previously impractical approaches. We will discuss the approach used by Convey?s de Bruijn graph constructor for short-read, de-novo assembly. Bioinformatics applications that have random access patterns to large memory spaces, such as graph-based algorithms, experience memory performance limitations on cache-based x86more » servers. Convey?s highly parallel memory subsystem allows application-specific logic to simultaneously access 8192 individual words in memory, significantly increasing effective memory bandwidth over cache-based memory systems. Many algorithms, such as Velvet and other de Bruijn graph based, short-read, de-novo assemblers, can greatly benefit from this type of memory architecture. Furthermore, small data type operations (four nucleotides can be represented in two bits) make more efficient use of logic gates than the data types dictated by conventional programming models.JGI is comparing the performance of Convey?s graph constructor and Velvet on both synthetic and real data. We will present preliminary results on memory usage and run time metrics for various data sets with different sizes, from small microbial and fungal genomes to very large cow rumen metagenome. For genomes with references we will also present assembly quality comparisons between the two assemblers.« less

RHrFPGA Radiation-Hardened Re-programmable Field-Programmable Gate Array

NASA Technical Reports Server (NTRS)

Sanders, A. B.; LaBel, K. A.; McCabe, J. F.; Gardner, G. A.; Lintz, J.; Ross, C.; Golke, K.; Burns, B.; Carts, M. A.; Kim, H. S.

2004-01-01

Viewgraphs on the development of the Radiation-Hardened Re-programmable Field-Programmable Gate Array (RHrFPGA) are presented. The topics include: 1) Radiation Test Suite; 2) Testing Interface; 3) Test Configuration; 4) Facilities; 5) Test Programs; 6) Test Procedure; and 7) Test Results. A summary of heavy ion and proton testing is also included.

An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays

ERIC Educational Resources Information Center

Meyer-Base, U.; Vera, A.; Meyer-Base, A.; Pattichis, M. S.; Perry, R. J.

2010-01-01

In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the…

Optical microwave filter based on spectral slicing by use of arrayed waveguide gratings.

PubMed

Pastor, Daniel; Ortega, Beatriz; Capmany, José; Sales, Salvador; Martinez, Alfonso; Muñoz, Pascual

2003-10-01

We have experimentally demonstrated a new optical signal processor based on the use of arrayed waveguide gratings. The structure exploits the concept of spectral slicing combined with the use of an optical dispersive medium. The approach presents increased flexibility from previous slicing-based structures in terms of tunability, reconfiguration, and apodization of the samples or coefficients of the transversal optical filter.

Energy efficiency analysis and implementation of AES on an FPGA

NASA Astrophysics Data System (ADS)

Kenney, David

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

How do bendy straws bend? A study of re-configurability of multi-stable corrugated shells

NASA Astrophysics Data System (ADS)

Bende, Nakul; Selden, Sarah; Evans, Arthur; Santangelo, Christian; Hayward, Ryan

Shape programmable systems have evolved to allow for reconfiguration of structures through a variety of mechanisms including swelling, stress-relaxation, and thermal expansion. Particularly, there has been a recent interest in systems that exhibit bi-stability or multi-stability to achieve transformation between two or more pre-programmed states. Here, we study the ubiquitous architecture of corrugated shells, such as drinking straws or bellows, which has been well known for centuries. Some of these structures exhibit almost continuous stability amongst a wide range of reconfigurable shapes, but the underlying mechanisms are not well understood. To understand multi-stability in `bendy-straw' structures, we study the unit bi-conical segment using experiments and finite element modeling to elucidate the key geometrical and mechanical factors responsible for its multi-stability. The simple transformations of a unit segment - a change in length or angle can impart complex re-configurability of a structure containing many of these units. The fundamental understanding provided of this simple multi-stable building block could yield improvements in shape re-configurability for a wide array of applications such as corrugated medical tubing, robotics, and deployable structures. NSF EFRI ODISSEI-1240441.

Dynamically programmable cache

NASA Astrophysics Data System (ADS)

Nakkar, Mouna; Harding, John A.; Schwartz, David A.; Franzon, Paul D.; Conte, Thomas

1998-10-01

Reconfigurable machines have recently been used as co- processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: (1) the small on-chip memory which results in slower execution time, and (2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory access problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implemented multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X faster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).

Architecutres, Models, Algorithms, and Software Tools for Configurable Computing

DTIC Science & Technology

2000-03-06

and J.G. Nash. The gated interconnection network for dynamic programming. Plenum, 1988 . [18] Ju wook Jang, Heonchul Park, and Viktor K. Prasanna. A ...Sep. 1997. [2] C. Ebeling, D. C. Cronquist , P. Franklin and C. Fisher, "RaPiD - A configurable computing architecture for compute-intensive...ABSTRACT (Maximum 200 words) The Models, Algorithms, and Architectures for Reconfigurable Computing (MAARC) project developed a sound framework for

Reconfigurable phased antenna array for extending cubesat operations to Ka-band: Design and feasibility

NASA Astrophysics Data System (ADS)

Buttazzoni, G.; Comisso, M.; Cuttin, A.; Fragiacomo, M.; Vescovo, R.; Vincenti Gatti, R.

2017-08-01

Started as educational tools, CubeSats have immediately encountered the favor of the scientific community, subsequently becoming viable platforms for research and commercial applications. To ensure competitive data rates, some pioneers have started to explore the usage of the Ka-band beside the conventional amateur radio frequencies. In this context, this study proposes a phased antenna array design for Ka-band downlink operations consisting of 8×8 circularly polarized subarrays of microstrip patches filling one face of a single CubeSat unit. The conceived structure is developed to support 1.5 GHz bandwidth and dual-task missions, whose feasibility is verified by proper link budgets. The dual-task operations are enabled by a low-complexity phase-only control algorithm that provides pattern reconfigurability in order to satisfy both orbiting and intersatellite missions, while remaining adherent to the cost-effective CubeSat paradigm.

Finite Element Methods for real-time Haptic Feedback of Soft-Tissue Models in Virtual Reality Simulators

NASA Technical Reports Server (NTRS)

Frank, Andreas O.; Twombly, I. Alexander; Barth, Timothy J.; Smith, Jeffrey D.; Dalton, Bonnie P. (Technical Monitor)

2001-01-01

We have applied the linear elastic finite element method to compute haptic force feedback and domain deformations of soft tissue models for use in virtual reality simulators. Our results show that, for virtual object models of high-resolution 3D data (>10,000 nodes), haptic real time computations (>500 Hz) are not currently possible using traditional methods. Current research efforts are focused in the following areas: 1) efficient implementation of fully adaptive multi-resolution methods and 2) multi-resolution methods with specialized basis functions to capture the singularity at the haptic interface (point loading). To achieve real time computations, we propose parallel processing of a Jacobi preconditioned conjugate gradient method applied to a reduced system of equations resulting from surface domain decomposition. This can effectively be achieved using reconfigurable computing systems such as field programmable gate arrays (FPGA), thereby providing a flexible solution that allows for new FPGA implementations as improved algorithms become available. The resulting soft tissue simulation system would meet NASA Virtual Glovebox requirements and, at the same time, provide a generalized simulation engine for any immersive environment application, such as biomedical/surgical procedures or interactive scientific applications.

Runtime verification of embedded real-time systems.

PubMed

Reinbacher, Thomas; Függer, Matthias; Brauer, Jörg

We present a runtime verification framework that allows on-line monitoring of past-time Metric Temporal Logic (ptMTL) specifications in a discrete time setting. We design observer algorithms for the time-bounded modalities of ptMTL, which take advantage of the highly parallel nature of hardware designs. The algorithms can be translated into efficient hardware blocks, which are designed for reconfigurability, thus, facilitate applications of the framework in both a prototyping and a post-deployment phase of embedded real-time systems. We provide formal correctness proofs for all presented observer algorithms and analyze their time and space complexity. For example, for the most general operator considered, the time-bounded Since operator, we obtain a time complexity that is doubly logarithmic both in the point in time the operator is executed and the operator's time bounds. This result is promising with respect to a self-contained, non-interfering monitoring approach that evaluates real-time specifications in parallel to the system-under-test. We implement our framework on a Field Programmable Gate Array platform and use extensive simulation and logic synthesis runs to assess the benefits of the approach in terms of resource usage and operating frequency.

The Interplanetary Overlay Networking Protocol Accelerator

NASA Technical Reports Server (NTRS)

Pang, Jackson; Torgerson, Jordan L.; Clare, Loren P.

2008-01-01

A document describes the Interplanetary Overlay Networking Protocol Accelerator (IONAC) an electronic apparatus, now under development, for relaying data at high rates in spacecraft and interplanetary radio-communication systems utilizing a delay-tolerant networking protocol. The protocol includes provisions for transmission and reception of data in bundles (essentially, messages), transfer of custody of a bundle to a recipient relay station at each step of a relay, and return receipts. Because of limitations on energy resources available for such relays, data rates attainable in a conventional software implementation of the protocol are lower than those needed, at any given reasonable energy-consumption rate. Therefore, a main goal in developing the IONAC is to reduce the energy consumption by an order of magnitude and the data-throughput capability by two orders of magnitude. The IONAC prototype is a field-programmable gate array that serves as a reconfigurable hybrid (hardware/ firmware) system for implementation of the protocol. The prototype can decode 108,000 bundles per second and encode 100,000 bundles per second. It includes a bundle-cache static randomaccess memory that enables maintenance of a throughput of 2.7Gb/s, and an Ethernet convergence layer that supports a duplex throughput of 1Gb/s.

Fused smart sensor network for multi-axis forward kinematics estimation in industrial robots.

PubMed

Rodriguez-Donate, Carlos; Osornio-Rios, Roque Alfredo; Rivera-Guillen, Jesus Rooney; Romero-Troncoso, Rene de Jesus

2011-01-01

Flexible manipulator robots have a wide industrial application. Robot performance requires sensing its position and orientation adequately, known as forward kinematics. Commercially available, motion controllers use high-resolution optical encoders to sense the position of each joint which cannot detect some mechanical deformations that decrease the accuracy of the robot position and orientation. To overcome those problems, several sensor fusion methods have been proposed but at expenses of high-computational load, which avoids the online measurement of the joint's angular position and the online forward kinematics estimation. The contribution of this work is to propose a fused smart sensor network to estimate the forward kinematics of an industrial robot. The developed smart processor uses Kalman filters to filter and to fuse the information of the sensor network. Two primary sensors are used: an optical encoder, and a 3-axis accelerometer. In order to obtain the position and orientation of each joint online a field-programmable gate array (FPGA) is used in the hardware implementation taking advantage of the parallel computation capabilities and reconfigurability of this device. With the aim of evaluating the smart sensor network performance, three real-operation-oriented paths are executed and monitored in a 6-degree of freedom robot.

Efficient architecture for spike sorting in reconfigurable hardware.

PubMed

Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

2013-11-01

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

A programmable metasurface with dynamic polarization, scattering and focusing control

NASA Astrophysics Data System (ADS)

Yang, Huanhuan; Cao, Xiangyu; Yang, Fan; Gao, Jun; Xu, Shenheng; Li, Maokun; Chen, Xibi; Zhao, Yi; Zheng, Yuejun; Li, Sijia

2016-10-01

Diverse electromagnetic (EM) responses of a programmable metasurface with a relatively large scale have been investigated, where multiple functionalities are obtained on the same surface. The unit cell in the metasurface is integrated with one PIN diode, and thus a binary coded phase is realized for a single polarization. Exploiting this anisotropic characteristic, reconfigurable polarization conversion is presented first. Then the dynamic scattering performance for two kinds of sources, i.e. a plane wave and a point source, is carefully elaborated. To tailor the scattering properties, genetic algorithm, normally based on binary coding, is coupled with the scattering pattern analysis to optimize the coding matrix. Besides, inverse fast Fourier transform (IFFT) technique is also introduced to expedite the optimization process of a large metasurface. Since the coding control of each unit cell allows a local and direct modulation of EM wave, various EM phenomena including anomalous reflection, diffusion, beam steering and beam forming are successfully demonstrated by both simulations and experiments. It is worthwhile to point out that a real-time switch among these functionalities is also achieved by using a field-programmable gate array (FPGA). All the results suggest that the proposed programmable metasurface has great potentials for future applications.

A programmable metasurface with dynamic polarization, scattering and focusing control

PubMed Central

Yang, Huanhuan; Cao, Xiangyu; Yang, Fan; Gao, Jun; Xu, Shenheng; Li, Maokun; Chen, Xibi; Zhao, Yi; Zheng, Yuejun; Li, Sijia

2016-01-01

Diverse electromagnetic (EM) responses of a programmable metasurface with a relatively large scale have been investigated, where multiple functionalities are obtained on the same surface. The unit cell in the metasurface is integrated with one PIN diode, and thus a binary coded phase is realized for a single polarization. Exploiting this anisotropic characteristic, reconfigurable polarization conversion is presented first. Then the dynamic scattering performance for two kinds of sources, i.e. a plane wave and a point source, is carefully elaborated. To tailor the scattering properties, genetic algorithm, normally based on binary coding, is coupled with the scattering pattern analysis to optimize the coding matrix. Besides, inverse fast Fourier transform (IFFT) technique is also introduced to expedite the optimization process of a large metasurface. Since the coding control of each unit cell allows a local and direct modulation of EM wave, various EM phenomena including anomalous reflection, diffusion, beam steering and beam forming are successfully demonstrated by both simulations and experiments. It is worthwhile to point out that a real-time switch among these functionalities is also achieved by using a field-programmable gate array (FPGA). All the results suggest that the proposed programmable metasurface has great potentials for future applications. PMID:27774997

A programmable metasurface with dynamic polarization, scattering and focusing control.

PubMed

Yang, Huanhuan; Cao, Xiangyu; Yang, Fan; Gao, Jun; Xu, Shenheng; Li, Maokun; Chen, Xibi; Zhao, Yi; Zheng, Yuejun; Li, Sijia

2016-10-24

Diverse electromagnetic (EM) responses of a programmable metasurface with a relatively large scale have been investigated, where multiple functionalities are obtained on the same surface. The unit cell in the metasurface is integrated with one PIN diode, and thus a binary coded phase is realized for a single polarization. Exploiting this anisotropic characteristic, reconfigurable polarization conversion is presented first. Then the dynamic scattering performance for two kinds of sources, i.e. a plane wave and a point source, is carefully elaborated. To tailor the scattering properties, genetic algorithm, normally based on binary coding, is coupled with the scattering pattern analysis to optimize the coding matrix. Besides, inverse fast Fourier transform (IFFT) technique is also introduced to expedite the optimization process of a large metasurface. Since the coding control of each unit cell allows a local and direct modulation of EM wave, various EM phenomena including anomalous reflection, diffusion, beam steering and beam forming are successfully demonstrated by both simulations and experiments. It is worthwhile to point out that a real-time switch among these functionalities is also achieved by using a field-programmable gate array (FPGA). All the results suggest that the proposed programmable metasurface has great potentials for future applications.

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

PubMed Central

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

PubMed

Cheung, Kit; Schultz, Simon R; Luk, Wayne

2015-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

Training a molecular automaton to play a game

NASA Astrophysics Data System (ADS)

Pei, Renjun; Matamoros, Elizabeth; Liu, Manhong; Stefanovic, Darko; Stojanovic, Milan N.

2010-11-01

Research at the interface between chemistry and cybernetics has led to reports of `programmable molecules', but what does it mean to say `we programmed a set of solution-phase molecules to do X'? A survey of recently implemented solution-phase circuitry indicates that this statement could be replaced with `we pre-mixed a set of molecules to do X and functional subsets of X'. These hard-wired mixtures are then exposed to a set of molecular inputs, which can be interpreted as being keyed to human moves in a game, or as assertions of logical propositions. In nucleic acids-based systems, stemming from DNA computation, these inputs can be seen as generic oligonucleotides. Here, we report using reconfigurable nucleic acid catalyst-based units to build a multipurpose reprogrammable molecular automaton that goes beyond single-purpose `hard-wired' molecular automata. The automaton covers all possible responses to two consecutive sets of four inputs (such as four first and four second moves for a generic set of trivial two-player two-move games). This is a model system for more general molecular field programmable gate array (FPGA)-like devices that can be programmed by example, which means that the operator need not have any knowledge of molecular computing methods.

Launching GUPPI: the Green Bank Ultimate Pulsar Processing Instrument

NASA Astrophysics Data System (ADS)

DuPlain, Ron; Ransom, Scott; Demorest, Paul; Brandt, Patrick; Ford, John; Shelton, Amy L.

2008-08-01

The National Radio Astronomy Observatory (NRAO) is launching the Green Bank Ultimate Pulsar Processing Instrument (GUPPI), a prototype flexible digital signal processor designed for pulsar observations with the Robert C. Byrd Green Bank Telescope (GBT). GUPPI uses field programmable gate array (FPGA) hardware and design tools developed by the Center for Astronomy Signal Processing and Electronics Research (CASPER) at the University of California, Berkeley. The NRAO has been concurrently developing GUPPI software and hardware using minimal software resources. The software handles instrument monitor and control, data acquisition, and hardware interfacing. GUPPI is currently an expert-only spectrometer, but supports future integration with the full GBT production system. The NRAO was able to take advantage of the unique flexibility of the CASPER FPGA hardware platform, develop hardware and software in parallel, and build a suite of software tools for monitoring, controlling, and acquiring data with a new instrument over a short timeline of just a few months. The NRAO interacts regularly with CASPER and its users, and GUPPI stands as an example of what reconfigurable computing and open-source development can do for radio astronomy. GUPPI is modular for portability, and the NRAO provides the results of development as an open-source resource.

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

PubMed Central

Cheung, Kit; Schultz, Simon R.; Luk, Wayne

2016-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation. PMID:26834542

Mechanically tunable terahertz graphene plasmonics using soft metasurface

NASA Astrophysics Data System (ADS)

Wang, Li; Liu, Xin; Zang, Jianfeng

2016-12-01

This letter presents a new approach to continuously tune the resonances of graphene plasmons in terahertz soft metasurface. The continuous tunability of plasmon resonance is either unachievable in conventional plasmonic materials like noble metals or requires gate voltage regulation in graphene. Here we investigate a simplest form of terahertz metasurface, graphene nanoribbon arrays (GNRAs), and demonstrate the graphene plasmon resonance modes can be tailored by mechanical deformation of the elastomeric substrate using finite element method (FEM). By integrating the electric doping with substrate deformation, we have managed to tune the resonance wavelength from 13.7 to 50.6 μm. The 36.9 μm tuning range is nearly doubled compared with that by electric doping regulation only. Moreover, we observe the plasmon coupling effect in GNRAs on waved substrate and its evolution with substrate curvature. A new decoupling mechanism enabled by the out-of-plane separation of the adjacent ribbons is revealed. The out-of-plane setup of plasmonic components extends the fabrication of plasmonic devices into three-dimensional space, which simultaneously increases the nanoribbon density and decreases the coupling strength. Our findings provide an additional degree of freedom to design reconfigurable metasurfaces and metadevices.

Training a molecular automaton to play a game.

PubMed

Pei, Renjun; Matamoros, Elizabeth; Liu, Manhong; Stefanovic, Darko; Stojanovic, Milan N

2010-11-01

Research at the interface between chemistry and cybernetics has led to reports of 'programmable molecules', but what does it mean to say 'we programmed a set of solution-phase molecules to do X'? A survey of recently implemented solution-phase circuitry indicates that this statement could be replaced with 'we pre-mixed a set of molecules to do X and functional subsets of X'. These hard-wired mixtures are then exposed to a set of molecular inputs, which can be interpreted as being keyed to human moves in a game, or as assertions of logical propositions. In nucleic acids-based systems, stemming from DNA computation, these inputs can be seen as generic oligonucleotides. Here, we report using reconfigurable nucleic acid catalyst-based units to build a multipurpose reprogrammable molecular automaton that goes beyond single-purpose 'hard-wired' molecular automata. The automaton covers all possible responses to two consecutive sets of four inputs (such as four first and four second moves for a generic set of trivial two-player two-move games). This is a model system for more general molecular field programmable gate array (FPGA)-like devices that can be programmed by example, which means that the operator need not have any knowledge of molecular computing methods.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Implementation and Performance of GaAs Digital Signal Processing ASICs

NASA Technical Reports Server (NTRS)

Whitaker, William D.; Buchanan, Jeffrey R.; Burke, Gary R.; Chow, Terrance W.; Graham, J. Scott; Kowalski, James E.; Lam, Barbara; Siavoshi, Fardad; Thompson, Matthew S.; Johnson, Robert A.

1993-01-01

The feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.

Ferroelectric/Semiconductor Tunable Microstrip Patch Antenna Developed

NASA Technical Reports Server (NTRS)

Romanofsky, Robert R.

2001-01-01

A lithographically printed microwave antenna that can be switched and tuned has been developed. The structure consists of a rectangular metallic "patch" radiator patterned on a thin ferroelectric film that was grown on high-resistivity silicon. Such an antenna may one day enable a single-phased array aperture to transmit and receive signals at different frequencies, or it may provide a simple way to reconfigure fractal arrays for communications and radar applications.

Dynamic partial reconfiguration of logic controllers implemented in FPGAs

NASA Astrophysics Data System (ADS)

Bazydło, Grzegorz; Wiśniewski, Remigiusz

2016-09-01

Technological progress in recent years benefits in digital circuits containing millions of logic gates with the capability for reprogramming and reconfiguring. On the one hand it provides the unprecedented computational power, but on the other hand the modelled systems are becoming increasingly complex, hierarchical and concurrent. Therefore, abstract modelling supported by the Computer Aided Design tools becomes a very important task. Even the higher consumption of the basic electronic components seems to be acceptable because chip manufacturing costs tend to fall over the time. The paper presents a modelling approach for logic controllers with the use of Unified Modelling Language (UML). Thanks to the Model Driven Development approach, starting with a UML state machine model, through the construction of an intermediate Hierarchical Concurrent Finite State Machine model, a collection of Verilog files is created. The system description generated in hardware description language can be synthesized and implemented in reconfigurable devices, such as FPGAs. Modular specification of the prototyped controller permits for further dynamic partial reconfiguration of the prototyped system. The idea bases on the exchanging of the functionality of the already implemented controller without stopping of the FPGA device. It means, that a part (for example a single module) of the logic controller is replaced by other version (called context), while the rest of the system is still running. The method is illustrated by a practical example by an exemplary Home Area Network system.

Reconfigurable signal processor designs for advanced digital array radar systems

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Vanadium dioxide based frequency tunable metasurface filters for realizing reconfigurable terahertz optical phase and polarization control.

PubMed

Nouman, M Tayyab; Hwang, Ji Hyun; Faiyaz, Mohd; Lee, Kye-Jeong; Noh, Do-Young; Jang, Jae-Hyung

2018-05-14

Metasurfaces are two dimensional arrays of artificial subwavelength resonators, which can manipulate the amplitude and phase profile of incident electromagnetic fields. To date, limited progress has been achieved in realizing reconfigurable phase control of incident waves using metasurfaces. Here, an active metasurface is presented, whose resonance frequency can be tuned by employing insulator to metal transition in vanadium dioxide. By virtue of the phase jump accompanied by the resonance frequency tuning, the proposed metasurface acts as a phase shifter at THz frequency. It is further demonstrated that by appropriately tailoring the anisotropy of the metasurface, the observed phase shift can be used to switch the transmitted polarization from circular to approximately linear. This work thus shows potential for reconfigurable phase and polarization control at THz frequencies using vanadium dioxide based frequency tunable metasurfaces.

Dynamically re-configurable CMOS imagers for an active vision system

NASA Technical Reports Server (NTRS)

Yang, Guang (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

A vision system is disclosed. The system includes a pixel array, at least one multi-resolution window operation circuit, and a pixel averaging circuit. The pixel array has an array of pixels configured to receive light signals from an image having at least one tracking target. The multi-resolution window operation circuits are configured to process the image. Each of the multi-resolution window operation circuits processes each tracking target within a particular multi-resolution window. The pixel averaging circuit is configured to sample and average pixels within the particular multi-resolution window.

Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth; Kim, Hak

2014-01-01

An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

Computing the Algebraic Immunity of Boolean Functions on the SRC-6 Reconfigurable Computer

DTIC Science & Technology

2012-03-01

and Budget, Paperwork Reduction Project (0704-0188) Washington DC 20503. 1. AGENCY USE ONLY (Leave blank) 2 . REPORT DATE March 2012 3. REPORT... CA 93943-5000 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING /MONITORING AGENCY NAME(S) AND ADDRESS(ES) N/A 10. SPONSORING...developed for this conversion. This reduced form requires many fewer gates and has ( )n delay versus ( 2 ) n delay for a full transeunt triangle

Scaling Trapped Ion Quantum Computers Using Fast Gates and Microtraps

NASA Astrophysics Data System (ADS)

Ratcliffe, Alexander K.; Taylor, Richard L.; Hope, Joseph J.; Carvalho, André R. R.

2018-06-01

Most attempts to produce a scalable quantum information processing platform based on ion traps have focused on the shuttling of ions in segmented traps. We show that an architecture based on an array of microtraps with fast gates will outperform architectures based on ion shuttling. This system requires higher power lasers but does not require the manipulation of potentials or shuttling of ions. This improves optical access, reduces the complexity of the trap, and reduces the number of conductive surfaces close to the ions. The use of fast gates also removes limitations on the gate time. Error rates of 10-5 are shown to be possible with 250 mW laser power and a trap separation of 100 μ m . The performance of the gates is shown to be robust to the limitations in the laser repetition rate and the presence of many ions in the trap array.

Symmetric reconfigurable capacity assignment in a bidirectional DWDM access network.

PubMed

Ortega, Beatriz; Mora, José; Puerto, Gustavo; Capmany, José

2007-12-10

This paper presents a novel architecture for DWDM bidirectional access networks providing symmetric dynamic capacity allocation for both downlink and uplink signals. A foldback arrayed waveguide grating incorporating an optical switch enables the experimental demonstration of flexible assignment of multiservice capacity. Different analog and digital services, such as CATV, 10 GHz-tone, 155Mb/s PRBS and UMTS signals have been transmitted in order to successfully test the system performance under different scenarios of total capacity distribution from the Central Station to different Base Stations with two reconfigurable extra channels for each down and upstream direction.

High-speed multiple sequence alignment on a reconfigurable platform.

PubMed

Oliver, Tim; Schmidt, Bertil; Maskell, Douglas; Nathan, Darran; Clemens, Ralf

2006-01-01

Progressive alignment is a widely used approach to compute multiple sequence alignments (MSAs). However, aligning several hundred sequences by popular progressive alignment tools requires hours on sequential computers. Due to the rapid growth of sequence databases biologists have to compute MSAs in a far shorter time. In this paper we present a new approach to MSA on reconfigurable hardware platforms to gain high performance at low cost. We have constructed a linear systolic array to perform pairwise sequence distance computations using dynamic programming. This results in an implementation with significant runtime savings on a standard FPGA.

Time delay and integration array (TDI) using charge transfer device technology. Phase 2, volume 1: Technical

NASA Technical Reports Server (NTRS)

1977-01-01

The 20x9 TDI array was developed to meet the LANDSAT Thematic Mapper Requirements. This array is based upon a self-aligned, transparent gate, buried channel process. The process features: (1) buried channel, four phase, overlapping gate CCD's for high transfer efficiency without fat zero; (2) self-aligned transistors to minimize clock feedthrough and parasitic capacitance; and (3) transparent tin oxide electrode for high quantum efficiency with front surface irradiation. The requirements placed on the array and the performance achieved are summarized. This data is the result of flat field measurements only, no imaging or dynamic target measurements were made during this program. Measurements were performed with two different test stands. The bench test equipment fabricated for this program operated at the 8 micro sec line time and employed simple sampling of the gated MOSFET output video signal. The second stand employed Correlated Doubled Sampling (CDS) and operated at 79.2 micro sec line time.

Field ionization characteristics of an ion source array for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Resnick, P. J.; Holland, C. E.; Hertz, K. L.; Chichester, D. L.

2013-11-01

A new deuterium ion source is being developed to improve the performance of existing compact neutron generators. The ion source is a microfabricated array of metal tips with an integrated gate (i.e., grid) and produces deuterium ions by field ionizing (or field desorbing) a supply of deuterium gas. Deuterium field ion currents from arrays at source temperatures of 77 K and 293 K are studied. Ion currents from single etched-wire tips operating under the same conditions are used to help understand array results. I-F characteristics of the arrays were found to follow trends similar to those of the better understood single etched-wire tip results; however, the fields achieved by the arrays are limited by electrical breakdown of the structure. Neutron production by field ionization at 293 K was demonstrated for the first time from microfabricated array structures with integrated gates.

The Complete Reconfiguration of Dendritic Gold

NASA Astrophysics Data System (ADS)

Paneru, Govind; Flanders, Bret

2014-03-01

Reconfigurability-by-design is an important strategy in modern materials science, as materials with this capability could potentially be used to confer hydrophobic, lipophobic, or anti-corrosive character to substrates in a regenerative manner. The present work extends the directed electrochemical nanowire assembly (DENA) methodology, which is a technique that employs alternating voltages to grow single crystalline metallic nanowires and nano-dendrites from simple salt solutions, to enable the complete dissolution of macroscopic arrays of metallic dendrites following their growth. Our main finding is that structural reconfiguration of dendritic gold is induced by changes in the MHz-level frequencies of voltages that are applied to the dendrites. Cyclic voltammetry and micro-Raman spectroscopy have been used to show that dendritic gold grows and dissolves by the same chemical mechanisms as bulk gold. Hence, the redox chemistry that occurs at the crystal-solution interface is no different than the established electrochemistry of gold. What differs in this process and allows for reconfiguration to occur is the diffusive behavior of the gold chloride molecules in the solution adjacent to the interface. We will present a simple model that captures the physics of this behavior.

Dynamically Reconfigurable Microphone Arrays

DTIC Science & Technology

2011-05-01

from a number of different positions. In the second tests, the 2 wireless microphones were combined with a rigid binaural array on top of the b21r...Static + 2 Wireless Using only a standard computer sound card, a robot is limited to binaural inputs. Even when using wireless microphones, the audio...34 in HRI, Arlington, VA, 2007, pp. 113-120. [6] M. Heckmann, T. Rodemann, F. Joublin, C. Goerick, and B. Scholling, "Auditory Inspired Binaural

Two CMOS gate arrays for the EPACT experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Winkert, G.

1992-08-01

Two semicustom CMOS digital gate arrays are described in this paper which have been developed for the Energetic Particles: Acceleration, Composition, and Transport (EPACT) experiment. The first device, the 'Event Counters: 16 by 24-bit' (EC1624), implements sixteen 24-bit ripple counters and has flexible counting and readout options. The second device, the 'Serial Transmitter/Receiver' (SXR), is a multi-personality chip that can be used at either end of a serial, synchronous communications data link. It can be configured as a master in a central control unit, or as one of many slaves within remote assemblies. Together a network of SXRs allows formore » commanding and verification of distributed control signals. Both gate arrays are radiation hardened and qualified for space flight use. The architecture of each chip is presented and the benefits to the experiment summarized.« less

Roll Angle Estimation Using Thermopiles for a Flight Controlled Mortar

DTIC Science & Technology

2012-06-01

Using Xilinx’s System generator, the entire design was implemented at a relatively high level within Malab’s Simulink. This allowed VHDL code to...thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA). These results demonstrate the...accurately estimated by processing the thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA

Voltage-Controlled Reconfigurable Spin-Wave Nanochannels and Logic Devices

NASA Astrophysics Data System (ADS)

Rana, Bivas; Otani, YoshiChika

2018-01-01

Propagating spin waves (SWs) promise to be a potential information carrier in future spintronics devices with lower power consumption. Here, we propose reconfigurable nanochannels (NCs) generated by voltage-controlled magnetic anisotropy (VCMA) in an ultrathin ferromagnetic waveguide for SW propagation. Numerical micromagnetic simulations are performed to demonstrate the confinement of magnetostatic forward volumelike spin waves in NCs by VCMA. We demonstrate that the NCs, with a width down to a few tens of a nanometer, can be configured either into a straight or curved structure on an extended SW waveguide. The key advantage is that either a single NC or any combination of a number of NCs can be easily configured by VCMA for simultaneous propagation of SWs either with the same or different wave vectors according to our needs. Furthermore, we demonstrate the logic operation of a voltage-controlled magnonic xnor and universal nand gate and propose a voltage-controlled reconfigurable SW switch for the development of a multiplexer and demultiplexer. We find that the NCs and logic devices can even be functioning in the absence of the external-bias magnetic field. These results are a step towards the development of all-voltage-controlled magnonic devices with an ultralow power consumption.

Implementation of a Novel Low-Cost Low-Profile Ku-Band Antenna Array for Single Beam Steering from Space

NASA Technical Reports Server (NTRS)

Host, Nicholas K.; Chen, Chi-Chih; Volakis, John L.; Miranda, Felix A.

2013-01-01

Phased array antennas afford many advantages over traditional reflector antennas due to their conformality, high aperture efficiency, and unfettered beam steering capability at the price of increased cost and complexity. This paper eliminates the complex and costly array backend via the implementation of a series fed array employing a propagation constant reconfigurable transmission line connecting each element in series. Scanning can then be accomplished through one small (less than or equal to 100mil) linear motion that controls propagation constant. Specifically, each element is fed via a reconfigurable coplanar stripline transmission line with a tapered dielectric insert positioned between the transmission line traces. The dielectric insert is allowed to move up and down to control propagation constant and therefore induce scanning. We present a 20 element patch array design, scanning from -25 deg. less than or equal to theta less than or equal to 21 deg. at 13GHz. Measurements achieve only10.5 deg. less than or equal to theta less than or equal to 22 deg. scanning due to a faulty, yet correctable, manufacturing process. Beam squint is measured to be plus or minus 3 deg. for a 600MHz bandwidth. This prototype was improved to give scanning of 3.5 deg. less than or equal to theta less than or equal to 22 deg. Cross-pol patterns were shown to be -15dB below the main beam. Simulations accounting for fabrication errors match measured patterns, thus validating the designs.

Analysis of a Waveguide-Fed Metasurface Antenna

NASA Astrophysics Data System (ADS)

Smith, David R.; Yurduseven, Okan; Mancera, Laura Pulido; Bowen, Patrick; Kundtz, Nathan B.

2017-11-01

The metasurface concept has emerged as an advantageous reconfigurable antenna architecture for beam forming and wave-front shaping, with applications that include satellite and terrestrial communications, radar, imaging, and wireless power transfer. The metasurface antenna consists of an array of metamaterial elements distributed over an electrically large structure, each subwavelength in dimension and with subwavelength separation between elements. In the antenna configuration we consider, the metasurface is excited by the fields from an attached waveguide. Each metamaterial element can be modeled as a polarizable dipole that couples the waveguide mode to radiation modes. Distinct from the phased array and electronically-scanned-antenna architectures, a dynamic metasurface antenna does not require active phase shifters and amplifiers but rather achieves reconfigurability by shifting the resonance frequency of each individual metamaterial element. We derive the basic properties of a one-dimensional waveguide-fed metasurface antenna in the approximation in which the metamaterial elements do not perturb the waveguide mode and are noninteracting. We derive analytical approximations for the array factors of the one-dimensional antenna, including the effective polarizabilities needed for amplitude-only, phase-only, and binary constraints. Using full-wave numerical simulations, we confirm the analysis, modeling waveguides with slots or complementary metamaterial elements patterned into one of the surfaces.

Integrated optical maze

DOE Office of Scientific and Technical Information (OSTI.GOV)

Roos, E.V.; Hendrix, J.L.

1994-06-01

Improvements to Nuclear Weapons Surety through the development of new detonation control techniques incorporating electro-optic technology are reviewed and proposed in this report. The results of the Kansas City Division`s (KCD`s) literature and vendor search, potential system architecture synthesis, and device test results are the basis of this report. This study has revealed several potential reconfigureable optical interconnect architectures that meet Los Alamos National Laboratory`s preliminary performance specifications. Several planer and global architectures have the potential for meeting the Department of Energy`s applications. Preliminary conclusions on the proposed architectures are discussed. The planer approach of monolithic GaAs amplifier switch arraysmore » is the leading candidate because it meets most of the specifications now. LiNbO{sub 3} and LiTaO{sub 3} planer tree switch arrays are the second choice because they meet all the specifications except for laser power transmission. Although not atop choice, acousto-optical free space switch arrays have been considered and meet most of the specifications. Symmetric-Self Electro-Optic Effect Devices (S-SEED) free space switch arrays are being considered and have excellent potential for smart reconfigureable optical interconnects in the future.« less

Integrated feeds for electronically reconfigurable apertures

NASA Astrophysics Data System (ADS)

Nicholls, Jeffrey Grant

With the increasing ubiquity of wireless technology, the need for lower-profile, electronically reconfigurable, highly-directive beam-steering antennas is increasing. This thesis proposes a new electronic beam-steering antenna architecture which combines the full-space beam-steering properties of reflectarrays and transmitarrays with the low-profile feeding characteristics of leaky-wave antennas. Two designs are developed: an integrated feed reflectarray and an integrated feed transmitarray, both of which integrate a leaky-wave feed directly next to the reconfigurable aperture itself. The integrated feed transmitarray proved to be the better architecture due to its simpler design and better performance. A 6-by-6 element array was fabricated and experimentally verified, and full-space (both azimuth and elevation) beam-steering was demonstrated at angles up to 45 degrees off broadside. In addition to the reduction in profile, the integrated feed design enables robust fixed control of the amplitude distribution across the aperture, a characteristic not as easily attained in typical reflectarrays/transmitarrays.

Reconfigurable L-Band Radar

NASA Technical Reports Server (NTRS)

Rincon, Rafael F.

2008-01-01

The reconfigurable L-Band radar is an ongoing development at NASA/GSFC that exploits the capability inherently in phased array radar systems with a state-of-the-art data acquisition and real-time processor in order to enable multi-mode measurement techniques in a single radar architecture. The development leverages on the L-Band Imaging Scatterometer, a radar system designed for the development and testing of new radar techniques; and the custom-built DBSAR processor, a highly reconfigurable, high speed data acquisition and processing system. The radar modes currently implemented include scatterometer, synthetic aperture radar, and altimetry; and plans to add new modes such as radiometry and bi-static GNSS signals are being formulated. This development is aimed at enhancing the radar remote sensing capabilities for airborne and spaceborne applications in support of Earth Science and planetary exploration This paper describes the design of the radar and processor systems, explains the operational modes, and discusses preliminary measurements and future plans.

Reconfigurable nanomechanical photonic metamaterials

NASA Astrophysics Data System (ADS)

Zheludev, Nikolay I.; Plum, Eric

2016-01-01

The changing balance of forces at the nanoscale offers the opportunity to develop a new generation of spatially reconfigurable nanomembrane metamaterials in which electromagnetic Coulomb, Lorentz and Ampère forces, as well as thermal stimulation and optical signals, can be engaged to dynamically change their optical properties. Individual building blocks of such metamaterials, the metamolecules, and their arrays fabricated on elastic dielectric membranes can be reconfigured to achieve optical modulation at high frequencies, potentially reaching the gigahertz range. Mechanical and optical resonances enhance the magnitude of actuation and optical response within these nanostructures, which can be driven by electric signals of only a few volts or optical signals with power of only a few milliwatts. We envisage switchable, electro-optical, magneto-optical and nonlinear metamaterials that are compact and silicon-nanofabrication-technology compatible with functionalities surpassing those of natural media by orders of magnitude in some key design parameters.

Dosimetric verification of gated delivery of electron beams using a 2D ion chamber array

PubMed Central

Yoganathan, S. A.; Das, K. J. Maria; Raj, D. Gowtham; Kumar, Shaleen

2015-01-01

The purpose of this study was to compare the dosimetric characteristics; such as beam output, symmetry and flatness between gated and non-gated electron beams. Dosimetric verification of gated delivery was carried for all electron beams available on Varian CL 2100CD medical linear accelerator. Measurements were conducted for three dose rates (100 MU/min, 300 MU/min and 600 MU/min) and two respiratory motions (breathing period of 4s and 8s). Real-time position management (RPM) system was used for the gated deliveries. Flatness and symmetry values were measured using Imatrixx 2D ion chamber array device and the beam output was measured using plane parallel ion chamber. These detector systems were placed over QUASAR motion platform which was programmed to simulate the respiratory motion of target. The dosimetric characteristics of gated deliveries were compared with non-gated deliveries. The flatness and symmetry of all the evaluated electron energies did not differ by more than 0.7 % with respect to corresponding non-gated deliveries. The beam output variation of gated electron beam was less than 0.6 % for all electron energies except for 16 MeV (1.4 %). Based on the results of this study, it can be concluded that Varian CL2100 CD is well suitable for gated delivery of non-dynamic electron beams. PMID:26170552

Final Environmental Assessment (EA) for Headquarters Building Construction and Main Gate Reconfiguration White Bluff, Spokane, Washington

DTIC Science & Technology

2012-12-01

undulating or flat lands covering approximately 62,900 square miles in eastern Washington , western Idaho and northeast Oregon (Tolan et al.1989). Plateau...and thousands of square miles throughout eastern Washington , and pushed the Spokane River north to its present location. Generally, the plateau is...the plateau in eastern Washington (Eliot et al. 1986). The floods scoured the landscape of soil, leaving bare basalt in many areas. Mazama ash and

A reconfigurable waveguide for energy-efficient transmission and local manipulation of information in a nanomagnetic device

NASA Astrophysics Data System (ADS)

Haldar, Arabinda; Kumar, Dheeraj; Adeyeye, Adekunle Olusola

2016-05-01

Spin-wave-based devices promise to usher in an era of low-power computing where information is carried by the precession of the electrons' spin instead of dissipative translation of their charge. This potential is, however, undermined by the need for a bias magnetic field, which must remain powered on to maintain an anisotropic device characteristic. Here, we propose a reconfigurable waveguide design that can transmit and locally manipulate spin waves without the need for any external bias field once initialized. We experimentally demonstrate the transmission of spin waves in straight as well as curved waveguides without a bias field, which has been elusive so far. Furthermore, we experimentally show a binary gating of the spin-wave signal by controlled switching of the magnetization, locally, in the waveguide. The results have potential implications in high-density integration and energy-efficient operation of nanomagnetic devices at room temperature.

Tunable Electron-Electron Interactions in LaAlO 3 / SrTiO 3 Nanostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cheng, Guanglei; Tomczyk, Michelle; Tacla, Alexandre B.

The interface between the two complex oxides LaAlO 3 and SrTiO 3 has remarkable properties that can be locally reconfigured between conducting and insulating states using a conductive atomic force microscope. Prior investigations of “sketched” quantum dot devices revealed a phase in which electrons form pairs, implying a strongly attractive electron-electron interaction. Here, we show that these devices with strong electron-electron interactions can exhibit a gate-tunable transition from a pair-tunneling regime to a single-electron (Andreev bound state) tunneling regime where the interactions become repulsive. The electron-electron interaction sign change is associated with a Lifshitz transition where the d xz andmore » d yz bands start to become occupied. This electronically tunable electron-electron interaction, combined with the nanoscale reconfigurability of this system, provides an interesting starting point towards solid-state quantum simulation.« less

Tunable Electron-Electron Interactions in LaAlO 3 / SrTiO 3 Nanostructures

DOE PAGES

Cheng, Guanglei; Tomczyk, Michelle; Tacla, Alexandre B.; ...

2016-12-01

The interface between the two complex oxides LaAlO 3 and SrTiO 3 has remarkable properties that can be locally reconfigured between conducting and insulating states using a conductive atomic force microscope. Prior investigations of “sketched” quantum dot devices revealed a phase in which electrons form pairs, implying a strongly attractive electron-electron interaction. Here, we show that these devices with strong electron-electron interactions can exhibit a gate-tunable transition from a pair-tunneling regime to a single-electron (Andreev bound state) tunneling regime where the interactions become repulsive. The electron-electron interaction sign change is associated with a Lifshitz transition where the d xz andmore » d yz bands start to become occupied. This electronically tunable electron-electron interaction, combined with the nanoscale reconfigurability of this system, provides an interesting starting point towards solid-state quantum simulation.« less

Real-Time Label-Free Detection of Suspicious Powders Using Noncontact Optical Methods

DTIC Science & Technology

2013-11-05

energy in a small, 1 pound, low power consumption package; and 2) new technology resistive gate linear CCD array detectors developed by Hamamatsu Corp...as a wide range of possible interferent or confusant organic materials such as powdered sugar, granulate sugar, fruit pectin, flower, corn starch ...resolution, room temperature, resistive gate linear CCD array, the BRANE sensor SWAP decreases along with a decrease in sensitivity, but the information

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

2017-01-01

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.; Carmichael, C.; Tseng, C.

2007-01-01

We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.

Analog storage integrated circuit

DOEpatents

Walker, J. T.; Larsen, R. S.; Shapiro, S. L.

1989-01-01

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.

Analog storage integrated circuit

DOEpatents

Walker, J.T.; Larsen, R.S.; Shapiro, S.L.

1989-03-07

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks. 6 figs.

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

PubMed Central

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Single array of magnetic vortex disks uses in-plane anisotropy to create different logic gates

NASA Astrophysics Data System (ADS)

Vigo-Cotrina, H.; Guimarães, A. P.

2017-11-01

Using micromagnetic simulation, we show that in-plane uniaxial magnetic anisotropy (IPUA) can be used to obtain FAN-OUT, AND and OR gates in an array of coupled disks with magnetic vortex configuration. First, we studied the influence of the direction of application of the IPUA on the energy transfer time (τ) between two identical coupled nanodisks. We found that when the direction of the IPUA is along the x axis the magnetic interaction increases, allowing shorter values of τ , while the IPUA along the y direction has the opposite effect. The magnetic interactions between the nanodisks along x and y directions (the coupling integrals) as a function of the uniaxial anisotropy constant (Kσ) were obtained using a simple dipolar model. Next, we demonstrated that choosing a suitable direction of application of the IPUA, it is possible to create several different logic gates with a single array of coupled nanodisks.

Scalable Creation of Long-Lived Multipartite Entanglement

NASA Astrophysics Data System (ADS)

Kaufmann, H.; Ruster, T.; Schmiegelow, C. T.; Luda, M. A.; Kaushal, V.; Schulz, J.; von Lindenfels, D.; Schmidt-Kaler, F.; Poschinger, U. G.

2017-10-01

We demonstrate the deterministic generation of multipartite entanglement based on scalable methods. Four qubits are encoded in 40Ca+, stored in a microstructured segmented Paul trap. These qubits are sequentially entangled by laser-driven pairwise gate operations. Between these, the qubit register is dynamically reconfigured via ion shuttling operations, where ion crystals are separated and merged, and ions are moved in and out of a fixed laser interaction zone. A sequence consisting of three pairwise entangling gates yields a four-ion Greenberger-Horne-Zeilinger state |ψ ⟩=(1 /√{2 })(|0000 ⟩+|1111 ⟩) , and full quantum state tomography reveals a state fidelity of 94.4(3)%. We analyze the decoherence of this state and employ dynamic decoupling on the spatially distributed constituents to maintain 69(5)% coherence at a storage time of 1.1 sec.

Space Debris Detection on the HPDP, a Coarse-Grained Reconfigurable Array Architecture for Space

NASA Astrophysics Data System (ADS)

Suarez, Diego Andres; Bretz, Daniel; Helfers, Tim; Weidendorfer, Josef; Utzmann, Jens

2016-08-01

Stream processing, widely used in communications and digital signal processing applications, requires high- throughput data processing that is achieved in most cases using Application-Specific Integrated Circuit (ASIC) designs. Lack of programmability is an issue especially in space applications, which use on-board components with long life-cycles requiring applications updates. To this end, the High Performance Data Processor (HPDP) architecture integrates an array of coarse-grained reconfigurable elements to provide both flexible and efficient computational power suitable for stream-based data processing applications in space. In this work the capabilities of the HPDP architecture are demonstrated with the implementation of a real-time image processing algorithm for space debris detection in a space-based space surveillance system. The implementation challenges and alternatives are described making trade-offs to improve performance at the expense of negligible degradation of detection accuracy. The proposed implementation uses over 99% of the available computational resources. Performance estimations based on simulations show that the HPDP can amply match the application requirements.

Voltage-Dependent Gating of hERG Potassium Channels

PubMed Central

Cheng, Yen May; Claydon, Tom W.

2012-01-01

The mechanisms by which voltage-gated channels sense changes in membrane voltage and energetically couple this with opening of the ion conducting pore has been the source of significant interest. In voltage-gated potassium (Kv) channels, much of our knowledge in this area comes from Shaker-type channels, for which voltage-dependent gating is quite rapid. In these channels, activation and deactivation are associated with rapid reconfiguration of the voltage-sensing domain unit that is electromechanically coupled, via the S4–S5 linker helix, to the rate-limiting opening of an intracellular pore gate. However, fast voltage-dependent gating kinetics are not typical of all Kv channels, such as Kv11.1 (human ether-à-go-go related gene, hERG), which activates and deactivates very slowly. Compared to Shaker channels, our understanding of the mechanisms underlying slow hERG gating is much poorer. Here, we present a comparative review of the structure–function relationships underlying activation and deactivation gating in Shaker and hERG channels, with a focus on the roles of the voltage-sensing domain and the S4–S5 linker that couples voltage sensor movements to the pore. Measurements of gating current kinetics and fluorimetric analysis of voltage sensor movement are consistent with models suggesting that the hERG activation pathway contains a voltage independent step, which limits voltage sensor transitions. Constraints upon hERG voltage sensor movement may result from loose packing of the S4 helices and additional intra-voltage sensor counter-charge interactions. More recent data suggest that key amino acid differences in the hERG voltage-sensing unit and S4–S5 linker, relative to fast activating Shaker-type Kv channels, may also contribute to the increased stability of the resting state of the voltage sensor. PMID:22586397

Tunable Metasurface and Flat Optical Zoom Lens on a Stretchable Substrate.

PubMed

Ee, Ho-Seok; Agarwal, Ritesh

2016-04-13

A mechanically reconfigurable metasurface that can continuously tune the wavefront is demonstrated in the visible frequency range by changing the lattice constant of a complex Au nanorod array fabricated on a stretchable polydimethylsiloxane substrate. It is shown that the anomalous refraction angle of visible light at 632.8 nm interacting with the tunable metasurface can be adjusted from 11.4° to 14.9° by stretching the substrate by ∼30%. An ultrathin flat 1.7× zoom lens whose focal length can continuously be changed from 150 to 250 μm is realized, which also demonstrates the potential of utilizing metasurfaces for reconfigurable flat optics.

Dynamic non-reciprocal meta-surfaces with arbitrary phase reconfigurability based on photonic transition in meta-atoms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Yu; Fan, Shanhui, E-mail: shanhui@stanford.edu

2016-01-11

We introduce a distinct class of dynamic non-reciprocal meta-surfaces with arbitrary phase-reconfigurability. This meta-surface consists of an array of meta-atoms, each of which is subject to temporal refractive index modulation, which induces photonic transitions between the states of the meta-atom. We show that arbitrary phase profile for the outgoing wave can be achieved by controlling the phase of the modulation at each meta-atom. Moreover, such dynamic meta-surfaces exhibit non-reciprocal response without the need for magneto-optical effects. The use of photonic transition significantly enhances the tunability and the possible functionalities of meta-surfaces.

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Semantically Aware Foundation Environment (SAFE) for Clean-Slate Design of Resilient, Adaptive Secure Hosts (CRASH)

DTIC Science & Technology

2016-02-01

system consists of a high-fidelity hardware simulation using field programmable gate arrays (FPGAs), with a set of runtime services (ConcreteWare...perimeter protection, patch, and pray” is not aligned with the threat. Programmers will not bail us out of this situation (by writing defect free code...hosted on a Field Programmable Gate Array (FPGA), with a set of runtime services (concreteware) running on the hardware. Secure applications can be

Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

NASA Technical Reports Server (NTRS)

Straka, Bartholomew

2013-01-01

Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

Plastic fiber scintillator response to fast neutrons

NASA Astrophysics Data System (ADS)

Danly, C. R.; Sjue, S.; Wilde, C. H.; Merrill, F. E.; Haight, R. C.

2014-11-01

The Neutron Imaging System at NIF uses an array of plastic scintillator fibers in conjunction with a time-gated imaging system to form an image of the neutron emission from the imploded capsule. By gating on neutrons that have scattered from the 14.1 MeV DT energy to lower energy ranges, an image of the dense, cold fuel around the hotspot is also obtained. An unmoderated spallation neutron beamline at the Weapons Neutron Research facility at Los Alamos was used in conjunction with a time-gated imaging system to measure the yield of a scintillating fiber array over several energy bands ranging from 1 to 15 MeV. The results and comparison to simulation are presented.

Plastic fiber scintillator response to fast neutrons.

PubMed

Danly, C R; Sjue, S; Wilde, C H; Merrill, F E; Haight, R C

2014-11-01

The Neutron Imaging System at NIF uses an array of plastic scintillator fibers in conjunction with a time-gated imaging system to form an image of the neutron emission from the imploded capsule. By gating on neutrons that have scattered from the 14.1 MeV DT energy to lower energy ranges, an image of the dense, cold fuel around the hotspot is also obtained. An unmoderated spallation neutron beamline at the Weapons Neutron Research facility at Los Alamos was used in conjunction with a time-gated imaging system to measure the yield of a scintillating fiber array over several energy bands ranging from 1 to 15 MeV. The results and comparison to simulation are presented.

Field programmable gate arrays: Evaluation report for space-flight application

NASA Technical Reports Server (NTRS)

Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

1992-01-01

Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems

DTIC Science & Technology

2007-05-01

these systems, and after being run through an optimizing CAD tool the resulting circuit is a single entangled mess of gates and wires. To prevent the...translates MATLAB [48] algorithms into HDL, logic synthesis translates this HDL into a netlist, a synthesis tool uses a place-and-route algorithm to...Core Soft Core µ Soft P Core µP Core Hard Soft Algorithms MATLAB gcc ExecutableC Code HDL C Code Bitstream Place and Route NetlistLogic Synthesis EDK µP

KSC-03pd1169

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. - The STS-116 crew take part in training in the SPACEHAB module. From left are Mission Specialist Christer Fuglesang; a trainer; Pilot Michael Oefelein; Mission Specialist Robert Curbeam; and Commander Terrence Wilcutt. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review

KSC-03pd1173

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. - STS-116 Commander Terrence Wilcutt is in training at SPACEHAB, Port Canaveral, Fla., along with other crew members Pilot William Oefelein and Mission Specialists Robert Curbeam and Christer Fuglesang. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

KSC-03pd1174

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. - STS-116 Pilot William Oelefein is in training at SPACEHAB, Port Canaveral, Fla., along with other crew members Commander Terrence Wilcutt and Mission Specialists Robert Curbeam and Christer Fuglesang. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

KSC-03pd1175

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. - STS-116 Mission Specialist Robert Curbeam is in training at SPACEHAB, Port Canaveral, Fla., along with other crew members Commander Terrence Wilcutt, Pilot William Oelefein and Mission Specialist Christer Fuglesang. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

A Reconfigurable Pneumatic Bending Actuator with Replaceable Inflation Modules.

PubMed

Natividad, Rainier; Del Rosario, Manuel; Chen, Peter C Y; Yeow, Chen-Hua

2018-06-01

A fully reconfigurable, pneumatic bending actuator is fabricated by implementing the concept of modularity to soft robotics. The actuator features independent, removable, fabric inflation modules that are attached to a common flexible but non-inflating plastic spine. The fabric modules are individually fabricated by heat sealing a thermoplastic polyurethane-coated nylon fabric, whereas the spine is manufactured through fused deposition modeling 3D printing; the components can be assembled and dismantled without the aid of any external tools. The replacement of specific modules along the array facilitates the reconfiguration of the actuator's bending trajectory and torque output; likewise, the combination of inflation modules with dissimilar geometries translates to several different trajectories on a single spine and allows the actuator to bend into assorted, unique structures. A detailed description of the actuator's design is thoroughly presented. We explored how reconfiguration of the actuator's modular geometry affected both the steady state and the dynamic characteristics of the actuator. The torque output of the actuator is proportional to the magnitude of the pressure applied. The actuator was excited by sinusoidal and square pressure inputs, and a second-order linear fit was performed. There were no perceived changes in its performance even after 100,000 inflation and deflation cycles.

A Hardware-Accelerated Quantum Monte Carlo framework (HAQMC) for N-body systems

NASA Astrophysics Data System (ADS)

Gothandaraman, Akila; Peterson, Gregory D.; Warren, G. Lee; Hinde, Robert J.; Harrison, Robert J.

2009-12-01

Interest in the study of structural and energetic properties of highly quantum clusters, such as inert gas clusters has motivated the development of a hardware-accelerated framework for Quantum Monte Carlo simulations. In the Quantum Monte Carlo method, the properties of a system of atoms, such as the ground-state energies, are averaged over a number of iterations. Our framework is aimed at accelerating the computations in each iteration of the QMC application by offloading the calculation of properties, namely energy and trial wave function, onto reconfigurable hardware. This gives a user the capability to run simulations for a large number of iterations, thereby reducing the statistical uncertainty in the properties, and for larger clusters. This framework is designed to run on the Cray XD1 high performance reconfigurable computing platform, which exploits the coarse-grained parallelism of the processor along with the fine-grained parallelism of the reconfigurable computing devices available in the form of field-programmable gate arrays. In this paper, we illustrate the functioning of the framework, which can be used to calculate the energies for a model cluster of helium atoms. In addition, we present the capabilities of the framework that allow the user to vary the chemical identities of the simulated atoms. Program summaryProgram title: Hardware Accelerated Quantum Monte Carlo (HAQMC) Catalogue identifier: AEEP_v1_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEEP_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 691 537 No. of bytes in distributed program, including test data, etc.: 5 031 226 Distribution format: tar.gz Programming language: C/C++ for the QMC application, VHDL and Xilinx 8.1 ISE/EDK tools for FPGA design and development Computer: Cray XD1 consisting of a dual-core, dualprocessor AMD Opteron 2.2 GHz with a Xilinx Virtex-4 (V4LX160) or Xilinx Virtex-II Pro (XC2VP50) FPGA per node. We use the compute node with the Xilinx Virtex-4 FPGA Operating system: Red Hat Enterprise Linux OS Has the code been vectorised or parallelized?: Yes Classification: 6.1 Nature of problem: Quantum Monte Carlo is a practical method to solve the Schrödinger equation for large many-body systems and obtain the ground-state properties of such systems. This method involves the sampling of a number of configurations of atoms and averaging the properties of the configurations over a number of iterations. We are interested in applying the QMC method to obtain the energy and other properties of highly quantum clusters, such as inert gas clusters. Solution method: The proposed framework provides a combined hardware-software approach, in which the QMC simulation is performed on the host processor, with the computationally intensive functions such as energy and trial wave function computations mapped onto the field-programmable gate array (FPGA) logic device attached as a co-processor to the host processor. We perform the QMC simulation for a number of iterations as in the case of our original software QMC approach, to reduce the statistical uncertainty of the results. However, our proposed HAQMC framework accelerates each iteration of the simulation, by significantly reducing the time taken to calculate the ground-state properties of the configurations of atoms, thereby accelerating the overall QMC simulation. We provide a generic interpolation framework that can be extended to study a variety of pure and doped atomic clusters, irrespective of the chemical identities of the atoms. For the FPGA implementation of the properties, we use a two-region approach for accurately computing the properties over the entire domain, employ deep pipelines and fixed-point for all our calculations guaranteeing the accuracy required for our simulation.

High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

PubMed

Ly, Daniel Le; Chow, Paul

2010-11-01

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

Fused Smart Sensor Network for Multi-Axis Forward Kinematics Estimation in Industrial Robots

PubMed Central

Rodriguez-Donate, Carlos; Osornio-Rios, Roque Alfredo; Rivera-Guillen, Jesus Rooney; de Jesus Romero-Troncoso, Rene

2011-01-01

Flexible manipulator robots have a wide industrial application. Robot performance requires sensing its position and orientation adequately, known as forward kinematics. Commercially available, motion controllers use high-resolution optical encoders to sense the position of each joint which cannot detect some mechanical deformations that decrease the accuracy of the robot position and orientation. To overcome those problems, several sensor fusion methods have been proposed but at expenses of high-computational load, which avoids the online measurement of the joint’s angular position and the online forward kinematics estimation. The contribution of this work is to propose a fused smart sensor network to estimate the forward kinematics of an industrial robot. The developed smart processor uses Kalman filters to filter and to fuse the information of the sensor network. Two primary sensors are used: an optical encoder, and a 3-axis accelerometer. In order to obtain the position and orientation of each joint online a field-programmable gate array (FPGA) is used in the hardware implementation taking advantage of the parallel computation capabilities and reconfigurability of this device. With the aim of evaluating the smart sensor network performance, three real-operation-oriented paths are executed and monitored in a 6-degree of freedom robot. PMID:22163850

DOE Office of Scientific and Technical Information (OSTI.GOV)

Learn, Mark Walter

Sandia National Laboratories is currently developing new processing and data communication architectures for use in future satellite payloads. These architectures will leverage the flexibility and performance of state-of-the-art static-random-access-memory-based Field Programmable Gate Arrays (FPGAs). One such FPGA is the radiation-hardened version of the Virtex-5 being developed by Xilinx. However, not all features of this FPGA are being radiation-hardened by design and could still be susceptible to on-orbit upsets. One such feature is the embedded hard-core PPC440 processor. Since this processor is implemented in the FPGA as a hard-core, traditional mitigation approaches such as Triple Modular Redundancy (TMR) are not availablemore » to improve the processor's on-orbit reliability. The goal of this work is to investigate techniques that can help mitigate the embedded hard-core PPC440 processor within the Virtex-5 FPGA other than TMR. Implementing various mitigation schemes reliably within the PPC440 offers a powerful reconfigurable computing resource to these node-based processing architectures. This document summarizes the work done on the cache mitigation scheme for the embedded hard-core PPC440 processor within the Virtex-5 FPGAs, and describes in detail the design of the cache mitigation scheme and the testing conducted at the radiation effects facility on the Texas A&M campus.« less

An adaptive software defined radio design based on a standard space telecommunication radio system API

NASA Astrophysics Data System (ADS)

Xiong, Wenhao; Tian, Xin; Chen, Genshe; Pham, Khanh; Blasch, Erik

2017-05-01

Software defined radio (SDR) has become a popular tool for the implementation and testing for communications performance. The advantage of the SDR approach includes: a re-configurable design, adaptive response to changing conditions, efficient development, and highly versatile implementation. In order to understand the benefits of SDR, the space telecommunication radio system (STRS) was proposed by NASA Glenn research center (GRC) along with the standard application program interface (API) structure. Each component of the system uses a well-defined API to communicate with other components. The benefit of standard API is to relax the platform limitation of each component for addition options. For example, the waveform generating process can support a field programmable gate array (FPGA), personal computer (PC), or an embedded system. As long as the API defines the requirements, the generated waveform selection will work with the complete system. In this paper, we demonstrate the design and development of adaptive SDR following the STRS and standard API protocol. We introduce step by step the SDR testbed system including the controlling graphic user interface (GUI), database, GNU radio hardware control, and universal software radio peripheral (USRP) tranceiving front end. In addition, a performance evaluation in shown on the effectiveness of the SDR approach for space telecommunication.

A single-board NMR spectrometer based on a software defined radio architecture

NASA Astrophysics Data System (ADS)

Tang, Weinan; Wang, Weimin

2011-01-01

A single-board software defined radio (SDR) spectrometer for nuclear magnetic resonance (NMR) is presented. The SDR-based architecture, realized by combining a single field programmable gate array (FPGA) and a digital signal processor (DSP) with peripheral radio frequency (RF) front-end circuits, makes the spectrometer compact and reconfigurable. The DSP, working as a pulse programmer, communicates with a personal computer via a USB interface and controls the FPGA through a parallel port. The FPGA accomplishes digital processing tasks such as a numerically controlled oscillator (NCO), digital down converter (DDC) and gradient waveform generator. The NCO, with agile control of phase, frequency and amplitude, is part of a direct digital synthesizer that is used to generate an RF pulse. The DDC performs quadrature demodulation, multistage low-pass filtering and gain adjustment to produce a bandpass signal (receiver bandwidth from 3.9 kHz to 10 MHz). The gradient waveform generator is capable of outputting shaped gradient pulse waveforms and supports eddy-current compensation. The spectrometer directly acquires an NMR signal up to 30 MHz in the case of baseband sampling and is suitable for low-field (<0.7 T) application. Due to the featured SDR architecture, this prototype has flexible add-on ability and is expected to be suitable for portable NMR systems.

Programmable Ultra-Lightweight System Adaptable Radio

NASA Technical Reports Server (NTRS)

Werkheiser, Arthur

2015-01-01

The programmable ultra-lightweight system adaptable radio (PULSAR) is a NASA Marshall Space Flight Center transceiver designed for the CubeSat market, but has the potential for other markets. The PULSAR project aims to reduce size, weight, and power while increasing telemetry data rate. The current version of the PULSAR has a mass of 2.2 kg and a footprint of 10.8 cm2. The height depends on the specific configuration. The PULSAR S-Band Communications Subsystem is an S- and X-band transponder system comprised of a receiver/detector (receiver) element, a transmitter element(s), and related power distribution, command, control, and telemetry element for operation and information interfaces. It is capable of receiving commands, encoding and transmitting telemetry, as well as providing tracking data in a manner compatible with Earthbased ground stations, near Earth network, and deep space network station resources. The software-defined radio's (SDR's) data format characteristics can be defined and reconfigured during spaceflight or prior to launch. The PULSAR team continues to evolve the SDR to improve the performance and form factor to meet the requirements that the CubeSat market space requires. One of the unique features is that the actual radio design can change (somewhat), but not require any hardware modifications due to the use of field programmable gate arrays.

Optical Breath Gas Extravehicular Activity Sensor for the Advanced Portable Life Support System

NASA Technical Reports Server (NTRS)

Wood, William R.; Casias, Miguel E.; Pilgrim, Jeffrey S.; Chullen, Cinda; Campbell, Colin

2016-01-01

The infrared gas transducer used during extravehicular activity (EVA) in the extravehicular mobility unit (EMU) measures and reports the concentration of carbon dioxide (CO2) in the ventilation loop. It is nearing its end of life and there are a limited number remaining. Meanwhile, the next generation advanced portable life support system (PLSS) now being developed requires CO2 sensing technology with performance beyond that presently in use. A laser diode (LD) spectrometer based on wavelength modulation spectroscopy (WMS) is being developed to address both applications by Vista Photonics, Inc. Accommodation within space suits demands that optical sensors meet stringent size, weight, and power requirements. Version 1.0 devices were delivered to NASA Johnson Space Center (JSC) in 2011. The sensors incorporate a laser diode based CO2 channel that also includes an incidental water vapor (humidity) measurement. The prototypes are controlled digitally with a field-programmable gate array (FPGA)/microcontroller architecture. Version 2.0 devices with improved electronics and significantly reduced wetted volumes were delivered to JSC in 2012. A version 2.5 upgrade recently implemented wavelength stabilized operation, better humidity measurement, and much faster data analysis/reporting. A wholly reconfigured version 3.0 will maintain the demonstrated performance of earlier versions while being backwards compatible with the EMU and offering a radiation tolerant architecture.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

NASA Astrophysics Data System (ADS)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baart, T. A.; Vandersypen, L. M. K.; Kavli Institute of Nanoscience, Delft University of Technology, P.O. Box 5046, 2600 GA Delft

We report the computer-automated tuning of gate-defined semiconductor double quantum dots in GaAs heterostructures. We benchmark the algorithm by creating three double quantum dots inside a linear array of four quantum dots. The algorithm sets the correct gate voltages for all the gates to tune the double quantum dots into the single-electron regime. The algorithm only requires (1) prior knowledge of the gate design and (2) the pinch-off value of the single gate T that is shared by all the quantum dots. This work significantly alleviates the user effort required to tune multiple quantum dot devices.

One GigaSample Per Second Data Acquisition using Available Gate Array Technology

NASA Technical Reports Server (NTRS)

Wagner, K.W.

1999-01-01

A new National Aeronautics and Space Administration instrument forced demanding requirements upon its altimeter digitizer system. Eight-bit data would be generated at a rate of one billion samples per second. NASA had never before attempted to capture such high-speed data in the radiation, low-power, no-convective-cooling, limited-board-area environment of space. This presentation describes how the gate array technology available at the time of the design was used to implement this one gigasample per second data acquisition system

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory; Edmonds, Larry D.; Swift, Gary; Carmichael, Carl; Tseng, Chen Wei; Heldt, Kevin; Anderson, Scott Arlo; Coe, Michael

2010-01-01

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

Detection of Bioaerosols Using Single Particle Thermal Emission Spectroscopy (First-year Report)

DTIC Science & Technology

2012-02-01

cooled MCT detector with a noise equivalent power (NEP) of 7x10(–13) W/Hz, yields a detection S/N > 13 (assuming a sufficiently cooled background). We...dispersively resolved using 190-mm Horiba spectrometer that houses a time-gated 32-element mercury cadmium telluride ( MCT ) linear array. In this report...to 10.0 ms. Minimum integration (and readout) periods for the time-gated 32-element mercury cadmium telluride ( MCT ) linear array are 10 µs. Based

Quantum many-body dynamics of strongly interacting atom arrays

NASA Astrophysics Data System (ADS)

Bernien, Hannes; Keesling, Alexander; Levine, Harry; Schwartz, Sylvain; Omran, Ahmed; Anschuetz, Eric; Endres, Manuel; Vuletic, Vladan; Greiner, Markus; Lukin, Mikhail

2017-04-01

The coherent interaction between large numbers of particles gives rise to fascinating quantum many-body effects and lies at the center of quantum simulations and quantum information processing. The development of systems consisting of many, well-controlled particles with tunable interactions is an outstanding challenge. Here we present a new platform based on large, reconfigurable arrays of individually trapped atoms. Strong interactions between these atoms are enabled by exciting them to Rydberg states. This flexible approach allows access to vastly different regimes with interactions tunable over several orders of magnitude. We study the coherent many-body dynamics in varying array geometries and observe the formation of Rydberg crystals.

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Group-Velocity-Controlled and Gate-Tunable Directional Excitation of Polaritons in Graphene-Boron Nitride Heterostructures

NASA Astrophysics Data System (ADS)

Jiang, Yuyu; Lin, Xiao; Low, Tony; Zhang, Baile; Chen, Hongsheng

2018-05-01

A fundamental building block in nano-photonics is the ability to directionally excite highly squeezed optical mode dynamically, particularly with an electrical bias. Such capabilities would enable the active manipulation of light propagation for information processing and transfer. However, when the optical source is built-in, it remains challenging to steer the excitation directionality in a flexible way. Here, we reveal a novel mechanism for tunable directional excitation of highly squeezed polaritons in graphene-hexagonal boron nitride (hBN) heterostructures. The effect relies on controlling the sign of the group velocity of the coupled plasmon-phonon polaritons, which can be flipped by simply tuning the chemical potential of graphene (through electrostatic gating) in the heterostructures. Graphene-hBN heterostructure thus present a promising platform toward nano-photonic circuits and nano-devices with electrically reconfigurable functionalities.

DNA-programmed dynamic assembly of quantum dots for molecular computation.

PubMed

He, Xuewen; Li, Zhi; Chen, Muzi; Ma, Nan

2014-12-22

Despite the widespread use of quantum dots (QDs) for biosensing and bioimaging, QD-based bio-interfaceable and reconfigurable molecular computing systems have not yet been realized. DNA-programmed dynamic assembly of multi-color QDs is presented for the construction of a new class of fluorescence resonance energy transfer (FRET)-based QD computing systems. A complete set of seven elementary logic gates (OR, AND, NOR, NAND, INH, XOR, XNOR) are realized using a series of binary and ternary QD complexes operated by strand displacement reactions. The integration of different logic gates into a half-adder circuit for molecular computation is also demonstrated. This strategy is quite versatile and straightforward for logical operations and would pave the way for QD-biocomputing-based intelligent molecular diagnostics. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Scalable Creation of Long-Lived Multipartite Entanglement.

PubMed

Kaufmann, H; Ruster, T; Schmiegelow, C T; Luda, M A; Kaushal, V; Schulz, J; von Lindenfels, D; Schmidt-Kaler, F; Poschinger, U G

2017-10-13

We demonstrate the deterministic generation of multipartite entanglement based on scalable methods. Four qubits are encoded in ^{40}Ca^{+}, stored in a microstructured segmented Paul trap. These qubits are sequentially entangled by laser-driven pairwise gate operations. Between these, the qubit register is dynamically reconfigured via ion shuttling operations, where ion crystals are separated and merged, and ions are moved in and out of a fixed laser interaction zone. A sequence consisting of three pairwise entangling gates yields a four-ion Greenberger-Horne-Zeilinger state |ψ⟩=(1/sqrt[2])(|0000⟩+|1111⟩), and full quantum state tomography reveals a state fidelity of 94.4(3)%. We analyze the decoherence of this state and employ dynamic decoupling on the spatially distributed constituents to maintain 69(5)% coherence at a storage time of 1.1 sec.

SU-E-T-350: Verification of Gating Performance of a New Elekta Gating Solution: Response Kit and Catalyst System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xie, X; Cao, D; Housley, D

2014-06-01

Purpose: In this work, we have tested the performance of new respiratory gating solutions for Elekta linacs. These solutions include the Response gating and the C-RAD Catalyst surface mapping system.Verification measurements have been performed for a series of clinical cases. We also examined the beam on latency of the system and its impact on delivery efficiency. Methods: To verify the benefits of tighter gating windows, a Quasar Respiratory Motion Platform was used. Its vertical-motion plate acted as a respiration surrogate and was tracked by the Catalyst system to generate gating signals. A MatriXX ion-chamber array was mounted on its longitudinal-movingmore » platform. Clinical plans are delivered to a stationary and moving Matrix array at 100%, 50% and 30% gating windows and gamma scores were calculated comparing moving delivery results to the stationary result. It is important to note that as one moves to tighter gating windows, the delivery efficiency will be impacted by the linac's beam-on latency. Using a specialized software package, we generated beam-on signals of lengths of 1000ms, 600ms, 450ms, 400ms, 350ms and 300ms. As the gating windows get tighter, one can expect to reach a point where the dose rate will fall to nearly zero, indicating that the gating window is close to beam-on latency. A clinically useful gating window needs to be significantly longer than the latency for the linac. Results: As expected, the use of tighter gating windows improved delivery accuracy. However, a lower limit of the gating window, largely defined by linac beam-on latency, exists at around 300ms. Conclusion: The Response gating kit, combined with the C-RAD Catalyst, provides an effective solution for respiratorygated treatment delivery. Careful patient selection, gating window design, even visual/audio coaching may be necessary to ensure both delivery quality and efficiency. This research project is funded by Elekta.« less

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Transformational electronics are now reconfiguring

NASA Astrophysics Data System (ADS)

Rojas, Jhonathan P.; Hussain, Aftab M.; Arevalo, A.; Foulds, I. G.; Torres Sevilla, Galo A.; Nassar, Joanna M.; Hussain, Muhammad M.

2015-05-01

Current developments on enhancing our smart living experience are leveraging the increased interest for novel systems that can be compatible with foldable, wrinkled, wavy and complex geometries and surfaces, and thus become truly ubiquitous and easy to deploy. Therefore, relying on innovative structural designs we have been able to reconfigure the physical form of various materials, to achieve remarkable mechanical flexibility and stretchability, which provides us with the perfect platform to develop enhanced electronic systems for application in entertainment, healthcare, fitness and wellness, military and manufacturing industry. Based on these novel structural designs we have developed a siliconbased network of hexagonal islands connected through double-spiral springs, forming an ultra-stretchable (~1000%) array for full compliance to highly asymmetric shapes and surfaces, as well as a serpentine design used to show an ultrastretchable (~800%) and flexible, spatially reconfigurable, mobile, metallic thin film copper (Cu)-based, body-integrated and non-invasive thermal heater with wireless controlling capability, reusability, heating-adaptability and affordability due to low-cost complementary metal oxide semiconductor (CMOS)-compatible integration.

A reconfigurable waveguide for energy-efficient transmission and local manipulation of information in a nanomagnetic device

NASA Astrophysics Data System (ADS)

Adeyeye, Adekunle

In the last few years, interest in propagating-spin-wave based devices has grown largely due to advances in nanotechnology which allows shapes of geometrically confined magnonic elements to be fabricated, the development of new advanced experimental techniques for studying high-frequency magnetization dynamics and the potential use of spin waves as information carriers in spintronic applications. The first part of this talk will focus on design and fabrication strategies for synthesizing nanomagnetic networks with deterministic magnetic ground states. Reliable reconfiguration between ferromagnetic (FM), antiferromagnetic (AFM) and ferrimagnetic ground magnetic states will be shown in rhomboid nanomagnets which stabilize to unique ground states upon field initialized along their short axis. In the second part, a new waveguide consisting of dipolar coupled rhombic shaped nanomagnetic chain that eliminate the requirement of a stand-by power during operation will be presented. The sizes of the nanomagnets are small enough to retain their correct magnetic states once initialized. It will be shown that our waveguide could be used to send spin wave signal around a corner without any stand-by power. Another important parameter for device operation is the manipulation of the output signal, which is similar to a gating operation in a transistor. In our design, gating operation is demonstrated by switching the magnetization of single/multiple nanomagnets in the waveguides in order to manipulate the spin wave amplitude at the output. This work is supported by the National Research Foundation, Prime Minister's Office, under CRP 10-2012-03.

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor.

PubMed

Tzu-Yun Wang; Min-Rui Lai; Twigg, Christopher M; Sheng-Yu Peng

2014-06-01

A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm (2) silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

Study of array plasma antenna parameters

NASA Astrophysics Data System (ADS)

Kumar, Rajneesh; Kumar, Prince

2018-04-01

This paper is aimed to investigate the array plasma antenna parameters to help the optimization of an array plasma antenna. Single plasma antenna is transformed into array plasma antenna by changing the operating parameters. The re-configurability arises in the form of striations, due to transverse bifurcation of plasma column by changing the operating parameters. Each striation can be treated as an antenna element and system performs like an array plasma antenna. In order to achieve the goal of this paper, three different configurations of array plasma antenna (namely Array 1, Array 2 and Array 3) are simulated. The observations are made on variation in antenna parameters like resonance frequency, radiation pattern, directivity and gain with variation in length and number of antenna elements for each array plasma antenna. Moreover experiments are also performed and results are compared with simulation. Further array plasma antenna parameters are also compared with monopole plasma antenna parameters. The study of present paper invoke the array plasma antenna can be applied for steering and controlling the strength of Wi-Fi signals as per requirement.

N channel JFET based digital logic gate structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor)

2010-01-01

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Spin Transport in Nondegenerate Si with a Spin MOSFET Structure at Room Temperature

NASA Astrophysics Data System (ADS)

Sasaki, Tomoyuki; Ando, Yuichiro; Kameno, Makoto; Tahara, Takayuki; Koike, Hayato; Oikawa, Tohru; Suzuki, Toshio; Shiraishi, Masashi

2014-09-01

Spin transport in nondegenerate semiconductors is expected to pave the way to the creation of spin transistors, spin logic devices, and reconfigurable logic circuits, because room-temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be used to manipulate such signals. Here, we report the experimental demonstration of spin transport in nondegenerate Si with a spin metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We successfully observe the modulation of the Hanle-type spin-precession signals, which is a characteristic spin dynamics in nondegenerate semiconductors. We obtain long spin transport of more than 20 μm and spin rotation greater than 4π at RT. We also observe gate-induced modulation of spin-transport signals at RT. The modulation of the spin diffusion length as a function of a gate voltage is successfully observed, which we attribute to the Elliott-Yafet spin relaxation mechanism. These achievements are expected to lead to the creation of practical Si-based spin MOSFETs.

A Compression Algorithm for Field Programmable Gate Arrays in the Space Environment

DTIC Science & Technology

2011-12-01

Bit 1 ,Bit 0P  . (V.3) Equation (V.3) is implemented with a string of XOR gates and Bit Basher blocks, as shown in Figure 31. As discussed in...5], the string of Bit Basher blocks are used to separate each 35-bit value into 35 one-bit values, and the string of XOR gates is used to

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

PubMed Central

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system. PMID:25346683

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

PubMed

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

A mixed-signal implementation of a polychronous spiking neural network with delay adaptation

PubMed Central

Wang, Runchun M.; Hamilton, Tara J.; Tapson, Jonathan C.; van Schaik, André

2014-01-01

We present a mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns. The proposed neural network contains one neuron array and one axon array. Spike Timing Dependent Delay Plasticity is used to fine-tune delays and add dynamics to the network. In our mixed-signal implementation, the neurons and axons have been implemented as both analog and digital circuits. The system thus consists of one FPGA, containing the digital neuron array and the digital axon array, and one analog IC containing the analog neuron array and the analog axon array. The system can be easily configured to use different combinations of each. We present and discuss the experimental results of all combinations of the analog and digital axon arrays and the analog and digital neuron arrays. The test results show that the proposed neural network is capable of successfully recalling more than 85% of stored patterns using both analog and digital circuits. PMID:24672422

A mixed-signal implementation of a polychronous spiking neural network with delay adaptation.

PubMed

Wang, Runchun M; Hamilton, Tara J; Tapson, Jonathan C; van Schaik, André

2014-01-01

We present a mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns. The proposed neural network contains one neuron array and one axon array. Spike Timing Dependent Delay Plasticity is used to fine-tune delays and add dynamics to the network. In our mixed-signal implementation, the neurons and axons have been implemented as both analog and digital circuits. The system thus consists of one FPGA, containing the digital neuron array and the digital axon array, and one analog IC containing the analog neuron array and the analog axon array. The system can be easily configured to use different combinations of each. We present and discuss the experimental results of all combinations of the analog and digital axon arrays and the analog and digital neuron arrays. The test results show that the proposed neural network is capable of successfully recalling more than 85% of stored patterns using both analog and digital circuits.

Reconfigurable Full-Page Braille Displays

NASA Technical Reports Server (NTRS)

Garner, H. Douglas

1994-01-01

Electrically actuated braille display cells of proposed type arrayed together to form full-page braille displays. Like other braille display cells, these provide changeable patterns of bumps driven by digitally recorded text stored on magnetic tapes or in solid-state electronic memories. Proposed cells contain electrorheological fluid. Viscosity of such fluid increases in strong electrostatic field.

Three fundamental devices in one: a reconfigurable multifunctional device in two-dimensional WSe2

NASA Astrophysics Data System (ADS)

Dhakras, Prathamesh; Agnihotri, Pratik; Lee, Ji Ung

2017-06-01

The three pillars of semiconductor device technologies are (1) the p-n diode, (2) the metal-oxide-semiconductor field-effect transistor and (3) the bipolar junction transistor. They have enabled the unprecedented growth in the field of information technology that we see today. Until recently, the technological revolution for better, faster and more efficient devices has been governed by scaling down the device dimensions following Moore’s Law. With the slowing of Moore’s law, there is a need for alternative materials and computing technologies that can continue the advancement in functionality. Here, we describe a single, dynamically reconfigurable device that implements these three fundamental device functions. The device uses buried gates to achieve n- and p-channels and fits into a larger effort to develop devices with enhanced functionalities, including logic functions, over device scaling. As they are all surface conducting devices, we use one material parameter, the interface trap density of states, to describe the key figure-of-merit of each device.

Reconfigurable p-n junction diodes and the photovoltaic effect in exfoliated MoS{sub 2} films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sutar, Surajit; Agnihotri, Pratik; Comfort, Everett

2014-03-24

Realizing basic semiconductor devices such as p-n junctions are necessary for developing thin-film and optoelectronic technologies in emerging planar materials such as MoS{sub 2}. In this work, electrostatic doping by buried gates is used to study the electronic and optoelectronic properties of p-n junctions in exfoliated MoS{sub 2} flakes. Creating a controllable doping gradient across the device leads to the observation of the photovoltaic effect in monolayer and bilayer MoS{sub 2} flakes. For thicker flakes, strong ambipolar conduction enables realization of fully reconfigurable p-n junction diodes with rectifying current-voltage characteristics, and diode ideality factors as low as 1.6. The spectralmore » response of the photovoltaic effect shows signatures of the predicted band gap transitions. For the first excitonic transition, a shift of >4{sub kB}T is observed between monolayer and bulk devices, indicating a thickness-dependence of the excitonic coulomb interaction.« less

Single-atom trapping and transport in DMD-controlled optical tweezers

NASA Astrophysics Data System (ADS)

Stuart, Dustin; Kuhn, Axel

2018-02-01

We demonstrate the trapping and manipulation of single neutral atoms in reconfigurable arrays of optical tweezers. Our approach offers unparalleled speed by using a Texas instruments digital micro-mirror device as a holographic amplitude modulator with a frame rate of 20 000 per second. We show the trapping of static arrays of up to 20 atoms, as well as transport of individually selected atoms over a distance of 25 μm with laser cooling and 4 μm without. We discuss the limitations of the technique and the scope for technical improvements.

KSC-03pd1181

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. - The STS-116 crew poses outside the SPACEHAB module during training. In the rear are Commander Terrence Wilcutt and Mission Specialist Christer Fuglesang; in front are Pilot William Oefelein and Mission Specialist Robert Curbeam. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

KSC-03pd1165

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. -- Members of the STS-116 crew look over equipment at SPACEHAB in Port Canaveral, Fla. On the left are Mission Specialists Robert Curbeam and Christer Fuglesang; on the right are Commander Terrence Wilcutt and Pilot William Oefelein. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

KSC-03pd1166

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. -- Members of the STS-116 crew handle equipment at SPACEHAB in Port Canaveral, Fla. On the left are Mission Specialists Robert Curbeam and Christer Fuglesang; on the right are Pilot William Oefelein (front) and Commander Terrence Wilcutt. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

KSC-03pd1170

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. -- The STS-116 crew poses outside the SPACEHAB module during training. In the rear are Commander Terrence Wilcutt and Mission Specialist Christer Fuglesang;; in front are Pilot William Oefelein and Mission Specialist Robert Curbeam. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

Integrated Reconfigurable Aperture, Digital Beam Forming, and Software GPS Receiver for UAV Navigation

DTIC Science & Technology

2007-12-11

Implemented both carrier and code phase tracking loop for performance evaluation of a minimum power beam forming algorithm and null steering algorithm...4 Antennal Antenna2 Antenna K RF RF RF ct, Ct~2 ChKx1 X2 ....... Xk A W ~ ~ =Z, x W ,=1 Fig. 5. Schematics of a K-element antenna array spatial...adaptive processor Antennal Antenna K A N-i V/ ( Vil= .i= VK Fig. 6. Schematics of a K-element antenna array space-time adaptive processor Two additional

Transient Negative Optical Nonlinearity of Indium Oxide Nanorod Arrays in the Full-Visible Range

DOE PAGES

Guo, Peijun; Chang, Robert P. H.; Schaller, Richard D.

2017-06-09

Dynamic control of the optical response of materials at visible wavelengths is key to future metamaterials and photonic integrated circuits. Here we demonstrate large amplitude, negative optical nonlinearity (Δ n from -0.05 to -0.09) of indium oxide nanorod arrays in the full-visible range. We experimentally quantify and theoretically calculate the optical nonlinearity, which arises from the modifications of interband optical transitions. Furthermore, the approach towards negative optical nonlinearity can be generalized to other transparent semiconductors and opens door to reconfigurable, sub-wavelength optical components.

KSC-03pd1180

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. - During a break in training at SPACEHAB, Port Canaveral, Fla., STS-116 Commander Terrence Wilcutt, Mission Specialist Christer Fuglesang and Pilot Michael Oelefein share a laugh. Not seen is Mission Specialist Robert Curbeam. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application

NASA Technical Reports Server (NTRS)

Sheldon, Douglas; Schone, Harald

2005-01-01

This viewgraph document reviews the issue of using Field Programmable Gate Arrays (FPGAs) in Space Application, and the some of the strategies for qualifying the FPGA. Qualification and risk management of such complex systems requires new approaches. The paper presents a matrix approach to qualification has been presented that: - Complements historical specifications - Highlights the importance of device physics as a cornerstone to qualification. - Provides levels of risk management that expressly document trade offs. - Stresses the role of the FPGA vendor as team member in the development of modern spacecraft.

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

NASA Astrophysics Data System (ADS)

Kim, J. B.; Won, E.

2018-03-01

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit.

PubMed

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-12-21

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10 -9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

NASA Astrophysics Data System (ADS)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-12-01

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10-9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

PubMed Central

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-01-01

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than −30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10−9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers. PMID:28000735

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Liquid-based gating mechanism with tunable multiphase selectivity and antifouling behaviour

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hou, X; Hu, YH; Grinthal, A

Living organisms make extensive use of micro- and nanometre-sized pores as gatekeepers for controlling the movement of fluids, vapours and solids between complex environments. The ability of such pores to coordinate multiphase transport, in a highly selective and subtly triggered fashion and without clogging, has inspired interest in synthetic gated pores for applications ranging from fluid processing to 3D printing and lab-on-chip systems(1-10). But although specific gating and transport behaviours have been realized by precisely tailoring pore surface chemistries and pore geometries(6,11-17), a single system capable of controlling complex, selective multiphase transport has remained a distant prospect, and fouling ismore » nearly inevitable(11,12). Here we introduce a gating mechanism that uses a capillary-stabilized liquid as a reversible, reconfigurable gate that fills and seals pores in the closed state, and creates a non-fouling, liquid-lined pore in the open state. Theoretical modelling and experiments demonstrate that for each transport substance, the gating threshold-the pressure needed to open the pores-can be rationally tuned over a wide pressure range. This enables us to realize in one system differential response profiles for a variety of liquids and gases, even letting liquids flow through the pore while preventing gas from escaping. These capabilities allow us to dynamically modulate gas-liquid sorting in a microfluidic flow and to separate a three-phase air-water-oil mixture, with the liquid lining ensuring sustained antifouling behaviour. Because the liquid gating strategy enables efficient long-term operation and can be applied to a variety of pore structures and membrane materials, and to micro- as well as macroscale fluid systems, we expect it to prove useful in a wide range of applications.« less

Liquid-based gating mechanism with tunable multiphase selectivity and antifouling behaviour

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hou, Xu; Hu, Yuhang; Grinthal, Alison

Living organisms make extensive use of micro- and nanometre-sized pores as gatekeepers for controlling the movement of fluids, vapours and solids between complex environments. In addition, the ability of such pores to coordinate multiphase transport, in a highly selective and subtly triggered fashion and without clogging, has inspired interest in synthetic gated pores for applications ranging from fluid processing to 3D printing and lab-on-chip systems 1-10.But although specific gating and transport behaviours have been realized by precisely tailoring pore surface chemistries and pore geometries 6,11–17, a single system capable of controlling complex, selective multiphase transport has remained a distant prospect,more » and fouling is nearly inevitable.Here we introduce a gating mechanism that uses a capillary-stabilized liquid as a reversible, reconfigurable gate that fills and seals pores in the closed state, and creates a non-fouling, liquid-lined pore in the open state.Theoretical modelling and experiments demonstrate that for each transport substance, the gating threshold—the pressure needed to open the pores—can be rationally tuned over a wide pressure range. This enables us to realize in one system differential response profiles for a variety of liquids and gases, even letting liquids flow through the pore while preventing gas from escaping.These capabilities allow us to dynamically modulate gas–liquid sorting in a microfluidic flow and to separate a three-phase air water–oil mixture, with the liquid lining ensuring sustained antifouling behaviour. Because the liquid gating strategy enables efficient long-term operation and can be applied to a variety of pore structures and membrane materials, and to micro- as well as macroscale fluid systems, we expect it to prove useful in a wide range of applications.« less

Liquid-based gating mechanism with tunable multiphase selectivity and antifouling behaviour

NASA Astrophysics Data System (ADS)

Hou, Xu; Hu, Yuhang; Grinthal, Alison; Khan, Mughees; Aizenberg, Joanna

2015-03-01

Living organisms make extensive use of micro- and nanometre-sized pores as gatekeepers for controlling the movement of fluids, vapours and solids between complex environments. The ability of such pores to coordinate multiphase transport, in a highly selective and subtly triggered fashion and without clogging, has inspired interest in synthetic gated pores for applications ranging from fluid processing to 3D printing and lab-on-chip systems. But although specific gating and transport behaviours have been realized by precisely tailoring pore surface chemistries and pore geometries, a single system capable of controlling complex, selective multiphase transport has remained a distant prospect, and fouling is nearly inevitable. Here we introduce a gating mechanism that uses a capillary-stabilized liquid as a reversible, reconfigurable gate that fills and seals pores in the closed state, and creates a non-fouling, liquid-lined pore in the open state. Theoretical modelling and experiments demonstrate that for each transport substance, the gating threshold--the pressure needed to open the pores--can be rationally tuned over a wide pressure range. This enables us to realize in one system differential response profiles for a variety of liquids and gases, even letting liquids flow through the pore while preventing gas from escaping. These capabilities allow us to dynamically modulate gas-liquid sorting in a microfluidic flow and to separate a three-phase air-water-oil mixture, with the liquid lining ensuring sustained antifouling behaviour. Because the liquid gating strategy enables efficient long-term operation and can be applied to a variety of pore structures and membrane materials, and to micro- as well as macroscale fluid systems, we expect it to prove useful in a wide range of applications.

Liquid-based gating mechanism with tunable multiphase selectivity and antifouling behaviour

DOE PAGES

Hou, Xu; Hu, Yuhang; Grinthal, Alison; ...

2015-03-04

Living organisms make extensive use of micro- and nanometre-sized pores as gatekeepers for controlling the movement of fluids, vapours and solids between complex environments. In addition, the ability of such pores to coordinate multiphase transport, in a highly selective and subtly triggered fashion and without clogging, has inspired interest in synthetic gated pores for applications ranging from fluid processing to 3D printing and lab-on-chip systems 1-10.But although specific gating and transport behaviours have been realized by precisely tailoring pore surface chemistries and pore geometries 6,11–17, a single system capable of controlling complex, selective multiphase transport has remained a distant prospect,more » and fouling is nearly inevitable.Here we introduce a gating mechanism that uses a capillary-stabilized liquid as a reversible, reconfigurable gate that fills and seals pores in the closed state, and creates a non-fouling, liquid-lined pore in the open state.Theoretical modelling and experiments demonstrate that for each transport substance, the gating threshold—the pressure needed to open the pores—can be rationally tuned over a wide pressure range. This enables us to realize in one system differential response profiles for a variety of liquids and gases, even letting liquids flow through the pore while preventing gas from escaping.These capabilities allow us to dynamically modulate gas–liquid sorting in a microfluidic flow and to separate a three-phase air water–oil mixture, with the liquid lining ensuring sustained antifouling behaviour. Because the liquid gating strategy enables efficient long-term operation and can be applied to a variety of pore structures and membrane materials, and to micro- as well as macroscale fluid systems, we expect it to prove useful in a wide range of applications.« less

Liquid-based gating mechanism with tunable multiphase selectivity and antifouling behaviour.

PubMed

Hou, Xu; Hu, Yuhang; Grinthal, Alison; Khan, Mughees; Aizenberg, Joanna

2015-03-05

Living organisms make extensive use of micro- and nanometre-sized pores as gatekeepers for controlling the movement of fluids, vapours and solids between complex environments. The ability of such pores to coordinate multiphase transport, in a highly selective and subtly triggered fashion and without clogging, has inspired interest in synthetic gated pores for applications ranging from fluid processing to 3D printing and lab-on-chip systems. But although specific gating and transport behaviours have been realized by precisely tailoring pore surface chemistries and pore geometries, a single system capable of controlling complex, selective multiphase transport has remained a distant prospect, and fouling is nearly inevitable. Here we introduce a gating mechanism that uses a capillary-stabilized liquid as a reversible, reconfigurable gate that fills and seals pores in the closed state, and creates a non-fouling, liquid-lined pore in the open state. Theoretical modelling and experiments demonstrate that for each transport substance, the gating threshold-the pressure needed to open the pores-can be rationally tuned over a wide pressure range. This enables us to realize in one system differential response profiles for a variety of liquids and gases, even letting liquids flow through the pore while preventing gas from escaping. These capabilities allow us to dynamically modulate gas-liquid sorting in a microfluidic flow and to separate a three-phase air-water-oil mixture, with the liquid lining ensuring sustained antifouling behaviour. Because the liquid gating strategy enables efficient long-term operation and can be applied to a variety of pore structures and membrane materials, and to micro- as well as macroscale fluid systems, we expect it to prove useful in a wide range of applications.

Terahertz modulation based on surface plasmon resonance by self-gated graphene

NASA Astrophysics Data System (ADS)

Qian, Zhenhai; Yang, Dongxiao; Wang, Wei

2018-05-01

We theoretically and numerically investigate the extraordinary optical transmission through a terahertz metamaterial composed of metallic ring aperture arrays. The physical mechanism of different transmission peaks is elucidated to be magnetic polaritons or propagation surface plasmons with the help of surface current and electromagnetic field distributions at respective resonance frequencies. Then, we propose a high performance terahertz modulator based on the unique PSP resonance and combined with the metallic ring aperture arrays and a self-gated parallel-plate graphene capacitor. Because, to date, few researches have exhibited gate-controlled graphene modulation in terahertz region with low insertion losses, high modulation depth and low control voltage at room temperature. Here, we propose a 96% amplitude modulation with 0.7 dB insertion losses and ∼5.5 V gate voltage. Besides, we further study the absorption spectra of the modulator. When the transmission of modulator is very low, a 91% absorption can be achieved for avoiding damaging the source devices.

A Programmable and Configurable Mixed-Mode FPAA SoC

DTIC Science & Technology

2016-03-17

A Programmable and Configurable Mixed-Mode FPAA SoC Sahil Shah, Sihwan Kim, Farhan Adil, Jennifer Hasler, Suma George, Michelle Collins, Richard...Abstract: The authors present a Floating-Gate based, System-On-Chip large-scale Field- Programmable Analog Array IC that integrates divergent concepts...Floating-Gate, SoC, Command Word Classification This paper presents a Floating-Gate (FG) based, System- On-Chip (SoC) large-scale Field- Programmable

Two stage dual gate MESFET monolithic gain control amplifier for Ka-band

NASA Technical Reports Server (NTRS)

Sokolov, V.; Geddes, J.; Contolatis, A.

1987-01-01

A monolithic two stage gain control amplifier has been developed using submicron gate length dual gate MESFETs fabricated on ion implanted material. The amplifier has a gain of 12 dB at 30 GHz with a gain control range of over 30 dB. This ion implanted monolithic IC is readily integrable with other phased array receiver functions such as low noise amplifiers and phase shifters.

Master-slave mixed arrays for data-flow computations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, T.L.; Fisher, P.D.

1983-01-01

Control cells (masters) and computation cells (slaves) are mixed in regular geometric patterns to form reconfigurable arrays known as master-slave mixed arrays (MSMAS). Interconnections of the corners and edges of the hexagonal control cells and the edges of the hexagonal computation cells are used to construct synchronous and asynchronous communication networks, which support local computation and local communication. Data-driven computations result in self-directed ring pipelines within the MSMA, and composite data-flow computations are executed in a pipelined fashion. By viewing an MSMA as a computing network of tightly-linked ring pipelines, data-flow programs can be uniformly distributed over these pipelines formore » efficient resource utilisation. 9 references.« less

Reconfigurable Microfluidic Magnetic Valve Arrays: Towards a Radiotherapy-Compatible Spheroid Culture Platform for the Combinatorial Screening of Cancer Therapies

PubMed Central

Labelle, Frédérique; Wong, Philip

2017-01-01

We introduce here a microfluidic cell culture platform or spheroid culture chamber array (SCCA) that can synthesize, culture, and enable fluorescence imaging of 3D cell aggregates (typically spheroids) directly on-chip while specifying the flow of reagents in each chamber via the use of an array of passive magnetic valves. The SCCA valves demonstrated sufficient resistance to burst (above 100 mBar), including after receiving radiotherapy (RT) doses of up to 8 Gy combined with standard 37 °C incubation for up to 7 days, enabling the simultaneous synthesis of multiple spheroids from different cell lines on the same array. Our results suggest that SCCA would be an asset in drug discovery processes, seeking to identify combinatorial treatments. PMID:28976942

Golden Gate Assembly of CRISPR gRNA expression array for simultaneously targeting multiple genes.

PubMed

Vad-Nielsen, Johan; Lin, Lin; Bolund, Lars; Nielsen, Anders Lade; Luo, Yonglun

2016-11-01

The engineered CRISPR/Cas9 technology has developed as the most efficient and broadly used genome editing tool. However, simultaneously targeting multiple genes (or genomic loci) in the same individual cells using CRISPR/Cas9 remain one technical challenge. In this article, we have developed a Golden Gate Assembly method for the generation of CRISPR gRNA expression arrays, thus enabling simultaneous gene targeting. Using this method, the generation of CRISPR gRNA expression array can be accomplished in 2 weeks, and contains up to 30 gRNA expression cassettes. We demonstrated in the study that simultaneously targeting 10 genomic loci or simultaneously inhibition of multiple endogenous genes could be achieved using the multiplexed gRNA expression array vector in human cells. The complete set of plasmids is available through the non-profit plasmid repository Addgene.

High-resolution depth profiling using a range-gated CMOS SPAD quanta image sensor.

PubMed

Ren, Ximing; Connolly, Peter W R; Halimi, Abderrahim; Altmann, Yoann; McLaughlin, Stephen; Gyongy, Istvan; Henderson, Robert K; Buller, Gerald S

2018-03-05

A CMOS single-photon avalanche diode (SPAD) quanta image sensor is used to reconstruct depth and intensity profiles when operating in a range-gated mode used in conjunction with pulsed laser illumination. By designing the CMOS SPAD array to acquire photons within a pre-determined temporal gate, the need for timing circuitry was avoided and it was therefore possible to have an enhanced fill factor (61% in this case) and a frame rate (100,000 frames per second) that is more difficult to achieve in a SPAD array which uses time-correlated single-photon counting. When coupled with appropriate image reconstruction algorithms, millimeter resolution depth profiles were achieved by iterating through a sequence of temporal delay steps in synchronization with laser illumination pulses. For photon data with high signal-to-noise ratios, depth images with millimeter scale depth uncertainty can be estimated using a standard cross-correlation approach. To enhance the estimation of depth and intensity images in the sparse photon regime, we used a bespoke clustering-based image restoration strategy, taking into account the binomial statistics of the photon data and non-local spatial correlations within the scene. For sparse photon data with total exposure times of 75 ms or less, the bespoke algorithm can reconstruct depth images with millimeter scale depth uncertainty at a stand-off distance of approximately 2 meters. We demonstrate a new approach to single-photon depth and intensity profiling using different target scenes, taking full advantage of the high fill-factor, high frame rate and large array format of this range-gated CMOS SPAD array.

Digital Beamforming Scatterometer

NASA Technical Reports Server (NTRS)

Rincon, Rafael F.; Vega, Manuel; Kman, Luko; Buenfil, Manuel; Geist, Alessandro; Hillard, Larry; Racette, Paul

2009-01-01

This paper discusses scatterometer measurements collected with multi-mode Digital Beamforming Synthetic Aperture Radar (DBSAR) during the SMAP-VEX 2008 campaign. The 2008 SMAP Validation Experiment was conducted to address a number of specific questions related to the soil moisture retrieval algorithms. SMAP-VEX 2008 consisted on a series of aircraft-based.flights conducted on the Eastern Shore of Maryland and Delaware in the fall of 2008. Several other instruments participated in the campaign including the Passive Active L-Band System (PALS), the Marshall Airborne Polarimetric Imaging Radiometer (MAPIR), and the Global Positioning System Reflectometer (GPSR). This campaign was the first SMAP Validation Experiment. DBSAR is a multimode radar system developed at NASA/Goddard Space Flight Center that combines state-of-the-art radar technologies, on-board processing, and advances in signal processing techniques in order to enable new remote sensing capabilities applicable to Earth science and planetary applications [l]. The instrument can be configured to operate in scatterometer, Synthetic Aperture Radar (SAR), or altimeter mode. The system builds upon the L-band Imaging Scatterometer (LIS) developed as part of the RadSTAR program. The radar is a phased array system designed to fly on the NASA P3 aircraft. The instrument consists of a programmable waveform generator, eight transmit/receive (T/R) channels, a microstrip antenna, and a reconfigurable data acquisition and processor system. Each transmit channel incorporates a digital attenuator, and digital phase shifter that enables amplitude and phase modulation on transmit. The attenuators, phase shifters, and calibration switches are digitally controlled by the radar control card (RCC) on a pulse by pulse basis. The antenna is a corporate fed microstrip patch-array centered at 1.26 GHz with a 20 MHz bandwidth. Although only one feed is used with the present configuration, a provision was made for separate corporate feeds for vertical and horizontal polarization. System upgrades to dual polarization are currently under way. The DBSAR processor is a reconfigurable data acquisition and processor system capable of real-time, high-speed data processing. DBSAR uses an FPGA-based architecture to implement digitally down-conversion, in-phase and quadrature (I/Q) demodulation, and subsequent radar specific algorithms. The core of the processor board consists of an analog-to-digital (AID) section, three Altera Stratix field programmable gate arrays (FPGAs), an ARM microcontroller, several memory devices, and an Ethernet interface. The processor also interfaces with a navigation board consisting of a GPS and a MEMS gyro. The processor has been configured to operate in scatterometer, Synthetic Aperture Radar (SAR), and altimeter modes. All the modes are based on digital beamforming which is a digital process that generates the far-field beam patterns at various scan angles from voltages sampled in the antenna array. This technique allows steering the received beam and controlling its beam-width and side-lobe. Several beamforming techniques can be implemented each characterized by unique strengths and weaknesses, and each applicable to different measurement scenarios. In Scatterometer mode, the radar is capable to.generate a wide beam or scan a narrow beam on transmit, and to steer the received beam on processing while controlling its beamwidth and side-lobe level. Table I lists some important radar characteristics

TU-E-BRB-08: Dual Gated Volumetric Modulated Arc Therapy.

PubMed

Wu, J; Fahimian, B; Wu, H; Xing, L

2012-06-01

Gated Volumetric Modulated Arc Therapy (VMAT) is an emerging treatment modality for Stereotactic Body Radiotherapy (SBRT). However, gating significantly prolongs treatment time. In order to enhance treatment efficiency, a novel dual gated VMAT, in which dynamic arc deliveries are executed sequentially in alternating exhale and inhale phases, is proposed and evaluated experimentally. The essence of dual gated VMAT is to take advantage of the natural pauses that occur at inspiration and exhalation by alternatively delivering the dose at the two phases, instead of the exhale window only. The arc deliveries at the two phases are realized by rotating gantry forward at the exhale window and backward at the inhale in an alternative fashion. Custom XML scripts were developed in Varian's TrueBeam STx Developer Mode to enable dual gated VMAT delivery. RapidArc plans for a lung case were generated for both inhale and exhale phases. The two plans were then combined into a dual gated arc by interleaving the arc treatment nodes of the two RapidArc plans. The dual gated plan was delivered in the development mode of TrueBeam LINAC onto a motion phantom and the delivery was measured by using pinpoint chamber/film/diode array (delta 4). The measured dose distribution was compared with that computed using Eclipse AAA algorithm. The treatment delivery time was recorded and compared with the corresponding single gated plans. Relative to the corresponding single gated delivery, it was found that treatment time efficiency was improved by 95.5% for the case studied here. Pinpoint chamber absolute dose measurement agreed the calculation to within 0.7%. Diode chamber array measurements revealed that 97.5% of measurement points of dual gated RapidArc delivery passed the 3% and 3mm gamma-test criterion. A dual gated VMAT treatment has been developed and implemented successfully with nearly doubled treatment delivery efficiency. © 2012 American Association of Physicists in Medicine.

Pixel parallel localized driver design for a 128 x 256 pixel array 3D 1Gfps image sensor

NASA Astrophysics Data System (ADS)

Zhang, C.; Dao, V. T. S.; Etoh, T. G.; Charbon, E.

2017-02-01

In this paper, a 3D 1Gfps BSI image sensor is proposed, where 128 × 256 pixels are located in the top-tier chip and a 32 × 32 localized driver array in the bottom-tier chip. Pixels are designed with Multiple Collection Gates (MCG), which collects photons selectively with different collection gates being active at intervals of 1ns to achieve 1Gfps. For the drivers, a global PLL is designed, which consists of a ring oscillator with 6-stage current starved differential inverters, achieving a wide frequency tuning range from 40MHz to 360MHz (20ps rms jitter). The drivers are the replicas of the ring oscillator that operates within a PLL. Together with level shifters and XNOR gates, continuous 3.3V pulses are generated with desired pulse width, which is 1/12 of the PLL clock period. The driver array is activated by a START signal, which propagates through a highly balanced clock tree, to activate all the pixels at the same time with virtually negligible skew.

Resonant tunneling of 1-dimensional electrons across an array of 3-dimensionally confined potential wells

NASA Astrophysics Data System (ADS)

Allee, D. R.; Chou, S. Y.; Harris, J. S.; Pease, R. F. W.

A lateral resonant tunneling field effect transistor has been fabricated with a gate electrode in the form of a railway such that the two rails form a lateral double barrier potential at the GaAs/AlGaAs interface. The ties confine the electrons in the third dimension forming an array of potential boxes or three dimensionally confined potential wells. The width of the ties and rails is 50nm; the spacings between the ties and between the two rails are 230nm and 150nm respectively. The ties are 750nm long and extend beyond the the two rails forming one dimensional wires on either side. Conductance oscillations are observed in the drain current at 4.2K as the gate voltage is scanned. Comparison with devices with a solid gate, and with a monorail gate with ties fabricated on the same wafer suggest that these conductance oscillations are electron resonant tunneling from one dimensional wires through the quasi-bound states of the three dimensionally confined potential wells. Comparison with a device with a two rail gate without ties (previously published) indicates that additional confinement due to the ties enhances the strength of the conductance oscillations.

Modular, Reconfigurable, High-Energy Technology Development

NASA Technical Reports Server (NTRS)

Carrington, Connie; Howell, Joe

2006-01-01

The Modular, Reconfigurable High-Energy (MRHE) Technology Demonstrator project was to have been a series of ground-based demonstrations to mature critical technologies needed for in-space assembly of a highpower high-voltage modular spacecraft in low Earth orbit, enabling the development of future modular solar-powered exploration cargo-transport vehicles and infrastructure. MRHE was a project in the High Energy Space Systems (HESS) Program, within NASA's Exploration Systems Research and Technology (ESR&T) Program. NASA participants included Marshall Space Flight Center (MSFC), the Jet Propulsion Laboratory (JPL), and Glenn Research Center (GRC). Contractor participants were the Boeing Phantom Works in Huntsville, AL, Lockheed Martin Advanced Technology Center in Palo Alto, CA, ENTECH, Inc. in Keller, TX, and the University of AL Huntsville (UAH). MRHE's technical objectives were to mature: (a) lightweight, efficient, high-voltage, radiation-resistant solar power generation (SPG) technologies; (b) innovative, lightweight, efficient thermal management systems; (c) efficient, 100kW-class, high-voltage power delivery systems from an SPG to an electric thruster system; (d) autonomous rendezvous and docking technology for in-space assembly of modular, reconfigurable spacecraft; (e) robotic assembly of modular space systems; and (f) modular, reconfigurable distributed avionics technologies. Maturation of these technologies was to be implemented through a series of increasingly-inclusive laboratory demonstrations that would have integrated and demonstrated two systems-of-systems: (a) the autonomous rendezvous and docking of modular spacecraft with deployable structures, robotic assembly, reconfiguration both during assembly and (b) the development and integration of an advanced thermal heat pipe and a high-voltage power delivery system with a representative lightweight high-voltage SPG array. In addition, an integrated simulation testbed would have been developed containing software models representing the technologies being matured in the laboratory demos. The testbed would have also included models for non-MRHE developed subsystems such as electric propulsion, so that end-to-end performance could have been assessed. This paper presents an overview of the MRHE Phase I activities at MSFC and its contractor partners. One of the major Phase I accomplishments is the assembly demonstration in the Lockheed Martin Advanced Technology Center (LMATC) Robot-Satellite facility, in which three robot-satellites successfully demonstrated rendezvous & docking, self-assembly, reconfiguration, adaptable GN&C, deployment, and interfaces between modules. Phase I technology maturation results from ENTECH include material recommendations for radiation hardened Stretched Lens Array (SLA) concentrator lenses, and a design concept and test results for a hi-voltage PV receiver. UAH's accomplishments include Supertube heatpipe test results, which support estimates of thermal conductivities at 30,000 times that of an equivalent silver rod. MSFC performed systems trades and developed a preliminary concept design for a 100kW-class modular reconfigurable solar electric propulsion transport vehicle, and Boeing Phantom Works in Huntsville performed assembly and rendezvous and docking trades. A concept animation video was produced by SAIC, wllich showed rendezvous and docking and SLA-square-rigger deployment in LEO.

TID Effects of High-Z Material Spot Shields on FPGA Using MPTB Data

NASA Technical Reports Server (NTRS)

Hardage, Donna (Technical Monitor); Crain, S. H.; Mazur, J. E.; Looper, M. D.

2003-01-01

An experiment on the Microelectronics and Photonics Test Bed (MPTB) was testing lield programmable gate arrays using spot shields to extend the life of some of the devices being tested. It was expected that the unshielded parts would fail from a total ionizing dose (TID) and yet the opposite occurred. The data show that the devices failing from the TID effects are those with the spot shields attached. This effort is to determine the mechanism by which the environment is interacting with the high-Z material to enhance the TID in these field programmable gate arrays.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array.

PubMed

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Liang, Futian; Jin, Ge

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Kun; Wang, Xu; Li, Feng

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Field programmable gate array-assigned complex-valued computation and its limits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernard-Schwarz, Maria, E-mail: maria.bernardschwarz@ni.com; Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien; Zwick, Wolfgang

We discuss how leveraging Field Programmable Gate Array (FPGA) technology as part of a high performance computing platform reduces latency to meet the demanding real time constraints of a quantum optics simulation. Implementations of complex-valued operations using fixed point numeric on a Virtex-5 FPGA compare favorably to more conventional solutions on a central processing unit. Our investigation explores the performance of multiple fixed point options along with a traditional 64 bits floating point version. With this information, the lowest execution times can be estimated. Relative error is examined to ensure simulation accuracy is maintained.

A control system based on field programmable gate array for papermaking sewage treatment

NASA Astrophysics Data System (ADS)

Zhang, Zi Sheng; Xie, Chang; Qing Xiong, Yan; Liu, Zhi Qiang; Li, Qing

2013-03-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

Electrically switchable metadevices via graphene

PubMed Central

Balci, Osman; Kakenov, Nurbek; Karademir, Ertugrul; Balci, Sinan; Cakmakyapan, Semih; Polat, Emre O.; Caglayan, Humeyra; Özbay, Ekmel; Kocabas, Coskun

2018-01-01

Metamaterials bring subwavelength resonating structures together to overcome the limitations of conventional materials. The realization of active metadevices has been an outstanding challenge that requires electrically reconfigurable components operating over a broad spectrum with a wide dynamic range. However, the existing capability of metamaterials is not sufficient to realize this goal. By integrating passive metamaterials with active graphene devices, we demonstrate a new class of electrically controlled active metadevices working in microwave frequencies. The fabricated active metadevices enable efficient control of both amplitude (>50 dB) and phase (>90°) of electromagnetic waves. In this hybrid system, graphene operates as a tunable Drude metal that controls the radiation of the passive metamaterials. Furthermore, by integrating individually addressable arrays of metadevices, we demonstrate a new class of spatially varying digital metasurfaces where the local dielectric constant can be reconfigured with applied bias voltages. In addition, we reconfigure resonance frequency of split-ring resonators without changing its amplitude by damping one of the two coupled metasurfaces via graphene. Our approach is general enough to implement various metamaterial systems that could yield new applications ranging from electrically switchable cloaking devices to adaptive camouflage systems. PMID:29322094

Floating gate memory with charge storage dots array formed by Dps protein modified with site-specific binding peptides

NASA Astrophysics Data System (ADS)

Kamitake, Hiroki; Uenuma, Mutsunori; Okamoto, Naofumi; Horita, Masahiro; Ishikawa, Yasuaki; Yamashita, Ichro; Uraoka, Yukiharu

2015-05-01

We report a nanodot (ND) floating gate memory (NFGM) with a high-density ND array formed by a biological nano process. We utilized two kinds of cage-shaped proteins displaying SiO2 binding peptide (minTBP-1) on their outer surfaces: ferritin and Dps, which accommodate cobalt oxide NDs in their cavities. The diameters of the cobalt NDs were regulated by the cavity sizes of the proteins. Because minTBP-1 is strongly adsorbed on the SiO2 surface, high-density cobalt oxide ND arrays were obtained by a simple spin coating process. The densities of cobalt oxide ND arrays based on ferritin and Dps were 6.8 × 1011 dots cm-2 and 1.2 × 1012 dots cm-2, respectively. After selective protein elimination and embedding in a metal-oxide-semiconductor (MOS) capacitor, the charge capacities of both ND arrays were evaluated by measuring their C-V characteristics. The MOS capacitor embedded with the Dps ND array showed a wider memory window than the device embedded with the ferritin ND array. Finally, we fabricated an NFGM with a high-density ND array based on Dps, and confirmed its competent writing/erasing characteristics and long retention time.

Integration of digital signal processing technologies with pulsed electron paramagnetic resonance imaging

PubMed Central

Pursley, Randall H.; Salem, Ghadi; Devasahayam, Nallathamby; Subramanian, Sankaran; Koscielniak, Janusz; Krishna, Murali C.; Pohida, Thomas J.

2006-01-01

The integration of modern data acquisition and digital signal processing (DSP) technologies with Fourier transform electron paramagnetic resonance (FT-EPR) imaging at radiofrequencies (RF) is described. The FT-EPR system operates at a Larmor frequency (Lf) of 300 MHz to facilitate in vivo studies. This relatively low frequency Lf, in conjunction with our ~10 MHz signal bandwidth, enables the use of direct free induction decay time-locked subsampling (TLSS). This particular technique provides advantages by eliminating the traditional analog intermediate frequency downconversion stage along with the corresponding noise sources. TLSS also results in manageable sample rates that facilitate the design of DSP-based data acquisition and image processing platforms. More specifically, we utilize a high-speed field programmable gate array (FPGA) and a DSP processor to perform advanced real-time signal and image processing. The migration to a DSP-based configuration offers the benefits of improved EPR system performance, as well as increased adaptability to various EPR system configurations (i.e., software configurable systems instead of hardware reconfigurations). The required modifications to the FT-EPR system design are described, with focus on the addition of DSP technologies including the application-specific hardware, software, and firmware developed for the FPGA and DSP processor. The first results of using real-time DSP technologies in conjunction with direct detection bandpass sampling to implement EPR imaging at RF frequencies are presented. PMID:16243552

NASA Accelerates SpaceCube Technology into Orbit

NASA Technical Reports Server (NTRS)

Petrick, David

2010-01-01

On May 11, 2009, STS-125 Space Shuttle Atlantis blasted off from Kennedy Space Center on a historic mission to service the Hubble Space Telescope (HST). In addition to sending up the hardware and tools required to repair the observatory, the servicing team at NASA's Goddard Space Flight Center also sent along a complex experimental payload called Relative Navigation Sensors (RNS). The main objective of the RNS payload was to provide real-time image tracking of HST during rendezvous and docking operations. RNS was a complete success, and was brought to life by four Xilinx FPGAs (Field Programmable Gate Arrays) tightly packed into one integrated computer called SpaceCube. SpaceCube is a compact, reconfigurable, multiprocessor computing platform for space applications demanding extreme processing capabilities based on Xilinx Virtex 4 FX60 FPGAs. In a matter of months, the concept quickly went from the white board to a fully funded flight project. The 4-inch by 4-inch SpaceCube processor card was prototyped by a group of Goddard engineers using internal research funding. Once engineers were able to demonstrate the processing power of SpaceCube to NASA, HST management stood behind the product and invested in a flight qualified version, inserting it into the heart of the RNS system. With the determination of putting Xilinx into space, the team strengthened to a small army and delivered a fully functional, space qualified system to the mission.

Dynamically reconfigurable photovoltaic system

DOEpatents

Okandan, Murat; Nielson, Gregory N.

2016-05-31

A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

Dynamically reconfigurable photovoltaic system

DOEpatents

Okandan, Murat; Nielson, Gregory N.

2016-12-27

A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

Neuron array with plastic synapses and programmable dendrites.

PubMed

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

KSC-03pd1179

NASA Image and Video Library

2003-04-17

KENNEDY SPACE CENTER, FLA. - At SPACEHAB, Port Canaveral, Fla., STS-116 Mission Specialist Christer Fuglesang (left) and Pilot Michael Oelefein share a laugh during a break in training. Fuglesang is with the European Space Agency. Not seen are Commander Terrence Wilcutt and Mission Specialist Robert Curbeam. Objective of their mission to the International Space Station is to deliver and attach the third port truss segment, the P5 Truss, deactivate and retract the P6 Truss Channel 4B (port-side) solar array, and reconfigure station power from 2A and 4A solar arrays. A launch date is under review.

Optical Interconnection Via Computer-Generated Holograms

NASA Technical Reports Server (NTRS)

Liu, Hua-Kuang; Zhou, Shaomin

1995-01-01

Method of free-space optical interconnection developed for data-processing applications like parallel optical computing, neural-network computing, and switching in optical communication networks. In method, multiple optical connections between multiple sources of light in one array and multiple photodetectors in another array made via computer-generated holograms in electrically addressed spatial light modulators (ESLMs). Offers potential advantages of massive parallelism, high space-bandwidth product, high time-bandwidth product, low power consumption, low cross talk, and low time skew. Also offers advantage of programmability with flexibility of reconfiguration, including variation of strengths of optical connections in real time.

Demonstration of a small programmable quantum computer with atomic qubits.

PubMed

Debnath, S; Linke, N M; Figgatt, C; Landsman, K A; Wright, K; Monroe, C

2016-08-04

Quantum computers can solve certain problems more efficiently than any possible conventional computer. Small quantum algorithms have been demonstrated on multiple quantum computing platforms, many specifically tailored in hardware to implement a particular algorithm or execute a limited number of computational paths. Here we demonstrate a five-qubit trapped-ion quantum computer that can be programmed in software to implement arbitrary quantum algorithms by executing any sequence of universal quantum logic gates. We compile algorithms into a fully connected set of gate operations that are native to the hardware and have a mean fidelity of 98 per cent. Reconfiguring these gate sequences provides the flexibility to implement a variety of algorithms without altering the hardware. As examples, we implement the Deutsch-Jozsa and Bernstein-Vazirani algorithms with average success rates of 95 and 90 per cent, respectively. We also perform a coherent quantum Fourier transform on five trapped-ion qubits for phase estimation and period finding with average fidelities of 62 and 84 per cent, respectively. This small quantum computer can be scaled to larger numbers of qubits within a single register, and can be further expanded by connecting several such modules through ion shuttling or photonic quantum channels.

Demonstration of a small programmable quantum computer with atomic qubits

NASA Astrophysics Data System (ADS)

Debnath, S.; Linke, N. M.; Figgatt, C.; Landsman, K. A.; Wright, K.; Monroe, C.

2016-08-01

Quantum computers can solve certain problems more efficiently than any possible conventional computer. Small quantum algorithms have been demonstrated on multiple quantum computing platforms, many specifically tailored in hardware to implement a particular algorithm or execute a limited number of computational paths. Here we demonstrate a five-qubit trapped-ion quantum computer that can be programmed in software to implement arbitrary quantum algorithms by executing any sequence of universal quantum logic gates. We compile algorithms into a fully connected set of gate operations that are native to the hardware and have a mean fidelity of 98 per cent. Reconfiguring these gate sequences provides the flexibility to implement a variety of algorithms without altering the hardware. As examples, we implement the Deutsch-Jozsa and Bernstein-Vazirani algorithms with average success rates of 95 and 90 per cent, respectively. We also perform a coherent quantum Fourier transform on five trapped-ion qubits for phase estimation and period finding with average fidelities of 62 and 84 per cent, respectively. This small quantum computer can be scaled to larger numbers of qubits within a single register, and can be further expanded by connecting several such modules through ion shuttling or photonic quantum channels.

A Novel Design of Reconfigurable Wavelength-Time Optical Codes to Enhance Security in Optical CDMA Networks

NASA Astrophysics Data System (ADS)

Nasaruddin; Tsujioka, Tetsuo

An optical CDMA (OCDMA) system is a flexible technology for future broadband multiple access networks. A secure OCDMA network in broadband optical access technologies is also becoming an issue of great importance. In this paper, we propose novel reconfigurable wavelength-time (W-T) optical codes that lead to secure transmission in OCDMA networks. The proposed W-T optical codes are constructed by using quasigroups (QGs) for wavelength hopping and one-dimensional optical orthogonal codes (OOCs) for time spreading; we call them QGs/OOCs. Both QGs and OOCs are randomly generated by a computer search to ensure that an eavesdropper could not improve its interception performance by making use of the coding structure. Then, the proposed reconfigurable QGs/OOCs can provide more codewords, and many different code set patterns, which differ in both wavelength and time positions for given code parameters. Moreover, the bit error probability of the proposed codes is analyzed numerically. To realize the proposed codes, a secure system is proposed by employing reconfigurable encoders/decoders based on array waveguide gratings (AWGs), which allow the users to change their codeword patterns to protect against eavesdropping. Finally, the probability of breaking a certain codeword in the proposed system is evaluated analytically. The results show that the proposed codes and system can provide a large codeword pattern, and decrease the probability of breaking a certain codeword, to enhance OCDMA network security.

AGILIS: Agile Guided Interferometer for Longbaseline Imaging Synthesis. Demonstration and concepts of reconfigurable optical imaging interferometers

NASA Astrophysics Data System (ADS)

Woillez, Julien; Lai, Olivier; Perrin, Guy; Reynaud, François; Baril, Marc; Dong, Yue; Fédou, Pierre

2017-06-01

Context. In comparison to the radio and sub-millimetric domains, imaging with optical interferometry is still in its infancy. Due to the limited number of telescopes in existing arrays, image generation is a demanding process that relies on time-consuming reconfiguration of the interferometer array and super-synthesis. Aims: Using single mode optical fibres for the coherent transport of light from the collecting telescopes to the focal plane, a new generation of interferometers optimized for imaging can be designed. Methods: To support this claim, we report on the successful completion of the `OHANA Iki project: an end-to-end, on-sky demonstration of a two-telescope interferometer, built around near-infrared single mode fibres, carried out as part of the `OHANA project. Results: Having demonstrated that coherent transport by single-mode fibres is feasible, we explore the concepts, performances, and limitations of a new imaging facility with single mode fibres at its heart: Agile Guided Interferometer for Longbaseline Imaging Synthesis (AGILIS). Conclusions: AGILIS has the potential of becoming a next generation facility or a precursor to a much larger project like the Planet Formation Imager (PFI).

An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

ERIC Educational Resources Information Center

Foster, D. L.

2012-01-01

For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

FPGAs in Space Environment and Design Techniques

NASA Technical Reports Server (NTRS)

Katz, Richard B.; Day, John H. (Technical Monitor)

2001-01-01

This viewgraph presentation gives an overview of Field Programmable Gate Arrays (FPGA) in the space environment and design techniques. Details are given on the effects of the space radiation environment, total radiation dose, single event upset, single event latchup, single event transient, antifuse technology and gate rupture, proton upsets and sensitivity, and loss of functionality.

Cryogenic on-chip multiplexer for the study of quantum transport in 256 split-gate devices

NASA Astrophysics Data System (ADS)

Al-Taie, H.; Smith, L. W.; Xu, B.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2013-06-01

We present a multiplexing scheme for the measurement of large numbers of mesoscopic devices in cryogenic systems. The multiplexer is used to contact an array of 256 split gates on a GaAs/AlGaAs heterostructure, in which each split gate can be measured individually. The low-temperature conductance of split-gate devices is governed by quantum mechanics, leading to the appearance of conductance plateaux at intervals of 2e2/h. A fabrication-limited yield of 94% is achieved for the array, and a "quantum yield" is also defined, to account for disorder affecting the quantum behaviour of the devices. The quantum yield rose from 55% to 86% after illuminating the sample, explained by the corresponding increase in carrier density and mobility of the two-dimensional electron gas. The multiplexer is a scalable architecture, and can be extended to other forms of mesoscopic devices. It overcomes previous limits on the number of devices that can be fabricated on a single chip due to the number of electrical contacts available, without the need to alter existing experimental set ups.

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

The quantal nature of Ca2+ sparks and in situ operation of the ryanodine receptor array in cardiac cells.

PubMed

Wang, Shi Qiang; Stern, Michael D; Ríos, Eduardo; Cheng, Heping

2004-03-16

Intracellular Ca(2+) release in many types of cells is mediated by ryanodine receptor Ca(2+) release channels (RyRCs) that are assembled into two-dimensional paracrystalline arrays in the endoplasmic/sarcoplasmic reticulum. However, the in situ operating mechanism of the RyRC array is unknown. Here, we found that the elementary Ca(2+) release events, Ca(2+) sparks from individual RyRC arrays in rat ventricular myocytes, exhibit quantized Ca(2+) release flux. Analysis of the quantal property of Ca(2+) sparks provided a view of unitary Ca(2+) current and gating kinetics of the RyRC in intact cells and revealed that spark activation involves dynamic recruitment of small, variable cohorts of RyRCs. Intriguingly, interplay of RyRCs in multichannel sparks renders an unusual, thermodynamically irreversible mode of channel gating that is unshared by an RyRC acting solo, nor by RyRCs in vitro. Furthermore, an array-based inhibitory feedback, overriding the regenerative Ca(2+)-induced Ca(2+) release of RyRCs, provides a supramolecular mechanism for the microscopic stability of intracellular Ca(2+) signaling.

Time-Reversal MUSIC Imaging with Time-Domain Gating Technique

NASA Astrophysics Data System (ADS)

Choi, Heedong; Ogawa, Yasutaka; Nishimura, Toshihiko; Ohgane, Takeo

A time-reversal (TR) approach with multiple signal classification (MUSIC) provides super-resolution for detection and localization using multistatic data collected from an array antenna system. The theory of TR-MUSIC assumes that the number of antenna elements is greater than that of scatterers (targets). Furthermore, it requires many sets of frequency-domain data (snapshots) in seriously noisy environments. Unfortunately, these conditions are not practical for real environments due to the restriction of a reasonable antenna structure as well as limited measurement time. We propose an approach that treats both noise reduction and relaxation of the transceiver restriction by using a time-domain gating technique accompanied with the Fourier transform before applying the TR-MUSIC imaging algorithm. Instead of utilizing the conventional multistatic data matrix (MDM), we employ a modified MDM obtained from the gating technique. The resulting imaging functions yield more reliable images with only a few snapshots regardless of the limitation of the antenna arrays.

Digital Logic and Reconfigurable Interconnects Using Aluminum Gallium Arsenide Electro-Optic Fredkin Gates

DTIC Science & Technology

1994-06-01

length and coupling coefficient for the zero-gap directional coupler are obtained by using Eq. 3.2.39. Bums and Milton Effective Index Method In a 1975...nj) with •i wavegulde thicness b. Effective index N1 is then used to find the effective >Vt.,:, ;- 105 c a ¶ 2 n. n_ z n2 - : n4 Three-Dimensional...constant for the TM, modes is determined in a manner similar to the one used for the TEp modes. First, effective index N1 of 2-D Waveguide I is found by

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

NASA Astrophysics Data System (ADS)

Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2014-01-01

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

Towards a DNA Nanoprocessor: Reusable Tile-Integrated DNA Circuits.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2016-08-22

Modern electronic microprocessors use semiconductor logic gates organized on a silicon chip to enable efficient inter-gate communication. Here, arrays of communicating DNA logic gates integrated on a single DNA tile were designed and used to process nucleic acid inputs in a reusable format. Our results lay the foundation for the development of a DNA nanoprocessor, a small and biocompatible device capable of performing complex analyses of DNA and RNA inputs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms.

PubMed

Pruttivarasin, Thaned; Katori, Hidetoshi

2015-11-01

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp; Katori, Hidetoshi; Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Complete all-optical processing polarization-based binary logic gates and optical processors.

PubMed

Zaghloul, Y A; Zaghloul, A R M

2006-10-16

We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple-input gates, and sequential and non-sequential Boolean expressions are presented and discussed. The operation of each design is simply understood by a bullet train traveling at the speed of light on a railroad system preconditioned by the crossover states predetermined by the control inputs. The presented designs allow for optical processing of the information eliminating the need to convert it, back and forth, to an electronic signal for processing purposes. All gates with a truth table, including for example Fredkin, Toffoli, testable reversible logic, and threshold logic gates, can be designed and implemented using the railroad architecture. That includes any future gates not known today. Those designs and the quantum gates are not discussed in this paper.

Electrostatically defined isolated domain wall in integer quantum Hall regime as precursor for reconfigurable Majorana network

NASA Astrophysics Data System (ADS)

Kazakov, Alexander; Simion, George; Kolkovsky, Valery; Adamus, Zbigniew; Karczewski, Grzegorz; Wojtowicz, Tomasz; Lyanda-Geller, Yuli; Rokhinson, Leonid

Development of a two-dimensional systems with reconfigurable one-dimensional topological superconductor channels became primary direction in experimental branch of Majorana physics. Such system would allow to probe non-Abelian properties of Majorana quasiparticles and realize the ultimate goal of Majorana research - topological qubit for topologically protected quantum computations. In order to create and exchange Majorana quasiparticles desired system may be spin-full, but fermion doubling should be lifted. These requirements may be fulfilled in domain walls (DW) which are formed during quantum Hall ferromagnet (QHF) transition when two Landau levels with opposite spin polarization become degenerate. We developed a system based on CdMnTe quantum well with engineered placement of Mn ions where exchange interaction and, consequently, QHF transition can be controlled by electrostatic gating. Using electrostatic control of exchange we create conductive channels of DWs which, unlike conventional edge channels, are not chiral and should contain both spin polarizations. We will present results on the formation of isolated DWs of various widths and discuss their transport properties. Department of Defence Office of Naval research Award N000141410339.

Flexible and stackable terahertz metamaterials via silver-nanoparticle inkjet printing

NASA Astrophysics Data System (ADS)

Kashiwagi, K.; Xie, L.; Li, X.; Kageyama, T.; Miura, M.; Miyashita, H.; Kono, J.; Lee, S.-S.

2018-04-01

There is presently much interest in tunable, flexible, or reconfigurable metamaterial structures that work in the terahertz frequency range. They can be useful for a range of applications, including spectroscopy, sensing, imaging, and communications. Various methods based on microelectromechanical systems have been used for fabricating terahertz metamaterials, but they typically require high-cost facilities and involve a number of time-consuming and intricate processes. Here, we demonstrate a simple, robust, and cost-effective method for fabricating flexible and stackable multiresonant terahertz metamaterials, using silver nanoparticle inkjet printing. Using this method, we designed and fabricated two arrays of split-ring resonators (SRRs) having different resonant frequencies on separate sheets of paper and then combined the two arrays by stacking. Through terahertz time-domain spectroscopy, we observed resonances at the frequencies expected for the individual SRR arrays as well as at a new frequency due to coupling between the two SRR arrays.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Magnetic-field-controlled reconfigurable semiconductor logic.

PubMed

Joo, Sungjung; Kim, Taeyueb; Shin, Sang Hoon; Lim, Ju Young; Hong, Jinki; Song, Jin Dong; Chang, Joonyeon; Lee, Hyun-Woo; Rhie, Kungwon; Han, Suk Hee; Shin, Kyung-Ho; Johnson, Mark

2013-02-07

Logic devices based on magnetism show promise for increasing computational efficiency while decreasing consumed power. They offer zero quiescent power and yet combine novel functions such as programmable logic operation and non-volatile built-in memory. However, practical efforts to adapt a magnetic device to logic suffer from a low signal-to-noise ratio and other performance attributes that are not adequate for logic gates. Rather than exploiting magnetoresistive effects that result from spin-dependent transport of carriers, we have approached the development of a magnetic logic device in a different way: we use the phenomenon of large magnetoresistance found in non-magnetic semiconductors in high electric fields. Here we report a device showing a strong diode characteristic that is highly sensitive to both the sign and the magnitude of an external magnetic field, offering a reversible change between two different characteristic states by the application of a magnetic field. This feature results from magnetic control of carrier generation and recombination in an InSb p-n bilayer channel. Simple circuits combining such elementary devices are fabricated and tested, and Boolean logic functions including AND, OR, NAND and NOR are performed. They are programmed dynamically by external electric or magnetic signals, demonstrating magnetic-field-controlled semiconductor reconfigurable logic at room temperature. This magnetic technology permits a new kind of spintronic device, characterized as a current switch rather than a voltage switch, and provides a simple and compact platform for non-volatile reconfigurable logic devices.

GATE: software for the analysis and visualization of high-dimensional time series expression data.

PubMed

MacArthur, Ben D; Lachmann, Alexander; Lemischka, Ihor R; Ma'ayan, Avi

2010-01-01

We present Grid Analysis of Time series Expression (GATE), an integrated computational software platform for the analysis and visualization of high-dimensional biomolecular time series. GATE uses a correlation-based clustering algorithm to arrange molecular time series on a two-dimensional hexagonal array and dynamically colors individual hexagons according to the expression level of the molecular component to which they are assigned, to create animated movies of systems-level molecular regulatory dynamics. In order to infer potential regulatory control mechanisms from patterns of correlation, GATE also allows interactive interroga-tion of movies against a wide variety of prior knowledge datasets. GATE movies can be paused and are interactive, allowing users to reconstruct networks and perform functional enrichment analyses. Movies created with GATE can be saved in Flash format and can be inserted directly into PDF manuscript files as interactive figures. GATE is available for download and is free for academic use from http://amp.pharm.mssm.edu/maayan-lab/gate.htm

NASA Tech Briefs, July 2005

NASA Technical Reports Server (NTRS)

2005-01-01

Thin-Film Resistance Heat-Flux Sensors Circuit Indicates that Voice-Recording Disks are Nearly Full Optical Sensing of Combustion Instabilities in Gas Turbines Topics include: Crane-Load Contact Sensor; Hexagonal and Pentagonal Fractal Multiband Antennas; Multifunctional Logic Gate Controlled by Temperature; Multifunctional Logic Gate Controlled by Supply Voltage; Power Divider for Waveforms Rich in Harmonics; SCB Quantum Computers Using iSWAP and 1-Qubit Rotations; CSAM Metrology Software Tool; Update on Rover Sequencing and Visualization Program; Selecting Data from a Star Catalog; Rotating Desk for Collaboration by Two Computer Programmers; Variable-Pressure Washer; Magnetically Attached Multifunction Maintenance Rover; Improvements in Fabrication of Sand/Binder Cores for Casting; Solid Freeform Fabrication of Composite-Material Objects; Efficient Computational Model of Hysteresis; Gauges for Highly Precise Metrology of a Compound Mirror; Improved Electrolytic Hydrogen Peroxide Generator; High-Power Fiber Lasers Using Photonic Band Gap Materials; Ontology-Driven Information Integration; Quantifying Traversability of Terrain for a Mobile Robot; More About Arc-Welding Process for Making Carbon Nanotubes; Controlling Laser Spot Size in Outer Space; or Software-Reconfigurable Processors for Spacecraft.

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

NASA Technical Reports Server (NTRS)

Vasile, Stefan; Lipson, Jerold

2012-01-01

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

A Triple-Mode Flexible E-Skin Sensor Interface for Multi-Purpose Wearable Applications

PubMed Central

Kim, Sung-Woo; Lee, Youngoh; Park, Jonghwa; Kim, Seungmok; Chae, Heeyoung; Ko, Hyunhyub

2017-01-01

This study presents a flexible wireless electronic skin (e-skin) sensor system that includes a multi-functional sensor device, a triple-mode reconfigurable readout integrated circuit (ROIC), and a mobile monitoring interface. The e-skin device’s multi-functionality is achieved by an interlocked micro-dome array structure that uses a polyvinylidene fluoride and reduced graphene oxide (PVDF/RGO) composite material that is inspired by the structure and functions of the human fingertip. For multi-functional implementation, the proposed triple-mode ROIC is reconfigured to support piezoelectric, piezoresistance, and pyroelectric interfaces through single-type e-skin sensor devices. A flexible system prototype was developed and experimentally verified to provide various wireless wearable sensing functions—including pulse wave, voice, chewing/swallowing, breathing, knee movements, and temperature—while their real-time sensed data are displayed on a smartphone. PMID:29286312

Optical network security using unipolar Walsh code

NASA Astrophysics Data System (ADS)

Sikder, Somali; Sarkar, Madhumita; Ghosh, Shila

2018-04-01

Optical code-division multiple-access (OCDMA) is considered as a good technique to provide optical layer security. Many research works have been published to enhance optical network security by using optical signal processing. The paper, demonstrates the design of the AWG (arrayed waveguide grating) router-based optical network for spectral-amplitude-coding (SAC) OCDMA networks with Walsh Code to design a reconfigurable network codec by changing signature codes to against eavesdropping. In this paper we proposed a code reconfiguration scheme to improve the network access confidentiality changing the signature codes by cyclic rotations, for OCDMA system. Each of the OCDMA network users is assigned a unique signature code to transmit the information and at the receiving end each receiver correlates its own signature pattern a(n) with the receiving pattern s(n). The signal arriving at proper destination leads to s(n)=a(n).

Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

DTIC Science & Technology

2004-01-01

VCSEL requires placing the array far enough as to overlap the entire footprint of the signal beam in order to record the hologram. Therefore, these...hologram that self-focuses, due to phase -conjugation, on the array of detectors in the chip. VC A 10 m m 10 mm 18mm 16mm SEL RRAY OPTICAL MEMORY LOGIC...the VCSEL array , the chip and the optical material, and the requirements they have to meet for their use in the OPGA system. Section

Auto and hetero-associative memory using a 2-D optical logic gate

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin (Inventor)

1992-01-01

An optical system for auto-associative and hetero-associative recall utilizing Hamming distance as the similarity measure between a binary input image vector V(sup k) and a binary image vector V(sup m) in a first memory array using an optical Exclusive-OR gate for multiplication of each of a plurality of different binary image vectors in memory by the input image vector. After integrating the light of each product V(sup k) x V(sup m), a shortest Hamming distance detection electronics module determines which product has the lowest light intensity and emits a signal that activates a light emitting diode to illuminate a corresponding image vector in a second memory array for display. That corresponding image vector is identical to the memory image vector V(sup m) in the first memory array for auto-associative recall or related to it, such as by name, for hetero-associative recall.

Reconfigurable superconducting vortex pinning potential for magnetic disks in hybrid structures

NASA Astrophysics Data System (ADS)

Marchiori, Estefani; Curran, Peter J.; Kim, Jangyong; Satchell, Nathan; Burnell, Gavin; Bending, Simon J.

2017-03-01

High resolution scanning Hall probe microscopy has been used to directly visualise the superconducting vortex behavior in hybrid structures consisting of a square array of micrometer-sized Py ferromagnetic disks covered by a superconducting Nb thin film. At remanence the disks exist in almost fully flux-closed magnetic vortex states, but the observed cloverleaf-like stray fields indicate the presence of weak in-plane anisotropy. Micromagnetic simulations suggest that the most likely origin is an unintentional shape anisotropy. We have studied the pinning of added free superconducting vortices as a function of the magnetisation state of the disks, and identified a range of different phenomena arising from competing energy contributions. We have also observed clear differences in the pinning landscape when the superconductor and the ferromagnet are electron ically coupled or insulated by a thin dielectric layer, with an indication of non-trivial vortex-vortex interactions. We demonstrate a complete reconfiguration of the vortex pinning potential when the magnetisation of the disks evolves from the vortex-like state to an onion-like one under an in-plane magnetic field. Our results are in good qualitative agreement with theoretical predictions and could form the basis of novel superconducting devices based on reconfigurable vortex pinning sites.

Reconfigurable superconducting vortex pinning potential for magnetic disks in hybrid structures.

PubMed

Marchiori, Estefani; Curran, Peter J; Kim, Jangyong; Satchell, Nathan; Burnell, Gavin; Bending, Simon J

2017-03-24

High resolution scanning Hall probe microscopy has been used to directly visualise the superconducting vortex behavior in hybrid structures consisting of a square array of micrometer-sized Py ferromagnetic disks covered by a superconducting Nb thin film. At remanence the disks exist in almost fully flux-closed magnetic vortex states, but the observed cloverleaf-like stray fields indicate the presence of weak in-plane anisotropy. Micromagnetic simulations suggest that the most likely origin is an unintentional shape anisotropy. We have studied the pinning of added free superconducting vortices as a function of the magnetisation state of the disks, and identified a range of different phenomena arising from competing energy contributions. We have also observed clear differences in the pinning landscape when the superconductor and the ferromagnet are electron ically coupled or insulated by a thin dielectric layer, with an indication of non-trivial vortex-vortex interactions. We demonstrate a complete reconfiguration of the vortex pinning potential when the magnetisation of the disks evolves from the vortex-like state to an onion-like one under an in-plane magnetic field. Our results are in good qualitative agreement with theoretical predictions and could form the basis of novel superconducting devices based on reconfigurable vortex pinning sites.

Within compound, from Gate House, looking northwest, Power Plant (Building ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

Within compound, from Gate House, looking northwest, Power Plant (Building 5761) to left, Electrical Substation (Building 5770) and Supply Warehouse (Building 5768) center, Satellite Communications Terminal (Building 5771) to far left - Beale Air Force Base, Perimeter Acquisition Vehicle Entry Phased-Array Warning System, End of Spencer Paul Road, north of Warren Shingle Road (14th Street), Marysville, Yuba County, CA

Low-Noise Free-Running High-Rate Photon-Counting for Space Communication and Ranging

NASA Technical Reports Server (NTRS)

Lu, Wei; Krainak, Michael A.; Yang, Guangning; Sun, Xiaoli; Merritt, Scott

2016-01-01

We present performance data for low-noise free-running high-rate photon counting method for space optical communication and ranging. NASA GSFC is testing the performance of two types of novel photon-counting detectors 1) a 2x8 mercury cadmium telluride (HgCdTe) avalanche array made by DRS Inc., and a 2) a commercial 2880-element silicon avalanche photodiode (APD) array. We successfully measured real-time communication performance using both the 2 detected-photon threshold and logic AND-gate coincidence methods. Use of these methods allows mitigation of dark count, after-pulsing and background noise effects without using other method of Time Gating The HgCdTe APD array routinely demonstrated very high photon detection efficiencies ((is) greater than 50%) at near infrared wavelength. The commercial silicon APD array exhibited a fast output with rise times of 300 ps and pulse widths of 600 ps. On-chip individually filtered signals from the entire array were multiplexed onto a single fast output. NASA GSFC has tested both detectors for their potential application for space communications and ranging. We developed and compare their performances using both the 2 detected photon threshold and coincidence methods.

Low-Noise Free-Running High-Rate Photon-Counting for Space Communication and Ranging

NASA Technical Reports Server (NTRS)

Lu, Wei; Krainak, Michael A.; Yang, Guan; Sun, Xiaoli; Merritt, Scott

2016-01-01

We present performance data for low-noise free-running high-rate photon counting method for space optical communication and ranging. NASA GSFC is testing the performance of two types of novel photon-counting detectors 1) a 2x8 mercury cadmium telluride (HgCdTe) avalanche array made by DRS Inc., and a 2) a commercial 2880-element silicon avalanche photodiode (APD) array. We successfully measured real-time communication performance using both the 2 detected-photon threshold and logic AND-gate coincidence methods. Use of these methods allows mitigation of dark count, after-pulsing and background noise effects without using other method of Time Gating The HgCdTe APD array routinely demonstrated very high photon detection efficiencies (50) at near infrared wavelength. The commercial silicon APD array exhibited a fast output with rise times of 300 ps and pulse widths of 600 ps. On-chip individually filtered signals from the entire array were multiplexed onto a single fast output. NASA GSFC has tested both detectors for their potential application for space communications and ranging. We developed and compare their performances using both the 2 detected photon threshold and coincidence methods.

A new 4D chaotic system with hidden attractor and its engineering applications: Analog circuit design and field programmable gate array implementation

NASA Astrophysics Data System (ADS)

Abdolmohammadi, Hamid Reza; Khalaf, Abdul Jalil M.; Panahi, Shirin; Rajagopal, Karthikeyan; Pham, Viet-Thanh; Jafari, Sajad

2018-06-01

Nowadays, designing chaotic systems with hidden attractor is one of the most interesting topics in nonlinear dynamics and chaos. In this paper, a new 4D chaotic system is proposed. This new chaotic system has no equilibria, and so it belongs to the category of systems with hidden attractors. Dynamical features of this system are investigated with the help of its state-space portraits, bifurcation diagram, Lyapunov exponents diagram, and basin of attraction. Also a hardware realisation of this system is proposed by using field programmable gate arrays (FPGA). In addition, an electronic circuit design for the chaotic system is introduced.

Surface-confined assemblies and polymers for molecular logic.

PubMed

de Ruiter, Graham; van der Boom, Milko E

2011-08-16

Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the output of one gate is used as the input for another gate. Using the same setup, we were able to display both combinatorial and sequential logic. We have demonstrated MBLC by coupling electrochemical inputs with optical readout, which resulted in various logic architectures built on a redox-active, functionalized surface. Electrochemically operated sequential logic systems such as flip-flops, multivalued logic, and multistate memory could enhance computational power without increasing spatial requirements. Applying multivalued digits in data storage could exponentially increase memory capacity. Furthermore, we evaluate the pros and cons of MBLC and identify targets for future research in this Account. © 2011 American Chemical Society

Two-dimensional radiant energy array computers and computing devices

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1976-01-01

Two dimensional digital computers and computer devices operate in parallel on rectangular arrays of digital radiant energy optical signal elements which are arranged in ordered rows and columns. Logic gate devices receive two input arrays and provide an output array having digital states dependent only on the digital states of the signal elements of the two input arrays at corresponding row and column positions. The logic devices include an array of photoconductors responsive to at least one of the input arrays for either selectively accelerating electrons to a phosphor output surface, applying potentials to an electroluminescent output layer, exciting an array of discrete radiant energy sources, or exciting a liquid crystal to influence crystal transparency or reflectivity.

Gate-Sensing the Potential Landscape of a GaAs Two-Dimensional Electron Gas

NASA Astrophysics Data System (ADS)

Croot, Xanthe; Mahoney, Alice; Pauka, Sebastian; Colless, James; Reilly, David; Watson, John; Fallahi, Saeed; Gardner, Geoff; Manfra, Michael; Lu, Hong; Gossard, Arthur

In situ dispersive gate sensors hold potential as a means of enabling the scalable readout of quantum dot arrays. Sensitive to quantum capacitance, dispersive sensors have been used to detect inter- and intra-dot transitions in GaAs double quantum dots, and can distinguish the spin states of singlet triplet qubits. In addition, the gate-sensing technique is likely of value in probing the physics of Majorana zero modes in nanowire devices. Beyond the readout signatures associated with charge and spin configurations of qubits, gate-sensing is sensitive to trapped charge in the potential landscape. Here, we report gate-sensing signals arising from tunnelling of electrons between puddles of trapped charge in a GaAs 2DEG. We examine these signals in a family of different devices with varying mobilities, and as a function of temperature and bias. Implications for qubit readout using the gate-sensing technique are discussed.

Voltage tunable plasmon propagation in dual gated bilayer graphene

NASA Astrophysics Data System (ADS)

Farzaneh, Seyed M.; Rakheja, Shaloo

2017-10-01

In this paper, we theoretically investigate plasmon propagation characteristics in AB and AA stacked bilayer graphene (BLG) in the presence of energy asymmetry due to an electrostatic field oriented perpendicularly to the plane of the graphene sheet. We first derive the optical conductivity of BLG using the Kubo formalism incorporating energy asymmetry and finite electron scattering. All results are obtained for room temperature (300 K) operation. By solving Maxwell's equations in a dual gate device setup, we obtain the wavevector of propagating plasmon modes in the transverse electric (TE) and transverse magnetic (TM) directions at terahertz frequencies. The plasmon wavevector allows us to compare the compression factor, propagation length, and the mode confinement of TE and TM plasmon modes in bilayer and monolayer graphene sheets and also to study the impact of material parameters on plasmon characteristics. Our results show that the energy asymmetry can be harnessed to increase the propagation length of TM plasmons in BLG. AA stacked BLG shows a larger increase in the propagation length than AB stacked BLG; conversely, it is very insensitive to the Fermi level variations. Additionally, the dual gate structure allows independent modulation of the energy asymmetry and the Fermi level in BLG, which is advantageous for reconfiguring plasmon characteristics post device fabrication.

Space charge effects on the current-voltage characteristics of gated field emitter arrays

NASA Astrophysics Data System (ADS)

Jensen, K. L.; Kodis, M. A.; Murphy, R. A.; Zaidman, E. G.

1997-07-01

Microfabricated field emitter arrays (FEAs) can provide the very high electron current densities required for rf amplifier applications, typically on the order of 100 A/cm2. Determining the dependence of emission current on gate voltage is important for the prediction of emitter performance for device applications. Field emitters use high applied fields to extract current, and therefore, unlike thermionic emitters, the current densities can exceed 103A/cm2 when averaged over an array. At such high current densities, space charge effects (i.e., the influence of charge between cathode and collector on emission) affect the emission process or initiate conditions which can lead to failure mechanisms for field emitters. A simple model of a field emitter will be used to calculate the one-dimensional space charge effects on the emission characteristics by examining two components: charge between the gate and anode, which leads to Child's law, and charge within the FEA unit cell, which gives rise to a field suppression effect which can exist for a single field emitter. The predictions of the analytical model are compared with recent experimental measurements designed to assess space charge effects and predict the onset of gate current. It is shown that negative convexity on a Fowler-Nordheim plot of Ianode(Vgate) data can be explained in terms of field depression at the emitter tip in addition to reflection of electrons by a virtual cathode created when the anode field is insufficient to extract all of the current; in particular, the effects present within the unit cell constitute a newly described effect.

Stabilization of the Activated hERG Channel Voltage Sensor by Depolarization Involves the S4-S5 Linker.

PubMed

Thouta, Samrat; Hull, Christina M; Shi, Yu Patrick; Sergeev, Valentine; Young, James; Cheng, Yen M; Claydon, Thomas W

2017-01-24

Slow deactivation of hERG channels is critical for preventing cardiac arrhythmia yet the mechanistic basis for the slow gating transition is unclear. Here, we characterized the temporal sequence of events leading to voltage sensor stabilization upon membrane depolarization. Progressive increase in step depolarization duration slowed voltage-sensor return in a biphasic manner (τ fast = 34 ms, τ slow  = 2.5 s). The faster phase of voltage-sensor return slowing correlated with the kinetics of pore opening. The slower component occurred over durations that exceeded channel activation and was consistent with voltage sensor relaxation. The S4-S5 linker mutation, G546L, impeded the faster phase of voltage sensor stabilization without attenuating the slower phase, suggesting that the S4-S5 linker is important for communications between the pore gate and the voltage sensor during deactivation. These data also demonstrate that the mechanisms of pore gate-opening-induced and relaxation-induced voltage-sensor stabilization are separable. Deletion of the distal N-terminus (Δ2-135) accelerated off-gating current, but did not influence the relative contribution of either mechanism of stabilization of the voltage sensor. Lastly, we characterized mode-shift behavior in hERG channels, which results from stabilization of activated channel states. The apparent mode-shift depended greatly on recording conditions. By measuring slow activation and deactivation at steady state we found the "true" mode-shift to be ∼15 mV. Interestingly, the "true" mode-shift of gating currents was ∼40 mV, much greater than that of the pore gate. This demonstrates that voltage sensor return is less energetically favorable upon repolarization than pore gate closure. We interpret this to indicate that stabilization of the activated voltage sensor limits the return of hERG channels to rest. The data suggest that this stabilization occurs as a result of reconfiguration of the pore gate upon opening by a mechanism that is influenced by the S4-S5 linker, and by a separable voltage-sensor intrinsic relaxation mechanism. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

Design and development progress of a LLRF control system for a 500 MHz superconducting cavity

NASA Astrophysics Data System (ADS)

Lee, Y. S.; Kim, H. W.; Song, H. S.; Lee, J. H.; Park, K. H.; Yu, I. H.; Chai, J. S.

2012-07-01

The LLRF (low-level radio-frequency) control system which regulates the amplitude and the phase of the accelerating voltage inside a RF cavity is essential to ensure the stable operation of charged particle accelerators. Recent advances in digital signal processors and data acquisition systems have allowed the LLRF control system to be implemented in digitally and have made it possible to meet the higher demands associated with the performance of LLRF control systems, such as stability, accuracy, etc. For this reason, many accelerator laboratories have completed or are completing the developments of digital LLRF control systems. The digital LLRF control system has advantages related with flexibility and fast reconfiguration. This paper describes the design of the FPGA (field programmable gate array) based LLRF control system and the status of development for this system. The proposed LLRF control system includes an analog front-end, a digital board (ADC (analog to digital converter), DAC (digital to analog converter), FPGA, etc.) and a RF & clock generation system. The control algorithms will be implemented by using the VHDL (VHSIC (very high speed integrated circuits) hardware description language), and the EPICS (experiment physics and industrial control system) will be ported to the host computer for the communication. In addition, the purpose of this system is to control a 500 MHz RF cavity, so the system will be applied to the superconducting cavity to be installed in the PLS storage ring, and its performance will be tested.

Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

PubMed Central

Dandass, Yoginder S; Burgess, Shane C; Lawrence, Mark; Bridges, Susan M

2008-01-01

Background This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA) devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM) is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences). Results This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM) resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation. PMID:18412963

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

CRionScan: A stand-alone real time controller designed to perform ion beam imaging, dose controlled irradiation and proton beam writing

NASA Astrophysics Data System (ADS)

Daudin, L.; Barberet, Ph.; Serani, L.; Moretto, Ph.

2013-07-01

High resolution ion microbeams, usually used to perform elemental mapping, low dose targeted irradiation or ion beam lithography needs a very flexible beam control system. For this purpose, we have developed a dedicated system (called “CRionScan”), on the AIFIRA facility (Applications Interdisciplinaires des Faisceaux d'Ions en Région Aquitaine). It consists of a stand-alone real-time scanning and imaging instrument based on a Compact Reconfigurable Input/Output (Compact RIO) device from National Instruments™. It is based on a real-time controller, a Field Programmable Gate Array (FPGA), input/output modules and Ethernet connectivity. We have implemented a fast and deterministic beam scanning system interfaced with our commercial data acquisition system without any hardware development. CRionScan is built under LabVIEW™ and has been used on AIFIRA's nanobeam line since 2009 (Barberet et al., 2009, 2011) [1,2]. A Graphical User Interface (GUI) embedded in the Compact RIO as a web page is used to control the scanning parameters. In addition, a fast electrostatic beam blanking trigger has been included in the FPGA and high speed counters (15 MHz) have been implemented to perform dose controlled irradiation and on-line images on the GUI. Analog to Digital converters are used for the beam current measurement and in the near future for secondary electrons imaging. Other functionalities have been integrated in this controller like LED lighting using Pulse Width Modulation and a “NIM Wilkinson ADC” data acquisition.

High-Speed On-Board Data Processing for Science Instruments

NASA Technical Reports Server (NTRS)

Beyon, Jeffrey Y.; Ng, Tak-Kwong; Lin, Bing; Hu, Yongxiang; Harrison, Wallace

2014-01-01

A new development of on-board data processing platform has been in progress at NASA Langley Research Center since April, 2012, and the overall review of such work is presented in this paper. The project is called High-Speed On-Board Data Processing for Science Instruments (HOPS) and focuses on a high-speed scalable data processing platform for three particular National Research Council's Decadal Survey missions such as Active Sensing of CO2 Emissions over Nights, Days, and Seasons (ASCENDS), Aerosol-Cloud-Ecosystems (ACE), and Doppler Aerosol Wind Lidar (DAWN) 3-D Winds. HOPS utilizes advanced general purpose computing with Field Programmable Gate Array (FPGA) based algorithm implementation techniques. The significance of HOPS is to enable high speed on-board data processing for current and future science missions with its reconfigurable and scalable data processing platform. A single HOPS processing board is expected to provide approximately 66 times faster data processing speed for ASCENDS, more than 70% reduction in both power and weight, and about two orders of cost reduction compared to the state-of-the-art (SOA) on-board data processing system. Such benchmark predictions are based on the data when HOPS was originally proposed in August, 2011. The details of these improvement measures are also presented. The two facets of HOPS development are identifying the most computationally intensive algorithm segments of each mission and implementing them in a FPGA-based data processing board. A general introduction of such facets is also the purpose of this paper.

Evaluation of the FIR Example using Xilinx Vivado High-Level Synthesis Compiler

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Zheming; Finkel, Hal; Yoshii, Kazutomo

Compared to central processing units (CPUs) and graphics processing units (GPUs), field programmable gate arrays (FPGAs) have major advantages in reconfigurability and performance achieved per watt. This development flow has been augmented with high-level synthesis (HLS) flow that can convert programs written in a high-level programming language to Hardware Description Language (HDL). Using high-level programming languages such as C, C++, and OpenCL for FPGA-based development could allow software developers, who have little FPGA knowledge, to take advantage of the FPGA-based application acceleration. This improves developer productivity and makes the FPGA-based acceleration accessible to hardware and software developers. Xilinx Vivado HLSmore » compiler is a high-level synthesis tool that enables C, C++ and System C specification to be directly targeted into Xilinx FPGAs without the need to create RTL manually. The white paper [1] published recently by Xilinx uses a finite impulse response (FIR) example to demonstrate the variable-precision features in the Vivado HLS compiler and the resource and power benefits of converting floating point to fixed point for a design. To get a better understanding of variable-precision features in terms of resource usage and performance, this report presents the experimental results of evaluating the FIR example using Vivado HLS 2017.1 and a Kintex Ultrascale FPGA. In addition, we evaluated the half-precision floating-point data type against the double-precision and single-precision data type and present the detailed results.« less

Adaptive lenticular microlens array based on voltage-induced waves at the surface of polyvinyl chloride/dibutyl phthalate gels.

PubMed

Xu, Miao; Jin, Boya; He, Rui; Ren, Hongwen

2016-04-18

We report a new approach to preparing a lenticular microlens array (LMA) using polyvinyl chloride (PVC)/dibutyl phthalate (DBP) gels. The PVD/DBP gels coated on a glass substrate form a membrane. With the aid of electrostatic repulsive force, the surface of the membrane can be reconfigured with sinusoidal waves by a DC voltage. The membrane with wavy surface functions as a LMA. By switching over the anode and cathode, the convex shape of each lenticular microlens in the array can be converted to the concave shape. Therefore, the LMA can present a large dynamic range. The response time is relatively fast and the driving voltage is low. With the advantages of compact structure, optical isotropy, and good mechanical stability, our LMA has potential applications in imaging, information processing, biometrics, and displays.

Functional metasurfaces based on metallic and dielectric subwavelength slits and stripes array

NASA Astrophysics Data System (ADS)

Guo, Yinghui; Pu, Mingbo; Li, Xiong; Ma, Xiaoliang; Gao, Ping; Wang, Yanqin; Luo, Xiangang

2018-04-01

Starting with the early works of extraordinary optical transmission and extraordinary Young’s interference, researchers have been fascinated by the unusual optical properties displayed by metallic holes/slits and subsequently found similar abnormities in dielectric counterparts. Benefiting from the shrinking wavelength of surface plasmon polaritons excited in metallic slits and high refractive index of dielectric stripes, one can realize local phase modulation and approach desired dispersion by engineering the geometries of a slits and stripes array. In this review, we review recent developments in functional metasurfaces composed of various metallic and dielectric subwavelength slits and stripes arrays, with special emphasis on achromatic, ultra-broadband, quasi-continuous, multifunctional and reconfigurable metasurfaces. Particular attention is paid to provide insight into the design strategies for these devices. Finally, we give an outlook of the development in this fascinating area.

A novel reconfigurable electromagnetically induced transparency based on S-PINs

NASA Astrophysics Data System (ADS)

Xue, Feng; Liu, Shao-Bin; Zhang, Hai-Feng; Wen, Yong-Diao; Kong, Xiang-Kun; Li, Hai-Ming

2018-02-01

In this paper, a tunable electromagnetically induced transparency (EIT) based on S-PINs is theoretically analyzed. Unit cell of the structure consists of a cutwire (CW), split ring resonator (SRR), and solid state plasma (SS plasma) patches which are composed of S-PIN array. The destructive interference between the CW and SRR results in a narrowband transparency window accompanied with strong phase dispersion. The proposed design can obtain a tunable EIT with different frequencies range from 12.8 GHz to 16.5 GHz in a simple method by switching these S-PINs on or off selectively. The related parameters of the S-PIN such as the size, carrier concentration, and volt-ampere characteristics have been studied theoretically. The interaction and coupling between two resonators are investigated in detail by the analysis of the current distribution and E-field strength as well. The research results provide an effective way to realize reconfigurable compact slow-light devices.

Expandable and reconfigurable instrument node arrays

NASA Technical Reports Server (NTRS)

Hilliard, Lawrence M. (Inventor); Deshpande, Manohar (Inventor)

2012-01-01

An expandable and reconfigurable instrument node includes a feature detection means and a data processing portion in communication with the feature detection means, the data processing portion configured and disposed to process feature information. The instrument node further includes a phase locked loop (PLL) oscillator in communication with the data processing portion, the PLL oscillator configured and disposed to provide PLL information to the processing portion. The instrument node further includes a single tone transceiver and a pulse transceiver in communication with the PLL oscillator, the single tone transceiver configured and disposed to transmit or receive a single tone for phase correction of the PLL oscillator and the pulse transceiver configured and disposed to transmit and receive signals for phase correction of the PLL oscillator. The instrument node further includes a global positioning (GPA) receiver in communication with the processing portion, the GPS receiver configured and disposed to establish a global position of the instrument node.

Multiple-mode reconfigurable electro-optic switching network for optical fiber sensor array

NASA Technical Reports Server (NTRS)

Chen, Ray T.; Wang, Michael R.; Jannson, Tomasz; Baumbick, Robert

1991-01-01

This paper reports the first switching network compatible with multimode fibers. A one-to-many cascaded reconfigurable interconnection was built. A thin glass substrate was used as the guiding medium which provides not only higher coupling efficiency from multimode fiber to waveguide but also better tolerance of phase-matching conditions. Involvement of a total-internal-reflection hologram and multimode waveguide eliminates interface problems between fibers and waveguides. The DCG polymer graft has proven to be reliable from -180 C to +200 C. Survivability of such an electrooptic system in harsh environments is further ensured. LiNbO3 was chosen as the E-O material because of its stability at high temperatures (phase-transition temperature of more than 1000 C) and maturity of E-O device technology. Further theoretical calculation was conducted to provide the optimal interaction length and device capacitance.

Prototype Focal-Plane-Array Optoelectronic Image Processor

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Shaw, Timothy; Yu, Jeffrey

1995-01-01

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

DBSAR's First Multimode Flight Campaign

NASA Technical Reports Server (NTRS)

Rincon, Rafael F.; Vega, Manuel; Buenfil, Manuel; Geist, Alessandro; Hilliard, Lawrence; Racette, Paul

2010-01-01

The Digital Beamforming SAR (DBSAR) is an airborne imaging radar system that combines phased array technology, reconfigurable on-board processing and waveform generation, and advances in signal processing to enable techniques not possible with conventional SARs. The system exploits the versatility inherently in phased-array technology with a state-of-the-art data acquisition and real-time processor in order to implement multi-mode measurement techniques in a single radar system. Operational modes include scatterometry over multiple antenna beams, Synthetic Aperture Radar (SAR) over several antenna beams, or Altimetry. The radar was flight tested in October 2008 on board of the NASA P3 aircraft over the Delmarva Peninsula, MD. The results from the DBSAR system performance is presented.

Electrical design for origami solar panels and a small spacecraft test mission

NASA Astrophysics Data System (ADS)

Drewelow, James; Straub, Jeremy

2017-05-01

Efficient power generation is crucial to the design of spacecraft. Mass, volume, and other limitations prevent the use of traditional spacecraft support structures from being suitable for the size of solar array required for some missions. Folding solar panel / panel array systems, however, present a number of design challenges. This paper considers the electrical design of an origami system. Specifically, it considers how to provide low impedance, durable channels for the generated power and the electrical aspects of the deployment system and procedure. The ability to dynamically reconfigure the electrical configuration of the solar cells is also discussed. Finally, a small satellite test mission to demonstrate the technology is proposed, before concluding.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A 2D Material based Gate Tunable Memristive Device for Emulating Modulatory Input-dependent Hetero-synaptic Plasticity.

NASA Astrophysics Data System (ADS)

Yan, Xiaodong; Tian, He; Xie, Yujun; Kostelec, Andrew; Zhao, Huan; Cha, Judy J.; Tice, Jesse; Wang, Han

Modulatory input-dependent plasticity is a well-known type of hetero-synaptic response where the release of neuromodulators can alter the efficacy of neurotransmission in a nearby chemical synapse. Solid-state devices that can mimic such phenomenon are desirable for enhancing the functionality and reconfigurability of neuromorphic electronics. In this work, we demonstrated a tunable artificial synaptic device concept based on the properties of graphene and tin oxide that can mimic the modulatory input-dependent plasticity. By using graphene as the contact electrode, a third electrode terminal can be used to modulate the conductive filament formation in the vertical tin oxide based resistive memory device. The resulting synaptic characteristics of this device, in terms of the profile of synaptic weight change and the spike-timing-dependent-plasticity, is tunable with the bias at the modulating terminal. Furthermore, the synaptic response can be reconfigured between excitatory and inhibitory modes by this modulating bias. The operation mechanism of the device is studied with combined experimental and theoretical analysis. The device is attractive for application in neuromorphic electronics. This work is supported by ARO and NG-ION2 at USC.

Reconfiguration Schemes for Fault-Tolerant Processor Arrays

DTIC Science & Technology

1992-10-15

partially notion of linear schedule are easily related to similar ordered subset of a multidimensional integer lattice models and concepts used in [11-[131...and several other (called indec set). The points of this lattice correspond works. to (i.e.. are the indices of) computations, and the partial There are...These data dependencies are represented as vectors that of all computations of the algorithm is to be minimized. connect points of the lattice . If a

Reconfigurable RF Systems Using Commercially Available Digital Capacitor Arrays

DTIC Science & Technology

2013-03-01

for changing antenna loading. Note that for the receiver circuitry, the path through the FEM is reversed and the wideband RF engine is given...Network A tunable impedance-matching network is commonly used to match variable antenna impedance to the transmitter output or receiver input [1...2]. There are multiple utilities for this device. In one, the so-called static mode, the antenna can be matched to the rest of the system before

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

PubMed Central

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-01-01

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s. PMID:26950128

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System.

PubMed

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-03-02

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

Field-programmable gate array-controlled sweep velocity-locked laser pulse generator

NASA Astrophysics Data System (ADS)

Chen, Zhen; Hefferman, Gerald; Wei, Tao

2017-05-01

A field-programmable gate array (FPGA)-controlled sweep velocity-locked laser pulse generator (SV-LLPG) design based on an all-digital phase-locked loop (ADPLL) is proposed. A distributed feedback laser with modulated injection current was used as a swept-frequency laser source. An open-loop predistortion modulation waveform was calibrated using a feedback iteration method to initially improve frequency sweep linearity. An ADPLL control system was then implemented using an FPGA to lock the output of a Mach-Zehnder interferometer that was directly proportional to laser sweep velocity to an on-board system clock. Using this system, linearly chirped laser pulses with a sweep bandwidth of 111.16 GHz were demonstrated. Further testing evaluating the sensing utility of the system was conducted. In this test, the SV-LLPG served as the swept laser source of an optical frequency-domain reflectometry system used to interrogate a subterahertz range fiber structure (sub-THz-FS) array. A static strain test was then conducted and linear sensor results were observed.

Multiple Quantum Phase Transitions in a two-dimensional superconductor

NASA Astrophysics Data System (ADS)

Bergeal, Nicolas; Biscaras, J.; Hurand, S.; Feuillet-Palma, C.; Lesueur, J.; Budhani, R. C.; Rastogi, A.; Caprara, S.; Grilli, M.

2013-03-01

We studied the magnetic field driven Quantum Phase Transition (QPT) in electrostatically gated superconducting LaTiO3/SrTiO3 interfaces. Through finite size scaling analysis, we showed that it belongs to the (2 +1)D XY model universality class. The system can be described as a disordered array of superconducting islands coupled by a two dimensional electron gas (2DEG). Depending on the 2DEG conductance tuned by the gate voltage, the QPT is single (corresponding to the long range phase coherence in the whole array) or double (one related to local phase coherence, the other one to the array). By retrieving the coherence length critical exponent ν, we showed that the QPT can be ``clean'' or ``dirty'' according to the Harris criteria, depending on whether the phase coherence length is smaller or larger than the island size. The overall behaviour is well described by a model of coupled superconducting puddles in the framework of the fermionic scenario of 2D superconducting QPT.

A preliminary study of molecular dynamics on reconfigurable computers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wolinski, C.; Trouw, F. R.; Gokhale, M.

2003-01-01

In this paper we investigate the performance of platform FPGAs on a compute-intensive, floating-point-intensive supercomputing application, Molecular Dynamics (MD). MD is a popular simulation technique to track interacting particles through time by integrating their equations of motion. One part of the MD algorithm was implemented using the Fabric Generator (FG)[l I ] and mapped onto several reconfigurable logic arrays. FG is a Java-based toolset that greatly accelerates construction of the fabrics from an abstract technology independent representation. Our experiments used technology-independent IEEE 32-bit floating point operators so that the design could be easily re-targeted. Experiments were performed using both non-pipelinedmore » and pipelined floating point modules. We present results for the Altera Excalibur ARM System on a Programmable Chip (SoPC), the Altera Strath EPlS80, and the Xilinx Virtex-N Pro 2VP.50. The best results obtained were 5.69 GFlops at 8OMHz(Altera Strath EPlS80), and 4.47 GFlops at 82 MHz (Xilinx Virtex-II Pro 2VF50). Assuming a lOWpower budget, these results compare very favorably to a 4Gjlop/40Wprocessing/power rate for a modern Pentium, suggesting that reconfigurable logic can achieve high performance at low power on jloating-point-intensivea pplications.« less

A switchable magnetic low-index metamaterial for use in a dynamically reconfigurable beam-scanning lens antenna with a single feed

NASA Astrophysics Data System (ADS)

Turpin, Jeremiah Paul

Metamaterials and Transformation Optics (TO) have been used to design and implement many novel electromagnetic devices that can achieve effects not possible using conventional materials. Compact high-gain antennas are one of the more popular and successful emerging applications for the new TO and metamaterial design approaches. This dissertation details an extension of uniaxial near-zero-index metamaterial lenses through the incorporation of a tunable or reconfigurable metamaterial as a replacement for the static metamaterial of the original antenna. A design is presented for a beam-scanning TO lens that allows an arbitrary number of beams at controlled magnitudes to be dynamically synthesized from a single omnidirectional source, unlike the equivalent antenna constructed using an array. A cylindrical slab of zero-index magnetic metamaterial controls the radiation pattern by altering the effective shape of the lens through switching of selected regions 'off' to emulate free-space conditions. A design for a switchable metamaterial is presented that allows for digital control over its bulk properties, from near-zero-index to near-free-space at the targeted operational frequency. Extensive modeling and simulations were performed for the design of the lens and metamaterial and during the analysis of measurement results. Initial prototypes of the tunable metamaterial were fabricated and characterized to confirm the original measurements, and the design updated to incorporate the measured data. These measurements were performed using custom test fixtures manufactured specifically for this project. Finally, a simplified prototype lens was manufactured and characterized in an anechoic as a proof-of-concept for the design. This dissertation presents the lens and metamaterial specifications, as well as the design process and considerations that were determined for practical tunable and reconfigurable metamaterials. Although the focus is on the particular example of the beam-scanning reconfigurable antenna, the analysis and modeling methods presented here are applicable to any reconfigurable metamaterial application.

Mechanical design of SST-GATE, a dual-mirror telescope for the Cherenkov Telescope Array

NASA Astrophysics Data System (ADS)

Dournaux, Jean-Laurent; Huet, Jean-Michel; Amans, Jean-Philippe; Dumas, Delphine; Laporte, Philippe; Sol, Hélène; Blake, Simon

2014-07-01

The Cherenkov Telescope Array (CTA) project aims to create the next generation Very High Energy (VHE) gamma-ray telescope array. It will be devoted to the observation of gamma rays over a wide band of energy, from a few tens of GeV to more than 100 TeV. Two sites are foreseen to view the whole sky where about 100 telescopes, composed of three different classes, related to the specific energy region to be investigated, will be installed. Among these, the Small Size class of Telescopes, SSTs, are devoted to the highest energy region, to beyond 100 TeV. Due to the large number of SSTs, their unit cost is an important parameter. At the Observatoire de Paris, we have designed a prototype of a Small Size Telescope named SST-GATE, based on the dual-mirror Schwarzschild-Couder optical formula, which has never before been implemented in the design of a telescope. Over the last two years, we developed a mechanical design for SST-GATE from the optical and preliminary mechanical designs made by the University of Durham. The integration of this telescope is currently in progress. Since the early stages of mechanical design of SST-GATE, finite element method has been used employing shape and topology optimization techniques to help design several elements of the telescope. This allowed optimization of the mechanical stiffness/mass ratio, leading to a lightweight and less expensive mechanical structure. These techniques and the resulting mechanical design are detailed in this paper. We will also describe the finite element analyses carried out to calculate the mechanical deformations and the stresses in the structure under observing and survival conditions.

Demonstration of universal parametric entangling gates on a multi-qubit lattice

PubMed Central

Reagor, Matthew; Osborn, Christopher B.; Tezak, Nikolas; Staley, Alexa; Prawiroatmodjo, Guenevere; Scheer, Michael; Alidoust, Nasser; Sete, Eyob A.; Didier, Nicolas; da Silva, Marcus P.; Acala, Ezer; Angeles, Joel; Bestwick, Andrew; Block, Maxwell; Bloom, Benjamin; Bradley, Adam; Bui, Catvu; Caldwell, Shane; Capelluto, Lauren; Chilcott, Rick; Cordova, Jeff; Crossman, Genya; Curtis, Michael; Deshpande, Saniya; El Bouayadi, Tristan; Girshovich, Daniel; Hong, Sabrina; Hudson, Alex; Karalekas, Peter; Kuang, Kat; Lenihan, Michael; Manenti, Riccardo; Manning, Thomas; Marshall, Jayss; Mohan, Yuvraj; O’Brien, William; Otterbach, Johannes; Papageorge, Alexander; Paquette, Jean-Philip; Pelstring, Michael; Polloreno, Anthony; Rawat, Vijay; Ryan, Colm A.; Renzas, Russ; Rubin, Nick; Russel, Damon; Rust, Michael; Scarabelli, Diego; Selvanayagam, Michael; Sinclair, Rodney; Smith, Robert; Suska, Mark; To, Ting-Wai; Vahidpour, Mehrnoosh; Vodrahalli, Nagesh; Whyland, Tyler; Yadav, Kamal; Zeng, William; Rigetti, Chad T.

2018-01-01

We show that parametric coupling techniques can be used to generate selective entangling interactions for multi-qubit processors. By inducing coherent population exchange between adjacent qubits under frequency modulation, we implement a universal gate set for a linear array of four superconducting qubits. An average process fidelity of ℱ = 93% is estimated for three two-qubit gates via quantum process tomography. We establish the suitability of these techniques for computation by preparing a four-qubit maximally entangled state and comparing the estimated state fidelity with the expected performance of the individual entangling gates. In addition, we prepare an eight-qubit register in all possible bitstring permutations and monitor the fidelity of a two-qubit gate across one pair of these qubits. Across all these permutations, an average fidelity of ℱ = 91.6 ± 2.6% is observed. These results thus offer a path to a scalable architecture with high selectivity and low cross-talk. PMID:29423443

Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

2012-02-01

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the Vth distribution with interference and disturbance problems and Vth shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

Quantum Algorithms to Simulate Many-Body Physics of Correlated Fermions

NASA Astrophysics Data System (ADS)

Jiang, Zhang; Sung, Kevin J.; Kechedzhi, Kostyantyn; Smelyanskiy, Vadim N.; Boixo, Sergio

2018-04-01

Simulating strongly correlated fermionic systems is notoriously hard on classical computers. An alternative approach, as proposed by Feynman, is to use a quantum computer. We discuss simulating strongly correlated fermionic systems using near-term quantum devices. We focus specifically on two-dimensional (2D) or linear geometry with nearest-neighbor qubit-qubit couplings, typical for superconducting transmon qubit arrays. We improve an existing algorithm to prepare an arbitrary Slater determinant by exploiting a unitary symmetry. We also present a quantum algorithm to prepare an arbitrary fermionic Gaussian state with O (N2) gates and O (N ) circuit depth. Both algorithms are optimal in the sense that the numbers of parameters in the quantum circuits are equal to those describing the quantum states. Furthermore, we propose an algorithm to implement the 2D fermionic Fourier transformation on a 2D qubit array with only O (N1.5) gates and O (√{N }) circuit depth, which is the minimum depth required for quantum information to travel across the qubit array. We also present methods to simulate each time step in the evolution of the 2D Fermi-Hubbard model—again on a 2D qubit array—with O (N ) gates and O (√{N }) circuit depth. Finally, we discuss how these algorithms can be used to determine the ground-state properties and phase diagrams of strongly correlated quantum systems using the Hubbard model as an example.

Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

NASA Astrophysics Data System (ADS)

Yang, Chen; Liu, LeiBo; Yin, ShouYi; Wei, ShaoJun

2014-12-01

The computational capability of a coarse-grained reconfigurable array (CGRA) can be significantly restrained due to data and context memory bandwidth bottlenecks. Traditionally, two methods have been used to resolve this problem. One method loads the context into the CGRA at run time. This method occupies very small on-chip memory but induces very large latency, which leads to low computational efficiency. The other method adopts a multi-context structure. This method loads the context into the on-chip context memory at the boot phase. Broadcasting the pointer of a set of contexts changes the hardware configuration on a cycle-by-cycle basis. The size of the context memory induces a large area overhead in multi-context structures, which results in major restrictions on application complexity. This paper proposes a Predictable Context Cache (PCC) architecture to address the above context issues by buffering the context inside a CGRA. In this architecture, context is dynamically transferred into the CGRA. Utilizing a PCC significantly reduces the on-chip context memory and the complexity of the applications running on the CGRA is no longer restricted by the size of the on-chip context memory. Data preloading is the most frequently used approach to hide input data latency and speed up the data transmission process for the data bandwidth issue. Rather than fundamentally reducing the amount of input data, the transferred data and computations are processed in parallel. However, the data preloading method cannot work efficiently because data transmission becomes the critical path as the reconfigurable array scale increases. This paper also presents a Hierarchical Data Memory (HDM) architecture as a solution to the efficiency problem. In this architecture, high internal bandwidth is provided to buffer both reused input data and intermediate data. The HDM architecture relieves the external memory from the data transfer burden so that the performance is significantly improved. As a result of using PCC and HDM, experiments running mainstream video decoding programs achieved performance improvements of 13.57%-19.48% when there was a reasonable memory size. Therefore, 1080p@35.7fps for H.264 high profile video decoding can be achieved on PCC and HDM architecture when utilizing a 200 MHz working frequency. Further, the size of the on-chip context memory no longer restricted complex applications, which were efficiently executed on the PCC and HDM architecture.

Development of a Crosstalk Suppression Algorithm for KID Readout

NASA Astrophysics Data System (ADS)

Lee, Kyungmin; Ishitsuka, H.; Oguri, S.; Suzuki, J.; Tajima, O.; Tomita, N.; Won, Eunil; Yoshida, M.

2018-06-01

The GroundBIRD telescope aims to detect B-mode polarization of the cosmic microwave background radiation using the kinetic inductance detector array as a polarimeter. For the readout of the signal from detector array, we have developed a frequency division multiplexing readout system based on a digital down converter method. These techniques in general have the leakage problems caused by the crosstalks. The window function was applied in the field programmable gate arrays to mitigate the effect of these problems and tested it in algorithm level.

Nonvolatile programmable neural network synaptic array

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1994-01-01

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Programmable computing with a single magnetoresistive element

NASA Astrophysics Data System (ADS)

Ney, A.; Pampuch, C.; Koch, R.; Ploog, K. H.

2003-10-01

The development of transistor-based integrated circuits for modern computing is a story of great success. However, the proved concept for enhancing computational power by continuous miniaturization is approaching its fundamental limits. Alternative approaches consider logic elements that are reconfigurable at run-time to overcome the rigid architecture of the present hardware systems. Implementation of parallel algorithms on such `chameleon' processors has the potential to yield a dramatic increase of computational speed, competitive with that of supercomputers. Owing to their functional flexibility, `chameleon' processors can be readily optimized with respect to any computer application. In conventional microprocessors, information must be transferred to a memory to prevent it from getting lost, because electrically processed information is volatile. Therefore the computational performance can be improved if the logic gate is additionally capable of storing the output. Here we describe a simple hardware concept for a programmable logic element that is based on a single magnetic random access memory (MRAM) cell. It combines the inherent advantage of a non-volatile output with flexible functionality which can be selected at run-time to operate as an AND, OR, NAND or NOR gate.