Maximizing the value of gate capacitance in field-effect devices using an organic interface layer

NASA Astrophysics Data System (ADS)

Kwok, H. L.

2015-12-01

Past research has confirmed the existence of negative capacitance in organics such as tris (8-Hydroxyquinoline) Aluminum (Alq3). This work explored using such an organic interface layer to enhance the channel voltage in the field-effect transistor (FET) thereby lowering the sub-threshold swing. In particular, if the values of the positive and negative gate capacitances are approximately equal, the composite negative capacitance will increase by orders of magnitude. One concern is the upper frequency limit (∼100 Hz) over which negative capacitance has been observed. Nonetheless, this frequency limit can be raised to kHz when the organic layer is subjected to a DC bias.

Novel attributes of AlGaN/AlN/GaN/SiC HEMTs with the multiple indented channel

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Ghaffari, Majid

2015-11-01

In this paper, a high performance AlGaN/AlN/GaN/SiC High Electron Mobility Transistor (HEMT) with the multiple indented channel (MIC-HEMT) is proposed. The main focus of the proposed structure is based on reduction of the space around the gate, stop of the spread of the depletion region around the source-drain, and decrement of the thickness of the channel between the gate and drain. Therefore, the breakdown voltage increases, meanwhile the elimination of the gate depletion layer extension to source/drain decreases the gate-source and gate-drain capacitances. The optimized results reveal that the breakdown voltage and the drain saturation current increase about 178% and 46% compared with a conventional HEMT (C-HEMT), respectively. Therefore, the maximum output power density is improved by factor 4.1 in comparison with conventional one. Also, the cut-off frequency of 25.2 GHz and the maximum oscillation frequency of 92.1 GHz for the MIC-HEMT are obtained compared to 13 GHz and 43 GHz for that of the C-HEMT and the minimum figure noise decreased consequently of reducing the gate-drain and gate-source capacitances by about 42% and 40%, respectively. The proposed MIC-HEMT shows a maximum stable gain (MSG) exceeding 24.1 dB at 3.1 GHz which the greatest gain is yet reported for HEMTs, showing the potential of this device for high power RF applications.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Efficient Multi-Dimensional Simulation of Quantum Confinement Effects in Advanced MOS Devices

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Ancona, Mario G.; Rafferty, Conor S.; Yu, Zhiping

2000-01-01

We investigate the density-gradient (DG) transport model for efficient multi-dimensional simulation of quantum confinement effects in advanced MOS devices. The formulation of the DG model is described as a quantum correction ot the classical drift-diffusion model. Quantum confinement effects are shown to be significant in sub-100nm MOSFETs. In thin-oxide MOS capacitors, quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements for oxide thickness down to 2 nm. Significant quantum corrections also occur in the I-V characteristics of short-channel (30 to 100 nm) n-MOSFETs, with current drive reduced by up to 70%. This effect is shown to result from reduced inversion charge due to quantum confinement of electrons in the channel. Also, subthreshold slope is degraded by 15 to 20 mV/decade with the inclusion of quantum effects via the density-gradient model, and short channel effects (in particular, drain-induced barrier lowering) are noticeably increased.

A high-performance channel engineered charge-plasma-based MOSFET with high-κ spacer

NASA Astrophysics Data System (ADS)

Shan, Chan; Wang, Ying; Luo, Xin; Bao, Meng-tian; Yu, Cheng-hao; Cao, Fei

2017-12-01

In this paper, the performance of graded channel double-gate MOSFET (GC-DGFET) that utilizes the charge-plasma concept and a high-κ spacer is investigated through 2-D device simulations. The results demonstrate that GC-DGFET with high-κ spacer can effectively improve the ON-state driving current (ION) and reduce the OFF-leakage current (IOFF). We find that reduction of the initial energy barrier between the source and channel is the origin of this ION enhancement. The reason for the IOFF reduction is identified to be the extension of the effective channel length owing to the fringing field via high-κ spacers. Consequently, these devices offer enhanced performance by reducing the total gate-to-gate capacitance (Cgg) and decreasing the intrinsic delay (τ).

Exact CNOT gates with a single nonlocal rotation for quantum-dot qubits

NASA Astrophysics Data System (ADS)

Pal, Arijeet; Rashba, Emmanuel I.; Halperin, Bertrand I.

2015-09-01

We investigate capacitively-coupled exchange-only two-qubit quantum gates based on quantum dots. For exchange-only coded qubits electron spin S and its projection Sz are exact quantum numbers. Capacitive coupling between qubits, as distinct from interqubit exchange, preserves these quantum numbers. We prove, both analytically and numerically, that conservation of the spins of individual qubits has a dramatic effect on the performance of two-qubit gates. By varying the level splittings of individual qubits, Ja and Jb, and the interqubit coupling time, t , we can find an infinite number of triples (Ja,Jb,t ) for which the two-qubit entanglement, in combination with appropriate single-qubit rotations, can produce an exact cnot gate. This statement is true for practically arbitrary magnitude and form of capacitive interqubit coupling. Our findings promise a large decrease in the number of nonlocal (two-qubit) operations in quantum circuits.

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

PubMed

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

NASA Astrophysics Data System (ADS)

Oh, Himchan; Pi, Jae-Eun; Hwang, Chi-Sun; Kwon, Oh-Sang

2017-12-01

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

Impact of negative capacitance effect on Germanium Double Gate pFET for enhanced immunity to interface trap charges

NASA Astrophysics Data System (ADS)

Bansal, Monika; Kaur, Harsupreet

2018-05-01

In this work, a comprehensive drain current model has been developed for long channel Negative Capacitance Germanium Double Gate p-type Field Effect Transistor (NCGe-DG-pFET) by using 1-D Poisson's equation and Landau-Khalatnikov equation. The model takes into account interface trap charges and by using the derived model various parameters such as surface potential, gain, gate capacitance, subthreshold swing, drain current, transconductance, output conductance and Ion/Ioff ratio have been obtained and it is demonstrated that by incorporating ferroelectric material as gate insulator with Ge-channel, subthreshold swing values less than 60 mV/dec can be achieved along with improved gate controllability and current drivability. Further, to critically analyze the advantages offered by NCGe-DG-pFET, a detailed comparison has been done with Germanium Double Gate p-type Field Effect Transistor (Ge-DG-pFET) and it is shown that NCGe-DG-pFET exhibits high gain, enhanced transport efficiency in channel, very less or negligible degradation in device characteristics due to interface trap charges as compared to Ge-DG-pFET. The analytical results so obtained show good agreement with simulated results obtained from Silvaco ATLAS TCAD tool.

Improving the gate fidelity of capacitively coupled spin qubits

NASA Astrophysics Data System (ADS)

Wang, Xin; Barnes, Edwin

2015-03-01

Precise execution of quantum gates acting on two or multiple qubits is essential to quantum computation. For semiconductor spin qubits coupled via capacitive interaction, the best fidelity for a two-qubit gate demonstrated so far is around 70%, insufficient for fault-tolerant quantum computation. In this talk we present control protocols that may substantially improve the robustness of two-qubit gates against both nuclear noise and charge noise. Our pulse sequences incorporate simultaneous dynamical decoupling protocols and are simple enough for immediate experimental realization. Together with existing control protocols for single-qubit gates, our results constitute an important step toward scalable quantum computation using spin qubits. This work is done in collaboration with Sankar Das Sarma and supported by LPS-NSA-CMTC and IARPA-MQCO.

On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2 V operation

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-02-01

We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate stack thickness on the I on/I off ratio of DGNCFET. DGNCFET has wider design window for the gate stack where higher I on/I off ratio can be achieved than DG classical MOSFET. Under a process-induced constraint with sub-10 nm gate length (L g), FE:HfO2-based DGNCFET still has a design point for high I on/I off ratio. With an optimized gate stack thickness for sub-10 nm L g, FE:HfO2-based DGNCFET has 2.5× higher energy efficiency than DG classical MOSFET even at ultralow operation voltage of sub-0.2 V.

Low-voltage electric-double-layer paper transistors gated by microporous SiO2 processed at room temperature

NASA Astrophysics Data System (ADS)

Sun, Jia; Wan, Qing; Lu, Aixia; Jiang, Jie

2009-11-01

Battery drivable low-voltage SnO2-based paper thin-film transistors with a near-zero threshold voltage (Vth=0.06 V) gated by microporous SiO2 dielectric with electric-double-layer (EDL) effect are fabricated at room temperature. The operating voltage is found to be as low as 1.5 V due to the huge gate specific capacitance (1.34 μF/cm2 at 40 Hz) related to EDL formation. The subthreshold gate voltage swing and current on/off ratio is found to be 82 mV/decade and 2.0×105, respectively. The electron field-effect mobility is estimated to be 47.3 cm2/V s based on the measured gate specific capacitance at 40 Hz.

On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

NASA Astrophysics Data System (ADS)

Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

2018-02-01

In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

Electric double-layer capacitance between an ionic liquid and few-layer graphene.

PubMed

Uesugi, Eri; Goto, Hidenori; Eguchi, Ritsuko; Fujiwara, Akihiko; Kubozono, Yoshihiro

2013-01-01

Ionic-liquid gates have a high carrier density due to their atomically thin electric double layer (EDL) and extremely large geometrical capacitance Cg. However, a high carrier density in graphene has not been achieved even with ionic-liquid gates because the EDL capacitance CEDL between the ionic liquid and graphene involves the series connection of Cg and the quantum capacitance Cq, which is proportional to the density of states. We investigated the variables that determine CEDL at the molecular level by varying the number of graphene layers n and thereby optimising Cq. The CEDL value is governed by Cq at n < 4, and by Cg at n > 4. This transition with n indicates a composite nature for CEDL. Our finding clarifies a universal principle that determines capacitance on a microscopic scale, and provides nanotechnological perspectives on charge accumulation and energy storage using an ultimately thin capacitor.

Electric double-layer capacitance between an ionic liquid and few-layer graphene

PubMed Central

Uesugi, Eri; Goto, Hidenori; Eguchi, Ritsuko; Fujiwara, Akihiko; Kubozono, Yoshihiro

2013-01-01

Ionic-liquid gates have a high carrier density due to their atomically thin electric double layer (EDL) and extremely large geometrical capacitance Cg. However, a high carrier density in graphene has not been achieved even with ionic-liquid gates because the EDL capacitance CEDL between the ionic liquid and graphene involves the series connection of Cg and the quantum capacitance Cq, which is proportional to the density of states. We investigated the variables that determine CEDL at the molecular level by varying the number of graphene layers n and thereby optimising Cq. The CEDL value is governed by Cq at n < 4, and by Cg at n > 4. This transition with n indicates a composite nature for CEDL. Our finding clarifies a universal principle that determines capacitance on a microscopic scale, and provides nanotechnological perspectives on charge accumulation and energy storage using an ultimately thin capacitor. PMID:23549208

A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar behaviour

NASA Astrophysics Data System (ADS)

Yadav, Shivendra; Sharma, Dheeraj; Chandan, Bandi Venkata; Aslam, Mohd; Soni, Deepak; Sharma, Neeraj

2018-05-01

In this article, the impact of gate-underlap with hetero material (low band gap) has been investigated in terms of DC and Analog/RF parameters by proposed device named as hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET). Gate-underlap resolves the problem of ambipolarity, gate leakage current (Ig) and slightly improves the gate to drain capacitance, but DC performance is almost unaffected. Further, the use of low band gap material (Si0.5 Ge) in proposed device causes a drastic improvement in the DC as well as RF figures of merit. We have investigated the Si0.5 Ge as a suitable candidate among different low band gap materials. In addition, the sensitivity of gate-underlap in terms of gate to drain inversion and parasitic capacitances has been studied for HM-GUL-ED-TFET. Further, relatively it is observed that gate-underlap is a better way than drain-underlap in the proposed structure to improve Analog/RF performances without degrading the DC parameters of device. Additionally, hetero-junction alignment analysis has been done for fabrication feasibility.

Electrolyte gated TFT biosensors based on the Donnan's capacitance of anchored biomolecules

NASA Astrophysics Data System (ADS)

Manoli, Kyriaki; Palazzo, Gerardo; Macchia, Eleonora; Tiwari, Amber; Di Franco, Cinzia; Scamarcio, Gaetano; Favia, Pietro; Mallardi, Antonia; Torsi, Luisa

2017-08-01

Biodetection using electrolyte gated field effect transistors has been mainly correlated to charge modulated transduction. Therefore, such platforms are designed and studied for limited applications involving relatively small charged species and much care is taken in the operating conditions particularly pH and salt concentration (ionic strength). However, there are several reports suggesting that the device conductance can also be very sensitive towards variations in the capacitance coupling. Understanding the sensing mechanism is important for further exploitation of these promising sensors in broader range of applications. In this paper, we present a thorough and in depth study of a multilayer protein system coupled to an electrolyte gated transistor. It is demonstrated that detection associated to a binding event taking place at a distance of 30 nm far from the organic semiconductor-electrolyte interface is possible and the device conductance is dominated by Donnan's capacitance of anchored biomolecules.

Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications.

PubMed

Choi, Sungjin; Lee, Junhyuk; Kim, Donghyoun; Oh, Seulki; Song, Wangyu; Choi, Seonjun; Choi, Eunsuk; Lee, Seung-Beck

2011-12-01

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.

Low-voltage organic strain sensor on plastic using polymer/high- K inorganic hybrid gate dielectrics

NASA Astrophysics Data System (ADS)

Jung, Soyoun; Ji, Taeksoo; Varadan, Vijay K.

2007-12-01

In this paper, gate-induced pentacene semiconductor strain sensors based on hybrid-gate dielectrics using poly-vinylphenol (PVP) and high-K inorganic, Ta IIO 5 are fabricated on flexible substrates, polyethylene naphthalate (PEN). The Ta IIO 5 gate dielectric layer is combined with a thin PVP layer to obtain very smooth and hydrophobic surfaces which improve the molecular structures of pentacene films. The PVP-Ta IIO 5 hybrid-gate dielectric films exhibit a high dielectric capacitance and low leakage current. The sensors adopting thin film transistor (TFT)-like structures show a significantly reduced operating voltage (~6V), and good device characteristics with a field-effect mobility of 1.89 cm2/V•s, a threshold voltage of -0.5 V, and an on/off ratio of 10 3. The strain sensor, one of the practical applications in large-area organic electronics, was characterized with different bending radii of 50, 40, 30, and 20 mm. The sensor output signals were significantly improved with low-operating voltages.

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

NASA Astrophysics Data System (ADS)

Poorvasha, S.; Lakshmi, B.

2018-05-01

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (f t), maximum oscillation frequency (f max), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (I ON) of about 0.2 mA and less leakage current (I OFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (g m), higher f t and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher f max of 985 GHz is obtained for drain doping of 5 × 1017 cm‑3 because of the reduced gate-drain capacitance (C gd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of C gd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values. Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

Best-Practice Criteria for Practical Security of Self-Differencing Avalanche Photodiode Detectors in Quantum Key Distribution

NASA Astrophysics Data System (ADS)

Koehler-Sidki, A.; Dynes, J. F.; Lucamarini, M.; Roberts, G. L.; Sharpe, A. W.; Yuan, Z. L.; Shields, A. J.

2018-04-01

Fast-gated avalanche photodiodes (APDs) are the most commonly used single photon detectors for high-bit-rate quantum key distribution (QKD). Their robustness against external attacks is crucial to the overall security of a QKD system, or even an entire QKD network. We investigate the behavior of a gigahertz-gated, self-differencing (In,Ga)As APD under strong illumination, a tactic Eve often uses to bring detectors under her control. Our experiment and modeling reveal that the negative feedback by the photocurrent safeguards the detector from being blinded through reducing its avalanche probability and/or strengthening the capacitive response. Based on this finding, we propose a set of best-practice criteria for designing and operating fast-gated APD detectors to ensure their practical security in QKD.

Progress towards a microwave-based high-fidelity Toffoli gate with superconducting qubits

NASA Astrophysics Data System (ADS)

Rigetti, Chad; Chow, Jerry; Corcoles, Antonio; Rozen, Jim; Keefe, George; Rothwell, Mary Beth; Rohrs, Jack; Borstelmann, Mark; Divincenzo, David; Ketchen, Mark; Steffen, Matthias

2011-03-01

We describe recent progress at IBM towards a microwave-based implementation of the Toffoli gate using three capacitively shunted flux qubits dispersively coupled to a resonator. We discuss the device architecture and the microwave protocol, along with expected limits to gate fidelity and scaling.

Attofarad resolution capacitance-voltage measurement of nanometer scale field effect transistors utilizing ambient noise.

PubMed

Gokirmak, Ali; Inaltekin, Hazer; Tiwari, Sandip

2009-08-19

A high resolution capacitance-voltage (C-V) characterization technique, enabling direct measurement of electronic properties at the nanoscale in devices such as nanowire field effect transistors (FETs) through the use of random fluctuations, is described. The minimum noise level required for achieving sub-aF (10(-18) F) resolution, the leveraging of stochastic resonance, and the effect of higher levels of noise are illustrated through simulations. The non-linear DeltaC(gate-source/drain)-V(gate) response of FETs is utilized to determine the inversion layer capacitance (C(inv)) and carrier mobility. The technique is demonstrated by extracting the carrier concentration and effective electron mobility in a nanoscale Si FET with C(inv) = 60 aF.

Millimeter-Wave Voltage-Controlled Oscillators in 0.13-micrometer CMOS Technology

DTIC Science & Technology

2006-06-01

controlled oscillators. Varactor , transistor, and in- ductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between...quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 m result both good...millimeter wave, MOS varactor , quality factor, transmission line, voltage-controlled oscillator (VCO). I. INTRODUCTION WITH THE RAPID advance of high

Simulation of Ultra-Small MOSFETs Using a 2-D Quantum-Corrected Drift-Diffusion Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Rafferty, Conor S.; Yu, Zhiping; Dutton, Robert W.; Ancona, Mario G.; Saini, Subhash (Technical Monitor)

1998-01-01

We describe an electronic transport model and an implementation approach that respond to the challenges of device modeling for gigascale integration. We use the density-gradient (DG) transport model, which adds tunneling and quantum smoothing of carrier density profiles to the drift-diffusion model. We present the current implementation of the DG model in PROPHET, a partial differential equation solver developed by Lucent Technologies. This implementation approach permits rapid development and enhancement of models, as well as run-time modifications and model switching. We show that even in typical bulk transport devices such as P-N diodes and BJTs, DG quantum effects can significantly modify the I-V characteristics. Quantum effects are shown to be even more significant in small, surface transport devices, such as sub-0.1 micron MOSFETs. In thin-oxide MOS capacitors, we find that quantum effects may reduce gate capacitance by 25% or more. The inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements. Significant quantum corrections also occur in the I-V characteristics of short-channel MOSFETs due to the gate capacitance correction.

Crosstalk error correction through dynamical decoupling of single-qubit gates in capacitively coupled singlet-triplet semiconductor spin qubits

NASA Astrophysics Data System (ADS)

Buterakos, Donovan; Throckmorton, Robert E.; Das Sarma, S.

2018-01-01

In addition to magnetic field and electric charge noise adversely affecting spin-qubit operations, performing single-qubit gates on one of multiple coupled singlet-triplet qubits presents a new challenge: crosstalk, which is inevitable (and must be minimized) in any multiqubit quantum computing architecture. We develop a set of dynamically corrected pulse sequences that are designed to cancel the effects of both types of noise (i.e., field and charge) as well as crosstalk to leading order, and provide parameters for these corrected sequences for all 24 of the single-qubit Clifford gates. We then provide an estimate of the error as a function of the noise and capacitive coupling to compare the fidelity of our corrected gates to their uncorrected versions. Dynamical error correction protocols presented in this work are important for the next generation of singlet-triplet qubit devices where coupling among many qubits will become relevant.

125 GHz sine wave gating InGaAs/InP single-photon detector with a monolithically integrated readout circuit

NASA Astrophysics Data System (ADS)

Jiang, Wen-Hao; Liu, Jian-Hong; Liu, Yin; Jin, Ge; Zhang, Jun; Pan, Jian-Wei

2017-12-01

InGaAs/InP single-photon detectors (SPDs) are the key devices for applications requiring near-infrared single-photon detection. Gating mode is an effective approach to synchronous single-photon detection. Increasing gating frequency and reducing module size are important challenges for the design of such detector system. Here we present for the first time an InGaAs/InP SPD with 1.25 GHz sine wave gating using a monolithically integrated readout circuit (MIRC). The MIRC has a size of 15 mm * 15 mm and implements the miniaturization of avalanche extraction for high-frequency sine wave gating. In the MIRC, low-pass filters and a low-noise radio frequency amplifier are integrated based on the technique of low temperature co-fired ceramic, which can effectively reduce the parasitic capacitance and extract weak avalanche signals. We then characterize the InGaAs/InP SPD to verify the functionality and reliability of MIRC, and the SPD exhibits excellent performance with 27.5 % photon detection efficiency, 1.2 kcps dark count rate, and 9.1 % afterpulse probability at 223 K and 100 ns hold-off time. With this MIRC, one can further design miniaturized high-frequency SPD modules that are highly required for practical applications.

Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

NASA Astrophysics Data System (ADS)

Kumar, Narendra; Sutradhar, Moitri; Kumar, Jitendra; Panda, Siddhartha

2017-03-01

The deposition of the top gate dielectric in thin film transistor (TFT)-based dual-gate ion-sensitive field-effect transistors (DG ISFETs) is critical, and expected not to affect the bottom gate TFT characteristics, while providing a higher pH sensitive surface and efficient capacitive coupling between the gates. Amorphous Ta2O5, in addition to having good sensing properties, possesses a high dielectric constant of ˜25 making it well suited as the top gate dielectric in a DG ISFET by providing higher capacitive coupling (ratio of C top/C bottom) leading to higher amplification. To avoid damage of the a-IGZO channel reported to be caused by plasma exposure, deposition of Ta2O5 by e-beam evaporation followed by annealing was investigated in this work to obtain sensitivity over the Nernst limit. The deteriorated bottom gate TFT characteristics, indicated by an increase in the channel conductance, confirmed that plasma exposure is not the sole contributor to the changes. Oxygen vacancies at the Ta2O5/a-IGZO interface, which emerged during processing, increased the channel conductivity, became filled by optimum annealing in oxygen at 400 °C for 1 h, which was confirmed by an x-ray photoelectron spectroscopy depth profiling analysis. The obtained pH sensitivity of the TFT-based DG ISFET was 402 mV pH-1, which is about 6.8 times the Nernst limit (59 mV pH-1). The concept of capacitive coupling was also demonstrated by simulating an a-IGZO-based DG TFT structure. Here, the exposure of the top gate dielectric to the electrolyte without applying any top gate bias led to changes in the measured threshold voltage of the bottom gate TFT, and this obviated the requirement of a reference electrode needed in conventional ISFETs and other reported DG ISFETs. These devices, with high sensitivities and requiring low volumes (˜2 μl) of analyte solution, could be potential candidates for utilization as chemical sensors and biosensors.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

CMOS based capacitance to digital converter circuit for MEMS sensor

NASA Astrophysics Data System (ADS)

Rotake, D. R.; Darji, A. D.

2018-02-01

Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

NASA Astrophysics Data System (ADS)

Chen, Meng; Lei, Jiefeng; Huang, Shengxiang; Liao, Congwei; Deng, Lianwen

2017-06-01

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive {V}{TH} shift within 0.4 V and negative {V}{TH} shift within -1.2 V and it is robust and promising for high-resolution display. Project supported by the Science and Technology Project of Hunan Province, China (No. 2015JC3401)

Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

NASA Astrophysics Data System (ADS)

Sivaram, Gollamudi Sai; Chakraborty, Shramana; Das, Rahul; Dasgupta, Arpan; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme.

PubMed

Fan, Ching-Lin; Shang, Ming-Chi; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der

2014-08-11

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm²/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

PubMed Central

Fan, Ching-Lin; Shang, Ming-Chi; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der

2014-01-01

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm2/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased. PMID:28788159

Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction

NASA Astrophysics Data System (ADS)

Mohamad, B.; Leroux, C.; Reimbold, G.; Ghibaudo, G.

2018-01-01

For advanced gate stacks, effective work function (WFeff) and equivalent oxide thickness (EOT) are fundamental parameters for technology optimization. On FDSOI transistors, and contrary to the bulk technologies, while EOT can still be extracted at strong inversion from the typical gate-to-channel capacitance (Cgc), it is no longer the case for WFeff due to the disappearance of an observable flat band condition on capacitance characteristics. In this work, a new experimental method, the Cbg(VBG) characteristic, is proposed in order to extract the well flat band condition (VFB, W). This characteristic enables an accurate and direct evaluation of WFeff. Moreover, using the previous extraction of the gate oxide (tfox), and buried oxide (tbox) from typical capacitance characteristics (Cgc and Cbc), it allows the extraction of the channel thickness (tch). Furthermore, the measurement of the well flat band condition on Cbg(VBG) characteristics for two different Si and SiGe channel also proves the existence of a dipole at the SiGe/SiO2 interface.

Triangulating the source of tunneling resonances in a point contact with nanometer scale sensitivity

NASA Astrophysics Data System (ADS)

Bishop, N. C.; Boras Pinilla, C.; Stalford, H. L.; Young, R. W.; Ten Eyck, G. A.; Wendt, J. R.; Eng, K.; Lilly, M. P.; Carroll, M. S.

2011-03-01

We observe resonant tunneling in split gate point contacts defined in a double gate enhancement mode Si-MOS device structure. We determine the capacitances from the resonant feature to each of the conducting gates and the source/drain two dimensional electron gas regions. In our device, these capacitances provide information about the resonance location in three dimensions. Semi-classical electrostatic simulations of capacitance, already used to map quantum dot size and position [Stalford et al., IEEE Nanotechnology], identify a combination of location and confinement potential size that satisfy our experimental observations. The sensitivity of simulation to position and size allow us to triangulate possible locations of the resonant level with nanometer resolution. We discuss our results and how they may apply to resonant tunneling through a single donor. This work was supported by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under Contract DE-AC04-94AL85000.

Performance comparison between p–i–n and p–n junction tunneling field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-06-01

In this study, we investigated the direct-current (DC) and radio-frequency (RF) performances of p–i–n and p–n junction tunneling field-effect transistors (TFETs). Compared to the p–i–n junction TFET, the p–n junction TFET exhibited higher on-state current (I on) because the channel formation mechanism of the p–n junction TFET resulted in a narrower tunneling barrier and an expanded tunneling area. Further, the reduction of I on of the p–n junction TFET by the interface trap was smaller. Moreover, the p–n junction TFET exhibited lower gate-to-drain capacitance (C gd) because a depletion capacitance (C gd,dep) was formed by the depletion region under gate dielectric. Consequently, the p–n junction TFET achieved an improvement of cut-off frequency (f T) and intrinsic delay time (τ), which are related to the current performance and total gate capacitance (C gg). We confirmed the enhancement of device performances in terms of I on, f T, and τ by the conduction mechanism of the p–n junction TFET.

Fabrication and Analysis of a Selectively Contacted Dual Channel High Electron Mobility Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Khanna, Ravi

1992-01-01

A selectively contacted dual-channel high electron mobility transistor (SCD-CHEMT) has been designed, fabricated, and electrically characterized, in order to better understand the properties of two layers of two-dimensional electron gases (2DEGs) confined within a quantum well. The 2DEGs are placed under a Schottky barrier control gate which modulates their sheet charge densities, and by use of auxiliary Schottky barrier gates and two levels of ohmic contacts, electrical contacts to the individual channels in which each 2DEG resides is achieved. The design of the dual channel FET structure, and its practical realization by recourse to process development and fabrication are described, as are the techniques, results, and interpretations of electrical characterizations used to analyze the completed device. Critical fabrication procedures involving photolithography, etching, deposition, shallow and deep ohmic contact formation, and gate formation are developed, and a simple technique to reduce gate leakage by photo-oxidation is demonstrated. Analysis of the completed device is performed using one-dimensional band diagram simulations, magnetotransport and electrical measurements. Magnetotransport studies establish the existence of two 2DEGs within the quantum well at 4K. Drain current vs. drain voltage, and transconductance vs. gate voltage characteristics at room temperature confirm the presence of two 2DEGs and show that current flow between them occurs easily at room temperature. Carrier electron mobility profiles are taken of the 2DEGs and show that the lower 2DEG has a mobility comparable to that of a 2DEG formed at a normal interface, indicating that the "inverted interface problem" has been overcome. Capacitance vs. gate voltage measurements are taken, which are consistent with a simple device model consisting of gate depletion and interelectrode parasitic capacitances. It is concluded from the analysis that the dual channel system resides in three basic states: (1) Both channels are occupied by 2DEGs or (2) The upper channel is depleted, or (3) Both channels depleted. Finally, increase in isolation between the two 2DEGs is dramatically demonstrated at 77K by the drain current vs. drain voltage, and transconductance vs. gate voltage characteristics.

Self-Aligned, Extremely High Frequency III-V Metal-Oxide-Semiconductor Field-Effect Transistors on Rigid and Flexible Substrates

DTIC Science & Technology

2012-06-29

resistances, respectively, and gd is the output conductance. The reduced parasitic capacitances and resistances provided by the self-aligned T-gate design ...Department of the Army position, policy or decision, unless so designated by other documentation. 12. DISTRIBUTION AVAILIBILITY STATEMENT Approved for...position, policy or decision, unless so designated by other documentation. Approved for public release; distribution is unlimited. ... 59654.5-MS-DRP Self

A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Raad, Bhagwan Ram; Sharma, Dheeraj

2016-12-01

In this paper, we focus on the improvement of figures of merit for charge plasma based tunnel field-effect transistor (TFET) in terms of ON-state current, threshold voltage, sub-threshold swing, ambipolar nature, and gate to drain capacitance which provides better channel controlling of the device with improved high frequency response at ultra-low supply voltages. Regarding this, we simultaneously employ work function engineering on the drain and gate electrode of the charge plasma TFET. The use of gate work function engineering modulates the barrier on the source/channel interface leads to improvement in the ON-state current, threshold voltage, and sub-threshold swing. Apart from this, for the first time use of work function engineering on the drain electrode increases the tunneling barrier for the flow of holes on the drain/channel interface, it results into suppression of ambipolar behavior. The lowering of gate to drain capacitance therefore enhanced high frequency parameters. Whereas, the presence of dual work functionality at the gate electrode and over the drain region improves the overall performance of the charge plasma based TFET.

Anomalous single-electron transfer in common-gate quadruple-dot single-electron devices with asymmetric junction capacitances

NASA Astrophysics Data System (ADS)

Imai, Shigeru; Ito, Masato

2018-06-01

In this paper, anomalous single-electron transfer in common-gate quadruple-dot turnstile devices with asymmetric junction capacitances is revealed. That is, the islands have the same total number of excess electrons at high and low gate voltages of the swing that transfers a single electron. In another situation, two electrons enter the islands from the source and two electrons leave the islands for the source and drain during a gate voltage swing cycle. First, stability diagrams of the turnstile devices are presented. Then, sequences of single-electron tunneling events by gate voltage swings are investigated, which demonstrate the above-mentioned anomalous single-electron transfer between the source and the drain. The anomalous single-electron transfer can be understood by regarding the four islands as “three virtual islands and a virtual source or drain electrode of a virtual triple-dot device”. The anomalous behaviors of the four islands are explained by the normal behavior of the virtual islands transferring a single electron and the behavior of the virtual electrode.

Combined electrical transport and capacitance spectroscopy of a MoS2-LiNbO3 field effect transistor

NASA Astrophysics Data System (ADS)

Michailow, Wladislaw; Schülein, Florian J. R.; Möller, Benjamin; Preciado, Edwin; Nguyen, Ariana E.; von Son, Gretel; Mann, John; Hörner, Andreas L.; Wixforth, Achim; Bartels, Ludwig; Krenner, Hubert J.

2017-01-01

We have measured both the current-voltage ( ISD - VGS ) and capacitance-voltage (C- VGS ) characteristics of a MoS2-LiNbO3 field effect transistor. From the measured capacitance, we calculate the electron surface density and show that its gate voltage dependence follows the theoretical prediction resulting from the two-dimensional free electron model. This model allows us to fit the measured ISD - VGS characteristics over the entire range of VGS . Combining this experimental result with the measured current-voltage characteristics, we determine the field effect mobility as a function of gate voltage. We show that for our device, this improved combined approach yields significantly smaller values (more than a factor of 4) of the electron mobility than the conventional analysis of the current-voltage characteristics only.

The effects of dielectric decrement and finite ion size on differential capacitance of electrolytically gated graphene

NASA Astrophysics Data System (ADS)

Daniels, Lindsey; Scott, Matthew; Mišković, Z. L.

2018-06-01

We analyze the effects of dielectric decrement and finite ion size in an aqueous electrolyte on the capacitance of a graphene electrode, and make comparisons with the effects of dielectric saturation combined with finite ion size. We first derive conditions for the cross-over from a camel-shaped to a bell-shaped capacitance of the diffuse layer. We show next that the total capacitance is dominated by a V-shaped quantum capacitance of graphene at low potentials. A broad peak develops in the total capacitance at high potentials, which is sensitive to the ion size with dielectric saturation, but is stable with dielectric decrement.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture

NASA Astrophysics Data System (ADS)

Das, Rahul; Chakraborty, Shramana; Dasgupta, Arpan; Dutta, Arka; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of high-k spacers. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE's), however, it significantly reduces the on current due to the increased channel resistance. To overcome these drawbacks, the use of high-k spacers is projected as one of the remedies. In this paper, the analog performance of the devices is studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/Id) and intrinsic gain (gmro). The RF performance is analyzed on the merits of intrinsic capacitance (Cgd, Cgs), resistance (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillation (fmax). The circuit performance of the devices are studied by implementing the device as the driver MOSFET in a Single Stage Common Source Amplifier. The Gain Bandwidth Product (GBW) has been analyzed from the frequency response of the circuit.

Floating gate transistors as biosensors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Frisbie, C. Daniel

2016-11-01

Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment.

PubMed

Porrazzo, Rossella; Luzio, Alessandro; Bellani, Sebastiano; Bonacchini, Giorgio Ernesto; Noh, Yong-Young; Kim, Yun-Hi; Lanzani, Guglielmo; Antognazza, Maria Rosa; Caironi, Mario

2017-01-31

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm -2 in full accumulation and a mobility-capacitance product of 7 × 10 -3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment

PubMed Central

2017-01-01

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm–2 in full accumulation and a mobility–capacitance product of 7 × 10–3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation. PMID:28180187

A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure

PubMed Central

Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go

2017-01-01

This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO2 interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e−rms, low dark current density of 56 pA/cm2 at −35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV. PMID:29295523

A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure.

PubMed

Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

2017-12-23

This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e - rms , low dark current density of 56 pA/cm² at -35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.

All-printed thin-film transistors from networks of liquid-exfoliated nanosheets

NASA Astrophysics Data System (ADS)

Kelly, Adam G.; Hallam, Toby; Backes, Claudia; Harvey, Andrew; Esmaeily, Amir Sajad; Godwin, Ian; Coelho, João; Nicolosi, Valeria; Lauth, Jannika; Kulkarni, Aditya; Kinge, Sachin; Siebbeles, Laurens D. A.; Duesberg, Georg S.; Coleman, Jonathan N.

2017-04-01

All-printed transistors consisting of interconnected networks of various types of two-dimensional nanosheets are an important goal in nanoscience. Using electrolytic gating, we demonstrate all-printed, vertically stacked transistors with graphene source, drain, and gate electrodes, a transition metal dichalcogenide channel, and a boron nitride (BN) separator, all formed from nanosheet networks. The BN network contains an ionic liquid within its porous interior that allows electrolytic gating in a solid-like structure. Nanosheet network channels display on:off ratios of up to 600, transconductances exceeding 5 millisiemens, and mobilities of >0.1 square centimeters per volt per second. Unusually, the on-currents scaled with network thickness and volumetric capacitance. In contrast to other devices with comparable mobility, large capacitances, while hindering switching speeds, allow these devices to carry higher currents at relatively low drive voltages.

Graphene bolometer with thermoelectric readout and capacitive coupling to an antenna

NASA Astrophysics Data System (ADS)

Skoblin, Grigory; Sun, Jie; Yurgens, August

2018-02-01

We report on a prototype graphene radiation detector based on the thermoelectric effect. We used a split top gate to create a p-n junction in the graphene, thereby making an effective thermocouple to read out the electronic temperature in the graphene. The electronic temperature is increased due to the AC currents induced in the graphene from the incoming radiation, which is first received by an antenna and then directed to the graphene via the top-gate capacitance. With the exception of the constant DC voltages applied to the gate, the detector does not need any bias and is therefore very simple to use. The measurements showed a clear response to microwaves at 94 GHz with the signal being almost temperature independent in the 4-100 K temperature range. The optical responsivity reached ˜700 V/W.

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

PubMed

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device andmore » thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.« less

Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

NASA Astrophysics Data System (ADS)

Vishvakarma, S. K.; Beohar, Ankur; Vijayvargiya, Vikas; Trivedi, Priyal

2017-07-01

In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device. Project supported by the Council of Scientific and Industrial Research (CSIR) Funded Research Project, Grant No. 22/0651/14/EMR-II, Government of India.

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

PubMed

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Super Gate Turn-Off Thyristor

DTIC Science & Technology

2006-08-01

semiconductor (nMOS) and turned it off through a positive metal oxide semiconductor (pMOS). For turn-on, although 1 V worked, a HP6227B power supply at 2...E3614A power supply at –8 V provided IG during the rise time, and thus need enough capacitance working to a frequency around 3/trise time...load’s screw terminal posts would have reduced the ESL and ESR. The SGTO turned off 5.8 A from the power supply at 20 V and was usually fan cooled

Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor

NASA Astrophysics Data System (ADS)

Yang, Paul; Kim, Hyung Jun; Zheng, Hong; Beom, Geon Won; Park, Jong-Sung; Kang, Chi Jung; Yoon, Tae-Sik

2017-06-01

A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor.

PubMed

Yang, Paul; Jun Kim, Hyung; Zheng, Hong; Won Beom, Geon; Park, Jong-Sung; Jung Kang, Chi; Yoon, Tae-Sik

2017-06-02

A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

Equivalent distributed capacitance model of oxide traps on frequency dispersion of C-V curve for MOS capacitors

NASA Astrophysics Data System (ADS)

Lu, Han-Han; Xu, Jing-Ping; Liu, Lu; Lai, Pui-To; Tang, Wing-Man

2016-11-01

An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C-V curve of MOS capacitors measured for a frequency range from 1 kHz to 1 MHz. The proposed model is based on the Fermi-Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal. The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data. Simulations indicate that the capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface, with negligible effects from the traps far from the interface, and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed. In addition, by excluding the negligible effect of oxide-trap conductance, the model avoids the use of imaginary numbers and complex calculations, and thus is simple and intuitive. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176100 and 61274112), the University Development Fund of the University of Hong Kong, China (Grant No. 00600009), and the Hong Kong Polytechnic University, China (Grant No. 1-ZVB1).

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

NASA Technical Reports Server (NTRS)

Shuler, Robert L.; Balasubramanian, Anupama; Narasimham, Balaji; Bhuva, Bharat; O'Neill, Patrick M.; Kouba, Coy

2006-01-01

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Undoped Si/SiGe Depletion-Mode Few-Electron Double Quantum Dots

NASA Astrophysics Data System (ADS)

Borselli, Matthew; Huang, Biqin; Ross, Richard; Croke, Edward; Holabird, Kevin; Hazard, Thomas; Watson, Christopher; Kiselev, Andrey; Deelman, Peter; Alvarado-Rodriguez, Ivan; Schmitz, Adele; Sokolich, Marko; Gyure, Mark; Hunter, Andrew

2011-03-01

We have successfully formed a double quantum dot in the sSi/SiGe material system without need for intentional dopants. In our design, a two-dimensional electron gas is formed in a strained silicon well by forward biasing a global gate. Lateral definition of quantum dots is established with reverse-biased gates with ~ 40 nm critical dimensions. Low-temperature capacitance and Hall measurements confirm electrons are confined in the Si-well with mobilities > 10 4 cm 2 / V - s . Further characterization identifies practical gate bias limits for this design and will be compared to simulation. Several double dot devices have been brought into the few-electron Coulomb blockade regime as measured by through-dot transport. Honeycomb diagrams and nonlinear through-dot transport measurements are used to quantify dot capacitances and addition energies of several meV. Sponsored by United States Department of Defense. Approved for Public Release, Distribution Unlimited.

FAST TRACK COMMUNICATION High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Xia, D. X.; Xu, J. B.

2010-11-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm2 V-1 s-1 and 2.1 cm2 V-1 s-1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics.

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

NASA Astrophysics Data System (ADS)

Panda, D. K.; Lenka, T. R.

2017-06-01

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I d-V ds, I d-V gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

PubMed

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

Engineering Ultra-Low Work Function of Graphene.

PubMed

Yuan, Hongyuan; Chang, Shuai; Bargatin, Igor; Wang, Ning C; Riley, Daniel C; Wang, Haotian; Schwede, Jared W; Provine, J; Pop, Eric; Shen, Zhi-Xun; Pianetta, Piero A; Melosh, Nicholas A; Howe, Roger T

2015-10-14

Low work function materials are critical for energy conversion and electron emission applications. Here, we demonstrate for the first time that an ultralow work function graphene is achieved by combining electrostatic gating with a Cs/O surface coating. A simple device is built from large-area monolayer graphene grown by chemical vapor deposition, transferred onto 20 nm HfO2 on Si, enabling high electric fields capacitive charge accumulation in the graphene. We first observed over 0.7 eV work function change due to electrostatic gating as measured by scanning Kelvin probe force microscopy and confirmed by conductivity measurements. The deposition of Cs/O further reduced the work function, as measured by photoemission in an ultrahigh vacuum environment, which reaches nearly 1 eV, the lowest reported to date for a conductive, nondiamond material.

Spatial mapping and statistical reproducibility of an array of 256 one-dimensional quantum wires

NASA Astrophysics Data System (ADS)

Al-Taie, H.; Smith, L. W.; Lesage, A. A. J.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2015-08-01

We utilize a multiplexing architecture to measure the conductance properties of an array of 256 split gates. We investigate the reproducibility of the pinch off and one-dimensional definition voltage as a function of spatial location on two different cooldowns, and after illuminating the device. The reproducibility of both these properties on the two cooldowns is high, the result of the density of the two-dimensional electron gas returning to a similar state after thermal cycling. The spatial variation of the pinch-off voltage reduces after illumination; however, the variation of the one-dimensional definition voltage increases due to an anomalous feature in the center of the array. A technique which quantifies the homogeneity of split-gate properties across the array is developed which captures the experimentally observed trends. In addition, the one-dimensional definition voltage is used to probe the density of the wafer at each split gate in the array on a micron scale using a capacitive model.

Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors.

PubMed

Lepadatu, A M; Palade, C; Slav, A; Maraloiu, A V; Lazanu, S; Stoica, T; Logofatu, C; Teodorescu, V S; Ciurea, M L

2017-04-28

High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO 2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2 /floating gate of single layer of Ge QDs in HfO 2 /tunnel HfO 2 /p-Si wafers. Both Ge and HfO 2 are nanostructured by RTA at moderate temperatures of 600-700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2-3 nm at a density of 4-5 × 10 15 m -2 is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO 2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO 2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO 2 NCs boundaries, while another part of the Ge atoms is present inside the HfO 2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance-time characteristic with 14% capacitance decay in the first 3000-4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO 2 , distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

NASA Astrophysics Data System (ADS)

Lagger, P.; Steinschifter, P.; Reiner, M.; Stadtmüller, M.; Denifl, G.; Naumann, A.; Müller, J.; Wilde, L.; Sundqvist, J.; Pogany, D.; Ostermaier, C.

2014-07-01

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔVth, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness tD and barrier thickness tB, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔNit, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔNit is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

Small signal measurement of Sc 2O 3 AlGaN/GaN moshemts

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kang, B. S.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J. K.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2004-02-01

The rf performance of 1 × 200 μm 2 AlGaN/GaN MOS-HEMTs with Sc 2O 3 used as both the gate dielectric and as a surface passivation layer is reported. A maximum fT of ˜11 GHz and fMAX of 19 GHz were obtained. The equivalent device parameters were extracted by fitting this data to obtain the transconductance, drain resistance, drain-source resistance, transfer time and gate-drain and gate-source capacitance as a function of gate voltage. The transfer time is in the order 0.5-1 ps and decreases with increasing gate voltage.

Characterisation of Nd2O3 thick gate dielectric for silicon

NASA Astrophysics Data System (ADS)

Dakhel, A. A.

2004-03-01

Thin neodymium films were prepared by the reactive synthesis method on Si (P) substrates to form MOS devices. The oxide films were characterised by UV absorption spectroscopy, X-ray fluorescence (EDXRF) and X-ray diffraction (XRD). The ac conductance and capacitance of the devices were studied as a function of frequency in the range 100 Hz-100 kHz, of temperature in the range 293-473 K and of gate voltage. It was proved that a suitable formalism to explain the frequency dependence of the ac conductivity and capacitance of the insulator is controlled by a universal power law based on the relaxation processes of the hopping or tunnelling of the current carriers between equilibrium sites. The temperature dependence of the ac conductance at the accumulation state shows a small activation energy of about 0.07 eV for a MOS device with amorphous neodymium oxide. The temperature dependence of the accumulation capacitance for a MOS structure with crystalline neodymium oxide shows a maximum at about 390 K; such a maximum was not observed for the structure with amorphous neodymium oxide. The method of capacitance-gate voltage (C-Vg) measurements was used to investigate the effect of annealing in air and in vacuum on the surface density of states (Nss) at the insulator/semiconductor (I/S) interface. It was concluded that the density of surface states in the mid-gap increases by about five times while the density of the trapped charges in the oxide layer decreases by about eight times when the oxide crystallises into a polycrystalline structure.

1.25  GHz sine wave gating InGaAs/InP single-photon detector with a monolithically integrated readout circuit.

PubMed

Jiang, Wen-Hao; Liu, Jian-Hong; Liu, Yin; Jin, Ge; Zhang, Jun; Pan, Jian-Wei

2017-12-15

InGaAs/InP single-photon detectors (SPDs) are the key devices for applications requiring near-infrared single-photon detection. The gating mode is an effective approach to synchronous single-photon detection. Increasing gating frequency and reducing the module size are important challenges for the design of such a detector system. Here we present for the first time, to the best of our knowledge, an InGaAs/InP SPD with 1.25 GHz sine wave gating (SWG) using a monolithically integrated readout circuit (MIRC). The MIRC has a size of 15  mm×15  mm and implements the miniaturization of avalanche extraction for high-frequency SWG. In the MIRC, low-pass filters and a low-noise radio frequency amplifier are integrated based on the technique of low temperature co-fired ceramic, which can effectively reduce the parasitic capacitance and extract weak avalanche signals. We then characterize the InGaAs/InP SPD to verify the functionality and reliability of the MIRC, and the SPD exhibits excellent performance with 27.5% photon detection efficiency, a 1.2 kcps dark count rate, and 9.1% afterpulse probability at 223 K and 100 ns hold-off time. With this MIRC, one can further design miniaturized high-frequency SPD modules that are highly required for practical applications.

Temperature-dependent field-effect carrier mobility in organic thin-film transistors with a gate SiO2 dielectric modified by H2O2 treatment

NASA Astrophysics Data System (ADS)

Lin, Yow-Jon; Hung, Cheng-Chun

2018-02-01

The effect of the modification of a gate SiO2 dielectric using an H2O2 solution on the temperature-dependent behavior of carrier transport for pentacene-based organic thin-film transistors (OTFTs) is studied. H2O2 treatment leads to the formation of Si(-OH) x (i.e., the formation of a hydroxylated layer) on the SiO2 surface that serves to reduce the SiO2 capacitance and weaken the pentacene-SiO2 interaction, thus increasing the field-effect carrier mobility ( µ) in OTFTs. The temperature-dependent behavior of carrier transport is dominated by the multiple trapping model. Note that H2O2 treatment leads to a reduction in the activation energy. The increased value of µ is also attributed to the weakening of the interactions of the charge carriers with the SiO2 dielectric that serves to reduce the activation energy.

Characterization and metrology implications of the 1997 NTRS

NASA Astrophysics Data System (ADS)

Class, W.; Wortman, J. J.

1998-11-01

In the Front-end (transistor forming) area of silicon CMOS device processing, several NTRS difficult challenges have been identified including; scaled and alternate gate dielectric materials, new DRAM dielectric materials, alternate gate materials, elevated contact structures, engineered channels, and large-area cost-effective silicon substrates. This paper deals with some of the characterization and metrology challenges facing the industry if it is to meet the projected needs identified in the NTRS. In the areas of gate and DRAM dielectric, scaling requires that existing material layers be thinned to maximize capacitance. For the current gate dielectric, SiO2 and its nitrided derivatives, direct tunneling will limit scaling to approximately 1.5nm for logic applications before power losses become unacceptable. Low power logic and memory applications may limit scaling to the 2.0-2.2nm range. Beyond these limits, dielectric materials having higher dielectric constant, will permit continued capacitance increases while allowing for the use of thicker dielectric layers, where tunneling may be minimized. In the near term silicon nitride is a promising SiO2 substitute material while in the longer term "high-k" materials such as tantalum pentoxide and barium strontium titanate (BST) will be required. For these latter materials, it is likely that a multilayer dielectric stack will be needed, consisting of an ultra-thin (1-2 atom layer) interfacial SiO2 layer and a high-k overlayer. Silicon wafer surface preparation control, as well as the control of composition, crystal structure, and thickness for such stacks pose significant characterization and metrology challenges. In addition to the need for new gate dielectric materials, new gate materials will be required to overcome the limitations of the current doped polysilicon gate materials. Such a change has broad ramifications on device electrical performance and manufacturing process robustness which again implies a broad range of new characterization and metrology requirements. Finally, the doped structure of the MOS transistor must scale to very small lateral and depth dimensions, and thermal budgets must be reduced to permit the retention of very abrupt highly doped drain and channel engineered structures. Eventually, the NTRS forecasts the need for an elevated contact structure. Here, there are significant challenges associated with three-dimensional dopant profiling, measurement of dopant activity in ultra-shallow device regions, as well as point defect metrology and characterization.

Influence of gate width on gate-channel carrier mobility in AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Ming; Ji, Qizheng; Gao, Zhiliang; Zhang, Shufeng; Lin, Zhaojun; Yuan, Yafei; Song, Bo; Mei, Gaofeng; Lu, Ziwei; He, Jihao

2017-11-01

For the fabricated AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate widths, the gate-channel carrier mobility is experimentally obtained from the measured current-voltage and capacitance-voltage curves. Under each gate voltage, the mobility gets lower with gate width increasing. Analysis shows that the phenomenon results from the polarization Coulomb field (PCF) scattering, which originates from the irregularly distributed polarization charges at the AlGaN/GaN interface. The device with a larger gate width is with a larger PCF scattering potential and a stronger PCF scattering intensity. As a function of gate width, PCF scattering potential shows a same trend with the mobility variation. And the theoretically calculated mobility values fits well with the experimentally obtained values. Varying gate widths will be a new perspective for the improvement of device characteristics by modulating the gate-channel carrier mobility.

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

NASA Astrophysics Data System (ADS)

McGuire, Felicia A.; Cheng, Zhihui; Price, Katherine; Franklin, Aaron D.

2016-08-01

There is a rising interest in employing the negative capacitance (NC) effect to achieve sub-60 mV/decade (below the thermal limit) switching in field-effect transistors (FETs). The NC effect, which is an effectual amplification of the applied gate potential, is realized by incorporating a ferroelectric material in series with a dielectric in the gate stack of a FET. One of the leading challenges to such NC-FETs is the variable substrate capacitance exhibited in 3D semiconductor channels (bulk, Fin, or nanowire) that minimizes the extent of sub-60 mV/decade switching. In this work, we demonstrate 2D NC-FETs that combine the NC effect with 2D MoS2 channels to extend the steep switching behavior. Using the ferroelectric polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)), these 2D NC-FETs are fabricated by modification of top-gated 2D FETs through the integrated addition of P(VDF-TrFE) into the gate stack. The impact of including an interfacial metal between the ferroelectric and dielectric is studied and shown to be critical. These 2D NC-FETs exhibit a decrease in subthreshold swing from 113 mV/decade down to 11.7 mV/decade at room temperature with sub-60 mV/decade switching occurring over more than 4 decades of current. The P(VDF-TrFE) proves to be an unstable option for a device technology, yet the superb switching behavior observed herein opens the way for further exploration of nanomaterials for extremely low-voltage NC-FETs.

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

NASA Astrophysics Data System (ADS)

Al-Ameri, Talib; Georgiev, Vihar P.; Sadi, Toufik; Wang, Yijiao; Adamu-Lema, Fikru; Wang, Xingsheng; Amoroso, Salvatore M.; Towie, Ewan; Brown, Andrew; Asenov, Asen

2017-03-01

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <1 1 0> and <1 0 0> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90° on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5 nm, 6 nm, 7 nm and 8 nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

Electrical Double Layer Capacitance in a Graphene-embedded Al2O3 Gate Dielectric

PubMed Central

Ki Min, Bok; Kim, Seong K.; Jun Kim, Seong; Ho Kim, Sung; Kang, Min-A; Park, Chong-Yun; Song, Wooseok; Myung, Sung; Lim, Jongsun; An, Ki-Seok

2015-01-01

Graphene heterostructures are of considerable interest as a new class of electronic devices with exceptional performance in a broad range of applications has been realized. Here, we propose a graphene-embedded Al2O3 gate dielectric with a relatively high dielectric constant of 15.5, which is about 2 times that of Al2O3, having a low leakage current with insertion of tri-layer graphene. In this system, the enhanced capacitance of the hybrid structure can be understood by the formation of a space charge layer at the graphene/Al2O3 interface. The electrical properties of the interface can be further explained by the electrical double layer (EDL) model dominated by the diffuse layer. PMID:26530817

A novel source-drain follower for monolithic active pixel sensors

NASA Astrophysics Data System (ADS)

Gao, C.; Aglieri, G.; Hillemanns, H.; Huang, G.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Mager, M.; Marin Tobon, C. A.; Martinengo, P.; Mugnier, H.; Musa, L.; Lee, S.; Reidt, F.; Riedler, P.; Rousset, J.; Sielewicz, K. M.; Snoeys, W.; Sun, X.; Van Hoorne, J. W.; Yang, P.

2016-09-01

Monolithic active pixel sensors (MAPS) receive interest in tracking applications in high energy physics as they integrate sensor and readout electronics in one silicon die with potential for lower material budget and cost, and better performance. Source followers (SFs) are widely used for MAPS readout: they increase charge conversion gain 1/Ceff or decrease the effective sensing node capacitance Ceff because the follower action compensates part of the input capacitance. Charge conversion gain is critical for analog power consumption and therefore for material budget in tracking applications, and also has direct system impact. This paper presents a novel source-drain follower (SDF), where both source and drain follow the gate potential improving charge conversion gain. For the inner tracking system (ITS) upgrade of the ALICE experiment at CERN, low material budget is a primary requirement. The SDF circuit was studied as part of the effort to optimize the effective capacitance of the sensing node. The collection electrode, input transistor and routing metal all contribute to Ceff. Reverse sensor bias reduces the collection electrode capacitance. The novel SDF circuit eliminates the contribution of the input transistor to Ceff, reduces the routing contribution if additional shielding is introduced, provides a way to estimate the capacitance of the sensor itself, and has a voltage gain closer to unity than the standard SF. The SDF circuit has a somewhat larger area with a somewhat smaller bandwidth, but this is acceptable in most cases. A test chip, manufactured in a 180 nm CMOS image sensor process, implements small prototype pixel matrices in different flavors to compare the standard SF to the novel SF and to the novel SF with additional shielding. The effective sensing node capacitance was measured using a 55Fe source. Increasing reverse substrate bias from -1 V to -6 V reduces Ceff by 38% and the equivalent noise charge (ENC) by 22% for the standard SF. The SDF provides a further 9% improvement for Ceff and 25% for ENC. The SDF circuit with additional shielding provides 18% improvement for Ceff, and combined with -6 V reverse bias yields almost a factor 2.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors.

PubMed

Giusi, G; Giordano, O; Scandurra, G; Rapisarda, M; Calvi, S; Ciofi, C

2016-04-01

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giusi, G.; Giordano, O.; Scandurra, G.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz{sup 1/2}, while DC performances are limited only bymore » the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.« less

Organic electrical double layer transistors gated with ionic liquids

NASA Astrophysics Data System (ADS)

Xie, Wei; Frisbie, C. Daniel

2011-03-01

Transport in organic semiconductors gated with several types of ionic liquids has been systematically studied at charge densities larger than 1013 cm-2 . We observe a pronounced maximum in channel conductance for both p-type and n-type organic single crystals which is attributed to carrier localization at the semiconductor-electrolyte interface. Carrier mobility, as well as charge density and dielectric capacitance are determined through displacement current measurement and capacitance-voltage measurement. By using a larger-sized and spherical anion, tris(pentafluoroethyl)trifluorophosphate (FAP), effective carrier mobility in rubrene can be enhanced substantially up to 3.2 cm2 V-1 s -1 . Efforts have been made to maximize the charge density in rubrene single crystals, and at low temperature when higher gate bias can be applied, charge density can more than double the amount of that at room temperature, reaching 8*1013 cm-2 holes (0.4 holes per rubrene molecule). NSF MRSEC program at the University of Minnesota.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kovchavtsev, A. P., E-mail: kap@isp.nsc.ru; Tsarenko, A. V.; Guzev, A. A.

The influence of electron energy quantization in a space-charge region on the accumulation capacitance of the InAs-based metal-oxide-semiconductor capacitors (MOSCAPs) has been investigated by modeling and comparison with the experimental data from Au/anodic layer(4-20 nm)/n-InAs(111)A MOSCAPs. The accumulation capacitance for MOSCAPs has been calculated by the solution of Poisson equation with different assumptions and the self-consistent solution of Schrödinger and Poisson equations with quantization taken into account. It was shown that the quantization during the MOSCAPs accumulation capacitance calculations should be taken into consideration for the correct interface states density determination by Terman method and the evaluation of gate dielectric thicknessmore » from capacitance-voltage measurements.« less

Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance

NASA Astrophysics Data System (ADS)

Madan, Jaya; Chaujar, Rishu

2017-02-01

This work integrates the merits of gate-drain underlapping (GDU) and N+ source pocket on cylindrical gate all around tunnel FET (GAA-TFET) to form GDU-PNIN-GAA-TFET. It is analysed that the source pocket located at the source-channel junction narrows the tunneling barrier width at the tunneling junction and thereby enhances the ON-state current of GAA-TFET. Further, it is obtained that the GDU resists the extension of carrier density (built-up under the gated region) towards the drain side (under the underlapped length), thereby suppressing the ambipolar current and reducing the parasitic capacitances of GAA-TFET. Consequently, the amalgamated merits of both engineering schemes are obtained in GDU-PNIN-GAA-TFET that thus conquers the greatest challenges faced by TFET. Thus, GDU-PNIN-GAA-TFET results in an up-gradation in the overall performance of GAA-TFET. Moreover, it is realised that the RF figure of merits FOMs such as cut-off frequency (fT) and maximum oscillation frequency (fMAX) are also considerably improved with integration of source pocket on GAA-TFET. Thus, the improved analog and RF performance of GDU-PNIN-GAA-TFET makes it ideal for low power and high-speed applications.

Design and analysis of 30 nm T-gate InAlN/GaN HEMT with AlGaN back-barrier for high power microwave applications

NASA Astrophysics Data System (ADS)

Murugapandiyan, P.; Ravimaran, S.; William, J.; Meenakshi Sundaram, K.

2017-11-01

In this article, we present the DC and microwave characteristics of a novel 30 nm T-gate InAlN/AlN/GaN HEMT with AlGaN back-barrier. The device structure is simulated by using Synopsys Sentaurus TCAD Drift-Diffusion transport model at room temperature. The device features are heavily doped (n++ GaN) source/drain regions with Si3N4 passivated device surface for reducing the contact resistances and gate capacitances of the device, which uplift the microwave characteristics of the HEMTs. 30 nm gate length D-mode (E-mode) HEMT exhibited a peak drain current density Idmax of 2.3 (2.42) A/mm, transconductance gm of 1.24(1.65) S/mm, current gain cut-off frequency ft of 262 (246) GHz, power gain cut-off frequency fmax of 246(290) GHz and the three terminal off-state breakdown voltage VBR of 40(38) V. The preeminent microwave characteristics with the higher breakdown voltage of the proposed GaN-based HEMT are the expected to be the most optimistic applicant for future high power millimeter wave applications.

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

2017-03-01

In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

State-conditional coherent charge qubit oscillations in a Si/SiGe quadruple quantum dot

NASA Astrophysics Data System (ADS)

Ward, Daniel R.; Kim, Dohun; Savage, Donald E.; Lagally, Max G.; Foote, Ryan H.; Friesen, Mark; Coppersmith, Susan N.; Eriksson, Mark A.

2016-10-01

Universal quantum computation requires high-fidelity single-qubit rotations and controlled two-qubit gates. Along with high-fidelity single-qubit gates, strong efforts have been made in developing robust two-qubit logic gates in electrically gated quantum dot systems to realise a compact and nanofabrication-compatible architecture. Here we perform measurements of state-conditional coherent oscillations of a charge qubit. Using a quadruple quantum dot formed in a Si/SiGe heterostructure, we show the first demonstration of coherent two-axis control of a double quantum dot charge qubit in undoped Si/SiGe, performing Larmor and Ramsey oscillation measurements. We extract the strength of the capacitive coupling between a pair of double quantum dots by measuring the detuning energy shift (≈75 μeV) of one double dot depending on the excess charge configuration of the other double dot. We further demonstrate that the strong capacitive coupling allows fast, state-conditional Landau-Zener-Stückelberg oscillations with a conditional π phase flip time of about 80 ps, showing a promising pathway towards multi-qubit entanglement and control in semiconductor quantum dots.

State-conditional coherent charge qubit oscillations in a Si/SiGe quadruple quantum dot

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ward, Daniel R.; Kim, Dohun; Savage, Donald E.

Universal quantum computation requires high-fidelity single-qubit rotations and controlled two-qubit gates. Along with high-fidelity single-qubit gates, strong efforts have been made in developing robust two-qubit logic gates in electrically gated quantum dot systems to realise a compact and nanofabrication-compatible architecture. Here we perform measurements of state-conditional coherent oscillations of a charge qubit. Using a quadruple quantum dot formed in a Si/SiGe heterostructure, we show the first demonstration of coherent two-axis control of a double quantum dot charge qubit in undoped Si/SiGe, performing Larmor and Ramsey oscillation measurements. We extract the strength of the capacitive coupling between a pair of doublemore » quantum dots by measuring the detuning energy shift (≈75 μeV) of one double dot depending on the excess charge configuration of the other double dot. Finally, we further demonstrate that the strong capacitive coupling allows fast, state-conditional Landau–Zener–Stückelberg oscillations with a conditional π phase flip time of about 80 ps, showing a promising pathway towards multi-qubit entanglement and control in semiconductor quantum dots.« less

State-conditional coherent charge qubit oscillations in a Si/SiGe quadruple quantum dot

DOE PAGES

Ward, Daniel R.; Kim, Dohun; Savage, Donald E.; ...

2016-10-18

Universal quantum computation requires high-fidelity single-qubit rotations and controlled two-qubit gates. Along with high-fidelity single-qubit gates, strong efforts have been made in developing robust two-qubit logic gates in electrically gated quantum dot systems to realise a compact and nanofabrication-compatible architecture. Here we perform measurements of state-conditional coherent oscillations of a charge qubit. Using a quadruple quantum dot formed in a Si/SiGe heterostructure, we show the first demonstration of coherent two-axis control of a double quantum dot charge qubit in undoped Si/SiGe, performing Larmor and Ramsey oscillation measurements. We extract the strength of the capacitive coupling between a pair of doublemore » quantum dots by measuring the detuning energy shift (≈75 μeV) of one double dot depending on the excess charge configuration of the other double dot. Finally, we further demonstrate that the strong capacitive coupling allows fast, state-conditional Landau–Zener–Stückelberg oscillations with a conditional π phase flip time of about 80 ps, showing a promising pathway towards multi-qubit entanglement and control in semiconductor quantum dots.« less

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

High performance photolithographically-patterned polymer thin-film transistors gated with an ionic liquid/poly(ionic liquid) blend ion gel

NASA Astrophysics Data System (ADS)

Thiburce, Q.; Porcarelli, L.; Mecerreyes, D.; Campbell, A. J.

2017-06-01

We demonstrate the fabrication of polymer thin-film transistors gated with an ion gel electrolyte made of the blend of an ionic liquid and a polymerised ionic liquid. The ion gel exhibits a high stability and ionic conductivity, combined with facile processing by simple drop-casting from solution. In order to avoid parasitic effects such as high hysteresis, high off-currents, and slow switching, a fluorinated photoresist is employed in order to enable high-resolution orthogonal patterning of the polymer semiconductor over an area that precisely defines the transistor channel. The resulting devices exhibit excellent characteristics, with an on/off ratio of 106, low hysteresis, and a very large transconductance of 3 mS. We show that this high transconductance value is mostly the result of ions penetrating the polymer film and doping the entire volume of the semiconductor, yielding an effective capacitance per unit area of about 200 μF cm-2, one order of magnitude higher than the double layer capacitance of the ion gel. This results in channel currents larger than 1 mA at an applied gate bias of only -1 V. We also investigate the dynamic performance of the devices and obtain a switching time of 20 ms, which is mostly limited by the overlap capacitance between the ion gel and the source and drain contacts.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

NASA Astrophysics Data System (ADS)

Xu, Jing; Jiang, Shu-Ye; Zhang, Min; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2018-03-01

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Comparison of conductor and dielectric inks in printed organic complementary transistors

NASA Astrophysics Data System (ADS)

Ng, Tse Nga; Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Abraham, Biby; Wu, Yiliang; Veres, Janos

2014-10-01

Two types of printable conductor and a bilayer gate dielectric are evaluated for use in all-additive, inkjetprinted complementary OTFTs. The Ag nanoparticle ink based on nonpolar alkyl amine surfactant or stabilizer enables good charge injection into p-channel devices, but this ink also leaves residual stabilizer that modifies the transistor backchannel and shifts the turn-on voltage to negative values. The Ag ink based on polar solvent requires dopant modification to improve charge injection to p-channel devices, but this ink allows the OTFT turn-on voltage to be close to 0 V. The reverse trend is observed for n-channel OTFTs. For gate insulator, a bilayer dielectric is demonstrated that combines the advantages of two types of insulator materials, in which a fluoropolymer reduces dipolar disorder at the semiconductor-dielectric interface, while a high-k PVDF terpolymer dielectric facilitates high gate capacitance. The dielectric is incorporated into an inverter and a three-stage ring oscillator, and the resulting circuits were demonstrated to operate at a supply voltage as low as 2 V, with bias stress levels comparable to circuits with other types of dielectrics.

cGMP and cyclic nucleotide-gated channels participate in mouse sperm capacitation.

PubMed

Cisneros-Mejorado, Abraham; Sánchez Herrera, Daniel P

2012-01-20

During capacitation of mammalian sperm intracellular [Ca(2+)] and cyclic nucleotides increase, suggesting that CNG channels play a role in the physiology of sperm. Here we study the effect of capacitation, 8Br-cAMP (8-bromoadenosine 3',5'-cyclic monophosphate) and 8Br-cGMP (8-bromoguanosine 3',5'-cyclic monophosphate) on the macroscopic ionic currents of mouse sperm, finding the existence of different populations of sperm, in terms of the recorded current and its response to cyclic nucleotides. Our results show that capacitation and cyclic nucleotides increase the ionic current, having a differential sensitivity to cGMP (cyclic guanosine monophosphate) and cAMP (cyclic adenosine monophosphate). Using a specific inhibitor we determine the contribution of CNG channels to macroscopic current and capacitation. Copyright © 2011 Federation of European Biochemical Societies. Published by Elsevier B.V. All rights reserved.

Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement

NASA Astrophysics Data System (ADS)

Li, Cong; Zhao, Xiaolong; Zhuang, Yiqi; Yan, Zhirui; Guo, Jiaming; Han, Ru

2018-03-01

L-shaped tunneling field-effect transistor (LTFET) has larger tunnel area than planar TFET, which leads to enhanced on-current ION . However, LTFET suffers from severe ambipolar behavior, which needs to be further optimized for low power and high-frequency applications. In this paper, both hetero-gate-dielectric (HGD) and lightly doped drain (LDD) structures are introduced into LTFET for suppression of ambipolarity and improvement of analog/RF performance of LTFET. Current-voltage characteristics, the variation of energy band diagrams, distribution of band-to-band tunneling (BTBT) generation and distribution of electric field are analyzed for our proposed HGD-LDD-LTFET. In addition, the effect of LDD on the ambipolar behavior of LTFET is investigated, the length and doping concentration of LDD is also optimized for better suppression of ambipolar current. Finally, analog/RF performance of HGD-LDD-LTFET are studied in terms of gate-source capacitance, gate-drain capacitance, cut-off frequency, and gain bandwidth production. TCAD simulation results show that HGD-LDD-LTFET not only drastically suppresses ambipolar current but also improves analog/RF performance compared with conventional LTFET.

Determining oxide trapped charges in Al2O3 insulating films on recessed AlGaN/GaN heterostructures by gate capacitance transients measurements

NASA Astrophysics Data System (ADS)

Fiorenza, Patrick; Greco, Giuseppe; Schilirò, Emanuela; Iucolano, Ferdinando; Lo Nigro, Raffaella; Roccaforte, Fabrizio

2018-05-01

This letter presents time-dependent gate-capacitance transient measurements (C–t) to determine the oxide trapped charges (N ot) in Al2O3 films deposited on recessed AlGaN/GaN heterostructures. The C–t transients acquired at different temperatures under strong accumulation allowed to accurately monitor the gradual electron trapping, while hindering the re-emission by fast traps that may affect conventional C–V hysteresis measurements. Using this method, an increase of N ot from 2 to 6 × 1012 cm‑2 was estimated between 25 and 150 °C. The electron trapping is ruled by an Arrhenius dependence with an activation energy of 0.12 eV which was associated to points defects present in the Al2O3 films.

The effect of a source-contacted light shield on the electrical characteristics of an LTPS TFT

NASA Astrophysics Data System (ADS)

Kim, Miryeon; Sun, Wookyung; Kang, Jongseuk; Shin, Hyungsoon

2017-08-01

The electrical characteristics of a low-temperature polycrystalline silicon thin-film transistor (TFT) with a source-contacted light shield (SCLS) are observed and analyzed. Compared with that of a conventional TFT without a light shield (LS), the on-current of the TFT with an SCLS is lower because the SCLS blocks the fringing electric field from the drain to the active layer. Furthermore, the gate-to-source capacitance (C gs) of the TFT with an SCLS in the off and saturation regions is higher than that of a conventional TFT, which is due to the gate-to-LS capacitance (C g-LS). The electrical characteristics of the TFT with an SCLS are thoroughly investigated by two-dimensional device simulations, and a semi-empirical C g-LS model for SPICE simulation is proposed and verified.

MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit.

PubMed

Liu, Xingqiang; Liang, Renrong; Gao, Guoyun; Pan, Caofeng; Jiang, Chunsheng; Xu, Qian; Luo, Jun; Zou, Xuming; Yang, Zhenyu; Liao, Lei; Wang, Zhong Lin

2018-05-21

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec -1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS 2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec -1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10 6 with channel length less than 100 nm. Furthermore, the inserted HfO 2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS 2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

NASA Astrophysics Data System (ADS)

Saeidi, Ali; Jazaeri, Farzan; Stolichnov, Igor; Luong, Gia V.; Zhao, Qing-Tai; Mantl, Siegfried; Ionescu, Adrian M.

2018-03-01

This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a trained-polycrystalline PZT capacitor and the tunnel FET (TFET) gate capacitance fabricated on a strained silicon-nanowire technology. We report a non-hysteretic switch configuration by combining a homojunction TFET and a negative capacitance effect booster, suitable for logic applications, for which the on-current is increased by a factor of 100, the transconductance by 2 orders of magnitude, and the low swing region is extended. The operation of a hysteretic negative capacitance TFET, when the matching condition for the negative capacitance is fulfilled only in a limited region of operation, is also reported and discussed. In this late case, a limited improvement in the device performance is observed. Overall, the paper demonstrates the main beneficial effects of negative capacitance on TFETs are the overdrive and transconductance amplification, which exactly address the most limiting performances of current TFETs.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

High-mobility low-temperature ZnO transistors with low-voltage operation

NASA Astrophysics Data System (ADS)

Bong, Hyojin; Lee, Wi Hyoung; Lee, Dong Yun; Kim, Beom Joon; Cho, Jeong Ho; Cho, Kilwon

2010-05-01

Low voltage high mobility n-type thin film transistors (TFTs) based on sol-gel processed zinc oxide (ZnO) were fabricated using a high capacitance ion gel gate dielectric. The ion gel gated solution-processed ZnO TFTs were found to exhibit excellent electrical properties. TFT carrier mobilities were 13 cm2/V s, ON/OFF current ratios were 105, regardless of the sintering temperature used for the preparation of the ZnO thin films. Ion gel gated ZnO TFTs are successfully demonstrated on plastic substrates for the large area flexible electronics.

Electro-optic modulator based gate transient suppression for sine-wave gated InGaAs/InP single photon avalanche photodiode

NASA Astrophysics Data System (ADS)

Zhang, Yixin; Zhang, Xuping; Shi, Yuanlei; Ying, Zhoufeng; Wang, Shun

2014-06-01

Capacitive gate transient noise has been problematic for the high-speed single photon avalanche photodiode (SPAD), especially when the operating frequency extends to the gigahertz level. We proposed an electro-optic modulator based gate transient noise suppression method for sine-wave gated InGaAs/InP SPAD. With the modulator, gate transient is up-converted to its higher-order harmonics that can be easily removed by low pass filtering. The proposed method enables online tuning of the operating rate without modification of the hardware setup. At 250 K, detection efficiency of 14.7% was obtained with 4.8×10-6 per gate dark count and 3.6% after-pulse probabilities for 1550-nm optical signal under 1-GHz gating frequency. Experimental results have shown that the performance of the detector can be maintained within a designated frequency range from 0.97 to 1.03 GHz, which is quite suitable for practical high-speed SPAD applications operated around the gigahertz level.

2D negative capacitance field-effect transistor with organic ferroelectrics.

PubMed

Zhang, Heng; Chen, Yan; Ding, Shijin; Wang, Jianlu; Bao, Wenzhong; Zhang, David Wei; Zhou, Peng

2018-06-15

In the past fifty years, complementary metal-oxide-semiconductor integrated circuits have undergone significant development, but Moore's law will soon come to an end. In order to break through the physical limit of Moore's law, 2D materials have been widely used in many electronic devices because of their high mobility and excellent mechanical flexibility. And the emergence of a negative capacitance field-effect transistor (NCFET) could not only break the thermal limit of conventional devices, but reduce the operating voltage and power consumption. This paper demonstrates a 2D NCFET that treats molybdenum disulfide as a channel material and organic P(VDF-TrFE) as a gate dielectric directly. This represents a new attempt to prepare NCFETs and produce flexible electronic devices. It exhibits a 10^6 on-/off-current ratio. And the minimum subthreshold swing (SS) of the 21 mV/decade and average SS of the 44 mV/decade in four orders of magnitude of drain current can also be observed at room temperature of 300 K.

2D negative capacitance field-effect transistor with organic ferroelectrics

NASA Astrophysics Data System (ADS)

Zhang, Heng; Chen, Yan; Ding, Shijin; Wang, Jianlu; Bao, Wenzhong; Zhang, David Wei; Zhou, Peng

2018-06-01

In the past fifty years, complementary metal-oxide-semiconductor integrated circuits have undergone significant development, but Moore’s law will soon come to an end. In order to break through the physical limit of Moore’s law, 2D materials have been widely used in many electronic devices because of their high mobility and excellent mechanical flexibility. And the emergence of a negative capacitance field-effect transistor (NCFET) could not only break the thermal limit of conventional devices, but reduce the operating voltage and power consumption. This paper demonstrates a 2D NCFET that treats molybdenum disulfide as a channel material and organic P(VDF-TrFE) as a gate dielectric directly. This represents a new attempt to prepare NCFETs and produce flexible electronic devices. It exhibits a 106 on-/off-current ratio. And the minimum subthreshold swing (SS) of the 21 mV/decade and average SS of the 44 mV/decade in four orders of magnitude of drain current can also be observed at room temperature of 300 K.

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.

PubMed

Nair, Aswathi; Bhattacharya, Prasenjit; Sambandan, Sanjiv

2017-12-20

The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

Measurement of the electronic compressibility of bilayer graphene

NASA Astrophysics Data System (ADS)

Henriksen, E. A.; Eisenstein, J. P.

2010-03-01

We report on recent measurements of the electronic compressibility in bilayer graphene. The devices consist of a mechanically exfoliated bilayer graphene flake in a dual-gated configuration, having a global back gate from the underlying Si substrate and a lithographically defined top gate. With suitable shielding, an oscillating voltage applied to the back gate will generate corresponding signals in the top gate only via electric fields which penetrate the graphene, thereby allowing a direct measurement of the compressibility of the bilayer [1]. In our experiments, we map this quantity as a function of the back and top gate bias voltages and compare it to similar maps of the graphene sheet resistivity and capacitance. We discuss our results in light of numerical calculations of the underlying band structure as well as recent theoretical predictions. [1] J. P. Eisenstein, L. N. Pfeiffer, K. W. West, Phys. Rev. B 50, 1760 (1994).

Gate-Sensing the Potential Landscape of a GaAs Two-Dimensional Electron Gas

NASA Astrophysics Data System (ADS)

Croot, Xanthe; Mahoney, Alice; Pauka, Sebastian; Colless, James; Reilly, David; Watson, John; Fallahi, Saeed; Gardner, Geoff; Manfra, Michael; Lu, Hong; Gossard, Arthur

In situ dispersive gate sensors hold potential as a means of enabling the scalable readout of quantum dot arrays. Sensitive to quantum capacitance, dispersive sensors have been used to detect inter- and intra-dot transitions in GaAs double quantum dots, and can distinguish the spin states of singlet triplet qubits. In addition, the gate-sensing technique is likely of value in probing the physics of Majorana zero modes in nanowire devices. Beyond the readout signatures associated with charge and spin configurations of qubits, gate-sensing is sensitive to trapped charge in the potential landscape. Here, we report gate-sensing signals arising from tunnelling of electrons between puddles of trapped charge in a GaAs 2DEG. We examine these signals in a family of different devices with varying mobilities, and as a function of temperature and bias. Implications for qubit readout using the gate-sensing technique are discussed.

Transfer printing of thermoreversible ion gels for flexible electronics.

PubMed

Lee, Keun Hyung; Zhang, Sipei; Gu, Yuanyan; Lodge, Timothy P; Frisbie, C Daniel

2013-10-09

Thermally assisted transfer printing was employed to pattern thin films of high capacitance ion gels on polyimide, poly(ethylene terephthalate), and SiO2 substrates. The ion gels consisted of 20 wt % block copolymer poly(styrene-b-ethylene oxide-b-styrene and 80 wt % ionic liquid 1-ethyl-3-methylimidazolium bis(trifluoromethyl sulfonyl)amide. Patterning resolution was on the order of 10 μm. Importantly, ion gels containing the block polymer with short PS end blocks (3.4 kg/mol) could be transfer-printed because of thermoreversible gelation that enabled intimate gel-substrate contact at 100 °C, while gels with long PS blocks (11 kg/mol) were not printable at the same temperature due to poor wetting contact between the gel and substrates. By using printed ion gels as high-capacitance gate insulators, electrolyte-gated thin-film transistors were fabricated that operated at low voltages (<1 V) with high on/off current ratios (∼10(5)). Statistical analysis of carrier mobility, turn-on voltage, and on/off ratio for an array of printed transistors demonstrated the excellent reproducibility of the printing technique. The results show that transfer printing is an attractive route to pattern high-capacitance ion gels for flexible thin-film devices.

Enhancement of capacitance benefit by drain offset structure in tunnel field-effect transistor circuit speed associated with tunneling probability increase

NASA Astrophysics Data System (ADS)

Asai, Hidehiro; Mori, Takahiro; Matsukawa, Takashi; Hattori, Junichi; Endo, Kazuhiko; Fukuda, Koichi

2018-04-01

The effect of a drain offset structure on the operation speed of a tunnel field-effect transistor (TFET) ring oscillator is investigated by technology computer-aided design (TCAD) simulation. We demonstrate that the reduction of gate-drain capacitance by the drain offset structure dramatically increases the operation speed of the ring oscillators. Interestingly, we find that this capacitance benefit to operation speed is enhanced by the increase in band-to-band tunneling probability. The “synergistic” speed enhancement by the drain offset structure and the tunneling rate increase will have promising application to the significant improvement of the operation speed of TFET circuits.

Energetic distributions of interface states Dit(phi sub s) of MOS transistors in extension of Kuhn's quasistatic C(V)-method

NASA Astrophysics Data System (ADS)

Krautschneider, W.; Wagemann, H. G.

1983-10-01

Kuhn's quasi-static C(V)-method has been extended to MOS transistors by considering the capacitances of the source and drain p-n junctions additionally to the MOS varactor circuit model. The width of the space charge layers w(phi sub s) is calculated as a function of the surface potential phi sub s and applied to the MOS capacitance as a function of the gate voltage. Capacitance behavior for different channel length is presented as a model and compared to measurement results and evaluations of energetic distributions of interface states Dit(phi sub s) for MOS transistor and MOS varactor on the same chip.

A carrier-based analytical theory for negative capacitance symmetric double-gate field effect transistors and its simulation verification

NASA Astrophysics Data System (ADS)

Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

2015-09-01

A carrier-based analytical drain current model for negative capacitance symmetric double-gate field effect transistors (NC-SDG FETs) is proposed by solving the differential equation of the carrier, the Pao-Sah current formulation, and the Landau-Khalatnikov equation. The carrier equation is derived from Poisson’s equation and the Boltzmann distribution law. According to the model, an amplified semiconductor surface potential and a steeper subthreshold slope could be obtained with suitable thicknesses of the ferroelectric film and insulator layer at room temperature. Results predicted by the analytical model agree well with those of the numerical simulation from a 2D simulator without any fitting parameters. The analytical model is valid for all operation regions and captures the transitions between them without any auxiliary variables or functions. This model can be used to explore the operating mechanisms of NC-SDG FETs and to optimize device performance.

Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs

NASA Astrophysics Data System (ADS)

Pradhan, K. P.; Andrade, M. G. C.; Sahu, P. K.

2016-12-01

The symmetrical dual-k spacer technology in hybrid FinFETs has been widely explored for better electrostatic control of the fin-based devices in nanoscale region. Since, high-k tangible spacer materials are broadly became a matter of study due to their better immunity to the short channel effects (SCEs) in nano devices. However, the only cause that restricts the circuit designers from using high-k spacer is the unreasonable increasing fringing capacitances. This work quantitatively analyzed the benefits and drawbacks of considering two different dielectric spacer materials symmetrically in either sides of the channel for the hybrid device. From the demonstrated results, the inclusion of high-k spacer predicts an effective reduction in off-state leakage along with an improvement in drive current. However, these devices have paid the cost in terms of a high total gate-to-gate capacitance (Cgg) that consequently results poor cutoff frequency (fT) and delay.

Capacitive Trans-Impedance Amplifier Circuit with Charge Injection Compensation

NASA Technical Reports Server (NTRS)

Milkov, Mihail M. (Inventor); Gulbransen, David J. (Inventor)

2016-01-01

A capacitive trans-impedance amplifier circuit with charge injection compensation is provided. A feedback capacitor is connected between an inverting input port and an output port of an amplifier. A MOS reset switch has source and drain terminals connected between the inverting input and output ports of the amplifier, and a gate terminal controlled by a reset signal. The reset switch is open or inactive during an integration phase, and closed or active to electrically connect the inverting input port and output port of the amplifier during a reset phase. One or more compensation capacitors are provided that are not implemented as gate oxide or MOS capacitors. Each compensation capacitor has a first port connected to a compensation signal that is a static signal or a toggling compensation signal that toggles between two compensation voltage values, and a second port connected to the inverting input port of the amplifier.

Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vostokov, N. V., E-mail: vostokov@ipm.sci-nnov.ru; Shashkin, V. I.

2015-11-28

We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The resultsmore » given by the different models are discussed.« less

Gatemon Benchmarking and Two-Qubit Operation

NASA Astrophysics Data System (ADS)

Casparis, Lucas; Larsen, Thorvald; Olsen, Michael; Petersson, Karl; Kuemmeth, Ferdinand; Krogstrup, Peter; Nygard, Jesper; Marcus, Charles

Recent experiments have demonstrated superconducting transmon qubits with semiconductor nanowire Josephson junctions. These hybrid gatemon qubits utilize field effect tunability singular to semiconductors to allow complete qubit control using gate voltages, potentially a technological advantage over conventional flux-controlled transmons. Here, we present experiments with a two-qubit gatemon circuit. We characterize qubit coherence and stability and use randomized benchmarking to demonstrate single-qubit gate errors of ~0.5 % for all gates, including voltage-controlled Z rotations. We show coherent capacitive coupling between two gatemons and coherent SWAP operations. Finally, we perform a two-qubit controlled-phase gate with an estimated fidelity of ~91 %, demonstrating the potential of gatemon qubits for building scalable quantum processors. We acknowledge financial support from Microsoft Project Q and the Danish National Research Foundation.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

Investigation of sensing mechanism and signal amplification in carbon nanotube based microfluidic liquid-gated transistors via pulsating gate bias.

PubMed

Wijaya, I Putu Mahendra; Nie, Tey Ju; Rodriguez, Isabel; Mhaisalkar, Subodh G

2010-06-07

The advent of a carbon nanotube liquid-gated transistor (LGFET) for biosensing applications allows the possibility of real-time and label-free detection of biomolecular interactions. The use of an aqueous solution as dielectric, however, has traditionally restricted the operating gate bias (VG) within |VG| < 1 V, due to the electrolysis of water. Here, we propose pulsed-gating as a facile method to extend the operation window of LGFETs to |VG| > 1 V. A comparison between simulation and experimental results reveals that at voltages in excess of 1 V, the LGFET sensing mechanism has a contribution from two factors: electrostatic gating as well as capacitance modulation. Furthermore, the large IDS drop observed in the |VG| > 1 V region indicates that pulsed-gating may be readily employed as a simple method to amplify the signal in the LGFET and pushes the detection limit down to attomolar concentration levels, an order of magnitude improvement over conventionally employed DC VG biasing.

Origin of flatband voltage shift and unusual minority carrier generation in thermally grown GeO2/Ge metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Hosoi, Takuji; Kutsuki, Katsuhiro; Okamoto, Gaku; Saito, Marina; Shimura, Takayoshi; Watanabe, Heiji

2009-05-01

Improvement in electrical properties of thermally grown GeO2/Ge metal-oxide-semiconductor (MOS) capacitors, such as significantly reduced flatband voltage (VFB) shift, small hysteresis, and minimized minority carrier response in capacitance-voltage (C-V) characteristics, has been demonstrated by in situ low temperature vacuum annealing prior to gate electrode deposition. Thermal desorption analysis has revealed that not only water but also hydrocarbons are easily infiltrated into GeO2 layers during air exposure and desorbed at around 300 °C, indicating that organic molecules within GeO2/Ge MOS structures are possible origins of electrical defects. The inversion capacitance, indicative of minority carrier generation, increases with air exposure time for Au/GeO2/Ge MOS capacitors, while maintaining an interface state density (Dit) of about a few 1011 cm-2 eV-1. Unusual increase in inversion capacitance was found to be suppressed by Al2O3 capping (Au/Al2O3/GeO2/Ge structures). This suggests that electrical defects induced outside the Au electrode by infiltrated molecules may enhance the minority carrier generation, and thus acting as a minority carrier source just like MOS field-effect transistors.

Wide memory window in graphene oxide charge storage nodes

NASA Astrophysics Data System (ADS)

Wang, Shuai; Pu, Jing; Chan, Daniel S. H.; Cho, Byung Jin; Loh, Kian Ping

2010-04-01

Solution-processable, isolated graphene oxide (GO) monolayers have been used as a charge trapping dielectric in TaN gate/Al2O3/isolated GO sheets/SiO2/p-Si memory device (TANOS). The TANOS type structure serves as memory device with the threshold voltage controlled by the amount of charge trapped in the GO sheet. Capacitance-Voltage hysteresis curves reveal a 7.5 V memory window using the sweep voltage of -5-14 V. Thermal reduction in the GO to graphene reduces the memory window to 1.4 V. The unique charge trapping properties of GO points to the potential applications in flexible organic memory devices.

Effects of Dissipation on a Superconducting Single Electron Transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kycia, J. B.; Chen, J.; Therrien, R.

2001-07-02

We measure the effect of dissipation on the minimum zero-bias conductance, G{sup min}{sub 0} , of a superconducting single electron transistor (sSET) capacitively coupled to a two-dimensional electron gas (2DEG) in a GaAs/AlGaAs heterostructure. Depleting the 2DEG with a back gate voltage decreases the dissipation experienced by the sSET in situ. We find that G{sup min}{sub 0} increases as the dissipation is increased or the temperature is reduced; the functional forms of these dependences are compared with the model of Wilhelm etal.in which the leads coupled to the sSET are represented by lossy transmission lines.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Numerical analysis of the reverse blocking enhancement in High-K passivation AlGaN/GaN Schottky barrier diodes with gated edge termination

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Xin, Qi; Li, Ruonan; Yu, Qi

2018-02-01

We conducted a numerical analysis on high-K dielectric passivated AlGaN/GaN Schottky barrier diodes (HPG-SBDs) with a gated edge termination (GET). The reverse blocking characteristics were significantly enhanced without the stimulation of any parasitic effect by varying the dielectric thickness dge under the GET, thickness TP, and dielectric constant εr of the high-K passivation layer. The leakage current was reduced by increasing εr and decreasing dge. The breakdown voltage of the device was enhanced by increasing εr and TP. The highest breakdown voltage of 970 V and the lowest leakage current of 0.5 nA/mm were achieved under the conditions of εr = 80, TP = 800 nm, and dge = 10 nm. C-V simulation revealed that the HPG-SBDs induced no parasitic capacitance by comparing the integrated charges of the devices with different high-K dielectrics and different dge.

Impact of oxygen precursor flow on the forward bias behavior of MOCVD-Al2O3 dielectrics grown on GaN

NASA Astrophysics Data System (ADS)

Chan, Silvia H.; Bisi, Davide; Liu, Xiang; Yeluri, Ramya; Tahhan, Maher; Keller, Stacia; DenBaars, Steven P.; Meneghini, Matteo; Mishra, Umesh K.

2017-11-01

This paper investigates the effects of the oxygen precursor flow supplied during metalorganic chemical vapor deposition (MOCVD) of Al2O3 films on the forward bias behavior of Al2O3/GaN metal-oxide-semiconductor capacitors. The low oxygen flow (100 sccm) delivered during the in situ growth of Al2O3 on GaN resulted in films that exhibited a stable capacitance under forward stress, a lower density of stress-generated negative fixed charges, and a higher dielectric breakdown strength compared to Al2O3 films grown under high oxygen flow (480 sccm). The low oxygen grown Al2O3 dielectrics exhibited lower gate current transients in stress/recovery measurements, providing evidence of a reduced density of trap states near the GaN conduction band and an enhanced robustness under accumulated gate stress. This work reveals oxygen flow variance in MOCVD to be a strategy for controlling the dielectric properties and performance.

Analysis of source/drain engineered 22nm FDSOI using high-k spacers

NASA Astrophysics Data System (ADS)

Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

While looking at the current classical scaling of devices there are lots of short channel effects come into consideration. In this paper, a novel device structure is proposed that is an improved structure of Modified Source(MS) FDSOI in terms of better electrical performance, on current and reduced off state leakage current with a higher Ion/Ioff ratio that helps in fast switching of low power nano electronic devices. Proposed structure has Modified drain and source regions with two different type to doping profile at 22nm gate length. In the upper part of engineered region (MD and MS) the doping concentration is kept high and less in the lower region. The purpose was to achieve low parasitic capacitance in source and drain region by reducing doping concentration [1].

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

NASA Astrophysics Data System (ADS)

Gao, Tao; Xu, Ruimin; Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng

2015-06-01

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr0.52Ti0.48)-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (gm-Vg) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

A 4H Silicon Carbide Gate Buffer for Integrated Power Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ericson, N; Frank, S; Britton, C

2014-02-01

A gate buffer fabricated in a 2-mu m 4H silicon carbide (SiC) process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics, simulation results, and directions for future improvement of this buffer are presented. In addition, plans for its incorporation into anmore » isolated high-side/low-side gate-driver architecture, fully integrated with power switching devices in a SiC process, are briefly discussed. This letter represents the first reported MOSFET-based gate buffer fabricated in 4H SiC.« less

Surface properties of SiO2 with and without H2O2 treatment as gate dielectrics for pentacene thin-film transistor applications

NASA Astrophysics Data System (ADS)

Hung, Cheng-Chun; Lin, Yow-Jon

2018-01-01

The effect of H2O2 treatment on the surface properties of SiO2 is studied. H2O2 treatment leads to the formation of Si(sbnd OH)x at the SiO2 surface that serves to reduce the number of trap states, inducing the shift of the Fermi level toward the conduction band minimum. H2O2 treatment also leads to a noticeable reduction in the value of the SiO2 capacitance per unit area. The effect of SiO2 layers with H2O2 treatment on the behavior of carrier transports for the pentacene/SiO2-based organic thin-film transistor (OTFT) is also studied. Experimental identification confirms that the shift of the threshold voltage towards negative gate-source voltages is due to the reduced number of trap states in SiO2 near the pentacene/SiO2 interface. The existence of a hydrogenated layer between pentacene and SiO2 leads to a change in the pentacene-SiO2 interaction, increasing the value of the carrier mobility.

Triple voltage dc-to-dc converter and method

DOEpatents

Su, Gui-Jia

2008-08-05

A circuit and method of providing three dc voltage buses and transforming power between a low voltage dc converter and a high voltage dc converter, by coupling a primary dc power circuit and a secondary dc power circuit through an isolation transformer; providing the gating signals to power semiconductor switches in the primary and secondary circuits to control power flow between the primary and secondary circuits and by controlling a phase shift between the primary voltage and the secondary voltage. The primary dc power circuit and the secondary dc power circuit each further comprising at least two tank capacitances arranged in series as a tank leg, at least two resonant switching devices arranged in series with each other and arranged in parallel with the tank leg, and at least one voltage source arranged in parallel with the tank leg and the resonant switching devices, said resonant switching devices including power semiconductor switches that are operated by gating signals. Additional embodiments having a center-tapped battery on the low voltage side and a plurality of modules on both the low voltage side and the high voltage side are also disclosed for the purpose of reducing ripple current and for reducing the size of the components.

Simulation design of high reverse blocking high-K/low-K compound passivation AlGaN/GaN Schottky barrier diode with gated edge termination

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Xin, Qi; Li, Ruonan; Yu, Qi

2017-11-01

In this paper, a novel high-K/low-K compound passivation AlGaN/GaN Schottky Barrier Diode (CPG-SBD) is proposed to improve the off-state characteristics of AlGaN/GaN schottky barrier diode with gated edge termination (GET-SBD) by adding low-K blocks in to the high-K passivation layer. The reverse leakage current of CPG-SBD can be reduced to 1.6 nA/mm by reducing the thickness of high-K dielectric under GET region to 5 nm, while the forward voltage and on-state resistance keep 1 V and 3.8 Ω mm, respectively. Breakdown voltage of CPG-SBDs can be improved by inducing discontinuity of the electric field at the high-K/low-K interface. The breakdown voltage of the optimized CPG-SBD with 4 blocks of low-K can reach 1084 V with anode to cathode distance of 5 μm yielding a high FOM of 5.9 GW/cm2. From the C-V simulation results, CPG-SBDs induce no parasitic capacitance by comparison of the GET-SBDs.

Steep-slope hysteresis-free negative capacitance MoS2 transistors

NASA Astrophysics Data System (ADS)

Si, Mengwei; Su, Chun-Jung; Jiang, Chunsheng; Conrad, Nathan J.; Zhou, Hong; Maize, Kerry D.; Qiu, Gang; Wu, Chien-Ting; Shakouri, Ali; Alam, Muhammad A.; Ye, Peide D.

2018-01-01

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4-12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

Abrupt Depletion Layer Approximation for the Metal Insulator Semiconductor Diode.

ERIC Educational Resources Information Center

Jones, Kenneth

1979-01-01

Determines the excess surface change carrier density, surface potential, and relative capacitance of a metal insulator semiconductor diode as a function of the gate voltage, using the precise questions and the equations derived with the abrupt depletion layer approximation. (Author/GA)

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Anomalous bias-stress-induced unstable phenomena of InZnO thin-film transistors using Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Xu, Wangying; Dai, Mingzhi; Liang, Lingyan; Liu, Zhimin; Sun, Xilian; Wan, Qing; Cao, Hongtao

2012-05-01

InZnO thin-film transistors using high-κ Ta2O5 gate dielectric are presented and analysed. The large capacitance coupling effect of amorphous Ta2O5 results in fabricated devices with good electrical properties. However, an anomalous negative threshold voltage (Vth) shift under positive bias stress is observed. It is suggested that electron detrapping from the high-κ Ta2O5 dielectric to the gate electrode is responsible for this Vth shift, which is supported both by the logarithmical dependence of the Vth change on the duration of the bias stress and device simulation extracted trapped charges involved.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE and the Japan Society of Applied Physics. Dr. Hiramoto is a fellow of Japan Society of Applied Physics and a member of IEEE and IEICE. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He was on Committee of IEDM from 2003 to 2009. He was the Program Chair of Symposium on VLSI Technology in 2013 and was the General Chair in 2015. He is the Program Chair of International Conference on Solid-State Devices and Materials (SSDM) in 2016.

Impact of Interface States and Bulk Carrier Lifetime on Photocapacitance of Metal/Insulator/GaN Structure for Ultraviolet Light Detection

NASA Astrophysics Data System (ADS)

Bidzinski, Piotr; Miczek, Marcin; Adamowicz, Boguslawa; Mizue, Chihoko; Hashizume, Tamotsu

2011-04-01

The influence of interface state density and bulk carrier lifetime on the dependencies of photocapacitance versus wide range of gate bias (-0.1 to -3 V) and light intensity (109 to 1020 photon cm-2 s-1) was studied for metal/insulator/n-GaN UV light photodetector by means of numerical simulations. The light detection limit and photocapacitance saturation were analyzed in terms of the interface charge and interface Fermi level for electrons and holes and effective interface recombination velocity. It was proven that the excess carrier recombination through interface states is the main reason of photocapacitance signal quenching. It was found that the photodetector can work in various modes (on-off or quantitative light measurement) adjusted by the gate bias. A comparison between experimental data and theoretical capacitance-light intensity characteristics was made. A new method for the determination of the interface state density distribution from capacitance-voltage-light intensity measurements was also proposed.

Extraction of sub-gap density of states via capacitance-voltage measurement for the erasing process in a TFT charge-trapping memory

NASA Astrophysics Data System (ADS)

Chiang, Yen-Chang; Hsiao, Yang-Hsuan; Li, Jeng-Ting; Chen, Jen-Sue

2018-02-01

Charge-trapping memories (CTMs) based on zinc tin oxide (ZTO) semiconductor thin-film transistors (TFTs) can be programmed by a positive gate voltage and erased by a negative gate voltage in conjunction with light illumination. To understand the mechanism involved, the sub-gap density of states associated with ionized oxygen vacancies in the ZTO active layer is extracted from optical response capacitance-voltage (C-V) measurements. The corresponding energy states of ionized oxygen vacancies are observed below the conduction band minimum at approximately 0.5-1.0 eV. From a comparison of the fitted oxygen vacancy concentration in the CTM-TFT after the light-bias erasing operation, it is found that the pristine-erased device contains more oxygen vacancies than the program-erased device because the trapped electrons in the programmed device are pulled into the active layer and neutralized by the oxygen vacancies that are present there.

Temperature dependence of frequency dispersion in III–V metal-oxide-semiconductor C-V and the capture/emission process of border traps

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vais, Abhitosh, E-mail: Abhitosh.Vais@imec.be; Martens, Koen; DeMeyer, Kristin

2015-08-03

This paper presents a detailed investigation of the temperature dependence of frequency dispersion observed in capacitance-voltage (C-V) measurements of III-V metal-oxide-semiconductor (MOS) devices. The dispersion in the accumulation region of the capacitance data is found to change from 4%–9% (per decade frequency) to ∼0% when the temperature is reduced from 300 K to 4 K in a wide range of MOS capacitors with different gate dielectrics and III-V substrates. We show that such significant temperature dependence of C-V frequency dispersion cannot be due to the temperature dependence of channel electrostatics, i.e., carrier density and surface potential. We also show that the temperaturemore » dependence of frequency dispersion, and hence, the capture/emission process of border traps can be modeled by a combination of tunneling and a “temperature-activated” process described by a non-radiative multi-phonon model, instead of a widely believed single-step elastic tunneling process.« less

Pulse-Driven Capacitive Lead Ion Detection with Reduced Graphene Oxide Field-Effect Transistor Integrated with an Analyzing Device for Rapid Water Quality Monitoring.

PubMed

Maity, Arnab; Sui, Xiaoyu; Tarman, Chad R; Pu, Haihui; Chang, Jingbo; Zhou, Guihua; Ren, Ren; Mao, Shun; Chen, Junhong

2017-11-22

Rapid and real-time detection of heavy metals in water with a portable microsystem is a growing demand in the field of environmental monitoring, food safety, and future cyber-physical infrastructure. Here, we report a novel ultrasensitive pulse-driven capacitance-based lead ion sensor using self-assembled graphene oxide (GO) monolayer deposition strategy to recognize the heavy metal ions in water. The overall field-effect transistor (FET) structure consists of a thermally reduced graphene oxide (rGO) channel with a thin layer of Al 2 O 3 passivation as a top gate combined with sputtered gold nanoparticles that link with the glutathione (GSH) probe to attract Pb 2+ ions in water. Using a preprogrammed microcontroller, chemo-capacitance based detection of lead ions has been demonstrated with this FET sensor. With a rapid response (∼1-2 s) and negligible signal drift, a limit of detection (LOD) < 1 ppb and excellent selectivity (with a sensitivity to lead ions 1 order of magnitude higher than that of interfering ions) can be achieved for Pb 2+ measurements. The overall assay time (∼10 s) for background water stabilization followed by lead ion testing and calculation is much shorter than common FET resistance/current measurements (∼minutes) and other conventional methods, such as optical and inductively coupled plasma methods (∼hours). An approximate linear operational range (5-20 ppb) around 15 ppb (the maximum contaminant limit by US Environmental Protection Agency (EPA) for lead in drinking water) makes it especially suitable for drinking water quality monitoring. The validity of the pulse method is confirmed by quantifying Pb 2+ in various real water samples such as tap, lake, and river water with an accuracy ∼75%. This capacitance measurement strategy is promising and can be readily extended to various FET-based sensor devices for other targets.

Organic transistors making use of room temperature ionic liquids as gating medium

NASA Astrophysics Data System (ADS)

Hoyos, Jonathan Javier Sayago

The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric biases. We systematically investigated EG transistors employing RTILs belonging to the same family, i.e. based on a common anion and different cations. The transistor characteristics showed a limited cation influence in establishing the p-type doping of the conducting polymer. Interestingly, we observed that the transistor response time depends on at least two processes: the redistribution of ions from the electrolyte into the transistor channel, affecting the gate-source current (I gs); and the redistribution of charges in the transistor channel, affecting the drain-source current (Ids), as a function of time. The two processes have different rates, with the latter being the slowest. Incorporating propylene carbonate in the electrolyte proved to be an effective solution to increase the ionic conductivity, to lower the viscosity and, consequently, to reduce the transistor response time. Finally, we were able to demonstrate a multifunctional device integrating the transistor logic function with that of energy storage in a supercapacitor: the TransCap. The polymer/electrolyte/carbon vertical stacking of the EG transistor features the cell configuration of a hybrid supercapacitor. Supercapacitors are high specific power systems that, for their ability to store/deliver charge within short times may outperform batteries in applications having high power demand. When the TransCap is ON (open transistor channel), the polymer and the carbon gate electrodes store charge (Q) at a given Vgs, hence the stored energy equals Q˙V gs. When the TransCap is switched OFF, the channel and the gate are discharged and the energy can be delivered back to power other electronic components. EG transistors, making use of activated carbon as gate electrode and different RTILs as well as RTIL solvent mixtures as electrolyte gating medium, are interesting towards low voltage printable electronics. The high capacitance at the interface between the electrolyte and the transistor channel enables energy storage within the EG transistor architecture.

Gate line edge roughness amplitude and frequency variation effects on intra die MOS device characteristics

NASA Astrophysics Data System (ADS)

Hamadeh, Emad; Gunther, Norman G.; Niemann, Darrell; Rahman, Mahmud

2006-06-01

Random fluctuations in fabrication process outcomes such as gate line edge roughness (LER) give rise to corresponding fluctuations in scaled down MOS device characteristics. A thermodynamic-variational model is presented to study the effects of LER on threshold voltage and capacitance of sub-50 nm MOS devices. Conceptually, we treat the geometric definition of the MOS devices on a die as consisting of a collection of gates. In turn, each of these gates has an area, A, and a perimeter, P, defined by nominally straight lines subject to random process outcomes producing roughness. We treat roughness as being deviations from straightness consisting of both transverse amplitude and longitudinal wavelength each having lognormal distribution. We obtain closed-form expressions for variance of threshold voltage ( Vth), and device capacitance ( C) at Onset of Strong Inversion (OSI) for a small device. Using our variational model, we characterized the device electrical properties such as σ and σC in terms of the statistical parameters of the roughness amplitude and spatial frequency, i.e., inverse roughness wavelength. We then verified our model with numerical analysis of Vth roll-off for small devices and σ due to dopant fluctuation. Our model was also benchmarked against TCAD of σ as a function of LER. We then extended our analysis to predict variations in σ and σC versus average LER spatial frequency and amplitude, and oxide-thickness. Given the intuitive expectation that LER of very short wavelengths must also have small amplitude, we have investigated the case in which the amplitude mean is inversely related to the frequency mean. We compare with the situation in which amplitude and frequency mean are unrelated. Given also that the gate perimeter may consist of different LER signature for each side, we have extended our analysis to the case when the LER statistical difference between gate sides is moderate, as well as when it is significantly large.

Thermal Analysis of AlGaN/GaN High-Electron-Mobility Transistor and Its RF Power Efficiency Optimization with Source-Bridged Field-Plate Structure.

PubMed

Kwak, Hyeon-Tak; Chang, Seung-Bo; Jung, Hyun-Gu; Kim, Hyun-Seok

2018-09-01

In this study, we consider the relationship between the temperature in a two-dimensional electron gas (2-DEG) channel layer and the RF characteristics of an AlGaN/GaN high-electron-mobility transistor by changing the geometrical structure of the field-plate. The final goal is to achieve a high power efficiency by decreasing the channel layer temperature. First, simulations were performed to compare and contrast the experimental data of a conventional T-gate head structure. Then, a source-bridged field-plate (SBFP) structure was used to obtain the lower junction temperature in the 2-DEG channel layer. The peak electric field intensity was reduced, and a decrease in channel temperature resulted in an increase in electron mobility. Furthermore, the gate-to-source capacitance was increased by the SBFP structure. However, under the large current flow condition, the SBFP structure had a lower maximum temperature than the basic T-gate head structure, which improved the device electron mobility. Eventually, an optimum position of the SBFP was used, which led to higher frequency responses and improved the breakdown voltages. Hence, the optimized SBFP structure can be a promising candidate for high-power RF devices.

Capacitance of graphenes

NASA Astrophysics Data System (ADS)

Young, Andrea; Dean, Cory; Meric, Inanc; Hone, Jim; Shepard, Ken; Kim, Philip

2010-03-01

Using a transfer procedure and single crystal hexagonal Boron Nitride gate dielectric, we are able to fabricate high mobility graphene devices with local top and back gates. The novel geometry of these devices allows us to measure the spatially averaged compressibility of mono- and bilayer graphene using the ``penetration field'' technique [Eisenstein, J.P. et al. Phys. Rev. Lett. 68, 674 (1992)]. In particular, we analyze the the effects of strong transverse electric fields on the compressibility of graphenes, especially as pertains to charged impurity scattering in single layer graphene and the opening of an energy gap in bilayer.

Hetero-Material Gate Doping-Less Tunnel FET and Its Misalignment Effects on Analog/RF Parameters

NASA Astrophysics Data System (ADS)

Anand, Sunny; Sarin, R. K.

2018-03-01

In this paper, with the use of a hetero-material gate technique, a tunnel field-effect transistor (TFET) subject to charge plasma technique is proposed, named as hetero-material gate doping-less tunnel FET (HMG-DLTFET) and a brief study has been done on the effects due to misalignment of the bottom gate towards drain (GMAD) and towards source (GMAS). The proposed devices provide better performance as the drive current increased by three times as compared to conventional doping-less TFET (DLTFET). The results are then analyzed and compared with conventional doped hetero-material gate double-gate tunnel FET (HMG-DGTFET). The analog/radiofrequency (RF) performance has been studied for both devices and comparative analysis has been done for different parameters such as drain current (I D), transconductance (g m), output conductance (g d), total gate capacitance (C gg) and cutoff frequency (f T). Both devices performed similarly in different misalignment configurations. When the bottom gate is perfectly aligned, the best performance is observed for both devices, but the doping-less device gives slightly more freedom for fabrication engineers as the amount of tolerance for HMG-DLTFET is better than that of HMG-DGTFET.

Actuation and transduction of resonant vibrations in GaAs/AlGaAs-based nanoelectromechanical systems containing two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shevyrin, A. A., E-mail: shevandrey@isp.nsc.ru; Pogosov, A. G.; Bakarov, A. K.

2015-05-04

Driven vibrations of a nanoelectromechanical system based on GaAs/AlGaAs heterostructure containing two-dimensional electron gas are experimentally investigated. The system represents a conductive cantilever with the free end surrounded by a side gate. We show that out-of-plane flexural vibrations of the cantilever are driven when alternating signal biased by a dc voltage is applied to the in-plane side gate. We demonstrate that these vibrations can be on-chip linearly transduced into a low-frequency electrical signal using the heterodyne down-mixing method. The obtained data indicate that the dominant physical mechanism of the vibrations actuation is capacitive interaction between the cantilever and the gate.

Advanced insulated gate bipolar transistor gate drive

DOEpatents

Short, James Evans [Monongahela, PA; West, Shawn Michael [West Mifflin, PA; Fabean, Robert J [Donora, PA

2009-08-04

A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, Tao; Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016; Xu, Ruimin

2015-06-15

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectricmore » constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.« less

Extraction of carrier mobility and interface trap density in InGaAs metal oxide semiconductor structures using gated Hall method

NASA Astrophysics Data System (ADS)

Chidambaram, Thenappan

III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for D it and mobility. Here we employ gated Hall method to quantify the D it spectrum at the high-K oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values.

Structural Modification of Organic Thin-Film Transistors for Photosensor Application

NASA Astrophysics Data System (ADS)

Jeong, Hyeon Seok; Bae, Jin-Hyuk; Lee, Hyeonju; Ndikumana, Joel; Park, Jaehoon

2018-05-01

We investigated the light response characteristics of bottom-gate/top-contact organic TFTs fabricated using pentacene and polystyrene as an organic semiconductor and a polymeric insulator, respectively. The pentacene TFT with overlaps (50 μm) between the source and gate electrodes as well as between the drain and gate electrodes exhibited negligible hysteresis in its transfer characteristics upon reversal of the gate voltage sweep direction. When the TFTs were structurally modified to produce an underlap structure between the source and gate electrodes, clockwise hysteresis and a drain-current decrease were observed, which were further augmented by increasing the gate underlap (from 30 μm to 50 μm and 70 μm). Herein, these results are explained in terms of space charge formation and accumulation capacitance reduction. Importantly, we found that space charges formed under the source electrode contributed to the drain currents via light irradiation through the underlap region. Under constant bias conditions, the TFTs with gate underlap structures thus exhibited on-state drain current changes in response to light signals. In our study, an optimal photosensitivity exceeding 11 was achieved by the TFT with a 30 μm gate underlap. Consequently, we suggest that gate underlap structure modification is a viable means of implementing light responsiveness in organic TFTs.

Radiation sensors based on the generation of mobile protons in organic dielectrics.

PubMed

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Structured-gate organic field-effect transistors

NASA Astrophysics Data System (ADS)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

PubMed

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Sensitivity Enhancement of an Inductively Coupled Local Detector Using a HEMT-based Current Amplifier

PubMed Central

Qian, Chunqi; Duan, Qi; Dodd, Steve; Koretsky, Alan; Murphy-Boesch, Joe

2015-01-01

Purpose To improve the signal transmission efficiency and sensitivity of a local detection coil that is weakly inductively coupled to a larger receive coil. Methods The resonant detection coil is connected in parallel with the gate of a HEMT transistor without impedance matching. When the drain of the transistor is capacitively shunted to ground, current amplification occurs in the resonator by feedback that transforms a capacitive impedance on the transistor’s source to a negative resistance on its gate. Results High resolution images were obtained from a mouse brain using a small, 11 mm diameter surface coil that was inductively coupled to a commercial, phased array chest coil. Although the power consumption of the amplifier was only 88 µW, 14 dB gain was obtained with excellent noise performance. Conclusion An integrated current amplifier based on a High Electron Mobility Transistor (HEMT) can enhance the sensitivity of inductively coupled local detectors when weakly coupled. This amplifier enables efficient signal transmission between customized user coils and commercial clinical coils, without the need for a specialized signal interface. PMID:26192998

Self-Healing Polymer Dielectric for a High Capacitance Gate Insulator.

PubMed

Ko, Jieun; Kim, Young-Jae; Kim, Youn Sang

2016-09-14

Self-healing materials are required for development of various flexible electronic devices to repair cracks and ruptures caused by repetitive bending or folding. Specifically, a self-healing dielectric layer has huge potential to achieve healing electronics without mechanical breakdown in flexible operations. Here, we developed a high performance self-healing dielectric layer with an ionic liquid and catechol-functionalized polymer which exhibited a self-healing ability for both bulk and film states under mild self-healing conditions at 55 °C for 30 min. Due to the sufficient ion mobility of the ionic liquid in the polymer matrix, it had a high capacitance value above 1 μF/cm(2) at 20 Hz. Moreover, zinc oxide (ZnO) thin-film transistors (TFTs) with a self-healing dielectric layer exhibited a high field-effect mobility of 16.1 ± 3.07 cm(2) V(-1) s(-1) at a gate bias of 3 V. Even after repetitive self-healing of the dielectric layer from mechanical breaking, the electrical performance of the TFTs was well-maintained.

Admittance–voltage profiling of Al{sub x}Ga{sub 1−x}N/GaN heterostructures: Frequency dependence of capacitance and conductance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Köhler, K.; Pletschen, W.; Godejohann, B.

2015-11-28

Admittance–voltage profiling of Al{sub x}Ga{sub 1−x}N/GaN heterostructures was used to determine the frequency dependent capacitance and conductance of FET devices in the frequency range from 50 Hz to 1 MHz. The nominally undoped low pressure metal-organic vapor-phase epitaxy structures were grown with an Al-content of 30%. An additional 1 nm thick AlN interlayer was placed in one structure before the Al{sub 0.3}Ga{sub 0.7}N layer growth. For frequencies below 10{sup 8} Hz it is convenient to use equivalent circuits to represent electric or dielectric properties of a material, a method widely used, for example, in impedance spectroscopy. We want to emphasize the relation betweenmore » frequency dependent admittance–voltage profiling and the corresponding equivalent circuits to the complex dielectric function. Debye and Drude models are used for the description of the frequency dependent admittance profiles in a range of depletion onset of the two-dimensional electron gas. Capacitance- and conductance-frequency profiles are fitted in the entire measured range by combining both models. Based on our results, we see contributions to the two-dimensional electron gas for our samples from surface states (80%) as well as from background doping in the Al{sub 0.3}Ga{sub 0.7}N barriers (20%). The specific resistance of the layers below the gate is above 10{sup 5} Ω cm for both samples and increases with increasing negative bias, i.e., the layers below the gate are essentially depleted. We propose that the resistance due to free charge carriers, determined by the Drude model, is located between gate and drain and, because of the AlN interlayer, the resistance is lowered by a factor of about 30 if compared to the sample without an AlN layer.« less

High temperature 1 MHz capacitance-voltage method for evaluation of border traps in 4H-SiC MOS system

NASA Astrophysics Data System (ADS)

Peng, Zhao-Yang; Wang, Sheng-Kai; Bai, Yun; Tang, Yi-Dan; Chen, Xi-Ming; Li, Cheng-Zhan; Liu, Ke-An; Liu, Xin-Yu

2018-04-01

In this work, border traps located in SiO2 at different depths in 4H-SiC MOS system are evaluated by a simple and effective method based on capacitance-voltage (C-V) measurements. This method estimates the border traps between two adjacent depths through C-V measurement at various frequencies at room and elevated temperatures. By comparison of these two C-V characteristics, the correlation between time constant of border traps and temperatures is obtained. Then the border trap density is determined by integration of capacitance difference against gate voltage at the regions where border traps dominate. The results reveal that border trap concentration a few nanometers away from the interface increases exponentially towards the interface, which is in good agreement with previous work. It has been proved that high temperature 1 MHz C-V method is effective for border trap evaluation.

Common source cascode amplifiers for integrating IR-FPA applications

NASA Technical Reports Server (NTRS)

Woolaway, James T.; Young, Erick T.

1989-01-01

Space based astronomical infrared measurements present stringent performance requirements on the infrared detector arrays and their associated readout circuitry. To evaluate the usefulness of commercial CMOS technology for astronomical readout applications a theoretical and experimental evaluation was performed on source follower and common-source cascode integrating amplifiers. Theoretical analysis indicates that for conditions where the input amplifier integration capacitance is limited by the detectors capacitance the input referred rms noise electrons of each amplifier should be equivalent. For conditions of input gate limited capacitance the source follower should provide lower noise. Measurements of test circuits containing both source follower and common source cascode circuits showed substantially lower input referred noise for the common-source cascode input circuits. Noise measurements yielded 4.8 input referred rms noise electrons for an 8.5 minute integration. The signal and noise gain of the common-source cascode amplifier appears to offer substantial advantages in acheiving predicted noise levels.

Fabrication of 80-nm T-gate high indium In0.7Ga0.3As/In0.6Ga0.4As composite channels mHEMT on GaAs substrate with simple technological process

NASA Astrophysics Data System (ADS)

Xian, Ji; Xiaodong, Zhang; Weihua, Kang; Zhili, Zhang; Jiahui, Zhou; Wenjun, Xu; Qi, Li; Gongli, Xiao; Zhijun, Yin; Yong, Cai; Baoshun, Zhang; Haiou, Li

2016-02-01

An 80-nm gate length metamorphic high electron mobility transistor (mHEMT) on a GaAs substrate with high indium composite compound-channels In0.7Ga0.3 As/In0.6Ga0.4 As and an optimized grade buffer scheme is presented. High 2-DEG Hall mobility values of 10200 cm2/(V·s) and a sheet density of 3.5 × 1012 cm-2 at 300 K have been achieved. The device's T-shaped gate was made by utilizing a simple three layers electron beam resist, instead of employing a passivation layer for the T-share gate, which is beneficial to decreasing parasitic capacitance and parasitic resistance of the gate and simplifying the device manufacturing process. The ohmic contact resistance Rc is 0.2 ω·mm when using the same metal system with the gate (Pt/Ti/Pt/Au), which reduces the manufacturing cycle of the device. The mHEMT device demonstrates excellent DC and RF characteristics. The peak extrinsic transconductance of 1.1 S/mm and the maximum drain current density of 0.86 A/mm are obtained. The unity current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are 246 and 301 GHz, respectively. Project supported by the Key Laboratory of Nano-Devices and Applications, Nano-Fabrication Facility of SINANO, Chinese Academy of Sciences, the National Natural Science Foundation of China (Nos. 61274077, 61474031, 61464003), the Guangxi Natural Science Foundation (Nos. 2013GXNSFGA019003, 2013GXNSFAA019335), the National Basic Research Program of China (Nos. 2011CBA00605, 2010CB327501), the Project (No. 9140C140101140C14069), and the Innovation Project of GUET Graduate Education (Nos. GDYCSZ201448, GDYCSZ201449, YJCXS201529).

Voltage gating by molecular subunits of Na+ and K+ ion channels: higher-dimensional cubic kinetics, rate constants, and temperature

PubMed Central

2015-01-01

The structural similarity between the primary molecules of voltage-gated Na and K channels (alpha subunits) and activation gating in the Hodgkin-Huxley model is brought into full agreement by increasing the model's sodium kinetics to fourth order (m3 → m4). Both structures then virtually imply activation gating by four independent subprocesses acting in parallel. The kinetics coalesce in four-dimensional (4D) cubic diagrams (16 states, 32 reversible transitions) that show the structure to be highly failure resistant against significant partial loss of gating function. Rate constants, as fitted in phase plot data of retinal ganglion cell excitation, reflect the molecular nature of the gating transitions. Additional dimensions (6D cubic diagrams) accommodate kinetically coupled sodium inactivation and gating processes associated with beta subunits. The gating transitions of coupled sodium inactivation appear to be thermodynamically irreversible; response to dielectric surface charges (capacitive displacement) provides a potential energy source for those transitions and yields highly energy-efficient excitation. A comparison of temperature responses of the squid giant axon (apparently Arrhenius) and mammalian channel gating yields kinetic Q10 = 2.2 for alpha unit gating, whose transitions are rate-limiting at mammalian temperatures; beta unit kinetic Q10 = 14 reproduces the observed non-Arrhenius deviation of mammalian gating at low temperatures; the Q10 of sodium inactivation gating matches the rate-limiting component of activation gating at all temperatures. The model kinetics reproduce the physiologically large frequency range for repetitive firing in ganglion cells and the physiologically observed strong temperature dependence of recovery from inactivation. PMID:25867741

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.

PubMed

Wang, Binghao; Huang, Wei; Chi, Lifeng; Al-Hashimi, Mohammed; Marks, Tobin J; Facchetti, Antonio

2018-05-22

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Taehoon; Jung, Yong Chan; Seong, Sejong

The metal gate electrodes of Ni, W, and Pt have been investigated for their scavenging effect: a reduction of the GeO{sub x} interfacial layer (IL) between HfO{sub 2} dielectric and Ge substrate in metal/HfO{sub 2}/GeO{sub x}/Ge capacitors. All the capacitors were fabricated using the same process except for the material used in the metal electrodes. Capacitance-voltage measurements, scanning transmission electron microscopy, and electron energy loss spectroscopy were conducted to confirm the scavenging of GeO{sub x} IL. Interestingly, these metals are observed to remotely scavenge the interfacial layer, reducing its thickness in the order of Ni, W, and then Pt. Themore » capacitance equivalent thickness of these capacitors with Ni, W, and Pt electrodes are evaluated to be 2.7 nm, 3.0 nm, and 3.5 nm, and each final remnant physical thickness of GeO{sub x} IL layer is 1.1 nm 1.4 nm, and 1.9 nm, respectively. It is suggested that the scavenging effect induced by the metal electrodes is related to the concentration of oxygen vacancies generated by oxidation reaction at the metal/HfO{sub 2} interface.« less

Ultrathin ZnO interfacial passivation layer for atomic layer deposited ZrO2 dielectric on the p-In0.2Ga0.8As substrate

NASA Astrophysics Data System (ADS)

Liu, Chen; Lü, Hongliang; Yang, Tong; Zhang, Yuming; Zhang, Yimen; Liu, Dong; Ma, Zhenqiang; Yu, Weijian; Guo, Lixin

2018-06-01

Interfacial and electrical properties were investigated on metal-oxidesemiconductor capacitors (MOSCAPs) fabricated with bilayer ZnO/ZrO2 films by atomic layer deposition (ALD) on p-In0.2Ga0.8As substrates. The ZnO passivated In0.2Ga0.8As MOSCAPs have exhibited significantly improved capacitance-voltage (C-V) characteristics with the suppressed "stretched out" effect, increased accumulation capacitance and reduced accumulation frequency dispersion as well as the lower gate leakage current. In addition, the interface trap density (Dit) estimated by the Terman method was decreased dramatically for ZnO passivated p-In0.2Ga0.8As. The inherent mechanism is attributed to the fact that an ultrathin ZnO IPL employed by ALD prior to ZrO2 dielectric deposition can effectively suppress the formation of defect-related low-k oxides and As-As dimers at the interface, thus effectively improving the interface quality by largely removing the border traps aligned near the valence band edge of the p-In0.2Ga0.8As substrate.

Nanoelectronics and Plasma Processing---The Next 15 Years and Beyond

NASA Astrophysics Data System (ADS)

Lieberman, Michael A.

2006-10-01

The number of transistors per chip has doubled every 2 years since 1959, and this doubling will continue over the next 15 years as transistor sizes shrink. There has been a 25 million-fold decrease in cost for the same performance, and in 15 years a desktop computer will be hundreds of times more powerful than one today. Transistors now have 37 nm (120 atoms) gate lengths and 1.5 nm (5 atoms) gate oxide thicknesses. The smallest working transistor has a 5 nm (17 atoms) gate length, close to the limiting gate length, from simulations, of about 4 nm. Plasma discharges are used to fabricate hundreds of billions of these nano-size transistors on a silicon wafer. These discharges have evolved from a first generation of ``low density'' reactors capacitively driven by a single source, to a second generation of ``high density'' reactors (inductive and electron cyclotron resonance) having two rf power sources, in order to control independently the ion flux and ion bombarding energy to the substrate. A third generation of ``moderate density'' reactors, driven capacitively by one high and one low frequency rf source, is now widely used. Recently, triple frequency and combined dc/dual frequency discharges have been investigated, to further control processing characteristics, such as ion energy distributions, uniformity, and plasma etch selectivities. There are many interesting physics issues associated with these discharges, including stochastic heating of discharge electrons by dual frequency sheaths, nonlinear frequency interactions, powers supplied by the multi-frequency sources, and electromagnetic effects such as standing waves and skin effects. Beyond the 4 nm transistor limit lies a decade of further performance improvements for conventional nanoelectronics, and beyond that, a dimly-seen future of spintronics, single-electron transistors, cross-bar latches, and molecular electronics.

Effect of reducing system on capacitive behavior of reduced graphene oxide film: Application for supercapacitor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akbi, Hamdane; Yu, Lei; Wang, Bin

2015-01-15

To determine the best chemical reduction of graphene oxide film with hydriodic acid that gives maximum energy and power density, we studied the effect of two reducing systems, hydriodic acid/water and hydriodic acid/acetic acid, on the morphology and electrochemical features of reduced graphene oxide film. Using acetic acid as solvent results in high electrical conductivity (5195 S m{sup −1}), excellent specific capacitance (384 F g{sup −1}) and good cyclic stability (about 98% of its initial response after 4000 cycles). Using water as a solvent, results in an ideal capacitive behavior and excellent cyclic stability (about 6% increase of its initialmore » response after 2100 cycles). - Graphical abstract: The choice of reducing system determines the morphology and structure of the chemically reduced graphene film and, as a result, affects largely the capacitive behavior. - Highlights: • The structure of the graphene film has a pronounced effect on capacitive behavior. • The use of water/HI as reducing system results in an ideal capacitive behavior. • The use of acetic acid/HI as reducing system results in a high specific capacitance.« less

Impact of device engineering on analog/RF performances of tunnel field effect transistors

NASA Astrophysics Data System (ADS)

Vijayvargiya, V.; Reniwal, B. S.; Singh, P.; Vishvakarma, S. K.

2017-06-01

The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

Adiabatically-controlled two-qubit gates using quantum dot hybrid qubits

NASA Astrophysics Data System (ADS)

Frees, Adam; Gamble, John King; Friesen, Mark; Coppersmith, S. N.

With its recent success in experimentally performing single-qubit gates, the quantum dot hybrid qubit is an excellent candidate for two-qubit gating. Here, we propose an operational scheme which exploits the electrostatic properties of such qubits to yield a tunable effective coupling in a system with a static capacitive coupling between the dots. We then use numerically calculated fidelities to demonstrate the effect of charge noise on single- and two-qubit gates with this scheme. Finally, we show steps towards optimizing the gates fidelities, and discuss ways that the scheme could be further improved. This work was supported in part by ARO (W911NF-12-0607) (W911NF-12-R-0012), NSF (PHY-1104660), ONR (N00014-15-1-0029). The authors gratefully acknowledge support from the Sandia National Laboratories Truman Fellowship Program, which is funded by the Laboratory Directed Research and Development (LDRD) Program. Sandia is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the US Department of Energy's National Nuclear Security Administration under Contract No. DE-AC04-94AL85000.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Device and material characterization and analytic modeling of amorphous silicon thin film transistors

NASA Astrophysics Data System (ADS)

Slade, Holly Claudia

Hydrogenated amorphous silicon thin film transistors (TFTs) are now well-established as switching elements for a variety of applications in the lucrative electronics market, such as active matrix liquid crystal displays, two-dimensional imagers, and position-sensitive radiation detectors. These applications necessitate the development of accurate characterization and simulation tools. The main goal of this work is the development of a semi- empirical, analytical model for the DC and AC operation of an amorphous silicon TFT for use in a manufacturing facility to improve yield and maintain process control. The model is physically-based, in order that the parameters scale with gate length and can be easily related back to the material and device properties. To accomplish this, extensive experimental data and 2D simulations are used to observe and quantify non- crystalline effects in the TFTs. In particular, due to the disorder in the amorphous network, localized energy states exist throughout the band gap and affect all regimes of TFT operation. These localized states trap most of the free charge, causing a gate-bias-dependent field effect mobility above threshold, a power-law dependence of the current on gate bias below threshold, very low leakage currents, and severe frequency dispersion of the TFT gate capacitance. Additional investigations of TFT instabilities reveal the importance of changes in the density of states and/or back channel conduction due to bias and thermal stress. In the above threshold regime, the model is similar to the crystalline MOSFET model, considering the drift component of free charge. This approach uses the field effect mobility to take into account the trap states and must utilize the correct definition of threshold voltage. In the below threshold regime, the density of deep states is taken into account. The leakage current is modeled empirically, and the parameters are temperature dependent to 150oC. The capacitance of the TFT can be modeled using a transmission line model, which is implemented using a small signal circuit with access resistors in series with the source and drain capacitances. This correctly reproduces the frequency dispersion in the TFT. Automatic parameter extraction routines are provided and are used to test the robustness of the model on a variety of devices from different research laboratories. The results demonstrate excellent agreement, showing that the model is suitable for device design, scaling, and implementation in the manufacturing process.

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

NASA Astrophysics Data System (ADS)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

Photo-Patterned Ion Gel Electrolyte-Gated Thin Film Transistors

NASA Astrophysics Data System (ADS)

Choi, Jae-Hong; Gu, Yuanyan; Hong, Kihyun; Frisbie, C. Daniel; Lodge, Timothy P.

2014-03-01

We have developed a novel fabrication route to pattern electrolyte thin films in electrolyte-gated transistors (EGTs) using a chemically crosslinkable ABA-triblock copolymer ion gel. In the self-assembly of poly[(styrene-r-vinylbenzylazide)-b-ethylene oxide-b-(styrene-r-vinylbenzylazide)] (SOS-N3) triblock copolymer and the ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]), the azide groups of poly(styrene-r-vinylbenzylazide) (PS-N3) end-blocks in the cores can be chemically cross-linked via UV irradiation (λ = 254 nm). Impedance spectroscopy and small-angle X-ray scattering confirmed that ion transport and microstructure of the ion gel are not affected by UV cross-linking. Using this chemical cross-linking strategy, we demonstrate a photo-patterning of ion gels through a patterned mask and the fabricated electrolyte-gated thin film transistors with photo-patterned ion gels as high-capacitance gate insulators exhibited high device performance (low operation voltages and high on/off current ratios).

HIGH-k GATE DIELECTRIC: AMORPHOUS Ta/La2O3 FILMS GROWN ON Si AT LOW PRESSURE

NASA Astrophysics Data System (ADS)

Bahari, Ali; Khorshidi, Zahra

2014-09-01

In the present study, Ta/La2O3 films (La2O3 doped with Ta2O5) as a gate dielectric were prepared using a sol-gel method at low pressure. Ta/La2O3 film has some hopeful properties as a gate dielectric of logic device. The structure and morphology of Ta/La2O3 films were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM). Electrical properties of films were performed using capacitance-voltage (C-V) and current density-voltage (J-V) measurements. The optical bandgap of samples was studied by UV-visible optical absorbance measurement. The optical bandgap, Eopt, is determined from the absorbance spectra. The obtained results show that Ta/La2O3 film as a good gate dielectric has amorphous structure, good thermal stability, high dielectric constant (≈ 25), low leakage current and wide bandgap (≈ 4.7 eV).

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

High-frequency self-aligned graphene transistors with transferred gate stacks

PubMed Central

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-06-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-05-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Capacitation and Ca(2+) influx in spermatozoa: role of CNG channels and protein kinase G.

PubMed

Cisneros-Mejorado, A; Hernández-Soberanis, L; Islas-Carbajal, M C; Sánchez, D

2014-01-01

Cyclic guanosine monophosphate (cGMP) has been recently shown to modulate in vitro capacitation of mammalian spermatozoa, but the mechanisms through which it influences sperm functions have not been clarified. There are at least two targets of cGMP, cyclic nucleotide-gated (CNG) channels and cGMP-dependent protein kinase (PKG), involved in several physiological events in mammalian spermatozoa. It has been suggested that CNG channels allow the influx of Ca(2+) to cytoplasm during capacitation, whereas PKG could trigger a phosphorylation pathway which might also, indirectly, mediate calcium entry. Using the patch-clamp technique in whole-cell configuration, we showed how l-cis-Diltiazem (a CNG-channel inhibitor) and KT5823 (a PKG inhibitor) decreased significantly the amplitude of macroscopic ion currents in a dose-response manner, and decreased in vitro capacitation. The inhibition of CNG channels completely abolishes the Ca(2+) influx induced by cyclic nucleotides in mouse spermatozoa. This work suggests that the downstream cGMP pathway is required in mammalian sperm capacitation and the mechanisms involved include CNG channels and PKG, highlighting these molecules as important therapeutic targets for infertility treatments or to develop new male contraceptives. © 2013 American Society of Andrology and European Academy of Andrology.

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

Enhanced performance CCD output amplifier

DOEpatents

Dunham, Mark E.; Morley, David W.

1996-01-01

A low-noise FET amplifier is connected to amplify output charge from a che coupled device (CCD). The FET has its gate connected to the CCD in common source configuration for receiving the output charge signal from the CCD and output an intermediate signal at a drain of the FET. An intermediate amplifier is connected to the drain of the FET for receiving the intermediate signal and outputting a low-noise signal functionally related to the output charge signal from the CCD. The amplifier is preferably connected as a virtual ground to the FET drain. The inherent shunt capacitance of the FET is selected to be at least equal to the sum of the remaining capacitances.

High quality factor graphene varactors for wireless sensing applications

NASA Astrophysics Data System (ADS)

Koester, Steven J.

2011-10-01

A graphene wireless sensor concept is described. By utilizing thin gate dielectrics, the capacitance in a metal-insulator-graphene structure varies with charge concentration through the quantum capacitance effect. Simulations using realistic structural and transport parameters predict quality factors, Q, >60 at 1 GHz. When placed in series with an ideal inductor, a resonant frequency tuning ratio of 25% (54%) is predicted for sense charge densities ranging from 0.32 to 1.6 μC/cm2 at an equivalent oxide thickness of 2.0 nm (0.5 nm). The resonant frequency has a temperature sensitivity, df/dT, less than 0.025%/K for sense charge densities >0.32 μC/cm2.

Performance improvement of doped TFET by using plasma formation concept

NASA Astrophysics Data System (ADS)

Soni, Deepak; Sharma, Dheeraj; Yadav, Shivendra; Aslam, Mohd.; Sharma, Neeraj

2018-01-01

Formation of abrupt doping profile at tunneling junction for the nanoscale tunnel field effect transistor (TFET) is a critical issue for attaining improved electrical behaviour. The realization of abrupt doping profile is more difficult in the case of physically doped TFETs due to material solubility limit. In this concern, we propose a novel design of TFET. For this, P+ (source)-I (channel)-N (drain) type structure has been considered, wherein a metal electrode is deposited over the source region. In addition to this, a negative voltage is applied to the source electrode (SE). It induces the surface plasma layer of holes in the source region, which is responsible for steepness in the bands at source/channel junction and provides the advantage of higher doping in source region without any addition of the physical impurity. The proposed modification is helpful for achieving steeper band bending at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface and overcomes the issue of low ON-state current. Thus, the proposed device shows the increment of 2 decades in drain current and 252 mV reduction in threshold voltage compared with conventional device. The optimization of spacer length (LSG) between source/gate (LSG) and applied negative voltage (Vpg) over source electrode have been performed to obtain optimum drain current and threshold voltage (Vth). Further, for the suppression of ambipolar current, drain region is kept lightly doped, which reduces the ambipolar current up to level of Off state current. Moreover, in the proposed device gate electrode is underlapped for improving RF performance. It also reduces gate to drain capacitances (Cgd) and increases cut-off-frequency (fT), fmax, GBP, TFP. In addition to these, linearity analysis has been performed to validate the applicability of the device.

Voltage gating by molecular subunits of Na+ and K+ ion channels: higher-dimensional cubic kinetics, rate constants, and temperature.

PubMed

Fohlmeister, Jürgen F

2015-06-01

The structural similarity between the primary molecules of voltage-gated Na and K channels (alpha subunits) and activation gating in the Hodgkin-Huxley model is brought into full agreement by increasing the model's sodium kinetics to fourth order (m(3) → m(4)). Both structures then virtually imply activation gating by four independent subprocesses acting in parallel. The kinetics coalesce in four-dimensional (4D) cubic diagrams (16 states, 32 reversible transitions) that show the structure to be highly failure resistant against significant partial loss of gating function. Rate constants, as fitted in phase plot data of retinal ganglion cell excitation, reflect the molecular nature of the gating transitions. Additional dimensions (6D cubic diagrams) accommodate kinetically coupled sodium inactivation and gating processes associated with beta subunits. The gating transitions of coupled sodium inactivation appear to be thermodynamically irreversible; response to dielectric surface charges (capacitive displacement) provides a potential energy source for those transitions and yields highly energy-efficient excitation. A comparison of temperature responses of the squid giant axon (apparently Arrhenius) and mammalian channel gating yields kinetic Q10 = 2.2 for alpha unit gating, whose transitions are rate-limiting at mammalian temperatures; beta unit kinetic Q10 = 14 reproduces the observed non-Arrhenius deviation of mammalian gating at low temperatures; the Q10 of sodium inactivation gating matches the rate-limiting component of activation gating at all temperatures. The model kinetics reproduce the physiologically large frequency range for repetitive firing in ganglion cells and the physiologically observed strong temperature dependence of recovery from inactivation. Copyright © 2015 the American Physiological Society.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance

NASA Astrophysics Data System (ADS)

Cecil, Kanchan; Singh, Jawar

2017-01-01

Dopingless (DL) and junctionless devices have attracted attention due to their simplified fabrication process and low thermal budget requirements. Therefore, in this work, we investigated the influence of low band gap Germanium (Ge) instead of Silicon (Si) as a "Source region" material in dopingless (DL) tunnel field-effect transistor (DLTFET). We observed that the Ge source DLTFET delivers much better performance in comparison to Si DLTFET under various analog/RF figure of merits (FOMs), such as transconductance (gm), transconductance generation factor (TGF) (gm /Id), output conductance (gd), output resistance (RO), intrinsic gain (gmRO), intrinsic gate delay (τ) and RF FOMs, like unity gain frequency (fT), gain bandwidth product (GBW) along with various gate capacitances. These parameters were extracted using 2D TCAD device simulations through small signal ac analysis. Higher ION /IOFF ratio (1014) of Ge source DLTFET can reduce the dynamic as well as static power in digital circuits, while higher transconductance generation factor (gm /Id) ∼ 2287 V-1 can lower the bias power of an amplifier. Similarly, enhanced RF FOMs i.e unity gain frequency (fT) and gain bandwidth product (GBW) in Gigahertz range projects the proposed device preference for RF circuits.

Scanning gate imaging of two coupled quantum dots in single-walled carbon nanotubes.

PubMed

Zhou, Xin; Hedberg, James; Miyahara, Yoichi; Grutter, Peter; Ishibashi, Koji

2014-12-12

Two coupled single wall carbon nanotube quantum dots in a multiple quantum dot system were characterized by using a low temperature scanning gate microscopy (SGM) technique, at a temperature of 170 mK. The locations of single wall carbon nanotube quantum dots were identified by taking the conductance images of a single wall carbon nanotube contacted by two metallic electrodes. The single electron transport through single wall carbon nanotube multiple quantum dots has been observed by varying either the position or voltage bias of a conductive atomic force microscopy tip. Clear hexagonal patterns were observed in the region of the conductance images where only two sets of overlapping conductance rings are visible. The values of coupling capacitance over the total capacitance of the two dots, C(m)/C(1(2)) have been extracted to be 0.21 ∼ 0.27 and 0.23 ∼ 0.28, respectively. In addition, the interdot coupling (conductance peak splitting) has also been confirmed in both conductance image measurement and current-voltage curves. The results show that a SGM technique enables spectroscopic investigation of coupled quantum dots even in the presence of unexpected multiple quantum dots.

Single phase dynamic CMOS PLA using charge sharing technique

NASA Technical Reports Server (NTRS)

Dhong, Y. B.; Tsang, C. P.

1991-01-01

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu, E-mail: iyun@yonsei.ac.kr

2014-11-07

A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulationmore » results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.« less

Ionic liquid gating reveals trap-filled limit mobility in low temperature amorphous zinc oxide

NASA Astrophysics Data System (ADS)

Bubel, S.; Meyer, S.; Kunze, F.; Chabinyc, M. L.

2013-10-01

In low-temperature solution processed amorphous zinc oxide (a-ZnO) thin films, we show the thin film transistor (TFT) characteristics for the trap-filled limit (TFL), when the quasi Fermi energy exceeds the conduction band edge and all tail-states are filled. In order to apply gate fields that are high enough to reach the TFL, we use an ionic liquid tape gate. Performing capacitance voltage measurements to determine the accumulated charge during TFT operation, we find the TFL at biases higher than predicted by the electronic structure of crystalline ZnO. We conclude that the density of states in the conduction band of a-ZnO is higher than in its crystalline state. Furthermore, we find no indication of percolative transport in the conduction band but trap assisted transport in the tail-states of the band.

A novel high-performance high-frequency SOI MESFET by the damped electric field

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

2016-06-01

In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

I-V Characteristics of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

Extraction method of interfacial injected charges for SiC power MOSFETs

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Li, Sheng; Song, Haiyang; Chen, Xin; Li, Ting; Fang, Jiong; Sun, Weifeng

2018-01-01

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

Transmission and reflection of charge-density wave packets in a quantum Hall edge controlled by a metal gate

NASA Astrophysics Data System (ADS)

Matsuura, Masahiro; Mano, Takaaki; Noda, Takeshi; Shibata, Naokazu; Hotta, Masahiro; Yusa, Go

2018-02-01

Quantum energy teleportation (QET) is a proposed protocol related to quantum vacuum. The edge channels in a quantum Hall system are well suited for the experimental verification of QET. For this purpose, we examine a charge-density wave packet excited and detected by capacitively coupled front gate electrodes. We observe the waveform of the charge packet, which is proportional to the time derivative of the applied square voltage wave. Further, we study the transmission and reflection behaviors of the charge-density wave packet by applying a voltage to another front gate electrode to control the path of the edge state. We show that the threshold voltages where the dominant direction is switched in either transmission or reflection for dense and sparse wave packets are different from the threshold voltage where the current stops flowing in an equilibrium state.

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

NASA Technical Reports Server (NTRS)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Exceptionally High Electric Double Layer Capacitances of Oligomeric Ionic Liquids.

PubMed

Matsumoto, Michio; Shimizu, Sunao; Sotoike, Rina; Watanabe, Masayoshi; Iwasa, Yoshihiro; Itoh, Yoshimitsu; Aida, Takuzo

2017-11-15

Electric double layer (EDL) capacitors are promising as next-generation energy accumulators if their capacitances and operation voltages are both high. However, only few electrolytes can simultaneously fulfill these two requisites. Here we report that an oligomeric ionic liquid such as IL4 TFSI with four imidazolium ion units in its structure provides a wide electrochemical window of ∼5.0 V, similar to monomeric ionic liquids. Furthermore, electrochemical impedance measurements using Au working electrodes demonstrated that IL4 TFSI exhibits an exceptionally high EDL capacitance of ∼66 μF/cm 2 , which is ∼6 times as high as those of monomeric ionic liquids so far reported. We also found that an EDL-based field effect transistor (FET) using IL4 TFSI as a gate dielectric material and SrTiO 3 as a channel material displays a very sharp transfer curve with an enhanced carrier accumulation capability of ∼64 μF/cm 2 , as determined by Hall-effect measurements.

Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs

NASA Astrophysics Data System (ADS)

Pi-Ho Hu, Vita; Chiu, Pin-Chieh

2018-04-01

The impact of device parameters on the switching characteristics of negative capacitance ultra-thin-body (UTB) germanium-on-insulator (NC-GeOI) MOSFETs is analyzed. NC-GeOI MOSFETs with smaller gate length (L g), EOT, and buried oxide thickness (T box) and thicker ferroelectric layer thickness (T FE) exhibit larger subthreshold swing improvements over GeOI MOSFETs due to better capacitance matching. Compared with GeOI MOSFETs, NC-GeOI MOSFETs exhibit better switching time due to improvements in effective drive current (I eff) and subthreshold swing. NC-GeOI MOSFET exhibits larger ST improvements at V dd = 0.3 V (-82.9%) than at V dd = 0.86 V (-9.7%), because NC-GeOI MOSFET shows 18.2 times higher I eff than the GeOI MOSFET at V dd = 0.3 V, while 2.5 times higher I eff at V dd = 0.86 V. This work provides the device design guideline of NC-GeOI MOSFETs for ultra-low power applications.

Opening of K+ channels by capacitive stimulation from silicon chip

NASA Astrophysics Data System (ADS)

Ulbrich, M. H.; Fromherz, P.

2005-10-01

The development of stable neuroelectronic systems requires a stimulation of nerve cells from semiconductor devices without electrochemical effects at the electrolyte/solid interface and without damage of the cell membrane. The interaction must rely on a reversible opening of voltage-gated ion channels by capacitive coupling. In a proof-of-principle experiment, we demonstrate that Kv1.3 potassium channels expressed in HEK293 cells can be opened from an electrolyte/oxide/silicon (EOS) capacitor. A sufficient strength of electrical coupling is achieved by insulating silicon with a thin film of TiO2 to achieve a high capacitance and by removing NaCl from the electrolyte to enhance the resistance of the cell-chip contact. When a decaying voltage ramp is applied to the EOS capacitor, an outward current through the attached cell membrane is observed that is specific for Kv1.3 channels. An open probability up to fifty percent is estimated by comparison with a numerical simulation of the cell-chip contact.

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

Nonvolatile floating gate organic memory device based on pentacene/CdSe quantum dot heterojuction

NASA Astrophysics Data System (ADS)

Shin, Ik-Soo; Kim, Jung-Min; Jeun, Jun-Ho; Yoo, Seok-Hyun; Ge, Ziyi; Hong, Jong-In; Ho Bang, Jin; Kim, Yong-Sang

2012-04-01

An organic floating-gate memory device using CdSe quantum dots (QDs) as a charge-trapping element was fabricated. CdSe QDs were localized beneath a pentacene without any tunneling insulator, and the QD layer played a role as hole-trapping sites. The band bending formed at the junction between pentacene and QD layers inhibited back-injection of holes trapped in CdSe into pentacene, which appeared as a hysteretic capacitance-voltage response during the operation of the device. Nearly, 60% of trapped charge was sustained even after 104 s in programmed state, and this long retention time can be potentially useful in practical applications of non-volatile memory.

Full-range electrical characteristics of WS{sub 2} transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, Jatinder; Bellus, Matthew Z.; Chiu, Hsin-Ying, E-mail: chiu@ku.edu

We fabricated transistors formed by few layers to bulk single crystal WS{sub 2} to quantify the factors governing charge transport. We established a capacitor network to analyze the full-range electrical characteristics of the channel, highlighting the role of quantum capacitance and interface trap density. We find that the transfer characteristics are mainly determined by the interplay between quantum and oxide capacitances. In the OFF-state, the interface trap density (<10{sup 12} cm{sup –2}) is a limiting factor for the subthreshold swing. Furthermore, the superior crystalline quality and the low interface trap density enabled the subthreshold swing to approach the theoretical limit onmore » a back-gated device on SiO{sub 2}/Si substrate.« less

Measurement of the quantum capacitance from two-dimensional surface state of a topological insulator at room temperature

NASA Astrophysics Data System (ADS)

Choi, Hyunwoo; Kim, Tae Geun; Shin, Changhwan

2017-06-01

A topological insulator (TI) is a new kind of material that exhibits unique electronic properties owing to its topological surface state (TSS). Previous studies focused on the transport properties of the TSS, since it can be used as the active channel layer in metal-oxide-semiconductor field-effect transistors (MOSFETs). However, a TI with a negative quantum capacitance (QC) effect can be used in the gate stack of MOSFETs, thereby facilitating the creation of ultra-low power electronics. Therefore, it is important to study the physics behind the QC in TIs in the absence of any external magnetic field, at room temperature. We fabricated a simple capacitor structure using a TI (TI-capacitor: Au-TI-SiO2-Si), which shows clear evidence of QC at room temperature. In the capacitance-voltage (C-V) measurement, the total capacitance of the TI-capacitor increases in the accumulation regime, since QC is the dominant capacitive component in the series capacitor model (i.e., CT-1 = CQ-1 + CSiO2-1). Based on the QC model of the two-dimensional electron systems, we quantitatively calculated the QC, and observed that the simulated C-V curve theoretically supports the conclusion that the QC of the TI-capacitor is originated from electron-electron interaction in the two-dimensional surface state of the TI.

A gating grid driver for time projection chambers

NASA Astrophysics Data System (ADS)

Tangwancharoen, S.; Lynch, W. G.; Barney, J.; Estee, J.; Shane, R.; Tsang, M. B.; Zhang, Y.; Isobe, T.; Kurata-Nishimura, M.; Murakami, T.; Xiao, Z. G.; Zhang, Y. F.; SπRIT Collaboration

2017-05-01

A simple but novel driver system has been developed to operate the wire gating grid of a Time Projection Chamber (TPC). This system connects the wires of the gating grid to its driver via low impedance transmission lines. When the gating grid is open, all wires have the same voltage allowing drift electrons, produced by the ionization of the detector gas molecules, to pass through to the anode wires. When the grid is closed, the wires have alternating higher and lower voltages causing the drift electrons to terminate at the more positive wires. Rapid opening of the gating grid with low pickup noise is achieved by quickly shorting the positive and negative wires to attain the average bias potential with N-type and P-type MOSFET switches. The circuit analysis and simulation software SPICE shows that the driver restores the gating grid voltage to 90% of the opening voltage in less than 0.20 μs, for small values of the termination resistors. When tested in the experimental environment of a time projection chamber larger termination resistors were chosen so that the driver opens the gating grid in 0.35 μs. In each case, opening time is basically characterized by the RC constant given by the resistance of the switches and terminating resistors and the capacitance of the gating grid and its transmission line. By adding a second pair of N-type and P-type MOSFET switches, the gating grid is closed by restoring 99% of the original charges to the wires within 3 μs.

Molecule counting with alkanethiol and DNA immobilized on gold microplates for extended gate FET.

PubMed

Cao, Zhong; Xiao, Zhong-Liang; Zhang, Ling; Luo, Dong-Mei; Kamahori, Masao; Shimoda, Maki

2013-04-01

Several molecule counting methods based on electrochemical characterization of alkanethiol and thiolated single-stranded oligonucleotide (HS-ssDNA) immobilized on gold microplates, which were used as extended gates of field effect transistors (FETs), have been investigated in this paper. The surface density of alkanethiol and DNA monolayers on gold microplates were quantitatively evaluated from the reductive desorption charge by using cyclic voltammetry (CV) and fast CV (FCV) methods in strong alkali solution. Typically, the surface density of 6-hydroxy-1-hexanethiol (6-HHT) was evaluated to be 4.639 molecules/nm(2), and the 28 base-pair dsDNA about 1.226-4.849 molecules/100 nm(2) on Au microplates after post-treatment with 6-HHT. The behaviors on surface potential and capacitance of different aminoalkanethiols on Au microplates were measured in 0.1 mol/L Na2SO4 and 10 mmol/L Tris-HCl (pH=7.4) solutions, indicating that the surface potential increases and the double-layer capacitance decreases with the length of carbon chain increased for the thiol monolayers, which obey a physics relationship for a capacitor. Comparably, a simple sensing method based on the electronic signals of biochemical reaction events on DNA immobilization and hybridization at the Au surface of the extended gate FET (EGFET) was developed, with which the surface density of the hybridized dsDNA on the gold surface of the EGFET was evaluated to be 1.36 molecules per 100 nm(2), showing that the EGFET is a promising sensing biochip for DNA molecule counting. Copyright © 2012 Elsevier B.V. All rights reserved.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Efficient Multi-Dimensional Simulation of Quantum Confinement Effects in Advanced MOS Devices

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Rafferty, Conor S.; Ancona, Mario G.; Yu, Zhi-Ping

2000-01-01

We investigate the density-gradient (DG) transport model for efficient multi-dimensional simulation of quantum confinement effects in advanced MOS devices. The formulation of the DG model is described as a quantum correction to the classical drift-diffusion model. Quantum confinement effects are shown to be significant in sub-100nm MOSFETs. In thin-oxide MOS capacitors, quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion or quantum effects in simulations dramatically improves the match between C-V simulations and measurements for oxide thickness down to 2 nm. Significant quantum corrections also occur in the I-V characteristics of short-channel (30 to 100 nm) n-MOSFETs, with current drive reduced by up to 70%. This effect is shown to result from reduced inversion charge due to quantum confinement of electrons in the channel. Also, subthreshold slope is degraded by 15 to 20 mV/decade with the inclusion of quantum effects via the density-gradient model, and short channel effects (in particular, drain-induced barrier lowering) are noticeably increased.

Increasing Linear Dynamic Range of a CMOS Image Sensor

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

A generic design and a corresponding operating sequence have been developed for increasing the linear-response dynamic range of a complementary metal oxide/semiconductor (CMOS) image sensor. The design provides for linear calibrated dual-gain pixels that operate at high gain at a low signal level and at low gain at a signal level above a preset threshold. Unlike most prior designs for increasing dynamic range of an image sensor, this design does not entail any increase in noise (including fixed-pattern noise), decrease in responsivity or linearity, or degradation of photometric calibration. The figure is a simplified schematic diagram showing the circuit of one pixel and pertinent parts of its column readout circuitry. The conventional part of the pixel circuit includes a photodiode having a small capacitance, CD. The unconventional part includes an additional larger capacitance, CL, that can be connected to the photodiode via a transfer gate controlled in part by a latch. In the high-gain mode, the signal labeled TSR in the figure is held low through the latch, which also helps to adapt the gain on a pixel-by-pixel basis. Light must be coupled to the pixel through a microlens or by back illumination in order to obtain a high effective fill factor; this is necessary to ensure high quantum efficiency, a loss of which would minimize the efficacy of the dynamic- range-enhancement scheme. Once the level of illumination of the pixel exceeds the threshold, TSR is turned on, causing the transfer gate to conduct, thereby adding CL to the pixel capacitance. The added capacitance reduces the conversion gain, and increases the pixel electron-handling capacity, thereby providing an extension of the dynamic range. By use of an array of comparators also at the bottom of the column, photocharge voltages on sampling capacitors in each column are compared with a reference voltage to determine whether it is necessary to switch from the high-gain to the low-gain mode. Depending upon the built-in offset in each pixel and in each comparator, the point at which the gain change occurs will be different, adding gain-dependent fixed pattern noise in each pixel. The offset, and hence the fixed pattern noise, is eliminated by sampling the pixel readout charge four times by use of four capacitors (instead of two such capacitors as in conventional design) connected to the bottom of the column via electronic switches SHS1, SHR1, SHS2, and SHR2, respectively, corresponding to high and low values of the signals TSR and RST. The samples are combined in an appropriate fashion to cancel offset-induced errors, and provide spurious-free imaging with extended dynamic range.

DC and analog/RF performance optimisation of source pocket dual work function TFET

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Sharma, Dheeraj; Kondekar, Pravin; Nigam, Kaushal; Baronia, Sagar

2017-12-01

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n+ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.

A linkage analysis toolkit for studying allosteric networks in ion channels

PubMed Central

2013-01-01

A thermodynamic approach to studying allosterically regulated ion channels such as the large-conductance voltage- and Ca2+-dependent (BK) channel is presented, drawing from principles originally introduced to describe linkage phenomena in hemoglobin. In this paper, linkage between a principal channel component and secondary elements is derived from a four-state thermodynamic cycle. One set of parallel legs in the cycle describes the “work function,” or the free energy required to activate the principal component. The second are “lever operations” activating linked elements. The experimental embodiment of this linkage cycle is a plot of work function versus secondary force, whose asymptotes are a function of the parameters (displacements and interaction energies) of an allosteric network. Two essential work functions play a role in evaluating data from voltage-clamp experiments. The first is the conductance Hill energy WH[g], which is a “local” work function for pore activation, and is defined as kT times the Hill transform of the conductance (G-V) curve. The second is the electrical capacitance energy WC[q], representing “global” gating charge displacement, and is equal to the product of total gating charge per channel times the first moment (VM) of normalized capacitance (slope of Q-V curve). Plots of WH[g] and WC[q] versus voltage and Ca2+ potential can be used to measure thermodynamic parameters in a model-independent fashion of the core gating constituents (pore, voltage-sensor, and Ca2+-binding domain) of BK channel. The method is easily generalized for use in studying other allosterically regulated ion channels. The feasibility of performing linkage analysis from patch-clamp data were explored by simulating gating and ionic currents of a 17-particle model BK channel in response to a slow voltage ramp, which yielded interaction energies deviating from their given values in the range of 1.3 to 7.2%. PMID:23250867

SLO3 auxiliary subunit LRRC52 controls gating of sperm KSPER currents and is critical for normal fertility

PubMed Central

Zeng, Xu-Hui; Yang, Chengtao; Xia, Xiao-Ming; Liu, Min; Lingle, Christopher J.

2015-01-01

Following entry into the female reproductive tract, mammalian sperm undergo a maturation process termed capacitation that results in competence to fertilize ova. Associated with capacitation is an increase in membrane conductance to both Ca2+ and K+, leading to an elevation in cytosolic Ca2+ critical for activation of hyperactivated swimming motility. In mice, the Ca2+ conductance (alkalization-activated Ca2+-permeable sperm channel, CATSPER) arises from an ensemble of CATSPER subunits, whereas the K+ conductance (sperm pH-regulated K+ current, KSPER) arises from a pore-forming ion channel subunit encoded by the slo3 gene (SLO3) subunit. In the mouse, both CATSPER and KSPER are activated by cytosolic alkalization and a concerted activation of CATSPER and KSPER is likely a common facet of capacitation-associated increases in Ca2+ and K+ conductance among various mammalian species. The properties of heterologously expressed mouse SLO3 channels differ from native mouse KSPER current. Recently, a potential KSPER auxiliary subunit, leucine-rich-repeat-containing protein 52 (LRRC52), was identified in mouse sperm and shown to shift gating of SLO3 to be more equivalent to native KSPER. Here, we show that genetic KO of LRRC52 results in mice with severely impaired fertility. Activation of KSPER current in sperm lacking LRRC52 requires more positive voltages and higher pH than for WT KSPER. These results establish a critical role of LRRC52 in KSPER channels and demonstrate that loss of a non-pore-forming auxiliary subunit results in severe fertility impairment. Furthermore, through analysis of several genotypes that influence KSPER current properties we show that in vitro fertilization competence correlates with the net KSPER conductance available for activation under physiological conditions. PMID:25675513

Vascular capacitance and cardiac output in pacing-induced canine models of acute and chronic heart failure.

PubMed

Ogilvie, R I; Zborowska-Sluis, D

1995-11-01

The relationship between stressed and total blood volume, total vascular capacitance, central blood volume, cardiac output (CO), and pulmonary capillary wedge pressure (Ppcw) was investigated in pacing-induced acute and chronic heart failure. Acute heart failure was induced in anesthetized splenectomized dogs by a volume load (20 mL/kg over 10 min) during rapid right ventricular pacing at 250 beats/min (RRVP) for 60 min. Chronic heart failure was induced by continuous RRVP for 2-6 weeks (average 24 +/- 2 days). Total vascular compliance and capacitance were calculated from the mean circulatory filling pressure (Pmcf) during transient circulatory arrest after acetylcholine at three different circulating volumes. Stressed blood volume was calculated as a product of compliance and Pmcf, with the total blood volume measured by a dye dilution. Central blood volume (CBV) and CO were measured by thermodilution. Central (heart and lung) vascular capacitance was estimated from the plot of Ppcw against CBV. Acute volume loading without RRVP increased capacitance and CO, whereas after volume loading with RRVP, capacitance and CO were unaltered from baseline. Chronic RRVP reduced capacitance and CO. All interventions, volume +/- RRVP or chronic RRVP, increased stressed and central blood volumes and Ppcw. Acute or chronic RRVP reduced central vascular capacitance. Cardiac output was increased when stressed and unstressed blood volumes increased proportionately as during volume loading alone. When CO was reduced and Ppcw increased, as during chronic RRVP or acute RRVP plus a volume load, stressed blood volume was increased and unstressed blood volume was decreased. Thus, interventions that reduced CO and increased Ppcw also increased stressed and reduced unstressed blood volume and total vascular capacitance.

Transient digitizer with displacement current samplers

DOEpatents

McEwan, T.E.

1996-05-21

A low component count, high speed sample gate, and digitizer architecture using the sample gates is based on use of a signal transmission line, a strobe transmission line and a plurality of sample gates connected to the sample transmission line at a plurality of positions. The sample gates include a strobe pickoff structure near the strobe transmission line which generates a charge displacement current in response to propagation of the strobe signal on the strobe transmission line sufficient to trigger the sample gate. The sample gate comprises a two-diode sampling bridge and is connected to a meandered signal transmission line at one end and to a charge-holding cap at the other. The common cathodes are reverse biased. A voltage step is propagated down the strobe transmission line. As the step propagates past a capacitive pickoff, displacement current i=c(dv/dT), flows into the cathodes, driving the bridge into conduction and thereby charging the charge-holding capacitor to a value related to the signal. A charge amplifier converts the charge on the charge-holding capacitor to an output voltage. The sampler is mounted on a printed circuit board, and the sample transmission line and strobe transmission line comprise coplanar microstrips formed on a surface of the substrate. Also, the strobe pickoff structure may comprise a planar pad adjacent the strobe transmission line on the printed circuit board. 16 figs.

Transient digitizer with displacement current samplers

DOEpatents

McEwan, Thomas E.

1996-01-01

A low component count, high speed sample gate, and digitizer architecture using the sample gates is based on use of a signal transmission line, a strobe transmission line and a plurality of sample gates connected to the sample transmission line at a plurality of positions. The sample gates include a strobe pickoff structure near the strobe transmission line which generates a charge displacement current in response to propagation of the strobe signal on the strobe transmission line sufficient to trigger the sample gate. The sample gate comprises a two-diode sampling bridge and is connected to a meandered signal transmission line at one end and to a charge-holding cap at the other. The common cathodes are reverse biased. A voltage step is propagated down the strobe transmission line. As the step propagates past a capacitive pickoff, displacement current i=c(dv/dT), flows into the cathodes, driving the bridge into conduction and thereby charging the charge-holding capacitor to a value related to the signal. A charge amplifier converts the charge on the charge-holding capacitor to an output voltage. The sampler is mounted on a printed circuit board, and the sample transmission line and strobe transmission line comprise coplanar microstrips formed on a surface of the substrate. Also, the strobe pickoff structure may comprise a planar pad adjacent the strobe transmission line on the printed circuit board.

Electron Transporting Semiconductor Dielectric Intramolecular

DTIC Science & Technology

2012-04-27

gate dielectric, and the capacitance times mobility was 80 nS/V (10x typical pentacene /oxide), stable to heating to 70 °C in air. Remarkably...oxide/ Pentacene Bilayer Transistors: High Mobility n-Channel, Ambipolar and Nonvolatile Devices” Adv. Funct. Mater. 18, 1832-1839 (2008) Sun, J...case of layered OSC OFETs. This proposal is somewhat different from a model by deLeeuw for amorphous OFETs13 in which carriers would be locally

Sensitivity Enhancement of an Inductively Coupled Local Detector Using a HEMT-Based Current Amplifier.

PubMed

Qian, Chunqi; Duan, Qi; Dodd, Steve; Koretsky, Alan; Murphy-Boesch, Joe

2016-06-01

To improve the signal transmission efficiency and sensitivity of a local detection coil that is weakly inductively coupled to a larger receive coil. The resonant detection coil is connected in parallel with the gate of a high electron mobility transistor (HEMT) transistor without impedance matching. When the drain of the transistor is capacitively shunted to ground, current amplification occurs in the resonator by feedback that transforms a capacitive impedance on the transistor's source to a negative resistance on its gate. High resolution images were obtained from a mouse brain using a small, 11 mm diameter surface coil that was inductively coupled to a commercial, phased array chest coil. Although the power consumption of the amplifier was only 88 μW, 14 dB gain was obtained with excellent noise performance. An integrated current amplifier based on a HEMT can enhance the sensitivity of inductively coupled local detectors when weakly coupled. This amplifier enables efficient signal transmission between customized user coils and commercial clinical coils, without the need for a specialized signal interface. Magn Reson Med 75:2573-2578, 2016. Published 2015. This article is a U.S. Government work and is in the public domain in the USA. Published 2015 This article is a U.S. Government work and is in the public domain in the USA.

Analysis of amorphous indium-gallium-zinc-oxide thin-film transistor contact metal using Pilling-Bedworth theory and a variable capacitance diode model

NASA Astrophysics Data System (ADS)

Kiani, Ahmed; Hasko, David G.; Milne, William I.; Flewitt, Andrew J.

2013-04-01

It is widely reported that threshold voltage and on-state current of amorphous indium-gallium-zinc-oxide bottom-gate thin-film transistors are strongly influenced by the choice of source/drain contact metal. Electrical characterisation of thin-film transistors indicates that the electrical properties depend on the type and thickness of the metal(s) used. Electron transport mechanisms and possibilities for control of the defect state density are discussed. Pilling-Bedworth theory for metal oxidation explains the interaction between contact metal and amorphous indium-gallium-zinc-oxide, which leads to significant trap formation. Charge trapping within these states leads to variable capacitance diode-like behavior and is shown to explain the thin-film transistor operation.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

Surface potential based modeling of charge, current, and capacitances in DGTFET including mobile channel charge and ambipolar behaviour

NASA Astrophysics Data System (ADS)

Jain, Prateek; Yadav, Chandan; Agarwal, Amit; Chauhan, Yogesh Singh

2017-08-01

We present a surface potential based analytical model for double gate tunnel field effect transistor (DGTFET) for the current, terminal charges, and terminal capacitances. The model accounts for the effect of the mobile charge in the channel and captures the device physics in depletion as well as in the strong inversion regime. The narrowing of the tunnel barrier in the presence of mobile charges in the channel is incorporated via modeling of the inverse decay length, which is constant under channel depletion condition and bias dependent under inversion condition. To capture the ambipolar current behavior in the model, tunneling at the drain junction is also included. The proposed model is validated against TCAD simulation data and it shows close match with the simulation data.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

PubMed

Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer

NASA Astrophysics Data System (ADS)

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-01

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd)4Ti3O12 films as insulator, and HfO2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO2 defect control layer shows a low leakage current density of 3.1 × 10-9 A/cm2 at a gate voltage of - 3 V.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer.

PubMed

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-27

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd) 4 Ti 3 O 12 films as insulator, and HfO 2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO 2 defect control layer shows a low leakage current density of 3.1 × 10 -9  A/cm 2 at a gate voltage of - 3 V.

SiO 2/SiC interface proved by positron annihilation

NASA Astrophysics Data System (ADS)

Maekawa, M.; Kawasuso, A.; Yoshikawa, M.; Itoh, H.

2003-06-01

We have studied positron annihilation in a Silicon carbide (SiC)-metal/oxide/semiconductor (MOS) structure using a monoenergetic positron beam. The Doppler broadening of annihilation quanta were measured as functions of the incident positron energy and the gate bias. Applying negative gate bias, significant increases in S-parameters were observed. This indicates the migration of implanted positrons towards SiO 2/SiC interface and annihilation at open-volume type defects. The behavior of S-parameters depending on the bias voltage was well correlated with the capacitance-voltage ( C- V) characteristics. We observed higher S-parameters and the interfacial trap density in MOS structures fabricated using the dry oxidation method as compared to those by pyrogenic oxidation method.

Temperature dependent DC characterization of InAlN/(AlN)/GaN HEMT for improved reliability

NASA Astrophysics Data System (ADS)

Takhar, K.; Gomes, U. P.; Ranjan, K.; Rathi, S.; Biswas, D.

2015-02-01

InxAl1-xN/AlN/GaN HEMT device performance is analysed at various temperatures with the help of physics based 2-D simulation using commercially available BLAZE and GIGA modules from SILVACO. Various material parameters viz. band-gap, low field mobility, density of states, velocity saturation, and substrate thermal conductivity are considered as critical parameters for predicting temperature effect in InxAl1-xN/AlN/GaN HEMT. Reduction in drain current and transconductance has been observed due to the decrease of 2-DEG mobility and effective electron velocity with the increase in temperature. Degradation in cut-off frequency follows the transconductance profile as variation in gate-source/gate-drain capacitances observed very small.

Trielectrode capacitive pressure transducer

NASA Technical Reports Server (NTRS)

Coon, G. W. (Inventor)

1976-01-01

A capacitive transducer and circuit especially suited for making measurements in a high-temperature environment are described. The transducer includes two capacitive electrodes and a shield electrode. As the temperature of the transducer rises, the resistance of the insulation between the capacitive electrode decreases and a resistive current attempts to interfere with the capacitive current between the capacitive electrodes. The shield electrode and the circuit coupled there reduce the resistive current in the transducer. A bridge-type circuit coupled to the transducer ignores the resistive current and measures only the capacitive current flowing between the capacitive electrodes.

Scaling and application of commercial, feature-rich, modular mixed-signal technology platforms for large format ROICs

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Racanelli, Marco; Howard, David; Miyagi, Glenn; Bowler, Mark; Jordan, Scott; Zhang, Tao; Krieger, William

2010-04-01

Today's modular, mixed-signal CMOS process platforms are excellent choices for manufacturing of highly integrated, large-format read out integrated circuits (ROICs). Platform features, that can be used for both cooled and un-cooled ROIC applications, can include (1) quality passives such as 4fFμm2 stacked MIM capacitors for linearity and higher density capacitance per pixel, 1kOhm high-value poly-silicon resistors, 2.8μm thick metals for efficient power distribution and reduced I-R drop; (2) analog active devices such as low noise single gate 3.3V, and 1.8V/3.3V or 1.8V/5V dual gate configurations, 40V LDMOS FETs, and NPN and PNP devices, deep n-well for substrate isolation for analog blocks and digital logic; (3) tools to assist the circuit designer such as models for cryogenic temperatures, CAD assistance for metal density uniformity determination, statistical, X-sigma and PCM-based models for corner validation and to simulate design sensitivity, and (4) sub-field stitching for large die. The TowerJazz platform of technology for 0.50μm, 0.25μm and 0.18μm CMOS nodes, with features as described above, is described in detail in this paper.

Statistical evaluation of metal fill widths for emulated metal fill in parasitic extraction methodology

NASA Astrophysics Data System (ADS)

J-Me, Teh; Noh, Norlaili Mohd.; Aziz, Zalina Abdul

2015-05-01

In the chip industry today, the key goal of a chip development organization is to develop and market chips within a short time frame to gain foothold on market share. This paper proposes a design flow around the area of parasitic extraction to improve the design cycle time. The proposed design flow utilizes the usage of metal fill emulation as opposed to the current flow which performs metal fill insertion directly. By replacing metal fill structures with an emulation methodology in earlier iterations of the design flow, this is targeted to help reduce runtime in fill insertion stage. Statistical design of experiments methodology utilizing the randomized complete block design was used to select an appropriate emulated metal fill width to improve emulation accuracy. The experiment was conducted on test cases of different sizes, ranging from 1000 gates to 21000 gates. The metal width was varied from 1 x minimum metal width to 6 x minimum metal width. Two-way analysis of variance and Fisher's least significant difference test were used to analyze the interconnect net capacitance values of the different test cases. This paper presents the results of the statistical analysis for the 45 nm process technology. The recommended emulated metal fill width was found to be 4 x the minimum metal width.

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate.

PubMed

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Yang, Zhaonian

2017-12-01

In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N + pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g  = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate

NASA Astrophysics Data System (ADS)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Yang, Zhaonian

2017-03-01

In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.

Enhanced two dimensional electron gas transport characteristics in Al2O3/AlInN/GaN metal-oxide-semiconductor high-electron-mobility transistors on Si substrate

NASA Astrophysics Data System (ADS)

Freedsman, J. J.; Watanabe, A.; Urayama, Y.; Egawa, T.

2015-09-01

The authors report on Al2O3/Al0.85In0.15N/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor (MOS-HEMT) on Si fabricated by using atomic layer deposited Al2O3 as gate insulator and passivation layer. The MOS-HEMT with the gate length of 2 μm exhibits excellent direct-current (dc) characteristics with a drain current maximum of 1270 mA/mm at a gate bias of 3 V and an off-state breakdown voltage of 180 V for a gate-drain spacing of 4 μm. Also, the 1 μm-gate MOS-HEMT shows good radio-frequency (rf) response such as current gain and maximum oscillation cut-off frequencies of 10 and 34 GHz, respectively. The capacitance-voltage characteristics at 1 MHz revealed significant increase in two-dimensional electron gas (2DEG) density for the MOS-HEMT compared to conventional Schottky barrier HEMTs. Analyses using drain-source conductivity measurements showed improvements in 2DEG transport characteristics for the MOS-HEMT. The enhancements in dc and rf performances of the Al2O3/Al0.85In0.15N/GaN MOS-HEMT are attributed to the improvements in 2DEG characteristics.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Negative Capacitance in BaTiO3/BiFeO3 Bilayer Capacitors.

PubMed

Hou, Ya-Fei; Li, Wei-Li; Zhang, Tian-Dong; Yu, Yang; Han, Ren-Lu; Fei, Wei-Dong

2016-08-31

Negative capacitances provide an approach to reduce heat generations in field-effect transistors during the switch processes, which contributes to further miniaturization of the conventional integrated circuits. Although there are many studies about negative capacitances using ferroelectric materials, the direct observation of stable ferroelectric negative capacitances has rarely been reported. Here, we put forward a dc bias assistant model in bilayer capacitors, where one ferroelectric layer with large dielectric constant and the other ferroelectric layer with small dielectric constant are needed. Negative capacitances can be obtained when external dc bias electric fields are larger than a critical value. Based on the model, BaTiO3/BiFeO3 bilayer capacitors are chosen as study objects, and negative capacitances are observed directly. Additionally, the upward self-polarization effect in the ferroelectric layer reduces the critical electric field, which may provide a method for realizing zero and/or small dc bias assistant negative capacitances.

Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation

NASA Astrophysics Data System (ADS)

Singh, Gurmeet; Amin, S. Intekhab; Anand, Sunny; Sarin, R. K.

2016-04-01

In this work, the performance comparison of two heterojunction PIN TFETs having Si channel and Si0.5Ge0.5 source with high-k (SiGe DGTFET HK) and hetero-gate dielectric (SiGe DGTFET HG) respectively with those of two homojunction Si based PIN (DGTFET HK and DGTFET HG) TFETs is performed. Similarly, by employing the technique of pocketing at source junction in above four PIN TFETs, the performances of resultant four PNPN TFETs (SiGe PNPN DGTFET HK, SiGe PNPN DGTFET HG, PNPN DGTFET HK and PNPN DGTFET HG) are also compared with each other. Due to lower tunnel resistance of SiGe based heterojunction PIN and PNPN TFETs, the DC parameters such as ON current, ON-OFF current ratio, average subthreshold slope are improved significantly as compared to Si based PIN and PNPN TFETs respectively. The output characteristics of HG architectures in Si based homojunction PIN and PNPN TFETs is observed to be identical to with respective Si based HK PIN and PNPN TFET architectures. However, the output characteristics of HG architectures in SiGe based heterojunction PIN and PNPN TFETs degrade as compared to their respective SiGe based HK PIN and PNPN TFET architectures. In ON state, SiGe based HK and HG PIN and PNPN TFETs have lower gate capacitance (Cgg) as compared to their respective Si based HK and HG PIN and PNPN TFETs. Moreover, HG architecture suppresses gate to drain capacitance (Cgd) and ambipolar conduction. Transconductance (gm) and cut off frequency (fT) is also observed to be higher for SiGe based PIN and PNPN TFETs.

Simulation of 1.5-mm-thick and 15-cm-diameter gated silicon drift X-ray detector operated with a single high-voltage source

NASA Astrophysics Data System (ADS)

Matsuura, Hideharu

2015-04-01

High-resolution silicon X-ray detectors with a large active area are required for effectively detecting traces of hazardous elements in food and soil through the measurement of the energies and counts of X-ray fluorescence photons radially emitted from these elements. The thicknesses and areas of commercial silicon drift detectors (SDDs) are up to 0.5 mm and 1.5 cm2, respectively. We describe 1.5-mm-thick gated SDDs (GSDDs) that can detect photons with energies up to 50 keV. We simulated the electric potential distributions in GSDDs with a Si thickness of 1.5 mm and areas from 0.18 to 168 cm2 at a single high reverse bias. The area of a GSDD could be enlarged simply by increasing all the gate widths by the same multiple, and the capacitance of the GSDD remained small and its X-ray count rate remained high.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Controlling the ambipolarity and improvement of RF performance using Gaussian Drain Doped TFET

NASA Astrophysics Data System (ADS)

Nigam, Kaushal; Gupta, Sarthak; Pandey, Sunil; Kondekar, P. N.; Sharma, Dheeraj

2018-05-01

Ambipolar conduction in tunnel field-effect transistors (TFETs) has been occurred as an inherent issue due to drain-channel tunneling. It makes TFET less efficient and restricts its application in complementary digital circuits. Therefore, this manuscript reports the application of Gaussian doping profile on nanometer regime silicon channel TFETs to completely eliminate the ambipolarity. For this, Gaussian doping is used in the drain region of conventional gate-drain overlap TFET to control the tunneling of electrons from the valence band of channel to the conduction band of drain. As a result, barrier width at the drain/channel junction increases significantly leading to the suppression of an ambipolar current even when higher doping concentration (1 ? 10 ? cm ?) is considered in the drain region. However, significant improvement in terms of RF figure-of-merits such as cut-off frequency (f ?), gain bandwidth product (GBW), and gate-to-drain capacitance (C ?) is achieved with Gaussian doped gate on drain overlap TFET as compared to its counterpart TFET.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Comparative study of mobility extraction methods in p-type polycrystalline silicon thin film transistors

NASA Astrophysics Data System (ADS)

Liu, Kai; Liu, Yuan; Liu, Yu-Rong; En, Yun-Fei; Li, Bin

2017-07-01

Channel mobility in the p-type polycrystalline silicon thin film transistors (poly-Si TFTs) is extracted using Hoffman method, linear region transconductance method and multi-frequency C-V method. Due to the non-negligible errors when neglecting the dependence of gate-source voltage on the effective mobility, the extracted mobility results are overestimated using linear region transconductance method and Hoffman method, especially in the lower gate-source voltage region. By considering of the distribution of localized states in the band-gap, the frequency independent capacitance due to localized charges in the sub-gap states and due to channel free electron charges in the conduction band were extracted using multi-frequency C-V method. Therefore, channel mobility was extracted accurately based on the charge transport theory. In addition, the effect of electrical field dependent mobility degradation was also considered in the higher gate-source voltage region. In the end, the extracted mobility results in the poly-Si TFTs using these three methods are compared and analyzed.

Time delay and integration array (TDI) using charge transfer device technology. Phase 2, volume 1: Technical

NASA Technical Reports Server (NTRS)

1977-01-01

The 20x9 TDI array was developed to meet the LANDSAT Thematic Mapper Requirements. This array is based upon a self-aligned, transparent gate, buried channel process. The process features: (1) buried channel, four phase, overlapping gate CCD's for high transfer efficiency without fat zero; (2) self-aligned transistors to minimize clock feedthrough and parasitic capacitance; and (3) transparent tin oxide electrode for high quantum efficiency with front surface irradiation. The requirements placed on the array and the performance achieved are summarized. This data is the result of flat field measurements only, no imaging or dynamic target measurements were made during this program. Measurements were performed with two different test stands. The bench test equipment fabricated for this program operated at the 8 micro sec line time and employed simple sampling of the gated MOSFET output video signal. The second stand employed Correlated Doubled Sampling (CDS) and operated at 79.2 micro sec line time.

Dynamically correcting two-qubit gates against any systematic logical error

NASA Astrophysics Data System (ADS)

Calderon Vargas, Fernando Antonio

The reliability of quantum information processing depends on the ability to deal with noise and error in an efficient way. A significant source of error in many settings is coherent, systematic gate error. This work introduces a set of composite pulse sequences that generate maximally entangling gates and correct all systematic errors within the logical subspace to arbitrary order. These sequences are applica- ble for any two-qubit interaction Hamiltonian, and make no assumptions about the underlying noise mechanism except that it is constant on the timescale of the opera- tion. The prime use for our results will be in cases where one has limited knowledge of the underlying physical noise and control mechanisms, highly constrained control, or both. In particular, we apply these composite pulse sequences to the quantum system formed by two capacitively coupled singlet-triplet qubits, which is charac- terized by having constrained control and noise sources that are low frequency and of a non-Markovian nature.

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

PubMed

Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

2017-10-11

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

Passivation of oxide traps and interface states in GaAs metal-oxide-semiconductor capacitor by LaTaON passivation layer and fluorine incorporation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, L. N.; Choi, H. W.; Lai, P. T., E-mail: laip@eee.hku.hk

2015-11-23

GaAs metal-oxide-semiconductor capacitor with TaYON/LaTaON gate-oxide stack and fluorine-plasma treatment is fabricated and compared with its counterparts without the LaTaON passivation interlayer or the fluorine treatment. Experimental results show that the sample exhibits better characteristics: low interface-state density (8 × 10{sup 11 }cm{sup −2}/eV), small flatband voltage (0.69 V), good capacitance-voltage behavior, small frequency dispersion, and small gate leakage current (6.35 × 10{sup −6} A/cm{sup 2} at V{sub fb} + 1 V). These should be attributed to the suppressed growth of unstable Ga and As oxides on the GaAs surface during gate-oxide annealing by the LaTaON interlayer and fluorine incorporation, and the passivating effects of fluorine atoms on the acceptor-likemore » interface and near-interface traps.« less

Investigation of high sensitivity radio-frequency readout circuit based on AlGaN/GaN high electron mobility transistor

NASA Astrophysics Data System (ADS)

Zhang, Xiao-Yu; Tan, Ren-Bing; Sun, Jian-Dong; Li, Xin-Xing; Zhou, Yu; Lü, Li; Qin, Hua

2015-10-01

An AlGaN/GaN high electron mobility transistor (HEMT) device is prepared by using a semiconductor nanofabrication process. A reflective radio-frequency (RF) readout circuit is designed and the HEMT device is assembled in an RF circuit through a coplanar waveguide transmission line. A gate capacitor of the HEMT and a surface-mounted inductor on the transmission line are formed to generate LC resonance. By tuning the gate voltage Vg, the variations of gate capacitance and conductance of the HEMT are reflected sensitively from the resonance frequency and the magnitude of the RF reflection signal. The aim of the designed RF readout setup is to develop a highly sensitive HEMT-based detector. Project supported by the National Natural Science Foundation of China (Grant No. 61107093), the Suzhou Science and Technology Project, China (Grant No. ZXG2012024), and the Youth Innovation Promotion Association, Chinese Academy of Sciences (Grant No. 2012243).

Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs

NASA Astrophysics Data System (ADS)

Lahgere, Avinash; Panchore, Meena; Singh, Jawar

2016-08-01

In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling junction. Similarly, use of dopingless silicon nanowire with CP has a genuine advantage in process engineering. Therefore, combination of both technology boosters (CP and NC) in the proposed device enable low thermal budget, process variation immunity, and excellent electrical characteristics in contrast with its counterpart dopingless (DL) TFET (DL-TFET). An optimized device accomplishes an impressive 10× improvement in on-current, 100× reduced leakage current, 3× more transconductance (gm), and on-off current ratio of ∼1011 as compared to DL-TFET.

Controlled Quantum Operations of a Semiconductor Three-Qubit System

NASA Astrophysics Data System (ADS)

Li, Hai-Ou; Cao, Gang; Yu, Guo-Dong; Xiao, Ming; Guo, Guang-Can; Jiang, Hong-Wen; Guo, Guo-Ping

2018-02-01

In a specially designed semiconductor device consisting of three capacitively coupled double quantum dots, we achieve strong and tunable coupling between a target qubit and two control qubits. We demonstrate how to completely switch on and off the target qubit's coherent rotations by presetting two control qubits' states. A Toffoli gate is, therefore, possible based on these control effects. This research paves a way for realizing full quantum-logic operations in semiconductor multiqubit systems.

DC and small-signal physical models for the AlGaAs/GaAs high electron mobility transistor

NASA Technical Reports Server (NTRS)

Sarker, J. C.; Purviance, J. E.

1991-01-01

Analytical and numerical models are developed for the microwave small-signal performance, such as transconductance, gate-to-source capacitance, current gain cut-off frequency and the optimum cut-off frequency of the AlGaAs/GaAs High Electron Mobility Transistor (HEMT), in both normal and compressed transconductance regions. The validated I-V characteristics and the small-signal performances of four HeMT's are presented.

Universal non-adiabatic geometric manipulation of pseudo-spin charge qubits

NASA Astrophysics Data System (ADS)

Azimi Mousolou, Vahid

2017-01-01

Reliable quantum information processing requires high-fidelity universal manipulation of quantum systems within the characteristic coherence times. Non-adiabatic holonomic quantum computation offers a promising approach to implement fast, universal, and robust quantum logic gates particularly useful in nano-fabricated solid-state architectures, which typically have short coherence times. Here, we propose an experimentally feasible scheme to realize high-speed universal geometric quantum gates in nano-engineered pseudo-spin charge qubits. We use a system of three coupled quantum dots containing a single electron, where two computational states of a double quantum dot charge qubit interact through an intermediate quantum dot. The additional degree of freedom introduced into the qubit makes it possible to create a geometric model system, which allows robust and efficient single-qubit rotations through careful control of the inter-dot tunneling parameters. We demonstrate that a capacitive coupling between two charge qubits permits a family of non-adiabatic holonomic controlled two-qubit entangling gates, and thus provides a promising procedure to maintain entanglement in charge qubits and a pathway toward fault-tolerant universal quantum computation. We estimate the feasibility of the proposed structure by analyzing the gate fidelities to some extent.

Flexible graphene/carbon nanotube hybrid papers chemical-reduction-tailored by gallic acid for high-performance electrochemical capacitive energy storages

NASA Astrophysics Data System (ADS)

Yao, Lu; Zhou, Chao; Hu, Nantao; Hu, Jing; Hong, Min; Zhang, Liying; Zhang, Yafei

2018-03-01

Mechanically robust graphene papers with both high gravimetric and volumetric capacitances are desired for high-performance energy storages. However, it's still a challenge to tailor the structure of graphene papers in order to meet this requirement. In this work, a kind of chemical-reduction-tailored mechanically-robust reduced graphene oxide/carbon nanotube hybrid paper has been reported for high-performance electrochemical capacitive energy storages. Gallic acid (GA), as an excellent reducing agent, was used to reduce graphene oxide. Through vacuum filtration of gallic acid reduced graphene oxide (GA-rGO) and carboxylic multiwalled carbon nanotubes (MWCNTs) aqueous suspensions, mechanically robust GA-rGO/MWCNTs hybrid papers were obtained. The resultant hybrid papers showed high gravimetric capacitance of 337.6 F g-1 (0.5 A g-1) and volumetric capacitance of 151.2 F cm-3 (0.25 A cm-3). In addition, the assembled symmetric device based on the hybrid papers exhibited high gravimetric capacitance of 291.6 F g-1 (0.5 A g-1) and volumetric capacitance of 136.6 F cm-3 (0.25 A cm-3). Meanwhile, it exhibited excellent rate capability and cycling stability. Above all, this chemical reduction tailoring technique and the resultant high-performance GA-rGO/MWCNTs hybrid papers give an insight for designing high-performance electrodes and hold a great potential in the field of energy storages.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Study of bulk Hafnium oxide (HfO2) under compression

NASA Astrophysics Data System (ADS)

Pathak, Santanu; Mandal, Guruprasad; Das, Parnika

2018-04-01

Hafnium oxide (HfO2) is a technologically important material. This material has K-value of 25 and band gap 5.8 eV. A k value of 25-30 is preferred for a gate dielectric [1]. As it shows good insulating and capacitive properties, HfO2 is being considered as a replacement to SiO2 in microelectronic devices as gate dielectrics. On the other hand because of toughening mechanism due to phase transformation induced by stress field observed in these oxides, HFO2 has been a material of investigations in various configurations for a very long time. However the controversies about phase transition of HfO2 under pressure still exists. High quality synchrotron radiation has been used to study the structural phase transition of HfO2 under pressure.

Effects of HfO2/Al2O3 gate stacks on electrical performance of planar In x Ga1- x As tunneling field-effect transistors

NASA Astrophysics Data System (ADS)

Ahn, Dae-Hwan; Yoon, Sang-Hee; Takenaka, Mitsuru; Takagi, Shinichi

2017-08-01

We study the impact of gate stacks on the electrical characteristics of Zn-diffused source In x Ga1- x As tunneling field-effect transistors (TFETs) with Al2O3 or HfO2/Al2O3 gate insulators. Ta and W gate electrodes are compared in terms of the interface trap density (D it) of InGaAs MOS interfaces. It is found that D it is lower at the W/HfO2/Al2O3 InGaAs MOS interface than at the Ta/HfO2/Al2O3 interface. The In0.53Ga0.47As TFET with a W/HfO2 (2.7 nm)/Al2O3 (0.3 nm) gate stack of 1.4-nm-thick capacitance equivalent thickness (CET) has a steep minimum subthreshold swing (SS) of 57 mV/dec, which is attributed to the thin CET and low D it. Also, the In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33As (3.2 nm)/In0.53Ga0.47As (96.5 nm) quantum-well (QW) TFET supplemented with this 1.4-nm-thick CET gate stack exhibits a steeper minimum SS of 54 mV/dec and a higher on-current (I on) than those of the In0.53Ga0.47As TFET.

Coupling between electrolyte and organic semiconductor in electrolyte-gated organic field effect transistors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Biscarini, Fabio; Di Lauro, Michele; Berto, Marcello; Bortolotti, Carlo A.; Geerts, Yves H.; Vuillaume, Dominique

2016-11-01

Organic field effect transistors (OFET) operated in aqueous environments are emerging as ultra-sensitive biosensors and transducers of electrical and electrochemical signals from a biological environment. Their applications range from detection of biomarkers in bodily fluids to implants for bidirectional communication with the central nervous system. They can be used in diagnostics, advanced treatments and theranostics. Several OFET layouts have been demonstrated to be effective in aqueous operations, which are distinguished either by their architecture or by the respective mechanism of doping by the ions in the electrolyte solution. In this work we discuss the unification of the seemingly different architectures, such as electrolyte-gated OFET (EGOFET), organic electrochemical transistor (OECT) and dual-gate ion-sensing FET. We first demonstrate that these architectures give rise to the frequency-dependent response of a synapstor (synapse-like transistor), with enhanced or depressed modulation of the output current depending on the frequency of the time-dependent gate voltage. This behavior that was reported for OFETs with embedded metal nanoparticles shows the existence of a capacitive coupling through an equivalent network of RC elements. Upon the systematic change of ions in the electrolyte and the morphology of the charge transport layer, we show how the time scale of the synapstor is changed. We finally show how the substrate plays effectively the role of a second bottom gate, whose potential is actually fixed by the pH/composition of the electrolyte and the gate voltage applied.

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

NASA Astrophysics Data System (ADS)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

Analysis and optimization of RC delay in vertical nanoplate FET

NASA Astrophysics Data System (ADS)

Woo, Changbeom; Ko, Kyul; Kim, Jongsu; Kim, Minsoo; Kang, Myounggon; Shin, Hyungcheol

2017-10-01

In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (LG) of 12.2 nm, channel thickness (Tch) of 4 nm, and spacer length (LSD) of 6 nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (LG = 12.2 nm, Tch = 6 nm, LSD = 11.9 nm). It has each characteristic in this dimension (Ion/Ioff = 1.64 × 105, Subthreshold swing (S.S.) = 73 mV/dec, Drain-induced barrier lowering (DIBL) = 60 mV/V, and RC delay = 0.214 ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (Ti), we can reduce RC delay from 0.214 ps to 0.163 ps. It is about a 23.8% reduction. Without decreasing drain current, there is a reduction of RC delay as reducing outer fringing capacitance (Cof). Finally, when source/drain spacer length is set to be different, we have verified RC delay to be optimum.

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Room temperature 1040fps, 1 megapixel photon-counting image sensor with 1.1um pixel pitch

NASA Astrophysics Data System (ADS)

Masoodian, S.; Ma, J.; Starkey, D.; Wang, T. J.; Yamashita, Y.; Fossum, E. R.

2017-05-01

A 1Mjot single-bit quanta image sensor (QIS) implemented in a stacked backside-illuminated (BSI) process is presented. This is the first work to report a megapixel photon-counting CMOS-type image sensor to the best of our knowledge. A QIS with 1.1μm pitch tapered-pump-gate jots is implemented with cluster-parallel readout, where each cluster of jots is associated with its own dedicated readout electronics stacked under the cluster. Power dissipation is reduced with this cluster readout because of the reduced column bus parasitic capacitance, which is important for the development of 1Gjot arrays. The QIS functions at 1040fps with binary readout and dissipates only 17.6mW, including I/O pads. The readout signal chain uses a fully differential charge-transfer amplifier (CTA) gain stage before a 1b-ADC to achieve an energy/bit FOM of 16.1pJ/b and 6.9pJ/b for the whole sensor and gain stage+ADC, respectively. Analog outputs with on-chip gain are implemented for pixel characterization purposes.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Sensitive Precise p H Measurement with Large-Area Graphene Field-Effect Transistors at the Quantum-Capacitance Limit

NASA Astrophysics Data System (ADS)

Fakih, Ibrahim; Mahvash, Farzaneh; Siaj, Mohamed; Szkopek, Thomas

2017-10-01

A challenge for p H sensing is decreasing the minimum measurable p H per unit bandwidth in an economical fashion. Minimizing noise to reach the inherent limit imposed by charge fluctuation remains an obstacle. We demonstrate here graphene-based ion-sensing field-effect transistors that saturate the physical limit of sensitivity, defined here as the change in electrical response with respect to p H , and achieve a precision limited by charge-fluctuation noise at the sensing layer. We present a model outlining the necessity for maximizing the device carrier mobility, active sensing area, and capacitive coupling in order to minimize noise. We encapsulate large-area graphene with an ultrathin layer of parylene, a hydrophobic polymer, and deposit an ultrathin, stoichiometric p H -sensing layer of either aluminum oxide or tantalum pentoxide. With these structures, we achieve gate capacitances ˜0.6 μ F /cm2 , approaching the quantum-capacitance limit inherent to graphene, along with a near-Nernstian p H response of ˜55 ±2 mV /p H . We observe field-effect mobilities as high as 7000 cm2 V-1 s-1 with minimal hysteresis as a result of the parylene encapsulation. A detection limit of 0.1 m p H in a 60-Hz electrical bandwidth is observed in optimized graphene transistors.

Gating capacitive field-effect sensors by the charge of nanoparticle/molecule hybrids.

PubMed

Poghossian, Arshak; Bäcker, Matthias; Mayer, Dirk; Schöning, Michael J

2015-01-21

The semiconductor field-effect platform is a powerful tool for chemical and biological sensing with direct electrical readout. In this work, the field-effect capacitive electrolyte-insulator-semiconductor (EIS) structure - the simplest field-effect (bio-)chemical sensor - modified with citrate-capped gold nanoparticles (AuNPs) has been applied for a label-free electrostatic detection of charged molecules by their intrinsic molecular charge. The EIS sensor detects the charge changes in AuNP/molecule inorganic/organic hybrids induced by the molecular adsorption or binding events. The feasibility of the proposed detection scheme has been exemplarily demonstrated by realizing capacitive EIS sensors consisting of an Al-p-Si-SiO2-silane-AuNP structure for the label-free detection of positively charged cytochrome c and poly-d-lysine molecules as well as for monitoring the layer-by-layer formation of polyelectrolyte multilayers of poly(allylamine hydrochloride)/poly(sodium 4-styrene sulfonate), representing typical model examples of detecting small proteins and macromolecules and the consecutive adsorption of positively/negatively charged polyelectrolytes, respectively. For comparison, EIS sensors without AuNPs have been investigated, too. The adsorption of molecules on the surface of AuNPs has been verified via the X-ray photoelectron spectroscopy method. In addition, a theoretical model of the functioning of the capacitive field-effect EIS sensor functionalized with AuNP/charged-molecule hybrids has been discussed.

Characterizing Radio Emission From Extensive Air Showers with the SLAC-T510 Experiment, with Applications to ANITA

NASA Astrophysics Data System (ADS)

McGuire, Felicia Ann

Essential to metal-oxide-semiconductor field-effect transistor (MOSFET) scaling is the reduction of the supply voltage to mitigate the power consumption and corresponding heat dissipation. Conventional dielectric materials are subject to the thermal limit imposed by the Boltzmann factor in the subthreshold swing, which places an absolute minimum on the supply voltage required to modulate the current. Furthermore, as technology approaches the 5 nm node, electrostatic control of a silicon channel becomes exceedingly difficult, regardless of the gating technique. This notion of "the end of silicon scaling" has rapidly increased research into more scalable channel materials as well as new methods of transistor operation. Among the many promising options are two-dimensional (2D) FETs and negative capacitance (NC) FETs. 2D-FETs make use of atomically thin semiconducting channels that have enabled demonstrated scalability beyond what silicon can offer. NC-FETs demonstrate an effective negative capacitance arising from the integration of a ferroelectric into the transistor gate stack, allowing sub-60 mV/dec switching. While both of these devices provide significant advantages, neither can accomplish the ultimate goal of a FET that is both low-voltage and scalable. However, an appropriate fusion of the 2D-FET and NC-FET into a 2D NC-FET has the potential of enabling a steep-switching device that is dimensionally scalable beyond the 5 nm technology node. In this work, the motivation for and operation of 2D NC-FETs is presented. Experimental realization of 2D NC-FETs using 2D transition metal dichalcogenide molybdenum disulfide (MoS2) as the channel is shown with two different ferroelectric materials: 1) a solution-processed, polymeric poly(vinylidene difluoride trifluoroethylene) ferroelectric and 2) an atomic layer deposition (ALD) grown hafnium zirconium oxide (HfZrO2) ferroelectric. Each ferroelectric was integrated into the gate stack of a 2D-FET having either a top-gate (polymeric ferroelectric) or bottom-gate (HfZrO2 ferroelectric) configuration. HfZrO 2 devices with metallic interfacial layers (between ferroelectric and dielectric) and thinner ferroelectric layers were found to reduce both the hysteresis and the threshold voltage. Detailed characterization of the devices was performed and, most significantly, the 2D NC-FETs with HfZrO2 reproducibly yielded subthreshold swings well below the thermal limit with over more than four orders of magnitude in drain current modulation. HfZrO 2 devices without metallic interfacial layers were utilized to explore the impact of ferroelectric thickness, dielectric thickness, and dielectric composition on device performance. The impact of an interfacial metallic layer on the device operation was investigated in devices with HfZrO2 and shown to be crucial at enabling sub-60 mV/dec switching and large internal voltage gains. The significance of dielectric material choice on device performance was explored and found to be a critical factor in 2D NC-FET transistor operation. These successful results pave the way for future integration of this new device structure into existing technology markets.

Microscopic Theory of Supercapacitors

NASA Astrophysics Data System (ADS)

Skinner, Brian Joseph

As new energy technologies are designed and implemented, there is a rising demand for improved energy storage devices. At present the most promising class of these devices is the electric double-layer capacitor (EDLC), also known as the supercapacitor. A number of recently created supercapacitors have been shown to produce remarkably large capacitance, but the microscopic mechanisms that underlie their operation remain largely mysterious. In this thesis we present an analytical, microscopic-level theory of supercapacitors, and we explain how such large capacitance can result. Specifically, we focus on four types of devices that have been shown to produce large capacitance. The first is a capacitor composed of a clean, low-temperature two-dimensional electron gas adjacent to a metal gate electrode. Recent experiments have shown that such a device can produce capacitance as much as 40% larger than that of a conventional plane capacitor. We show that this enhanced capacitance can be understood as the result of positional correlations between electrons and screening by the gate electrode in the form of image charges. Thus, the enhancement of the capacitance can be understood primarily as a classical, electrostatic phenomenon. Accounting for the quantum mechanical properties of the electron gas provides corrections to the classical theory, and these are discussed. We also present a detailed numerical calculation of the capacitance of the system based on a calculation of the system's ground state energy using the variational principle. The variational technique that we develop is broadly applicable, and we use it here to make an accurate comparison to experiment and to discuss quantitatively the behavior of the electrons' correlation function. The second device discussed in this thesis is a simple EDLC composed of an ionic liquid between two metal electrodes. We adopt a simple description of the ionic liquid and show that for realistic parameter values the capacitance can be as much as three times larger than that of a plane capacitor with thickness equal to the ion diameter. As in the previous system, this large capacitance is the result of image charge formation in the metal electrode and positional correlations between discrete ions that comprise the electric double-layer. We show that the maximum capacitance scales with the temperature to the power -1/3, and that at moderately large voltage the capacitance also decays as the inverse one third power of voltage. These results are confirmed by a Monte Carlo simulation. The third type of device we consider is that of a porous supercapacitor, where the electrode is made from a conducting material with a dense arrangement of narrow, planar pores into which ionic liquid can enter when a voltage is applied. In this case we show that when the electrode is metallic the narrow pores aggressively screen the interaction between neighboring ions in a pore, leading to an interaction energy between ions that decays exponentially. This exponential interaction between ions allows the capacitance to be nearly an order of magnitude larger than what is predicted by mean-field theories. This result is confirmed by a Monte Carlo simulation. We also present a theory for the capacitance when the electrode is not a perfect metal, but has a finite electronic screening radius. When this screening radius is larger than the distance between pores, ions begin to interact across multiple pores and the capacitance is determined by the Yukawa-like interaction of a three-dimensional, correlated arrangement of ions. Finally, we consider the case of supercapacitor electrodes made from a stack of graphene sheets with randomly-inserted "spacer" molecules. For such devices, experiments have produced very large capacitance despite the small density of states of the electrode material, which would seem to imply poor screening of the ionic charge. We show that these large capacitance values can be understood as the result of collective entrance of ions into the graphene stack (GS) and the renormalization of the ionic charge produced by nonlinear screening. The collective behavior of ions results from the strong elastic energy associated with intercalated ions deforming the GS, which creates an effective attraction between them. The result is the formation of "disks" of charge that enter the electrode collectively and have their charge renormalized by the strong, nonlinear screening of the surrounding graphene layers. This renormalization leads to a capacitance that at small voltages increases linearly with voltage and is enhanced over mean-field predictions by a large factor proportional to the number of ions within the disk to the power 9/4. At large voltages, the capacitance is dictated by the physics of graphite intercalation compounds and is proportional to the voltage raised to the power -4/5. We also examine theoretically the case where the effective fine structure constant of the GS is a small parameter, and we uncover a wealth of scaling regimes.

Special Component Designs for Differential-Amplifier MMICs

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka

2010-01-01

Special designs of two types of electronic components transistors and transmission lines have been conceived to optimize the performances of these components as parts of waveguide-embedded differential-amplifier monolithic microwave integrated circuits (MMICs) of the type described in the immediately preceding article. These designs address the following two issues, the combination of which is unique to these particular MMICs: Each MMIC includes a differential double-strip transmission line that typically has an impedance between 60 and 100 W. However, for purposes of matching of impedances, transmission lines having lower impedances are also needed. The transistors in each MMIC are, more specifically, one or more pair(s) of InP-based high-electron-mobility transistors (HEMTs). Heretofore, it has been common practice to fabricate each such pair as a single device configured in the side-to-side electrode sequence source/gate/drain/gate/source. This configuration enables low-inductance source grounding from the sides of the device. However, this configuration is not suitable for differential operation, in which it is necessary to drive the gates differentially and to feed the output from the drain electrodes differentially. The special transmission-line design provides for three conductors, instead of two, in places where lower impedance is needed. The third conductor is a metal strip placed underneath the differential double-strip transmission line. The third conductor increases the capacitance per unit length of the transmission line by such an amount as to reduce the impedance to between 5 and 15 W. In the special HEMT-pair design, the side-to-side electrode sequence is changed to drain/gate/source/gate/ drain. In addition, the size of the source is reduced significantly, relative to corresponding sizes in prior designs. This reduction is justified by the fact that, by virtue of the differential configuration, the device has an internal virtual ground, and therefore there is no need for a low-resistance contact between the source and the radio-frequency circuitry. The source contact is needed only for DC biasing. These designs were implemented in a single-stage-amplifier MMIC. In a test at a frequency of 305 GHz, the amplifier embedded in a waveguide exhibited a gain of 0 dB; after correcting for the loss in the waveguide, the amplifier was found to afford a gain of 0.9 dB. In a test at 220 GHz, the overall gain of the amplifier- and-waveguide assembly was found to be 3.5 dB.

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

NASA Astrophysics Data System (ADS)

Gupta, Ritesh; Rathi, Servin; Kaur, Ravneet; Gupta, Mridula; Gupta, R. S.

2009-03-01

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal-insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268-2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534-2540] are also being fabricated these days, mainly at the drain end ( Γ-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal-Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189-198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

Increases in intracellular pH facilitate endocytosis and decrease availability of voltage-gated proton channels in osteoclasts and microglia

PubMed Central

Sakai, Hiromu; Li, Guangshuai; Hino, Yoshiko; Moriura, Yoshie; Kawawaki, Junko; Sawada, Makoto; Kuno, Miyuki

2013-01-01

Voltage-gated proton channels (H+ channels) are highly proton-selective transmembrane pathways. Although the primary determinants for activation are the pH and voltage gradients across the membrane, the current amplitudes fluctuate often when these gradients are constant. The aim of this study was to investigate the role of the intracellular pH (pHi) in regulating the availability of H+ channels in osteoclasts and microglia. In whole-cell clamp recordings, the pHi was elevated after exposure to NH4Cl and returned to the control level after washout. However, the H+ channel conductance did not recover fully when the exposure was prolonged (>5 min). Similar results were observed in osteoclasts and microglia, but not in COS7 cells expressing a murine H+ channel gene (mVSOP). As other electrophysiological properties, like the gating kinetics and voltage dependence for activation, were unchanged, the decreases in the H+ channel conductance were probably due to the decreases in H+ channels available at the plasma membrane. The decreases in the H+ channel conductances were accompanied by reductions in the cell capacitance. Exposure to NH4Cl increased the uptake of the endocytosis marker FM1-43, substantiating the idea that pHi increases facilitated endocytosis. In osteoclasts, whose plasma membrane expresses V-ATPases and H+ channels, pHi increases by these H+-transferring molecules in part facilitated endocytosis. The endocytosis and decreases in the H+ channel conductance were reduced by dynasore, a dynamin blocker. These results suggest that pHi increases in osteoclasts and microglia decrease the numbers of H+ channels available at the plasma membrane through facilitation of dynamin-dependent endocytosis. PMID:24081153

Effect of surface fields on the dynamic resistance of planar HgCdTe mid-wavelength infrared photodiodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Kai; Wang, Xi; Zhang, Peng

2015-05-28

This work investigates the effect of surface fields on the dynamic resistance of a planar HgCdTe mid-wavelength infrared photodiode from both theoretical and experimental aspects, considering a gated n-on-p diode with the surface potential of its p-region modulated. Theoretical models of the surface leakage current are developed, where the surface tunnelling current in the case of accumulation is expressed by modifying the formulation of bulk tunnelling currents, and the surface channel current for strong inversion is simulated with a transmission line method. Experimental data from the fabricated devices show a flat-band voltage of V{sub FB}=−5.7 V by capacitance-voltage measurement, and thenmore » the physical parameters for bulk properties are determined from the resistance-voltage characteristics of the diode working at a flat-band gate voltage. With proper values of the modeling parameters such as surface trap density and channel electron mobility, the theoretical R{sub 0}A product and corresponding dark current calculated from the proposed model as functions of the gate voltage V{sub g} demonstrate good consistency with the measured values. The R{sub 0}A product remarkably degenerates when V{sub g} is far below or above V{sub FB} because of the surface tunnelling current or channel current, respectively; and it attains the maximum value of 5.7×10{sup 7} Ω · cm{sup 2} around the transition between surface depletion and weak inversion when V{sub g}≈−4 V, which might result from reduced generation-recombination current.« less

Non-Faradaic electrochemical detection of protein interactions by integrated neuromorphic CMOS sensors.

PubMed

Jacquot, Blake C; Muñoz, Nini; Branch, Darren W; Kan, Edwin C

2008-05-15

Electronic detection of the binding event between biotinylated bovine serum albumen (BSA) and streptavidin is demonstrated with the chemoreceptive neuron MOS (CnuMOS) device. Differing from the ion-sensitive field-effect transistors (ISFET), CnuMOS, with the potential of the extended floating gate determined by both the sensing and control gates in a neuromorphic style, can provide protein detection without requiring analyte reference electrodes. In comparison with the microelectrode arrays, measurements are gathered through purely capacitive, non-Faradaic interactions across insulating interfaces. By using a (3-glycidoxypropyl)trimethoxysilane (3-GPS) self-assembled monolayer (SAM) as a simple covalent link for attaching proteins to a silicon dioxide sensing surface, a fully integrated, electrochemical detection platform is realized for protein interactions through monotone large-signal measurements or small-signal impedance spectroscopy. Calibration curves were created to coordinate the sensor response with ellipsometric measurements taken on witness samples. By monitoring the film thickness of streptavidin capture, a sensitivity of 25ng/cm2 or 2A of film thickness was demonstrated. With an improved noise floor the sensor can detect down to 2ng/(cm2mV) based on the calibration curve. AC measurements are shown to significantly reduce long-term sensor drift. Finally, a noise analysis of electrochemical data indicates 1/f(alpha) behavior with a noise floor beginning at approximately 1Hz.

Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

2016-12-01

The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Capacitance-voltage measurement in memory devices using ferroelectric polymer

NASA Astrophysics Data System (ADS)

Nguyen, Chien A.; Lee, Pooi See

2006-01-01

Application of thin polymer film as storing mean for non-volatile memory devices is investigated. Capacitance-voltage (C-V) measurement of metal-ferroelectric-metal device using ferroelectric copolymer P(VDF-TrFE) as dielectric layer shows stable 'butter-fly' curve. The two peaks in C-V measurement corresponding to the largest capacitance are coincidental at the coercive voltages that give rise to zero polarization in the polarization hysteresis measurement. By comparing data of C-V and P-E measurement, a correlation between two types of hysteresis is established in which it reveals simultaneous electrical processes occurring inside the device. These processes are caused by the response of irreversible and reversible polarization to the applied electric field that can be used to present a memory window. The memory effect of ferroelectric copolymer is further demonstrated for fabricating polymeric non-volatile memory devices using metal-ferroelectric-insulator-semiconductor structure (MFIS). By applying different sweeping voltages at the gate, bidirectional flat-band voltage shift is observed in the ferroelectric capacitor. The asymmetrical shift after negative sweeping is resulted from charge accumulation at the surface of Si substrate caused by the dipole direction in the polymer layer. The effect is reversed for positive voltage sweeping.

Local gate control in carbon nanotube quantum devices

NASA Astrophysics Data System (ADS)

Biercuk, Michael Jordan

This thesis presents transport measurements of carbon nanotube electronic devices operated in the quantum regime. Nanotubes are contacted by source and drain electrodes, and multiple lithographically-patterned electrostatic gates are aligned to each device. Transport measurements of device conductance or current as a function of local gate voltages reveal that local gates couple primarily to the proximal section of the nanotube, hence providing spatially localized control over carrier density along the nanotube length. Further, using several different techniques we are able to produce local depletion regions along the length of a tube. This phenomenon is explored in detail for different contact metals to the nanotube. We utilize local gating techniques to study multiple quantum dots in carbon nanotubes produced both by naturally occurring defects, and by the controlled application of voltages to depletion gates. We study double quantum dots in detail, where transport measurements reveal honeycomb charge stability diagrams. We extract values of energy-level spacings, capacitances, and interaction energies for this system, and demonstrate independent control over all relevant tunneling rates. We report rf-reflectometry measurements of gate-defined carbon nanotube quantum dots with integrated charge sensors. Aluminum rf-SETs are electrostatically coupled to carbon nanotube devices and detect single electron charging phenomena in the Coulomb blockade regime. Simultaneous correlated measurements of single electron charging are made using reflected rf power from the nanotube itself and from the rf-SET on microsecond time scales. We map charge stability diagrams for the nanotube quantum dot via charge sensing, observing Coulomb charging diamonds beyond the first order. Conductance measurements of carbon nanotubes containing gated local depletion regions exhibit plateaus as a function of gate voltage, spaced by approximately 1e2/h, the quantum of conductance for a single (non-degenerate) mode. Plateau structure is investigated as a function of bias voltage, temperature, and magnetic field. We speculate on the origin of this surprising quantization, which appears to lack band and spin degeneracy.

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

Impact of underlap and mole-fraction on RF performance of strained-Si/Si1-xGex/strained-Si DG MOSFETs

NASA Astrophysics Data System (ADS)

Dutta, Arka; Koley, Kalyan; Sarkar, Chandan K.

2014-11-01

In this paper, a systematic RF performance analysis of double-gate strained silicon (DGSS) nMOSFETs is presented. The analysis is focused upon impact of Germanium mole-fraction variation on RF performance of underlap engineered DGSS nMOSFET. The RF performance of the device is analysed as a function of intrinsic RF figure of merits (FOMs) including non-quasi static effects (NQS). The RF FOMs are represented by the intrinsic gate to source/drain capacitance (Cgs and Cgd) and resistance (Rgs and Rgd), the transport delay (τm), the intrinsic inductance (Lsd), the cut-off frequency (fT), and the maximum oscillation frequency (fMAX). The results of the study suggested a significant improvement in the device performance, up to 40% increase in Germanium mole fraction (χ).

High mobility back-gated InAs/GaSb double quantum well grown on GaSb substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nguyen, Binh-Minh, E-mail: mbnguyen@hrl.com, E-mail: MSokolich@hrl.com; Yi, Wei; Noah, Ramsey

2015-01-19

We report a backgated InAs/GaSb double quantum well device grown on GaSb substrate. The use of the native substrate allows for high materials quality with electron mobility in excess of 500 000 cm{sup 2}/Vs at sheet charge density of 8 × 10{sup 11} cm{sup −2} and approaching 100 000 cm{sup 2}/Vs near the charge neutrality point. Lattice matching between the quantum well structure and the substrate eliminates the need for a thick buffer, enabling large back gate capacitance and efficient coupling with the conduction channels in the quantum wells. As a result, quantum Hall effects are observed in both electron and hole regimes across the hybridizationmore » gap.« less

Gate-controlled-diodes in silicon-on-sapphire: A computer simulation

NASA Technical Reports Server (NTRS)

Gassaway, J. D.

1974-01-01

The computer simulation of the electrical behavior of a Gate-Controlled Diode (GCD) fabricated in Silicon-On-Sapphire (SOS) was described. A procedure for determining lifetime profiles from capacitance and reverse current measurements on the GCD was established. Chapter 1 discusses the SOS structure and points out the need of lifetime profiles to assist in device design for GCD's and bipolar transistors. Chapter 2 presents the one-dimensional analytical formula for electrostatic analysis of the SOS-GCD which are useful for data interpretation and setting boundary conditions on a simplified two-dimensional analysis. Chapter 3 gives the results of a two-dimensional analysis which treats the field as one-dimensional until the silicon film is depleted and the field penetrates the sapphire substrate. Chapter 4 describes a more complete two-dimensional model and gives results of programs implementing the model.

Electrochemical and Capacitive Properties of Carbon Dots/Reduced Graphene Oxide Supercapacitors.

PubMed

Dang, Yong-Qiang; Ren, Shao-Zhao; Liu, Guoyang; Cai, Jiangtao; Zhang, Yating; Qiu, Jieshan

2016-11-14

There is much recent interest in graphene-based composite electrode materials because of their excellent mechanical strengths, high electron mobilities, and large specific surface areas. These materials are good candidates for applications in supercapacitors. In this work, a new graphene-based electrode material for supercapacitors was fabricated by anchoring carbon dots (CDs) on reduced graphene oxide (rGO). The capacitive properties of electrodes in aqueous electrolytes were systematically studied by galvanostatic charge-discharge measurements, cyclic voltammetry, and electrochemical impedance spectroscopy. The capacitance of rGO was improved when an appropriate amount of CDs were added to the material. The CD/rGO electrode exhibited a good reversibility, excellent rate capability, fast charge transfer, and high specific capacitance in 1 M H₂SO₄. Its capacitance was as high as 211.9 F/g at a current density of 0.5 A/g. This capacitance was 74.3% higher than that of a pristine rGO electrode (121.6 F/g), and the capacitance of the CD/rGO electrode retained 92.8% of its original value after 1000 cycles at a CDs-to-rGO ratio of 5:1.

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al{sub 2}O{sub 3} gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aoki, Takeshi, E-mail: aokit@sc.sumitomo-chem.co.jp; Fukuhara, Noboru; Osada, Takenori

2015-08-15

This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al{sub 2}O{sub 3} gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al{sub 2}O{sub 3} in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al{sub 2}O{sub 3} layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resultingmore » MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (D{sub it}) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce D{sub it} to below 2 × 10{sup 12} cm{sup −2} eV{sup −1}. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.« less

Modelling and simulation of parallel triangular triple quantum dots (TTQD) by using SIMON 2.0

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fathany, Maulana Yusuf, E-mail: myfathany@gmail.com; Fuada, Syifaul, E-mail: fsyifaul@gmail.com; Lawu, Braham Lawas, E-mail: bram-labs@rocketmail.com

2016-04-19

This research presents analysis of modeling on Parallel Triple Quantum Dots (TQD) by using SIMON (SIMulation Of Nano-structures). Single Electron Transistor (SET) is used as the basic concept of modeling. We design the structure of Parallel TQD by metal material with triangular geometry model, it is called by Triangular Triple Quantum Dots (TTQD). We simulate it with several scenarios using different parameters; such as different value of capacitance, various gate voltage, and different thermal condition.

Simulation model for electron irradiated IGZO thin film transistors

NASA Astrophysics Data System (ADS)

Dayananda, G. K.; Shantharama Rai, C.; Jayarama, A.; Kim, Hyun Jae

2018-02-01

An efficient drain current simulation model for the electron irradiation effect on the electrical parameters of amorphous In-Ga-Zn-O (IGZO) thin-film transistors is developed. The model is developed based on the specifications such as gate capacitance, channel length, channel width, flat band voltage etc. Electrical parameters of un-irradiated IGZO samples were simulated and compared with the experimental parameters and 1 kGy electron irradiated parameters. The effect of electron irradiation on the IGZO sample was analysed by developing a mathematical model.

Instrumentation for measuring aircraft noise and sonic boom

NASA Technical Reports Server (NTRS)

Zuckerwar, A. J. (Inventor)

1976-01-01

Improved instrumentation suitable for measuring aircraft noise and sonic booms is described. An electric current proportional to the sound pressure level at a condenser microphone is produced and transmitted over a cable and amplified by a zero drive amplifier. The converter consists of a local oscillator, a dual-gate field-effect transistor mixer, and a voltage regulator/impedance translator. The improvements include automatic tuning compensation against changes in static microphone capacitance and means for providing a remote electrical calibration capability.

Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

DTIC Science & Technology

2010-03-31

in OFETs have been investigated extensively in the past couple of years. They are mainly attributed to the (i) charge trapping and release in the...This sharp rise in capacitance can be attributed due to trap charges or impurities such as ions which is most likely in the bulk of DNA-CTMA as well...5 Transient response of BiOFETs As mentioned before, charge trapping and release time can be strong function of applied voltage as well as device

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography.

PubMed

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-01-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Top-gate organic depletion and inversion transistors with doped channel and injection contact

NASA Astrophysics Data System (ADS)

Liu, Xuhai; Kasemann, Daniel; Leo, Karl

2015-03-01

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

NASA Astrophysics Data System (ADS)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Development of a Si/ SiO 2-based double quantum dot charge qubit with dispersive microwave readout

NASA Astrophysics Data System (ADS)

House, M. G.; Henry, E.; Schmidt, A.; Naaman, O.; Siddiqi, I.; Pan, H.; Xiao, M.; Jiang, H. W.

2011-03-01

Coupling of a high-Q microwave resonator to superconducting qubits has been successfully used to prepare, manipulate, and read out the state of a single qubit, and to mediate interactions between qubits. Our work is geared toward implementing this architecture in a semiconductor qubit. We present the design and development of a lateral quantum dot in which a superconducting microwave resonator is capacitively coupled to a double dot charge qubit. The device is a silicon MOSFET structure with a global gate which is used to accumulate electrons at a Si/ Si O2 interface. A set of smaller gates are used to deplete these electrons to define a double quantum dot and adjacent conduction channels. Two of these depletion gates connect directly to the conductors of a 6 GHz co-planar stripline resonator. We present measurements of transport and conventional charge sensing used to characterize the double quantum dot, and demonstrate that it is possible to reach the few-electron regime in this system. This work is supported by the DARPA-QuEST program.

QCAD simulation and optimization of semiconductor double quantum dots

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nielsen, Erik; Gao, Xujiao; Kalashnikova, Irina

2013-12-01

We present the Quantum Computer Aided Design (QCAD) simulator that targets modeling quantum devices, particularly silicon double quantum dots (DQDs) developed for quantum qubits. The simulator has three di erentiating features: (i) its core contains nonlinear Poisson, e ective mass Schrodinger, and Con guration Interaction solvers that have massively parallel capability for high simulation throughput, and can be run individually or combined self-consistently for 1D/2D/3D quantum devices; (ii) the core solvers show superior convergence even at near-zero-Kelvin temperatures, which is critical for modeling quantum computing devices; (iii) it couples with an optimization engine Dakota that enables optimization of gate voltagesmore » in DQDs for multiple desired targets. The Poisson solver includes Maxwell- Boltzmann and Fermi-Dirac statistics, supports Dirichlet, Neumann, interface charge, and Robin boundary conditions, and includes the e ect of dopant incomplete ionization. The solver has shown robust nonlinear convergence even in the milli-Kelvin temperature range, and has been extensively used to quickly obtain the semiclassical electrostatic potential in DQD devices. The self-consistent Schrodinger-Poisson solver has achieved robust and monotonic convergence behavior for 1D/2D/3D quantum devices at very low temperatures by using a predictor-correct iteration scheme. The QCAD simulator enables the calculation of dot-to-gate capacitances, and comparison with experiment and between solvers. It is observed that computed capacitances are in the right ballpark when compared to experiment, and quantum con nement increases capacitance when the number of electrons is xed in a quantum dot. In addition, the coupling of QCAD with Dakota allows to rapidly identify which device layouts are more likely leading to few-electron quantum dots. Very efficient QCAD simulations on a large number of fabricated and proposed Si DQDs have made it possible to provide fast feedback for design comparison and optimization.« less

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lim, Kwan-Yong; Park, Dae-Gyu; Cho, Heung-Jae; Kim, Joong-Jung; Yang, Jun-Mo; Ii, Choi-Sang; Yeo, In-Seok; Park, Jin Won

2002-01-01

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50-140 Å)/SiO2(7 Å)/p-Si metal-oxide-semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance-voltage hysteresis as small as ˜12 mV with the flatband voltage of -0.5 V and the interface trap density of ˜5×1010cm-2 eV-1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min.

Electrode influence on the number of oxygen vacancies at the gate/high-κ dielectric interface in nanoscale MIM capacitors

NASA Astrophysics Data System (ADS)

Stojanovska-Georgievska, Lihnida

2015-02-01

In this paper, a particular attention has been paid in determining the impact of the type of top electrode (the gate), on the overall characteristics of the examined metal-insulator-metal structures, that contain doped Ta2O5:Hf high-κ dielectric as an insulator. For that purpose MIM capacitors with different metal gates (conventional Al and also W, Au, Pt, Mo, TiN, Ta) were formed. The results obtained, consider both the influence of metal work function and oxygen affinity, as possible reasons for increasing of number of oxygen vacancies at the gate/dielectric interface. Here we use capacitance-voltage alteration (C-V measurements) under constant current stress (CCS) conditions as characterization technique. The measurements show grater creation of positive oxygen vacancies in the case of metal electrodes with high work function, like Au and Pt, for almost one order of magnitude. It is also indicative that these metals have also the lowest values of heat of oxygen formation, which also favors the creation of oxygen vacancies. All results are discussed taking into consideration the nanoscale thickness of the dielectric layer (of the order of 8 nm), implicating the stronger effect of interface properties on the overall behavior rather than the one originating from the bulk of material.

Transient release kinetics of rod bipolar cells revealed by capacitance measurement of exocytosis from axon terminals in rat retinal slices.

PubMed

Oltedal, Leif; Hartveit, Espen

2010-05-01

Presynaptic transmitter release has mostly been studied through measurements of postsynaptic responses, but a few synapses offer direct access to the presynaptic terminal, thereby allowing capacitance measurements of exocytosis. For mammalian rod bipolar cells, synaptic transmission has been investigated in great detail by recording postsynaptic currents in AII amacrine cells. Presynaptic measurements of the dynamics of vesicular cycling have so far been limited to isolated rod bipolar cells in dissociated preparations. Here, we first used computer simulations of compartmental models of morphologically reconstructed rod bipolar cells to adapt the 'Sine + DC' technique for capacitance measurements of exocytosis at axon terminals of intact rod bipolar cells in retinal slices. In subsequent physiological recordings, voltage pulses that triggered presynaptic Ca(2+) influx evoked capacitance increases that were proportional to the pulse duration. With pulse durations 100 ms, the increase saturated at 10 fF, corresponding to the size of a readily releasable pool of vesicles. Pulse durations 400 ms evoked additional capacitance increases, probably reflecting recruitment from additional pools of vesicles. By using Ca(2+) tail current stimuli, we separated Ca(2+) influx from Ca(2+) channel activation kinetics, allowing us to estimate the intrinsic release kinetics of the readily releasable pool, yielding a time constant of 1.1 ms and a maximum release rate of 2-3 vesicles (release site)(1) ms(1). Following exocytosis, we observed endocytosis with time constants ranging from 0.7 to 17 s. Under physiological conditions, it is likely that release will be transient, with the kinetics limited by the activation kinetics of the voltage-gated Ca(2+) channels.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Paramagnetic defects and charge trapping behavior of ZrO2 films deposited on germanium by plasma-enhanced CVD

NASA Astrophysics Data System (ADS)

Mahata, C.; Bera, M. K.; Bose, P. K.; Maiti, C. K.

2009-02-01

Internal photoemission and magnetic resonance studies have been performed to investigate the charge trapping behavior and chemical nature of defects in ultrathin (~14 nm) high-k ZrO2 dielectric films deposited on p-Ge (1 0 0) substrates at low temperature (<200 °C) by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma at a pressure of ~65 Pa. Both the band and defect-related electron states have been characterized using electron paramagnetic resonance, internal photoemission, capacitance-voltage and current-voltage measurements under UV illumination. Capacitance-voltage and photocurrent-voltage measurements were used to determine the centroid of oxide charge within the high-k gate stack. The observed shifts in photocurrent response of the Al/ZrO2/GeO2/p-Ge metal-insulator-semiconductor (MIS) capacitors indicate the location of the centroids to be within the ZrO2 dielectric near to the gate electrode. Moreover, the measured flat band voltage and photocurrent shifts also indicate a large density of traps in the dielectric. The impact of plasma nitridation on the interfacial quality of the oxides has been investigated. Different N sources, such as NO and NH3, have been used for nitrogen engineering. Oxynitride samples show a lower defect density and trapping over the non-nitrided samples. The charge trapping and detrapping properties of MIS capacitors under stressing in constant current and voltage modes have been investigated in detail.

Comprehensive analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications

NASA Astrophysics Data System (ADS)

Kumar, Ajay; Tripathi, M. M.; Chaujar, Rishu

2018-04-01

In this work, a comprehensive analog and RF performance of a novel Black Phosphorus-Junctionless-Recessed Channel (BP-JL-RC) MOSFET has been explored at 45 nm technology node (Gate length = 20 nm). The integration of black phosphorus with junctionless recessed channel MOSFET, leads to higher drain current of about 0.3 mA and excellent switching ratio (of the order of 1011) due to reduced off-current which leads to improvement in sub-threshold slope (SS) (67mV/dec). Further, RF performance metrics have also been studied with an aim to analyze high-frequency performance. The following FOMs have been evaluated: cut-off frequency (fT), maximum oscillator frequency (fMAX), stern stability factor, various power gains and parasitic capacitances at THz frequency range. Thus, in addition to the high packing density offered by RC MOSFET, the proposed design finds numerous application at THz frequency making it a promising candidate at wafer scale integration level.

Regulation of Calcium Channels and Exocytosis in Mouse Adrenal Chromaffin Cells by Prostaglandin EP3 Receptors

PubMed Central

Jewell, Mark L.; Breyer, Richard M.

2011-01-01

Prostaglandin (PG) E2 controls numerous physiological functions through a family of cognate G protein-coupled receptors (EP1–EP4). Targeting specific EP receptors might be therapeutically useful and reduce side effects associated with nonsteroidal anti-inflammatory drugs and selective cyclooxygenase-2 inhibitors that block prostanoid synthesis. Systemic immune challenge and inflammatory cytokines have been shown to increase expression of the synthetic enzymes for PGE2 in the adrenal gland. Catecholamines and other hormones, released from adrenal chromaffin cells in response to Ca2+ influx through voltage-gated Ca2+ channels, play central roles in homeostatic function and the coordinated stress response. However, long-term elevation of circulating catecholamines contributes to the pathogenesis of hypertension and heart failure. Here, we investigated the EP receptor(s) and cellular mechanisms by which PGE2 might modulate chromaffin cell function. PGE2 did not alter resting intracellular [Ca2+] or the peak amplitude of nicotinic acetylcholine receptor currents, but it did inhibit CaV2 voltage-gated Ca2+ channel currents (ICa). This inhibition was voltage-dependent and mediated by pertussis toxin-sensitive G proteins, consistent with a direct Gβγ subunit-mediated mechanism common to other Gi/o-coupled receptors. mRNA for all four EP receptors was detected, but using selective pharmacological tools and EP receptor knockout mice, we demonstrated that EP3 receptors mediate the inhibition of ICa. Finally, changes in membrane capacitance showed that Ca2+-dependent exocytosis was reduced in parallel with ICa. To our knowledge, this is the first study of EP receptor signaling in mouse chromaffin cells and identifies a molecular mechanism for paracrine regulation of neuroendocrine function by PGE2. PMID:21383044

Observed circuit limits to time resolution in correlation measurements with Si-on-sapphire, GaAs, and InP picosecond photoconductors

NASA Astrophysics Data System (ADS)

Hammond, R. B.; Paulter, N. G.; Wagner, R. S.

1984-08-01

Cross-correlation measurements of the response of photoconductor pulsers and sampling gates excited by a femtosecond laser are reported. The photoconductors were fabricated in microstrip transmission line structures on Si-on-sapphire, semiinsulating GaAs, and semiinsulating InP wafers. The photoconductor sampling gates were ion beam-damaged to produce short carrier lifetimes (less than 3 ps in one case). Damage was introduced with 6 MeV Ne-20 on the Si-on-sapphire, 2 MeV H-2 on the GaAs, and 2 MeV He-4 on the InP. Doses in the range 10 to the 12th - 10 to the 15th were used. Results show circuit limits to the time resolution in correlation measurements from two sources: (1) RC time constants due to photoconductor gap capacitance and transmission line characteristic impedance and (2) dispersion in microstrip transmission lines.

Fabrication and characterization of physically defined quantum dots on a boron-doped silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Mizoguchi, Seiya; Shimatani, Naoki; Kobayashi, Mizuki; Makino, Takaomi; Yamaoka, Yu; Kodera, Tetsuo

2018-04-01

We study hole transport properties in physically defined p-type silicon quantum dots (QDs) on a heavily doped silicon-on-insulator (SOI) substrate. We observe Coulomb diamonds using single QDs and estimate the charging energy as ∼1.6 meV. We obtain the charge stability diagram of double QDs using single QDs as a charge sensor. This is the first demonstration of charge sensing in p-type heavily doped silicon QDs. For future time-resolved measurements, we apply radio-frequency reflectometry using impedance matching of LC circuits to the device. We observe the resonance and estimate the capacitance as ∼0.12 pF from the resonant frequency. This value is smaller than that of the devices with top gates on nondoped SOI substrate. This indicates that high-frequency signals can be applied efficiently to p-type silicon QDs without top gates.

Ferroelectric polarization induces electric double layer bistability in electrolyte-gated field-effect transistors.

PubMed

Fabiano, Simone; Crispin, Xavier; Berggren, Magnus

2014-01-08

The dense surface charges expressed by a ferroelectric polymeric thin film induce ion displacement within a polyelectrolyte layer and vice versa. This is because the density of dipoles along the surface of the ferroelectric thin film and its polarization switching time matches that of the (Helmholtz) electric double layers formed at the ferroelectric/polyelectrolyte and polyelectrolyte/semiconductor interfaces. This combination of materials allows for introducing hysteresis effects in the capacitance of an electric double layer capacitor. The latter is advantageously used to control the charge accumulation in the semiconductor channel of an organic field-effect transistor. The resulting memory transistors can be written at a gate voltage of around 7 V and read out at a drain voltage as low as 50 mV. The technological implication of this large difference between write and read-out voltages lies in the non-destructive reading of this ferroelectric memory.

Experimental evidence for the correlation between the weak inversion hump and near midgap states in dielectric/InGaAs interfaces

NASA Astrophysics Data System (ADS)

Krylov, Igor; Kornblum, Lior; Gavrilov, Arkady; Ritter, Dan; Eizenberg, Moshe

2012-04-01

Temperature dependent capacitance-voltage (C-V) and conductance-voltage (G-V) measurements were performed to obtain activation energies (EA) for weak inversion C-V humps and parallel conductance peaks in Al2O3/InGaAs and Si3N4/InGaAs gate stacks. Values of 0.48 eV (slightly more than half of the band gap of the studied In0.53Ga0.47As) were obtained for EA of both phenomena for both gate dielectrics studied. This indicates an universal InGaAs behavior and shows that both phenomena are due to generation-recombination of minority carriers through near midgap located interface states. The C-V hump correlates with the interface states density (Dit) and can be used as a characterization tool for dielectric/InGaAs systems.

Increasing the dynamic range of CMOS photodiode imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor)

2007-01-01

A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.

A Self-Aligned InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated through a Lift-Off-Free Front-End Process

NASA Astrophysics Data System (ADS)

Lin, Jianqiang; Kim, Tae-Woo; Antoniadis, Dimitri A.; del Alamo, Jesús A.

2012-06-01

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm2 V-1 s-1.

Porous NiCo2O4 nanosheets/reduced graphene oxide composite: facile synthesis and excellent capacitive performance for supercapacitors.

PubMed

Ma, Lianbo; Shen, Xiaoping; Ji, Zhenyuan; Cai, Xiaoqing; Zhu, Guoxing; Chen, Kangmin

2015-02-15

A composite with porous NiCo2O4 nanosheets attached on reduced graphene oxide (RGO) sheets is synthesized through a facile solution-based method combined with a simple thermal annealing process. The capacitive performances of the as-prepared NiCo2O4/RGO (NCG) composites as electrode materials are investigated. It is found that the NCG composites exhibit a high specific capacitance up to 1186.3 F g(-1) at the current density of 0.5 A g(-1), and superior cycling stability with about 97% of the initial capacitance after 100 cycles. The greatly enhanced capacitive performance of the NCG electrode can be attributed to the existence of RGO support, which serves as both conductive channels and active interface. The approach used in the synthesis provides a facile route for preparing graphene-binary metal oxide electrode materials. The remarkable capacitive performance of NCG composites will undoubtedly make them be attractive for high performance energy storage applications. Copyright © 2014 Elsevier Inc. All rights reserved.

Surface and Interface Chemistry for Gate Stacks on Silicon

NASA Astrophysics Data System (ADS)

Frank, M. M.; Chabal, Y. J.

This chapter addresses the fundamental silicon surface science associated with the continued progress of nanoelectronics along the path prescribed by Moore's law. Focus is on hydrogen passivation layers and on ultrathin oxide films encountered during silicon cleaning and gate stack formation in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs). Three main topics are addressed. (i) First, the current practices and understanding of silicon cleaning in aqueous solutions are reviewed, including oxidizing chemistries and cleans leading to a hydrogen passivation layer. The dependence of the final surface termination and morphology/roughness on reactant choice and pH and the influence of impurities such as dissolved oxygen or metal ions are discussed. (ii) Next, the stability of hydrogen-terminated silicon in oxidizing liquid and gas phase environments is considered. In particular, the remarkable stability of hydrogen-terminated silicon surface in pure water vapor is discussed in the context of atomic layer deposition (ALD) of high-permittivity (high-k) gate dielectrics where water is often used as an oxygen precursor. Evidence is also provided for co-operative action between oxygen and water vapor that accelerates surface oxidation in humid air. (iii) Finally, the fabrication of hafnium-, zirconium- and aluminum-based high-k gate stacks is described, focusing on the continued importance of the silicon/silicon oxide interface. This includes a review of silicon surface preparation by wet or gas phase processing and its impact on high-k nucleation during ALD growth, and the consideration of gate stack capacitance and carrier mobility. In conclusion, two issues are highlighted: the impact of oxygen vacancies on the electrical characteristics of high-k MOS devices, and the way alloyed metal ions (such as Al in Hf-based gate stacks) in contact with the interfacial silicon oxide layer can be used to control flatband and threshold voltages.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Nanowire FET Based Neural Element for Robotic Tactile Sensing Skin

PubMed Central

Taube Navaraj, William; García Núñez, Carlos; Shakthivel, Dhayalan; Vinciguerra, Vincenzo; Labeau, Fabrice; Gregory, Duncan H.; Dahiya, Ravinder

2017-01-01

This paper presents novel Neural Nanowire Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in electronic skin (e-skin). The viability of Si nanowires (NWs) as the active material for υ-NWFETs in HNN is explored through modeling and demonstrated by fabricating the first device. Using υ-NWFETs to realize HNNs is an interesting approach as by printing NWs on large area flexible substrates it will be possible to develop a bendable tactile skin with distributed neural elements (for local data processing, as in biological skin) in the backplane. The modeling and simulation of υ-NWFET based devices show that the overlapping areas between individual gates and the floating gate determines the initial synaptic weights of the neural network - thus validating the working of υ-NWFETs as the building block for HNN. The simulation has been further extended to υ-NWFET based circuits and neuronal computation system and this has been validated by interfacing it with a transparent tactile skin prototype (comprising of 6 × 6 ITO based capacitive tactile sensors array) integrated on the palm of a 3D printed robotic hand. In this regard, a tactile data coding system is presented to detect touch gesture and the direction of touch. Following these simulation studies, a four-gated υ-NWFET is fabricated with Pt/Ti metal stack for gates, source and drain, Ni floating gate, and Al2O3 high-k dielectric layer. The current-voltage characteristics of fabricated υ-NWFET devices confirm the dependence of turn-off voltages on the (synaptic) weight of each gate. The presented υ-NWFET approach is promising for a neuro-robotic tactile sensory system with distributed computing as well as numerous futuristic applications such as prosthetics, and electroceuticals. PMID:28979183

A Power-Efficient Capacitive Read-Out Circuit With Parasitic-Cancellation for MEMS Cochlea Sensors.

PubMed

Wang, Shiwei; Koickal, Thomas Jacob; Hamilton, Alister; Mastropaolo, Enrico; Cheung, Rebecca; Abel, Andrew; Smith, Leslie S; Wang, Lei

2016-02-01

This paper proposes a solution for signal read-out in the MEMS cochlea sensors that have very small sensing capacitance and do not have differential sensing structures. The key challenge in such sensors is the significant signal degradation caused by the parasitic capacitance at the MEMS-CMOS interface. Therefore, a novel capacitive read-out circuit with parasitic-cancellation mechanism is developed; the equivalent input capacitance of the circuit is negative and can be adjusted to cancel the parasitic capacitance. Chip results prove that the use of parasitic-cancellation is able to increase the sensor sensitivity by 35 dB without consuming any extra power. In general, the circuit follows a low-degradation low-amplification approach which is more power-efficient than the traditional high-degradation high-amplification approach; it employs parasitic-cancellation to reduce the signal degradation and therefore a lower gain is required in the amplification stage. Besides, the chopper-stabilization technique is employed to effectively reduce the low-frequency circuit noise and DC offsets. As a result of these design considerations, the prototype chip demonstrates the capability of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output at the cost of only 165.2 μW power consumption.

Transparent Flexible Active Faraday Cage Enables In Vivo Capacitance Measurement in Assembled Microsensor.

PubMed

Ahmadi, Mahdi; Rajamani, Rajesh; Sezen, Serdar

2017-10-01

Capacitive micro-sensors such as accelerometers, gyroscopes and pressure sensors are increasingly used in the modern electronic world. However, the in vivo use of capacitive sensing for measurement of pressure or other variables inside a human body suffers from significant errors due to stray capacitance. This paper proposes a solution consisting of a transparent thin flexible Faraday cage that surrounds the sensor. By supplying the active sensing voltage simultaneously to the deformable electrode of the capacitive sensor and to the Faraday cage, the stray capacitance during in vivo measurements can be largely eliminated. Due to the transparency of the Faraday cage, the top and bottom portions of a capacitive sensor can be accurately aligned and assembled together. Experimental results presented in the paper show that stray capacitance is reduced by a factor of 10 by the Faraday cage, when the sensor is subjected to a full immersion in water.

Low temperature growth and electrical characterization of insulators for GaAs MISFETS

NASA Technical Reports Server (NTRS)

Borrego, J. M.; Ghandhi, S. K.

1981-01-01

Progress in the low temperature growth of oxides and layers on GaAs and the detailed electrical characterization of these oxides is reported. A plasma anodization system was designed, assembled, and put into operation. A measurement system was assembled for determining capacitance and conductance as a function of gate voltage for frequencies in the range from 1 Hz to 1 MHz. Initial measurements were carried out in Si-SiO2 capacitors in order to test the system and in GaAs MIS capacitors abricated using liquid anodization.

Complex oxide thin films for microelectronics

NASA Astrophysics Data System (ADS)

Suvorova, Natalya

The rapid scaling of the device dimensions, namely in metal oxide semiconductor field effect transistor (MOSFET), is reaching its fundamental limit which includes the increase in allowable leakage current due to direct tunneling with decrease of physical thickness of SiO2 gate dielectric. The significantly higher relative dielectric constant (in the range 9--25) of the gate dielectric beyond the 3.9 value of silicon dioxide will allow increasing the physical thickness. Among the choices for the high dielectric constant (K) materials for future generation MOSFET application, barium strontium titanate (BST) and strontium titanate (STO) possess one of the highest attainable K values making them the promising candidates for alternative gate oxide. However, the gate stack engineering does not imply the simple replacement of the SiO2 with the new dielectric. Several requirements should be met for successful integration of a new material. The major one is a production of high level of interface states (Dit) compared to that of SiO 2 on Si. An insertion of a thin SiO2 layer prior the growth of high-K thin film is a simple solution that helps to limit reaction with Si substrate and attains a high quality interface. However, the combination of two thin films reduces the overall K of the dielectric stack. An optimization of the SiO2 underlayer in order to maintain the interface quality yet minimize the effect on K is the focus of this work. The results from our study are presented with emphasis on the key process parameters that improve the dielectric film stack. For in-situ growth characterization of BST and STO films sputter deposited on thermally oxidized Si substrates spectroscopic ellipsometry in combination with time of flight ion scattering and recoil spectrometry have been employed. Studies of material properties have been complemented with analytical electron microscopy. To evaluate the interface quality the electrical characterization has been employed using capacitance-voltage and conductance-voltage measurements. Special attention was given to the extraction of static dielectric constant of BST and STO from the multiple film stack. The K value was found to be sensitive to the input parameters such as dielectric constant and thickness of interface layers.

Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng

2014-11-17

Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. Withmore » a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.« less

Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform

NASA Astrophysics Data System (ADS)

Anand, Sunny; Sarin, R. K.

2016-09-01

In this paper for the first time, InAs based doping-less Tunnel FET is proposed and investigated. This paper also demonstrates and discusses the impact of gate stacking (SiO2 + HfO2) with equivalent oxide thickness EOT = 0.8 for analog/RF performance. The charge plasma technique is used to form source/drain region on an intrinsic InAs body by selecting proper work function of metal electrode. The paper compares different combinations of gate stacking (SiO2 and HfO2) on the basis of different analog and RF parameters such as transconductance (gm), transconductance to drive current ratio (gm/ID), output conductance (gd), intrinsic gain (AV), total gate capacitance (Cgg) and unity-gain cutoff frequency (fT). The proposed device produces an ON state current of ION ∼6 mA along with ION/IOFF ∼1012, point subthreshold slope (SS ∼ 1.9 mV/dec), average subthreshold slope (AV-SS ∼ 14.2 mV/dec) and cut-off frequency in Terahertz. The focus of this work is to eliminate the fabrication issues and providing the enhanced performance compared to doped device.

Flexible capacitive behavior of hybrid carbon materials prepared from graphene sheets

NASA Astrophysics Data System (ADS)

Ding, Y.-H.; Xie, W.; Zhang, P.; Jiang, Y.

2016-06-01

High frequency ultrasonication was employed to reduce the aggregation of graphene by constructing hybrid carbon materials (HCMs), which are endowed with a large electrochemical reaction area and high energy density. HCMs exhibited a specific capacitance of 168.5 F · g-1 with ˜100% capacitance retention over 500 cycles. Flexible supercapacitors fabricated from HCMs also showed an excellent capacitive behavior even under tough conditions. These outstanding electrochemical properties were ascribed to the increased specific surface area and open structure of HCMs.

Acute effect of L-arginine on hemodynamics and vascular capacitance in the canine pacing model of heart failure.

PubMed

Ogilvie, R I; Zborowska-Sluis, D

1995-09-01

The effect of L-arginine, 250 mg/kg over 10 min, on hemodynamics and venous function was studied in nine splenectomized dogs under light pentobarbital anesthesia before and after 17 +/- 1 days of rapid right ventricular pacing (RRVP) at 250 beats/min. Chronic RRVP induced mild congestive heart failure with increased mean circulatory filling (Pmcf), right atrial (Pra) and pulmonary capillary wedge pressures (Ppcw), and reduced cardiac output (CO). During the development of heart failure, total vascular compliance assessed from Pmcf-blood volume relationships during circulatory arrest was unchanged, but total vascular capacitance was markedly reduced, with an increase in stressed and reduction in unstressed blood volumes. At baseline but not after RRVP, L-arginine increased CO and reduced pulmonary vascular resistance. There were no significant changes in Pra, Ppcw, or total peripheral resistance. L-Arginine failed to alter total vascular compliance and capacitance or central blood volume in the baseline or failure state. These results do not support the hypothesis that increased Pmcf and reduced total vascular capacitance in the early stages of pacing-induced heart failure are caused by reduced substrate availability for or an endogenous competitive antagonist of NO synthase in venous endothelial cells.

Voltage Gated Ion Channel Function: Gating, Conduction, and the Role of Water and Protons

PubMed Central

Kariev, Alisher M.; Green, Michael E.

2012-01-01

Ion channels, which are found in every biological cell, regulate the concentration of electrolytes, and are responsible for multiple biological functions, including in particular the propagation of nerve impulses. The channels with the latter function are gated (opened) by a voltage signal, which allows Na+ into the cell and K+ out. These channels have several positively charged amino acids on a transmembrane domain of their voltage sensor, and it is generally considered, based primarily on two lines of experimental evidence, that these charges move with respect to the membrane to open the channel. At least three forms of motion, with greatly differing extents and mechanisms of motion, have been proposed. There is a “gating current”, a capacitative current preceding the channel opening, that corresponds to several charges (for one class of channel typically 12–13) crossing the membrane field, which may not require protein physically crossing a large fraction of the membrane. The coupling to the opening of the channel would in these models depend on the motion. The conduction itself is usually assumed to require the “gate” of the channel to be pulled apart to allow ions to enter as a section of the protein partially crosses the membrane, and a selectivity filter at the opposite end of the channel determines the ion which is allowed to pass through. We will here primarily consider K+ channels, although Na+ channels are similar. We propose that the mechanism of gating differs from that which is generally accepted, in that the positively charged residues need not move (there may be some motion, but not as gating current). Instead, protons may constitute the gating current, causing the gate to open; opening consists of only increasing the diameter at the gate from approximately 6 Å to approximately 12 Å. We propose in addition that the gate oscillates rather than simply opens, and the ion experiences a barrier to its motion across the channel that is tuned by the water present within the channel. Our own quantum calculations as well as numerous experiments of others are interpreted in terms of this hypothesis. It is also shown that the evidence that supports the motion of the sensor as the gating current can also be consistent with the hypothesis we present. PMID:22408417

The Role of Ion Exchange Membranes in Membrane Capacitive Deionisation.

PubMed

Hassanvand, Armineh; Wei, Kajia; Talebi, Sahar; Chen, George Q; Kentish, Sandra E

2017-09-14

Ion-exchange membranes (IEMs) are unique in combining the electrochemical properties of ion exchange resins and the permeability of a membrane. They are being used widely to treat industrial effluents, and in seawater and brackish water desalination. Membrane Capacitive Deionisation (MCDI) is an emerging, energy efficient technology for brackish water desalination in which these ion-exchange membranes act as selective gates allowing the transport of counter-ions toward carbon electrodes. This article provides a summary of recent developments in the preparation, characterization, and performance of ion exchange membranes in the MCDI field. In some parts of this review, the most relevant literature in the area of electrodialysis (ED) is also discussed to better elucidate the role of the ion exchange membranes. We conclude that more work is required to better define the desalination performance of the proposed novel materials and cell designs for MCDI in treating a wide range of feed waters. The extent of fouling, the development of cleaning strategies, and further techno-economic studies, will add value to this emerging technique.

Local epitaxial growth of ZrO2 on Ge (100) substrates by atomic layer epitaxy

NASA Astrophysics Data System (ADS)

Kim, Hyoungsub; Chui, Chi On; Saraswat, Krishna C.; McIntyre, Paul C.

2003-09-01

High-k dielectric deposition processes for gate dielectric preparation on Si surfaces usually result in the unavoidable and uncontrolled formation of a thin interfacial oxide layer. Atomic layer deposition of ˜55-Å ZrO2 film on a Ge (100) substrate using ZrCl4 and H2O at 300 °C was found to produce local epitaxial growth [(001) Ge//(001) ZrO2 and [100] Ge//[100] ZrO2] without a distinct interfacial layer, unlike the situation observed when ZrO2 is deposited using the same method on Si. Relatively large lattice mismatch (˜10%) between ZrO2 and Ge produced a high areal density of interfacial misfit dislocations. Large hysteresis (>200 mV) and high frequency dispersion were observed in capacitance-voltage measurements due to the high density of interface states. However, a low leakage current density, comparable to values obtained on Si substrates, was observed with the same capacitance density regardless of the high defect density.

Size dependence in tunneling spectra of PbSe quantum-dot arrays.

PubMed

Ou, Y C; Cheng, S F; Jian, W B

2009-07-15

Interdot Coulomb interactions and collective Coulomb blockade were theoretically argued to be a newly important topic, and experimentally identified in semiconductor quantum dots, formed in the gate confined two-dimensional electron gas system. Developments of cluster science and colloidal synthesis accelerated the studies of electron transport in colloidal nanocrystal or quantum-dot solids. To study the interdot coupling, various sizes of two-dimensional arrays of colloidal PbSe quantum dots are self-assembled on flat gold surfaces for scanning tunneling microscopy and scanning tunneling spectroscopy measurements at both room and liquid-nitrogen temperatures. The tip-to-array, array-to-substrate, and interdot capacitances are evaluated and the tunneling spectra of quantum-dot arrays are analyzed by the theory of collective Coulomb blockade. The current-voltage of PbSe quantum-dot arrays conforms properly to a scaling power law function. In this study, the dependence of tunneling spectra on the sizes (numbers of quantum dots) of arrays is reported and the capacitive coupling between quantum dots in the arrays is explored.

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

PubMed Central

Park, Jae Hyo; Jang, Gil Su; Kim, Hyung Yoon; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Joo, Seung Ki

2016-01-01

Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at −0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm2/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature. PMID:27098115

Conducted noise analysis and protection of 45 kJ/s, ±50 kV capacitor charging power supply when interfaced with repetitive Marx based pulse power system.

PubMed

Naresh, P; Patel, Ankur; Sharma, Archana

2015-09-01

Pulse power systems with highly dynamic loads like klystron, backward wave oscillator (BWO), and magnetron generate highly dynamic noise. This noise leads to frequent failure of controlled switches in the inverter stage of charging power supply. Designing a reliable and compatible power supply for pulse power applications is always a tricky job when charging rate is in multiples of 10 kJ/s. A ±50 kV and 45 kJ/s capacitor charging power supply based on 4th order LCLC resonant topology has been developed for a 10 Hz repetitive Marx based system. Conditions for load independent constant current and zero current switching (ZCS) are derived mathematically. Noise generated at load end due to dynamic load is tackled effectively and reduction in magnitude noise voltage is achieved by providing shielding between primary and secondary of high voltage high frequency transformer and with LCLC low pass filter. Shielding scales down the ratio between coupling capacitance (Cc) and the collector-emitter capacitance of insulated gate bi-polar transistor switch, which in turn reduces the common mode noise voltage magnitude. The proposed 4th order LCLC resonant network acts as a low pass filter for differential mode noise in the reverse direction (from load to source). Power supply has been tested repeatedly with 5 Hz repetition rate with repetitive Marx based system connected with BWO load working fine without failure of single switch in the inverter stage.

Conducted noise analysis and protection of 45 kJ/s, ±50 kV capacitor charging power supply when interfaced with repetitive Marx based pulse power system

NASA Astrophysics Data System (ADS)

Naresh, P.; Patel, Ankur; Sharma, Archana

2015-09-01

Pulse power systems with highly dynamic loads like klystron, backward wave oscillator (BWO), and magnetron generate highly dynamic noise. This noise leads to frequent failure of controlled switches in the inverter stage of charging power supply. Designing a reliable and compatible power supply for pulse power applications is always a tricky job when charging rate is in multiples of 10 kJ/s. A ±50 kV and 45 kJ/s capacitor charging power supply based on 4th order LCLC resonant topology has been developed for a 10 Hz repetitive Marx based system. Conditions for load independent constant current and zero current switching (ZCS) are derived mathematically. Noise generated at load end due to dynamic load is tackled effectively and reduction in magnitude noise voltage is achieved by providing shielding between primary and secondary of high voltage high frequency transformer and with LCLC low pass filter. Shielding scales down the ratio between coupling capacitance (Cc) and the collector-emitter capacitance of insulated gate bi-polar transistor switch, which in turn reduces the common mode noise voltage magnitude. The proposed 4th order LCLC resonant network acts as a low pass filter for differential mode noise in the reverse direction (from load to source). Power supply has been tested repeatedly with 5 Hz repetition rate with repetitive Marx based system connected with BWO load working fine without failure of single switch in the inverter stage.

Noncovalently-functionalized reduced graphene oxide sheets by water-soluble methyl green for supercapacitor application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ren, Xiaoying; Hu, Zhongai, E-mail: zhongai@nwnu.edu.cn; Hu, Haixiong

2015-10-15

Graphical abstract: Electroactive methyl green (MG) is selected to functionalize reduced graphene oxide (RGO) through non-covalent modification and the composite achieves high specific capacitance, good rate capability and excellent long life cycle. - Highlights: • MG–RGO composites were firstly prepared through non-covalent modification. • The mass ratio in composites is a key for achieving high specific capacitance. • MG–RGO 5:4 exhibits the highest specific capacitance of 341 F g{sup −1}. • MG–RGO 5:4 shows excellent rate capability and long life cycle. - Abstract: In the present work, water-soluble electroactive methyl green (MG) has been used to non-covalently functionalize reduced graphenemore » oxide (RGO) for enhancing supercapacitive performance. The microstructure, composition and morphology of MG–RGO composites are systematically characterized by UV–vis absorption, field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM) and X-ray diffraction (XRD). The electrochemical performances are investigated by cyclic voltammetry (CV), galvanostatic charge/discharge and electrochemical impedance spectroscopy (EIS). The fast redox reactions from MG could generate additional pseudocapacitance, which endows RGO higher capacitances. As a result, the MG–RGO composite (with the 5:4 mass ratio of MG:RGO) achieve a maximum value of 341 F g{sup −1} at 1 A g{sup −1} within the potential range from −0.25 to 0.75 V and provide a 180% enhancement in specific capacitance in comparison with pure RGO. Furthermore, excellent rate capability (72% capacitance retention from 1 A g{sup −1} to 20 A g{sup −1}) and long life cycle (12% capacitance decay after 5000 cycles) are achieved for the MG–RGO composite electrode.« less

Nickel oxide film with open macropores fabricated by surfactant-assisted anodic deposition for high capacitance supercapacitors.

PubMed

Wu, Mao-Sung; Wang, Min-Jyle

2010-10-07

Nickel oxide film with open macropores prepared by anodic deposition in the presence of surfactant shows a very high capacitance of 1110 F g(-1) at a scan rate of 10 mV s(-1), and the capacitance value reduces to 950 F g(-1) at a high scan rate of 200 mV s(-1).

Study on the electrical degradation of AlGaN/GaN MIS-HEMTs induced by residual stress of SiNx passivation

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Liu, Yong; Xin, Qi; Liu, Yang; Yu, Qi

2017-07-01

In this paper, we report a new phenomenon in C-V measurement of different gate length MIS-HEMTs, which can be associated with traps character of the AlGaN/GaN interface. The analysis of DC measurement, frequency dependent capacitance-voltage measurements and simulation show that the stress from passivation layer may induce a decrease of drain output current Ids, an increase of on-resistance, serious nonlinearity of transconductance gm, and a new peak of C-V curve. The value of the peak is reduced to zero while the gate length and measure frequency are increasing to 21 μm and 1 MHz, respectively. By using conductance method, the SiNx/GaN interface traps with energy level of EC-0.42 eV to EC-0.45 eV and density of 3.2 × 1012 ∼ 5.0 × 1012 eV-1 cm-2 is obtained after passivation. According to the experimental and simulation results, formation of the acceptor-like traps with concentration of 3 × 1011 cm-2 and energy level of EC-0.37 eV under the gate on AlGaN barrier side of AlGaN/GaN interface is the main reason for the degradation after the passivation. He is currently an Associate Professor with State Key Laboratory of Electronic Thin Films and Integrated Devices, School of Microelectronics and Solid-State Electronics, UESTC. He is the author of over 30 peer-reviewed journal papers and more than 20 conference papers. He has also hold over 20 patents. His research interests include Gallium Nitride based high-voltage power switching devices, microwave and millimeter-wave power devices and integrated technologies. Dr. Yu was a recipient of the prestigious Award of Science and Technology of China

Computation of Dielectric Response in Molecular Solids for High Capacitance Organic Dielectrics.

PubMed

Heitzer, Henry M; Marks, Tobin J; Ratner, Mark A

2016-09-20

The dielectric response of a material is central to numerous processes spanning the fields of chemistry, materials science, biology, and physics. Despite this broad importance across these disciplines, describing the dielectric environment of a molecular system at the level of first-principles theory and computation remains a great challenge and is of importance to understand the behavior of existing systems as well as to guide the design and synthetic realization of new ones. Furthermore, with recent advances in molecular electronics, nanotechnology, and molecular biology, it has become necessary to predict the dielectric properties of molecular systems that are often difficult or impossible to measure experimentally. In these scenarios, it is would be highly desirable to be able to determine dielectric response through efficient, accurate, and chemically informative calculations. A good example of where theoretical modeling of dielectric response would be valuable is in the development of high-capacitance organic gate dielectrics for unconventional electronics such as those that could be fabricated by high-throughput printing techniques. Gate dielectrics are fundamental components of all transistor-based logic circuitry, and the combination high dielectric constant and nanoscopic thickness (i.e., high capacitance) is essential to achieving high switching speeds and low power consumption. Molecule-based dielectrics offer the promise of cheap, flexible, and mass producible electronics when used in conjunction with unconventional organic or inorganic semiconducting materials to fabricate organic field effect transistors (OFETs). The molecular dielectrics developed to date typically have limited dielectric response, which results in low capacitances, translating into poor performance of the resulting OFETs. Furthermore, the development of better performing dielectric materials has been hindered by the current highly empirical and labor-intensive pace of synthetic progress. An accurate and efficient theoretical computational approach could drastically decrease this time by screening potential dielectric materials and providing reliable design rules for future molecular dielectrics. Until recently, accurate calculation of dielectric responses in molecular materials was difficult and highly approximate. Most previous modeling efforts relied on classical formalisms to relate molecular polarizability to macroscopic dielectric properties. These efforts often vastly overestimated polarizability in the subject materials and ignored crucial material properties that can affect dielectric response. Recent advances in first-principles calculations via density functional theory (DFT) with periodic boundary conditions have allowed accurate computation of dielectric properties in molecular materials. In this Account, we outline the methodology used to calculate dielectric properties of molecular materials. We demonstrate the validity of this approach on model systems, capturing the frequency dependence of the dielectric response and achieving quantitative accuracy compared with experiment. This method is then used as a guide to new high-capacitance molecular dielectrics by determining what materials and chemical properties are important in maximizing dielectric response in self-assembled monolayers (SAMs). It will be seen that this technique is a powerful tool for understanding and designing new molecular dielectric systems, the properties of which are fundamental to many scientific areas.

Predictive of the quantum capacitance effect on the excitation of plasma waves in graphene transistors with scaling limit

NASA Astrophysics Data System (ADS)

Wang, Lin; Chen, Xiaoshuang; Hu, Yibin; Wang, Shao-Wei; Lu, Wei

2015-04-01

Plasma waves in graphene field-effect transistors (FETs) and nano-patterned graphene sheets have emerged as very promising candidates for potential terahertz and infrared applications in myriad areas including remote sensing, biomedical science, military, and many other fields with their electrical tunability and strong interaction with light. In this work, we study the excitations and propagation properties of plasma waves in nanometric graphene FETs down to the scaling limit. Due to the quantum-capacitance effect, the plasma wave exhibits strong correlation with the distribution of density of states (DOS). It is indicated that the electrically tunable plasma resonance has a power-dependent V0.8TG relation on the gate voltage, which originates from the linear dependence of density of states (DOS) on the energy in pristine graphene, in striking difference to those dominated by classical capacitance with only V0.5TG dependence. The results of different transistor sizes indicate the potential application of nanometric graphene FETs in highly-efficient electro-optic modulation or detection of terahertz or infrared radiation. In addition, we highlight the perspectives of plasma resonance excitation in probing the many-body interaction and quantum matter state in strong correlation electron systems. This study reveals the key feature of plasma waves in decorated/nanometric graphene FETs, and paves the way to tailor plasma band-engineering and expand its application in both terahertz and mid-infrared regions.Plasma waves in graphene field-effect transistors (FETs) and nano-patterned graphene sheets have emerged as very promising candidates for potential terahertz and infrared applications in myriad areas including remote sensing, biomedical science, military, and many other fields with their electrical tunability and strong interaction with light. In this work, we study the excitations and propagation properties of plasma waves in nanometric graphene FETs down to the scaling limit. Due to the quantum-capacitance effect, the plasma wave exhibits strong correlation with the distribution of density of states (DOS). It is indicated that the electrically tunable plasma resonance has a power-dependent V0.8TG relation on the gate voltage, which originates from the linear dependence of density of states (DOS) on the energy in pristine graphene, in striking difference to those dominated by classical capacitance with only V0.5TG dependence. The results of different transistor sizes indicate the potential application of nanometric graphene FETs in highly-efficient electro-optic modulation or detection of terahertz or infrared radiation. In addition, we highlight the perspectives of plasma resonance excitation in probing the many-body interaction and quantum matter state in strong correlation electron systems. This study reveals the key feature of plasma waves in decorated/nanometric graphene FETs, and paves the way to tailor plasma band-engineering and expand its application in both terahertz and mid-infrared regions. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr07689c

Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

NASA Astrophysics Data System (ADS)

Pradhan, K. P.; Priyanka; Sahu, P. K.

2016-01-01

Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

Gate-Induced Metal–Insulator Transition in MoS 2 by Solid Superionic Conductor LaF 3

DOE PAGES

Wu, Chun-Lan; Yuan, Hongtao; Li, Yanbin; ...

2018-03-23

Electric-double-layer (EDL) gating with liquid electrolyte has been a powerful tool widely used to explore emerging interfacial electronic phenomena. Due to the large EDL capacitance, a high carrier density up to 10 14 cm –2 can be induced, directly leading to the realization of field-induced insulator to metal (or superconductor) transition. However, the liquid nature of the electrolyte has created technical issues including possible side electrochemical reactions or intercalation, and the potential for huge strain at the interface during cooling. In addition, the liquid coverage of active devices also makes many surface characterizations and in situ measurements challenging. Here, wemore » demonstrate an all solid-state EDL device based on a solid superionic conductor LaF 3, which can be used as both a substrate and a fluorine ionic gate dielectric to achieve a wide tunability of carrier density without the issues of strain or electrochemical reactions and can expose the active device surface for external access. Based on LaF 3 EDL transistors (EDLTs), we observe the metal–insulator transition in MoS 2. Interestingly, the well-defined crystal lattice provides a more uniform potential distribution in the substrate, resulting in less interface electron scattering and therefore a higher mobility in MoS 2 transistors. Finally, this result shows the powerful gating capability of LaF 3 solid electrolyte for new possibilities of novel interfacial electronic phenomena.« less

Diamond field effect transistors with a high-dielectric constant Ta2O5 as gate material

NASA Astrophysics Data System (ADS)

Liu, J.-W.; Liao, M.-Y.; Imura, M.; Watanabe, E.; Oosato, H.; Koide, Y.

2014-06-01

A Ta2O5/Al2O3 bilayer gate oxide with a high-dielectric constant (high-k) has been successfully applied to a hydrogenated-diamond (H-diamond) metal-insulator-semiconductor field effect transistor (MISFET). The Ta2O5 layer is prepared by a sputtering-deposition (SD) technique on the Al2O3 buffer layer fabricated by an atomic layer deposition (ALD) technique. The ALD-Al2O3 plays an important role to eliminate plasma damage for the H-diamond surface during SD-Ta2O5 deposition. The dielectric constants of the SD-Ta2O5/ALD-Al2O3 bilayer and single SD-Ta2O5 are as large as 12.7 and 16.5, respectively. The k value of the single SD-Ta2O5 in this study is in good agreement with that of the SD-Ta2O5 on oxygen-terminated diamond. The capacitance-voltage characteristic suggests low interfacial trapped charge density for the SD-Ta2O5/ALD-Al2O3/H-diamond MIS diode. The MISFET with a gate length of 4 µm has a drain current maximum and an extrinsic transconductance of -97.7 mA mm-1 (normalized by gate width) and 31.0 ± 0.1 mS mm-1, respectively. The effective mobility in the H-diamond channel layer is found to be 70.1 ± 0.5 cm2 V-1 s-1.

Atomic layer deposited TaCy metal gates: Impact on microstructure, electrical properties, and work function on HfO2 high-k dielectrics

NASA Astrophysics Data System (ADS)

Triyoso, D. H.; Gregory, R.; Schaeffer, J. K.; Werho, D.; Li, D.; Marcus, S.; Wilk, G. D.

2007-11-01

TaCy has been reported to have the appropriate work function for negative metal-oxide semiconductor metal in high-k metal-oxide field-effect transistors. As device size continues to shrink, a conformal deposition for metal gate electrodes is needed. In this work, we report on the development and characterization of a novel TaCy process by atomic layer deposition (ALD). Detailed physical properties of TaCy films are studied using ellipsometry, a four-point probe, Rutherford backscattering spectrometry (RBS), x-ray photoelectron spectroscopy (XPS), and x-ray diffraction (XRD). RBS and XPS analysis indicate that TaCy films are near-stoichiometric, nitrogen free, and have low oxygen impurities. Powder XRD spectra showed that ALD films have a cubic microstructure. XPS carbon bonding studies revealed that little or no glassy carbon is present in the bulk of the film. Excellent electrical properties are obtained using ALD TaCy as a metal gate electrode. Well-behaved capacitance-voltage characteristics with ALD HfO2 gate dielectrics are demonstrated for TaCy thicknesses of 50, 100, and 250 Å. A low fixed charge (˜2-4×10-11 cm-2) is observed for all ALD HfO2/ALD TaCy devices. Increasing the thickness of ALD TaCy results in a decrease in work function (4.77 to 4.54 eV) and lower threshold voltages.

PVA:LiClO4: a robust, high Tg polymer electrolyte for adjustable ion gating of 2D materials

NASA Astrophysics Data System (ADS)

Kinder, Erich; Fullerton, Susan; CenterLow Energy Systems Technology Team

2015-03-01

Polymer electrolytes are an effective way to gate organic semiconductors and nanomaterials, such as nanotubes and 2D materials, by establishing an electrostatic double layer with large capacitance. Widely used solid electrolytes, such as those based on polyethylene oxide, have a glass transition temperature below room temperature. This permits relatively fast ion mobility at T = 23 °C, but requires a constant applied field to maintain a doping profile. Moreover, PEO-based electrolytes cannot withstand a variety of solvents, limiting its use. Here, we demonstrate a polymer electrolyte using polyvinyl alcohol (PVA) with Tg >23 °C, through which a doping profile can be defined by a potential applied when the polymer is heated above Tg, then ``locked-in'' by cooling the electrolyte to room temperature (

Measurement of Aharonov-Casher effect in a Josephson junction chain

NASA Astrophysics Data System (ADS)

Pop, Ioan Mihai; Lecocq, Florent; Pannetier, Bernard; Buisson, Olivier; Guichard, Wiebke

2011-03-01

We have recently measured the effect of superconducting phase-slips on the ground state of a Josephson junction chain and a rhombi chain. Here we report clear evidence of Aharonov-Casher effect in a chain of Josephson junctions. This phenomenon is the dual of the well known Aharonov-Bohm interference. Using a capacitively coupled gate to the islands of the chain, we induce oscillations of the supercurrent by tuning the polarization charges on the islands. We observe complex interference patterns for different quantum phase slip amplitudes, that we understand quantitatively as Aharonov-Casher vortex interferences. European STREP MIDAS.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

PubMed

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-05-25

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0 dBm and -25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10(-9) ) with an energy efficiency of 2 pJ/bit.

Electronic hardware design of electrical capacitance tomography systems.

PubMed

Saied, I; Meribout, M

2016-06-28

Electrical tomography techniques for process imaging are very prominent for industrial applications, such as the oil and gas industry and chemical refineries, owing to their ability to provide the flow regime of a flowing fluid within a relatively high throughput. Among the various techniques, electrical capacitance tomography (ECT) is gaining popularity due to its non-invasive nature and its capability to differentiate between different phases based on their permittivity distribution. In recent years, several hardware designs have been provided for ECT systems that have improved its resolution of measurements to be around attofarads (aF, 10(-18) F), or the number of channels, that is required to be large for some applications that require a significant amount of data. In terms of image acquisition time, some recent systems could achieve a throughput of a few hundred frames per second, while data processing time could be achieved in only a few milliseconds per frame. This paper outlines the concept and main features of the most recent front-end and back-end electronic circuits dedicated for ECT systems. In this paper, multiple-excitation capacitance polling, a front-end electronic technique, shows promising results for ECT systems to acquire fast data acquisition speeds. A highly parallel field-programmable gate array (FPGA) based architecture for a fast reconstruction algorithm is also described. This article is part of the themed issue 'Supersensing through industrial process tomography'. © 2016 The Author(s).

Three-dimensional reduced graphene oxide/polyaniline nanocomposite film prepared by diffusion driven layer-by-layer assembly for high-performance supercapacitors

NASA Astrophysics Data System (ADS)

Hong, Xiaodong; Zhang, Binbin; Murphy, Elizabeth; Zou, Jianli; Kim, Franklin

2017-03-01

As a simple and versatile method, diffusion driven Layer-by-Layer assembly (dd-LbL) is developed to assemble graphene oxide (GO) into three-dimensional (3D) structure. The assembled GO macrostructure can be reduced through a hydrothermal treatment and used as a high volumetric capacitance electrode in supercapacitors. In this report we use rGO framework created from dd-LbL as a scaffold for in situ polymerization of aniline within the pores of the framework to form rGO/polyaniline (rGO/PANI) composite. The rGO/PANI composite affords a robust and porous structure, which facilitates electrolyte diffusion and exhibits excellent electrochemical performance as binder-free electrodes in a sandwich-configuration supercapacitor. Combining electric double layer capacitance and pseudo-capacitance, rGO/PANI electrodes exhibit a specific capacitance of 438.8 F g-1 at discharge rate of 5 mA (mass of electrodes were 10.0 mg, 0.5 A g-1) in 1 mol L-1 H2SO4 electrolyte; furthermore, the generated PANI nanoparticles in rGO template achieve a higher capacitance of 763 F g-1. The rGO/PANI composite electrodes also show an improved recyclability, 76.5% of capacitance retains after recycled 2000 times.

P-Channel InGaN/GaN heterostructure metal-oxide-semiconductor field effect transistor based on polarization-induced two-dimensional hole gas

PubMed Central

Zhang, Kexiong; Sumiya, Masatomo; Liao, Meiyong; Koide, Yasuo; Sang, Liwen

2016-01-01

The concept of p-channel InGaN/GaN heterostructure field effect transistor (FET) using a two-dimensional hole gas (2DHG) induced by polarization effect is demonstrated. The existence of 2DHG near the lower interface of InGaN/GaN heterostructure is verified by theoretical simulation and capacitance-voltage profiling. The metal-oxide-semiconductor FET (MOSFET) with Al2O3 gate dielectric shows a drain-source current density of 0.51 mA/mm at the gate voltage of −2 V and drain bias of −15 V, an ON/OFF ratio of two orders of magnitude and effective hole mobility of 10 cm2/Vs at room temperature. The normal operation of MOSFET without freeze-out at 8 K further proves that the p-channel behavior is originated from the polarization-induced 2DHG. PMID:27021054

A molecular orbital study of the energy spectrum, exchange interaction and gate crosstalk of a four-quantum-dot system

NASA Astrophysics Data System (ADS)

Yang, Xu-Chen; Wang, Xin

The manipulation of coupled quantum dot devices is crucial to scalable, fault-tolerant quantum computation. We present a theoretical study of a four-electron four-quantum-dot system based on molecular orbital methods, which depicts a pair of singlet-triplet (S-T) qubits. We find that while the two S-T qubits are coupled by the capacitive interaction when they are sufficiently far away, the admixture of wave functions undergoes a substantial change as the two S-T qubits get closer. We find that in certain parameter regime the exchange interaction may only be defined in the sense of an effective one when the computational basis states no longer dominate the eigenstates. We further discuss the gate crosstalk as a consequence of this wave function mixing. This work was supported by the Research Grants Council of the Hong Kong Special Administrative Region, China (No. CityU 21300116) and the National Natural Science Foundation of China (No. 11604277).

Design evaluation of graphene nanoribbon nanoelectromechanical devices

NASA Astrophysics Data System (ADS)

Lam, Kai-Tak; Stephen Leo, Marie; Lee, Chengkuo; Liang, Gengchiau

2011-07-01

Computational studies on nanoelectromechanical switches based on bilayer graphene nanoribbons (BGNRs) with different designs are presented in this work. By varying the interlayer distance via electrostatic means, the conductance of the BGNR can be changed in order to achieve ON-states and OFF-states, thereby mimicking the function of a switch. Two actuator designs based on the modified capacitive parallel plate (CPP) model and the electrostatic repulsive force (ERF) model are discussed for different applications. Although the CPP design provides a simple electrostatic approach to changing the interlayer distance of the BGNR, their switching gate bias VTH strongly depends on the gate area, which poses a limitation on the size of the device. In addition, there exists a risk of device failure due to static fraction between the mobile and fixed electrodes. In contrast, the ERF design can circumvent both issues with a more complex structure. Finally, optimizations of the devices are carried out in order to provide insights into the design considerations of these nanoelectromechanical switches.

Deposition and characterization of vanadium oxide based thin films for MOS device applications

NASA Astrophysics Data System (ADS)

Rakshit, Abhishek; Biswas, Debaleen; Chakraborty, Supratic

2018-04-01

Vanadium Oxide films are deposited on Si (100) substrate by reactive RF-sputtering of a pure Vanadium metallic target in an Argon-Oxygen plasma environment. The ratio of partial pressures of Argon to Oxygen in the sputtering-chamber is varied by controlling their respective flow rates and the resultant oxide films are obtained. MOS Capacitor based devices are then fabricated using the deposited oxide films. High frequency Capacitance-Voltage (C-V) and gate current-gate voltage (I-V) measurements reveal a significant dependence of electrical characteristics of the deposited films on their sputtering deposition parameters mainly, the relative content of Argon/Oxygen in the plasma chamber. A noteworthy change in the electrical properties is observed for the films deposited under higher relative oxygen content in the plasma atmosphere. Our results show that reactive sputtering serves as an indispensable deposition-setup for fabricating vanadium oxide based MOS devices tailor-made for Non-Volatile Memory (NVM) applications.

0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

NASA Astrophysics Data System (ADS)

Ikeda, Sho; Lee, Sang-Yeop; Ito, Hiroyuki; Ishihara, Noboru; Masu, Kazuya

2015-04-01

In this paper, we present a voltage-controlled oscillator (VCO), which achieves highly linear frequency tuning under a low supply voltage of 0.5 V. To obtain the linear frequency tuning of a VCO, the high linearity of the threshold voltage of a varactor versus its back-gate voltage is utilized. This enables the linear capacitance tuning of the varactor; thus, a highly linear VCO can be achieved. In addition, to decrease the power consumption of the VCO, a current-reuse structure is employed as a cross-coupled pair. The proposed VCO was fabricated using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. It shows the ratio of the maximum VCO gain (KVCO) to the minimum one to be 1.28. The dc power consumption is 0.33 mW at a supply voltage of 0.5 V. The measured phase noise at 10 MHz offset is -123 dBc/Hz at an output frequency of 5.8 GHz.

Fabrication of (NH4)2S passivated GaAs metal-insulator-semiconductor devices using low-frequency plasma-enhanced chemical vapor deposition

NASA Astrophysics Data System (ADS)

Jaouad, A.; Aimez, V.; Aktik, Ç.; Bellatreche, K.; Souifi, A.

2004-05-01

Metal-insulator-semiconductor (MIS) capacitors were fabricated on n-GaAs(100) substrate using (NH4)2S surface passivation and low-frequency plasma-enhanced chemical vapor deposited silicon nitride as gate insulators. The electrical properties of the fabricated MIS capacitors were analyzed using high-frequency capacitance-voltage and conductance-voltage measurements. The high concentration of hydrogen present during low-frequency plasma deposition of silicon nitride enhances the passivation of GaAs surface, leading to the unpinning of the Fermi level and to a good modulation of the surface potential by gate voltage. The electrical properties of the insulator-semiconductor interface are improved after annealing at 450 °C for 60 s, as a significant reduction of the interface fixed charges and of the interface states density is put into evidence. The minimum interface states density was found to be about 3×1011 cm-2 eV-1, as estimated by the Terman method. .

Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

2016-03-01

In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

Control of interfacial properties of Pr-oxide/Ge gate stack structure by introduction of nitrogen

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Kondo, Hiroki; Sakashita, Mitsuo; Nakatsuka, Osamu; Zaima, Shigeaki

2011-06-01

We have demonstrated the control of interfacial properties of Pr-oxide/Ge gate stack structure by the introduction of nitrogen. From C- V characteristics of Al/Pr-oxide/Ge 3N 4/Ge MOS capacitors, the interface state density decreases without the change of the accumulation capacitance after annealing. The TEM and TED measurements reveal that the crystallization of Pr-oxide is enhanced with annealing and the columnar structure of cubic-Pr 2O 3 is formed after annealing. From the depth profiles measured using XPS with Ar sputtering for the Pr-oxide/Ge 3N 4/Ge stack structure, the increase in the Ge component is not observed in a Pr-oxide film and near the interface between a Pr-oxide film and a Ge substrate. In addition, the N component segregates near the interface region, amorphous Pr-oxynitride (PrON) is formed at the interface. As a result, Pr-oxide/PrON/Ge stacked structure without the Ge-oxynitride interlayer is formed.

Richardson constant and electrostatics in transfer-free CVD grown few-layer MoS2/graphene barristor with Schottky barrier modulation >0.6eV

NASA Astrophysics Data System (ADS)

Jahangir, Ifat; Uddin, M. Ahsan; Singh, Amol K.; Koley, Goutam; Chandrashekhar, M. V. S.

2017-10-01

We demonstrate a large area MoS2/graphene barristor, using a transfer-free method for producing 3-5 monolayer (ML) thick MoS2. The gate-controlled diodes show good rectification, with an ON/OFF ratio of ˜103. The temperature dependent back-gated study reveals Richardson's coefficient to be 80.3 ± 18.4 A/cm2/K and a mean electron effective mass of (0.66 ± 0.15)m0. Capacitance and current based measurements show the effective barrier height to vary over a large range of 0.24-0.91 eV due to incomplete field screening through the thin MoS2. Finally, we show that this barristor shows significant visible photoresponse, scaling with the Schottky barrier height. A response time of ˜10 s suggests that photoconductive gain is present in this device, resulting in high external quantum efficiency.

Specific methodology for capacitance imaging by atomic force microscopy: A breakthrough towards an elimination of parasitic effects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Estevez, Ivan; Concept Scientific Instruments, ZA de Courtaboeuf, 2 rue de la Terre de Feu, 91940 Les Ulis; Chrétien, Pascal

2014-02-24

On the basis of a home-made nanoscale impedance measurement device associated with a commercial atomic force microscope, a specific operating process is proposed in order to improve absolute (in sense of “nonrelative”) capacitance imaging by drastically reducing the parasitic effects due to stray capacitance, surface topography, and sample tilt. The method, combining a two-pass image acquisition with the exploitation of approach curves, has been validated on sets of calibration samples consisting in square parallel plate capacitors for which theoretical capacitance values were numerically calculated.

Dynamic regulation of mechanosensitive channels: capacitance used to monitor patch tension in real time

NASA Astrophysics Data System (ADS)

Suchyna, Thomas M.; Besch, Steven R.; Sachs, Frederick

2004-03-01

All cells, from bacteria to human, are mechanically sensitive. The most rapid of these membrane protein transducers are mechanosensitive ion channels, ionic pores in the membrane that open and close in response to membrane tension. In specific sensory organs, these channels serve the senses of touch and hearing, and inform the central nervous system about the filling of hollow organs such as the bladder. Non-specialized cells use these channels to report on changes in cell volume and local strain. To preserve dynamic sensitivity, sensory receptors adapt to steady-state stimuli. Here we show that in rat astrocytes, the most abundant cells in the brain, this apparent adaptation to the stimulus is actually an inactivation. We have been able to track the time course of local strain by measuring attofarad changes in membrane capacitance and show that it is not correlated with loss of channel activity. The reduction in current with time is caused by an increased occupancy of low conductance states, and a reduction in the probability of opening, not a relaxation of local stress. The occupancy of these substates depends on the integrity of the cell's cytoplasm. However, while disruption of the cytoskeleton leads to a loss of inactivation, it leaves activation unaffected. The activation process is voltage-insensitive, closely correlated with changes in capacitance, and seems to arise solely from stress in the bilayer. The inactivation rate decreases with depolarization, and kinetic analysis suggests that the process involves multiple cytoplasmic ligands. Surprisingly, multivalent ions such as Gd+3 and Ca+2 that bind to the lipids and affect channel gating, do not affect the strain-induced increase in membrane capacitance; contrary to expectations, membrane elasticity is unchanged.

Plasma-induced highly efficient synthesis of boron doped reduced graphene oxide for supercapacitors.

PubMed

Li, Shaobo; Wang, Zhaofeng; Jiang, Hanmei; Zhang, Limei; Ren, Jingzheng; Zheng, Mingtao; Dong, Lichun; Sun, Luyi

2016-09-21

In this work, we presented a novel route to synthesize boron doped reduced graphene oxide (rGO) by using the dielectric barrier discharge (DBD) plasma technology under ambient conditions. The doping of boron (1.4 at%) led to a significant improvement in the capacitance of rGO and supercapacitors based on the as-synthesized B-rGO exhibited an outstanding specific capacitance.

A facile synthesis of reduced holey graphene oxide for supercapacitors.

PubMed

Hu, Xinjun; Bai, Dongchen; Wu, Yiqi; Chen, Songbo; Ma, Yu; Lu, Yue; Chao, Yuanzhi; Bai, Yongxiao

2017-12-12

Hydroxyl radicals (˙OH) generated from a UV/O 3 solution reaction is used to efficiently etch graphene oxide nanosheets under moderate conditions. Reduced holey graphene oxide is directly used as a supercapacitor electrode material and exhibits high specific capacitance (224 F g -1 at a current density of 1 A g -1 ) and high volumetric capacitance (up to 206 F cm -3 ).

Otoferlin acts as a Ca2+ sensor for vesicle fusion and vesicle pool replenishment at auditory hair cell ribbon synapses

PubMed Central

Goutman, Juan D; Auclair, Sarah Marie; Boutet de Monvel, Jacques; Tertrais, Margot; Emptoz, Alice; Parrin, Alexandre; Nouaille, Sylvie; Guillon, Marc; Sachse, Martin; Ciric, Danica; Bahloul, Amel; Hardelin, Jean-Pierre; Sutton, Roger Bryan; Avan, Paul; Krishnakumar, Shyam S; Rothman, James E

2017-01-01

Hearing relies on rapid, temporally precise, and sustained neurotransmitter release at the ribbon synapses of sensory cells, the inner hair cells (IHCs). This process requires otoferlin, a six C2-domain, Ca2+-binding transmembrane protein of synaptic vesicles. To decipher the role of otoferlin in the synaptic vesicle cycle, we produced knock-in mice (Otof Ala515,Ala517/Ala515,Ala517) with lower Ca2+-binding affinity of the C2C domain. The IHC ribbon synapse structure, synaptic Ca2+ currents, and otoferlin distribution were unaffected in these mutant mice, but auditory brainstem response wave-I amplitude was reduced. Lower Ca2+ sensitivity and delay of the fast and sustained components of synaptic exocytosis were revealed by membrane capacitance measurement upon modulations of intracellular Ca2+ concentration, by varying Ca2+ influx through voltage-gated Ca2+-channels or Ca2+ uncaging. Otoferlin thus functions as a Ca2+ sensor, setting the rates of primed vesicle fusion with the presynaptic plasma membrane and synaptic vesicle pool replenishment in the IHC active zone. PMID:29111973

Otoferlin acts as a Ca2+ sensor for vesicle fusion and vesicle pool replenishment at auditory hair cell ribbon synapses.

PubMed

Michalski, Nicolas; Goutman, Juan D; Auclair, Sarah Marie; Boutet de Monvel, Jacques; Tertrais, Margot; Emptoz, Alice; Parrin, Alexandre; Nouaille, Sylvie; Guillon, Marc; Sachse, Martin; Ciric, Danica; Bahloul, Amel; Hardelin, Jean-Pierre; Sutton, Roger Bryan; Avan, Paul; Krishnakumar, Shyam S; Rothman, James E; Dulon, Didier; Safieddine, Saaid; Petit, Christine

2017-11-07

Hearing relies on rapid, temporally precise, and sustained neurotransmitter release at the ribbon synapses of sensory cells, the inner hair cells (IHCs). This process requires otoferlin, a six C 2 -domain, Ca 2+ -binding transmembrane protein of synaptic vesicles. To decipher the role of otoferlin in the synaptic vesicle cycle, we produced knock-in mice ( Otof Ala515,Ala517/Ala515,Ala517 ) with lower Ca 2+ -binding affinity of the C 2 C domain. The IHC ribbon synapse structure, synaptic Ca 2+ currents, and otoferlin distribution were unaffected in these mutant mice, but auditory brainstem response wave-I amplitude was reduced. Lower Ca 2+ sensitivity and delay of the fast and sustained components of synaptic exocytosis were revealed by membrane capacitance measurement upon modulations of intracellular Ca 2+ concentration, by varying Ca 2+ influx through voltage-gated Ca 2+ -channels or Ca 2+ uncaging. Otoferlin thus functions as a Ca 2+ sensor, setting the rates of primed vesicle fusion with the presynaptic plasma membrane and synaptic vesicle pool replenishment in the IHC active zone.

Redox regulation of mammalian sperm capacitation

PubMed Central

O’Flaherty, Cristian

2015-01-01

Capacitation is a series of morphological and metabolic changes necessary for the spermatozoon to achieve fertilizing ability. One of the earlier happenings during mammalian sperm capacitation is the production of reactive oxygen species (ROS) that will trigger and regulate a series of events including protein phosphorylation, in a time-dependent fashion. The identity of the sperm oxidase responsible for the production of ROS involved in capacitation is still elusive, and several candidates are discussed in this review. Interestingly, ROS-induced ROS formation has been described during human sperm capacitation. Redox signaling during capacitation is associated with changes in thiol groups of proteins located on the plasma membrane and subcellular compartments of the spermatozoon. Both, oxidation of thiols forming disulfide bridges and the increase on thiol content are necessary to regulate different sperm proteins associated with capacitation. Reducing equivalents such as NADH and NADPH are necessary to support capacitation in many species including humans. Lactate dehydrogenase, glucose-6-phospohate dehydrogenase, and isocitrate dehydrogenase are responsible in supplying NAD (P) H for sperm capacitation. Peroxiredoxins (PRDXs) are newly described enzymes with antioxidant properties that can protect mammalian spermatozoa; however, they are also candidates for assuring the regulation of redox signaling required for sperm capacitation. The dysregulation of PRDXs and of enzymes needed for their reactivation such as thioredoxin/thioredoxin reductase system and glutathione-S-transferases impairs sperm motility, capacitation, and promotes DNA damage in spermatozoa leading to male infertility. PMID:25926608

Impacts of oxidants in atomic layer deposition method on Al2O3/GaN interface properties

NASA Astrophysics Data System (ADS)

Taoka, Noriyuki; Kubo, Toshiharu; Yamada, Toshikazu; Egawa, Takashi; Shimizu, Mitsuaki

2018-01-01

The electrical interface properties of GaN metal-oxide-semiconductor (MOS) capacitors with an Al2O3 gate insulator formed by atomic layer deposition method using three kinds of oxidants were investigated by the capacitance-voltage technique, Terman method, and conductance method. We found that O3 and the alternate supply of H2O and O3 (AS-HO) are effective for reducing the interface trap density (D it) at the energy range of 0.15 to 0.30 eV taking from the conduction band minimum. On the other hand, we found that surface potential fluctuation (σs) induced by interface charges for the AS-HO oxidant is much larger than that for a Si MOS capacitor with a SiO2 layer formed by chemical vapor deposition despite the small D it values for the AS-HO oxidant compared with the Si MOS capacitor. This means that the total charged center density including the fixed charge density, charged slow trap density, and charged interface trap density for the GaN MOS capacitor is higher than that for the Si MOS capacitor. Therefore, σs has to be reduced to improve the performances and reliability of GaN devices with the Al2O3/GaN interfaces.

Nanocrystal-mediated charge screening effects in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, C. J.; Yeom, D. H.; Jeong, D. Y.; Lee, M. G.; Moon, B. M.; Kim, S. S.; Choi, C. Y.; Koo, S. M.

2009-03-01

ZnO nanowire field-effect transistors having an omega-shaped floating gate (OSFG) have been successfully fabricated by directly coating CdTe nanocrystals (˜6±2.5 nm) at room temperature, and compared to simultaneously prepared control devices without nanocrystals. Herein, we demonstrate that channel punchthrough may occur when the depletion from the OSFG takes place due to the trapped charges in the nanocrystals. Electrical measurements on the OSFG nanowire devices showed static-induction transistorlike behavior in the drain output IDS-VDS characteristics and a hysteresis window as large as ˜3.1 V in the gate transfer IDS-VGS characteristics. This behavior is ascribed to the presence of the CdTe nanocrystals, and is indicative of the trapping and emission of electrons in the nanocrystals. The numerical simulations clearly show qualitatively the same characteristics as the experimental data and confirm the effect, showing that the change in the potential distribution across the channel, induced by both the wrapping-around gate and the drain, affects the transport characteristics of the device. The cross-sectional energy band and potential profile of the OSFG channel corresponding to the "programed (noncharged)" and "erased (charged)" operations for the device are also discussed on the basis of the numerical capacitance-voltage simulations.

Gate dielectric surface treatments for performance improvement of poly(3-hexylthiophene-2,5-diyl) based organic field-effect transistors

NASA Astrophysics Data System (ADS)

Nawaz, Ali; de, Cristiane, , Col; Cruz-Cruz, Isidro; Kumar, Anshu; Kumar, Anil; Hümmelgen, Ivo A.

2015-08-01

We report on enhanced performance in poly(3-hexylthiophene-2,5-diyl) (P3HT) based organic field effect transistors (OFETs) achieved by improvement in hole transport along the channel near the insulator/semiconductor (I/S) interface. The improvement in hole transport is demonstrated to occur very close to the I/S interface, after treatment of the insulator layer with sodium dodecyl sulfate (SDS). SDS is an anionic surfactant, with negatively charged heads, known for formation of micelles above critical micelle concentration (CMC), which contribute to the passivation of positively charged traps. Investigation of field-effect mobility (μFET) as a function of channel bottleneck thickness in OFETs reveals the favorable gate voltage regime where mobility is the highest. In addition, it shows that the gate dielectric surface treatment not only leads to an increase in mobility in that regime, but also displaces charge transport closer to the interface, hence pointing toward passivation of the charge traps at I/S interface. OFETs with SDS treatment were compared with untreated and vitamin C or hexadecyltrimethylammonium bromide (CTAB) treated OFETs. All the treatments resulted in significant improvements in specific dielectric capacitance, μFET, on/off current ratio and transconductance.

Electrically Small Folded Slot Antenna Utilizing Capacitive Loaded Slot Lines

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Ponchak, George E.; Merritt, Shane; Minor, John S.; Zorman, Christian A.

2007-01-01

This paper presents an electrically small, coplanar waveguide fed, folded slot antenna that uses capacitive loading. Several antennas are fabricated with and without capacitive loading to demonstrate the ability of this design approach to reduce the resonant frequency of the antenna, which is analogous to reducing the antenna size. The antennas are fabricated on Cu-clad Rogers Duriod(TM) 6006 with multilayer chip capacitors to load the antennas. Simulated and measured results show close agreement, thus, validating the approach. The electrically small antennas have a measured return loss greater than 15 dB and a gain of 5.4, 5.6, and 2.7 dBi at 4.3, 3.95, and 3.65 GHz, respectively.

One-step hydrothermal synthesis of three-dimensional porous Ni-Co sulfide/reduced graphene oxide composite with optimal incorporation of carbon nanotubes for high performance supercapacitors.

PubMed

Chiu, Cheng-Ting; Chen, Dong-Hwang

2018-04-27

Three-dimensional (3D) porous Ni-Co sulfide/reduced graphene oxide composite with the appropriate incorporation of carbon nanotubes (NCS/rGO/CNT) was fabricated as a promising material for supercapacitor electrodes. It combined the high pseudo-capacitance of Ni-Co sulfide as well as the large specific surface area and electrical double layer capacitance of reduced graphene oxide (rGO). Carbon nanotubes (CNTs) were incorporated to act as the spacer for hindering the restacking of rGO and to construct a conductive network for enhancing the electron transport. The 3D porous NCS/rGO/CNT composite was fabricated by a facile one-step hydrothermal process in which Ni-Co sulfide nanosheets were synthesized and graphene oxide was reduced simultaneously. It was shown that the capacitance and cyclic performance indeed could be effectively improved via the appropriate addition of CNTs. In addition, a flexible all-solid-state asymmetric supercapacitor based on the NCS/rGO/CNT electrode was fabricated and exhibited the same capacitive electrochemical performance under bending. Also, it could successfully turn on a light-emitting diode light, revealing its feasibility in practical application. All results demonstrated that the developed NCS/rGO/CNT composite has potential application in supercapacitors.

One-step hydrothermal synthesis of three-dimensional porous Ni-Co sulfide/reduced graphene oxide composite with optimal incorporation of carbon nanotubes for high performance supercapacitors

NASA Astrophysics Data System (ADS)

Chiu, Cheng-Ting; Chen, Dong-Hwang

2018-04-01

Three-dimensional (3D) porous Ni-Co sulfide/reduced graphene oxide composite with the appropriate incorporation of carbon nanotubes (NCS/rGO/CNT) was fabricated as a promising material for supercapacitor electrodes. It combined the high pseudo-capacitance of Ni-Co sulfide as well as the large specific surface area and electrical double layer capacitance of reduced graphene oxide (rGO). Carbon nanotubes (CNTs) were incorporated to act as the spacer for hindering the restacking of rGO and to construct a conductive network for enhancing the electron transport. The 3D porous NCS/rGO/CNT composite was fabricated by a facile one-step hydrothermal process in which Ni-Co sulfide nanosheets were synthesized and graphene oxide was reduced simultaneously. It was shown that the capacitance and cyclic performance indeed could be effectively improved via the appropriate addition of CNTs. In addition, a flexible all-solid-state asymmetric supercapacitor based on the NCS/rGO/CNT electrode was fabricated and exhibited the same capacitive electrochemical performance under bending. Also, it could successfully turn on a light-emitting diode light, revealing its feasibility in practical application. All results demonstrated that the developed NCS/rGO/CNT composite has potential application in supercapacitors.

The Role of Ion Exchange Membranes in Membrane Capacitive Deionisation

PubMed Central

Hassanvand, Armineh; Wei, Kajia; Talebi, Sahar

2017-01-01

Ion-exchange membranes (IEMs) are unique in combining the electrochemical properties of ion exchange resins and the permeability of a membrane. They are being used widely to treat industrial effluents, and in seawater and brackish water desalination. Membrane Capacitive Deionisation (MCDI) is an emerging, energy efficient technology for brackish water desalination in which these ion-exchange membranes act as selective gates allowing the transport of counter-ions toward carbon electrodes. This article provides a summary of recent developments in the preparation, characterization, and performance of ion exchange membranes in the MCDI field. In some parts of this review, the most relevant literature in the area of electrodialysis (ED) is also discussed to better elucidate the role of the ion exchange membranes. We conclude that more work is required to better define the desalination performance of the proposed novel materials and cell designs for MCDI in treating a wide range of feed waters. The extent of fouling, the development of cleaning strategies, and further techno-economic studies, will add value to this emerging technique. PMID:28906442

Respiratory gating and multifield technique radiotherapy for esophageal cancer.

PubMed

Ohta, Atsushi; Kaidu, Motoki; Tanabe, Satoshi; Utsunomiya, Satoru; Sasamoto, Ryuta; Maruyama, Katsuya; Tanaka, Kensuke; Saito, Hirotake; Nakano, Toshimichi; Shioi, Miki; Takahashi, Haruna; Kushima, Naotaka; Abe, Eisuke; Aoyama, Hidefumi

2017-03-01

To investigate the effects of a respiratory gating and multifield technique on the dose-volume histogram (DVH) in radiotherapy for esophageal cancer. Twenty patients who underwent four-dimensional computed tomography for esophageal cancer were included. We retrospectively created the four treatment plans for each patient, with or without the respiratory gating and multifield technique: No gating-2-field, No gating-4-field, Gating-2-field, and Gating-4-field plans. We compared the DVH parameters of the lung and heart in the No gating-2-field plan with the other three plans. In the comparison of the parameters in the No gating-2-field plan, there are significant differences in the Lung V 5Gy , V 20Gy , mean dose with all three plans and the Heart V 25Gy -V 40Gy with Gating-2-field plan, V 35Gy , V 40Gy , mean dose with No Gating-4-field plan and V 30Gy -V 40Gy , and mean dose with Gating-4-field plan. The lung parameters were smaller in the Gating-2-field plan and larger in the No gating-4-field and Gating-4-field plans. The heart parameters were all larger in the No gating-2-field plan. The lung parameters were reduced by the respiratory gating technique and increased by the multifield technique. The heart parameters were reduced by both techniques. It is important to select the optimal technique according to the risk of complications.

Strategies for dynamic soft-landing in capacitive microelectromechanical switches

NASA Astrophysics Data System (ADS)

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad A.

2011-06-01

Electromechanical dielectric degradation associated with the hard landing of movable electrode is a technology-inhibiting reliability concern for capacitive RF-MEMS switches. In this letter, we propose two schemes for dynamic soft-landing that obviate the need for external feedback circuitry. Instead, the proposed resistive and capacitive braking schemes can reduce impact velocity significantly without compromising other performance characteristics like pull-in voltage and pull-in time. Resistive braking is achieved by inserting a resistance in series with the voltage source whereas capacitive braking requires patterning of the electrode or the dielectric. Our results have important implications to the design and optimization of reliability aware electrostatically actuated MEMS switches.

Carbon-polyaniline nanocomposites as supercapacitor materials

NASA Astrophysics Data System (ADS)

Sathish Kumar, M.; Yamini Yasoda, K.; Batabyal, Sudip Kumar; Kothurkar, Nikhil K.

2018-04-01

Polyaniline-based nanocomposites containing carbon nanotubes (CNT), reduced graphene oxide (rGO) and mixture of CNTs and rGO were synthesized. UV-visible spectroscopy and FT-IR spectroscopy confirmed the presence of polyaniline (PANi) and carbon nanomaterials. Scanning electron microscopy revealed that the neat PANi had a granular morphology, which can lead to increased electrical resistance to high interfacial resistance between domains of PANi. Cyclic voltammetry of PANi, PANi/CNT, PANi/rGO and PANi/CNT/rGO showed that in general, specific capacitance reduces with increasing scan rate within the range (10–100 mV s‑1). Also the specific capacitance values at any given scan rate within the above range, for PANi, PANi/CNT, PANi/rGO and PANi/CNT/rGO were found to be in increasing order. The specific capacitance of the PANi/CNT/rGO nanocomposite as measured by galvanostatic charge-discharge measurements, was found to be 312.5 F g‑1. The introduction of the carbon nanomaterials (CNTs, rGO) in PANi in general leads to improved specific capacitance, while the addition of CNTs and rGO together leads to synergistic improvement in the specific capacitance, owing to a combination of factors.

Leptin Improves Sperm Cryopreservation via Antioxidant Defense

PubMed Central

Fontoura, Paula; Mello, Mariana Duque; Gallo-Sá, Paulo; Erthal-Martins, Maria Cecília; Cardoso, Maria Cecília Almeida; Ramos, Cristiane

2017-01-01

Background: Leptin and its receptor are present in spermatozoa; however, the role of leptin in sperm function is still controversial. Our present study aimed at demonstrating the effect of cryopreservation on sperm DNA fragmentation (DNAf) and investigating the possible effects of sperm capacitation techniques and leptin in vitro incubation on frozen-thawed sperm DNAf and oxidative stress. Methods: Samples of 45 normospermic men attending for infertility investigation at Vida Centro de Fertilidade, Rio de Janeiro, Brazil, were frozen and thawed with or without capacitation and leptin incubation prior to freezing. Sperm DNA fragmentation was evaluated by Sperm Chromatin Dispersion Assay before and after cryopreservation and oxidative stress parameters were measured by spectrophotometry with and without leptin incubation. Statistical analysis was performed using paired t test to compare DNAf between groups before and after freeze-thaw cycle, to compare groups before and after capacitation and leptin incubation and oxidative measurements before and after leptin incubation. Statistical significance was considered when p≤0.05. Results: Our results revealed a significant post-thaw rise in sperm DNAf compared with fresh samples (p=0.0003). Sperm DNAf was significantly reduced when sperm capacitation was performed before freezing, when compared to those frozen with no previous capacitation (p=0.01). The addition of leptin to capacitated sperm before freezing reduced DNAf (p<0.0001) and enhanced superoxide dismutase (p=0.001) and glutathione peroxidase (p=0.02) antioxidant enzymes activity. Conclusion: The addition of leptin to capacitated sperm can improve sperm DNA quality following cryopreservation, possibly by inducing the activity of certain antioxidant enzymes. PMID:28377896

Effects of dc bias on the kinetics and electrical properties of silicon dioxide grown in an electron cyclotron resonance plasma

NASA Astrophysics Data System (ADS)

Carl, D. A.; Hess, D. W.; Lieberman, M. A.; Nguyen, T. D.; Gronsky, R.

1991-09-01

Thin (3-300-nm) oxides were grown on single-crystal silicon substrates at temperatures from 523 to 673 K in a low-pressure electron cyclotron resonance (ECR) oxygen plasma. Oxides were grown under floating, anodic or cathodic bias conditions, although only the oxides grown under floating or anodic bias conditions are acceptable for use as gate dielectrics in metal-oxide-semiconductor technology. Oxide thickness uniformity as measured by ellipsometry decreased with increasing oxidation time for all bias conditions. Oxidation kinetics under anodic conditions can be explained by negatively charged atomic oxygen, O-, transport limited growth. Constant current anodizations yielded three regions of growth: (1) a concentration gradient dominated regime for oxides thinner than 10 nm, (2) a field dominated regime with ohmic charged oxidant transport for oxide thickness in the range of 10 nm to approximately 100 nm, and (3) a space-charge limited regime for films thicker than approximately 100 nm. The relationship between oxide thickness (xox), overall potential drop (Vox) and ion current (ji) in the space-charge limited transport region was of the form: ji ∝ V2ox/x3ox. Transmission electron microscopy analysis of 5-60-nm-thick anodized films indicated that the silicon-silicon dioxide interface was indistinguishable from that of thermal oxides grown at 1123 K. High-frequency capacitance-voltage (C-V) and ramped bias current-voltage (I-V) studies performed on 5.4-30-nm gate thickness capacitors indicated that the as-grown ECR films had high levels of fixed oxide charge (≳1011 cm-2) and interface traps (≳1012 cm-2 eV-1). The fixed charge level could be reduced to ≊4×1010 cm-2 by a 20 min polysilicon gate activation anneal at 1123 K in nitrogen; the interface trap density at mid-band gap decreased to ≊(1-2)×1011 cm-2 eV-1 after this process. The mean breakdown strength for anodic oxides grown under optimum conditions was 10.87±0.83 MV cm-1. Electrical properties of the 5.4-8-nm gates compared well with thicker films and control dry thermal oxides of similar thicknesses.

Reduced Graphene Oxide/Carbon Nanotube Composites as Electrochemical Energy Storage Electrode Applications.

PubMed

Yang, Wenyao; Chen, Yan; Wang, Jingfeng; Peng, Tianjun; Xu, Jianhua; Yang, Bangchao; Tang, Ke

2018-06-15

We demonstrate an electrochemical reduction method to reduce graphene oxide (GO) to electrochemically reduced graphene oxide (ERGO) with the assistance of carbon nanotubes (CNTs). The faster and more efficient reduction of GO can be achieved after proper addition of CNTs into GO during the reduction process. This nanotube/nanosheet composite was deposited on electrode as active material for electrochemical energy storage applications. It has been found that the specific capacitance of the composite film was strongly affected by the mass ratio of GO/CNTs and the scanning ratio of cyclic voltammetry. The obtained ERGO/CNT composite electrode exhibited a 279.4 F/g-specific capacitance and showed good cycle rate performance with the evidence that the specific capacitance maintained above 90% after 6000 cycles. The synergistic effect between ERGO and CNTs as well as crossing over of CNTs into ERGO is attributed to the high electrochemical performance of composite electrode.

Low voltage driven RF MEMS capacitive switch using reinforcement for reduced buckling

NASA Astrophysics Data System (ADS)

Bansal, Deepak; Bajpai, Anuroop; Kumar, Prem; Kaur, Maninder; Kumar, Amit; Chandran, Achu; Rangra, Kamaljit

2017-02-01

Variation in actuation voltage for RF MEMS switches is observed as a result of stress-generated buckling of MEMS structures. Large voltage driven RF-MEMS switches are a major concern in space bound communication applications. In this paper, we propose a low voltage driven RF MEMS capacitive switch with the introduction of perforations and reinforcement. The performance of the fabricated switch is compared with conventional capacitive RF MEMS switches. The pull-in voltage of the switch is reduced from 70 V to 16.2 V and the magnitude of deformation is reduced from 8 µm to 1 µm. The design of the reinforcement frame enhances the structural stiffness by 46 % without affecting the high frequency response of the switch. The measured isolation and insertion loss of the reinforced switch is more than 20 dB and 0.4 dB over the X band range.

High input impedance amplifier

NASA Technical Reports Server (NTRS)

Kleinberg, Leonard L.

1995-01-01

High input impedance amplifiers are provided which reduce the input impedance solely to a capacitive reactance, or, in a somewhat more complex design, provide an extremely high essentially infinite, capacitive reactance. In one embodiment, where the input impedance is reduced in essence, to solely a capacitive reactance, an operational amplifier in a follower configuration is driven at its non-inverting input and a resistor with a predetermined magnitude is connected between the inverting and non-inverting inputs. A second embodiment eliminates the capacitance from the input by adding a second stage to the first embodiment. The second stage is a second operational amplifier in a non-inverting gain-stage configuration where the output of the first follower stage drives the non-inverting input of the second stage and the output of the second stage is fed back to the non-inverting input of the first stage through a capacitor of a predetermined magnitude. These amplifiers, while generally useful, are very useful as sensor buffer amplifiers that may eliminate significant sources of error.

Issues of nanoelectronics: a possible roadmap.

PubMed

Wang, Kang L

2002-01-01

In this review, we will discuss a possible roadmap in scaling a nanoelectronic device from today's CMOS technology to the ultimate limit when the device fails. In other words, at the limit, CMOS will have a severe short channel effect, significant power dissipation in its quiescent (standby) state, and problems related to other essential characteristics. Efforts to use structures such as the double gate, vertical surround gate, and SOI to improve the gate control have continually been made. Other types of structures using SiGe source/drain, asymmetric Schottky source/drain, and the like will be investigated as viable structures to achieve ultimate CMOS. In reaching its scaling limit, tunneling will be an issue for CMOS. The tunneling current through the gate oxide and between the source and drain will limit the device operation. When tunneling becomes significant, circuits may incorporate tunneling devices with CMOS to further increase the functionality per device count. We will discuss both the top-down and bottom-up approaches in attaining the nanometer scale and eventually the atomic scale. Self-assembly is used as a bottom-up approach. The state of the art is reviewed, and the challenges of the multiple-step processing in using the self-assembly approach are outlined. Another facet of the scaling trend is to decrease the number of electrons in devices, ultimately leading to single electrons. If the size of a single-electron device is scaled in such a way that the Coulomb self-energy is higher than the thermal energy (at room temperature), a single-electron device will be able to operate at room temperature. In principle, the speed of the device will be fast as long as the capacitance of the load is also scaled accordingly. The single-electron device will have a small drive current, and thus the load capacitance, including those of interconnects and fanouts, must be small to achieve a reasonable speed. However, because the increase in the density (and/or functionality) of integrated circuits is the principal driver, the wiring or interconnects will increase and become the bottleneck for the design of future high-density and high-functionality circuits, particularly for single-electron devices. Furthermore, the massive interconnects needed in the architecture used today will result in an increase in load capacitance. Thus for single-electron device circuits, it is critical to have minimal interconnect loads. And new types of architectures with minimal numbers of global interconnects will be needed. Cellular automata, which need only nearest-neighbor interconnects, are discussed as a plausible example. Other architectures such as neural networks are also possible. Examples of signal processing using cellular automata are discussed. Quantum computing and information processing are based on quantum mechanical descriptions of individual particles correlated among each other. A quantum bit or qubit is described as a linear superposition of the wave functions of a two-state system, for example, the spin of a particle. With the interaction of two qubits, they are connected in a "wireless fashion" using wave functions via quantum mechanical interaction, referred to as entanglement. The interconnection by the nonlocality of wave functions affords a massive parallel nature for computing or so-called quantum parallelism. We will describe the potential and solid-state implementations of quantum computing and information, using electron spin and/or nuclear spin in Si and Ge. Group IV elements have a long coherent time and other advantages. The example of using SiGe for g factor engineering will be described.

Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

NASA Astrophysics Data System (ADS)

Maity, H.; Biswas, A.; Bhattacharjee, A. K.; Pal, A.

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

A genetic variant of the sperm-specific SLO3 K+ channel has altered pH and Ca2+ sensitivities.

PubMed

Geng, Yanyan; Ferreira, Juan J; Dzikunu, Victor; Butler, Alice; Lybaert, Pascale; Yuan, Peng; Magleby, Karl L; Salkoff, Lawrence; Santi, Celia M

2017-05-26

To fertilize an oocyte, sperm must first undergo capacitation in which the sperm plasma membrane becomes hyperpolarized via activation of potassium (K + ) channels and resultant K + efflux. Sperm-specific SLO3 K + channels are responsible for these membrane potential changes critical for fertilization in mouse sperm, and they are only sensitive to pH i However, in human sperm, the major K + conductance is both Ca 2+ - and pH i -sensitive. It has been debated whether Ca 2+ -sensitive SLO1 channels substitute for human SLO3 (hSLO3) in human sperm or whether human SLO3 channels have acquired Ca 2+ sensitivity. Here we show that hSLO3 is rapidly evolving and reveal a natural structural variant with enhanced apparent Ca 2+ and pH sensitivities. This variant allele (C382R) alters an amino acid side chain at a principal interface between the intramembrane-gated pore and the cytoplasmic gating ring of the channel. Because the gating ring contains sensors to intracellular factors such as pH and Ca 2+ , the effectiveness of transduction between the gating ring and the pore domain appears to be enhanced. Our results suggest that sperm-specific genes can evolve rapidly and that natural genetic variation may have led to a SLO3 variant that differs from wild type in both pH and intracellular Ca 2+ sensitivities. Whether this physiological variation confers differences in fertility among males remains to be established. © 2017 by The American Society for Biochemistry and Molecular Biology, Inc.

Hydrophobic interaction and charge accumulation at the diamond-electrolyte interface.

PubMed

Dankerl, M; Lippert, A; Birner, S; Stützel, E U; Stutzmann, M; Garrido, J A

2011-05-13

The hydrophobic interaction of surfaces with water is a well-known phenomenon, but experimental evidence of its influence on biosensor devices has been lacking. In this work we investigate diamond field-effect devices, reporting on Hall effect experiments and complementary simulations of the interfacial potential at the hydrogen-terminated diamond/aqueous electrolyte interface. The interfacial capacitance, derived from the gate-dependent Hall carrier concentration, can be modeled only when considering the hydrophobic nature of this surface and its influence on the structure of interfacial water. Our work demonstrates how profoundly the performance of potentiometric biosensor devices can be affected by their surfaces' hydrophobicity.

Low noise tuned amplifier

NASA Technical Reports Server (NTRS)

Kleinberg, L. L. (Inventor)

1984-01-01

A bandpass amplifier employing a field effect transistor amplifier first stage is described with a resistive load either a.c. or directly coupled to the non-inverting input of an operational amplifier second stage which is loaded in a Wien Bridge configuration. The bandpass amplifier may be operated with a signal injected into the gate terminal of the field effect transistor and the signal output taken from the output terminal of the operational amplifier. The operational amplifier stage appears as an inductive reactance, capacitive reactance and negative resistance at the non-inverting input of the operational amplifier, all of which appear in parallel with the resistive load of the field effect transistor.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

PubMed Central

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-01-01

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit. PMID:27231915

Temperature dependence of frequency response characteristics in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Lu, Xubing; Minari, Takeo; Liu, Chuan; Kumatani, Akichika; Liu, J.-M.; Tsukagoshi, Kazuhito

2012-04-01

The frequency response characteristics of semiconductor devices play an essential role in the high-speed operation of electronic devices. We investigated the temperature dependence of dynamic characteristics in pentacene-based organic field-effect transistors and metal-insulator-semiconductor capacitors. As the temperature decreased, the capacitance-voltage characteristics showed large frequency dispersion and a negative shift in the flat-band voltage at high frequencies. The cutoff frequency shows Arrhenius-type temperature dependence with different activation energy values for various gate voltages. These phenomena demonstrate the effects of charge trapping on the frequency response characteristics, since decreased mobility prevents a fast charge response for alternating current signals at low temperatures.

AlGaN/GaN-on-Si monolithic power-switching device with integrated gate current booster

NASA Astrophysics Data System (ADS)

Han, Sang-Woo; Jo, Min-Gi; Kim, Hyungtak; Cho, Chun-Hyung; Cha, Ho-Young

2017-08-01

This study investigates the effects of a monolithic gate current booster integrated with an AlGaN/GaN-on-Si power-switching device. The integrated gate current booster was implemented by a single-stage inverter topology consisting of a recessed normally-off AlGaN/GaN MOS-HFET and a mesa resistor. The monolithically integrated gate current booster in a switching FET eliminated the parasitic elements caused by external interconnection and enabled fast switching operation. The gate charging and discharging currents were boosted by the integrated inverter, which significantly reduced both rise and fall times: the rise time was reduced from 626 to 41.26 ns, while the fall time was reduced from 554 to 42.19 ns by the single-stage inverter. When the packaged monolithic power chip was tested under 1 MHz hard-switching operation with VDD = 200 V, the switching loss was found to have been drastically reduced, from 5.27 to 0.55 W.

Modulation of intracellular Ca(2+) via alpha(1B)-adrenoreceptor signaling molecules, G alpha(h) (transglutaminase II) and phospholipase C-delta 1.

PubMed

Kang, Sung Koo; Kim, Dae Kyong; Damron, Derek S; Baek, Kwang Jin; Im, Mie-Jae

2002-04-26

We characterized the alpha(1B)-adrenoreceptor (alpha(1B)-AR)-mediated intracellular Ca(2+) signaling involving G alpha(h) (transglutaminase II, TGII) and phospholipase C (PLC)-delta 1 using DDT1-MF2 cell. Expression of wild-type TGII and a TGII mutant lacking transglutaminase activity resulted in significant increases in a rapid peak and a sustained level of intracellular Ca(2+) concentration ([Ca(2+)](i)) in response to activation of the alpha(1B)-AR. Expression of a TGII mutant lacking the interaction with the receptor or PLC-delta 1 substantially reduced both the peak and sustained levels of [Ca(2+)](i). Expression of TGII mutants lacking the interaction with PLC-delta 1 resulted in a reduced capacitative Ca(2+) entry. Reduced expression of PLC-delta 1 displayed a transient elevation of [Ca(2+)](i) and a reduction in capacitative Ca(2+) entry. Expression of the C2-domain of PLC-delta 1, which contains the TGII interaction site, resulted in reduction of the alpha(1B)-AR-evoked peak increase in [Ca(2+)](i), while the sustained elevation in [Ca(2+)](i) and capacitative Ca(2+) entry remained unchanged. These findings demonstrate that stimulation of PLC-delta 1 via coupling of the alpha(1B)-AR with TGII evokes both Ca(2+) release and capacitative Ca(2+) entry and that capacitative Ca(2+) entry is mediated by the interaction of TGII with PLC-delta 1.

Neuron Morphology Influences Axon Initial Segment Plasticity.

PubMed

Gulledge, Allan T; Bravo, Jaime J

2016-01-01

In most vertebrate neurons, action potentials are initiated in the axon initial segment (AIS), a specialized region of the axon containing a high density of voltage-gated sodium and potassium channels. It has recently been proposed that neurons use plasticity of AIS length and/or location to regulate their intrinsic excitability. Here we quantify the impact of neuron morphology on AIS plasticity using computational models of simplified and realistic somatodendritic morphologies. In small neurons (e.g., dentate granule neurons), excitability was highest when the AIS was of intermediate length and located adjacent to the soma. Conversely, neurons having larger dendritic trees (e.g., pyramidal neurons) were most excitable when the AIS was longer and/or located away from the soma. For any given somatodendritic morphology, increasing dendritic membrane capacitance and/or conductance favored a longer and more distally located AIS. Overall, changes to AIS length, with corresponding changes in total sodium conductance, were far more effective in regulating neuron excitability than were changes in AIS location, while dendritic capacitance had a larger impact on AIS performance than did dendritic conductance. The somatodendritic influence on AIS performance reflects modest soma-to-AIS voltage attenuation combined with neuron size-dependent changes in AIS input resistance, effective membrane time constant, and isolation from somatodendritic capacitance. We conclude that the impact of AIS plasticity on neuron excitability will depend largely on somatodendritic morphology, and that, in some neurons, a shorter or more distally located AIS may promote, rather than limit, action potential generation.

Predictive of the quantum capacitance effect on the excitation of plasma waves in graphene transistors with scaling limit.

PubMed

Wang, Lin; Chen, Xiaoshuang; Hu, Yibin; Wang, Shao-Wei; Lu, Wei

2015-04-28

Plasma waves in graphene field-effect transistors (FETs) and nano-patterned graphene sheets have emerged as very promising candidates for potential terahertz and infrared applications in myriad areas including remote sensing, biomedical science, military, and many other fields with their electrical tunability and strong interaction with light. In this work, we study the excitations and propagation properties of plasma waves in nanometric graphene FETs down to the scaling limit. Due to the quantum-capacitance effect, the plasma wave exhibits strong correlation with the distribution of density of states (DOS). It is indicated that the electrically tunable plasma resonance has a power-dependent V0.8 TG relation on the gate voltage, which originates from the linear dependence of density of states (DOS) on the energy in pristine graphene, in striking difference to those dominated by classical capacitance with only V0.5 TG dependence. The results of different transistor sizes indicate the potential application of nanometric graphene FETs in highly-efficient electro-optic modulation or detection of terahertz or infrared radiation. In addition, we highlight the perspectives of plasma resonance excitation in probing the many-body interaction and quantum matter state in strong correlation electron systems. This study reveals the key feature of plasma waves in decorated/nanometric graphene FETs, and paves the way to tailor plasma band-engineering and expand its application in both terahertz and mid-infrared regions.

Contact resistance and overlapping capacitance in flexible sub-micron long oxide thin-film transistors for above 100 MHz operation

NASA Astrophysics Data System (ADS)

Münzenrieder, Niko; Salvatore, Giovanni A.; Petti, Luisa; Zysset, Christoph; Büthe, Lars; Vogt, Christian; Cantarella, Giuseppe; Tröster, Gerhard

2014-12-01

In recent years new forms of electronic devices such as electronic papers, flexible displays, epidermal sensors, and smart textiles have become reality. Thin-film transistors (TFTs) are the basic blocks of the circuits used in such devices and need to operate above 100 MHz to efficiently treat signals in RF systems and address pixels in high resolution displays. Beyond the choice of the semiconductor, i.e., silicon, graphene, organics, or amorphous oxides, the junctionless nature of TFTs and its geometry imply some limitations which become evident and important in devices with scaled channel length. Furthermore, the mechanical instability of flexible substrates limits the feature size of flexible TFTs. Contact resistance and overlapping capacitance are two parasitic effects which limit the transit frequency of transistors. They are often considered independent, while a deeper analysis of TFTs geometry imposes to handle them together; in fact, they both depend on the overlapping length (LOV) between source/drain and the gate contacts. Here, we conduct a quantitative analysis based on a large number of flexible ultra-scaled IGZO TFTs. Devices with three different values of overlap length and channel length down to 0.5 μm are fabricated to experimentally investigate the scaling behavior of the transit frequency. Contact resistance and overlapping capacitance depend in opposite ways on LOV. These findings establish routes for the optimization of the dimension of source/drain contact pads and suggest design guidelines to achieve megahertz operation in flexible IGZO TFTs and circuits.

Neuron Morphology Influences Axon Initial Segment Plasticity123

PubMed Central

2016-01-01

In most vertebrate neurons, action potentials are initiated in the axon initial segment (AIS), a specialized region of the axon containing a high density of voltage-gated sodium and potassium channels. It has recently been proposed that neurons use plasticity of AIS length and/or location to regulate their intrinsic excitability. Here we quantify the impact of neuron morphology on AIS plasticity using computational models of simplified and realistic somatodendritic morphologies. In small neurons (e.g., dentate granule neurons), excitability was highest when the AIS was of intermediate length and located adjacent to the soma. Conversely, neurons having larger dendritic trees (e.g., pyramidal neurons) were most excitable when the AIS was longer and/or located away from the soma. For any given somatodendritic morphology, increasing dendritic membrane capacitance and/or conductance favored a longer and more distally located AIS. Overall, changes to AIS length, with corresponding changes in total sodium conductance, were far more effective in regulating neuron excitability than were changes in AIS location, while dendritic capacitance had a larger impact on AIS performance than did dendritic conductance. The somatodendritic influence on AIS performance reflects modest soma-to-AIS voltage attenuation combined with neuron size-dependent changes in AIS input resistance, effective membrane time constant, and isolation from somatodendritic capacitance. We conclude that the impact of AIS plasticity on neuron excitability will depend largely on somatodendritic morphology, and that, in some neurons, a shorter or more distally located AIS may promote, rather than limit, action potential generation. PMID:27022619

Calibration of micro-capacitance measurement system for thermal barrier coating testing

NASA Astrophysics Data System (ADS)

Ren, Yuan; Chen, Dixiang; Wan, Chengbiao; Tian, Wugang; Pan, Mengchun

2018-06-01

In order to comprehensively evaluate the thermal barrier coating system of an engine blade, an integrated planar sensor combining electromagnetic coils with planar capacitors is designed, in which the capacitance measurement accuracy of the planar capacitor is a key factor. The micro-capacitance measurement system is built based on an impedance analyzer. Because of the influence of non-ideal factors on the measuring system, there is an obvious difference between the measured value and the actual value. It is necessary to calibrate the measured results and eliminate the difference. In this paper, the measurement model of a planar capacitive sensor is established, and the relationship between the measured value and the actual value of capacitance is deduced. The model parameters are estimated with the least square method, and the calibration accuracy is evaluated with experiments under different dielectric conditions. The capacitance measurement error is reduced from 29% ˜ 46.5% to around 1% after calibration, which verifies the feasibility of the calibration method.

Effect of incorporation of nitrogen atoms in Al2O3 gate dielectric of wide-bandgap-semiconductor MOSFET on gate leakage current and negative fixed charge

NASA Astrophysics Data System (ADS)

Kojima, Eiji; Chokawa, Kenta; Shirakawa, Hiroki; Araidai, Masaaki; Hosoi, Takuji; Watanabe, Heiji; Shiraishi, Kenji

2018-06-01

We performed first-principle calculations to investigate the effect of incorporation of N atoms into Al2O3 gate dielectrics. Our calculations show that the defect levels generated by VO in Al2O3 are the origin of the stress-induced gate leakage current and that VOVAl complexes in Al2O3 cause negative fixed charge. We revealed that the incorporation of N atoms into Al2O3 eliminates the VO defect levels, reducing the stress-induced gate leakage current. Moreover, this suppresses the formation of negatively charged VOVAl complexes. Therefore, AlON can reduce both stress-induced gate leakage current and negative fixed charge in wide-bandgap-semiconductor MOSFETs.

Characteristics of Nitrogen Balances of Large-scale Stock Farms and Reduction of Environmental Nitrogen Loads

NASA Astrophysics Data System (ADS)

Hattori, Toshihiro; Takamatsu, Rieko

We calculated nitrogen balances on farm gate and soil surface on large-scale stock farms and discussed methods for reducing environmental nitrogen loads. Four different types of public stock farms (organic beef, calf supply and daily cows) were surveyed in Aomori Prefecture. (1) Farm gate and soil surface nitrogen inflows were both larger than the respective outflows on all types of farms. Farm gate nitrogen balance for beef farms were worse than that for dairy farms. (2) Soil surface nitrogen outflows and soil nitrogen retention were in proportion to soil surface nitrogen inflows. (3) Reductions in soil surface nitrogen retention were influenced by soil surface nitrogen inflows. (4) In order to reduce farm gate nitrogen retention, inflows of formula feed and chemical fertilizer need to be reduced. (5) In order to reduce soil surface nitrogen retention, inflows of fertilizer need to be reduced and nitrogen balance needs to be controlled.

Solar Array Hysteresis and its Interaction with the MPPT System

NASA Astrophysics Data System (ADS)

Fernandez, A.; Baur, C.; Gomez-Carpintero, F.

2014-08-01

It is well known that solar cells have a capacitance in parallel which value changes with the voltage. Depending on the section arrangement on the Solar Array, the power conversion unit connected to it will see a smaller or larger capacitance value and will have to cope with its adverse effects. In the case of converters with an MPPT, this capacitance gives place to an hysteresis effect that might shift the tracking point, reducing the power extracted from the Solar Array. This paper explores the different sides of this issue, from capacitance modelling to the effects on the MPPT. Additionally, this paper analyses a similar interaction between MPPTs and commercial SAS.

SUPPRESSION OF AFTERPULSING IN PHOTOMULTIPLIERS BY GATING THE PHOTOCATHODE

EPA Science Inventory

A number of gating schemes to minimize the long-term afterpulse signal in photomultipliers have been evaluated. Blocking the excitation pulse by gating the photocathode was found to reduce the gate-on afterpulse background by a factor of 230 over that for nongated operation. Thi...

Methodology for Analysis, Modeling and Simulation of Airport Gate-waiting Delays

NASA Astrophysics Data System (ADS)

Wang, Jianfeng

This dissertation presents methodologies to estimate gate-waiting delays from historical data, to identify gate-waiting-delay functional causes in major U.S. airports, and to evaluate the impact of gate operation disruptions and mitigation strategies on gate-waiting delay. Airport gates are a resource of congestion in the air transportation system. When an arriving flight cannot pull into its gate, the delay it experiences is called gate-waiting delay. Some possible reasons for gate-waiting delay are: the gate is occupied, gate staff or equipment is unavailable, the weather prevents the use of the gate (e.g. lightning), or the airline has a preferred gate assignment. Gate-waiting delays potentially stay with the aircraft throughout the day (unless they are absorbed), adding costs to passengers and the airlines. As the volume of flights increases, ensuring that airport gates do not become a choke point of the system is critical. The first part of the dissertation presents a methodology for estimating gate-waiting delays based on historical, publicly available sources. Analysis of gate-waiting delays at major U.S. airports in the summer of 2007 identifies the following. (i) Gate-waiting delay is not a significant problem on majority of days; however, the worst delay days (e.g. 4% of the days at LGA) are extreme outliers. (ii) The Atlanta International Airport (ATL), the John F. Kennedy International Airport (JFK), the Dallas/Fort Worth International Airport (DFW) and the Philadelphia International Airport (PHL) experience the highest gate-waiting delays among major U.S. airports. (iii) There is a significant gate-waiting-delay difference between airlines due to a disproportional gate allocation. (iv) Gate-waiting delay is sensitive to time of a day and schedule peaks. According to basic principles of queueing theory, gate-waiting delay can be attributed to over-scheduling, higher-than-scheduled arrival rate, longer-than-scheduled gate-occupancy time, and reduced gate availability. Analysis of the worst days at six major airports in the summer of 2007 indicates that major gate-waiting delays are primarily due to operational disruptions---specifically, extended gate occupancy time, reduced gate availability and higher-than-scheduled arrival rate (usually due to arrival delay). Major gate-waiting delays are not a result of over-scheduling. The second part of this dissertation presents a simulation model to evaluate the impact of gate operational disruptions and gate-waiting-delay mitigation strategies, including building new gates, implementing common gates, using overnight off-gate parking and adopting self-docking gates. Simulation results show the following effects of disruptions: (i) The impact of arrival delay in a time window (e.g. 7 pm to 9 pm) on gate-waiting delay is bounded. (ii) The impact of longer-than-scheduled gate-occupancy times in a time window on gate-waiting delay can be unbounded and gate-waiting delay can increase linearly as the disruption level increases. (iii) Small reductions in gate availability have a small impact on gate-waiting delay due to slack gate capacity, while larger reductions have a non-linear impact as slack gate capacity is used up. Simulation results show the following effects of mitigation strategies: (i) Implementing common gates is an effective mitigation strategy, especially for airports with a flight schedule not dominated by one carrier, such as LGA. (ii) The overnight off-gate rule is effective in mitigating gate-waiting delay for flights stranded overnight following departure cancellations. This is especially true at airports where the gate utilization is at maximum overnight, such as LGA and DFW. The overnight off-gate rule can also be very effective to mitigate gate-waiting delay due to operational disruptions in evenings. (iii) Self-docking gates are effective in mitigating gate-waiting delay due to reduced gate availability.

Quantifying the impact of respiratory-gated 4D CT acquisition on thoracic image quality: a digital phantom study.

PubMed

Bernatowicz, K; Keall, P; Mishra, P; Knopf, A; Lomax, A; Kipritidis, J

2015-01-01

Prospective respiratory-gated 4D CT has been shown to reduce tumor image artifacts by up to 50% compared to conventional 4D CT. However, to date no studies have quantified the impact of gated 4D CT on normal lung tissue imaging, which is important in performing dose calculations based on accurate estimates of lung volume and structure. To determine the impact of gated 4D CT on thoracic image quality, the authors developed a novel simulation framework incorporating a realistic deformable digital phantom driven by patient tumor motion patterns. Based on this framework, the authors test the hypothesis that respiratory-gated 4D CT can significantly reduce lung imaging artifacts. Our simulation framework synchronizes the 4D extended cardiac torso (XCAT) phantom with tumor motion data in a quasi real-time fashion, allowing simulation of three 4D CT acquisition modes featuring different levels of respiratory feedback: (i) "conventional" 4D CT that uses a constant imaging and couch-shift frequency, (ii) "beam paused" 4D CT that interrupts imaging to avoid oversampling at a given couch position and respiratory phase, and (iii) "respiratory-gated" 4D CT that triggers acquisition only when the respiratory motion fulfills phase-specific displacement gating windows based on prescan breathing data. Our framework generates a set of ground truth comparators, representing the average XCAT anatomy during beam-on for each of ten respiratory phase bins. Based on this framework, the authors simulated conventional, beam-paused, and respiratory-gated 4D CT images using tumor motion patterns from seven lung cancer patients across 13 treatment fractions, with a simulated 5.5 cm(3) spherical lesion. Normal lung tissue image quality was quantified by comparing simulated and ground truth images in terms of overall mean square error (MSE) intensity difference, threshold-based lung volume error, and fractional false positive/false negative rates. Averaged across all simulations and phase bins, respiratory-gating reduced overall thoracic MSE by 46% compared to conventional 4D CT (p ∼ 10(-19)). Gating leads to small but significant (p < 0.02) reductions in lung volume errors (1.8%-1.4%), false positives (4.0%-2.6%), and false negatives (2.7%-1.3%). These percentage reductions correspond to gating reducing image artifacts by 24-90 cm(3) of lung tissue. Similar to earlier studies, gating reduced patient image dose by up to 22%, but with scan time increased by up to 135%. Beam paused 4D CT did not significantly impact normal lung tissue image quality, but did yield similar dose reductions as for respiratory-gating, without the added cost in scanning time. For a typical 6 L lung, respiratory-gated 4D CT can reduce image artifacts affecting up to 90 cm(3) of normal lung tissue compared to conventional acquisition. This image improvement could have important implications for dose calculations based on 4D CT. Where image quality is less critical, beam paused 4D CT is a simple strategy to reduce imaging dose without sacrificing acquisition time.

Redundancy Analysis of Capacitance Data of a Coplanar Electrode Array for Fast and Stable Imaging Processing

PubMed Central

Wen, Yintang; Zhang, Zhenda; Zhang, Yuyan; Sun, Dongtao

2017-01-01

A coplanar electrode array sensor is established for the imaging of composite-material adhesive-layer defect detection. The sensor is based on the capacitive edge effect, which leads to capacitance data being considerably weak and susceptible to environmental noise. The inverse problem of coplanar array electrical capacitance tomography (C-ECT) is ill-conditioning, in which a small error of capacitance data can seriously affect the quality of reconstructed images. In order to achieve a stable image reconstruction process, a redundancy analysis method for capacitance data is proposed. The proposed method is based on contribution rate and anti-interference capability. According to the redundancy analysis, the capacitance data are divided into valid and invalid data. When the image is reconstructed by valid data, the sensitivity matrix needs to be changed accordingly. In order to evaluate the effectiveness of the sensitivity map, singular value decomposition (SVD) is used. Finally, the two-dimensional (2D) and three-dimensional (3D) images are reconstructed by the Tikhonov regularization method. Through comparison of the reconstructed images of raw capacitance data, the stability of the image reconstruction process can be improved, and the quality of reconstructed images is not degraded. As a result, much invalid data are not collected, and the data acquisition time can also be reduced. PMID:29295537

Gated CT imaging using a free-breathing respiration signal from flow-volume spirometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

D'Souza, Warren D.; Kwok, Young; Deyoung, Chad

2005-12-15

Respiration-induced tumor motion is known to cause artifacts on free-breathing spiral CT images used in treatment planning. This leads to inaccurate delineation of target volumes on planning CT images. Flow-volume spirometry has been used previously for breath-holds during CT scans and radiation treatments using the active breathing control (ABC) system. We have developed a prototype by extending the flow-volume spirometer device to obtain gated CT scans using a PQ 5000 single-slice CT scanner. To test our prototype, we designed motion phantoms to compare image quality obtained with and without gated CT scan acquisition. Spiral and axial (nongated and gated) CTmore » scans were obtained of phantoms with motion periods of 3-5 s and amplitudes of 0.5-2 cm. Errors observed in the volume estimate of these structures were as much as 30% with moving phantoms during CT simulation. Application of motion-gated CT with active breathing control reduced these errors to within 5%. Motion-gated CT was then implemented in patients and the results are presented for two clinical cases: lung and abdomen. In each case, gated scans were acquired at end-inhalation, end-exhalation in addition to a conventional free-breathing (nongated) scan. The gated CT scans revealed reduced artifacts compared with the conventional free-breathing scan. Differences of up to 20% in the volume of the structures were observed between gated and free-breathing scans. A comparison of the overlap of structures between the gated and free-breathing scans revealed misalignment of the structures. These results demonstrate the ability of flow-volume spirometry to reduce errors in target volumes via gating during CT imaging.« less

A Capacitance-To-Digital Converter for MEMS Sensors for Smart Applications.

PubMed

Pérez Sanjurjo, Javier; Prefasi, Enrique; Buffa, Cesare; Gaggl, Richard

2017-06-07

The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm², which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply.

Fabrication and optimization of a whiskerless Schottky barrier diode for submillimeter wave applications

NASA Technical Reports Server (NTRS)

Bishop, W.; Mattauch, R. J.

1990-01-01

The following accomplishments were made towards the goal of an optimized whiskerless diode chip for submillimeter wavelength applications. (1) Surface channel whiskerless diode structure was developed which offers excellent DC and RF characteristics, reduced shunt capacitance and simplified fabrication compared to mesa and proton isolated structures. (2) Reliable fabrication technology was developed for the surface channel structure. The new anode plating technology is a major improvement. (3) DC and RF characterization of the surface channel diode was compared with whisker contacted diodes. This data indicates electrical performance as good as the best reported for similar whisker contacted devices. (4) Additional batches of surface channel diodes were fabricated with excellent I-V and reduced shunt capacitance. (5) Large scale capacitance modelinng was done for the planar diode structure. This work revealed the importance of removing the substrate gallium arsenide for absolute minimum pad capacitance. (6) A surface channel diode was developed on quartz substrate and this substrate was completely removed after diode mounting for minimum parasitic capacitance. This work continues with the goal of producing excellent quality submillimeter wavelength planar diodes which satisfy the requirements of easy handling and robustness. These devices will allow the routine implementation of Schottky receivers into space-based applications at frequencies as high as 1 THz, and, in the future, beyond.

A Capacitance-To-Digital Converter for MEMS Sensors for Smart Applications

PubMed Central

Pérez Sanjurjo, Javier; Prefasi, Enrique; Buffa, Cesare; Gaggl, Richard

2017-01-01

The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm2, which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply. PMID:28590425

Solution-Processed Transistors Using Colloidal Nanocrystals with Composition-Matched Molecular "Solders": Approaching Single Crystal Mobility.

PubMed

Jang, Jaeyoung; Dolzhnikov, Dmitriy S; Liu, Wenyong; Nam, Sooji; Shim, Moonsub; Talapin, Dmitri V

2015-10-14

Crystalline silicon-based complementary metal-oxide-semiconductor transistors have become a dominant platform for today's electronics. For such devices, expensive and complicated vacuum processes are used in the preparation of active layers. This increases cost and restricts the scope of applications. Here, we demonstrate high-performance solution-processed CdSe nanocrystal (NC) field-effect transistors (FETs) that exhibit very high carrier mobilities (over 400 cm(2)/(V s)). This is comparable to the carrier mobilities of crystalline silicon-based transistors. Furthermore, our NC FETs exhibit high operational stability and MHz switching speeds. These NC FETs are prepared by spin coating colloidal solutions of CdSe NCs capped with molecular solders [Cd2Se3](2-) onto various oxide gate dielectrics followed by thermal annealing. We show that the nature of gate dielectrics plays an important role in soldered CdSe NC FETs. The capacitance of dielectrics and the NC electronic structure near gate dielectric affect the distribution of localized traps and trap filling, determining carrier mobility and operational stability of the NC FETs. We expand the application of the NC soldering process to core-shell NCs consisting of a III-V InAs core and a CdSe shell with composition-matched [Cd2Se3](2-) molecular solders. Soldering CdSe shells forms nanoheterostructured material that combines high electron mobility and near-IR photoresponse.

Directional flow induced by synchronized longitudinal and zeta-potential controlling AC-electrical fields.

PubMed

van der Wouden, E J; Hermes, D C; Gardeniers, J G E; van den Berg, A

2006-10-01

Electroosmotic flow (EOF) in a microchannel can be controlled by electronic control of the surface charge using an electrode embedded in the wall of the channel. By setting a voltage to the electrode, the zeta-potential at the wall can be changed locally. Thus, the electrode acts as a "gate" for liquid flow, in analogy with a gate in a field-effect transistor. In this paper we will show three aspects of a Field Effect Flow Control (FEFC) structure. We demonstrate the induction of directional flow by the synchronized switching of the gate potential with the channel axial potential. The advantage of this procedure is that potential gas formation by electrolysis at the electrodes that provide the axial electric field is suppressed at sufficiently large switching frequencies, while the direction and magnitude of the EOF can be maintained. Furthermore we will give an analysis of the time constants involved in the charging of the insulator, and thus the switching of the zeta potential, in order to predict the maximum operating frequency. For this purpose an equivalent electrical circuit is presented and analyzed. It is shown that in order to accurately describe the charging dynamics and pH dependency the traditionally used three capacitor model should be expanded with an element describing the buffer capacitance of the silica wall surface.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Chun-Lan; Yuan, Hongtao; Li, Yanbin

Electric-double-layer (EDL) gating with liquid electrolyte has been a powerful tool widely used to explore emerging interfacial electronic phenomena. Due to the large EDL capacitance, a high carrier density up to 10 14 cm –2 can be induced, directly leading to the realization of field-induced insulator to metal (or superconductor) transition. However, the liquid nature of the electrolyte has created technical issues including possible side electrochemical reactions or intercalation, and the potential for huge strain at the interface during cooling. In addition, the liquid coverage of active devices also makes many surface characterizations and in situ measurements challenging. Here, wemore » demonstrate an all solid-state EDL device based on a solid superionic conductor LaF 3, which can be used as both a substrate and a fluorine ionic gate dielectric to achieve a wide tunability of carrier density without the issues of strain or electrochemical reactions and can expose the active device surface for external access. Based on LaF 3 EDL transistors (EDLTs), we observe the metal–insulator transition in MoS 2. Interestingly, the well-defined crystal lattice provides a more uniform potential distribution in the substrate, resulting in less interface electron scattering and therefore a higher mobility in MoS 2 transistors. Finally, this result shows the powerful gating capability of LaF 3 solid electrolyte for new possibilities of novel interfacial electronic phenomena.« less

Control of magnetism by electrical charge doping or redox reactions in a surface-oxidized Co thin film with a solid-state capacitor structure

NASA Astrophysics Data System (ADS)

Hirai, T.; Koyama, T.; Chiba, D.

2018-03-01

We have investigated the electric field (EF) effect on magnetism in a Co thin film with a naturally oxidized surface. The EF was applied to the oxidized Co surface through a gate insulator layer made of HfO2, which was formed using atomic layer deposition (ALD). The efficiency of the EF effect on the magnetic anisotropy in the sample with the HfO2 layer deposited at the appropriate temperature for the ALD process was relatively large compared to the previously reported values with an unoxidized Co film. The coercivity promptly and reversibly followed the variation in gate voltage. The modulation of the channel resistance was at most ˜0.02%. In contrast, a dramatic change in the magnetic properties including the large change in the saturation magnetic moment and a much larger EF-induced modulation of the channel resistance (˜10%) were observed in the sample with a HfO2 layer deposited at a temperature far below the appropriate temperature range. The response of these properties to the gate voltage was very slow, suggesting that a redox reaction dominated the EF effect on the magnetism in this sample. The frequency response for the capacitive properties was examined to discuss the difference in the mechanism of the EF effect observed here.

Device Physics of Contact Issues for the Overestimation and Underestimation of Carrier Mobility in Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Liu, Chuan; Li, Gongtan; Di Pietro, Riccardo; Huang, Jie; Noh, Yong-Young; Liu, Xuying; Minari, Takeo

2017-09-01

Very high values of carrier mobility have been recently reported in newly developed materials for field-effect transistors (FETs) or thin-film transistors (TFTs). However, there is an increasing concern of whether the values are overestimated. In this paper, we investigate how much contact resistance a FET or TFT can tolerate to allow the conventional current-voltage equations, which is derived for no contact resistance. We contend that mobility in transistors with resistive contact can be underestimated with the presence of the injection barrier, whereas mobility in transistors with gated Schottky contact can be overestimated by more than 10 times. The latter phenomenon occurs even in long-channel devices, and it becomes more severe when using low-k dielectrics. This is because the band bending and injection barrier experience a complicated evolution on account of electrostatic doping in the semiconducting layer; thus, they do not follow a capacitance approximation. When the band bending is weak, the accumulation is as weak as that in the subthreshold regime. Accordingly, the carrier concentration nonlinearly increases with the gate field. This mechanism can occur with or without exhibiting the "kink" feature in the transfer curves, which has been suggested as the signature of overestimation. For precision, carrier mobility should be presented against gate voltage and should be examined by other recommended extraction methods.

Scalable ferroelectric MOS capacitors comprised of single crystalline SrZrxTi1-xO3 on Ge.

NASA Astrophysics Data System (ADS)

Moghadam, Reza; Xiao, Z.-Y.; Ahmadi-Majlan, K.; Grimley, E.; Ong, P. V.; Lebeau, J. M.; Chambers, S. A.; Hong, X.; Sushko, P.; Ngai, J. H.

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to field-effect devices that require very little power to operate, or that possess both logic and memory functionalities. The development of metal-oxide-semiconductor (MOS) capacitors in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel is essential in order to realize such field-effect devices. Here we demonstrate that scalable, ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x = 0.7) that has been epitaxially grown on Ge. Single crystalline SrZrxTi1-xO3 exhibits characteristics that are ideal for a ferroelectric gate material, namely, a type-I band offset with respect to Ge, large coercive fields and polarization that can be enhanced with electric field. The latter characteristic stems from the relaxor nature of SrZrxTi1-xO3. These properties enable MOS capacitors with 5 nm thick SrZrxTi1-xO3 layers to exhibit a nearly 2 V wide hysteretic window in the capacitance-voltage characteristics. The realization of ferroelectric MOS capacitors with technologically relevant gate thicknesses opens the pathway to practical field effect devices. NSF DMR 1508530.

Electrical Characterization of Semiconductor and Dielectric Materials with a Non-Damaging FastGateTM Probe

NASA Astrophysics Data System (ADS)

Robert, Hillard; William, Howland; Bryan, Snyder

2002-03-01

Determination of the electrical properties of semiconductor materials and dielectrics is highly desirable since these correlate best to final device performance. The properties of SiO2 and high k dielectrics such as Equivalent Oxide Thickness(EOT), Interface Trap Density(Dit), Oxide Effective Charge(Neff), Flatband Voltage Hysteresis(Delta Vfb), Threshold Voltage(VT) and, bulk properties such as carrier density profile and channel dose are all important parameters that require monitoring during front end processing. Conventional methods for determining these parameters involve the manufacturing of polysilicon or metal gate MOS capacitors and subsequent measurements of capacitance-voltage(CV) and/or current-voltage(IV). These conventional techniques are time consuming and can introduce changes to the materials being monitored. Also, equivalent circuit effects resulting from excessive leakage current, series resistance and stray inductance can introduce large errors in the measured results. In this paper, a new method is discussed that provides rapid determination of these critical parameters and is robust against equivalent circuit errors. This technique uses a small diameter(30 micron), elastically deformed probe to form a gate for MOSCAP CV and IV and can be used to measure either monitor wafers or test areas within scribe lines on product wafers. It allows for measurements of dielectrics thinner than 10 Angstroms. A detailed description and applications such as high k dielectrics, will be presented.

Limitations of threshold voltage engineering of AlGaN/GaN heterostructures by dielectric interface charge density and manipulation by oxygen plasma surface treatments

NASA Astrophysics Data System (ADS)

Lükens, G.; Yacoub, H.; Kalisch, H.; Vescan, A.

2016-05-01

The interface charge density between the gate dielectric and an AlGaN/GaN heterostructure has a significant impact on the absolute value and stability of the threshold voltage Vth of metal-insulator-semiconductor (MIS) heterostructure field effect transistor. It is shown that a dry-etching step (as typically necessary for normally off devices engineered by gate-recessing) before the Al2O3 gate dielectric deposition introduces a high positive interface charge density. Its origin is most likely donor-type trap states shifting Vth to large negative values, which is detrimental for normally off devices. We investigate the influence of oxygen plasma annealing techniques of the dry-etched AlGaN/GaN surface by capacitance-voltage measurements and demonstrate that the positive interface charge density can be effectively compensated. Furthermore, only a low Vth hysteresis is observable making this approach suitable for threshold voltage engineering. Analysis of the electrostatics in the investigated MIS structures reveals that the maximum Vth shift to positive voltages achievable is fundamentally limited by the onset of accumulation of holes at the dielectric/barrier interface. In the case of the Al2O3/Al0.26Ga0.74N/GaN material system, this maximum threshold voltage shift is limited to 2.3 V.

Modulation of KvAP Unitary Conductance and Gating by 1-Alkanols and Other Surface Active Agents

PubMed Central

Finol-Urdaneta, Rocio K.; McArthur, Jeffrey R.; Juranka, Peter F.; French, Robert J.; Morris, Catherine E.

2010-01-01

Abstract The actions of alcohols and anesthetics on ion channels are poorly understood. Controversy continues about whether bilayer restructuring is relevant to the modulatory effects of these surface active agents (SAAs). Some voltage-gated K channels (Kv), but not KvAP, have putative low affinity alcohol-binding sites, and because KvAP structures have been determined in bilayers, KvAP could offer insights into the contribution of bilayer mechanics to SAA actions. We monitored KvAP unitary conductance and macroscopic activation and inactivation kinetics in PE:PG/decane bilayers with and without exposure to classic SAAs (short-chain 1-alkanols, cholesterol, and selected anesthetics: halothane, isoflurane, chloroform). At levels that did not measurably alter membrane specific capacitance, alkanols caused functional changes in KvAP behavior including lowered unitary conductance, modified kinetics, and shifted voltage dependence for activation. A simple explanation is that the site of SAA action on KvAP is its entire lateral interface with the PE:PG/decane bilayer, with SAA-induced changes in surface tension and bilayer packing order combining to modulate the shape and stability of various conformations. The KvAP structural adjustment to diverse bilayer pressure profiles has implications for understanding desirable and undesirable actions of SAA-like drugs and, broadly, predicts that channel gating, conductance and pharmacology may differ when membrane packing order differs, as in raft versus nonraft domains. PMID:20197029

Field effect transistor and method of construction thereof

NASA Technical Reports Server (NTRS)

Fletner, W. R. (Inventor)

1978-01-01

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Tunable inter-qubit coupling as a resource for gate based quantum computing with superconducting circuits

NASA Astrophysics Data System (ADS)

Chiaro, B.; Neill, C.; Chen, Z.; Dunsworth, A.; Foxen, B.; Quintana, C.; Wenner, J.; Martinis, J. M.; Google Quantum Hardware Team

Fast, high fidelity two qubit gates are an essential requirement of a quantum processor. In this talk, we discuss how the tunable coupling of the gmon architecture provides a pathway for an improved two qubit controlled-Z gate. The maximum inter-qubit coupling strength gmax = 60 MHz is sufficient for fast adiabatic two qubit gates to be performed as quickly as single qubit gates, reducing dephasing errors. Additionally, the ability to turn the coupling off allows all qubits to idle at low magnetic flux sensitivity, further reducing susceptibility to noise. However, the flexibility that this platform offers comes at the expense of increased control complexity. We describe our strategy for addressing the control challenges of the gmon architecture and show experimental progress toward fast, high fidelity controlled-Z gates with gmon qubits.

Ionic behavior of organic-inorganic metal halide perovskite based metal-oxide-semiconductor capacitors.

PubMed

Wang, Yucheng; Zhang, Yuming; Pang, Tiqiang; Xu, Jie; Hu, Ziyang; Zhu, Yuejin; Tang, Xiaoyan; Luan, Suzhen; Jia, Renxu

2017-05-24

Organic-inorganic metal halide perovskites are promising semiconductors for optoelectronic applications. Despite the achievements in device performance, the electrical properties of perovskites have stagnated. Ion migration is speculated to be the main contributing factor for the many unusual electrical phenomena in perovskite-based devices. Here, to understand the intrinsic electrical behavior of perovskites, we constructed metal-oxide-semiconductor (MOS) capacitors based on perovskite films and performed capacitance-voltage (C-V) and current-voltage (I-V) measurements of the capacitors. The results provide direct evidence for the mixed ionic-electronic transport behavior within perovskite films. In the dark, there is electrical hysteresis in both the C-V and I-V curves because the mobile negative ions take part in charge transport despite frequency modulation. However, under illumination, the large amount of photoexcited free carriers screens the influence of the mobile ions with a low concentration, which is responsible for the normal C-V properties. Validation of ion migration for the gate-control ability of MOS capacitors is also helpful for the investigation of perovskite MOS transistors and other gate-control photovoltaic devices.

Temperature-Dependent Characterization, Modeling, and Switching Speed-Limitation Analysis of Third-Generation 10-kV SiC MOSFET

DOE PAGES

Ji, Shiqi; Zheng, Sheng; Wang, Fei; ...

2017-07-06

The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. Here, a double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simplemore » behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.« less

Chemical shift and surface characteristics of Al-doped ZnO thin film on SiOC dielectrics.

PubMed

Oh, Teresa; Lee, Sang Yeol

2013-10-01

Aluminum doped zinc oxide (AZO) films were fabricated on SiOC/p-Si wafer and SiOC film was prepared on a p-type Si substrate with the SiC target at oxygen ambient with the gas flow rate of 5-30 sccm by a RF magnetron sputter. C-V curve of SiOC/Si wafer was measured to observe the relationship between the polarity of SiOC dielectrics and the change of capacitance depending on oxygen gas flow rate. The SiOC film could be controlled to be polar or nonpolar, and their surface energy was changed depending on the polarity. Smooth surface is essential to improve the TFT performance. AZO-TFTs used smooth SiOC film with low polarity as a gate insulator was observed to show low leakage current (IL) and low subthreshold voltage swing. It is proposed that SiOC film with high degree amorphous structure as a gate insulator between AZO and Si wafer could solve problems of the mismatched interfaces, which was originated from the electron scattering due to the grain boundary.

Temperature-Dependent Characterization, Modeling, and Switching Speed-Limitation Analysis of Third-Generation 10-kV SiC MOSFET

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ji, Shiqi; Zheng, Sheng; Wang, Fei

The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. Here, a double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simplemore » behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.« less

Hafnium germanosilicate thin films for gate and capacitor dielectric applications: thermal stability studies

NASA Astrophysics Data System (ADS)

Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

2003-03-01

The use of SiO_2-GeO2 mixtures in gate and capacitor dielectric applications is hampered by the inherent thermodynamic instability of germanium oxide. Studies to date have confirmed that germanium oxide is readily converted to elemental germanium [1,2]. In sharp contrast, germanium oxide is known to form stable compounds with transition metal oxides such as hafnium oxide (hafnium germanate, HfGeO_4) [3]. Thus, the incorporation of hafnium in SiO_2-GeO2 may be expected to enhance the thermal stability of germanium oxide via Hf-O-Ge bond formation. In addition, the introduction of a transition metal would simultaneously enhance the capacitance of the dielectric thereby permitting a thicker dielectric which reduces leakage current [4]. In this study, the thermal stability of PVD-grown hafnium germanosilicate (HfGeSiO) films was investigated. XPS, HR-TEM, C-V and I-V results of films after deposition and subsequent annealing treatments will be presented. The results indicate that the presence or formation of elemental germanium drastically affects the stability of the HfGeSiO films. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [2] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995) [3] P. M. Lambert, Inorganic Chemistry, 37, 1352 (1998) [4] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001)

SU-E-T-401: Feasibility Study of Using ABC to Gate Lung SBRT Treatment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, D; Xie, X; Shepard, D

2014-06-01

Purpose: The current SBRT treatment techniques include free breathing (FB) SBRT and gated FB SBRT. Gated FB SBRT has smaller target and less lung toxicity with longer treatment time. The recent development of direct connectivity between the ABC and linac allowing for automated beam gating. In this study, we have examined the feasibility of using ABC system to gate the lung SBRT treatment. Methods: A CIRS lung phantom with a 3cm sphere-insert and a moving chest plate was used in this study. Sinusoidal motion was used for the FB pattern. An ABC signal was imported to simulate breath holds. 4D-CTmore » was taken in FB mode and average-intensity-projection (AIP) was used to create FB and 50% gated FB SBRT planning CT. A manually gated 3D CT scan was acquired for ABC gated SBRT planning.An SBRT plan was created for each treatment option. A surface-mapping system was used for 50% gating and ABC system was used for ABC gating. A manually gated CBCT scan was also performed to verify setup. Results: Among three options, the ABC gated plan has the smallest PTV of 35.94cc, which is 35% smaller comparing to that of the FB plan. Consequently, the V20 of the left lung reduced by 15% and 23% comparing to the 50% gated FB and FB plans, respectively. The FB plan took 4.7 minutes to deliver, while the 50% gated FB plan took 18.5 minutes. The ABC gated plan delivery took only 10.6 minutes. A stationary target with 3cm diameter was also obtained from the manually gated CBCT scan. Conclusion: A strategy for ABC gated lung SBRT was developed. ABC gating can significantly reduce the lung toxicity while maintaining the target coverage. Comparing to the 50% gated FB SBRT, ABC gated treatment can also provide less lung toxicity as well as improved delivery efficiency. This research is funded by Elekta.« less

A membrane-associated adenylate cyclase modulates lactate dehydrogenase and creatine kinase activities required for bull sperm capacitation induced by hyaluronic acid.

PubMed

Fernández, Silvina; Córdoba, Mariana

2017-04-01

Hyaluronic acid, as well as heparin, is a glycosaminoglycan present in the female genital tract of cattle. The aim of this study was to evaluate oxidative metabolism and intracellular signals mediated by a membrane-associated adenylate cyclase (mAC), in sperm capacitation with hyaluronic acid and heparin, in cryopreserved bull sperm. The mAC inhibitor, 2',5'-dideoxyadenosine, was used in the present study. Lactate dehydrogenase (LDH) and creatine kinase (CK) activities and lactate concentration were determined spectrophotometrically in the incubation medium. Capacitation and acrosome reaction were evaluated by chlortetracycline technique, while plasma membrane and acrosome integrity were determined by trypan blue stain/differential interference contrast microscopy. Heparin capacitated samples had a significant decrease in LDH and CK activities, while in hyaluronic acid capacitated samples LDH and CK activities both increased compared to control samples, in heparin and hyaluronic acid capacitation conditions, respectively. A significant increase in lactate concentration in the incubation medium occurred in hyaluronic acid-treated sperm samples compared to heparin treatment, indicating this energetic metabolite is produced during capacitation. The LDH and CK enzyme activities and lactate concentrations in the incubation medium were decreased with 2',5'-dideoxyadenosine treatment in hyaluronic acid samples. The mAC inhibitor significantly inhibited heparin-induced capacitation of sperm cells, but did not completely inhibit hyaluronic acid capacitation. Therefore, hyaluronic acid and heparin are physiological glycosaminoglycans capable of inducing in vitro capacitation in cryopreserved bull sperm, stimulating different enzymatic pathways and intracellular signals modulated by a mAC. Hyaluronic acid induces sperm capacitation involving LDH and CK activities, thereby reducing oxidative metabolism, and this process is mediated by mAC. Copyright © 2017 Elsevier B.V. All rights reserved.

Modeling methodology for a CMOS-MEMS electrostatic comb

NASA Astrophysics Data System (ADS)

Iyer, Sitaraman V.; Lakdawala, Hasnain; Mukherjee, Tamal; Fedder, Gary K.

2002-04-01

A methodology for combined modeling of capacitance and force 9in a multi-layer electrostatic comb is demonstrated in this paper. Conformal mapping-based analytical methods are limited to 2D symmetric cross-sections and cannot account for charge concentration effects at corners. Vertex capacitance can be more than 30% of the total capacitance in a single-layer 2 micrometers thick comb with 10 micrometers overlap. Furthermore, analytical equations are strictly valid only for perfectly symmetrical finger positions. Fringing and corner effects are likely to be more significant in a multi- layered CMOS-MEMS comb because of the presence of more edges and vertices. Vertical curling of CMOS-MEMS comb fingers may also lead to reduced capacitance and vertical forces. Gyroscopes are particularly sensitive to such undesirable forces, which therefore, need to be well-quantified. In order to address the above issues, a hybrid approach of superposing linear regression models over a set of core analytical models is implemented. Design of experiments is used to obtain data for capacitance and force using a commercial 3D boundary-element solver. Since accurate force values require significantly higher mesh refinement than accurate capacitance, we use numerical derivatives of capacitance values to compute the forces. The model is formulated such that the capacitance and force models use the same regression coefficients. The comb model thus obtained, fits the numerical capacitance data to within +/- 3% and force to within +/- 10%. The model is experimentally verified by measuring capacitance change in a specially designed test structure. The capacitance model matches measurements to within 10%. The comb model is implemented in an Analog Hardware Description Language (ADHL) for use in behavioral simulation of manufacturing variations in a CMOS-MEMS gyroscope.

Method for reworkable packaging of high speed, low electrical parasitic power electronics modules through gate drive integration

DOEpatents

Passmore, Brandon; Cole, Zach; Whitaker, Bret; Barkley, Adam; McNutt, Ty; Lostetter, Alexander

2016-08-02

A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

High breakdown voltage and high driving current in a novel silicon-on-insulator MESFET with high- and low-resistance boxes in the drift region

NASA Astrophysics Data System (ADS)

Naderi, Ali; Mohammadi, Hamed

2018-06-01

In this paper a novel silicon-on-insulator metal oxide field effect transistor (SOI-MESFET) with high- and low-resistance boxes (HLRB) is proposed. This structure increases the current and breakdown voltage, simultaneously. The semiconductor at the source side of the channel is doped with higher impurity than the other parts to reduce its resistance and increase the driving current as low-resistance box. An oxide box is implemented at the upper part of the channel from the drain region toward the middle of the channel as the high-resistance box. Inserting a high-resistance box increases the breakdown voltage and improves the RF performance of the device because of its higher tolerable electric field and modification in gate-drain capacitance, respectively. The high-resistance region reduces the current density of the device which is completely compensated by low-resistance box. A 92% increase in breakdown voltage and an 11% improvement in the device current have been obtained. Also, maximum oscillation frequency, unilateral power gain, maximum available gain, maximum stable gain, and maximum output power density are improved by 7%, 35%, 23%, 26%, and 150%, respectively. These results show that the HLRB-SOI-MESFET can be considered as a candidate to replace Conventional SOI-MESFET (C-SOI-MESFET) for high-voltage and high-frequency applications.

Effects of (NH4)2S x treatment on the surface properties of SiO2 as a gate dielectric for pentacene thin-film transistor applications

NASA Astrophysics Data System (ADS)

Hung, Cheng-Chun; Lin, Yow-Jon

2018-01-01

The effect of (NH4)2S x treatment on the surface properties of SiO2 is studied. (NH4)2S x treatment leads to the formation of S-Si bonds on the SiO2 surface that serves to reduce the number of donor-like trap states, inducing the shift of the Fermi level toward the conduction band minimum. A finding in this case is the noticeably reduced value of the SiO2 capacitance as the sulfurated layer is formed at the SiO2 surface. The effect of SiO2 layers with (NH4)2S x treatment on the carrier transport behaviors for the pentacene/SiO2-based organic thin-film transistor (OTFT) is also studied. The pentacene/as-cleaned SiO2-based OTFT shows depletion-mode behavior, whereas the pentacene/(NH4)2S x -treated SiO2-based OTFT exhibits enhancement-mode behavior. Experimental identification confirms that the depletion-/enhancement-mode conversion is due to the dominance competition between donor-like trap states in SiO2 near the pentacene/SiO2 interface and acceptor-like trap states in the pentacene channel. A sulfurated layer between pentacene and SiO2 is expected to give significant contributions to carrier transport for pentacene/SiO2-based OTFTs.

Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

NASA Astrophysics Data System (ADS)

Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

2013-11-01

We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

N-doped structures and surface functional groups of reduced graphene oxide and their effect on the electrochemical performance of supercapacitor with organic electrolyte

NASA Astrophysics Data System (ADS)

Li, Shin-Ming; Yang, Shin-Yi; Wang, Yu-Sheng; Tsai, Hsiu-Ping; Tien, Hsi-Wen; Hsiao, Sheng-Tsung; Liao, Wei-Hao; Chang, Chien-Liang; Ma, Chen-Chi M.; Hu, Chi-Chang

2015-03-01

Nitrogen-doped reduced graphene oxide (N-rGO) has been synthesized using a simple, efficient method combining instant thermal exfoliation and covalent bond transformation from a melamine-graphene oxide mixture. The capacitive performance of N-rGO has been tested in both aqueous (0.5 M H2SO4) and organic (1 M tetraethyl-ammonium tetrafluoroborate (TEABF4) in propylene carbonate (PC)) electrolytes, which are compared with those obtained from thermal-reduced graphene oxide (T-rGO) and chemical-reduced graphene oxide (C-rGO). The contributions of scan-rate-independent (double-layer-like) and scan-rate-dependent (pseudo-capacitance-like) capacitance of all reduced graphene oxides in both aqueous and organic electrolytes were evaluated and compared. The results show that relatively rich oxygen-containing functional groups on C-rGO form significant ion-diffusion barrier, resulting in worse electrochemical responses in organic electrolyte. By contrast, the N-doped structures, large surface area, and lower density of oxygen-containing groups make N-rGO become a promising electrode material for organic electric double-layer capacitors (EDLCs). The capacitance rate-retention of N-rGO reaches 71.1% in 1 M TEABF4/PC electrolyte when the scan rate is elevated to 200 mVs-1, demonstrating that N-rGO improves the relatively low-power drawback of EDLCs in organic electrolytes. The specific energy and power of a symmetric N-rGO cell in the organic electrolyte reach 25 Wh kg-1 and 10 kW kg-1, respectively.

Flexible Graphene Transistor Architecture for Optical Sensor Technology

NASA Astrophysics Data System (ADS)

Ordonez, Richard Christopher

The unique electrical and optoelectronic properties of graphene allow tunable conductivity and broadband electromagnetic absorption that spans the ultraviolet and infrared regimes. However, in the current state-of-art graphene sensor architectures, junction resistance and doping concentration are predominant factors that affect signal strength and sensitivity. Unfortunately, graphene produces high contact resistances with standard electrode materials ( few kilo-ohms), therefore, signal is weak and large carrier concentrations are required to probe sensitivity. Moreover, the atomic thickness of graphene enables the potential for flexible electronics, but there has not been a successful graphene sensor architecture that demonstrates stable operation on flexible substrates and with minimal fabrication cost. In this study, the author explores a novel 3-terminal transistor architecture that integrates twodimensional graphene, liquid metal, and electrolytic gate dielectrics (LM-GFETs: Liquid Metal and Graphene Field-Effect Transistors ). The goal is to deliver a sensitive, flexible, and lightweight transistor architecture that will improve sensor technology and maneuverability. The reported high thermal conductivity of graphene provides potential for room-temperature thermal management without the need of thermal-electric and gas cooling systems that are standard in sensor platforms. Liquid metals provide a unique opportunity for conformal electrodes that maximize surface area contact, therefore, enable flexibility, lower contact resistance, and reduce damage to the graphene materials involved. Lastly, electrolytic gate dielectrics provide conformability and high capacitances needed for high on/off rations and electrostatic gating. Results demonstrated that with minimal fabrication steps the proposed flexible graphene transistor architecture demonstrated ambipolar current-voltage transfer characteristics that are comparable to the current state-of-the-art. An additional investigation demonstrated PN junction operation and the successful integration of the proposed architecture into an optoelectronic application with the use of semiconductor quantum dots in contact with the graphene material that acted as optical absorbers to increase detector gain. Applications that can benefit from such technology advancement include Nano-satellites (Nanosat), Underwater autonomous vehicles (UAV), and airborne platforms in which flexibility and sensitivity are critical parameters that must be optimized to increase mission duration and range.

Energy-loss return gate via liquid dielectric polarization.

PubMed

Kim, Taehun; Yong, Hyungseok; Kim, Banseok; Kim, Dongseob; Choi, Dukhyun; Park, Yong Tae; Lee, Sangmin

2018-04-12

There has been much research on renewable energy-harvesting techniques. However, owing to increasing energy demands, significant energy-related issues remain to be solved. Efforts aimed at reducing the amount of energy loss in electric/electronic systems are essential for reducing energy consumption and protecting the environment. Here, we design an energy-loss return gate system that reduces energy loss from electric/electronic systems by utilizing the polarization of liquid dielectrics. The use of a liquid dielectric material in the energy-loss return gate generates electrostatic potential energy while reducing the dielectric loss of the electric/electronic system. Hence, an energy-loss return gate can make breakthrough impacts possible by amplifying energy-harvesting efficiency, lowering the power consumption of electronics, and storing the returned energy. Our study indicates the potential for enhancing energy-harvesting technologies for electric/electronics systems, while increasing the widespread development of these systems.

Audio-visual biofeedback for respiratory-gated radiotherapy: Impact of audio instruction and audio-visual biofeedback on respiratory-gated radiotherapy

DOE Office of Scientific and Technical Information (OSTI.GOV)

George, Rohini; Department of Biomedical Engineering, Virginia Commonwealth University, Richmond, VA; Chung, Theodore D.

2006-07-01

Purpose: Respiratory gating is a commercially available technology for reducing the deleterious effects of motion during imaging and treatment. The efficacy of gating is dependent on the reproducibility within and between respiratory cycles during imaging and treatment. The aim of this study was to determine whether audio-visual biofeedback can improve respiratory reproducibility by decreasing residual motion and therefore increasing the accuracy of gated radiotherapy. Methods and Materials: A total of 331 respiratory traces were collected from 24 lung cancer patients. The protocol consisted of five breathing training sessions spaced about a week apart. Within each session the patients initially breathedmore » without any instruction (free breathing), with audio instructions and with audio-visual biofeedback. Residual motion was quantified by the standard deviation of the respiratory signal within the gating window. Results: Audio-visual biofeedback significantly reduced residual motion compared with free breathing and audio instruction. Displacement-based gating has lower residual motion than phase-based gating. Little reduction in residual motion was found for duty cycles less than 30%; for duty cycles above 50% there was a sharp increase in residual motion. Conclusions: The efficiency and reproducibility of gating can be improved by: incorporating audio-visual biofeedback, using a 30-50% duty cycle, gating during exhalation, and using displacement-based gating.« less

Cocaine sensitization increases subthreshold activity in dopamine neurons from the ventral tegmental area.

PubMed

Arencibia-Albite, Francisco; Vázquez-Torres, Rafael; Jiménez-Rivera, Carlos A

2017-02-01

The progressive escalation of psychomotor responses that results from repeated cocaine administration is termed sensitization. This phenomenon alters the intrinsic properties of dopamine (DA) neurons from the ventral tegmental area (VTA), leading to enhanced dopaminergic transmission in the mesocorticolimbic network. The mechanisms underlying this augmented excitation are nonetheless poorly understood. DA neurons display the hyperpolarization-activated, nonselective cation current, dubbed I h We recently demonstrated that I h and membrane capacitance are substantially reduced in VTA DA cells from cocaine-sensitized rats. The present study shows that 7 days of cocaine withdrawal did not normalize I h and capacitance. In cells from cocaine-sensitized animals, the amplitude of excitatory synaptic potentials, at -70 mV, was ∼39% larger in contrast to controls. Raise and decay phases of the synaptic signal were faster under cocaine, a result associated with a reduced membrane time constant. Synaptic summation was paradoxically elevated by cocaine exposure, as it consisted of a significantly reduced summation indexed but a considerably increased depolarization. These effects are at least a consequence of the reduced capacitance. I h attenuation is unlikely to explain such observations, since at -70 mV, no statistical differences exist in I h or input resistance. The neuronal shrinkage associated with a diminished capacitance may help to understand two fundamental elements of drug addiction: incentive sensitization and negative emotional states. A reduced cell size may lead to substantial enhancement of cue-triggered bursting, which underlies drug craving and reward anticipation, whereas it could also result in DA depletion, as smaller neurons might express low levels of tyrosine hydroxylase. This work uses a new approach that directly extracts important biophysical parameters from alpha function-evoked synaptic potentials. Two of these parameters are the cell membrane capacitance (C m ) and rate at any time point of the synaptic waveform. The use of such methodology shows that cocaine sensitization reduces C m and increases the speed of synaptic signaling. Paradoxically, although synaptic potentials show a faster decay under cocaine their temporal summation is substantially elevated. Copyright © 2017 the American Physiological Society.

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario; Rafferty, Conor; Saini, Subhash (Technical Monitor)

1999-01-01

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

Damage free Ar ion plasma surface treatment on In{sub 0.53}Ga{sub 0.47}As-on-silicon metal-oxide-semiconductor device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koh, Donghyi; Shin, Seung Heon; Ahn, Jaehyun

2015-11-02

In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}),more » which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.« less

A Novel Passive Wireless Sensor for Concrete Humidity Monitoring.

PubMed

Zhou, Shuangxi; Deng, Fangming; Yu, Lehua; Li, Bing; Wu, Xiang; Yin, Baiqiang

2016-09-20

This paper presents a passive wireless humidity sensor for concrete monitoring. After discussing the transmission of electromagnetic wave in concrete, a novel architecture of wireless humidity sensor, based on Ultra-High Frequency (UHF) Radio Frequency Identification (RFID) technology, is proposed for low-power application. The humidity sensor utilizes the top metal layer to form the interdigitated electrodes, which were then filled with polyimide as the humidity sensing layer. The sensor interface converts the humidity capacitance into a digital signal in the frequency domain. A two-stage rectifier adopts a dynamic bias-voltage generator to boost the effective gate-source voltage of the switches in differential-drive architecture. The clock generator employs a novel structure to reduce the internal voltage swing. The measurement results show that our proposed wireless humidity can achieve a high linearity with a normalized sensitivity of 0.55% %RH at 20 °C. Despite the high losses of concrete, the proposed wireless humidity sensor achieves reliable communication performances in passive mode. The maximum operating distance is 0.52 m when the proposed wireless sensor is embedded into the concrete at the depth of 8 cm. The measured results are highly consistent with the results measured by traditional methods.

A Novel Passive Wireless Sensor for Concrete Humidity Monitoring

PubMed Central

Zhou, Shuangxi; Deng, Fangming; Yu, Lehua; Li, Bing; Wu, Xiang; Yin, Baiqiang

2016-01-01

This paper presents a passive wireless humidity sensor for concrete monitoring. After discussing the transmission of electromagnetic wave in concrete, a novel architecture of wireless humidity sensor, based on Ultra-High Frequency (UHF) Radio Frequency Identification (RFID) technology, is proposed for low-power application. The humidity sensor utilizes the top metal layer to form the interdigitated electrodes, which were then filled with polyimide as the humidity sensing layer. The sensor interface converts the humidity capacitance into a digital signal in the frequency domain. A two-stage rectifier adopts a dynamic bias-voltage generator to boost the effective gate-source voltage of the switches in differential-drive architecture. The clock generator employs a novel structure to reduce the internal voltage swing. The measurement results show that our proposed wireless humidity can achieve a high linearity with a normalized sensitivity of 0.55% %RH at 20 °C. Despite the high losses of concrete, the proposed wireless humidity sensor achieves reliable communication performances in passive mode. The maximum operating distance is 0.52 m when the proposed wireless sensor is embedded into the concrete at the depth of 8 cm. The measured results are highly consistent with the results measured by traditional methods. PMID:27657070

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

SU-E-J-169: The Dosimetric and Temporal Effects of Respiratory-Gated Radiation Therapy in Lung Cancer Patients

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rouabhi, O; Gross, B; Xia, J

2015-06-15

Purpose: To evaluate the dosimetric and temporal effects of high dose rate treatment mode for respiratory-gated radiation therapy in lung cancer patients. Methods: Treatment plans from five lung cancer patients (3 nongated (Group 1), 2 gated at 80EX-80IN (Group 2)) were retrospectively evaluated. The maximum tumor motions range from 6–12 mm. Using the same planning criteria, four new treatment plans, corresponding to four gating windows (20EX–20IN, 40EX–40IN, 60EX–60IN, and 80EX–80IN), were generated for each patient. Mean tumor dose (MTD), mean lung dose (MLD), and lung V20 were used to assess the dosimetric effects. A MATLAB algorithm was developed to computemore » treatment time by considering gantry rotation time, time to position collimator leaves, dose delivery time (scaled relative to the gating window), and communication overhead. Treatment delivery time for each plan was estimated using a 500 MU/min dose rate for the original plans and a 1500 MU/min dose rate for the gated plans. Results: Differences in MTD were less than 1Gy across plans for all five patients. MLD and lung V20 were on average reduced between −16.1% to −6.0% and −20.0% to −7.2%, respectively for non-gated plans when compared with the corresponding gated plans, and between − 5.8% to −4.2% and −7.0% to −5.4%, respectively for plans originally gated at 80EX–80IN when compared with the corresponding 20EX-20IN to 60EX– 60IN gated plans. Treatment delivery times of gated plans using high dose rate were reduced on average between −19.7% (−1.9min) to −27.2% (−2.7min) for originally non-gated plans and −15.6% (−0.9min) to −20.3% (−1.2min) for originally 80EX-80IN gated plans. Conclusion: Respiratory-gated radiation therapy in lung cancer patients can reduce lung toxicity, while maintaining tumor dose. Using a gated high-dose-rate treatment, delivery time comparable to non-gated normal-dose-rate treatment can be achieved. This research is supported by Siemens Medical Solutions USA, Inc.« less

Germanium MOS capacitors grown on Silicon using low temperature RF-PECVD

NASA Astrophysics Data System (ADS)

Dushaq, Ghada; Rasras, Mahmoud; Nayfeh, Ammar

2017-10-01

In this paper, Ge metal-oxide-semiconductor capacitors (MOSCAPs) are fabricated on Si using a low temperature two-step deposition technique by radio frequency plasma enhanced chemical vapor deposition. The MOSCAP gate stack consists of atomic layer deposition of Al2O3 as the gate oxide and a Ti/Al metal gate electrode. The electrical characteristics of 9 nm Al2O3/i-Ge/Si MOSCAPs exhibit an n-type (p-channel) behavior and normal high frequency C-V responses. In addition to CV measurements, the gate leakage versus the applied voltage is measured and discussed. Moreover, the electrical behavior is discussed in terms of the material and interface quality. The Ge/high-k interface trap density versus the surface potential is extracted using the most commonly used methods in detemining the interface traps based on the capacitance-voltage (C-V) curves. The discussion included the Dit calculation from the conductance method, the high-low frequency (Castagné-Vapaille) method, and the Terman (high-frequency) method. Furthermore, the origins of the discrepancies in the interface trap densities determined from the different methods are discussed. The study of the post annealed Ge layers at different temperatures in H2 and N2 gas ambient revealed an improved electrical and transport properties of the films treated at T  <  600 °C. Also, samples annealed at  <550 °C show the lowest threading dislocation density of ~1  ×  106 cm-2. The low temperature processing of Ge/Si demonstrates a great potential for p-channel transistor applications in a monolithically integrated CMOS platform.

GATE Monte Carlo simulation of dose distribution using MapReduce in a cloud computing environment.

PubMed

Liu, Yangchuan; Tang, Yuguo; Gao, Xin

2017-12-01

The GATE Monte Carlo simulation platform has good application prospects of treatment planning and quality assurance. However, accurate dose calculation using GATE is time consuming. The purpose of this study is to implement a novel cloud computing method for accurate GATE Monte Carlo simulation of dose distribution using MapReduce. An Amazon Machine Image installed with Hadoop and GATE is created to set up Hadoop clusters on Amazon Elastic Compute Cloud (EC2). Macros, the input files for GATE, are split into a number of self-contained sub-macros. Through Hadoop Streaming, the sub-macros are executed by GATE in Map tasks and the sub-results are aggregated into final outputs in Reduce tasks. As an evaluation, GATE simulations were performed in a cubical water phantom for X-ray photons of 6 and 18 MeV. The parallel simulation on the cloud computing platform is as accurate as the single-threaded simulation on a local server and the simulation correctness is not affected by the failure of some worker nodes. The cloud-based simulation time is approximately inversely proportional to the number of worker nodes. For the simulation of 10 million photons on a cluster with 64 worker nodes, time decreases of 41× and 32× were achieved compared to the single worker node case and the single-threaded case, respectively. The test of Hadoop's fault tolerance showed that the simulation correctness was not affected by the failure of some worker nodes. The results verify that the proposed method provides a feasible cloud computing solution for GATE.

Modelling of cardiac-related changes in lung resistivity measured with EITS.

PubMed

Zhao, T X; Brown, B H; Nopp, P; Wang, W; Leathard, A D; Lu, L Q

1996-11-01

Resistivity data from 9.6 kHZ to 1.2 MHz were recorded from eight normal subjects using an electrical impedance tomographic spectroscopy (EITS) system and then averaged to a mean cardiac cycle using the ECG gating technique. The Cole-Cole model, that is, extracellular resistance R connected in parallel with intracellular resistance S and membrane capacitance C in series, with a distribution parameter a, was applied to model the frequency characteristics and to produce parametric images. During systole, SC and RC were found to decrease and FR increase. The changes in R/S were not consistent among the subjects. We estimated the peak changes in R, S and C to be -2.5%, -3.3% and -7.6% respectively. The results can be explained by considering the blood vessels as spheres of different sizes with blood inside them. The decrease in R during systole might be caused by the increased blood content in relatively large vessels, whereas that in S by the increased blood volume in relatively small vessels. The capacitance of blood is normally smaller than that of lung tissue, whereas FR blood is higher than that of lung tissue. Hence, as blood content increases, C should decrease and FR increase.

Quantum phase transition and Coulomb blockade effect in triangular quantum dots with interdot capacitive and tunnel couplings

NASA Astrophysics Data System (ADS)

Xiong, Yong-Chen; Wang, Wei-Zhong; Yang, Jun-Tao; Huang, Hai-Ming

2015-02-01

The quantum phase transition and the electronic transport in a triangular quantum dot system are investigated using the numerical renormalization group method. We concentrate on the interplay between the interdot capacitive coupling V and the interdot tunnel coupling t. For small t, three dots form a local spin doublet. As t increases, due to the competition between V and t, there exist two first-order transitions with phase sequence spin-doublet-magnetic frustration phase-orbital spin singlet. When t is absent, the evolutions of the total charge on the dots and the linear conductance are of the typical Coulomb-blockade features with increasing gate voltage. While for sufficient t, the antiferromagnetic spin correlation between dots is enhanced, and the conductance is strongly suppressed for the bonding state is almost doubly occupied. Project supported by the National Natural Science Foundation of China (Grant Nos. 10874132 and 11174228) and the Doctoral Scientific Research Foundation of HUAT (Grant No. BK201407). One of the authors (Huang Hai-Ming) supported by the Scientific Research Items Foundation of Educational Committee of Hubei Province, China (Grant No. Q20131805).

Layout optimization of GGISCR structure for on-chip system level ESD protection applications

NASA Astrophysics Data System (ADS)

Zeng, Jie; Dong, Shurong; Wong, Hei; Hu, Tao; Li, Xiang

2016-12-01

To improve the holding voltage, area efficiency and robustness, a comparative study on single finger, 4-finger and round shape layout of gate-grounded-nMOS incorporated SCR (GGISCR) devices are conducted. The devices were fabricated with a commercial 0.35 μm HV-CMOS process without any additional mask or process modification. To have a fair comparison, we develop a new Figure-of-Merit (FOM) modeling for the performance evaluation of these devices. We found that the ring type device which has an It2 value of 18.9 A is area efficient and has smaller effective capacitance. The different characteristics were explained with the different effective ESD currents in these layout structures.

Mapping from multiple-control Toffoli circuits to linear nearest neighbor quantum circuits

NASA Astrophysics Data System (ADS)

Cheng, Xueyun; Guan, Zhijin; Ding, Weiping

2018-07-01

In recent years, quantum computing research has been attracting more and more attention, but few studies on the limited interaction distance between quantum bits (qubit) are deeply carried out. This paper presents a mapping method for transforming multiple-control Toffoli (MCT) circuits into linear nearest neighbor (LNN) quantum circuits instead of traditional decomposition-based methods. In order to reduce the number of inserted SWAP gates, a novel type of gate with the optimal LNN quantum realization was constructed, namely NNTS gate. The MCT gate with multiple control bits could be better cascaded by the NNTS gates, in which the arrangement of the input lines was LNN arrangement of the MCT gate. Then, the communication overhead measurement model on inserted SWAP gate count from the original arrangement to the new arrangement was put forward, and we selected one of the LNN arrangements with the minimum SWAP gate count. Moreover, the LNN arrangement-based mapping algorithm was given, and it dealt with the MCT gates in turn and mapped each MCT gate into its LNN form by inserting the minimum number of SWAP gates. Finally, some simplification rules were used, which can further reduce the final quantum cost of the LNN quantum circuit. Experiments on some benchmark MCT circuits indicate that the direct mapping algorithm results in fewer additional SWAP gates in about 50%, while the average improvement rate in quantum cost is 16.95% compared to the decomposition-based method. In addition, it has been verified that the proposed method has greater superiority for reversible circuits cascaded by MCT gates with more control bits.

Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Colon, Albert; Stan, Liliana; Divan, Ralu

Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approachmore » this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material for both AlGaN/GaN and InAlN/GaN based devices.« less

CMOS SiPM with integrated amplifier

NASA Astrophysics Data System (ADS)

Schwinger, Alexander; Brockherde, Werner; Hosticka, Bedrich J.; Vogt, Holger

2017-02-01

The integration of silicon photomultiplier (SiPM) and frontend electronics in a suitable optoelectronic CMOS process is a promising approach to increase the versatility of single-photon avalanche diode (SPAD)-based singlephoton detectors. By integrating readout amplifiers, the device output capacitance can be reduced to minimize the waveform tail, which is especially important for large area detectors (>10 × 10mm2). Possible architectures include a single readout amplifier for the whole detector, which reduces the output capacitance to 1:1 pF at minimal reduction in detector active area. On the other hand, including a readout amplifier in every SiPM cell would greatly improve the total output capacitance by minimizing the influence of metal routing parasitic capacitance, but requiring a prohibitive amount of detector area. As tradeoff, the proposed detector features one readout amplifier for each column of the detector matrix to allow for a moderate reduction in output capacitance while allowing the electronics to be placed in the periphery of the active detector area. The presented detector with a total size of 1.7 ♢ 1.0mm2 features 400 cells with a 50 μm pitch, where the signal of each column of 20 SiPM cells is summed in a readout channel. The 20 readout channels are subsequently summed into one output channel, to allow the device to be used as a drop-in replacement for commonly used analog SiPMs.

Membrane status and in vitro capacitation of porcine sperm preserved in long-term extender at 16 degrees C.

PubMed

Conejo-Nava, J; Fierro, R; Gutierrez, C G; Betancourt, M

2003-01-01

Preservation of porcine semen in long-term extenders at 15-18 degrees C for more than 5 days results in decreased farrowing rates and reduced litter size after artificial insemination, despite the high progressive motility rates of sperm. To improve this preservation system it is necessary to understand sperm physiology under storage conditions. The purpose of this study was to determine the effect of storing diluted porcine semen (during 0, 2, 4, 6, and 8 days) on the sperm membranes status and the ability of sperm to respond to in vitro capacitation treatment. Ten semen samples from 5 adult boars were analyzed. Two aliquots were obtained from the sperm-rich fraction: one was used to assess fresh semen and the other was diluted in Reading extender and stored at 16 degrees C. Both semen samples were stained with chlortetracycline to assess the status of sperm membranes and with Hoechst 33258 to determine viability. Semen storage for 4-8 days increased the proportion of prematurely capacitated sperm. After 4 days of storage, in vitro capacitation treatment did not increase the percentage of capacitated sperm, but increased the percentage of acrosome reacted sperm. This phenomenon could explain the reduced fertilizing ability of porcine semen stored at 16 degrees C for over 4 days, in spite of the acceptable sperm viability and progressive motility.

Three Dimensional Nitrogen-Doped and Nitrogen, Sulfur-Codoped Graphene Hydrogels for Electrode Materials in Supercapacitors.

PubMed

Yuan, Zhao; Qiao, Fei; Wang, Guiqiang; Zhou, Jin; Cui, Hongyou; Zhuo, Shuping; Xing, Ling-Bao

2018-08-01

In present work, reduced graphene oxide hydrogels (RGOHs) with three-dimensional (3D) porous structure are prepared through chemical reduction method by using aminourea (NRGOHs) and aminothiourea (NSRGOHs) as reductants. The as-prepared RGOHs are considered not only as promising electrode materials for supercapacitors, but also the doping of nitrogen (aminourea, NRGOHs) or nitrogen/sulfur (aminothiourea, NSRGOHs) can improve electrochemical performance through faradaic pseudocapacitance. The optimized samples have been prepared by controlling the mass ratios of graphene oxide (GO) to aminourea or aminothiourea to be 1:1, 1:2 and 1:5, respectively. With adding different amounts of aminourea or aminothiourea, the obtained RGOHs exhibited different electrochemical performance in supercapacitors. With increasing the dosage of the reductants, the RGOHs revealed better specific capacitances. Moreover, NSRGOHs with nitrogen, sulfur-codoping exhibited better capacitance performance than that of NRGOHs with only nitrogen-doping. NSRGOHs showed excellent capacitive performance with a very high specific capacitance up to 232.2, 323.3 and 345.6 F g-1 at 0.2 A g-1, while NRGOHs showed capacitive performance with specific capacitance up to 220.6, 306.5 and 332.7 F g-1 at 0.2 A g-1. This provides a strategy to improve the capacitive properties of RGOHs significantly by controlling different doping the materials.

High-Sensitivity Encoder-Like Micro Area-Changed Capacitive Transducer for a Nano-g Micro Accelerometer

PubMed Central

Zheng, Panpan; Liu, Jinquan; Li, Zhu; Liu, Huafeng

2017-01-01

Encoder-like micro area-changed capacitive transducers are advantageous in terms of their better linearity and larger dynamic range compared to gap-changed capacitive transducers. Such transducers have been widely applied in rectilinear and rotational position sensors, lab-on-a-chip applications and bio-sensors. However, a complete model accounting for both the parasitic capacitance and fringe effect in area-changed capacitive transducers has not yet been developed. This paper presents a complete model for this type of transducer applied to a high-resolution micro accelerometer that was verified by both simulations and experiments. A novel optimization method involving the insertion of photosensitive polyimide was used to reduce the parasitic capacitance, and the capacitor spacing was decreased to overcome the fringe effect. The sensitivity of the optimized transducer was approximately 46 pF/mm, which was nearly 40 times higher than that of our previous transducer. The displacement detection resolution was measured as 50 pm/√Hz at 0.1 Hz using a precise capacitance detection circuit. Then, the transducer was applied to a sandwich in-plane micro accelerometer, and the measured level of the accelerometer was approximately 30 ng/√Hz at 1Hz. The earthquake that occurred in Taiwan was also detected during a continuous gravity measurement. PMID:28930176

Differential Depletion Capacitance Approximation Analysis Under DC Voltage for Air-Exposed Cu/n-Si Schottky Diodes

NASA Astrophysics Data System (ADS)

Korkut, A.

It is well known that the semiconductor surface is easily oxidized by air-media in time. This work studieds the characterization of Schottky diodes and changes in depletion capacitance, which is caused by air exposure of a group of Cu/n-Si/Al Schottky diodes. First, data for current-voltage and capacitance-voltage were a Ren, and then ideality factor, barrier height, built-in potential (Vbi), donor concentration and Fermi level, interfacial oxide thickness, interface state density were calculated. It is seen that depletion capacitance was calculate; whereafter built-in potential played an important role in Schottky diodes characteristic. Built-in potential directly affects the characteristic of Schottky diodes and a turning point occurs. In case of forward and reverse bias, depletion capacitance versus voltage graphics are matched, but in an opposite direction. In case of forward bias, differential depletion capacitance begins from minus values, it is raised to first Vbi, then reduced to second Vbi under the minus condition. And it sharply gones up to positive apex, then sharply falls down to near zero, but it takes positive values depending on DC voltage. In case of reverse bias, differential depletion capacitance takes to small positive values. In other respects, we see that depletion characteristics change considerably under DC voltage.

Utility of Electrocardiography (ECG)-Gated Computed Tomography (CT) for Preoperative Evaluations of Thymic Epithelial Tumors.

PubMed

Ozawa, Yoshiyuki; Hara, Masaki; Nakagawa, Motoo; Shibamoto, Yuta

2016-01-01

Preoperative evaluation of invasion to the adjacent organs is important for the thymic epithelial tumors on CT. The purpose of our study was to evaluate the utility of electrocardiography (ECG)-gated CT for assessing thymic epithelial tumors with regard to the motion artifacts produced and the preoperative diagnostic accuracy of the technique. Forty thymic epithelial tumors (36 thymomas and 4 thymic carcinomas) were examined with ECG-gated contrast-enhanced CT using a dual source scanner. The scan delay after the contrast media injection was 30 s for the non-ECG-gated CT and 100 s for the ECG-gated CT. Two radiologists blindly evaluated both the non-ECG-gated and ECG-gated CT images for motion artifacts and determined whether the tumors had invaded adjacent structures (mediastinal fat, superior vena cava, brachiocephalic veins, aorta, pulmonary artery, pericardium, or lungs) on each image. Motion artifacts were evaluated using a 3-grade scale. Surgical and pathological findings were used as a reference standard for tumor invasion. Motion artifacts were significantly reduced for all structures by ECG gating ( p =0.0089 for the lungs and p <0.0001 for the other structures). Non-ECG-gated CT and ECG-gated CT demonstrated 79% and 95% accuracy, respectively, during assessments of pericardial invasion ( p =0.03). ECG-gated CT reduced the severity of motion artifacts and might be useful for preoperative assessment whether thymic epithelial tumors have invaded adjacent structures.

Utility of Electrocardiography (ECG)-Gated Computed Tomography (CT) for Preoperative Evaluations of Thymic Epithelial Tumors

PubMed Central

Ozawa, Yoshiyuki; Hara, Masaki; Nakagawa, Motoo; Shibamoto, Yuta

2016-01-01

Summary Background Preoperative evaluation of invasion to the adjacent organs is important for the thymic epithelial tumors on CT. The purpose of our study was to evaluate the utility of electrocardiography (ECG)-gated CT for assessing thymic epithelial tumors with regard to the motion artifacts produced and the preoperative diagnostic accuracy of the technique. Material/Methods Forty thymic epithelial tumors (36 thymomas and 4 thymic carcinomas) were examined with ECG-gated contrast-enhanced CT using a dual source scanner. The scan delay after the contrast media injection was 30 s for the non-ECG-gated CT and 100 s for the ECG-gated CT. Two radiologists blindly evaluated both the non-ECG-gated and ECG-gated CT images for motion artifacts and determined whether the tumors had invaded adjacent structures (mediastinal fat, superior vena cava, brachiocephalic veins, aorta, pulmonary artery, pericardium, or lungs) on each image. Motion artifacts were evaluated using a 3-grade scale. Surgical and pathological findings were used as a reference standard for tumor invasion. Results Motion artifacts were significantly reduced for all structures by ECG gating (p=0.0089 for the lungs and p<0.0001 for the other structures). Non-ECG-gated CT and ECG-gated CT demonstrated 79% and 95% accuracy, respectively, during assessments of pericardial invasion (p=0.03). Conclusions ECG-gated CT reduced the severity of motion artifacts and might be useful for preoperative assessment whether thymic epithelial tumors have invaded adjacent structures. PMID:27920842

Highly compressible reduced graphene oxide/polypyrrole/MnO2 aerogel electrodes meeting the requirement of limiting space

NASA Astrophysics Data System (ADS)

Lv, Peng; Tang, Xun; Yuan, Jiajiao; Ji, Chenglong

2017-11-01

Highly compressible electrodes are in high demand in volume-restricted energy storage devices. Superelastic reduced graphene oxide (rGO) aerogel with attractive characteristics are proposed as the promising skeleton for compressible electrodes. Herein, a ternary aerogel was prepared by successively electrodepositing polypyrrole (PPy) and MnO2 into the superelastic rGO aerogel. In the rGO/PPy/MnO2 aerogel, rGO aerogel provides the continuously conductive network; MnO2 is mainly responsible for pseudo reactions; the middle PPy layer not only reduces the interface resistance between rGO and MnO2, but also further enhanced the mechanical strength of rGO backbone. The synergistic effect of the three components leads to excellent performances including high specific capacitance, reversible compressibility, and extreme durability. The gravimetric capacitance of the compressible rGO/PPy/MnO2 aerogel electrodes reaches 366 F g-1 and can retain 95.3% even under 95% compressive strain. And a volumetric capacitance of 138 F cm-3 is achieved, which is much higher than that of other rGO-based compressible electrodes. This volumetric capacitance value can be preserved by 85% after 3500 charge/discharge cycles with various compression conditions. This work will pave the way for advanced applications in the area of compressible energy-storage devices meeting the requirement of limiting space.

Improved two-photon imaging of living neurons in brain tissue through temporal gating

PubMed Central

Gautam, Vini; Drury, Jack; Choy, Julian M. C.; Stricker, Christian; Bachor, Hans-A.; Daria, Vincent R.

2015-01-01

We optimize two-photon imaging of living neurons in brain tissue by temporally gating an incident laser to reduce the photon flux while optimizing the maximum fluorescence signal from the acquired images. Temporal gating produces a bunch of ~10 femtosecond pulses and the fluorescence signal is improved by increasing the bunch-pulse energy. Gating is achieved using an acousto-optic modulator with a variable gating frequency determined as integral multiples of the imaging sampling frequency. We hypothesize that reducing the photon flux minimizes the photo-damage to the cells. Our results, however, show that despite producing a high fluorescence signal, cell viability is compromised when the gating and sampling frequencies are equal (or effectively one bunch-pulse per pixel). We found an optimum gating frequency range that maintains the viability of the cells while preserving a pre-set fluorescence signal of the acquired two-photon images. The neurons are imaged while under whole-cell patch, and the cell viability is monitored as a change in the membrane’s input resistance. PMID:26504651

Quantifying the impact of respiratory-gated 4D CT acquisition on thoracic image quality: A digital phantom study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernatowicz, K., E-mail: kingab@student.ethz.ch; Knopf, A.; Lomax, A.

Purpose: Prospective respiratory-gated 4D CT has been shown to reduce tumor image artifacts by up to 50% compared to conventional 4D CT. However, to date no studies have quantified the impact of gated 4D CT on normal lung tissue imaging, which is important in performing dose calculations based on accurate estimates of lung volume and structure. To determine the impact of gated 4D CT on thoracic image quality, the authors developed a novel simulation framework incorporating a realistic deformable digital phantom driven by patient tumor motion patterns. Based on this framework, the authors test the hypothesis that respiratory-gated 4D CTmore » can significantly reduce lung imaging artifacts. Methods: Our simulation framework synchronizes the 4D extended cardiac torso (XCAT) phantom with tumor motion data in a quasi real-time fashion, allowing simulation of three 4D CT acquisition modes featuring different levels of respiratory feedback: (i) “conventional” 4D CT that uses a constant imaging and couch-shift frequency, (ii) “beam paused” 4D CT that interrupts imaging to avoid oversampling at a given couch position and respiratory phase, and (iii) “respiratory-gated” 4D CT that triggers acquisition only when the respiratory motion fulfills phase-specific displacement gating windows based on prescan breathing data. Our framework generates a set of ground truth comparators, representing the average XCAT anatomy during beam-on for each of ten respiratory phase bins. Based on this framework, the authors simulated conventional, beam-paused, and respiratory-gated 4D CT images using tumor motion patterns from seven lung cancer patients across 13 treatment fractions, with a simulated 5.5 cm{sup 3} spherical lesion. Normal lung tissue image quality was quantified by comparing simulated and ground truth images in terms of overall mean square error (MSE) intensity difference, threshold-based lung volume error, and fractional false positive/false negative rates. Results: Averaged across all simulations and phase bins, respiratory-gating reduced overall thoracic MSE by 46% compared to conventional 4D CT (p ∼ 10{sup −19}). Gating leads to small but significant (p < 0.02) reductions in lung volume errors (1.8%–1.4%), false positives (4.0%–2.6%), and false negatives (2.7%–1.3%). These percentage reductions correspond to gating reducing image artifacts by 24–90 cm{sup 3} of lung tissue. Similar to earlier studies, gating reduced patient image dose by up to 22%, but with scan time increased by up to 135%. Beam paused 4D CT did not significantly impact normal lung tissue image quality, but did yield similar dose reductions as for respiratory-gating, without the added cost in scanning time. Conclusions: For a typical 6 L lung, respiratory-gated 4D CT can reduce image artifacts affecting up to 90 cm{sup 3} of normal lung tissue compared to conventional acquisition. This image improvement could have important implications for dose calculations based on 4D CT. Where image quality is less critical, beam paused 4D CT is a simple strategy to reduce imaging dose without sacrificing acquisition time.« less

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

Eco-friendly wood-based solid-state flexible supercapacitors from wood transverse section slice and reduced graphene oxide

NASA Astrophysics Data System (ADS)

Lv, Shaoyi; Fu, Feng; Wang, Siqun; Huang, Jingda; Hu, La

2015-07-01

An interesting wood-based all-solid-state supercapacitor is produced using reduced graphene oxide (RGO) coated on wood transverse section slice (WTSS) as electrode material by means of a low-cost, eco-friendly, and simple method for the first time. The RGO-coated WTSS electrode has a porous 3D honeycomb framework due to the hierarchical cellular structure of the WTSS substrate and can function as an electrolyte reservoir. This special construction endows this novel electrode with good areal capacitance (102 mF cm-2) and excellent cyclic stability (capacitance retention of 98.9% after 5000 cycles). In addition, the supercapacitors exhibit good mechanical flexibility and preserve almost constant capacitive behavior under different bending conditions. Our study introduces a new and eco-friendly material design for electrodes in future flexible energy storage devices that closely resemble natural materials. [Figure not available: see fulltext.

Three-dimensional sulphur/nitrogen co-doped reduced graphene oxide as high-performance supercapacitor binder-free electrodes

NASA Astrophysics Data System (ADS)

Huo, Jinghao; Zheng, Peng; Wang, Xiaofei; Guo, Shouwu

2018-06-01

Sulphur/nitrogen co-doped reduced graphene oxide (SNG) aerogels were prepared by a simple solvothermal method with l-cysteine-assisted in ethylene glycol. The morphology and composition tests showed that the S/N heteroatoms were evenly distributed on SNG microsheets, and these microsheets were further composed of SNG aerogels with three-dimensional (3D) porous structure. The cyclic voltammetry and galvanostatic charge/discharge tests illustrated the SNG bind-free electrode possessed electric double-layer capacitance and pseudocapacitance, and had a capacitance of 254 F g-1 at a current density of 1 A g-1. After the 5000 cycles tests, the capacitance retained 83.54% at a current density of 2 A g-1. Meanwhile, the electrochemical impedance spectroscopy data shown the electrode materials had excellent capacity and good conductivity. Hence, the SNG aerogel prepared by l-cysteine-assisted solvothermal method is a great material for high-performance supercapacitors.

Multi-images deconvolution improves signal-to-noise ratio on gated stimulated emission depletion microscopy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Castello, Marco; DIBRIS, University of Genoa, Via Opera Pia 13, Genoa 16145; Diaspro, Alberto

2014-12-08

Time-gated detection, namely, only collecting the fluorescence photons after a time-delay from the excitation events, reduces complexity, cost, and illumination intensity of a stimulated emission depletion (STED) microscope. In the gated continuous-wave- (CW-) STED implementation, the spatial resolution improves with increased time-delay, but the signal-to-noise ratio (SNR) reduces. Thus, in sub-optimal conditions, such as a low photon-budget regime, the SNR reduction can cancel-out the expected gain in resolution. Here, we propose a method which does not discard photons, but instead collects all the photons in different time-gates and recombines them through a multi-image deconvolution. Our results, obtained on simulated andmore » experimental data, show that the SNR of the restored image improves relative to the gated image, thereby improving the effective resolution.« less

Low temperature solution processed high-κ ZrO2 gate dielectrics for nanoelectonics

NASA Astrophysics Data System (ADS)

Kumar, Arvind; Mondal, Sandip; Rao, K. S. R. Koteswara

2016-05-01

The high-κ gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, ∼35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 °C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 Å, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (Cox), flat band capacitance (CFB), flat band voltage (VFB), dielectric constant (κ) and oxide trapped charges (Qot) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37 V, 15 and 2 × 10-11 C, respectively. The small flat band voltage 0.37 V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 × 10-9 A/cm2 at 1 V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics.

Ultra-low energy photoreceivers for optical interconnects

NASA Astrophysics Data System (ADS)

Going, Ryan Wayne

Optical interconnects are increasingly important for our communication and data center systems, and are forecasted to be an essential component of future computers. In order to meet these future demands, optical interconnects must be improved to consume less power than they do today. To do this, both more efficient transmitters and more sensitive receivers must be developed. This work addresses the latter, focusing on device level improvements to tightly couple a low capacitance photodiode with the first stage transistor of the receiver as a single phototransistor device. First I motivate the need for a coupled phototransistor using a simple circuit model which shows how receiver sensitivity is determined by photodiode capacitance and the length of wire connecting it to the first transistor in a receiver amplifier. Then I describe our use of the unique rapid melt growth technique, which is used to integrate crystalline germanium on silicon photonics substrates without an epitaxial reactor. The resulting material quality is demonstrated with high quality (0.95 A/W, 40+ GHz) germanium photodiodes on silicon waveguides. Next I describe two germanium phototransistors I have developed. One is a germanium- gated MOSFET on silicon photonics which has up to 18 A/W gate-controlled responsivity at 1550 nm. Simulations show how MOSFET scaling rules can be easily applied to increase both speed and sensitivity. The second is a floating base germanium bipolar phototransistor on silicon photonics with a 15 GHz gain x bandwidth product. The photoBJT also has a clear scaling path, and it is proposed to create a separate gain and absorption region photoBJT to realize the maximum benefit of scaling the BJT without negatively affecting its absorption and photocarrier collection. Following this design a 120 GHz gain x bandwidth photoBJT is simulated. Finally I present a metal-cavity, which can have over 50% quantum efficiency absorption in sub-100 aF germanium photodiodes, which addresses the issue of absorption in photodiodes which have been scaled to near sub-wavelength dimensions.

Pseudocapacitance and excellent cyclability of 2,5-dimethoxy-1,4-benzoquinone on graphene

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boota, Muhammad; Chen, Chi; Bécuwe, Matthieu

2016-01-01

Non-covalent functionalization of 2,5-dimethoxy-1,4-benzoquinone and hydroquinone on reduced graphene oxide sheets led to the formation of a redox-active three-dimensional gel architectureviaa one-step hydrothermal method, where the former exhibited high gravimetric and volumetric capacitance and 99% capacitance retention after 25000 cycles at 50 mV s -1.

A flexible amorphous Bi(5)Nb(3)O(15) film for the gate insulator of the low-voltage operating pentacene thin-film transistor fabricated at room temperature.

PubMed

Cho, Kyung-Hoon; Seong, Tae-Geun; Choi, Joo-Young; Kim, Jin-Seong; Kwon, Jae-Hong; Shin, Sang-Il; Chung, Myung-Ho; Ju, Byeong-Kwon; Nahm, Sahn

2009-10-20

The amorphous Bi(5)Nb(3)O(15) film grown at room temperature under an oxygen-plasma sputtering ambient (BNRT-O(2) film) has a hydrophobic surface with a surface energy of 35.6 mJ m(-2), which is close to that of the orthorhombic pentacene (38 mJ m(-2)), resulting in the formation of a good pentacene layer without the introduction of an additional polymer layer. This film was very flexible, maintaining a high capacitance of 145 nF cm(-2) during and after 10(5) bending cycles with a small curvature radius of 7.5 mm. This film was optically transparent. Furthermore, the flexible, pentacene-based, organic thin-film transistors (OTFTs) fabricated on the poly(ether sulfone) substrate at room temperature using a BNRT-O(2) film as a gate insulator exhibited a promising device performance with a high field effect mobility of 0.5 cm(2) V(-1) s(-1), an on/off current modulation of 10(5), and a small subthreshold slope of 0.2 V decade(-1) under a low operating voltage of -5 V. This device also maintained a high carrier mobility of 0.45 cm(2) V(-1 )s(-1) during the bending with a small curvature radius of 9 mm. Therefore, the BNRT-O(2) film is considered a promising material for the gate insulator of the flexible, pentacene-based OTFT.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Metal-to-insulator transition induced by UV illumination in a single SnO2 nanobelt

NASA Astrophysics Data System (ADS)

Viana, E. R.; Ribeiro, G. M.; de Oliveira, A. G.; González, J. C.

2017-11-01

An individual tin oxide (SnO2) nanobelt was connected in a back-gate field-effect transistor configuration and the conductivity of the nanobelt was measured at different temperatures from 400 K to 4 K, in darkness and under UV illumination. In darkness, the SnO2 nanobelts showed semiconductor behavior for the whole temperature range measured. However, when subjected to UV illumination the photoinduced carriers were high enough to lead to a metal-to-insulator transition (MIT), near room temperature, at T MIT = 240 K. By measuring the current versus gate voltage curves, and considering the electrostatic properties of a non-ideal conductor, for the SnO2 nanobelt on top of a gate-oxide substrate, we estimated the capacitance per unit length, the mobility and the density of carriers. In darkness, the density was estimated to be 5-10 × 1018 cm-3, in agreement with our previously reported result (Phys. Status Solid. RRL 6, 262-4 (2012)). However, under UV illumination the density of carriers was estimated to be 0.2-3.8 × 1019 cm-3 near T MIT, which exceeded the critical Mott density estimated to be 2.8 × 1019 cm-3 above 240 K. These results showed that the electrical properties of the SnO2 nanobelts can be drastically modified and easily tuned from semiconducting to metallic states as a function of temperature and light.

Programmable ion-sensitive transistor interfaces. II. Biomolecular sensing and manipulation.

PubMed

Jayant, Krishna; Auluck, Kshitij; Funke, Mary; Anwar, Sharlin; Phelps, Joshua B; Gordon, Philip H; Rajwade, Shantanu R; Kan, Edwin C

2013-07-01

The chemoreceptive neuron metal-oxide-semiconductor transistor described in the preceding paper is further used to monitor the adsorption and interaction of DNA molecules and subsequently manipulate the adsorbed biomolecules with injected static charge. Adsorption of DNA molecules onto poly-L-lysine-coated sensing gates (SGs) modulates the floating gate (FG) potential ψ(O), which is reflected as a threshold voltage shift measured from the control gate (CG) V(th_CG). The asymmetric capacitive coupling between the CG and SG to the FG results in V(th_CG) amplification. The electric field in the SG oxide E(SG_ox) is fundamentally different when we drive the current readout with V(CG) and V(ref) (i.e., the potential applied to the CG and reference electrode, respectively). The V(CG)-driven readout induces a larger E(SG_ox), leading to a larger V(th_CG) shift when DNA is present. Simulation studies indicate that the counterion screening within the DNA membrane is responsible for this effect. The DNA manipulation mechanism is enabled by tunneling electrons (program) or holes (erase) onto FGs to produce repulsive or attractive forces. Programming leads to repulsion and eventual desorption of DNA, while erasing reestablishes adsorption. We further show that injected holes or electrons prior to DNA addition either aids or disrupts the immobilization process, which can be used for addressable sensor interfaces. To further substantiate DNA manipulation, we used impedance spectroscopy with a split ac-dc technique to reveal the net interface impedance before and after charge injection.

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-05-01

In situ-formed SiO2 was introduced into HfO2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO2/SiO2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10-3 A/cm2 at gate bias of Vfb + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO2/SiO2/Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition.

PubMed

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-12-01

In situ-formed SiO 2 was introduced into HfO 2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO 2 /SiO 2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO 2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO 2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10 -3 A/cm 2 at gate bias of V fb  + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO 2 /SiO 2 /Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO 2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient

NASA Astrophysics Data System (ADS)

Xue, Peng; Fu, Guicui

2017-03-01

The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT's dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600 V/150 A CSTBT and a Infineon 600 V/200 A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT's clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT's dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT's experimental results implies that the CSTBT's abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT's abnormal dynamic avalanche mechanism. Moreover, the CSTBT's negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT's dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

PubMed Central

Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

2016-01-01

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

Synthesis of bacteria promoted reduced graphene oxide-nickel sulfide networks for advanced supercapacitors.

PubMed

Zhang, Haiming; Yu, Xinzhi; Guo, Di; Qu, Baihua; Zhang, Ming; Li, Qiuhong; Wang, Taihong

2013-08-14

Supercapacitors with potential high power are useful and have attracted much attention recently. Graphene-based composites have been demonstrated to be promising electrode materials for supercapacitors with enhanced properties. To improve the performance of graphene-based composites further and realize their synthesis with large scale, we report a green approach to synthesize bacteria-reduced graphene oxide-nickel sulfide (BGNS) networks. By using Bacillus subtilis as spacers, we deposited reduced graphene oxide/Ni3S2 nanoparticle composites with submillimeter pores directly onto substrate by a binder-free electrostatic spray approach to form BGNS networks. Their electrochemical capacitor performance was evaluated. Compared with stacked reduced graphene oxide-nickel sulfide (GNS) prepared without the aid of bacteria, BGNS with unique nm-μm structure exhibited a higher specific capacitance of about 1424 F g(-1) at a current density of 0.75 A g(-1). About 67.5% of the capacitance was retained as the current density increased from 0.75 to 15 A g(-1). At a current density of 75 A g(-1), a specific capacitance of 406 F g(-1) could still remain. The results indicate that the reduced graphene oxide-nickel sulfide network promoted by bacteria is a promising electrode material for supercapacitors.

Electrosorption capacitance of nanostructured carbon-based materials.

PubMed

Hou, Chia-Hung; Liang, Chengdu; Yiacoumi, Sotira; Dai, Sheng; Tsouris, Costas

2006-10-01

The fundamental mechanism of electrosorption of ions developing a double layer inside nanopores was studied via a combination of experimental and theoretical studies. A novel graphitized-carbon monolithic material has proven to be a good electrical double-layer capacitor that can be applied in the separation of ions from aqueous solutions. An extended electrical double-layer model indicated that the pore size distribution plays a key role in determining the double-layer capacitance in an electrosorption process. Because of the occurrence of double-layer overlapping in narrow pores, mesopores and micropores make significantly different contributions to the double-layer capacitance. Mesopores show good electrochemical accessibility. Micropores present a slow mass transfer of ions and a considerable loss of double-layer capacitance, associated with a shallow potential distribution inside pores. The formation of the diffuse layer inside the micropores determines the magnitude of the double-layer capacitance at low electrolyte concentrations and at conditions close to the point of zero charge of the material. The effect of the double-layer overlapping on the electrosorption capacitance can be reduced by increasing the pore size, electrolyte concentration, and applied potential. The results are relevant to water deionization.

Effect of noncovalent basal plane functionalization on the quantum capacitance in graphene.

PubMed

Ebrish, Mona A; Olson, Eric J; Koester, Steven J

2014-07-09

The concentration-dependent density of states in graphene allows the capacitance in metal-oxide-graphene structures to be tunable with the carrier concentration. This feature allows graphene to act as a variable capacitor (varactor) that can be utilized for wireless sensing applications. Surface functionalization can be used to make graphene sensitive to a particular species. In this manuscript, the effect on the quantum capacitance of noncovalent basal plane functionalization using 1-pyrenebutanoic acid succimidyl ester and glucose oxidase is reported. It is found that functionalized samples tested in air have (1) a Dirac point similar to vacuum conditions, (2) increased maximum capacitance compared to vacuum but similar to air, (3) and quantum capacitance "tuning" that is greater than that in vacuum and ambient atmosphere. These trends are attributed to reduced surface doping and random potential fluctuations as a result of the surface functionalization due to the displacement of H2O on the graphene surface and intercalation of a stable H2O layer beneath graphene that increases the overall device capacitance. The results are important for future application of graphene as a platform for wireless chemical and biological sensors.

Temperature dependent quasi-static capacitance-voltage characterization of SiO2/β-Ga2O3 interface on different crystal orientations

NASA Astrophysics Data System (ADS)

Zeng, Ke; Singisetti, Uttam

2017-09-01

The interface trap density (Dit) of the SiO2/β-Ga2O3 interface in ( 2 ¯ 01), (010), and (001) orientations is obtained by the Hi-Lo method with the low frequency capacitance measured using the Quasi-Static Capacitance-Voltage (QSCV) technique. QSCV measurements are carried out at higher temperatures to increase the measured energy range of Dit in the bandgap. At room temperature, higher Dit is observed near the band edge for all three orientations. The measurement at higher temperatures led to an annealing effect that reduced the Dit value for all samples. Comparison with the conductance method and frequency dispersion of the capacitance suggests that the traps at the band edge are slow traps which respond to low frequency signals.

High energy density asymmetric supercapacitors with a nickel oxide nanoflake cathode and a 3D reduced graphene oxide anode

NASA Astrophysics Data System (ADS)

Luan, Feng; Wang, Gongming; Ling, Yichuan; Lu, Xihong; Wang, Hanyu; Tong, Yexiang; Liu, Xiao-Xia; Li, Yat

2013-08-01

Here we demonstrate a high energy density asymmetric supercapacitor with nickel oxide nanoflake arrays as the cathode and reduced graphene oxide as the anode. Nickel oxide nanoflake arrays were synthesized on a flexible carbon cloth substrate using a seed-mediated hydrothermal method. The reduced graphene oxide sheets were deposited on three-dimensional (3D) nickel foam by hydrothermal treatment of nickel foam in graphene oxide solution. The nanostructured electrodes provide a large effective surface area. The asymmetric supercapacitor device operates with a voltage of 1.7 V and achieved a remarkable areal capacitance of 248 mF cm-2 (specific capacitance of 50 F g-1) at a charge/discharge current density of 1 mA cm-2 and a maximum energy density of 39.9 W h kg-1 (based on the total mass of active materials of 5.0 mg). Furthermore, the device showed an excellent charge/discharge cycling performance in 1.0 M KOH electrolyte at a current density of 5 mA cm-2, with a capacitance retention of 95% after 3000 cycles.

High energy density asymmetric supercapacitors with a nickel oxide nanoflake cathode and a 3D reduced graphene oxide anode.

PubMed

Luan, Feng; Wang, Gongming; Ling, Yichuan; Lu, Xihong; Wang, Hanyu; Tong, Yexiang; Liu, Xiao-Xia; Li, Yat

2013-09-07

Here we demonstrate a high energy density asymmetric supercapacitor with nickel oxide nanoflake arrays as the cathode and reduced graphene oxide as the anode. Nickel oxide nanoflake arrays were synthesized on a flexible carbon cloth substrate using a seed-mediated hydrothermal method. The reduced graphene oxide sheets were deposited on three-dimensional (3D) nickel foam by hydrothermal treatment of nickel foam in graphene oxide solution. The nanostructured electrodes provide a large effective surface area. The asymmetric supercapacitor device operates with a voltage of 1.7 V and achieved a remarkable areal capacitance of 248 mF cm(-2) (specific capacitance of 50 F g(-1)) at a charge/discharge current density of 1 mA cm(-2) and a maximum energy density of 39.9 W h kg(-1) (based on the total mass of active materials of 5.0 mg). Furthermore, the device showed an excellent charge/discharge cycling performance in 1.0 M KOH electrolyte at a current density of 5 mA cm(-2), with a capacitance retention of 95% after 3000 cycles.

Tunable Microwave Filter Design Using Thin-Film Ferroelectric Varactors

NASA Astrophysics Data System (ADS)

Haridasan, Vrinda

Military, space, and consumer-based communication markets alike are moving towards multi-functional, multi-mode, and portable transceiver units. Ferroelectric-based tunable filter designs in RF front-ends are a relatively new area of research that provides a potential solution to support wideband and compact transceiver units. This work presents design methodologies developed to optimize a tunable filter design for system-level integration, and to improve the performance of a ferroelectric-based tunable bandpass filter. An investigative approach to find the origins of high insertion loss exhibited by these filters is also undertaken. A system-aware design guideline and figure of merit for ferroelectric-based tunable band- pass filters is developed. The guideline does not constrain the filter bandwidth as long as it falls within the range of the analog bandwidth of a system's analog to digital converter. A figure of merit (FOM) that optimizes filter design for a specific application is presented. It considers the worst-case filter performance parameters and a tuning sensitivity term that captures the relation between frequency tunability and the underlying material tunability. A non-tunable parasitic fringe capacitance associated with ferroelectric-based planar capacitors is confirmed by simulated and measured results. The fringe capacitance is an appreciable proportion of the tunable capacitance at frequencies of X-band and higher. As ferroelectric-based tunable capac- itors form tunable resonators in the filter design, a proportionally higher fringe capacitance reduces the capacitance tunability which in turn reduces the frequency tunability of the filter. Methods to reduce the fringe capacitance can thus increase frequency tunability or indirectly reduce the filter insertion-loss by trading off the increased tunability achieved to lower loss. A new two-pole tunable filter topology with high frequency tunability (> 30%), steep filter skirts, wide stopband rejection, and constant bandwidth is designed, simulated, fabricated and measured. The filters are fabricated using barium strontium titanate (BST) varactors. Electromagnetic simulations and measured results of the tunable two-pole ferroelectric filter are analyzed to explore the origins of high insertion loss in ferroelectric filters. The results indicate that the high-permittivity of the BST (a ferroelectric) not only makes the filters tunable and compact, but also increases the conductive loss of the ferroelectric-based tunable resonators which translates into high insertion loss in ferroelectric filters.

Free-breathing 3D Cardiac MRI Using Iterative Image-Based Respiratory Motion Correction

PubMed Central

Moghari, Mehdi H.; Roujol, Sébastien; Chan, Raymond H.; Hong, Susie N.; Bello, Natalie; Henningsson, Markus; Ngo, Long H.; Goddu, Beth; Goepfert, Lois; Kissinger, Kraig V.; Manning, Warren J.; Nezafat, Reza

2012-01-01

Respiratory motion compensation using diaphragmatic navigator (NAV) gating with a 5 mm gating window is conventionally used for free-breathing cardiac MRI. Due to the narrow gating window, scan efficiency is low resulting in long scan times, especially for patients with irregular breathing patterns. In this work, a new retrospective motion compensation algorithm is presented to reduce the scan time for free-breathing cardiac MRI that increasing the gating window to 15 mm without compromising image quality. The proposed algorithm iteratively corrects for respiratory-induced cardiac motion by optimizing the sharpness of the heart. To evaluate this technique, two coronary MRI datasets with 1.3 mm3 resolution were acquired from 11 healthy subjects (7 females, 25±9 years); one using a NAV with a 5 mm gating window acquired in 12.0±2.0 minutes and one with a 15 mm gating window acquired in 7.1±1.0 minutes. The images acquired with a 15 mm gating window were corrected using the proposed algorithm and compared to the uncorrected images acquired with the 5 mm and 15 mm gating windows. The image quality score, sharpness, and length of the three major coronary arteries were equivalent between the corrected images and the images acquired with a 5 mm gating window (p-value>0.05), while the scan time was reduced by a factor of 1.7. PMID:23132549

Facile Co-Electrodeposition Method for High-Performance Supercapacitor Based on Reduced Graphene Oxide/Polypyrrole Composite Film.

PubMed

Chen, Junchen; Wang, Yaming; Cao, Jianyun; Liu, Yan; Zhou, Yu; Ouyang, Jia-Hu; Jia, Dechang

2017-06-14

A facile co-electrodeposition method has been developed to fabricate reduced graphene oxide/polypyrrole (rGO/PPy) composite films, with sodium dodecyl benzene sulfonate as both a surfactant and supporting electrolyte in the precursor solution. The introduction of rGO into the PPy films forms porous structure and enhances the conductivity across the film, leading to superior electrochemical performance. By controlling the deposition time and rGO concentration, the highest area capacitance can reach 411 mF/cm 2 (0.2 mA/cm 2 ) for rGO/PPy films, whereas optimized specific capacitance is as high as 361 F/g (0.2 mA/cm 2 ). All of the composite films exhibit excellent rate capability (at least 175 F/g at the current density of 12 mA/cm 2 ) compared with pure PPy film (only 12 F/g at the current density of 12 mA/cm 2 ). The rGO/PPy composite exhibits excellent cycling stability that maintains 104% of its initial capacitance after cycling for 2000 cycles and 80% for 5000 cycles. The two-electrode solid-state supercapacitor (SC) based on rGO/PPy composite electrodes demonstrates good rate performance, excellent cycling stability, as well as a high area capacitance of 222 mF/cm 2 . The solid-state planar SC based on the rGO/PPy composite exhibits an area capacitance of 9.4 mF/cm 2 , demonstrating great potential for fabrication of microsupercapacitors.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

NASA Astrophysics Data System (ADS)

Chappanda, K. N.; Ilyas, S.; Younis, M. I.

2018-05-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

A Self-Adaptive Capacitive Compensation Technique for Body Channel Communication.

PubMed

Mao, Jingna; Yang, Huazhong; Lian, Yong; Zhao, Bo

2017-10-01

In wireless body area network, capacitive-coupling body channel communication (CC-BCC) has the potential to attain better energy efficiency over conventional wireless communication schemes. The CC-BCC scheme utilizes the human body as the forward signal transmission medium, reducing the path loss in wireless body-centric communications. However, the backward path is formed by the coupling capacitance between the ground electrodes (GEs) of transmitter (Tx) and receiver (Rx), which increases the path loss and results in a body posture dependent backward impedance. Conventional methods use a fixed inductor to resonate with the backward capacitor to compensate the path loss, while it's not effective in compensating the variable backward impedance induced by the body movements. In this paper, we propose a self-adaptive capacitive compensation (SACC) technique to address such a problem. A backward distance detector is introduced to estimate the distance between two GEs of Tx and Rx, and a backward capacitance model is built to calculate the backward capacitance. The calculated backward capacitance at varying body posture is compensated by a digitally controlled tunable inductor (DCTI). The proposed SACC technique is validated by a prototype CC-BCC system, and measurements are taken on human subjects. The measurement results show that 9dB-16 dB channel enhancement can be achieved at a backward path distance of 1 cm-10 cm.

Measuring Input Thresholds on an Existing Board

NASA Technical Reports Server (NTRS)

Kuperman, Igor; Gutrich, Daniel G.; Berkun, Andrew C.

2011-01-01

A critical PECL (positive emitter-coupled logic) interface to Xilinx interface needed to be changed on an existing flight board. The new Xilinx input interface used a CMOS (complementary metal-oxide semiconductor) type of input, and the driver could meet its thresholds typically, but not in worst-case, according to the data sheet. The previous interface had been based on comparison with an external reference, but the CMOS input is based on comparison with an internal divider from the power supply. A way to measure what the exact input threshold was for this device for 64 inputs on a flight board was needed. The measurement technique allowed an accurate measurement of the voltage required to switch a Xilinx input from high to low for each of the 64 lines, while only probing two of them. Directly driving an external voltage was considered too risky, and tests done on any other unit could not be used to qualify the flight board. The two lines directly probed gave an absolute voltage threshold calibration, while data collected on the remaining 62 lines without probing gave relative measurements that could be used to identify any outliers. The PECL interface was forced to a long-period square wave by driving a saturated square wave into the ADC (analog to digital converter). The active pull-down circuit was turned off, causing each line to rise rapidly and fall slowly according to the input s weak pull-down circuitry. The fall time shows up as a change in the pulse width of the signal ready by the Xilinx. This change in pulse width is a function of capacitance, pulldown current, and input threshold. Capacitance was known from the different trace lengths, plus a gate input capacitance, which is the same for all inputs. The pull-down current is the same for all inputs including the two that are probed directly. The data was combined, and the Excel solver tool was used to find input thresholds for the 62 lines. This was repeated over different supply voltages and temperatures to show that the interface had voltage margin under all worst case conditions. Gate input thresholds are normally measured at the manufacturer when the device is on a chip tester. A key function of this machine was duplicated on an existing flight board with no modifications to the nets to be tested, with the exception of changes in the FPGA program.

Static charge outside chamber induces dielectric breakdown of solid-state nanopore membranes

NASA Astrophysics Data System (ADS)

Matsui, Kazuma; Goto, Yusuke; Yanagi, Itaru; Yanagawa, Yoshimitsu; Ishige, Yu; Takeda, Ken-ichi

2018-04-01

Reducing device capacitance is effective for decreasing current noise observed in a solid-state nanopore-based DNA sequencer. On the other hand, we have recently found that voltage stress causes pinhole-like defects in such low-capacitance devices. The origin of voltage stress, however, has not been determined. In this research, we identified that a dominant origin is static charge on the outer surface of a flow cell. Even though the outer surface was not in direct contact with electrolytes in the flow cell, the charge induces high voltage stress on a membrane according to the capacitance coupling ratio of the flow cell to the membrane.