2.4 GHz CMOS power amplifier with mode-locking structure to enhance gain.

PubMed

Lee, Changhyun; Park, Changkun

2014-01-01

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm(2).

2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

PubMed Central

2014-01-01

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2. PMID:25045755

A UHF RFID system with on-chip-antenna tag for short range communication

NASA Astrophysics Data System (ADS)

Qi, Peng; Chun, Zhang; Xijin, Zhao; Zhihua, Wang

2015-05-01

A UHF RF identification system based on the 0.18 μm CMOS process has been developed for short range and harsh size requirement applications, which is composed of a fully integrated tag and a special reader. The whole tag chip with the antenna takes up an area of 0.36 mm2, which is smaller than other reported tags with an on-chip antenna (OCA) using the standard CMOS process. A self-defined protocol is proposed to reduce the power consumption, and minimize the size of the tag. The specialized SOC reader system consists of the RF transceiver, digital baseband, MCU and host interface. Its power consumption is about 500 mW. Measurement results show that the system's reading range is 2 mm with 20 dBm reader output power. With an inductive antenna printed on a paper substrate around the OCA tag, the reading range can be extended from several centimeters to meters, depending on the shape and size of the inductive antenna.

SiGe BiCMOS manufacturing platform for mmWave applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

2010-10-01

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

Integrated Multiple Device CMOS-MEMS IMU Systems and RF MEMS Applications

DTIC Science & Technology

2002-12-17

microstructures [7]~[9]. The success of the surface-micromachined electrostatic micromotor in the late 80’s [10] stimulated the industry and government...processed electrostatic synchronous micromotors ,” Sensors Actuators, vol. 20, pp. 48-56, 1989. [11] “ADXL05-monolithic accelerometer with signal

Moving Beyond 3D Hetero-Integration and Towards Monolithic Integration of Phase-Change RF Switches with SiGe BiCMOS

DTIC Science & Technology

2016-03-31

Corporation, Linthicum, Maryland *Corresponding author: Pavel.Borodulin@ngc.com Abstract: A chip -scale, highly-reconfigurable transmitter and...the technology has been used in a chip -scale, reconfigurable receiver demonstration and ongoing efforts to increase the level of performance and...circuit (RF-FPGA). It consists of a heterogeneous assembly of a SiGe BiCMOS chip with multiple 3D-integrated, low-loss, phase-change switch chiplets

An Autonomous Wireless Sensor Node With Asynchronous ECG Monitoring in 0.18 μ m CMOS.

PubMed

Mansano, Andre L; Li, Yongjia; Bagga, Sumit; Serdijn, Wouter A

2016-06-01

The design of a 13.56 MHz/402 MHz autonomous wireless sensor node with asynchronous ECG monitoring for near field communication is presented. The sensor node consists of an RF energy harvester (RFEH), a power management unit, an ECG readout, a data encoder and an RF backscattering transmitter. The energy harvester supplies the system with 1.25 V and offers a power conversion efficiency of 19% from a -13 dBm RF source at 13.56 MHz. The power management unit regulates the output voltage of the RFEH to supply the ECG readout with VECG = 0.95 V and the data encoder with VDE = 0.65 V . The ECG readout comprises an analog front-end (low noise amplifier and programmable voltage to current converter) and an asynchronous level crossing ADC with 8 bits resolution. The ADC output is encoded by a pulse generator that drives a backscattering transmitter at 402 MHz. The total power consumption of the sensor node circuitry is 9.7 μ W for a data rate of 90 kb/s and a heart rate of 70 bpm. The chip has been designed in a 0.18 μm CMOS process and shows superior RF input power sensitivity and lower power consumption when compared to previous works.

Real-time digital signal processing for live electro-optic imaging.

PubMed

Sasagawa, Kiyotaka; Kanno, Atsushi; Tsuchiya, Masahiro

2009-08-31

We present an imaging system that enables real-time magnitude and phase detection of modulated signals and its application to a Live Electro-optic Imaging (LEI) system, which realizes instantaneous visualization of RF electric fields. The real-time acquisition of magnitude and phase images of a modulated optical signal at 5 kHz is demonstrated by imaging with a Si-based high-speed CMOS image sensor and real-time signal processing with a digital signal processor. In the LEI system, RF electric fields are probed with light via an electro-optic crystal plate and downconverted to an intermediate frequency by parallel optical heterodyning, which can be detected with the image sensor. The artifacts caused by the optics and the image sensor characteristics are corrected by image processing. As examples, we demonstrate real-time visualization of electric fields from RF circuits.

Systematic analysis of CMOS-micromachined inductors with application to mixer matching circuits

NASA Astrophysics Data System (ADS)

Wu, Jerry Chun-Li

The growing demand for consumer voice and data communication systems and military communication applications has created a need for low-power, low-cost, high-performance radio-frequency (RF) front-end. To achieve this goal, bringing passive components, especially inductors, to silicon is imperative. On-chip passive components such as inductors and capacitors generally enhance the reliability and efficiency of silicon-integrated RF cells. They can provide circuit solutions with superior performance and contribute to a higher level of integration. With passive components on chip, there is a great opportunity to have transformers, filters, and matching networks on chip. However, inductors on silicon have a low quality factor (Q) due to both substrate and metal loss. This dissertation demonstrates the systematic analysis of inductors fabricated using standard complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) system technologies. We report system-on-chip inductor modeling, simulation, and measurements of effective inductance and quality factors. In this analysis methodology, a number of systematic simulations are performed on regular and micromachined inductors with different parameters such as spiral topology, number of turns, outer diameter, thickness, and percentage of substrate removed by using micromachining technologies. Three different novel support structures of the micromachined spiral inductor are proposed, analyzed, and implemented for larger size suspended inductors. The sensitivity of the structure support and different degree of substrate etching by post-processing is illustrated. The results provide guidelines for the selection of inductor parameters, post-processing methodologies, and its spiral supports to meet the RF design specifications and the stability requirements for mobile communication. The proposed CMOS-micromachined inductor is used in a low cost-effective double-balanced Gilbert mixer with on-chip matching network. The integrated mixer inductor was implemented and tested to prove the concept.

Ultralow drive voltage silicon traveling-wave modulator.

PubMed

Baehr-Jones, Tom; Ding, Ran; Liu, Yang; Ayazi, Ali; Pinguet, Thierry; Harris, Nicholas C; Streshinsky, Matt; Lee, Poshen; Zhang, Yi; Lim, Andy Eu-Jin; Liow, Tsung-Yang; Teo, Selin Hwee-Gee; Lo, Guo-Qiang; Hochberg, Michael

2012-05-21

There has been great interest in the silicon platform as a material system for integrated photonics. A key challenge is the development of a low-power, low drive voltage, broadband modulator. Drive voltages at or below 1 Vpp are desirable for compatibility with CMOS processes. Here we demonstrate a CMOS-compatible broadband traveling-wave modulator based on a reverse-biased pn junction. We demonstrate operation with a drive voltage of 0.63 Vpp at 20 Gb/s, a significant improvement in the state of the art, with an RF energy consumption of only 200 fJ/bit.

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

DTIC Science & Technology

2015-12-24

Ripple-Carry RCA Ripple-Carry Adder RF Radio Frequency RMS Root-Mean-Square SEU Single Event Upset SIPI Signal and Image Processing Institute SNR...correctness, where 0.5 < p < 1, and a probability (1−p) of error. Errors could be caused by noise, radio frequency (RF) interference, crosstalk...utilized in the Apollo Guidance Computer is the three input NOR Gate. . . At the time that the decision was made to use in- 11 tegrated circuits, the

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm Using Probabilistic Boolean Logic Applied to CMOS Components

DTIC Science & Technology

2015-12-24

Ripple-Carry RCA Ripple-Carry Adder RF Radio Frequency RMS Root-Mean-Square SEU Single Event Upset SIPI Signal and Image Processing Institute SNR...correctness, where 0.5 < p < 1, and a probability (1−p) of error. Errors could be caused by noise, radio frequency (RF) interference, crosstalk...utilized in the Apollo Guidance Computer is the three input NOR Gate. . . At the time that the decision was made to use in- 11 tegrated circuits, the

A novel compact model for on-chip stacked transformers in RF-CMOS technology

NASA Astrophysics Data System (ADS)

Jun, Liu; Jincai, Wen; Qian, Zhao; Lingling, Sun

2013-08-01

A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S -parameters on the extracted parameters for a 1 : 1 stacked transformer manufactured in a commercial RF-CMOS technology.

An ultra-low-power RF transceiver for WBANs in medical applications

NASA Astrophysics Data System (ADS)

Qi, Zhang; Xiaofei, Kuang; Nanjian, Wu

2011-06-01

A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks (WBANs) in medical applications is presented. The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs. The transceiver consists of a main receiver (RX) with an ultra-low-power free-running ring oscillator and a high speed main transmitter (TX) with fast lock-in PLL. A passive wake-up receiver (WuRx) for wake-up function with a high power conversion efficiency (PCE) CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power. The chip is implemented in a 0.18 μm CMOS process. Its core area is 1.6 mm2. The main RX achieves a sensitivity of -55 dBm at a 100 kbps OOK data rate while consuming just 210 μA current from the 1 V power supply. The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is -15 dBm and the PCE is more than 25%.

Note: Characterization and test of a high input impedance RF amplifier for series nanowire detector

NASA Astrophysics Data System (ADS)

Wan, Chao; Pei, Yufeng; Jiang, Zhou; Kang, Lin; Wu, Peiheng

2016-09-01

We designed a high input impedance RF amplifier based on Tower Jazz's 0.18 μm SiGe BiCMOS process for series nanowire detector. The characterization of its gain and input impedance with a vector network analyzer is described in detail for its specificity. The actual 15 dB gain should be the measured value subtracts 6 dB, which is easy to be ignored. Its input impedance can be equivalent to 6.7 kΩ ∥ 3.4 pF though fitting the measurement, whose accuracy is verified. The process of measurement provides a good reference to characterize the similar special amplifier with unmatched impedance.

On-chip programmable ultra-wideband microwave photonic phase shifter and true time delay unit.

PubMed

Burla, Maurizio; Cortés, Luis Romero; Li, Ming; Wang, Xu; Chrostowski, Lukas; Azaña, José

2014-11-01

We proposed and experimentally demonstrated an ultra-broadband on-chip microwave photonic processor that can operate both as RF phase shifter (PS) and true-time-delay (TTD) line, with continuous tuning. The processor is based on a silicon dual-phase-shifted waveguide Bragg grating (DPS-WBG) realized with a CMOS compatible process. We experimentally demonstrated the generation of delay up to 19.4 ps over 10 GHz instantaneous bandwidth and a phase shift of approximately 160° over the bandwidth 22-29 GHz. The available RF measurement setup ultimately limits the phase shifting demonstration as the device is capable of providing up to 300° phase shift for RF frequencies over a record bandwidth approaching 1 THz.

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution

NASA Astrophysics Data System (ADS)

Utagawa, Akira; Asai, Tetsuya; Hirose, Tetsuya; Amemiya, Yoshihito

We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1], [2]. We regard neural oscillators as independent clock sources on LSIs; i. e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (<1GHz) by modifying the original neuron model to a new model that is suitable for CMOS implementation with 0.25-μm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

NASA Astrophysics Data System (ADS)

Oukacha, Hassan

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of circulator shows how crucial this device is to many industries and the need for smaller, cost effective RF components.

Interferometry-based free space communication and information processing

NASA Astrophysics Data System (ADS)

Arain, Muzammil Arshad

This dissertation studies, analyzes, and experimentally demonstrates the innovative use of interference phenomenon in the field of opto-electronic information processing and optical communications. A number of optical systems using interferometric techniques both in the optical and the electronic domains has been demonstrated in the filed of signal transmission and processing, optical metrology, defense, and physical sensors. Specifically it has been shown that the interference of waves in the form of holography can be exploited to realize a novel optical scanner called Code Multiplexed Optical Scanner (C-MOS). The C-MOS features large aperture, wide scan angles, 3-D beam control, no moving parts, and high beam scanning resolution. A C-MOS based free space optical transceiver for bi-directional communication has also been experimentally demonstrated. For high speed, large bandwidth, and high frequency operation, an optically implemented reconfigurable RF transversal filter design is presented that implements wide range of filtering algorithms. A number of techniques using heterodyne interferometry via acousto-optic device for optical path length measurements have been described. Finally, a whole new class of interferometric sensors for optical metrology and sensing applications is presented. A non-traditional interferometric output signal processing scheme has been developed. Applications include, for example, temperature sensors for harsh environments for a wide temperature range from room temperature to 1000°C.

FDSOI 28nm performances study for RF energy scavenging

NASA Astrophysics Data System (ADS)

Rochefeuille, E.; Alicalapa, F.; Douyère, A.; Vuong, T. P.

2018-03-01

This paper presents a study on an integrated technology: Fully-Depleted-Silicon-On-Insulator (FDSOI) at a 28nm node. FDSOI results are compared to another technology: Complementary-Metal-Oxide-Semiconductor (CMOS) 350nm. The aim of this work was to demonstrate the advantages of using FDSOI technology in RF energy scavenging applications. Characteristics of transistors are pointed out and results showed an improved 22%-output voltage gain for a series rectifier and a 13%-output voltage gain for a Dickson charge pump in FDSOI technology compared to CMOS, for an input voltage and power of 0.5 V and 0 dBm respectively. Those results allowed to prove that FDSOI 28nm is a better technology choice for energy scavenging and low-power applications.

Design and implementation of a low-power SOI CMOS receiver

NASA Astrophysics Data System (ADS)

Zencir, Ertan

There is a strong demand for wireless communications in civilian and military applications, and space explorations. This work attempts to implement a low-power, high-performance fully-integrated receiver for deep space communications using Silicon on Insulator (SOI) CMOS technology. Design and implementation of a UHF low-IF receiver front-end in a 0.35-mum SOI CMOS technology are presented. Problems and challenges in implementing a highly integrated receiver at UHF are identified. Low-IF architecture, suitable for low-power design, has been adopted to mitigate the noise at the baseband. Design issues of the receiver building blocks including single-ended and differential LNA's, passive and active mixers, and variable gain/bandwidth complex filters are discussed. The receiver is designed to have a variable conversion gain of more than 100 dB with a 70 dB image rejection and a power dissipation of 45 mW from a 2.5-V supply. Design and measured performance of the LNA's, and the mixer are presented. Measurement results of RF front-end blocks including a single-ended LNA, a differential LNA, and a double-balanced mixer demonstrate the low power realizability of RF front-end circuits in SOI CMOS technology. We also report on the design and simulation of the image-rejecting complex IF filter and the full receiver circuit. Gain, noise, and linearity performance of the receiver components prove the viability of fully integrated low-power receivers in SOI CMOS technology.

Single-chip fully integrated direct-modulation CMOS RF transmitters for short-range wireless applications.

PubMed

El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed; Deen, M Jamal

2013-08-02

Ultra-low power radio frequency (RF) transceivers used in short-range application such as wireless sensor networks (WSNs) require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs) in addition to a 2.0 GHz phase-locked loop (PLL) based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of -122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of -120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

PubMed Central

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

2014-01-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

PubMed

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

Review of mixer design for low voltage - low power applications

NASA Astrophysics Data System (ADS)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

Architecture for a 1-GHz Digital RADAR

NASA Technical Reports Server (NTRS)

Mallik, Udayan

2011-01-01

An architecture for a Direct RF-digitization Type Digital Mode RADAR was developed at GSFC in 2008. Two variations of a basic architecture were developed for use on RADAR imaging missions using aircraft and spacecraft. Both systems can operate with a pulse repetition rate up to 10 MHz with 8 received RF samples per pulse repetition interval, or at up to 19 kHz with 4K received RF samples per pulse repetition interval. The first design describes a computer architecture for a Continuous Mode RADAR transceiver with a real-time signal processing and display architecture. The architecture can operate at a high pulse repetition rate without interruption for an infinite amount of time. The second design describes a smaller and less costly burst mode RADAR that can transceive high pulse repetition rate RF signals without interruption for up to 37 seconds. The burst-mode RADAR was designed to operate on an off-line signal processing paradigm. The temporal distribution of RF samples acquired and reported to the RADAR processor remains uniform and free of distortion in both proposed architectures. The majority of the RADAR's electronics is implemented in digital CMOS (complementary metal oxide semiconductor), and analog circuits are restricted to signal amplification operations and analog to digital conversion. An implementation of the proposed systems will create a 1-GHz, Direct RF-digitization Type, L-Band Digital RADAR--the highest band achievable for Nyquist Rate, Direct RF-digitization Systems that do not implement an electronic IF downsample stage (after the receiver signal amplification stage), using commercially available off-the-shelf integrated circuits.

On the Application of Inverse-Mode SiGe HBTs in RF Receivers for the Mitigation of Single-Event Transients

NASA Astrophysics Data System (ADS)

Song, Ickhyun; Cho, Moon-Kyu; Oakley, Michael A.; Ildefonso, Adrian; Ju, Inchan; Buchner, Stephen P.; McMorrow, Dale; Paki, Pauline; Cressler, John. D.

2017-05-01

Best practice in mitigation strategies for single-event transients (SETs) in radio-frequency (RF) receiver modules is investigated using a variety of integrated receivers utilizing inverse-mode silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). The receivers were designed and implemented in a 130-nm SiGe BiCMOS technology platform. In general, RF switches, low-noise amplifiers (LNAs), and downconversion mixers utilizing inverse-mode SiGe HBTs exhibit less susceptibility to SETs than conventional RF designs, in terms of transient peaks and duration, at the cost of RF performance. Under normal RF operation, the SET-hardened switch is mainly effective in peak reduction, while the LNA and the mixer exhibit reductions in transient peaks as well as transient duration.

High Efficiency mm-Wave Transmitter Array

DTIC Science & Technology

2016-09-01

SECURITY CLASSIFICATION OF: High efficiency, high power transmitters integrated in silicon at 45, 94 and 138 GHz were developed. Our approach...employs CMOS-SOI and SiGe HBT unit amplifiers, power -combined in free-space using antenna arrays to attain high power levels. In the baseline approach...the-art were made. At 45GHz, a single CMOS chip produced an RF power of 630mW, which yielded an EIRP of 1. REPORT DATE (DD-MM-YYYY) 4. TITLE AND

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC.

PubMed

Xinkai Chen; Xiaoyu Zhang; Linwei Zhang; Xiaowen Li; Nan Qi; Hanjun Jiang; Zhihua Wang

2009-02-01

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

The rectenna design on contact lens for wireless powering of the active intraocular pressure monitoring system.

PubMed

Cheng, H W; Jeng, B M; Chen, C Y; Huang, H Y; Chiou, J C; Luo, C H

2013-01-01

This paper proposed a wireless power harvesting system with micro-electro-mechanical-systems (MEMS) fabrication for noninvasive intraocular pressure (IOP) measurement on soft contact lens substructure. The power harvesting IC consists of a loop antenna, an impedance matching network and a rectifier. The proposed IC has been designed and fabricated by CMOS 0.18 um process that operates at the ISM band of 5.8 GHz. The antenna and the power harvesting IC would be bonded together by using flip chip bonding technologies without extra wire interference. The circuit utilized an impedance transformation circuit to boost the input RF signal that improves the circuit performance. The proposed design achieves an RF-to-DC conversion efficiency of 35% at 5.8 GHz.

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

2017-05-01

Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

Development and production integration of a planarized AlCu interconnect process for submicron CMOS

NASA Astrophysics Data System (ADS)

Brown, Kevin C.; Hill, Rodney; Reddy, Krishna; Gadepally, Kamesh

1995-09-01

A planarized aluminum alloy interconnect has been developed as an alternative to tungsten plugs for a 0.65 (mu) CMOS technology. Contact resistance can increase with either an inadequate RF sputter clean or titanium that is too thin to reduce the native oxide. Diffusion barrier results show that a minimum amount of titanium nitride, whether deposited conventionally or with collimation, is necessary for low junction leakage and good sort yield. Stacked contacts and vias are supported while via resistance and defect density are improved. Electrical bridging due to silicon residues from AlSiCu can be minimized with metal overetching, but not to the extent of AlCu. Sidewall pitting was observed to be due to galvanic corrosion from copper precipitate formation. Overall yield has been improved along with decreased wafer cost compared to conventional tungsten plug technology.

Phase-synchroniser based on gm-C all-pass filter chain with sliding mode control

NASA Astrophysics Data System (ADS)

Mitić, Darko B.; Jovanović, Goran S.; Stojčev, Mile K.; Antić, Dragan S.

2015-03-01

Phase-synchronisers have many applications in VLSI circuit designs. They are used in CMOS RF circuits including phase (de)modulators, phase recovery circuits, multiphase synthesis, etc. In this article, a phase-synchroniser based on gm-C all-pass filter chain with sliding mode control is presented. The filter chain provides good controllable delay characteristics over the full range of phase and frequency regulation, without deterioration of input signal amplitude and waveform, while the sliding mode control enables us to achieve fast and predetermined finite locking time. IHP 0.25 µm SiGe BiCMOS technology has been used in design and verification processes. The circuit operates in the frequency range from 33 MHz up to 150 MHz. Simulation results indicate that it is possible to achieve very fast synchronisation time period, which is approximately four time intervals of the input signal during normal operation, and 20 time intervals during power-on.

Microwave components for cellular portable radiotelephone

NASA Astrophysics Data System (ADS)

Muraguchi, Masahiro; Aikawa, Masayoshi

1995-09-01

Mobile and personal communication systems are expected to represent a huge market for microwave components in the coming years. A number of components in silicon bipolar, silicon Bi-CMOS, GaAs MESFET, HBT and HEMT are now becoming available for system application. There are tradeoffs among the competing technologies with regard to performance, cost, reliability and time-to-market. This paper describes process selection and requirements of cost and r.f. performances to microwave semiconductor components for digital cellular and cordless telephones. Furthermore, new circuit techniques which were developed by NTT are presented.

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

2013-03-01

A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 μm CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

Integrated Kerr comb-based reconfigurable transversal differentiator for microwave photonic signal processing

NASA Astrophysics Data System (ADS)

Xu, Xingyuan; Wu, Jiayang; Shoeiby, Mehrdad; Nguyen, Thach G.; Chu, Sai T.; Little, Brent E.; Morandotti, Roberto; Mitchell, Arnan; Moss, David J.

2018-01-01

An arbitrary-order intensity differentiator for high-order microwave signal differentiation is proposed and experimentally demonstrated on a versatile transversal microwave photonic signal processing platform based on integrated Kerr combs. With a CMOS-compatible nonlinear micro-ring resonator, high quality Kerr combs with broad bandwidth and large frequency spacings are generated, enabling a larger number of taps and an increased Nyquist zone. By programming and shaping individual comb lines' power, calculated tap weights are realized, thus achieving a versatile microwave photonic signal processing platform. Arbitrary-order intensity differentiation is demonstrated on the platform. The RF responses are experimentally characterized, and systems demonstrations for Gaussian input signals are also performed.

A low-power RFID integrated circuits for intelligent healthcare systems.

PubMed

Lee, Shuenn-Yuh; Wang, Liang-Hung; Fang, Qiang

2010-11-01

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. With attention to power-efficient communication in the body sensor network, RF power transfer was estimated and the required low-power ICs, which are important in the development of a healthcare system with miniaturization and system integration, are discussed based on the RFID platform. To analyze the power transformation, this paper adopts a 915-MHz industrial, scientific, and medical RF with a radiation power of 70 mW to estimate the power loss under the 1-m communication distance between an RFID reader (bioinformation node) and a transponder (biosignal acquisition nodes). The low-power ICs of the transponder will be implemented in the TSMC 0.18-μm CMOS process. The simulation result reveals that the transponder's IC can fit in with the link budget of the UHF RFID system.

An RF energy harvesting power management circuit for appropriate duty-cycled operation

NASA Astrophysics Data System (ADS)

Shirane, Atsushi; Ito, Hiroyuki; Ishihara, Noboru; Masu, Kazuya

2015-04-01

In this study, we present an RF energy harvesting power management unit (PMU) for battery-less wireless sensor devices (WSDs). The proposed PMU realizes a duty-cycled operation that is divided into the energy charging time and discharging time. The proposed PMU detects two types of timing, thus, the appropriate timing for the activation can be recognized. The activation of WSDs at the proper timing leads to energy efficient operation and stable wireless communication. The proposed PMU includes a hysteresis comparator (H-CMP) and an RF signal detector (RF-SD) to detect the timings. The proposed RF-SD can operate without the degradation of charge efficiency by reusing the RF energy harvester (RF-EH) and H-CMP. The PMU fabricated in a 180 nm Si CMOS demonstrated the charge operation using the RF signal at 915 MHz and the two types of timing detection with less than 124 nW in the charge phase. Furthermore, in the active phase, the PMU generates a 0.5 V regulated power supply from the charged energy.

Emergency positioning system accuracy with infrared LEDs in high-security facilities

NASA Astrophysics Data System (ADS)

Knoch, Sierra N.; Nelson, Charles; Walker, Owens

2017-05-01

Instantaneous personnel location presents a challenge in Department of Defense applications where high levels of security restrict real-time tracking of crew members. During emergency situations, command and control requires immediate accountability of all personnel. Current radio frequency (RF) based indoor positioning systems can be unsuitable due to RF leakage and electromagnetic interference with sensitively calibrated machinery on variable platforms like ships, submarines and high-security facilities. Infrared light provide a possible solution to this problem. This paper proposes and evaluates an indoor line-of-sight positioning system that is comprised of IR and high-sensitivity CMOS camera receivers. In this system the movement of the LEDs is captured by the camera, uploaded and analyzed; the highest point of power is located and plotted to create a blueprint of crewmember location. Results provided evaluate accuracy as a function of both wavelength and environmental conditions. Research will further evaluate the accuracy of the LED transmitter and CMOS camera receiver system. Transmissions in both the 780 and 850nm IR are analyzed.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

NASA Astrophysics Data System (ADS)

Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

2015-10-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

The Biolink Implantable Telemetry System

NASA Technical Reports Server (NTRS)

Betancourt-Zamora, Rafael J.

1999-01-01

Most biotelemetry applications deal with the moderated data rates of biological signals. Few people have studied the problem of transcutaneous data transmission at the rates required by NASA's Life Sciences-Advanced BioTelemetry System (LS-ABTS). Implanted telemetry eliminate the problems associated with wire breaking the skin, and permits experiments with awake and unrestrained subjects. Our goal is to build a low-power 174-216MHz Radio Frequency (RF) transmitter suitable for short range biosensor and implantable use. The BioLink Implantable Telemetry System (BITS) is composed of three major units: an Analog Data Module (ADM), a Telemetry Transmitter Module (TTM), and a Command Receiver Module (CRM). BioLink incorporates novel low-power techniques to implement a monolithic digital RF transmitter operating at 100kbps, using quadrature phase shift keying (QPSK) modulation in the 174-216MHz ISM band. As the ADM will be specific for each application, we focused on solving the problems associated with a monolithic implementation of the TTM and CRM, and this is the emphasis of this report. A system architecture based on a Frequency-Locked Loop (FLL) Frequency Synthesizer is presented, and a novel differential frequency that eliminates the need for a frequency divider is also shown. A self sizing phase modulation scheme suitable for low power implementation was also developed. A full system-level simulation of the FLL was performed and loop filter parameters were determined. The implantable antenna has been designed, simulated and constructed. An implant package compatible with the ABTS requirements is also being proposed. Extensive work performed at 200MHz in 0.5um complementary metal oxide semiconductors (CMOS) showed the feasibility of integrating the RF transmitter circuits in a single chip. The Hajimiri phase noise model was used to optimize the Voltage Controlled Oscillator (VCO) for minimum power consumption. Two test chips were fabricated in a 0.5pm, 3V CMOS process. Measured phase noise for a 1.5mW, 200MHz ring oscillator VCO is -80dBc/Hz at 100KHZ offset, showing good agreement with the theory. We also propose a novel superregenerative receiver architecture for implementing the command receiver. The superregenerative receiver's simplicity, low cost, and low power consumption has made it the receiver of choice for short-distance data communications, remote control and home automation. We present the design of a superregenerative AM receiver implemented in a 0.5um CMOS technology that operates at 433.92MHz and dissipates only 300uW. Further work entails detailed transistor-level design of the FLL and superregenerative receiver and a monolithic implementation of an implantable transceiver in 0.5um CMOS technology.

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

NASA Astrophysics Data System (ADS)

Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

2009-05-01

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S21>13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

NASA Astrophysics Data System (ADS)

Park, Chester Sungchung; Park, Sungkyung

2018-07-01

A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6 ps and the typical settling time is <30 μs. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2 V single supply. The overall PLL draws about 1.1 mA from the supply.

A monolithic RF transceiver for DC-OFDM UWB

NASA Astrophysics Data System (ADS)

Yunfeng, Chen; Wei, Li; Haipeng, Fu; Ting, Gao; Danfeng, Chen; Feng, Zhou; Deyun, Cai; Dan, Li; Yangyang, Niu; Hanchao, Zhou; Ning, Zhu; Ning, Li; Junyan, Ren

2012-02-01

This paper presents a first monolithic RF transceiver for DC-OFDM UWB applications. The proposed direct-conversion transceiver integrates all the building blocks including two receiver (Rx) cores, two transmitter (Tx) cores and a dual-carrier frequency synthesizer (DC-FS) as well as a 3-wire serial peripheral interface (SPI) to set the operating status of the transceiver. The ESD-protected chip is fabricated by a TSMC 0.13-μm RF CMOS process with a die size of 4.5 × 3.6 mm2. The measurement results show that the wideband Rx achieves an NF of 5-6.2 dB, a max gain of 76-84 dB with 64-dB variable gain, an in-/out-of-band IIP3 of -6/+4 dBm and an input loss S11 of < -10 in all bands. The Tx achieves an LOLRR/IMGRR of -34/-33 dBc, a typical OIP3 of +6 dBm and a maximum output power of -5 dBm. The DC-FS outputs two separate carriers simultaneously with an inter-band hopping time of < 1.2 ns. The full chip consumes a maximum current of 420 mA under a 1.2-V supply.

Transmit/receive 3-20 GHz 1.2 mW packaged double-pole-16-throw switching matrix for radar-based target detection

NASA Astrophysics Data System (ADS)

Azhari, Afreen; Kuwano, Yuki; Xiao, Xia; Kikkawa, Takamaro

2018-01-01

A 3-20 GHz transmit/receive (T/R) double-pole-16-throw (DP16T) switching matrix has been developed on a printed circuit board (PCB) to control sixteen antennas in a radar-based portable breast-cancer detection system. The DP16T switch consists of four 65 nm CMOS 0.01-20 GHz double-pole-four-throw (DP4T) switches. The proposed switch increase the number of T/R combinations to 224 from the 196 of a conventional switching matrix in order to construct high-resolution images. Using this switch and a 4 × 4 slot antenna array, a 10 × 10 mm2 aluminum target was detected with an 8-GHz-center-frequency Gaussian monocycle pulse. The power consumption of the switch is only 1.2 mW. To the best of the authors’ knowledge, this is the first T/R radio frequency (RF) DP16T switching matrix, which was realized with four CMOS DP4T switches on a PCB and was measured with RF PCB connectors.

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

NASA Astrophysics Data System (ADS)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard CMOS IC. This device is expected to operate in hundreds of Mhz frequency range; quality factor surpasses 10000 and series motional impedance low enough that could be matching into conventional system without enormous effort. This MEMS resonator can be used in the design of many blocks in wireless and RF (Radio Frequency) systems such as low phase noise oscillator, band pass filter, power amplifier and in many sensing application.

An inductorless active mixer using stacked nMOS/pMOS configuration and LO shaping technique

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Jun; Wang, Xuebing; Chen, Hongpeng

2018-04-01

In this paper, a CMOS active down-conversion mixer is presented for wideband applications. Specifically, a LO generation chain is suggested to convert AC LO signal to shaped trapezoid burst, which reduces the sinusoidal LO power level requirement by the mixer. The current-reuse technique by stacked nMOS/pMOS architecture is used to save the power consumption of the circuit. Moreover, this complementary configuration is also employed to compensate second-order nonlinearity of the circuit. Implemented in a 0.18-μm CMOS process, post-simulations show that, driven by only ‑10 dBm sinusoidal LO signal, the proposed inductorless mixer provides a maximal conversion gain of 15.7 dB and a noise figure (NF) of 9.1-12 dB across RF input frequency range 0.5-1.6 GHz. The IIP3 and IP1dB of 3.5 dBm and ‑4.8 dBm are obtained, respectively. The mixer core only consumes 3.6 mW from a 1.8-V supply.

Preface to the special issue of Solid State Electronics EUROSOI/ULIS 2017

NASA Astrophysics Data System (ADS)

Nassiopoulou, Androula G.

2018-05-01

This special issue is devoted to selected papers presented at the EuroSOI-ULIS2017 international conference, held in Athens on 3-5 April 2017. EuroSOI-ULIS2017 Conference was mainly devoted to Si devices, which constitute the basic building blocks of any microelectronic circuit. It included papers on advanced Si technologies, novel nanoscale devices, advanced electronic materials and device architectures, mechanisms involved, test structures, substrate materials and technologies, modeling/simulation and characterization. Both CMOS and beyond CMOS devices were presented, covering the More Moore domain, as well as new functionalities in silicon-compatible nanostructures and innovative devices, representing the More than Moore domain (on-chip sensors, biosensors, energy harvesting devices, RF passives, etc.).

PREFACE: The Second Conference on Microelectronics, Microsystems and Nanotechnology

NASA Astrophysics Data System (ADS)

Nassiopoulou, Androula G.; Papanikolaou, Nikos; Tsamis, Christos

2005-01-01

The Second Conference on Microelectronics, Microsystems and Nanotechnology took place at the National Centre for Scientific Research `Demokritos', in Athens, Greece, between 14 and 17 November 2004. The conference was organized by the Institute of Microelectronics (IMEL) with the aim to bring together scientists and engineers working in the above exciting fields in an interactive forum. The conference included 45 oral presentations with 9 invited papers and was attended by 146 participants from 16 countries. The topics covered were nanotechnologies, quantum devices, sensors, micro- and nano-systems, semiconductor devices, C-MOS fabrication and characterization techniques, new materials, and IC design. Quantum devices and nanostructured materials attracted considerable attention. Both theoretical and experimental studies of metallic and semiconducting quantum systems were presented, with emphasis on their applications in electronics, optoelectronics, and nanocrystal memory devices. Another exciting topic was the recent developments in biocompatible lithographic processes for applications in biosensors. In particular novel processes for bio-friendly lithography, together with innovations in Si sensors for applications in medicine and food industry were presented. Recent developments and perspectives in CMOS technology towards the ultimate limit were also discussed. The conference covered issues and concepts of IC design with two invited talks on RF design and cryptography.The conference included presentations from several companies active in the field of microelectronics and systems in Greece.

Design of a 2.4-GHz CMOS monolithic fractional-N frequency synthesizer

NASA Astrophysics Data System (ADS)

Shu, Keliu

The wireless communication technology and market have been growing rapidly since a decade ago. The high demand market is a driving need for higher integration in the wireless transceivers. The trend is to achieve low-cost, small form factor and low power consumption. With the ever-reducing feature size, it is becoming feasible to integrate the RF front-end together with the baseband in the low-cost CMOS technology. The frequency synthesizer is a key building block in the RF front-end of the transceivers. It is used as a local oscillator for frequency translation and channel selection. The design of a 2.4-GHz low-power frequency synthesizer in 0.35mum CMOS is a challenging task mainly due to the high-speed prescaler. In this dissertation, a brief review of conventional PLL and frequency synthesizers is provided. Design techniques of a 2.4-GHz monolithic SigmaDelta fractional-N frequency synthesizer are investigated. Novel techniques are proposed to tackle the speed and integration bottlenecks of high-frequency PLL. A low-power and inherently glitch-free phase-switching prescaler and an on-chip loop filter with capacitance multiplier are developed. Compared with the existing and popular dual-path topology, the proposed loop filter reduces circuit complexity and its power consumption and noise are negligible. Furthermore, a third-order three-level digital SigmaDelta modulator topology is employed to reduce the phase noise generated by the modulator. Suitable PFD and charge-pump designs are employed to reduce their nonlinearity effects and thus minimize the folding of the SigmaDelta modulator-shaped phase noise. A prototype of the fractional-N synthesizer together with some standalone building blocks is designed and fabricated in TSMC 0.35mum CMOS through MOSIS. The prototype frequency synthesizer and standalone prescaler and loop filter are characterized. The feasibility and practicality of the proposed prescaler and loop filter are experimentally verified.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

UHF front-end feeding RFID-based body sensor networks by exploiting the reader signal

NASA Astrophysics Data System (ADS)

Pasca, M.; Colella, R.; Catarinucci, L.; Tarricone, L.; D'Amico, S.; Baschirotto, A.

2016-05-01

This paper presents an integrated, high-sensitivity UHF radio frequency identification (RFID) power management circuit for body sensor network applications. The circuit consists of a two-stage RF-DC Dickson's rectifier followed by an integrated five-stage DC-DC Pelliconi's charge pump driven by an ultralow start-up voltage LC oscillator. The DC-DC charge pump interposed between the RF-DC rectifier and the output load provides the RF to load isolation avoiding losses due to the diodes reverse saturation current. The RF-DC rectifier has been realized on FR4 substrate, while the charge pump and the oscillator have been realized in 180 nm complementary metal oxide semiconductor (CMOS) technology. Outdoor measurements demonstrate the ability of the power management circuit to provide 400 mV output voltage at 14 m distance from the UHF reader, in correspondence of -25 dBm input signal power. As demonstrated in the literature, such output voltage level is suitable to supply body sensor network nodes.

BICMOS power detector for pulsed Rf power amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bridge, Clayton D.

2016-10-01

A BiCMOS power detector for pulsed radio-frequency power amplifiers is proposed. Given the pulse waveform and a fraction of the power amplifier's input or output signal, the detector utilizes a low-frequency feedback loop to perform a successive approximation of the amplitude of the input signal. Upon completion of the successive approximation, the detector returns 9-bits representing the amplitude of the RF input signal. Using the pulse waveform from the power amplifier, the detector can dynamically adjust the rate of the binary search operation in order to return the updated amplitude information of the RF input signal at least every 1ms.more » The detector can handle pulse waveform frequencies from 50kHz to 10MHz with duty cycles in the range of 5- 50% and peak power levels of -10 to 10dBm. The signal amplitude measurement can be converted to a peak power measurement accurate to within ±0.6dB of the input RF power.« less

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

NASA Astrophysics Data System (ADS)

Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

2007-05-01

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

A Monolithic Multisensor Microchip with Complete On-Chip RF Front-End

PubMed Central

Felini, Corrado; Della Corte, Francesco G.

2018-01-01

In this paper, a new wireless sensor, designed for a 0.35 µm CMOS technology, is presented. The microchip was designed to be placed on an object for the continuous remote monitoring of its temperature and illumination state. The temperature sensor is based on the temperature dependence of the I-V characteristics of bipolar transistors available in CMOS technology, while the illumination sensor is an integrated p-n junction photodiode. An on-chip 2.5 GHz transmitter, coupled to a mm-sized dipole radiating element fabricated on the same microchip and made in the top metal layer of the same die, sends the collected data wirelessly to a radio receiver using an On-Off Keying (OOK) modulation pattern. PMID:29301297

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Three-dimensional impedance engineering for mixed-signal system-on-chip applications

NASA Astrophysics Data System (ADS)

Chong, Kyuchul

A novel approach for three-dimensional substrate impedance engineering of p-/p+ epi substrate is proposed for mixed-signal integrated circuit applications. This technology requires minimum intrusion to conventional Si CMOS processing, but offers astounding improvements with regard to RF crosstalk via substrate and RF passive device performance. The engineered substrate consists of conducting as well as semi-insulating regions strategically placed three-dimensionally throughout the volume of the substrate. The p-/p+ epi substrate is used to prevent latch-up at tight design rules in high performance digital CMOS. Metal vias are fabricated from the front side using electroless plating method for Faraday cage isolation structure as well as "true ground" contacts. A self-limiting micro-PS formation process is employed to allow the insertion of semi-insulating regions from the backside of the wafer and RIE etch to remove p- layer is performed from the front side completely eliminating any parasitic pathways for crosstalk. The crosstalk isolation methods in this study are based on the principle of RF noise shielding in addition to insulating. Both the suppression of crosstalk by the metal vias and micro-PS trench isolation are so significant that the crosstalk goes down to the noise floor of the conventional measurement instruments. The use of micro-PS layer effectively can reduce the parasitic substrate effect. These reductions result in higher Q and fr of inductors on micro-PS region. Inductors located on micro-PS are subjected to a much less stringent set of constraints than that on bulk Si substrates, allowing for much higher inductance without severe sacrifice in Q and fr, and much higher Q for with reasonable inductance and fr. The bond pad structure using micro-PS can significantly reduce the parasitic bond pad capacitance and increases the crosstalk isolation characteristic. Reducing the parasitic pad capacitance by using micro-PS results in high bond pad resonant frequency of up to 56.2 GHz. The crosstalk between bond pads becomes much smaller than that of conventional p- bulk substrate by using micro-PS. In addition, the use of micro-PS leads to greatly improved transformer performances including higher Q and fr, mutual reactive coupling coefficients with larger useable band-width and maximum available gain by reducing the substrate effect.

Toward a reduced-wire readout system for ultrasound imaging.

PubMed

Lim, Jaemyung; Arkan, Evren F; Degertekin, F Levent; Ghovanloo, Maysam

2014-01-01

We present a system-on-a-chip (SoC) for use in high-frequency capacitive micromachined ultrasonic transducer (CMUT) imaging systems. This SoC consists of trans-impedance amplifiers (TIA), delay locked loop (DLL) based clock multiplier, quadrature sampler, and pulse width modulator (PWM). The SoC down converts RF echo signal to baseband by quadrature sampling which facilitates modulation. To send data through a 1.6 m wire in the catheter which has limited bandwidth and is vulnerable to noise, the SoC creates a pseudo-digital PWM signal which can be used for back telemetry or wireless readout of the RF data. In this implementation, using a 0.35-μm std. CMOS process, the TIA and single-to-differential (STD) converter had 45 MHz bandwidth, the quadrature sampler had 10.1 dB conversion gain, and the PWM had 5-bit ENoB. Preliminary results verified front-end functionality, and the power consumption of a TIA, STD, quadrature sampler, PWM, and clock multiplier was 26 mW from a 3 V supply.

Toward a Reduced-Wire Readout System for Ultrasound Imaging

PubMed Central

Lim, Jaemyung; Arkan, Evren F.; Degertekin, F. Levent; Ghovanloo, Maysam

2015-01-01

We present a system-on-a-chip (SoC) for use in high-frequency capacitive micromachined ultrasonic transducer (CMUT) imaging systems. This SoC consists of trans-impedance amplifiers (TIA), delay locked loop (DLL) based clock multiplier, quadrature sampler, and pulse width modulator (PWM). The SoC down converts RF echo signal to baseband by quadrature sampling which facilitates modulation. To send data through a 1.6 m wire in the catheter which has limited bandwidth and is vulnerable to noise, the SoC creates a pseudo-digital PWM signal which can be used for back telemetry or wireless readout of the RF data. In this implementation, using a 0.35-μm std. CMOS process, the TIA and single-to-differential (STD) converter had 45 MHz bandwidth, the quadrature sampler had 10.1 dB conversion gain, and the PWM had 5-bit ENoB. Preliminary results verified front-end functionality, and the power consumption of a TIA, STD, quadrature sampler, PWM, and clock multiplier was 26 mW from a 3 V supply. PMID:25571135

Space Shuttle communications RF switch matrix

NASA Technical Reports Server (NTRS)

Winch, R.

1979-01-01

The Shuttle Orbiter communications equipment includes phase modulation (PM) and frequency modulation (FM) channels. The PM section has the capability of routing high levels of energy (175 W) from any one of four transmitters to any one of four antennas, mutually exclusive. The FM channel uses a maximum of 15-W power routed from either of two transmitters to one of two antennas, mutually exclusive. The paper describes the design and the theory of a logic-controlled RF switch matrix devised for the purposes cited. Both PM and FM channels are computer-controlled with manual overrides. The logic interface is realized with CMOS logic for low power consumption and high noise immunity. The interior of the switch matrix is maintained at a pressure of 15 psi (90% nitrogen, 10% helium) by an electron beam-welded encapsulation. The computational results confirm the viability of the RF switch matrix concept.

Radiofrequency characteristics of ionized sputtered tantalum nitride thin-film resistor in CMOS device

NASA Astrophysics Data System (ADS)

Sul, Woo Suk; Kwon, Soon Hyeong; Choi, Eunmi; Cui, Yinhua; Lee, Kang Won; Shim, Ho Jae; Gao, Yuan; Hahn, Sang June; Pyo, Sung Gyu

2017-05-01

We report the analysis of the radiofrequency (RF) characteristics according to the size, area, and shape of TaN thin-film resistor (TFR) layers. As the TFR size increased, its characteristics were degraded with increasing frequency owing to the increased capacitive parasitic components. As the frequency increased from 1 MHz to 10 GHz, the effective resistance decreased by approximately 12.5%, 16.4%, and 37.8% when the resistor widths and lengths were 0.5 × 20, 1 × 40, and 2 × 80 μm, respectively. To optimize the performance of the high-frequency TFR, ensuring RF isolation via sufficient separation from the silicon substrates was crucial. To realize this RF isolation, methods for minimizing the effect of lossy Si substrates by using TFRs with a smaller area or by forming a patterned ground shield should be introduced. [Figure not available: see fulltext.

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

NASA Astrophysics Data System (ADS)

Varlamava, Volha; De Amicis, Giovanni; Del Monte, Andrea; Perticaroli, Stefano; Rao, Rosario; Palma, Fabrizio

2016-08-01

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Non-contact thermoacoustic detection of embedded targets using airborne-capacitive micromachined ultrasonic transducers

NASA Astrophysics Data System (ADS)

Nan, Hao; Boyle, Kevin C.; Apte, Nikhil; Aliroteh, Miaad S.; Bhuyan, Anshuman; Nikoozadeh, Amin; Khuri-Yakub, Butrus T.; Arbabian, Amin

2015-02-01

A radio frequency (RF)/ultrasound hybrid imaging system using airborne capacitive micromachined ultrasonic transducers (CMUTs) is proposed for the remote detection of embedded objects in highly dispersive media (e.g., water, soil, and tissue). RF excitation provides permittivity contrast, and ultra-sensitive airborne-ultrasound detection measures thermoacoustic-generated acoustic waves that initiate at the boundaries of the embedded target, go through the medium-air interface, and finally reach the transducer. Vented wideband CMUTs interface to 0.18 μm CMOS low-noise amplifiers to provide displacement detection sensitivity of 1.3 pm at the transducer surface. The carefully designed vented CMUT structure provides a fractional bandwidth of 3.5% utilizing the squeeze-film damping of the air in the cavity.

SOI-CMOS Process for Monolithic, Radiation-Tolerant, Science-Grade Imagers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Williams, George; Lee, Adam

In Phase I, Voxtel worked with Jazz and Sandia to document and simulate the processes necessary to implement a DH-BSI SOI CMOS imaging process. The development is based upon mature SOI CMOS process at both fabs, with the addition of only a few custom processing steps for integration and electrical interconnection of the fully-depleted photodetectors. In Phase I, Voxtel also characterized the Sandia process, including the CMOS7 design rules, and we developed the outline of a process option that included a “BOX etch”, that will permit a “detector in handle” SOI CMOS process to be developed The process flows weremore » developed in cooperation with both Jazz and Sandia process engineers, along with detailed TCAD modeling and testing of the photodiode array architectures. In addition, Voxtel tested the radiation performance of the Jazz’s CA18HJ process, using standard and circular-enclosed transistors.« less

Graphene Quantum Capacitors for High Frequency Tunable Analog Applications.

PubMed

Moldovan, Clara F; Vitale, Wolfgang A; Sharma, Pankaj; Tamagnone, Michele; Mosig, Juan R; Ionescu, Adrian M

2016-08-10

Graphene quantum capacitors (GQC) are demonstrated to be enablers of radio-frequency (RF) functions through voltage-tuning of their capacitance. We show that GQC complements MEMS and MOSFETs in terms of performance for high frequency analog applications and tunability. We propose a CMOS compatible fabrication process and report the first experimental assessment of their performance at microwaves frequencies (up to 10 GHz), demonstrating experimental GQCs in the pF range with a tuning ratio of 1.34:1 within 1.25 V, and Q-factors up to 12 at 1 GHz. The figures of merit of graphene variable capacitors are studied in detail from 150 to 350 K. Furthermore, we describe a systematic, graphene specific approach to optimize their performance and predict the figures of merit achieved if such a methodology is applied.

A low power wearable transceiver for human body communication.

PubMed

Huang, Jin; Chen, Lian-Kang; Zhang, Yuan-Ting

2009-01-01

This paper reports a low power transceiver designed for wearable medical healthcare system. Based on a novel energy-efficient wideband wireless communication scheme that uses human body as a transmission medium, the transceiver can achieve a maximum 15 Mbps data rate with total receiver sensitivity of -30 dBm. The chip measures only 0.56 mm(2) and was fabricated in the SMIC 0.18um 1P6M RF CMOS process. The RX consumes 5mW and TX dissipates 1mW with delivering power up to 10uW, which is suitable for the body area network short range application. Real-time medical information collecting through the human body is fully simulated. Architecture of the chip together with the detail characterizes from its wireless analog front-end are presented.

A miniature batteryless health and usage monitoring system based on hybrid energy harvesting

NASA Astrophysics Data System (ADS)

Huang, Chenling; Chakrabartty, Shantanu

2011-04-01

The cost and size of the state-of-the-art health and usage monitoring systems (HUMS) are determined by capacity of on-board energy storage which limits their large scale deployment. In this paper, we present a miniature low-cost mechanical HUMS integrated circuit (IC) based on the concept of hybrid energy harvesting where continuous monitoring is achieved by self-powering, where as the programming, localization and communication with the sensor is achieved using remote RF powering. The self-powered component of the proposed HUMS is based on our previous result which used a controllable hot electron injection on floatinggate transistor as an ultra-low power signal processor. We show that the HUMS IC can seamlessly switch between different energy harvesting modes based on the availability of ambient RF power and that the configuration, programming and communication functions can be remotely performed without physically accessing the HUMS device. All the measured results presented in this paper have been obtained from prototypes fabricated in a 0.5 micron standard CMOS process and the entire system has been successfully integrated on a 1.5cm x 1.5cm package.

New Analysis and Design of a RF Rectifier for RFID and Implantable Devices

PubMed Central

Liu, Dong-Sheng; Li, Feng-Bo; Zou, Xue-Cheng; Liu, Yao; Hui, Xue-Mei; Tao, Xiong-Fei

2011-01-01

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from −15 dBm to −4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitableto passive UHF RFID tag IC and implantable devices. PMID:22163968

New analysis and design of a RF rectifier for RFID and implantable devices.

PubMed

Liu, Dong-Sheng; Li, Feng-Bo; Zou, Xue-Cheng; Liu, Yao; Hui, Xue-Mei; Tao, Xiong-Fei

2011-01-01

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from -15 dBm to -4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitable to passive UHF RFID tag IC and implantable devices.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Superconductor Digital Electronics: -- Current Status, Future Prospects

NASA Astrophysics Data System (ADS)

Mukhanov, Oleg

2011-03-01

Two major applications of superconductor electronics: communications and supercomputing will be presented. These areas hold a significant promise of a large impact on electronics state-of-the-art for the defense and commercial markets stemming from the fundamental advantages of superconductivity: simultaneous high speed and low power, lossless interconnect, natural quantization, and high sensitivity. The availability of relatively small cryocoolers lowered the foremost market barrier for cryogenically-cooled superconductor electronic systems. These fundamental advantages enabled a novel Digital-RF architecture - a disruptive technological approach changing wireless communications, radar, and surveillance system architectures dramatically. Practical results were achieved for Digital-RF systems in which wide-band, multi-band radio frequency signals are directly digitized and digital domain is expanded throughout the entire system. Digital-RF systems combine digital and mixed signal integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology, superconductor analog filter circuits, and semiconductor post-processing circuits. The demonstrated cryocooled Digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals, enabling multi-net data links, and performing signal acquisition from HF to L-band with 30 GHz clock frequencies. In supercomputing, superconductivity leads to the highest energy efficiencies per operation. Superconductor technology based on manipulation and ballistic transfer of magnetic flux quanta provides a superior low-power alternative to CMOS and other charge-transfer based device technologies. The fundamental energy consumption in SFQ circuits defined by flux quanta energy 2 x 10-19 J. Recently, a novel energy-efficient zero-static-power SFQ technology, eSFQ/ERSFQ was invented, which retains all advantages of standard RSFQ circuits: high-speed, dc power, internal memory. The voltage bias regulation, determined by SFQ clock, enables the zero-power at zero-activity regimes, indispensable for sensor and quantum bit readout.

A terahertz performance of hybrid single walled CNT based amplifier with analytical approach

NASA Astrophysics Data System (ADS)

Kumar, Sandeep; Song, Hanjung

2018-01-01

This work is focuses on terahertz performance of hybrid single walled carbon nanotube (CNT) based amplifier and proposed for measurement of soil parameters application. The proposed circuit topology provides hybrid structure which achieves wide impedance bandwidth of 0.33 THz within range of 1.07-THz to 1.42-THz with fractional amount of 28%. The single walled RF CNT network executes proposed ambition and proves its ability to resonant at 1.25-THz with analytical approach. Moreover, a RF based microstrip transmission line radiator used as compensator in the circuit topology which achieves more than 30 dB of gain. A proper methodology is chosen for achieves stability at circuit level in order to obtain desired optimal conditions. The fundamental approach optimizes matched impedance condition at (50+j0) Ω and noise variation with impact of series resistances for the proposed hybrid circuit topology and demonstrates the accuracy of performance parameters at the circuit level. The chip fabrication of the proposed circuit by using RF based commercial CMOS process of 45 nm which reveals promising results with simulation one. Additionally, power measurement analysis achieves highest output power of 26 dBm with power added efficiency of 78%. The succeed minimum noise figure from 0.6 dB to 0.4 dB is outstanding achievement for circuit topology at terahertz range. The chip area of hybrid circuit is 0.65 mm2 and power consumption of 9.6 mW.

Design of a multi-axis implantable MEMS sensor for intraosseous bone stress monitoring

NASA Astrophysics Data System (ADS)

Alfaro, Fernando; Weiss, Lee; Campbell, Phil; Miller, Mark; Fedder, Gary K.

2009-08-01

The capability to assess the biomechanical properties of living bone is important for basic research as well as the clinical management of skeletal trauma and disease. Even though radiodensitometric imaging is commonly used to infer bone quality, bone strength does not necessarily correlate well with these non-invasive measurements. This paper reports on the design, fabrication and initial testing of an implantable ultra-miniature multi-axis sensor for directly measuring bone stresses at a micro-scale. The device, which is fabricated with CMOS-MEMS processes, is intended to be permanently implanted within open fractures, or embedded in bone grafts, or placed on implants at the interfaces between bone and prosthetics. The stress sensor comprises an array of piezoresistive pixels to detect a stress tensor at the interfacial area between the MEMS chip and bone, with a resolution to 100 Pa, in 1 s averaging. The sensor system design and manufacture is also compatible with the integration of wireless RF telemetry, for power and data retrieval, all within a 3 mm × 3 mm × 0.3 mm footprint. The piezoresistive elements are integrated within a textured surface to enhance sensor integration with bone. Finite element analysis led to a sensor design for normal and shear stress detection. A wired sensor was fabricated in the Jazz 0.35 µm BiCMOS process and then embedded in mock bone material to characterize its response to tensile and bending loads up to 250 kPa.

Self-calibrated humidity sensor in CMOS without post-processing.

PubMed

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

All-CMOS night vision viewer with integrated microdisplay

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

A Low Power 2.4 GHz CMOS Mixer Using Forward Body Bias Technique for Wireless Sensor Network

NASA Astrophysics Data System (ADS)

Yin, C. J.; Murad, S. A. Z.; Harun, A.; Ramli, M. M.; Zulkifli, T. Z. A.; Karim, J.

2018-03-01

Wireless sensor network (WSN) is a highly-demanded application since the evolution of wireless generation which is often used in recent communication technology. A radio frequency (RF) transceiver in WSN should have a low power consumption to support long operating times of mobile devices. A down-conversion mixer is responsible for frequency translation in a receiver. By operating a down-conversion mixer at a low supply voltage, the power consumed by WSN receiver can be greatly reduced. This paper presents a development of low power CMOS mixer using forward body bias technique for wireless sensor network. The proposed mixer is implemented using CMOS 0.13 μm Silterra technology. The forward body bias technique is adopted to obtain low power consumption. The simulation results indicate that a low power consumption of 0.91 mW is achieved at 1.6 V supply voltage. Moreover, the conversion gain (CG) of 21.83 dB, the noise figure (NF) of 16.51 dB and the input-referred third-order intercept point (IIP3) of 8.0 dB at 2.4 GHz are obtained. The proposed mixer is suitable for wireless sensor network.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

A fully integrated direct-conversion digital satellite tuner in 0.18 μm CMOS

NASA Astrophysics Data System (ADS)

Si, Chen; Zengwang, Yang; Mingliang, Gu

2011-04-01

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 °C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

Silicon-gate CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1979-01-01

Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discussed, as well as the following process variations: (1) the double epi process; and (2) ion implantation.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Carbon Nanotube Integration with a CMOS Process

PubMed Central

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Fabrication of the planar angular rotator using the CMOS process

NASA Astrophysics Data System (ADS)

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

An RFID tag system-on-chip with wireless ECG monitoring for intelligent healthcare systems.

PubMed

Wang, Cheng-Pin; Lee, Shuenn-Yuh; Lai, Wei-Chih

2013-01-01

This paper presents a low-power wireless ECG acquisition system-on-chip (SoC), including an RF front-end circuit, a power unit, an analog front-end circuit, and a digital circuitry. The proposed RF front-end circuit can provide the amplitude shift keying demodulation and distance to digital conversion to accurately receive the data from the reader. The received data will wake up the power unit to provide the required supply voltages of analog front-end (AFE) and digital circuitry. The AFE, including a pre-amplifier, an analog filter, a post-amplifier, and an analog-to-digital converter, is used for the ECG acquisition. Moreover, the EPC Class I Gen 2 UHF standard is employed in the digital circuitry for the handshaking of communication and the control of the system. The proposed SoC has been implemented in 0.18-µm standard CMOS process and the measured results reveal the communication is compatible to the RFID protocol. The average power consumption for the operating chip is 12 µW. Using a Sony PR44 battery to the supply power (605mAh@1.4V), the RFID tag SoC operates continuously for about 50,000 hours (>5 years), which is appropriate for wireless wearable ECG monitoring systems.

A battery-free multichannel digital neural/EMG telemetry system for flying insects.

PubMed

Thomas, Stewart J; Harrison, Reid R; Leonardo, Anthony; Reynolds, Matthew S

2012-10-01

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902-928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10⁻⁵ BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 μ m 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36 × 1.88 mm, is 250 μm thick, and is wire bonded into a flex circuit assembly measuring 4.6 × 6.8 mm.

A wireless narrowband imaging chip for capsule endoscope.

PubMed

Lan-Rong Dung; Yin-Yi Wu

2010-12-01

This paper presents a dual-mode capsule gastrointestinal endoscope device. An endoscope combined with a narrowband image (NBI), has been shown to be a superior diagnostic tool for early stage tissue neoplasms detection. Nevertheless, a wireless capsule endoscope with the narrowband imaging technology has not been presented in the market up to now. The narrowband image acquisition and power dissipation reduction are the main challenges of NBI capsule endoscope. In this paper, we present the first narrowband imaging capsule endoscope that can assist clinical doctors to effectively diagnose early gastrointestinal cancers, profited from our dedicated dual-mode complementary metal-oxide semiconductor (CMOS) sensor. The dedicated dual-mode CMOS sensor can offer white-light and narrowband images. Implementation results show that the proposed 512 × 512 CMOS sensor consumes only 2 mA at a 3-V power supply. The average current of the NBI capsule with an 8-Mb/s RF transmitter is nearly 7 ~ 8 mA that can continuously work for 6 ~ 8 h with two 1.5-V 80-mAh button batteries while the frame rate is 2 fps. Experimental results on backside mucosa of a human tongue and pig's small intestine showed that the wireless NBI capsule endoscope can significantly improve the image quality, compared with a commercial-of-the-shelf capsule endoscope for gastrointestinal tract diagnosis.

LNA with wide range of gain control and wideband interference rejection

NASA Astrophysics Data System (ADS)

Wang, Jhen-Ji; Chen, Duan-Yu

2016-10-01

This work presents a low-noise amplifier (LNA) design with a wide-range gain control characteristic that integrates adjustable current distribution and output impedance techniques. For a given gain characteristic, the proposed LNA provides better wideband interference rejection performance than conventional LNA. Moreover, the proposed LNA also has a wider gain control range than conventional LNA. Therefore, it is suitable for satellite communications systems. The simulation results demonstrate that the voltage gain control range is between 14.5 and 34.2 dB for such applications (2600 MHz); the input reflection coefficient is less than -18.9 dB; the noise figure (NF) is 1.25 dB; and the third-order intercept point (IIP3) is 4.52 dBm. The proposed LNA consumes 23.85-28.17 mW at a supply voltage of 1.8 V. It is implemented by using TSMC 0.18-um RF CMOS process technology.

A novel high-performance high-frequency SOI MESFET by the damped electric field

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

2016-06-01

In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Delta Doping High Purity CCDs and CMOS for LSST

NASA Technical Reports Server (NTRS)

Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

2006-01-01

A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

The design of the CMOS wireless bar code scanner applying optical system based on ZigBee

NASA Astrophysics Data System (ADS)

Chen, Yuelin; Peng, Jian

2008-03-01

The traditional bar code scanner is influenced by the length of data line, but the farthest distance of the wireless bar code scanner of wireless communication is generally between 30m and 100m on the market. By rebuilding the traditional CCD optical bar code scanner, a CMOS code scanner is designed based on the ZigBee to meet the demands of market. The scan system consists of the CMOS image sensor and embedded chip S3C2401X, when the two dimensional bar code is read, the results show the inaccurate and wrong code bar, resulted from image defile, disturber, reads image condition badness, signal interference, unstable system voltage. So we put forward the method which uses the matrix evaluation and Read-Solomon arithmetic to solve them. In order to construct the whole wireless optics of bar code system and to ensure its ability of transmitting bar code image signals digitally with long distances, ZigBee is used to transmit data to the base station, and this module is designed based on image acquisition system, and at last the wireless transmitting/receiving CC2430 module circuit linking chart is established. And by transplanting the embedded RTOS system LINUX to the MCU, an applying wireless CMOS optics bar code scanner and multi-task system is constructed. Finally, performance of communication is tested by evaluation software Smart RF. In broad space, every ZIGBEE node can realize 50m transmission with high reliability. When adding more ZigBee nodes, the transmission distance can be several thousands of meters long.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Process Performance of Optima XEx Single Wafer High Energy Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.

2011-01-07

To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstreammore » dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.« less

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

SOI MESFETs on high-resistivity, trap-rich substrates

NASA Astrophysics Data System (ADS)

Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

2018-04-01

The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

NASA Astrophysics Data System (ADS)

Muhamad, M.; Soin, N.; Ramiah, H.

2018-03-01

This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

Application of CMOS Technology to Silicon Photomultiplier Sensors.

PubMed

D'Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-09-25

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Overview of CMOS process and design options for image sensor dedicated to space applications

NASA Astrophysics Data System (ADS)

Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

2005-10-01

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

USB video image controller used in CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhang, Wenxuan; Wang, Yuxia; Fan, Hong

2002-09-01

CMOS process is mainstream technique in VLSI, possesses high integration. SE402 is multifunction microcontroller, which integrates image data I/O ports, clock control, exposure control and digital signal processing into one chip. SE402 reduces the number of chips and PCB's room. The paper studies emphatically on USB video image controller used in CMOS image sensor and give the application on digital still camera.

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

NASA Technical Reports Server (NTRS)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18µm CMOS

NASA Astrophysics Data System (ADS)

Edward, Alexander; Chan, Pak Kwong

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

PubMed Central

Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

2014-01-01

Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

Application of CMOS Technology to Silicon Photomultiplier Sensors

PubMed Central

D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-01-01

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

Fundamental performance differences of CMOS and CCD imagers: part V

NASA Astrophysics Data System (ADS)

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

New integration concept of PIN photodiodes in 0.35μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Teva, J.; Park, J. M.; Jessenig, S.; Rohrbacher, M.; Wachmann, E.

2012-06-01

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 1•1012/cm3. In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 4•1013/cm3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100×100μm2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

CMOS-micromachined, two-dimenisional transistor arrays for neural recording and stimulation.

PubMed

Lin, J S; Chang, S R; Chang, C H; Lu, S C; Chen, H

2007-01-01

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die-level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

Ion traps fabricated in a CMOS foundry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mehta, K. K.; Ram, R. J.; Eltony, A. M.

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size.more » This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.« less

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Fully Integrated Optical Spectrometer in Visible and Near-IR in CMOS.

PubMed

Hong, Lingyu; Sengupta, Kaushik

2017-12-01

Optical spectrometry in the visible and near-infrared range has a wide range of applications in healthcare, sensing, imaging, and diagnostics. This paper presents the first fully integrated optical spectrometer in standard bulk CMOS process without custom fabrication, postprocessing, or any external optical passive structure such as lenses, gratings, collimators, or mirrors. The architecture exploits metal interconnect layers available in CMOS processes with subwavelength feature sizes to guide, manipulate, control, diffract light, integrated photodetector, and read-out circuitry to detect dispersed light, and then back-end signal processing for robust spectral estimation. The chip, realized in bulk 65-nm low power-CMOS process, measures 0.64 mm 0.56 mm in active area, and achieves 1.4 nm in peak detection accuracy for continuous wave excitations between 500 and 830 nm. This paper demonstrates the ability to use these metal-optic nanostructures to miniaturize complex optical instrumentation into a new class of optics-free CMOS-based systems-on-chip in the visible and near-IR for various sensing and imaging applications.

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

PubMed Central

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

NASA Astrophysics Data System (ADS)

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

NASA Astrophysics Data System (ADS)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

A CMOS high speed imaging system design based on FPGA

NASA Astrophysics Data System (ADS)

Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

2015-10-01

CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

Advancement of CMOS Doping Technology in an External Development Framework

NASA Astrophysics Data System (ADS)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

NASA Astrophysics Data System (ADS)

Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

2018-04-01

Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

PubMed

Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

2015-05-07

In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

NASA Astrophysics Data System (ADS)

Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

2017-05-01

Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive electro-optic characterization of these components will be presented.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

A fractional-N frequency synthesizer for WCDMA/Bluetooth/ZigBee applications

NASA Astrophysics Data System (ADS)

Chunyuan, Zhou; Guolin, Li; Chun, Zhang; Baoyong, Chi; Dongmei, Li; Zhihua, Wang

2009-07-01

A triple-mode fractional-N frequency synthesizer with a noise-filter voltage controlled oscillator (VCO) for WCDMA/Bluetooth/ZigBee applications has been implemented in 0.18-μm RF-CMOS technology. The proposed synthesizer achieves a good phase noise lower than -80 dBc/Hz in band and -115 dBc/Hz@1 MHz for the three modes, and only draws 21 mA from a 1.8 V supply. It has a high hardware sharing and a small size, only 1.5 × 1.4 mm2. The system architecture, circuit design, and measured results are also presented.

Portable design rules for bulk CMOS

NASA Technical Reports Server (NTRS)

Griswold, T. W.

1982-01-01

It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Fully CMOS-compatible titanium nitride nanoantennas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Briggs, Justin A., E-mail: jabriggs@stanford.edu; Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305; Naik, Gururaj V.

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements onmore » plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.« less

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka

2011-10-20

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensorsmore » are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.« less

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1979-01-01

Modifications and additions to the present process of making CMOS microcircuits which are designed to provide protective layers on the chip to guard against moisture and contaminants were investigated. High and low temperature Si3N4 protective layers were tested on the CMOS microcircuits and no conclusive improvements in device reliability characteristics were evidenced.

Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

NASA Astrophysics Data System (ADS)

Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

2013-09-01

This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

CMOS Image Sensors for High Speed Applications.

PubMed

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

Design and fabrication of a CMOS-compatible MHP gas sensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Ying; Yu, Jun, E-mail: junyu@dlut.edu.cn; Wu, Hao

2014-03-15

A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperaturemore » in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.« less

Self-Biased 215MHz Magnetoelectric NEMS Resonator for Ultra-Sensitive DC Magnetic Field Detection

NASA Astrophysics Data System (ADS)

Nan, Tianxiang; Hui, Yu; Rinaldi, Matteo; Sun, Nian X.

2013-06-01

High sensitivity magnetoelectric sensors with their electromechanical resonance frequencies < 200 kHz have been recently demonstrated using magnetostrictive/piezoelectric magnetoelectric heterostructures. In this work, we demonstrate a novel magnetoelectric nano-electromechanical systems (NEMS) resonator with an electromechanical resonance frequency of 215 MHz based on an AlN/(FeGaB/Al2O3) × 10 magnetoelectric heterostructure for detecting DC magnetic fields. This magnetoelectric NEMS resonator showed a high quality factor of 735, and strong magnetoelectric coupling with a large voltage tunable sensitivity. The admittance of the magnetoelectric NEMS resonator was very sensitive to DC magnetic fields at its electromechanical resonance, which led to a new detection mechanism for ultra-sensitive self-biased RF NEMS magnetoelectric sensor with a low limit of detection of DC magnetic fields of ~300 picoTelsa. The magnetic/piezoelectric heterostructure based RF NEMS magnetoelectric sensor is compact, power efficient and readily integrated with CMOS technology, which represents a new class of ultra-sensitive magnetometers for DC and low frequency AC magnetic fields.

Spin pumping driven auto-oscillator for phase-encoded logic—device design and material requirements

NASA Astrophysics Data System (ADS)

Rakheja, S.; Kani, N.

2017-05-01

In this work, we propose a spin nano-oscillator (SNO) device where information is encoded in the phase (time-shift) of the output oscillations. The spin current required to set up the oscillations in the device is generated through spin pumping from an input nanomagnet that is precessing at RF frequencies. We discuss the operation of the SNO device, in which either the in-plane (IP) or out-of-plane (OOP) magnetization oscillations are utilized toward implementing ultra-low-power circuits. Using physical models of the nanomagnet dynamics and the spin transport through non-magnetic channels, we quantify the reliability of the SNO device using a "scaling ratio". Material requirements for the nanomagnet and the channel to ensure correct logic functionality are identified using the scaling ratio metric. SNO devices consume (2-5)× lower energy compared to CMOS devices and other spin-based devices with similar device sizes and material parameters. The analytical models presented in this work can be used to optimize the performance and scaling of SNO devices in comparison to CMOS devices at ultra-scaled technology nodes.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

A sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications

PubMed Central

Mercier, Patrick P.; Bandyopadhyay, Saurav; Lysaght, Andrew C.; Stankovic, Konstantina M.; Chandrakasan, Anantha P.

2015-01-01

This paper presents the design of a narrowband transmitter and antenna system that achieves an average power consumption of 78 pW when operating at a duty-cycled data rate of 1 bps. Fabricated in a 0.18 µm CMOS process, the transmitter employs a direct-RF power oscillator topology where a loop antenna acts as a both a radiative and resonant element. The low-complexity single-stage architecture, in combination with aggressive power gating techniques and sizing optimizations, limited the standby power of the transmitter to only 39.7 pW at 0.8 V. Supporting both OOK and FSK modulations at 2.4 GHz, the transmitter consumed as low as 38 pJ/bit at an active-mode data rate of 5 Mbps. The loop antenna and integrated diodes were also used as part of a wireless power transfer receiver in order to kick-start the system power supply during energy harvesting operation. PMID:26246641

An All-Digital Fast Tracking Switching Converter with a Programmable Order Loop Controller for Envelope Tracking RF Power Amplifiers

PubMed Central

Anabtawi, Nijad; Ferzli, Rony; Harmanani, Haidar M.

2017-01-01

This paper presents a step down, switched mode power converter for use in multi-standard envelope tracking radio frequency power amplifiers (RFPA). The converter is based on a programmable order sigma delta modulator that can be configured to operate with either 1st, 2nd, 3rd or 4th order loop filters, eliminating the need for a bulky passive output filter. Output ripple, sideband noise and spectral emission requirements of different wireless standards can be met by configuring the modulator’s filter order and converter’s sampling frequency. The proposed converter is entirely digital and is implemented in 14nm bulk CMOS process for post layout verification. For an input voltage of 3.3V, the converter’s output can be regulated to any voltage level from 0.5V to 2.5V, at a nominal switching frequency of 150MHz. It achieves a maximum efficiency of 94% at 1.5 W output power. PMID:28919657

A Robust High-Performance GPS L1 Receiver with Single-stage Quadrature Redio-Frequency Circuit

NASA Astrophysics Data System (ADS)

Liu, Jianghua; Xu, Weilin; Wan, Qinq; Liu, Tianci

2018-03-01

A low power current reuse single-stage quadrature raido-frequency part (SQRF) is proposed for GPS L1 receiver in 180nm CMOS process. The proposed circuit consists of LNA, Mixer, QVCO, is called the QLMV cell. A two blocks stacked topology is adopted in this design. The parallel QVCO and mixer placed on the top forms the upper stacked block, and the LNA placed on the bottom forms the other stacked block. The two blocks share the current and achieve low power performance. To improve the stability, a float current source is proposed. The float current isolated the local oscillation signal and the input RF signal, which bring the whole circuit robust high-performance. The result shows conversion gain is 34 dB, noise figure is three dB, the phase noise is -110 dBc/Hz at 1MHz and IIP3 is -20 dBm. The proposed circuit dissipated 1.7mW with 1 V supply voltage.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

A CMOS Humidity Sensor for Passive RFID Sensing Applications

PubMed Central

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

A CMOS humidity sensor for passive RFID sensing applications.

PubMed

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-05-16

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

PubMed Central

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.

PubMed

Sporrer, Benjamin; Wu, Lianbo; Bettini, Luca; Vogt, Christian; Reber, Jonas; Marjanovic, Josip; Burger, Thomas; Brunner, David O; Pruessmann, Klaas P; Troster, Gerhard; Huang, Qiuting

2017-12-01

Magnetic resonance imaging (MRI) is among the most important medical imaging modalities. Coil arrays and receivers with high channel counts (16 and more) have to be deployed to obtain the image quality and acquisition speed required by modern clinical protocols. In this paper, we report the theoretical analysis, the system-level design, and the circuit implementation of the first receiver IC (RXIC) for clinical MRI fully integrated in a modern CMOS technology. The dual-channel RXIC sits directly on the sensor coil, thus eliminating any RF cable otherwise required to transport the information out of the magnetic field. The first stage LNA was implemented using a noise-canceling architecture providing a highly reflective input used to decouple the individual channels of the array. Digitization is performed directly on-chip at base-band by means of a delta-sigma modulator, allowing the subsequent optical transmission of data. The presented receiver, implemented in a CMOS technology, is compatible with MRI scanners up to . It reaches sub- noise figure for MRI units and features a dynamic range up to at a power consumption below per channel, with an area occupation of . Mounted on a small-sized printed circuit board (PCB), the receiver IC has been employed in a commercial MRI scanner to acquire in-vivo images matching the quality of traditional systems, demonstrating the first step toward multichannel wearable MRI array coils.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

PubMed Central

López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

PubMed

López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

PubMed Central

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Drop casting of stiffness gradients for chip integration into stretchable substrates

NASA Astrophysics Data System (ADS)

Naserifar, Naser; LeDuc, Philip R.; Fedder, Gary K.

2017-04-01

Stretchable electronics have demonstrated promise within unobtrusive wearable systems in areas such as health monitoring and medical therapy. One significant question is whether it is more advantageous to develop holistic stretchable electronics or to integrate mature CMOS into stretchable electronic substrates where the CMOS process is separated from the mechanical processing steps. A major limitation with integrating CMOS is the dissimilar interface between the soft stretchable and hard CMOS materials. To address this, we developed an approach to pattern an elastomeric polymer layer with spatially varying mechanical properties around CMOS electronics to create a controllable material stiffness gradient. Our experimental approach reveals that modifying the interfaces can increase the strain failure threshold up to 30% and subsequently decreases delamination. The stiffness gradient in the polymer layer provides a safe region for electronic chips to function under a substrate tensile strain up to 150%. These results will have impacts in diverse applications including skin sensors and wearable health monitoring systems.

Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

2018-04-01

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Contour mode resonators with acoustic reflectors

DOEpatents

Olsson, Roy H [Albuquerque, NM; Fleming, James G [Albuquerque, NM; Tuck, Melanie R [Albuquerque, NM

2008-06-10

A microelectromechanical (MEM) resonator is disclosed which has a linear or ring-shaped acoustic resonator suspended above a substrate by an acoustic reflector. The acoustic resonator can be formed with a piezoelectric material (e.g. aluminum nitride, zinc oxide or PZT), or using an electrostatically-actuated material. The acoustic reflector (also termed an acoustic mirror) uses alternating sections of a relatively low acoustic impedance Z.sub.L material and a relatively high acoustic impedance Z.sub.H material to isolate the acoustic resonator from the substrate. The MEM resonator, which can be formed on a silicon substrate with conventional CMOS circuitry, has applications for forming oscillators, rf filters, and acoustic sensors.

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

PubMed

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-11-01

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

PubMed

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

2011-12-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

A safety monitoring system for taxi based on CMOS imager

NASA Astrophysics Data System (ADS)

Liu, Zhi

2005-01-01

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Test results for SEU and SEL immune memory circuits

NASA Technical Reports Server (NTRS)

Wiseman, D.; Canaris, J.; Whitaker, S.; Gambles, J.; Arave, K.; Arave, L.

1993-01-01

Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

Equalizing Si photodetectors fabricated in standard CMOS processes

NASA Astrophysics Data System (ADS)

Guerrero, E.; Aguirre, J.; Sánchez-Azqueta, C.; Royo, G.; Gimeno, C.; Celma, S.

2017-05-01

This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.

Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

NASA Astrophysics Data System (ADS)

Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

2017-06-01

Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

CMOS dot matrix microdisplay

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa. PMID:22303167

Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

PubMed

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

Rf linearity in low dimensional nanowire mosfets

NASA Astrophysics Data System (ADS)

Razavieh, Ali

Ever decreasing cost of electronics due to unique scaling potential of today's VLSI processes such as CMOS technology along with innovations in RF devices, circuits and architectures make wireless communication an un-detachable part of everyday's life. This rapid transition of communication systems toward wireless technologies over last couple of decades resulted in operation of numerous standards within a small frequency window. More traffic in adjacent frequency ranges imposes more constraints on the linearity of RF front-end stages, and increases the need for more effective linearization techniques. Long-established ways to improve linearity in DSM CMOS technology are focused on system level methods which require complex circuit design techniques due to challenges such as nonlinear output conductance, and mobility degradation especially when low supply voltage is a key factor. These constrains have turned more focus toward improvement of linearity at the device level in order to simplify the existing linearization techniques. This dissertation discusses the possibility of employing nanostructures particularly nanowires in order to achieve and improve RF linearity at the device level by making a connection between the electronic transport properties of nanowires and their circuit level RF characteristics (RF linearity). Focus of this work is mainly on transconductance (gm) linearity because of the following reasons: 1) due to good electrostatics, nanowire transistors show fine current saturation at very small supply voltages. Good current saturation minimizes the output conductance nonlinearities. 2) non-linearity due to the gate to source capacitances (Cgs) can also be ignored in today's operating frequencies due to small gate capacitance values. If three criteria: i) operation in the quantum capacitance limit (QCL), ii) one-dimensional (1-D) transport, and iii) operation in the ballistic transport regime are met at the same time, a MOSFET will exhibit an ideal linear Id-Vgs characteristics with a constant gm of which is independent of the choice of channel material when operated under high enough drain voltages. Unique scaling potential of nanowires in terms of body thickness, channel length, and oxide thickness makes nanowire transistors an excellent device structure of choice to operate in 1-D ballistic transport regime in the QCL. A set of guidelines is provided for material parameters and device dimensions for nanowire FETs, which meet the three criteria of i) 1-D transport ii) operation in the QCL iii) ballistic transport, and challenges and limitations of fulfilling any of the above transport conditions from materials point of view are discussed. This work also elaborates how a non-ideal device, one that approaches but does not perfectly fulfill criteria i) through iii), can be analyzed in terms of its linearity performance. In particular the potential of silicon based devices will be discussed in this context, through mixture of experiment and simulation. 1-D transport is successfully achieved in the lab. QCL is simulated through back calculation of the band movement of the transistors in on-state. Quasi-ballistic transport conditions can be achieved by cooling down the samples to 77K. Since, ballistic transport is challenging to achieve for practical channel lengths in today's leading semiconductor device technologies the effect of carrier back-scattering on RF linearity is explored through third order intercept point (IIP3) analysis. These findings show that for the devices which operate in the QCL, while 1-D sub-bands are involved in carrier transport, current linearity is directly related to the nature of the dominant scattering mechanism in the channel, and can be improved by proper choice of channel material in order to enforce a specific scattering mechanism to prevail in the channel. Usually, in semiconductors, the dominant scattering mechanism in the channel is the superposition of different mechanisms. Suitable choice of channel material and bias conditions can magnify the effect of a particular scattering mechanism to achieve higher linearity levels. The closing section of this thesis focuses on InAS due to its potential for high linearity since it has small effective mass and large mean-free-path.

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

PubMed

Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

2012-07-01

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

1.05-GHz CMOS oscillator based on lateral- field-excited piezoelectric AlN contour- mode MEMS resonators.

PubMed

Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca

2010-01-01

This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contourmode resonators. The oscillator shows a phase noise level of -81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-microm complementary metaloxide- semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt 2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications.

Impulse radio ultra wideband wireless transmission of dopamine concentration levels recorded by fast-scan cyclic voltammetry.

PubMed

Ebrazeh, Ali; Bozorgzadeh, Bardia; Mohseni, Pedram

2015-01-01

This paper demonstrates the feasibility of utilizing impulse radio ultra wideband (IR-UWB) signaling technique for reliable, wireless transmission of dopamine concentration levels recorded by fast-scan cyclic voltammetry (FSCV) at a carbon-fiber microelectrode (CFM) to address the problem of elevated data rates in high-channel-count neurochemical monitoring. Utilizing an FSCV-sensing chip fabricated in AMS 0.35μm 2P/4M CMOS, a 3-5-GHz, IR-UWB transceiver (TRX) chip fabricated in TSMC 90nm 1P/9M RF CMOS, and two off-chip, miniature, UWB antennae, wireless transfer of pseudo-random binary sequence (PRBS) data at 50Mbps over a distance of <;1m is first shown with bit-error rates (BER) <; 10(-3). Further, IR-UWB wireless transmission of dopamine concentration levels prerecorded with FSCV at a CFM during flow injection analysis (FIA) is also demonstrated with transmitter (TX) power dissipation of only ~4.4μW from 1.2V, representing two orders of magnitude reduction in TX power consumption compared to that of a conventional frequency-shift-keyed (FSK) link operating at ~433MHz.

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

NASA Astrophysics Data System (ADS)

Kuan, Bao; Xiangning, Fan; Wei, Li; Zhigong, Wang

2013-01-01

This paper reports a wideband passive mixer for direct conversion multi-standard receivers. A brief comparison between current-commutating passive mixers and active mixers is presented. The effect of source and load impedance on the linearity of a mixer is analyzed. Specially, the impact of the input impedance of the transimpedance amplifier (TIA), which acts as the load impedance of a mixer, is investigated in detail. The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology. The circuit is inductorless and can operate over a broad frequency range. On wafer measurements show that, with radio frequency (RF) ranges from 700 MHz to 2.3 GHz, the mixer achieves 21 dB of conversion voltage gain with a -1 dB intermediate frequency (IF) bandwidth of 10 MHz. The measured IIP3 is 9 dBm and the measured double-sideband noise figure (NF) is 10.6 dB at 10 MHz output. The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

CMOS detector arrays in a virtual 10-kilopixel camera for coherent terahertz real-time imaging.

PubMed

Boppel, Sebastian; Lisauskas, Alvydas; Max, Alexander; Krozer, Viktor; Roskos, Hartmut G

2012-02-15

We demonstrate the principle applicability of antenna-coupled complementary metal oxide semiconductor (CMOS) field-effect transistor arrays as cameras for real-time coherent imaging at 591.4 GHz. By scanning a few detectors across the image plane, we synthesize a focal-plane array of 100×100 pixels with an active area of 20×20 mm2, which is applied to imaging in transmission and reflection geometries. Individual detector pixels exhibit a voltage conversion loss of 24 dB and a noise figure of 41 dB for 16 μW of the local oscillator (LO) drive. For object illumination, we use a radio-frequency (RF) source with 432 μW at 590 GHz. Coherent detection is realized by quasioptical superposition of the image and the LO beam with 247 μW. At an effective frame rate of 17 Hz, we achieve a maximum dynamic range of 30 dB in the center of the image and more than 20 dB within a disk of 18 mm diameter. The system has been used for surface reconstruction resolving a height difference in the μm range.

GaN-on-Silicon - Present capabilities and future directions

NASA Astrophysics Data System (ADS)

Boles, Timothy

2018-02-01

Gallium Nitride, in the form of epitaxial HEMT transistors on various substrate materials, is the newest and most promising semiconductor technology for high performance devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-Silicon based devices and MMIC's which enable both state-of-the-art high frequency functionality and the ability to scale production into large wafer diameter CMOS foundries. The design and development of GaN-on-Silicon structures and devices will be presented beginning with the basic material parameters, growth of the required epitaxial construction, and leading to the fundamental operational theory of high frequency, high power HEMTs. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including inherent frequency limiting transit time analysis, required impedance transformations, internal and external parasitic reactance, thermal impedance optimization, and challenges improved by full integration into monolithic MMICs. Lastly, future directions for implementing GaN-on-Silicon into mainstream CMOS silicon semiconductor technologies will be discussed.

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

The design and performance of a 2.5-GHz telecommand link for wireless biomedical monitoring.

PubMed

Crumley, G C; Evans, N E; Scanlon, W G; Burns, J B; Trouton, T G

2000-12-01

This paper details the implementation and operational performance of a minimum-power 2.45-GHz pulse receiver and a companion on-off keyed transmitter for use in a semi-active, duplex RF biomedical transponder. A 50-ohm microstrip stub-matched zero-bias diode detector forms the heart of a body-worn receiver that has a (CMOS baseband amplifier consuming 20 microA from +3 V and achieves a tangential sensitivity of -53 dBm. The base transmitter generates 0.5 W of peak RF output power into 50 ohms. Both linear and right-hand circularly polarized Tx-Rx antenna sets were employed in system reliability trials carried out in a hospital Coronary Care Unit. For transmitting antenna heights between 0.3 and 2.2 m above floor level, transponder interrogations were 95% reliable within the 67-m2 area of the ward, falling to an average of 46% in the surrounding rooms and corridors. Overall, the circular antenna set gave the higher reliability and lower propagation power decay index.

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

NASA Astrophysics Data System (ADS)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

2009-01-01

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

CMOS-compatible photonic devices for single-photon generation

NASA Astrophysics Data System (ADS)

Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

2016-09-01

Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Microactuateur electrothermique bistable: Etude d'implementation avec une technologie standard CMOS

NASA Astrophysics Data System (ADS)

Ressejac, Isabelle

The general objective of this Ph.D. thesis was to study the implementation of a new type of eletrothermal microactuator. This actuator presents the advantages to be bistable and fabricated in a standard CMOS process, allowing the integration of a microelectronics addressing circuit on the same substrate. Experimental research work, presented in this thesis, relate to the different steps carried out in order to implement this CMOS MEMS device: its theoretical conception, its fabrication with a standard CMOS technology, its micromachining as a post-process, its characterization and its electro-thermo-mechanical modeling. The device was designed and fabricated by using Mitel 1,5 mum CMOS technology and the Can-MEMS service which are both available via the Canadian Microelectronics Corporation. Fabricated monolithically within a standard CMOS process, our microactuator is suitable for large-scale integration due to its small dimensions (length ˜1000 mum and width ˜150 mum). It constitutes the basic component of a N by N matrix controlled by a microelectronic addressing system built on the same substrate. Initially, only one micromachining technique (involving TMAH) was used, and long etching times (>9 h) were requires} in order to release the microstructures. However, the passivation layer from the CMOS process could protect the underlying metal from the TMAH for a sufficient time (only ˜1--2 h). Consequently, we had to develop a micromachining strategy with shorter etching times to allow the complete release of the microstructures without damaging them. Post-processing begins with deposition (by sputtering) of a platinum layer intended to protect the abutment from subsequent etching. Our micromachining strategy is mainly based on the use of a hybrid etching process starting with a first anisotropic TMAH etching followed by a XeF2 isotropic etching. After micromachining, the released microactuator has a significant initial deflection with its tip reaching a height up to a hundred times higher than its thickness. This natural deflection results from the relaxation of internal stresses inside the thin films which are part of the microactuator. These internal stresses are intrinsics to the host CMOS process. We have developed a model of the microactuator's initial deflection using mechanical properties of thin films and dimensions of the structure. Actuation experiments were performed in order to characterize the deflection of the microactuator with respect to the heating of the bilayers (separately and together). We have developed a thermal actuation analytical model for an n-layers multimorph structure, which takes into account the initial deflection resulting from the relaxation of stresses as well as the deflection due to the temperature increase during the electrothermal activation of the bilayers. (Abstract shortened by UMI.)

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm process with a high resistivity epitaxial layer

NASA Astrophysics Data System (ADS)

Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

2013-12-01

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq /cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μm CMOS process for the ALICE ITS upgrade.

High Electron Mobility Transistor Structures on Sapphire Substrates Using CMOS Compatible Processing Techniques

NASA Technical Reports Server (NTRS)

Mueller, Carl; Alterovitz, Samuel; Croke, Edward; Ponchak, George

2004-01-01

System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced electron mobility as well as the processes that limit mobility, and will be presented.

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

Automatic arc welding of propulsion system tubing in close proximity to sensitive electronic devices

NASA Technical Reports Server (NTRS)

Lumsden, J. M.; Whittlesey, A. C.

1981-01-01

The planned final assembly of the Galileo spacecraft propulsion system tubing, which involves welding in close proximity to sensitive electronics, raised significant concerns about the effects of electromagnetic coupling of weld energy on CMOS and other sensitive integrated circuits. A test program was established to assess the potential of an orbital arc welder and an RF-induction brazing machine to damage sensitive electronic equipment. Test parameters were varied to assess the effectiveness of typical transient suppression practices such as grounding, bonding, and shielding. A technique was developed to calibrate the hazard levels at the victim-circuit location; this technique is described along with the results and conclusions of the test program.

Microsystem technologies for ophtalmological implants

NASA Astrophysics Data System (ADS)

Mokwa, Wilfried

2003-01-01

Due to the low power consumption CMOS electronics is ideal for the use in implanted systems. This paper presents two projects working on ophthalmological implants. Both systems are powered by an external RF-field. One system has been developed to measure the intraocular pressure continuously which is important for the therapy of glaucoma patients. The system consists of a micro coil and an integrated pressure transponder chip built into an artificial soft lens. A second example is a very complex system for epiretinal stimulation of the nerve cells of the retina. With such a system it might be possible to give blind people that are suffering from retinitis pigmentosa some visual contact to their surrounding.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly.

PubMed

Gall, Oren Z; Zhong, Xiahua; Schulman, Daniel S; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S

2017-06-30

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO 2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly

NASA Astrophysics Data System (ADS)

Gall, Oren Z.; Zhong, Xiahua; Schulman, Daniel S.; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S.

2017-06-01

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Theoretical performance analysis for CMOS based high resolution detectors.

PubMed

Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

2013-03-06

High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

Improved Space Object Observation Techniques Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

2013-08-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Demonstration of a wireless driven MEMS pond skater that uses EWOD technology

NASA Astrophysics Data System (ADS)

Mita, Y.; Li, Y.; Kubota, M.; Morishita, S.; Parkes, W.; Haworth, L. I.; Flynn, B. W.; Terry, J. G.; Tang, T.-B.; Ruthven, A. D.; Smith, S.; Walton, A. J.

2009-07-01

A silicon swimming robot or pond skating device has been demonstrated. It floats on liquid surfaces using surface tension and is capable of movement using electrowetting on dielectric (EWOD) based propulsion. Its dimensions are 6 × 9 mm and the driving mechanism involves first trapping air bubbles within the liquid onto the hydrophobic surface of the device. The air bubbles are then moved using EWOD, which provides the propulsion. The device employs a recently reported TaO EWOD technology enabling a driving voltage of ≈15 V, which is low enough for RF power transmission, thus facilitating wire-free movement. A wired version has been measured to move 1.35 mm in 168 ms (a speed of 8 mm s -1). This low voltage-EWOD (<15 V) device, fabricated using a CMOS compatible process, is believed to be the world's smallest swimming MEMS device that has no mechanical moving parts. The paper also reports results of EWOD droplet operation driven by wireless power transmission and demonstrates that such a wireless design can be successfully mounted on a floating EWOD device to produce movement.

A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform

NASA Astrophysics Data System (ADS)

Kim, Jeonghun; Kim, Suki; Baek, Kwang-Hyun

This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30mm2 in 0.18µm CMOS, and the worst-case current of the total chip is 54mA.

A Hybrid CMOS-Memristor Neuromorphic Synapse.

PubMed

Azghadi, Mostafa Rahimi; Linares-Barranco, Bernabe; Abbott, Derek; Leong, Philip H W

2017-04-01

Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre- and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as [Formula: see text] in a [Formula: see text] process-this represents a factor of ten reduction in area with respect to prior CMOS art. The new design is integrated with silicon neurons in a crossbar array structure amenable to large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent learning features. These systems are emerging for deployment in various applications ranging from basic neuroscience research, to pattern recognition, to Brain-Machine-Interfaces.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Efficient demodulation scheme for rolling-shutter-patterning of CMOS image sensor based visible light communications.

PubMed

Chen, Chia-Wei; Chow, Chi-Wai; Liu, Yang; Yeh, Chien-Hung

2017-10-02

Recently even the low-end mobile-phones are equipped with a high-resolution complementary-metal-oxide-semiconductor (CMOS) image sensor. This motivates using a CMOS image sensor for visible light communication (VLC). Here we propose and demonstrate an efficient demodulation scheme to synchronize and demodulate the rolling shutter pattern in image sensor based VLC. The implementation algorithm is discussed. The bit-error-rate (BER) performance and processing latency are evaluated and compared with other thresholding schemes.

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

PubMed

El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed S; Deen, M Jamal

2015-05-07

The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

Design of CMOS imaging system based on FPGA

NASA Astrophysics Data System (ADS)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

PubMed

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A CMOS image sensor with stacked photodiodes for lensless observation system of digital enzyme-linked immunosorbent assay

NASA Astrophysics Data System (ADS)

Takehara, Hironari; Miyazawa, Kazuya; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Kim, Soo Hyeon; Iino, Ryota; Noji, Hiroyuki; Ohta, Jun

2014-01-01

A CMOS image sensor with stacked photodiodes was fabricated using 0.18 µm mixed signal CMOS process technology. Two photodiodes were stacked at the same position of each pixel of the CMOS image sensor. The stacked photodiodes consist of shallow high-concentration N-type layer (N+), P-type well (PW), deep N-type well (DNW), and P-type substrate (P-sub). PW and P-sub were shorted to ground. By monitoring the voltage of N+ and DNW individually, we can observe two monochromatic colors simultaneously without using any color filters. The CMOS image sensor is suitable for fluorescence imaging, especially contact imaging such as a lensless observation system of digital enzyme-linked immunosorbent assay (ELISA). Since the fluorescence increases with time in digital ELISA, it is possible to observe fluorescence accurately by calculating the difference from the initial relation between the pixel values for both photodiodes.

Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

PubMed

Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

2015-02-01

An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

Review of the Reference Dose and Reference Concentration Processes Document

EPA Pesticide Factsheets

Summarizes the review and deliberations of the Risk Assessment Forum’s RfD/RfC Technical Panel and its recommendations for improvements in oral referencedose/inhalation reference concentration (RfD/RfC) process.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

Development of p-type oxide semiconductors based on tin oxide and its alloys: application to thin film transistors

NASA Astrophysics Data System (ADS)

Barros, Ana Raquel Xarouco de

In spite of the recent p-type oxide TFTs developments based on SnOx and CuxO, the results achieved so far refer to devices processed at high temperatures and are limited by a low hole mobility and a low On-Off ratio and still there is no report on p-type oxide TFTs with performance similar to n-type, especially when comparing their field-effect mobility values, which are at least one order of magnitude higher on n-type oxide TFTs. Achieving high performance p-type oxide TFTs will definitely promote a new era for electronics in rigid and flexible substrates, away from silicon. None of the few reported p-channel oxide TFTs is suitable for practical applications, which demand significant improvements in the device engineering to meet the real-world electronic requirements, where low processing temperatures together with high mobility and high On-Off ratio are required for TFT and CMOS applications. The present thesis focuses on the study and optimization of p-type thin film transistors based on oxide semiconductors deposited by r.f. magnetron sputtering without intentional substrate heating. In this work several p-type oxide semiconductors were studied and optimized based on undoped tin oxide, Cu-doped SnOx and In-doped SnO2.

A MEMS-based, wireless, biometric-like security system

NASA Astrophysics Data System (ADS)

Cross, Joshua D.; Schneiter, John L.; Leiby, Grant A.; McCarter, Steven; Smith, Jeremiah; Budka, Thomas P.

2010-04-01

We present a system for secure identification applications that is based upon biometric-like MEMS chips. The MEMS chips have unique frequency signatures resulting from fabrication process variations. The MEMS chips possess something analogous to a "voiceprint". The chips are vacuum encapsulated, rugged, and suitable for low-cost, highvolume mass production. Furthermore, the fabrication process is fully integrated with standard CMOS fabrication methods. One is able to operate the MEMS-based identification system similarly to a conventional RFID system: the reader (essentially a custom network analyzer) detects the power reflected across a frequency spectrum from a MEMS chip in its vicinity. We demonstrate prototype "tags" - MEMS chips placed on a credit card-like substrate - to show how the system could be used in standard identification or authentication applications. We have integrated power scavenging to provide DC bias for the MEMS chips through the use of a 915 MHz source in the reader and a RF-DC conversion circuit on the tag. The system enables a high level of protection against typical RFID hacking attacks. There is no need for signal encryption, so back-end infrastructure is minimal. We believe this system would make a viable low-cost, high-security system for a variety of identification and authentication applications.

An accurate model for predicting high frequency noise of nanoscale NMOS SOI transistors

NASA Astrophysics Data System (ADS)

Shen, Yanfei; Cui, Jie; Mohammadi, Saeed

2017-05-01

A nonlinear and scalable model suitable for predicting high frequency noise of N-type Metal Oxide Semiconductor (NMOS) transistors is presented. The model is developed for a commercial 45 nm CMOS SOI technology and its accuracy is validated through comparison with measured performance of a microwave low noise amplifier. The model employs the virtual source nonlinear core and adds parasitic elements to accurately simulate the RF behavior of multi-finger NMOS transistors up to 40 GHz. For the first time, the traditional long-channel thermal noise model is supplemented with an injection noise model to accurately represent the noise behavior of these short-channel transistors up to 26 GHz. The developed model is simple and easy to extract, yet very accurate.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

A single-channel implantable microstimulator for functional neuromuscular stimulation.

PubMed

Ziaie, B; Nardin, M D; Coghlan, A R; Najafi, K

1997-10-01

This paper describes a single-channel implantable microstimulator for functional neuromuscular stimulation. This device measures 2 x 2 x 10 mm3 and can be inserted into paralyzed muscle groups by expulsion from a hypodermic needle. Power and data to the device are supplied from outside by RF telemetry using an amplitude-modulated 2-MHz RF carrier generated using a high-efficiency class-E transmitter. The transmitted signal carries a 5-b address which selects one of the 32 possible microstimulators. The selected device then delivers up to 2 microC of charge store in a tantalum chip capacitor for up to 200 microseconds (10 mA) into loads of < 800 omega through a high-current thin-film iridium-oxide (IrOx) electrode (approximately 0.3 mm2 in area). A bi-CMOS receiver circuitry is used to: generate two regulated voltage supplies (4.5 and 9 V), recover a 2-MHz clock from the carrier, demodulate the address code, and activate the output current delivery circuitry upon the reception of an external command. The overall power dissipation of the receiver circuitry is 45-55 mW. The implant is hermetically packaged using a custom-made glass capsule.

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

PubMed

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

PubMed

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Radiation imaging with a new scintillator and a CMOS camera

NASA Astrophysics Data System (ADS)

Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

2014-07-01

A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

PubMed

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

Verification of a SEU model for advanced 1-micron CMOS structures using heavy ions

NASA Technical Reports Server (NTRS)

Cable, J. S.; Carter, J. R.; Witteles, A. A.

1986-01-01

Modeling and test results are reported for 1 micron CMOS circuits. Analytical predictions are correlated with experimental data, and sensitivities to process and design variations are discussed. Unique features involved in predicting the SEU performance of these devices are described. The results show that the critical charge for upset exhibits a strong dependence on pulse width for very fast devices, and upset predictions must factor in the pulse shape. Acceptable SEU error rates can be achieved for a 1 micron bulk CMOS process. A thin retrograde well provides complete SEU immunity for N channel hits at normal incidence angle. Source interconnect resistance can be important parameter in determining upset rates, and Cf-252 testing can be a valuable tool for cost-effective SEU testing.

Mk x Nk gated CMOS imager

NASA Astrophysics Data System (ADS)

Janesick, James; Elliott, Tom; Andrews, James; Tower, John; Bell, Perry; Teruya, Alan; Kimbrough, Joe; Bishop, Jeanne

2014-09-01

Our paper will describe a recently designed Mk x Nk x 10 um pixel CMOS gated imager intended to be first employed at the LLNL National Ignition Facility (NIF). Fabrication involves stitching MxN 1024x1024x10 um pixel blocks together into a monolithic imager (where M = 1, 2, . .10 and N = 1, 2, . . 10). The imager has been designed for either NMOS or PMOS pixel fabrication using a base 0.18 um/3.3V CMOS process. Details behind the design are discussed with emphasis on a custom global reset feature which erases the imager of unwanted charge in ~1 us during the fusion ignition process followed by an exposure to obtain useful data. Performance data generated by prototype imagers designed similar to the Mk x Nk sensor is presented.

A back-illuminated megapixel CMOS image sensor

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Analog CMOS design for optical coherence tomography signal detection and processing.

PubMed

Xu, Wei; Mathine, David L; Barton, Jennifer K

2008-02-01

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

A CMOS VLSI IC for Real-Time Opto-Electronic Two-Dimensional Histogram Generation

DTIC Science & Technology

1993-12-01

large scale integration) design; MAGIC ; CMOS; optics; image processing; 93 16. PRICE CODE 17. SECURITY CLASSIFICATION 18. SECURITY CLASSIFICATiON 19...1. Sun SPARCstation ............. .............. 6 2. Magic .................. ................... 6 a. Peg ................. .................. 7 b...38 v APPENDIX B. MAGIC CELL LAYOUTS .... ............ .. 39 APPENDIX C: SIMULATION DATA ....... ............. .. 56 A. FINITE STATE MACHINE

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

NASA Astrophysics Data System (ADS)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Quantitative optical metrology with CMOS cameras

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Kolenovic, Ervin; Ferguson, Curtis F.

2004-08-01

Recent advances in laser technology, optical sensing, and computer processing of data, have lead to the development of advanced quantitative optical metrology techniques for high accuracy measurements of absolute shapes and deformations of objects. These techniques provide noninvasive, remote, and full field of view information about the objects of interest. The information obtained relates to changes in shape and/or size of the objects, characterizes anomalies, and provides tools to enhance fabrication processes. Factors that influence selection and applicability of an optical technique include the required sensitivity, accuracy, and precision that are necessary for a particular application. In this paper, sensitivity, accuracy, and precision characteristics in quantitative optical metrology techniques, and specifically in optoelectronic holography (OEH) based on CMOS cameras, are discussed. Sensitivity, accuracy, and precision are investigated with the aid of National Institute of Standards and Technology (NIST) traceable gauges, demonstrating the applicability of CMOS cameras in quantitative optical metrology techniques. It is shown that the advanced nature of CMOS technology can be applied to challenging engineering applications, including the study of rapidly evolving phenomena occurring in MEMS and micromechatronics.

Imaging system design and image interpolation based on CMOS image sensor

NASA Astrophysics Data System (ADS)

Li, Yu-feng; Liang, Fei; Guo, Rui

2009-11-01

An image acquisition system is introduced, which consists of a color CMOS image sensor (OV9620), SRAM (CY62148), CPLD (EPM7128AE) and DSP (TMS320VC5509A). The CPLD implements the logic and timing control to the system. SRAM stores the image data, and DSP controls the image acquisition system through the SCCB (Omni Vision Serial Camera Control Bus). The timing sequence of the CMOS image sensor OV9620 is analyzed. The imaging part and the high speed image data memory unit are designed. The hardware and software design of the image acquisition and processing system is given. CMOS digital cameras use color filter arrays to sample different spectral components, such as red, green, and blue. At the location of each pixel only one color sample is taken, and the other colors must be interpolated from neighboring samples. We use the edge-oriented adaptive interpolation algorithm for the edge pixels and bilinear interpolation algorithm for the non-edge pixels to improve the visual quality of the interpolated images. This method can get high processing speed, decrease the computational complexity, and effectively preserve the image edges.

Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

NASA Astrophysics Data System (ADS)

Zhang, L.; Fu, M.; Zhang, Y.; Yan, W.; Wang, M.

2017-01-01

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm2.

USAF Logistics Process Optimization Study for the Aircraft Asset Sustainment Process. Volume 1.

DTIC Science & Technology

1998-12-31

solely to have a record that could be matched with the CMOS receipt data. (This problem is caused by DLA systems that currently do not populate CMOS with...unable to obtain passwords to the Depot D035 systems. Figure 16 shows daily savings as of 30 September 1998 (current time frame ) and projects savings...Engineering, modeling, and systems/software development company LAN Local Area Network LFA Large Frame Aircraft LMA Logistics Management Agency LMR

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

A Computationally Efficient Visual Saliency Algorithm Suitable for an Analog CMOS Implementation.

PubMed

D'Angelo, Robert; Wood, Richard; Lowry, Nathan; Freifeld, Geremy; Huang, Haiyao; Salthouse, Christopher D; Hollosi, Brent; Muresan, Matthew; Uy, Wes; Tran, Nhut; Chery, Armand; Poppe, Dorothy C; Sonkusale, Sameer

2018-06-27

Computer vision algorithms are often limited in their application by the large amount of data that must be processed. Mammalian vision systems mitigate this high bandwidth requirement by prioritizing certain regions of the visual field with neural circuits that select the most salient regions. This work introduces a novel and computationally efficient visual saliency algorithm for performing this neuromorphic attention-based data reduction. The proposed algorithm has the added advantage that it is compatible with an analog CMOS design while still achieving comparable performance to existing state-of-the-art saliency algorithms. This compatibility allows for direct integration with the analog-to-digital conversion circuitry present in CMOS image sensors. This integration leads to power savings in the converter by quantizing only the salient pixels. Further system-level power savings are gained by reducing the amount of data that must be transmitted and processed in the digital domain. The analog CMOS compatible formulation relies on a pulse width (i.e., time mode) encoding of the pixel data that is compatible with pulse-mode imagers and slope based converters often used in imager designs. This letter begins by discussing this time-mode encoding for implementing neuromorphic architectures. Next, the proposed algorithm is derived. Hardware-oriented optimizations and modifications to this algorithm are proposed and discussed. Next, a metric for quantifying saliency accuracy is proposed, and simulation results of this metric are presented. Finally, an analog synthesis approach for a time-mode architecture is outlined, and postsynthesis transistor-level simulations that demonstrate functionality of an implementation in a modern CMOS process are discussed.

Study of RF breakdown and multipacting in accelerator components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pande, Manjiri; Singh, P., E-mail: manjiri@barc.gov.in, E-mail: psingh@barc.gov.in

2014-07-01

Radio frequency (RF) structures that are part of accelerators and energy sources, operate with sinusoidally varying electromagnetic fields under high RF energy. Here, RF breakdown and multipacting take place in RF structures and limit their performance. Electron field emission processes in a RF structure are precursors for breakdown processes. RF breakdown is a major phenomena affecting and causing the irreversible damage to RF structures. Breakdown rate and the damage induced by the breakdowns are its important properties. The damage is related to power absorbed during breakdown, while the breakdown rate is determined by the amplitudes of surface electric and magneticmore » fields, geometry, metal surface preparation and conditioning history. It limits working power and produces irreversible surface damage. The breakdown limit depends on the RF circuit, structure geometry, RF frequency, input RF power, pulse width, materials used, surface processing technique and surface electric and magnetic fields. Multipactor (MP) is a low power, electron multiplication based resonance breakdown phenomenon in vacuum and is often observed in RF structures. A multipactor discharge is undesirable, as it can create a reactive component that detunes the resonant cavities and components, generates noise in communication system and induces gas desorption from the conductor surfaces. In RF structures, certain conditions are required to generate multipacting. (author)« less

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

PubMed

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

A CMOS current-mode log(x) and log(1/x) functions generator

NASA Astrophysics Data System (ADS)

Al-Absi, Munir A.; Al-Tamimi, Karama M.

2014-08-01

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

High-performance, mechanically flexible, and vertically integrated 3D carbon nanotube and InGaZnO complementary circuits with a temperature sensor.

PubMed

Honda, Wataru; Harada, Shingo; Ishida, Shohei; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-08-26

A vertically integrated inorganic-based flexible complementary metal-oxide-semiconductor (CMOS) inverter with a temperature sensor with a high inverter gain of ≈50 and a low power consumption of <7 nW mm(-1) is demonstrated using a layer-by-layer assembly process. In addition, the negligible influence of the mechanical flexibility on the performance of the CMOS inverter and the temperature dependence of the CMOS inverter characteristics are discussed. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The processed isoform of the translation termination factor eRF3 localizes to the nucleus to interact with the ARF tumor suppressor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hashimoto, Yoshifumi; Kumagai, Naomichi; Hosoda, Nao

2014-03-14

Highlights: • So far, eRF3 has been thought to function exclusively in the cytoplasm. • eRF3 is a nucleo-cutoplasmic shuttling protein. • eRF3 has a leptomycin-sensitive nuclear export signal (NES). • Removal of NES by proteolytic cleavage allows eRF3 to translocate to the nucleus. • The processed eRF3 (p-eRF3) interacts with a nuclear tumor suppressor ARF. - Abstract: The eukaryotic releasing factor eRF3 is a multifunctional protein that plays pivotal roles in translation termination as well as the initiation of mRNA decay. eRF3 also functions in the regulation of apoptosis; eRF3 is cleaved at Ala73 by an as yet unidentifiedmore » protease into processed isoform of eRF3 (p-eRF3), which interacts with the inhibitors of apoptosis proteins (IAPs). The binding of p-eRF3 with IAPs leads to the release of active caspases from IAPs, which promotes apoptosis. Although full-length eRF3 is localized exclusively in the cytoplasm, p-eRF3 localizes in the nucleus as well as the cytoplasm. We here focused on the role of p-eRF3 in the nucleus. We identified leptomycin-sensitive nuclear export signal (NES) at amino acid residues 61–71 immediately upstream of the cleavage site Ala73. Thus, the proteolytic cleavage of eRF3 into p-eRF3 leads to release an amino-terminal fragment containing NES to allow the relocalization of eRF3 into the nucleus. Consistent with this, p-eRF3 more strongly interacted with the nuclear ARF tumor suppressor than full-length eRF3. These results suggest that while p-eRF3 interacts with IAPs to promote apoptosis in the cytoplasm, p-eRF3 also has some roles in regulating cell death in the nucleus.« less

A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

NASA Astrophysics Data System (ADS)

Moradi, Behzad; Mirzaei, Abdolreza

2016-11-01

A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

PubMed Central

Wei, Liping.; Doughan, Samer.; Han, Yi.; DaCosta, Matthew V.; Krull, Ulrich J.; Ho, Derek.

2014-01-01

Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies. PMID:25211198

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology.

PubMed

Llobet, J; Rius, G; Chuquitarqui, A; Borrisé, X; Koops, R; van Veghel, M; Perez-Murano, F

2018-04-02

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

NASA Astrophysics Data System (ADS)

Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

2018-04-01

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

A comprehensive model on field-effect pnpn devices (Z2-FET)

NASA Astrophysics Data System (ADS)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

Evaluation of electron beam stabilization for ion implant processing

NASA Astrophysics Data System (ADS)

Buffat, Stephen J.; Kickel, Bee; Philipps, B.; Adams, J.; Ross, Matthew F.; Minter, Jason P.; Marlowe, Trey; Wong, Selmer S.

1999-06-01

With the integration of high energy ion implant processes into volume CMOS manufacturing, the need for thick resist stabilization to achieve a stable ion implant process is critical. With new photoresist characteristics, new implant end station characteristics arise. The resist outgassing needs to be addressed as well as the implant profile to ensure that the dosage is correct and the implant angle does not interfere with other underlying features. This study compares conventional deep-UV/thermal with electron beam stabilization. The electron beam system used in this study utilizes a flood electron source and is a non-thermal process. These stabilization techniques are applied to a MeV ion implant process in a CMOS production process flow.

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Magnan, Pierre; Bernard, Frédéric; Rolland, Guy; Saint-Pé, Olivier; Huger, Nicolas; Corbière, Franck

2008-02-01

We present here a study on both CMOS sensors and elementary structures (photodiodes and in-pixel MOSFETs) manufactured in a deep submicron process dedicated to imaging. We designed a test chip made of one 128×128-3T-pixel array with 10 μm pitch and more than 120 isolated test structures including photodiodes and MOSFETs with various implants and different sizes. All these devices were exposed to ionizing radiation up to 100 krad and their responses were correlated to identify the CMOS sensor weaknesses. Characterizations in darkness and under illumination demonstrated that dark current increase is the major sensor degradation. Shallow trench isolation was identified to be responsible for this degradation as it increases the number of generation centers in photodiode depletion regions. Consequences on hardness assurance and hardening-by-design are discussed.

Perception of shapes targeting local and global processes in autism spectrum disorders.

PubMed

Grinter, Emma J; Maybery, Murray T; Pellicano, Elizabeth; Badcock, Johanna C; Badcock, David R

2010-06-01

Several researchers have found evidence for impaired global processing in the dorsal visual stream in individuals with autism spectrum disorders (ASDs). However, support for a similar pattern of visual processing in the ventral visual stream is less consistent. Critical to resolving the inconsistency is the assessment of local and global form processing ability. Within the visual domain, radial frequency (RF) patterns - shapes formed by sinusoidally varying the radius of a circle to add 'bumps' of a certain number to a circle - can be used to examine local and global form perception. Typically developing children and children with an ASD discriminated between circles and RF patterns that are processed either locally (RF24) or globally (RF3). Children with an ASD required greater shape deformation to identify RF3 shapes compared to typically developing children, consistent with difficulty in global processing in the ventral stream. No group difference was observed for RF24 shapes, suggesting intact local ventral-stream processing. These outcomes support the position that a deficit in global visual processing is present in ASDs, consistent with the notion of Weak Central Coherence.

A low-noise delta-sigma phase modulator for polar transmitters.

PubMed

Zhou, Bo

2014-01-01

A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μ m CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of -104 dBc/Hz and -120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively.

Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

NASA Technical Reports Server (NTRS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-01-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

NASA Astrophysics Data System (ADS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-10-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders - from Optical Triangulation to the Automotive Field.

PubMed

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-03-13

With their significant features, the applications of complementary metal-oxidesemiconductor (CMOS) image sensors covers a very extensive range, from industrialautomation to traffic applications such as aiming systems, blind guidance, active/passiverange finders, etc. In this paper CMOS image sensor-based active and passive rangefinders are presented. The measurement scheme of the proposed active/passive rangefinders is based on a simple triangulation method. The designed range finders chieflyconsist of a CMOS image sensor and some light sources such as lasers or LEDs. Theimplementation cost of our range finders is quite low. Image processing software to adjustthe exposure time (ET) of the CMOS image sensor to enhance the performance oftriangulation-based range finders was also developed. An extensive series of experimentswere conducted to evaluate the performance of the designed range finders. From theexperimental results, the distance measurement resolutions achieved by the active rangefinder and the passive range finder can be better than 0.6% and 0.25% within themeasurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests onapplications of the developed CMOS image sensor-based range finders to the automotivefield were also conducted. The experimental results demonstrated that our range finders arewell-suited for distance measurements in this field.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

NASA Astrophysics Data System (ADS)

Schatz, A.; Pantel, D.; Hanemann, T.

2017-09-01

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

PubMed Central

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

Attentional gating models of object substitution masking.

PubMed

Põder, Endel

2013-11-01

Di Lollo, Enns, and Rensink (2000) proposed the computational model of object substitution (CMOS) to explain their experimental results with sparse visual maskers. This model supposedly is based on reentrant hypotheses testing in the visual system, and the modeled experiments are believed to demonstrate these reentrant processes in human vision. In this study, I analyze the main assumptions of this model. I argue that CMOS is a version of the attentional gating model and that its relationship with reentrant processing is rather illusory. The fit of this model to the data indicates that reentrant hypotheses testing is not necessary for the explanation of object substitution masking (OSM). Further, the original CMOS cannot predict some important aspects of the experimental data. I test 2 new models incorporating an unselective processing (divided attention) stage; these models are more consistent with data from OSM experiments. My modeling shows that the apparent complexity of OSM can be reduced to a few simple and well-known mechanisms of perception and memory. PsycINFO Database Record (c) 2013 APA, all rights reserved.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique

PubMed Central

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique.

PubMed

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

PubMed

Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

2016-02-01

Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications.

Design and simulation of multi-color infrared CMOS metamaterial absorbers

NASA Astrophysics Data System (ADS)

Cheng, Zhengxi; Chen, Yongping; Ma, Bin

2016-05-01

Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Embedded CMOS basecalling for nanopore DNA sequencing.

PubMed

Chengjie Wang; Junli Zheng; Magierowski, Sebastian; Ghafar-Zadeh, Ebrahim

2016-08-01

DNA sequencing based on nanopore sensors is now entering the marketplace. The ability to interface this technology to established CMOS microelectronics promises significant improvements in functionality and miniaturization. Among the key functions to benefit from this interface will be basecalling, the conversion of raw electronic molecular signatures to nucleotide sequence predictions. This paper presents the design and performance potential of custom CMOS base-callers embedded alongside nanopore sensors. A basecalliing architecture implemented in 32-nm technology is discussed with the ability to process the equivalent of 20 human genomes per day in real-time at a power density of 5 W/cm2 assuming a 3-mer nanopore sensor.

A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback

NASA Astrophysics Data System (ADS)

Huang, Zhangcai; Jiang, Minglu; Inoue, Yasuaki

Analog multipliers are one of the most important building blocks in analog signal processing circuits. The performance with high linearity and wide input range is usually required for analog four-quadrant multipliers in most applications. Therefore, a highly linear and wide input range four-quadrant CMOS analog multiplier using active feedback is proposed in this paper. Firstly, a novel configuration of four-quadrant multiplier cell is presented. Its input dynamic range and linearity are improved significantly by adding two resistors compared with the conventional structure. Then based on the proposed multiplier cell configuration, a four-quadrant CMOS analog multiplier with active feedback technique is implemented by two operational amplifiers. Because of both the proposed multiplier cell and active feedback technique, the proposed multiplier achieves a much wider input range with higher linearity than conventional structures. The proposed multiplier was fabricated by a 0.6µm CMOS process. Experimental results show that the input range of the proposed multiplier can be up to 5.6Vpp with 0.159% linearity error on VX and 4.8Vpp with 0.51% linearity error on VY for ±2.5V power supply voltages, respectively.

Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

NASA Astrophysics Data System (ADS)

Zhang, Ying; Zhu, Hongbo; Zhang, Liang; Fu, Min

2016-09-01

The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q / C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18 μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

Label-free CMOS bio sensor with on-chip noise reduction scheme for real-time quantitative monitoring of biomolecules.

PubMed

Seong-Jin Kim; Euisik Yoon

2012-06-01

We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate

PubMed Central

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 μm UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is −42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz–10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 μA, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

Radio-Frequency Applications for Food Processing and Safety.

PubMed

Jiao, Yang; Tang, Juming; Wang, Yifen; Koral, Tony L

2018-03-25

Radio-frequency (RF) heating, as a thermal-processing technology, has been extending its applications in the food industry. Although RF has shown some unique advantages over conventional methods in industrial drying and frozen food thawing, more research is needed to make it applicable for food safety applications because of its complex heating mechanism. This review provides comprehensive information regarding RF-heating history, mechanism, fundamentals, and applications that have already been fully developed or are still under research. The application of mathematical modeling as a useful tool in RF food processing is also reviewed in detail. At the end of the review, we summarize the active research groups in the RF food thermal-processing field, and address the current problems that still need to be overcome.

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks.

PubMed

Hou, Bing; Chen, Hua; Wang, Zhiyu; Mo, Jiongjiong; Chen, Junli; Yu, Faxin; Wang, Wenbo

2017-01-24

In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm² (1.2 mm² including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of -60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.

A Low-Cost CMOS Programmable Temperature Switch

PubMed Central

Li, Yunlong; Wu, Nanjian

2008-01-01

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis. PMID:27879871

Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

NASA Technical Reports Server (NTRS)

Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

2002-01-01

We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

Smart CMOS image sensor for lightning detection and imaging.

PubMed

Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

Monolithic optical phased-array transceiver in a standard SOI CMOS process.

PubMed

Abediasl, Hooman; Hashemi, Hossein

2015-03-09

Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

High-speed bipolar phototransistors in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Zimmermann, H

2013-03-01

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm 2 and 100×100 μm 2 . Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p + wafer with a p - epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

Optical, analog and digital domain architectural considerations for visual communications

NASA Astrophysics Data System (ADS)

Metz, W. A.

2008-01-01

The end of the performance entitlement historically achieved by classic scaling of CMOS devices is within sight, driven ultimately by fundamental limits. Performance entitlements predicted by classic CMOS scaling have progressively failed to be realized in recent process generations due to excessive leakage, increasing interconnect delays and scaling of gate dielectrics. Prior to reaching fundamental limits, trends in technology, architecture and economics will pressure the industry to adopt new paradigms. A likely response is to repartition system functions away from digital implementations and into new architectures. Future architectures for visual communications will require extending the implementation into the optical and analog processing domains. The fundamental properties of these domains will in turn give rise to new architectural concepts. The limits of CMOS scaling and impact on architectures will be briefly reviewed. Alternative approaches in the optical, electronic and analog domains will then be examined for advantages, architectural impact and drawbacks.

An SEU immune logic family

NASA Technical Reports Server (NTRS)

Canaris, J.

1991-01-01

A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.

Application specific serial arithmetic arrays

NASA Technical Reports Server (NTRS)

Winters, K.; Mathews, D.; Thompson, T.

1990-01-01

High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed for specific applications by applying hardware description language techniques to a library of full-custom CMOS building blocks. Single clock pre-charged circuits have been implemented for these arrays at clock rates in excess of 100 Mhz using economical 2-micron (minimum feature size) CMOS processes, which may be quickly configured for a variety of applications. A number of application-specific arrays are presented, including a 2-D convolver for image processing, an integer polynomial solver, and a finite-field polynomial solver.

Study of G-S/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model

NASA Astrophysics Data System (ADS)

Maity, Subir Kumar; Pandit, Soumya

2017-01-01

InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain (G-S/D) underlap length on the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results. The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance. We develop a non-quasi-static (NQS) small signal equivalent circuit model of the device which is used for study of the RF performance. With increase of the underlap length, the unity gain cut-off frequency degrades and the maximum oscillation frequency improves beyond a certain value of the underlap length. We further study the gain-frequency response of a common source amplifier using the NQS model, through SPICE simulation and observe that the voltage gain and the gain bandwidth improves.

Advanced CMOS Radiation Effects Testing and Analysis

NASA Technical Reports Server (NTRS)

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

A Multidisciplinary Approach to High Throughput Nuclear Magnetic Resonance Spectroscopy

PubMed Central

Pourmodheji, Hossein; Ghafar-Zadeh, Ebrahim; Magierowski, Sebastian

2016-01-01

Nuclear Magnetic Resonance (NMR) is a non-contact, powerful structure-elucidation technique for biochemical analysis. NMR spectroscopy is used extensively in a variety of life science applications including drug discovery. However, existing NMR technology is limited in that it cannot run a large number of experiments simultaneously in one unit. Recent advances in micro-fabrication technologies have attracted the attention of researchers to overcome these limitations and significantly accelerate the drug discovery process by developing the next generation of high-throughput NMR spectrometers using Complementary Metal Oxide Semiconductor (CMOS). In this paper, we examine this paradigm shift and explore new design strategies for the development of the next generation of high-throughput NMR spectrometers using CMOS technology. A CMOS NMR system consists of an array of high sensitivity micro-coils integrated with interfacing radio-frequency circuits on the same chip. Herein, we first discuss the key challenges and recent advances in the field of CMOS NMR technology, and then a new design strategy is put forward for the design and implementation of highly sensitive and high-throughput CMOS NMR spectrometers. We thereafter discuss the functionality and applicability of the proposed techniques by demonstrating the results. For microelectronic researchers starting to work in the field of CMOS NMR technology, this paper serves as a tutorial with comprehensive review of state-of-the-art technologies and their performance levels. Based on these levels, the CMOS NMR approach offers unique advantages for high resolution, time-sensitive and high-throughput bimolecular analysis required in a variety of life science applications including drug discovery. PMID:27294925

An easily accessible carbon material derived from carbonization of polyacrylonitrile ultrathin films: ambipolar transport properties and application in a CMOS-like inverter.

PubMed

Jiao, Fei; Zhang, Fengjiao; Zang, Yaping; Zou, Ye; Di, Chong'an; Xu, Wei; Zhu, Daoben

2014-03-04

Ultrathin carbon films were prepared by carbonization of a solution processed polyacrylonitrile (PAN) film in a moderate temperature range (500-700 °C). The films displayed balanced hole (0.50 cm(2) V(-1) s(-1)) and electron mobilities (0.20 cm(2) V(-1) s(-1)) under ambient conditions. Spectral characterization revealed that the electrical transport is due to the formation of sp(2) hybridized carbon during the carbonization process. A CMOS-like inverter demonstrated the potential application of this material in the area of carbon electronics, considering its processability and low-cost.

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders — from Optical Triangulation to the Automotive Field

PubMed Central

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-01-01

With their significant features, the applications of complementary metal-oxide semiconductor (CMOS) image sensors covers a very extensive range, from industrial automation to traffic applications such as aiming systems, blind guidance, active/passive range finders, etc. In this paper CMOS image sensor-based active and passive range finders are presented. The measurement scheme of the proposed active/passive range finders is based on a simple triangulation method. The designed range finders chiefly consist of a CMOS image sensor and some light sources such as lasers or LEDs. The implementation cost of our range finders is quite low. Image processing software to adjust the exposure time (ET) of the CMOS image sensor to enhance the performance of triangulation-based range finders was also developed. An extensive series of experiments were conducted to evaluate the performance of the designed range finders. From the experimental results, the distance measurement resolutions achieved by the active range finder and the passive range finder can be better than 0.6% and 0.25% within the measurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests on applications of the developed CMOS image sensor-based range finders to the automotive field were also conducted. The experimental results demonstrated that our range finders are well-suited for distance measurements in this field. PMID:27879789

Real-time biochemical sensor based on Raman scattering with CMOS contact imaging.

PubMed

Muyun Cao; Yuhua Li; Yadid-Pecht, Orly

2015-08-01

This work presents a biochemical sensor based on Raman scattering with Complementary metal-oxide-semiconductor (CMOS) contact imaging. This biochemical optical sensor is designed for detecting the concentration of solutions. The system is built with a laser diode, an optical filter, a sample holder and a commercial CMOS sensor. The output of the system is analyzed by an image processing program. The system provides instant measurements with a resolution of 0.2 to 0.4 Mol. This low cost and easy-operated small scale system is useful in chemical, biomedical and environmental labs for quantitative bio-chemical concentration detection with results reported comparable to a highly cost commercial spectrometer.

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

A Fully Integrated Quartz MEMS VHF TCXO.

PubMed

Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

2018-06-01

We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

CMOS single-stage input-powered bridge rectifier with boost switch and duty cycle control

NASA Astrophysics Data System (ADS)

Radzuan, Roskhatijah; Mohd Salleh, Mohd Khairul; Hamzah, Mustafar Kamal; Ab Wahab, Norfishah

2017-06-01

This paper presents a single-stage input-powered bridge rectifier with boost switch for wireless-powered devices such as biomedical implants and wireless sensor nodes. Realised using CMOS process technology, it employs a duty cycle switch control to achieve high output voltage using boost technique, leading to a high output power conversion. It has only six external connections with the boost inductance. The input frequency of the bridge rectifier is set at 50 Hz, while the switching frequency is 100 kHz. The proposed circuit is fabricated on a single 0.18-micron CMOS die with a space area of 0.024 mm2. The simulated and measured results show good agreement.

Design and analysis of high gain and low noise figure CMOS low noise amplifier for Q-band nano-sensor application

NASA Astrophysics Data System (ADS)

Suganthi, K.; Malarvizhi, S.

2018-03-01

A high gain, low power, low Noise figure (NF) and wide band of milli-meter Wave (mmW) circuits design at 50 GHz are used for Radio Frequency (RF) front end. The fundamental necessity of a receiver front-end includes perfect output and input impedance matching and port-to-port isolation with high gain and low noise over the entire band of interest. In this paper, a design of Cascade-Cascode CMOS LNA circuit at 50 GHz for Q-band application is proposed. The design of Low noise amplifier at 50 GHz using Agilent ADS tool with microstrip lines which provides simplicity in fabrication and less chip area. The low off-leakage current Ioff can be maintained with high K-dielectrics CMOS structure. Nano-scale electronics can be achieved with increased robustness. The design has overall gain of 11.091 dB and noise figure of 2.673 dB for the Q-band of 48.3 GHz to 51.3 GHz. Impedance matching is done by T matching network and the obtained input and output reflection coefficients are S11 = <-10 dB and S22 = <-10 dB. Compared to Silicon (Si) material, Wide Band Gap semiconductor materials used attains higher junction temperatures which is well matched to ceramics used in packaging technology, the protection and reliability also can be achieved with the electronic packaging. The reverse transmission coefficient S21 is less than -21 dB has shown that LNA has better isolation between input and output, Stability factor greater than 1 and Power is also optimized in this design. Layout is designed, power gain of 4.6 dB is achieved and area is optimized which is nearly equal to 502 740 μm2. The observed results show that the proposed Cascade-Cascode LNA design can find its suitability in future milli-meter Wave Radar application.

Real-Time RF-DNA Fingerprinting of ZigBee Devices Using a Software-Defined Radio with FPGA Processing

DTIC Science & Technology

2015-03-26

REAL-TIME RF-DNA FINGERPRINTING OF ZIGBEE DEVICES USING A SOFTWARE-DEFINED RADIO WITH FPGA...not subject to copyright protection in the United States. AFIT-ENG-MS-15-M-054 REAL-TIME RF-DNA FINGERPRINTING OF ZIGBEE DEVICES USING A...REAL-TIME RF-DNA FINGERPRINTING OF ZIGBEE DEVICES USING A SOFTWARE-DEFINED RADIO WITH FPGA PROCESSING William M. Lowder, BSEE, BSCPE

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

PubMed

Wei, Liping; Yan, Wenrong; Ho, Derek

2017-12-04

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics

PubMed Central

Yan, Wenrong; Ho, Derek

2017-01-01

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices. PMID:29207568

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

PubMed

Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

2014-11-17

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

NASA Astrophysics Data System (ADS)

Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

2018-04-01

This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

NASA Astrophysics Data System (ADS)

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

A Low-Noise Delta-Sigma Phase Modulator for Polar Transmitters

PubMed Central

Zhou, Bo

2014-01-01

A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μm CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of −104 dBc/Hz and −120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively. PMID:24719578

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Advanced Sensors for TBI

DTIC Science & Technology

2015-07-01

CMOS clean • Commercialization of the sensor is aided by this process as use of CMOS -clean commercial foundries will not be restricted Bench...AD_________________ Award Number: W81XWH-10-2-0040 TITLE: Advanced Sensors for TBI PRINCIPAL INVESTIGATOR: Bruce Lyeth, Ph.D. CONTRACTING...ABOVE ADDRESS. 1. REPORT DATE July 2015 2. REPORT TYPE Annual 3. DATES COVERED 1Jul2014 - 30Jun2015 4. TITLE AND SUBTITLE Advanced Sensors for TBI 5a

CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

PubMed

Hussain, Aftab M; Hussain, Muhammad M

2016-06-01

Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

PubMed

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

A research on radiation calibration of high dynamic range based on the dual channel CMOS

NASA Astrophysics Data System (ADS)

Ma, Kai; Shi, Zhan; Pan, Xiaodong; Wang, Yongsheng; Wang, Jianghua

2017-10-01

The dual channel complementary metal-oxide semiconductor (CMOS) can get high dynamic range (HDR) image through extending the gray level of the image by using image fusion with high gain channel image and low gain channel image in a same frame. In the process of image fusion with dual channel, it adopts the coefficients of radiation response of a pixel from dual channel in a same frame, and then calculates the gray level of the pixel in the HDR image. For the coefficients of radiation response play a crucial role in image fusion, it has to find an effective method to acquire these parameters. In this article, it makes a research on radiation calibration of high dynamic range based on the dual channel CMOS, and designs an experiment to calibrate the coefficients of radiation response for the sensor it used. In the end, it applies these response parameters in the dual channel CMOS which calibrates, and verifies the correctness and feasibility of the method mentioned in this paper.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

CMOS direct time interval measurement of long-lived luminescence lifetimes.

PubMed

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

NASA Astrophysics Data System (ADS)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials for Hybrid PN Junction and CMOS Inverters.

PubMed

Lee, Han Sol; Choi, Kyunghee; Kim, Jin Sung; Yu, Sanghyuck; Ko, Kyeong Rok; Im, Seongil

2017-05-10

We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe 2 and n-type thin film InGaZnO (IGZO) are coupled for each device process. IGZO thin film was initially patterned by conventional photolithography either for n-type material in a PN diode or for n-channel of top-gate field-effect transistors (FET) in CMOS inverter. The hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 10 4 . Under photons, our hybrid PN diode appeared somewhat stable only responding to high-energy photons of blue and ultraviolet. Our 2D nanosheet-oxide film hybrid CMOS inverter exhibits voltage gains as high as ∼40 at 5 V, low power consumption less than around a few nW at 1 V, and ∼200 μs switching dynamics.

Time-Domain Receiver Function Deconvolution using Genetic Algorithm

NASA Astrophysics Data System (ADS)

Moreira, L. P.

2017-12-01

Receiver Functions (RF) are well know method for crust modelling using passive seismological signals. Many different techniques were developed to calculate the RF traces, applying the deconvolution calculation to radial and vertical seismogram components. A popular method used a spectral division of both components, which requires human intervention to apply the Water Level procedure to avoid instabilities from division by small numbers. One of most used method is an iterative procedure to estimate the RF peaks and applying the convolution with vertical component seismogram, comparing the result with the radial component. This method is suitable for automatic processing, however several RF traces are invalid due to peak estimation failure.In this work it is proposed a deconvolution algorithm using Genetic Algorithm (GA) to estimate the RF peaks. This method is entirely processed in the time domain, avoiding the time-to-frequency calculations (and vice-versa), and totally suitable for automatic processing. Estimated peaks can be used to generate RF traces in a seismogram format for visualization. The RF trace quality is similar for high magnitude events, although there are less failures for RF calculation of smaller events, increasing the overall performance for high number of events per station.

Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

NASA Astrophysics Data System (ADS)

Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

2014-03-01

We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

HF-Release of Sacrificial Layers in CMOS-integrated MOEMS structures

NASA Astrophysics Data System (ADS)

Döring, S.; Friedrichs, M.; Pufe, W.; Schulze, M.

2016-10-01

In this paper we will present details of the release process of SiO2 sacrificial layers we use within a multi-level MOEMS process developed by IPMS. Using such sacrificial layers gain a lot of benefits necessary for the production of high-end MOEMS devices like high surface quality and great surface planarity. However the HF-release of the sacrificial layer can be connected with specific issues. We present, which mechanisms are involved in the release process and how knowing them, can be the key for an optimized performance of the device. More-over we will present how to protect the CMOS backplane of our devices from unwanted HF attack during the release.

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

PubMed Central

Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

2008-01-01

A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications. PMID:27873887

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

Fundamental performance differences between CMOS and CCD imagers: Part II

NASA Astrophysics Data System (ADS)

Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

2007-09-01

A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

Photon counting readout pixel array in 0.18-μm CMOS technology for on-line gamma-ray imaging of 103palladium seeds for permanent breast seed implant (PBSI) brachytherapy

NASA Astrophysics Data System (ADS)

Goldan, A. H.; Karim, K. S.; Reznik, A.; Caldwell, C. B.; Rowlands, J. A.

2008-03-01

Permanent breast seed implant (PBSI) brachytherapy technique was recently introduced as an alternative to high dose rate (HDR) brachytherapy and involves the permanent implantation of radioactive 103Palladium seeds into the surgical cavity of the breast for cancer treatment. To enable accurate seed implantation, this research introduces a gamma camera based on a hybrid amorphous selenium detector and CMOS readout pixel architecture for real-time imaging of 103Palladium seeds during the PBSI procedure. A prototype chip was designed and fabricated in 0.18-μm n-well CMOS process. We present the experimental results obtained from this integrated photon counting readout pixel.

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, X.; Mamaluy, D.; Cyr, E. C.

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE PAGES

Gao, X.; Mamaluy, D.; Cyr, E. C.; ...

2016-05-10

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

NASA Astrophysics Data System (ADS)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on the total ionizing dose (TID) effect, to understand the associated physical mechanisms, and to help to inspire ideas to improve radiation immunity of these novel devices. The experimental methods used in this thesis research include the measurements of C-V, I-V characteristics, where novel gate stack and interface characterization techniques are employed, such as AC Gm method, 1/f low frequency noise method, inelastic electron tunneling spectroscopy (IETS) for chemical bonding and defects detection, and carrier transport modeling. Sentaurus TCAD simulations are also carried out to obtain more physical insight in the complex, extremely scaled, device structures.

The fabrication of a programmable via using phase-change material in CMOS-compatible technology.

PubMed

Chen, Kuan-Neng; Krusin-Elbaum, Lia

2010-04-02

We demonstrate an energy-efficient programmable via concept using indirectly heated phase-change material. This via structure has maximum phase-change volume to achieve a minimum on resistance for high performance logic applications. Process development and material investigations for this device structure are reported. The device concept is successfully demonstrated in a standard CMOS-compatible technology capable of multiple cycles between on/off states for reconfigurable applications.

Optimization of a RF-generated CF4/O2 gas plasma sterilization process.

PubMed

Lassen, Klaus S; Nordby, Bolette; Grün, Reinar

2003-05-15

A sterilization process with the use of RF-generated (13.56 MHz) CF(4)/O(2) gas plasma was optimized in regards to power, flow rate, exposure time, and RF-system type. The dependency of the sporicidal effect on the spore inoculum positioning in the chamber of the RF systems was also investigated. Dried Bacillus stearothermophilus ATCC 7953 endospores were used as test organisms. The treatments were evaluated on the basis of survival curves and corresponding D values. The only parameter found to affect the sterilization process was the power of the RF system. Higher power resulted in higher kill. Finally, when the samples were placed more than 3-8 cm away from a centrally placed electrode in System 2, the sporicidal effect was reduced. The results are discussed and compared to results from the present literature. The RF excitation source is evaluated to be more appropriate for sterilization processes than the MW source. Copyright 2003 Wiley Periodicals, Inc. J Biomed Mater Res Part B: Appl Biomater 65B: 239-244, 2003

Built-in self-test (BIST) techniques for millimeter wave CMOS transceivers

NASA Astrophysics Data System (ADS)

Mahzabeen, Tabassum

The seamless integration of complementary metal oxide semiconductor (CMOS) transceivers with a digital CMOS process enhances on-chip testability, thus reducing production and testing costs. Built in self testability also improves yield by offering on-chip compensation. This work focuses on built in self test techniques for CMOS based millimeter wave (mm-wave) transceivers. Built-in-self-test (BIST) using the loopback method is one cost-effective method for testing these transceivers. Since the loopback switch is always present during the normal operation of the transceiver, the requirement of the switch is different than for a conventional switch. The switch needs to have high isolation and high impedance during its OFF period. Two 80 GHz single pole single throw (SPST) switches have been designed, fabricated in standard CMOS process, and measured to connect the loopback path for BIST applications. The loopback switches in this work provide the required criteria for loopback BIST. A stand alone 80 GHz low noise amplifier (LNA) and the same LNA integrated with one of the loopback switches have been fabricated, and measured to observe the difference in performance when the loopback switch is present. Besides the loopback switch, substrate leakage also forms a path between the transmitter and receiver. Substrate leakage has been characterized as a function of distance between the transmitter and receiver for consideration in using the BIST method. A BIST algorithm has been developed to estimate the process variation in device sizes by probing a low frequency ring oscillator to estimate the device variation and map this variation to the 80 GHz LNA. Probing a low frequency circuit is cheaper compared to the probing of a millimeter wave circuit and reduces the testing costs. The performance of the LNA degrades due to variation in device size. Once the shift in the device size is being estimated (from the ring oscillator's shifted frequency), the LNA's performance can be recovered using several methods; for example, using tunable transmission line lengths in the amplifier or using a variable supply voltage. This concept of estimating process variation has been demonstrated in Agilent Design System (ADS).

Using antennas separated in flight direction to avoid effect of emitter clock drift in geolocation

DOEpatents

Ormesher, Richard C.; Bickel, Douglas L

2012-10-23

The location of a land-based radio frequency (RF) emitter is determined from an airborne platform. RF signaling is received from the RF emitter via first and second antennas. In response to the received RF signaling, signal samples for both antennas are produced and processed to determine the location of the RF emitter.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Development of Integrated Preamplifier for High-Frequency Ultrasonic Transducers and Low-Power Handheld Receiver

PubMed Central

Choi, Hojong; Li, Xiang; Lau, Sien-Ting; Hu, ChangHong; Zhou, Qifa; Shung, K. Kirk

2012-01-01

This paper describes the design of a front-end circuit consisting of an integrated preamplifier with a Sallen-Key Butterworth filter for very-high-frequency ultrasonic transducers and a low-power handheld receiver. This preamplifier was fabricated using a 0.18-μm 7WL SiGe bi-polar complementary metal oxide semiconductor (BiCMOS) process. The Sallen-Key filter is used to increase the voltage gain of the front-end circuit for high-frequency transducers which are generally low in sensitivity. The measured peak voltage gain of the frontend circuits for the BiCMOS preamplifier with the Sallen-Key filter was 41.28 dB at 100 MHz with a −6-dB bandwidth of 91%, and the dc power consumption of the BiCMOS preamplifier was 49.53 mW. The peak voltage gain of the front-end circuits for the CMOS preamplifier with the Sallen-Key filter was 39.52 dB at 100 MHz with a −6-dB bandwidth of 108%, and the dc power consumption of the CMOS preamplifier was 43.57 mW. Pulse-echo responses and wire phantom images with a single-element ultrasonic transducer have been acquired to demonstrate the performance of the front-end circuit. PMID:23443700

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

A low jitter all - digital phase - locked loop in 180 nm CMOS technology

NASA Astrophysics Data System (ADS)

Shumkin, O. V.; Butuzov, V. A.; Normanov, D. D.; Ivanov, P. Yu

2016-02-01

An all-digital phase locked loop (ADPLL) was implemented in 180 nm CMOS technology. The proposed ADPLL uses a digitally controlled oscillator to achieve 3 ps resolution. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. The proposed ADPLL can be easily applied to different process as a soft IP block, making it very suitable for system-on-chip applications.

Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Y.; Hu-Guo, C.; Husson, D.

2011-07-01

Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial pointsmore » of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)« less

All-digital pulse-expansion-based CMOS digital-to-time converter.

PubMed

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μm Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm 2 . Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

All-digital pulse-expansion-based CMOS digital-to-time converter

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μ m Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm2. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

System-in Package of Integrated Humidity Sensor Using CMOS-MEMS Technology.

PubMed

Lee, Sung Pil

2015-10-01

Temperature/humidity microchips with micropump were fabricated using a CMOS-MEMS process and combined with ZigBee modules to implement a sensor system in package (SIP) for a ubiquitous sensor network (USN) and/or a wireless communication system. The current of a diode temperature sensor to temperature and a normalized current of FET humidity sensor to relative humidity showed linear characteristics, respectively, and the use of the micropump has enabled a faster response. A wireless reception module using the same protocol as that in transmission systems processed the received data within 10 m and showed temperature and humidity values in the display.

Design and fabrication of reflective spatial light modulator for high-dynamic-range wavefront control

NASA Astrophysics Data System (ADS)

Zhu, Hao; Bierden, Paul; Cornelissen, Steven; Bifano, Thomas; Kim, Jin-Hong

2004-10-01

This paper describes design and fabrication of a microelectromechanical metal spatial light modulator (SLM) integrated with complementary metal-oxide semiconductor (CMOS) electronics, for high-dynamic-range wavefront control. The metal SLM consists of a large array of piston-motion MEMS mirror segments (pixels) which can deflect up to 0.78 µm each. Both 32x32 and 150x150 arrays of the actuators (1024 and 22500 elements respectively) were fabricated onto the CMOS driver electronics and individual pixels were addressed. A new process has been developed to reduce the topography during the metal MEMS processing to fabricate mirror pixels with improved optical quality.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Bioinspired architecture approach for a one-billion transistor smart CMOS camera chip

NASA Astrophysics Data System (ADS)

Fey, Dietmar; Komann, Marcus

2007-05-01

In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long and too many global interconnects for the distribution of code or the access to common memory. On the other hand nature developed self-organising and emergent principles to manage successfully complex structures based on lots of interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a 0.18 μm CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100 MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow the integration and processing of Mega pixels within the same time since our architecture is fully scalable.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

NASA Astrophysics Data System (ADS)

Singh, Anil; Agarwal, Alpana

2016-10-01

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

Real-time optically sectioned wide-field microscopy employing structured light illumination and a CMOS detector

NASA Astrophysics Data System (ADS)

Mitic, Jelena; Anhut, Tiemo; Serov, Alexandre; Lasser, Theo; Bourquin, Stephane

2003-07-01

Real-time optically sectioned microscopy is demonstrated using an AC-sensitive detection concept realized with smart CMOS image sensor and structured light illumination by a continuously moving periodic pattern. We describe two different detection systems based on CMOS image sensors for the detection and on-chip processing of the sectioned images in real time. A region-of-interest is sampled at high frame rate. The demodulated signal delivered by the detector corresponds to the depth discriminated image of the sample. The measured FWHM of the axial response depends on the spatial frequency of the projected grid illumination and is in the μm-range. The effect of using broadband incoherent illumination is discussed. The performance of these systems is demonstrated by imaging technical as well as biological samples.

Ultralow-Loss CMOS Copper Plasmonic Waveguides.

PubMed

Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

2016-01-13

Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

2015-12-01

This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm2 and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

CMOS micromachined capacitive cantilevers for mass sensing

NASA Astrophysics Data System (ADS)

Li, Ying-Chung; Ho, Meng-Han; Hung, Shi-Jie; Chen, Meng-Huei; S-C Lu, Michael

2006-12-01

In this paper, we present the design, fabrication and characterization of the CMOS micromachined cantilevers for mass sensing in the femtogram range. The cantilevers consisting of multiple metal and dielectric layers are fabricated after completion of a conventional CMOS process by dry etching steps. The cantilevers are electrostatically actuated to resonance by in-plane electrodes. The mechanical resonant frequency is detected capacitively with on-chip circuitry, where the modulation technique is applied to eliminate capacitive feedthrough from the driving port and to lessen the effect of flicker noise. The highest resonant frequency of the cantilevers is measured at 396.46 kHz with a quality factor of 2600 at 10 mTorr. The resonant frequency shift after deposition of a 0.1 µm SiO2 layer is 140 Hz, averaging 353 fg Hz-1.

A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

PubMed Central

Huang, Che-Wei; Huang, Yu-Jie; Lu, Shey-Shi; Lin, Chih-Ting

2012-01-01

A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH) range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications

NASA Astrophysics Data System (ADS)

Tavel, B.; Duriez, B.; Gwoziecki, R.; Basso, M. T.; Julien, C.; Ortolland, C.; Laplanche, Y.; Fox, R.; Sabouret, E.; Detcheverry, C.; Boeuf, F.; Morin, P.; Barge, D.; Bidaud, M.; Biénacel, J.; Garnier, P.; Cooper, K.; Chapon, J. D.; Trouiller, Y.; Belledent, J.; Broekaart, M.; Gouraud, P.; Denais, M.; Huard, V.; Rochereau, K.; Difrenza, R.; Planes, N.; Marin, M.; Boret, S.; Gloria, D.; Vanbergue, S.; Abramowitz, P.; Vishnubhotla, L.; Reber, D.; Stolk, P.; Woo, M.; Arnaud, F.

2006-04-01

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with FT = 160 GHz for LP and 280 GHz for GP nMOS transistors.

The development of data acquisition and processing application system for RF ion source

NASA Astrophysics Data System (ADS)

Zhang, Xiaodan; Wang, Xiaoying; Hu, Chundong; Jiang, Caichao; Xie, Yahong; Zhao, Yuanzhe

2017-07-01

As the key ion source component of nuclear fusion auxiliary heating devices, the radio frequency (RF) ion source is developed and applied gradually to offer a source plasma with the advantages of ease of control and high reliability. In addition, it easily achieves long-pulse steady-state operation. During the process of the development and testing of the RF ion source, a lot of original experimental data will be generated. Therefore, it is necessary to develop a stable and reliable computer data acquisition and processing application system for realizing the functions of data acquisition, storage, access, and real-time monitoring. In this paper, the development of a data acquisition and processing application system for the RF ion source is presented. The hardware platform is based on the PXI system and the software is programmed on the LabVIEW development environment. The key technologies that are used for the implementation of this software programming mainly include the long-pulse data acquisition technology, multi-threading processing technology, transmission control communication protocol, and the Lempel-Ziv-Oberhumer data compression algorithm. Now, this design has been tested and applied on the RF ion source. The test results show that it can work reliably and steadily. With the help of this design, the stable plasma discharge data of the RF ion source are collected, stored, accessed, and monitored in real-time. It is shown that it has a very practical application significance for the RF experiments.

Effect of assistant rf field on phase composition of iron nitride film prepared by magnetron sputtering process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, W.L.; Zheng, F.; Fei, W.D.

2006-01-15

Fe-N thin films were fabricated using a direct current magnetron sputtering process assisted by a radio-frequency (rf) field. The effect of the rf field on the phase composition of the films was investigated. The results indicate that with the assistance of the rf field, various kinds of iron nitrides can be obtained in the films, including {alpha}{sup '}-Fe-N, {alpha}{sup ''}-Fe{sub 16}N{sub 2}, {xi}-Fe{sub 2}N, {epsilon}-Fe{sub 3}N, and {gamma}{sup ''}-FeN with ZnS structure. It was found that the rf field greatly benefits the formation of iron nitrides in the Fe-N films.

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

NASA Astrophysics Data System (ADS)

Davidson, Bradley Darren

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

NASA Astrophysics Data System (ADS)

Nan, Liu; Guoping, Chen; Zhiliang, Hong

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.

2017-12-01

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

An all-silicon optical PC-to-PC link utilizing USB

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Alberts, Antonie C.; Venter, Petrus J.; du Plessis, Monuko; Rademeyer, Pieter

2013-02-01

An integrated silicon light source still remains the Holy Grail for integrated optical communication systems. Hot carrier luminescent light sources provide a way to create light in a standard CMOS process, potentially enabling cost effective optical communication between CMOS integrated circuits. In this paper we present a 1 Mb/s integrated silicon optical link for information transfer, targeting a real-world integrated solution by connecting two PCs via a USB port while transferring data optically between the devices. This realization represents the first optical communication product prototype utilizing a CMOS light emitter. The silicon light sources which are implemented in a standard 0.35 μm CMOS technology are electrically modulated and detected using a commercial silicon avalanche photodiode. Data rates exceeding 10 Mb/s using silicon light sources have previously been demonstrated using raw bit streams. In this work data is sent in two half duplex streams accompanied with the separate transmission of a clock. Such an optical communication system could find application in high noise environments where data fidelity, range and cost are a determining factor.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

PubMed

Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

2012-05-07

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

A digital output piezoelectric accelerometer using a Pb(Zr, Ti)O3 thin film array electrically connected in series

NASA Astrophysics Data System (ADS)

Kobayashi, T.; Okada, H.; Masuda, T.; Maeda, R.; Itoh, T.

2010-10-01

A digital output piezoelectric accelerometer is proposed to realize an ultra-low power consumption wireless sensor node. The accelerometer has patterned piezoelectric thin films (piezoelectric plates) electrically connected in series accompanied by CMOS switches at the end of some of the piezoelectric plates. The connected piezoelectric plates amplify the output voltage without the use of amplifiers. The CMOS switches turn on when the output voltage of the piezoelectric plates is higher than the CMOS threshold voltage. The piezoelectric accelerometer converts the acceleration into a number of on-state CMOS switches, which can be called the digital output. The proposed digital output piezoelectric accelerometer, using Pb(Zr, Ti)O3 (PZT) thin films as the piezoelectric material, was fabricated through a microelectromechanical system (MEMS) microfabrication process. The output voltage was found to be amplified by the number of connected piezoelectric plates. The DC output voltage obtained by using an AC to DC conversion circuit is proportional to the number of connections. The results show the potential for realizing the proposed digital output piezoelectric accelerometer.

Numerical analysis of effects of ion-neutral collision processes on RF ICP discharge

NASA Astrophysics Data System (ADS)

Nishida, K.; Mattei, S.; Lettry, J.; Hatayama, A.

2018-01-01

The discharge process of a radiofrequency (RF) inductively coupled plasma (ICP) has been modeled by an ElectroMagnetic Particle-in-Cell Monte Carlo Collision method (EM PIC-MCC). Although the simulation had been performed by our previous model to investigate the discharge mode transition of the RF ICP from a kinetic point of view, the model neglected the collision processes of ions (H+ and H2+) with neutral particles. In this study, the RF ICP discharge process has been investigated by the latest version of the model which takes the ion-neutral collision processes into account. The basic characteristics of the discharge mode transition provided by the previous model have been verified by the comparison between the previous and present results. As for the H-mode discharge regime, on the other hand, the ion-neutral collisions play an important role in evaluating the growth of the plasma. Also, the effect of the ion-neutral collisions on the kinetic feature of the plasma has been investigated, which has highlighted the importance of kinetic perspective for modeling the RF ICP discharge.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seiya, K.; Drennan, C.; Pellico, W.

The extraction bucket position in the Fermilab Booster is controlled with a cogging process that involves the comparison of the Booster rf count and the Recycler Ring revolution marker. A one rf bucket jitter in the ex-traction bucket position results from the variability of the process that phase matches the Booster to the Recycler. However, the new slow phase lock process used to lock the frequency and phase of the Booster rf to the Recycler rf has been made digital and programmable and has been modified to correct the extraction notch position. The beam loss at the Recycler injection hasmore » been reduced by 20%. Beam studies and the phase lock system will be discussed in this paper.« less

Performance Analysis of Visible Light Communication Using CMOS Sensors.

PubMed

Do, Trong-Hop; Yoo, Myungsik

2016-02-29

This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Ultra compact 45 GHz CMOS compatible Germanium waveguide photodiode with low dark current.

PubMed

DeRose, Christopher T; Trotter, Douglas C; Zortman, William A; Starbuck, Andrew L; Fisher, Moz; Watts, Michael R; Davids, Paul S

2011-12-05

We present a compact 1.3 × 4 μm2 Germanium waveguide photodiode, integrated in a CMOS compatible silicon photonics process flow. This photodiode has a best-in-class 3 dB cutoff frequency of 45 GHz, responsivity of 0.8 A/W and dark current of 3 nA. The low intrinsic capacitance of this device may enable the elimination of transimpedance amplifiers in future optical data communication receivers, creating ultra low power consumption optical communications.

Performance Analysis of Visible Light Communication Using CMOS Sensors

PubMed Central

Do, Trong-Hop; Yoo, Myungsik

2016-01-01

This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

NASA Technical Reports Server (NTRS)

Timoc, C.; Tran, T.; Wongso, J.

1992-01-01

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Lo, R. Y.

1987-01-01

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Drake, G.; Garcia-Scivres, M.; Paramonov, A.

We propose to use silicon photonics technology to build radiation-hard fiber-optic links for high-bandwidth readout of tracking detectors. The CMOS integrated silicon photonics was developed by Luxtera and commercialized by Molex. The commercial off-the-shelf (COTS) fiber-optic links feature moderate radiation tolerance insufficient for trackers. A transceiver contains four RX and four TX channels operating at 10 Gbps each. The next generation will likely operate at 25 Gbps per channel. The approach uses a standard CMOS process and single-mode fibers, providing low power consumption and good scalability and reliability.

Optoelectronics in TESLA, LHC, and pi-of-the-sky experiments

NASA Astrophysics Data System (ADS)

Romaniuk, Ryszard S.; Pozniak, Krzysztof T.; Wrochna, Grzegorz; Simrock, Stefan

2004-09-01

Optical and optoelectronics technologies are more and more widely used in the biggest world experiments of high energy and nuclear physics, as well as in the astronomy. The paper is a kind of a broad digest describing the usage of optoelectronics is such experiments and information about some of the involved teams. The described experiments include: TESLA linear accelerator and FEL, Compact Muon Solenoid at LHC and recently started π-of-the-sky global gamma ray bursts (with asociated optical flashes) observation experiment. Optoelectornics and photonics offer several key features which are either extending the technical parameters of existing solutions or adding quite new practical application possibilities. Some of these favorable features of photonic systems are: high selectivity of optical sensors, immunity to some kinds of noise processes, extremely broad bandwidth exchangeable for either terabit rate transmission or ultrashort pulse generation, parallel image processing capability, etc. The following groups of photonic components and systems were described: (1) discrete components applications like: LED, PD, LD, CCD and CMOS cameras, active optical crystals and optical fibers in radiation dosimetry, astronomical image processing and for building of more complex photonic systems; (2) optical fiber networks serving as very stable phase distribution, clock signal distribution, distributed dosimeters, distributed gigabit transmission for control, diagnostics and data acquisition/processing; (3) fast and stable coherent femtosecond laser systems with active optical components for electro-optical sampling and photocathode excitation in the RF electron gun for linac; The parameters of some of these systems were quoted and discussed. A number of the debated solutions seems to be competitive against the classical ones. Several future fields seem to emerge involving direct coupling between the ultrafast photonic and the VLSI FPGA based technologies.

Research-grade CMOS image sensors for remote sensing applications

NASA Astrophysics Data System (ADS)

Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

2004-11-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

PubMed

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

2018-04-05

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing.

PubMed

Karimi-Bidhendi, Alireza; Malekzadeh-Arasteh, Omid; Lee, Mao-Cheng; McCrimmon, Colin M; Wang, Po T; Mahajan, Akshay; Liu, Charles Yu; Nenadic, Zoran; Do, An H; Heydari, Payam

2017-08-01

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 μV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels.

PubMed

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshiari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-09-02

In this paper we present a novel, quadruple well process developed in a modern 0.18 mm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 mm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

Integration of image capture and processing: beyond single-chip digital camera

NASA Astrophysics Data System (ADS)

Lim, SukHwan; El Gamal, Abbas

2001-05-01

An important trend in the design of digital cameras is the integration of capture and processing onto a single CMOS chip. Although integrating the components of a digital camera system onto a single chip significantly reduces system size and power, it does not fully exploit the potential advantages of integration. We argue that a key advantage of integration is the ability to exploit the high speed imaging capability of CMOS image senor to enable new applications such as multiple capture for enhancing dynamic range and to improve the performance of existing applications such as optical flow estimation. Conventional digital cameras operate at low frame rates and it would be too costly, if not infeasible, to operate their chips at high frame rates. Integration solves this problem. The idea is to capture images at much higher frame rates than he standard frame rate, process the high frame rate data on chip, and output the video sequence and the application specific data at standard frame rate. This idea is applied to optical flow estimation, where significant performance improvements are demonstrate over methods using standard frame rate sequences. We then investigate the constraints on memory size and processing power that can be integrated with a CMOS image sensor in a 0.18 micrometers process and below. We show that enough memory and processing power can be integrated to be able to not only perform the functions of a conventional camera system but also to perform applications such as real time optical flow estimation.

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2014-02-01

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

NASA Technical Reports Server (NTRS)

Stahl, R. H.

1977-01-01

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

NASA Astrophysics Data System (ADS)

Kim, Jungsuk

2016-12-01

This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

PubMed

Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

2013-01-01

One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

A 0.13µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation

NASA Astrophysics Data System (ADS)

Agawa, Kenichi; Ishizuka, Shinichiro; Majima, Hideaki; Kobayashi, Hiroyuki; Koizumi, Masayuki; Nagano, Takeshi; Arai, Makoto; Shimizu, Yutaka; Maki, Asuka; Urakawa, Go; Terada, Tadashi; Itoh, Nobuyuki; Hamada, Mototsugu; Fujii, Fumie; Kato, Tadamasa; Yoshitomi, Sadayuki; Otsuka, Nobuaki

A 2.4GHz 0.13µm CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40°C and +90°C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13µm CMOS and operation at a low supply voltage of 1.5V result in small area and low power consumption.

High-resolution, continuous field-of-view (FOV), non-rotating imaging system

NASA Technical Reports Server (NTRS)

Huntsberger, Terrance L. (Inventor); Stirbl, Robert C. (Inventor); Aghazarian, Hrand (Inventor); Padgett, Curtis W. (Inventor)

2010-01-01

A high resolution CMOS imaging system especially suitable for use in a periscope head. The imaging system includes a sensor head for scene acquisition, and a control apparatus inclusive of distributed processors and software for device-control, data handling, and display. The sensor head encloses a combination of wide field-of-view CMOS imagers and narrow field-of-view CMOS imagers. Each bank of imagers is controlled by a dedicated processing module in order to handle information flow and image analysis of the outputs of the camera system. The imaging system also includes automated or manually controlled display system and software for providing an interactive graphical user interface (GUI) that displays a full 360-degree field of view and allows the user or automated ATR system to select regions for higher resolution inspection.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

A 1.2 Gb/s Data Transmission Unit in CMOS 0.18 μm technology for the ALICE Inner Tracking System front-end ASIC

NASA Astrophysics Data System (ADS)

Mazza, G.; Aglieri Rinella, G.; Benotto, F.; Corrales Morales, Y.; Kugathasan, T.; Lattuca, A.; Lupi, M.; Ravasenga, I.

2017-02-01

The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 μ m process. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process. The DTU includes a clock multiplier PLL, a double data rate serializer and a pseudo-LVDS driver with pre-emphasis and is designed to be SEU tolerant.

Radiation tolerant 1 micron CMOS technology

NASA Astrophysics Data System (ADS)

Crevel, P.; Rodde, K.

1991-03-01

Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis.

PubMed

Huang, Xiwei; Yu, Hao; Liu, Xu; Jiang, Yu; Yan, Mei; Wu, Dongping

2015-09-01

The existing ISFET-based DNA sequencing detects hydrogen ions released during the polymerization of DNA strands on microbeads, which are scattered into microwell array above the ISFET sensor with unknown distribution. However, false pH detection happens at empty microwells due to crosstalk from neighboring microbeads. In this paper, a dual-mode CMOS ISFET sensor is proposed to have accurate pH detection toward DNA sequencing. Dual-mode sensing, optical and chemical modes, is realized by integrating a CMOS image sensor (CIS) with ISFET pH sensor, and is fabricated in a standard 0.18-μm CIS process. With accurate determination of microbead physical locations with CIS pixel by contact imaging, the dual-mode sensor can correlate local pH for one DNA slice at one location-determined microbead, which can result in improved pH detection accuracy. Moreover, toward a high-throughput DNA sequencing, a correlated-double-sampling readout that supports large array for both modes is deployed to reduce pixel-to-pixel nonuniformity such as threshold voltage mismatch. The proposed CMOS dual-mode sensor is experimentally examined to show a well correlated pH map and optical image for microbeads with a pH sensitivity of 26.2 mV/pH, a fixed pattern noise (FPN) reduction from 4% to 0.3%, and a readout speed of 1200 frames/s. A dual-mode CMOS ISFET sensor with suppressed FPN for accurate large-arrayed pH sensing is proposed and demonstrated with state-of-the-art measured results toward accurate and high-throughput DNA sequencing. The developed dual-mode CMOS ISFET sensor has great potential for future personal genome diagnostics with high accuracy and low cost.

Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

A simple and low-cost biofilm quantification method using LED and CMOS image sensor.

PubMed

Kwak, Yeon Hwa; Lee, Junhee; Lee, Junghoon; Kwak, Soo Hwan; Oh, Sangwoo; Paek, Se-Hwan; Ha, Un-Hwan; Seo, Sungkyu

2014-12-01

A novel biofilm detection platform, which consists of a cost-effective red, green, and blue light-emitting diode (RGB LED) as a light source and a lens-free CMOS image sensor as a detector, is designed. This system can measure the diffraction patterns of cells from their shadow images, and gather light absorbance information according to the concentration of biofilms through a simple image processing procedure. Compared to a bulky and expensive commercial spectrophotometer, this platform can provide accurate and reproducible biofilm concentration detection and is simple, compact, and inexpensive. Biofilms originating from various bacterial strains, including Pseudomonas aeruginosa (P. aeruginosa), were tested to demonstrate the efficacy of this new biofilm detection approach. The results were compared with the results obtained from a commercial spectrophotometer. To utilize a cost-effective light source (i.e., an LED) for biofilm detection, the illumination conditions were optimized. For accurate and reproducible biofilm detection, a simple, custom-coded image processing algorithm was developed and applied to a five-megapixel CMOS image sensor, which is a cost-effective detector. The concentration of biofilms formed by P. aeruginosa was detected and quantified by varying the indole concentration, and the results were compared with the results obtained from a commercial spectrophotometer. The correlation value of the results from those two systems was 0.981 (N = 9, P < 0.01) and the coefficients of variation (CVs) were approximately threefold lower at the CMOS image-sensor platform. Copyright © 2014 Elsevier B.V. All rights reserved.

Machine Learning Based Single-Frame Super-Resolution Processing for Lensless Blood Cell Counting

PubMed Central

Huang, Xiwei; Jiang, Yu; Liu, Xu; Xu, Hang; Han, Zhi; Rong, Hailong; Yang, Haiping; Yan, Mei; Yu, Hao

2016-01-01

A lensless blood cell counting system integrating microfluidic channel and a complementary metal oxide semiconductor (CMOS) image sensor is a promising technique to miniaturize the conventional optical lens based imaging system for point-of-care testing (POCT). However, such a system has limited resolution, making it imperative to improve resolution from the system-level using super-resolution (SR) processing. Yet, how to improve resolution towards better cell detection and recognition with low cost of processing resources and without degrading system throughput is still a challenge. In this article, two machine learning based single-frame SR processing types are proposed and compared for lensless blood cell counting, namely the Extreme Learning Machine based SR (ELMSR) and Convolutional Neural Network based SR (CNNSR). Moreover, lensless blood cell counting prototypes using commercial CMOS image sensors and custom designed backside-illuminated CMOS image sensors are demonstrated with ELMSR and CNNSR. When one captured low-resolution lensless cell image is input, an improved high-resolution cell image will be output. The experimental results show that the cell resolution is improved by 4×, and CNNSR has 9.5% improvement over the ELMSR on resolution enhancing performance. The cell counting results also match well with a commercial flow cytometer. Such ELMSR and CNNSR therefore have the potential for efficient resolution improvement in lensless blood cell counting systems towards POCT applications. PMID:27827837

Challenges of nickel silicidation in CMOS technologies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet

2015-04-01

In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of themore » nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.« less

Development of on-line laser power monitoring system

NASA Astrophysics Data System (ADS)

Ding, Chien-Fang; Lee, Meng-Shiou; Li, Kuan-Ming

2016-03-01

Since the laser was invented, laser has been applied in many fields such as material processing, communication, measurement, biomedical engineering, defense industries and etc. Laser power is an important parameter in laser material processing, i.e. laser cutting, and laser drilling. However, the laser power is easily affected by the environment temperature, we tend to monitor the laser power status, ensuring there is an effective material processing. Besides, the response time of current laser power meters is too long, they cannot measure laser power accurately in a short time. To be more precisely, we can know the status of laser power and help us to achieve an effective material processing at the same time. To monitor the laser power, this study utilize a CMOS (Complementary metal-oxide-semiconductor) camera to develop an on-line laser power monitoring system. The CMOS camera captures images of incident laser beam after it is split and attenuated by beam splitter and neutral density filter. By comparing the average brightness of the beam spots and measurement results from laser power meter, laser power can be estimated. Under continuous measuring mode, the average measuring error is about 3%, and the response time is at least 3.6 second shorter than thermopile power meters; under trigger measuring mode which enables the CMOS camera to synchronize with intermittent laser output, the average measuring error is less than 3%, and the shortest response time is 20 millisecond.

Comparative study of ITO and TiN fabricated by low-temperature RF biased sputtering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Simon, Daniel K., E-mail: daniel.simon@namlab.com; Schenk, Tony; Dirnstorfer, Ingo

2016-03-15

Radio frequency (RF) biasing induced by a second plasma source at the substrate is applied to low-temperature sputtering processes for indium tin oxide (ITO) and titanium nitride (TiN) thin films. Investigations on crystal structure and surface morphology show that RF-biased substrate plasma processes result in a changed growth regime with different grain sizes and orientations than those produced by processes without a substrate bias. The influence of the RF bias is shown comparatively for reactive RF-sputtered ITO and reactive direct-current-sputtered TiN. The ITO layers exhibit an improved electrical resistivity of 0.5 mΩ cm and an optical absorption coefficient of 0.5 × 10{sup 4 }cm{supmore » −1} without substrate heating. Room-temperature sputtered TiN layers are deposited that possess a resistivity (0.1 mΩ cm) of 3 orders of magnitude lower than, and a density (5.4 g/cm{sup 3}) up to 45% greater than, those obtained from layers grown using the standard process without a substrate plasma.« less

Simulation of beam-induced plasma in gas-filled rf cavities

DOE PAGES

Yu, Kwangmin; Samulyak, Roman; Yonehara, Katsuya; ...

2017-03-07

Processes occurring in a radio-frequency (rf) cavity, filled with high pressure gas and interacting with proton beams, have been studied via advanced numerical simulations. Simulations support the experimental program on the hydrogen gas-filled rf cavity in the Mucool Test Area (MTA) at Fermilab, and broader research on the design of muon cooling devices. space, a 3D electromagnetic particle-in-cell (EM-PIC) code with atomic physics support, was used in simulation studies. Plasma dynamics in the rf cavity, including the process of neutral gas ionization by proton beams, plasma loading of the rf cavity, and atomic processes in plasma such as electron-ion andmore » ion-ion recombination and electron attachment to dopant molecules, have been studied. Here, through comparison with experiments in the MTA, simulations quantified several uncertain values of plasma properties such as effective recombination rates and the attachment time of electrons to dopant molecules. Simulations have achieved very good agreement with experiments on plasma loading and related processes. Lastly, the experimentally validated code space is capable of predictive simulations of muon cooling devices.« less

Improved Space Object Orbit Determination Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris, was simulated. For the space-based scenario the simulations showed a 20 130 % improvement of the accuracy of all orbital parameters when varying the frame rate from 1/3 fps, which is the fastest rate for a typical CCD detector, to 50 fps, which represents the highest rate of scientific CMOS cameras. Changing the epoch registration accuracy from a typical 20.0 ms for a mechanical shutter to 0.025 ms, the theoretical value for the electronic shutter of a CMOS camera, improved the orbit accuracy by 4 to 190 %. The ground-based scenario also benefit from the specific CMOS characteristics, but to a lesser extent.

Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process

NASA Technical Reports Server (NTRS)

Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.;

Low-cost TDRSS communications for NASA's long duration balloon project

NASA Technical Reports Server (NTRS)

Israel, David J.

1993-01-01

A new transponder and RF ground support equipment for the NASA Tracking and Data Relay Satellite System (TDRSS) intended to support long duration scientific balloon flights in Antarctica are described. The new balloon class transponder features a highly integrated spread spectrum receiver design based on programmable charge coupled device (CCD) correlators and digital signal processing chips. The correlator chip is a Lincoln Labs 4ABC with four CCD channels. The balloon transponder is capable of reporting an estimate of its input bit error rate using digital signal processing. The TDRSS user RF test set is based on a set of RF ground support equipment capable of providing both the RF communications and direct control and monitoring necessary for transponder testing and a two-way RF link for preflight testing.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Radio frequency heating for in-situ remediation of DNAPL

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kasevich, R.S.

1996-08-01

In-situ radio frequency (RF) heating technology for treating soils contaminated with dense nonaqueous phase liquids (DNAPLs) is described. RF imparts heat to non-conducting materials through the application of carefully controlled RF transmissions, improving contaminant flow characteristics and facilitating separation and removal from subsurface soils. The paper outlines advantages and limitations of RF remediation, process operations, general technology considerations, low permeability media considerations, commercial availability, and costs. Two case histories of RF remediation are briefly summarized. 13 refs., 10 figs.

[Process-oriented cost calculation in interventional radiology. A case study].

PubMed

Mahnken, A H; Bruners, P; Günther, R W; Rasche, C

2012-01-01

Currently used costing methods such as cost centre accounting do not sufficiently reflect the process-based resource utilization in medicine. The goal of this study was to establish a process-oriented cost assessment of percutaneous radiofrequency (RF) ablation of liver and lung metastases. In each of 15 patients a detailed task analysis of the primary process of hepatic and pulmonary RF ablation was performed. Based on these data a dedicated cost calculation model was developed for each primary process. The costs of each process were computed and compared with the revenue for in-patients according to the German diagnosis-related groups (DRG) system 2010. The RF ablation of liver metastases in patients without relevant comorbidities and a low patient complexity level results in a loss of EUR 588.44, whereas the treatment of patients with a higher complexity level yields an acceptable profit. The treatment of pulmonary metastases is profitable even in cases of additional expenses due to complications. Process-oriented costing provides relevant information that is needed for understanding the economic impact of treatment decisions. It is well suited as a starting point for economically driven process optimization and reengineering. Under the terms of the German DRG 2010 system percutaneous RF ablation of lung metastases is economically reasonable, while RF ablation of liver metastases in cases of low patient complexity levels does not cover the costs.

Novel approach for low-cost muzzle flash detection system

NASA Astrophysics Data System (ADS)

Voskoboinik, Asher

2008-04-01

A low-cost muzzle flash detection based on CMOS sensor technology is proposed. This low-cost technology makes it possible to detect various transient events with characteristic times between dozens of microseconds up to dozens of milliseconds while sophisticated algorithms successfully separate them from false alarms by utilizing differences in geometrical characteristics and/or temporal signatures. The proposed system consists of off-the-shelf smart CMOS cameras with built-in signal and image processing capabilities for pre-processing together with allocated memory for storing a buffer of images for further post-processing. Such a sensor does not require sending giant amounts of raw data to a real-time processing unit but provides all calculations in-situ where processing results are the output of the sensor. This patented CMOS muzzle flash detection concept exhibits high-performance detection capability with very low false-alarm rates. It was found that most false-alarms due to sun glints are from sources at distances of 500-700 meters from the sensor and can be distinguished by time examination techniques from muzzle flash signals. This will enable to eliminate up to 80% of falsealarms due to sun specular reflections in the battle field. Additional effort to distinguish sun glints from suspected muzzle flash signal is made by optimization of the spectral band in Near-IR region. The proposed system can be used for muzzle detection of small arms, missiles and rockets and other military applications.

Parallel Processing of Broad-Band PPM Signals

NASA Technical Reports Server (NTRS)

Gray, Andrew; Kang, Edward; Lay, Norman; Vilnrotter, Victor; Srinivasan, Meera; Lee, Clement

2010-01-01

A parallel-processing algorithm and a hardware architecture to implement the algorithm have been devised for timeslot synchronization in the reception of pulse-position-modulated (PPM) optical or radio signals. As in the cases of some prior algorithms and architectures for parallel, discrete-time, digital processing of signals other than PPM, an incoming broadband signal is divided into multiple parallel narrower-band signals by means of sub-sampling and filtering. The number of parallel streams is chosen so that the frequency content of the narrower-band signals is low enough to enable processing by relatively-low speed complementary metal oxide semiconductor (CMOS) electronic circuitry. The algorithm and architecture are intended to satisfy requirements for time-varying time-slot synchronization and post-detection filtering, with correction of timing errors independent of estimation of timing errors. They are also intended to afford flexibility for dynamic reconfiguration and upgrading. The architecture is implemented in a reconfigurable CMOS processor in the form of a field-programmable gate array. The algorithm and its hardware implementation incorporate three separate time-varying filter banks for three distinct functions: correction of sub-sample timing errors, post-detection filtering, and post-detection estimation of timing errors. The design of the filter bank for correction of timing errors, the method of estimating timing errors, and the design of a feedback-loop filter are governed by a host of parameters, the most critical one, with regard to processing very broadband signals with CMOS hardware, being the number of parallel streams (equivalently, the rate-reduction parameter).

CMOS image sensor with contour enhancement

NASA Astrophysics Data System (ADS)

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-10-01

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Geng, Zihan; Zhuang, Leimeng; Burla, Maurizio; Taddei, Caterina; Hoekman, Marcel; Leinse, Arne; Roeloffzen, Chris G. H.; Boller, Klaus-J.; Lowery, Arthur J.

2017-12-01

Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF) filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP)-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

Electrical properties of HfO2 high- k thin-film MOS capacitors for advanced CMOS technology

NASA Astrophysics Data System (ADS)

Khairnar, A. G.; Patil, L. S.; Salunke, R. S.; Mahajan, A. M.

2015-11-01

We deposited the hafnium dioxide (HfO2) thin films on p-Si (100) substrates. The thin films were deposited with deposition time variations, viz 2, 4, 7 and 20 min using RF-sputtering technique. The thickness and refractive index of the films were measured using spectroscopic ellipsometer. The thicknesses of the films were measured to be 13.7, 21.9, 35.38 and 92.2 nm and refractive indices of 1.90, 1.93, 1.99 and 1.99, respectively, of the films deposited for 2, 4, 7 and 20 min deposition time. The crystal structures of the deposited HfO2 thin films were determined using XRD spectra and showed the monoclinic structure, confirmed with the ICDD card no 34-0104. Aluminum metallization was carried to form the Al/HfO2/ p-Si MOS structures by using thermal evaporation system with electrode area of 12.56 × 10-4 cm2. Capacitance voltage and current voltage measurements were taken to know electrical behavior of these fabricated MOS structures. The electrical parameters such as dielectric constant, flat-band shift and interface trap density determined through CV measurement were 7.99, 0.11 V and 6.94 × 1011 eV-1 cm-2, respectively. The low leakage current density was obtained from IV measurement of fabricated MOS structure at 1.5 V is 4.85 × 10-10 Acm-2. Aforesaid properties explored the suitability of the fabricated HfO2 high- k-based MOS capacitors for advanced CMOS technology.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels

PubMed Central

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshinari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-01-01

In this paper we present a novel, quadruple well process developed in a modern 0.18 μm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 μm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency. PMID:27873817

Toward high fidelity spectral sensing and RF signal processing in silicon photonic and nano-opto-mechanical platforms

NASA Astrophysics Data System (ADS)

Siddiqui, Aleem; Reinke, Charles; Shin, Heedeuk; Jarecki, Robert L.; Starbuck, Andrew L.; Rakich, Peter

2017-05-01

The performance of electronic systems for radio-frequency (RF) spectrum analysis is critical for agile radar and communications systems, ISR (intelligence, surveillance, and reconnaissance) operations in challenging electromagnetic (EM) environments, and EM-environment situational awareness. While considerable progress has been made in size, weight, and power (SWaP) and performance metrics in conventional RF technology platforms, fundamental limits make continued improvements increasingly difficult. Alternatively, we propose employing cascaded transduction processes in a chip-scale nano-optomechanical system (NOMS) to achieve a spectral sensor with exceptional signal-linearity, high dynamic range, narrow spectral resolution and ultra-fast sweep times. By leveraging the optimal capabilities of photons and phonons, the system we pursue in this work has performance metrics scalable well beyond the fundamental limitations inherent to all electronic systems. In our device architecture, information processing is performed on wide-bandwidth RF-modulated optical signals by photon-mediated phononic transduction of the modulation to the acoustical-domain for narrow-band filtering, and then back to the optical-domain by phonon-mediated phase modulation (the reverse process). Here, we rely on photonics to efficiently distribute signals for parallel processing, and on phononics for effective and flexible RF-frequency manipulation. This technology is used to create RF-filters that are insensitive to the optical wavelength, with wide center frequency bandwidth selectivity (1-100GHz), ultra-narrow filter bandwidth (1-100MHz), and high dynamic range (70dB), which we will present. Additionally, using this filter as a building block, we will discuss current results and progress toward demonstrating a multichannel-filter with a bandwidth of < 10MHz per channel, while minimizing cumulative optical/acoustic/optical transduced insertion-loss to ideally < 10dB. These proposed metric represent significant improvements over RF-platforms.

Standing Up a Narcotic Confirmation Laboratory for the Russian Federation Ministry of Defense Nuclear Personnel Reliability Program

DOE Office of Scientific and Technical Information (OSTI.GOV)

LukyanenkoMD, Victor; Eisele, Gerhard R; Coates, Cameron W

2010-01-01

Through a cooperative effort between the U. S. Department of Energy and the Russian Federation (RF) Ministry of Defense (MOD) a Personnel Reliability Program (PRP) for the nuclear handlers within the RF MOD has been implemented. A key element in the RF MOD PRP is the detection and confirmation of narcotic use in subject military and civilian personnel. This paper describes the process of narcotics screening and testing in the RF MOD and explains the confirmation process once screening has shown a positive result. Issues of laboratory certification, employee certification, employee training, sample chain-of-custody, and equipment needs will be addressed.

RF Conditioning of the Photo-Cathode RF Gun at the Advanced Photon Source - NWA RF Measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, T. L.; DiMonte, N.; Nassiri, A.

A new S-band Photo-cathode (PC) gun was recently installed and RF conditioned at the Advanced Photon Source (APS) Injector Test-stand (ITS) at Argonne National Lab (ANL). The APS PC gun is a LCLS type gun fabricated at SLAC [1]. The PC gun was delivered to the APS in October 2013 and installed in the APS ITS in December 2013. At ANL, we developed a new method of fast detection and mitigation of the guns internal arcs during the RF conditioning process to protect the gun from arc damage and to RF condition more efficiently. Here, we report the results ofmore » RF measurements for the PC gun and an Auto-Restart method for high power RF conditioning.« less

Cortical depth dependent population receptive field attraction by spatial attention in human V1.

PubMed

Klein, Barrie P; Fracasso, Alessio; van Dijk, Jelle A; Paffen, Chris L E; Te Pas, Susan F; Dumoulin, Serge O

2018-04-27

Visual spatial attention concentrates neural resources at the attended location. Recently, we demonstrated that voluntary spatial attention attracts population receptive fields (pRFs) toward its location throughout the visual hierarchy. Theoretically, both a feed forward or feedback mechanism could underlie pRF attraction in a given cortical area. Here, we use sub-millimeter ultra-high field functional MRI to measure pRF attraction across cortical depth and assess the contribution of feed forward and feedback signals to pRF attraction. In line with previous findings, we find consistent attraction of pRFs with voluntary spatial attention in V1. When assessed as a function of cortical depth, we find pRF attraction in every cortical portion (deep, center and superficial), although the attraction is strongest in deep cortical portions (near the gray-white matter boundary). Following the organization of feed forward and feedback processing across V1, we speculate that a mixture of feed forward and feedback processing underlies pRF attraction in V1. Specifically, we propose that feedback processing contributes to the pRF attraction in deep cortical portions. Copyright © 2018. Published by Elsevier Inc.

Integrated 3D porous C-MoS2/nitrogen-doped graphene electrode for high capacity and prolonged stability lithium storage

NASA Astrophysics Data System (ADS)

Xie, D.; Tang, W. J.; Xia, X. H.; Wang, D. H.; Zhou, D.; Shi, F.; Wang, X. L.; Gu, C. D.; Tu, J. P.

2015-11-01

Scrupulous design and fabrication of advanced anode materials are of great importance for developing high-performance lithium ion batteries. Herein, we report a facile strategy for construction of free-standing and free-binder 3D porous carbon coated MoS2/nitrogen-doped graphene (C-MoS2/N-G) integrated electrode via a hydrothermal-induced self-assembly process. The preformed carbon coated MoS2 is strongly anchored on the porous nitrogen-doped graphene aerogel architecture. As an anode for lithium ion batteries, the C-MoS2/N-G electrode delivers a high first discharge capacity of 1600 mAh g-1 and maintains 900 mAh g-1 after 500 cycles at a current density of 200 mA g-1. Impressively, superior high-rate capability is achieved for the C-MoS2/N-G with a reversible capacity of 500 mAh g-1 at a high current density of 4000 mA g-1. Furthermore, the lithium storage mechanism of the obtained integrated electrode is investigated by ex-situ X-ray photoelectron spectroscopy and transmission electron microscopy in detail.

A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor.

PubMed

Yu, Changwei; Nie, Kaiming; Xu, Jiangtao; Gao, Jing

2016-09-23

In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6 . 47 × 10 - 8 J/line and 7 . 4 × 10 - 8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

Micro-scale characterization of a CMOS-based neutron detector for in-phantom measurements in radiation therapy

NASA Astrophysics Data System (ADS)

Arbor, Nicolas; Higueret, Stephane; Husson, Daniel

2018-04-01

The CMOS sensor AlphaRad has been designed at the IPHC Strasbourg for real-time monitoring of fast and thermal neutrons over a full energy spectrum. Completely integrated, highly transparent to photons and optimized for low power consumption, this sensor offers very interesting characteristics for the study of internal neutrons in radiation therapy with anthropomorphic phantoms. However, specific effects related to the CMOS metal substructure and to the charge collection process of low energy particles must be carefully estimated before being used for medical applications. We present a detailed characterization of the AlphaRad chip in the MeV energy range using proton and alpha micro-beam experiments performed at the AIFIRA facility (CENBG, Bordeaux). Two-dimensional maps of the charge collection were carried out on a micro-metric scale to be integrated into a Geant4 Monte Carlo simulation of the system. The gamma rejection, as well as the fast and thermal neutrons separation, were studied using both simulation and experimental data. The results highlight the potential of a future system based on CMOS sensor for in-phantom neutron detection in radiation therapies.

Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

NASA Astrophysics Data System (ADS)

Farahabadi, Payam Masoumi; Basaligheh, Ali; Saffari, Parvaneh; Moez, Kambiz

2017-06-01

This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm2 power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.

Subpixel mapping and test beam studies with a HV2FEI4v2 CMOS-Sensor-Hybrid Module for the ATLAS inner detector upgrade

NASA Astrophysics Data System (ADS)

Bisanz, T.; Große-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.

2017-08-01

The upgrade to the High Luminosity Large Hadron Collider will increase the instantaneous luminosity by more than a factor of 5, thus creating significant challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors since they allow for smaller pixel sizes and cost effective production. This article presents studies of a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer, forming a capacitively coupled pixel detector. The pixel pitch of the device under test is 33× 125 μm2, while the pixels of the read-out chip have a pitch of 50× 250 μm2. Three pixels of the CMOS device are connected to one read-out pixel, the information of which of these subpixels is hit is encoded in the amplitude of the output signal (subpixel encoding). Test beam measurements are presented that demonstrate the usability of this subpixel encoding scheme.

Variation and Defect Tolerance for Nano Crossbars

NASA Astrophysics Data System (ADS)

Tunc, Cihan

With the extreme shrinking in CMOS technology, quantum effects and manufacturing issues are getting more crucial. Hence, additional shrinking in CMOS feature size seems becoming more challenging, difficult, and costly. On the other hand, emerging nanotechnology has attracted many researchers since additional scaling down has been demonstrated by manufacturing nanowires, Carbon nanotubes as well as molecular switches using bottom-up manufacturing techniques. In addition to the progress in manufacturing, developments in architecture show that emerging nanoelectronic devices will be promising for the future system designs. Using nano crossbars, which are composed of two sets of perpendicular nanowires with programmable intersections, it is possible to implement logic functions. In addition, nano crossbars present some important features as regularity, reprogrammability, and interchangeability. Combining these features, researchers have presented different effective architectures. Although bottom-up nanofabrication can greatly reduce manufacturing costs, due to low controllability in the manufacturing process, some critical issues occur. Bottom- up nanofabrication process results in high variation compared to conventional top- down lithography used in CMOS technology. In addition, an increased failure rate is expected. Variation and defect tolerance methods used for conventional CMOS technology seem inadequate for adapting to emerging nano technology because the variation and the defect rate for emerging nano technology is much more than current CMOS technology. Therefore, variations and defect tolerance methods for emerging nano technology are necessary for a successful transition. In this work, in order to tolerate variations for crossbars, we introduce a framework that is established based on reprogrammability and interchangeability features of nano crossbars. This framework is shown to be applicable for both FET-based and diode-based nano crossbars. We present a characterization testing method which requires minimal number of test vectors. We formulate the variation optimization problem using Simulated Annealing with different optimization goals. Furthermore, we extend the framework for defect tolerance. Experimental results and comparison of proposed framework with exhaustive methods confirm its effectiveness for both variation and defect tolerance.

A 205GHz Amplifier in 90nm CMOS Technology

DTIC Science & Technology

2017-03-01

San Jose State University San Jose, CA, USA       Abstract: This paper presents a 205GHz amplifier drawing 43.4mA from a 0.9V power supply with...10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...reported in [2]. In this paper, two neutralization techniques, internal and external approaches, have been implemented to achieve higher power

Applications of Non-linearities in RF MEMS Switches and Resonators

NASA Astrophysics Data System (ADS)

Vummidi Murali, Krishna Prasad

The 21st century is emerging into an era of wireless ubiquity. To support this trend, the RF (Radio Frequency) front end must be capable of processing a range of wireless signals (cellular phone, data connectivity, broadcast TV, GPS positioning, etc.) spanning a total bandwidth of nearly 6 GHz. This warrants the need for multi-band/multi-mode radio architectures. For such architectures to satisfy the constraints on size, battery life, functionality and cost, the radio front-end must be made reconfigurable. RF-MEMS (RF Micro-Electro-Mechanical Systems) are seen as an enabling technology for such reconfigurable radios. RF-MEMS mainly include micromechanical switches (used in phase shifters, switched capacitor banks, impedance tuners etc.) and micromechanical resonators (used in tunable filters, oscillators, reference clocks etc.). MEMS technology also has the potential to be directly integrated into CMOS (Complementary metal-oxide semiconductor) ICs (Integrated Circuits) leading to further potential reductions of cost and size. However, RF-MEMS face challenges that must be addressed before they can gain widespread commercial acceptance. Relatively low switching speed, power handling, and high-voltage drive are some of the key issues in MEMS switches. Phase noise influenced by non-linearities, need for temperature compensation (especially Si based resonators), large start-up times, and aging are the key issues in Si MEMS Resonators. In this work potential solutions are proposed to address some of these key issues, specifically the reduction of high voltage drives in switches and the reduction of phase noise in MEMS resonators for timing applications. MEMS devices that are electrostatically actuated exhibit significant non-linearities. The origins of the non-linearities are both electrical (electrostatic actuation) and mechanical (dimensions and material properties). The influence of spring non-linearities (cubic and quadratic) on the performance of switches and resonators are studied. Gold electroplated fixed-fixed beams were fabricated to test the phenomenon of dynamic (or resonant) pull-in in shunt switches. The dynamic pull-in phenomenon was also tested on commercially fabricated lateral switches. It is shown that the resonant pull-in technique reduces the overall voltage required to actuate the switch. There is an additional reduction of total actuation voltage possible via applying an AC actuation signal at the correct non-linear resonant frequency. The demonstrated best case savings from operating at the non-linear resonance is 50% (for the lateral switch) and 60% (for the vertical switch) as compared to 25% and 40% respectively using a fixed frequency approach. However, the timing response for resonant pull-in has been experimentally shown to be slower than the static actuation. To reduce the switching time, a shifted-frequency method is proposed where the excitation frequency is shifted up or down by a discrete amount deltaO after a brief hold time. It was theoretically shown that the shifted-frequency method enables a minimum realizable switching time comparable to the static switching time for a given set of actuation frequencies. The influence of VDC on the effective non-linearities of a fixed-fixed beam is also studied. Based on the dimensions of the resonator and the type of resonance there is a certain VDC,Lin where the response is near linear (S ≈ 0). In the near-linear domain, the dynamic pull-in is the only upper bound to the amplitude of vibrations, and hence the amplitude of output current, thereby maximizing the power handling capacity of the resonator. Apart from maximizing the output current, it is essential to reduce the amplitude and phase variations of the displacement response which are due to noise mixing into frequency of interest, and are eventually manifested as output phase noise due to capacitive current nonlinearity. Two major aliasing schemes were analyzed and it was shown that the capacitive force non-linearity is the major source of mixing that causes the up-conversion of 1/f frequency into signal sidebands. The resonator's periodic response (displacement) is defined by a set of two first-order nonlinear ordinary differential equations that describe the modulation of amplitude and phase of the response. Frequency response curves of amplitude and frequency are determined from these modulation equations. The zero slope point on the amplitude resonance curve is the peak of the resonance curve where the phase (gammadc) of the response is +/-pi/2. For a strongly non-linear system, the resonance curves are skewed based on the amount of total non-linearity S. For systems that are strongly non-linear, the best region to operate the resonator is the fixed point that correspond to infinite slope (gammadc = +/-2pi/3) in the frequency response of the system. The best case phase noise response was analytically developed for such a fixed point. Theoretically at this fixed point, phase noise will have contributions only from 1/ fnoise and not from 1/f2 and 1/ f3. The resonators phase can be set by controlling the rest of the phase in the loop such that the total phase around the loop is zero or 2pi. In addition, this work has also developed an analytical model for a lateral MEMS switch fabricated in a commercial foundry that has the potential to be processed as MEMS on CMOS. This model accounts for trapezoidal cross sections of the electrodes and springs and also models electrostatic fringing as a function of the moving gap. The analytical model matches closely with the Finite Element (FEA) model.

Research-grade CMOS image sensors for demanding space applications

NASA Astrophysics Data System (ADS)

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2004-06-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Research-grade CMOS image sensors for demanding space applications

NASA Astrophysics Data System (ADS)

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2017-11-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar

PubMed Central

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun

2018-01-01

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256×13 real-time radar image display with a throughput of 28.2 frames per second. PMID:29621170

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

Possible layout solutions for the improvement of the dark rate of geiger mode avalanche structures in the GLOBALFOUNDRIES BCDLITE 0.18 μm CMOS technology

NASA Astrophysics Data System (ADS)

D'Ascenzo, N.; Xie, Q.

2018-04-01

Modern concepts of single photon or charged particle detection systems are based on geiger mode avalanche devices developed in CMOS technology. The key-problem encountered in the fabrication of these devices in CMOS is the dark rate level. The dark rate and single photon signal are not distinguishable. This sets also the limits of the application of geiger mode avalanche devices to single photon or charged particle detection systems. We report the design and fabrication of four possible layouts of these devices using the 0.18 μm BCDLite GLOBALFOUNDRIES process. The devices have an area of 50×50 μm2. They are characterized by a fast response time and an approximately 60 ns recovery time. The best topology exhibits an average dark rate as low as 3×103 kHz/mm2.

Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

NASA Astrophysics Data System (ADS)

Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

2017-05-01

The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

NASA Astrophysics Data System (ADS)

Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

2018-01-01

We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1-200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

PubMed

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

PubMed

Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

2015-10-23

A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm.

Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

PubMed Central

Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

2015-01-01

A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

Innovative monolithic detector for tri-spectral (THz, IR, Vis) imaging

NASA Astrophysics Data System (ADS)

Pocas, S.; Perenzoni, M.; Massari, N.; Simoens, F.; Meilhan, J.; Rabaud, W.; Martin, S.; Delplanque, B.; Imperinetti, P.; Goudon, V.; Vialle, C.; Arnaud, A.

2012-10-01

Fusion of multispectral images has been explored for many years for security and used in a number of commercial products. CEA-Leti and FBK have developed an innovative sensor technology that gathers monolithically on a unique focal plane arrays, pixels sensitive to radiation in three spectral ranges that are terahertz (THz), infrared (IR) and visible. This technology benefits of many assets for volume market: compactness, full CMOS compatibility on 200mm wafers, advanced functions of the CMOS read-out integrated circuit (ROIC), and operation at room temperature. The ROIC houses visible APS diodes while IR and THz detections are carried out by microbolometers collectively processed above the CMOS substrate. Standard IR bolometric microbridges (160x160 pixels) are surrounding antenna-coupled bolometers (32X32 pixels) built on a resonant cavity customized to THz sensing. This paper presents the different technological challenges achieved in this development and first electrical and sensitivity experimental tests.

An acquisition system for CMOS imagers with a genuine 10 Gbit/s bandwidth

NASA Astrophysics Data System (ADS)

Guérin, C.; Mahroug, J.; Tromeur, W.; Houles, J.; Calabria, P.; Barbier, R.

2012-12-01

This paper presents a high data throughput acquisition system for pixel detector readout such as CMOS imagers. This CMOS acquisition board offers a genuine 10 Gbit/s bandwidth to the workstation and can provide an on-line and continuous high frame rate imaging capability. On-line processing can be implemented either on the Data Acquisition Board or on the multi-cores workstation depending on the complexity of the algorithms. The different parts composing the acquisition board have been designed to be used first with a single-photon detector called LUSIPHER (800×800 pixels), developed in our laboratory for scientific applications ranging from nano-photonics to adaptive optics. The architecture of the acquisition board is presented and the performances achieved by the produced boards are described. The future developments (hardware and software) concerning the on-line implementation of algorithms dedicated to single-photon imaging are tackled.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

NASA Astrophysics Data System (ADS)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Decoding mobile-phone image sensor rolling shutter effect for visible light communications

NASA Astrophysics Data System (ADS)

Liu, Yang

2016-01-01

Optical wireless communication (OWC) using visible lights, also known as visible light communication (VLC), has attracted significant attention recently. As the traditional OWC and VLC receivers (Rxs) are based on PIN photo-diode or avalanche photo-diode, deploying the complementary metal-oxide-semiconductor (CMOS) image sensor as the VLC Rx is attractive since nowadays nearly every person has a smart phone with embedded CMOS image sensor. However, deploying the CMOS image sensor as the VLC Rx is challenging. In this work, we propose and demonstrate two simple contrast ratio (CR) enhancement schemes to improve the contrast of the rolling shutter pattern. Then we describe their processing algorithms one by one. The experimental results show that both the proposed CR enhancement schemes can significantly mitigate the high-intensity fluctuations of the rolling shutter pattern and improve the bit-error-rate performance.

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

Color sensor and neural processor on one chip

NASA Astrophysics Data System (ADS)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

A high efficiency PWM CMOS class-D audio power amplifier

NASA Astrophysics Data System (ADS)

Zhangming, Zhu; Lianxi, Liu; Yintang, Yang; Han, Lei

2009-02-01

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Electron Heating Mode Transitions in Nitrogen (13.56 and 40.68) MHz RF-CCPs

NASA Astrophysics Data System (ADS)

Erozbek Gungor, Ummugul; Bilikmen, Sinan Kadri; Akbar, Demiral

2015-09-01

Capacitively coupled radio frequency plasmas (RF-CCPs) are commonly used in plasma material processing. Parametrical structure of the plasma determines the demands of processing applications. For example; high density plasmas in gamma mode are mostly preferred for etching applications while stabile plasmas in gamma mode are usually used in sputtering applications. For this reason, characterization of the plasma is very essential before surface modification of the materials. In this work, analysis of electron heating mode transition in high frequency (40.68 MHz) RF-CCP was deeply investigated. The plasma was generated in a home-made (500 × 400 mm2) stainless steel cylindrical reactor in which two identical (200 mm in diameter) electrodes were placed with 40 mm interval. In addition, L-type automatic matching network system was connected to the 40.68 MHz RF generator to get high accuracy. Moreover, the pure (99.995 %) nitrogen was used as an activation gas on account of having an appreciable impression in plasma processing applications. Furthermore, diagnostic measurements of the plasma were done by using the Impedans Langmuir single and double probe systems. It was found that two transition points; α- γ (pressure dependent) and γ- α (RF power dependent) were observed in both medium and high RF-CCPs. As a result, the α- γ pressure transition increased, whereas the γ- α power transition remained constant by changing the RF frequency sources.

First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

NASA Astrophysics Data System (ADS)

Pernegger, H.; Bates, R.; Buttar, C.; Dalla, M.; van Hoorne, J. W.; Kugathasan, T.; Maneuski, D.; Musa, L.; Riedler, P.; Riegel, C.; Sbarra, C.; Schaefer, D.; Schioppa, E. J.; Snoeys, W.

2017-06-01

The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 1015neq/cm2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

NASA Astrophysics Data System (ADS)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

Variable self-powered light detection CMOS chip with real-time adaptive tracking digital output based on a novel on-chip sensor.

PubMed

Wang, HongYi; Fan, Youyou; Lu, Zhijian; Luo, Tao; Fu, Houqiang; Song, Hongjiang; Zhao, Yuji; Christen, Jennifer Blain

2017-10-02

This paper provides a solution for a self-powered light direction detection with digitized output. Light direction sensors, energy harvesting photodiodes, real-time adaptive tracking digital output unit and other necessary circuits are integrated on a single chip based on a standard 0.18 µm CMOS process. Light direction sensors proposed have an accuracy of 1.8 degree over a 120 degree range. In order to improve the accuracy, a compensation circuit is presented for photodiodes' forward currents. The actual measurement precision of output is approximately 7 ENOB. Besides that, an adaptive under voltage protection circuit is designed for variable supply power which may undulate with temperature and process.

A Microfluidic Cytometer for Complete Blood Count With a 3.2-Megapixel, 1.1- μm-Pitch Super-Resolution Image Sensor in 65-nm BSI CMOS.

PubMed

Liu, Xu; Huang, Xiwei; Jiang, Yu; Xu, Hang; Guo, Jing; Hou, Han Wei; Yan, Mei; Yu, Hao

2017-08-01

Based on a 3.2-Megapixel 1.1- μm-pitch super-resolution (SR) CMOS image sensor in a 65-nm backside-illumination process, a lens-free microfluidic cytometer for complete blood count (CBC) is demonstrated in this paper. Backside-illumination improves resolution and contrast at the device level with elimination of surface treatment when integrated with microfluidic channels. A single-frame machine-learning-based SR processing is further realized at system level for resolution correction with minimum hardware resources. The demonstrated microfluidic cytometer can detect the platelet cells (< 2 μm) required in CBC, hence is promising for point-of-care diagnostics.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2016-12-01

The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1977-01-01

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

Advancement of In-Flight Alumina Powder Spheroidization Process with Water Droplet Injection Using a Small Power DC-RF Hybrid Plasma Flow System

NASA Astrophysics Data System (ADS)

Jang, Juyong; Takana, Hidemasa; Park, Sangkyu; Nishiyama, Hideya

2012-09-01

The correlation between plasma thermofluid characteristics and alumina powder spheroidization processes with water droplet injection using a small power DC-RF hybrid plasma flow system was experimentally clarified. Micro-sized water droplets with a low water flow rate were injected into the tail of thermal plasma flow so as not to disturb the plasma flow directly. Injected water droplets were vaporized in the thermal plasma flow and were transported upstream in the plasma flow to the torch by the backflow. After dissociation of water, the production of hydrogen was detected by the optical emission spectroscopy in the downstream RF plasma flow. The emission area of the DC plasma jet expanded and elongated in the vicinity of the RF coils. Additionally, the emission area of RF plasma flow enlarged and was visible as red emission in the downstream RF plasma flow in the vicinity below the RF coils due to hydrogen production. Therefore, the plasma flow mixed with produced hydrogen increased the plasma enthalpy and the highest spheroidization rate of 97% was obtained at a water flow rate of 15 Sm l/min and an atomizing gas flow rate of 8 S l/min using a small power DC-RF hybrid plasma flow system.

A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

PubMed

Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

2014-12-01

This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

High-Speed Scalable Silicon-MoS2 P-N Heterojunction Photodetectors

PubMed Central

Dhyani, Veerendra; Das, Samaresh

2017-01-01

Two-dimensional molybdenum disulfide (MoS2) is a promising material for ultrasensitive photodetector owing to its favourable band gap and high absorption coefficient. However, their commercial applications are limited by the lack of high quality p-n junction and large wafer scale fabrication process. A high speed Si/MoS2 p-n heterojunction photodetector with simple and CMOS compatible approach has been reported here. The large area MoS2 thin film on silicon platform has been synthesized by sulfurization of RF-sputtered MoO3 films. The fabricated molecular layers of MoS2 on silicon offers high responsivity up to 8.75 A/W (at 580 nm and 3 V bias) with ultra-fast response of 10 μsec (rise time). Transient measurements of Si/MoS2 heterojunction under the modulated light reveal that the devices can function up to 50 kHz. The Si/MoS2 heterojunction is found to be sensitive to broadband wavelengths ranging from visible to near-infrared light with maximum detectivity up to ≈1.4 × 1012 Jones (2 V bias). Reproducible low dark current and high responsivity from over 20 devices in the same wafer has been measured. Additionally, the MoS2/Si photodetectors exhibit excellent stability in ambient atmosphere. PMID:28281652

A microfluidic microprocessor: controlling biomimetic containers and cells using hybrid integrated circuit/microfluidic chips.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Westervelt, Robert M

2010-11-07

We present an integrated platform for performing biological and chemical experiments on a chip based on standard CMOS technology. We have developed a hybrid integrated circuit (IC)/microfluidic chip that can simultaneously control thousands of living cells and pL volumes of fluid, enabling a wide variety of chemical and biological tasks. Taking inspiration from cellular biology, phospholipid bilayer vesicles are used as robust picolitre containers for reagents on the chip. The hybrid chip can be programmed to trap, move, and porate individual living cells and vesicles and fuse and deform vesicles using electric fields. The IC spatially patterns electric fields in a microfluidic chamber using 128 × 256 (32,768) 11 × 11 μm(2) metal pixels, each of which can be individually driven with a radio frequency (RF) voltage. The chip's basic functions can be combined in series to perform complex biological and chemical tasks and can be performed in parallel on the chip's many pixels for high-throughput operations. The hybrid chip operates in two distinct modes, defined by the frequency of the RF voltage applied to the pixels: Voltages at MHz frequencies are used to trap, move, and deform objects using dielectrophoresis and voltages at frequencies below 1 kHz are used for electroporation and electrofusion. This work represents an important step towards miniaturizing the complex chemical and biological experiments used for diagnostics and research onto automated and inexpensive chips.

Substrate noise coupling: a pain for mixed-signal systems (Keynote Address)

NASA Astrophysics Data System (ADS)

Wambacq, Piet; Van der Plas, Geert; Donnay, Stephane; Badaroglu, Mustafa; Soens, Charlotte

2005-06-01

Crosstalk from digital to analog in mixed-signal ICs is recognized as one of the major roadblocks for systems-on-chip (SoC) in future CMOS technologies. This crosstalk mainly happens via the semiconducting silicon substrate, which is usually treated as a ground node by analog and RF designers. The substrate noise coupling problem leads more and more to malfunctioning or extra design iterations. One of the reasons is that the phenomenon of substrate noise coupling is difficult to model and hence difficult to understand. It can be caused by the switching of thousands or millions of gates and depends on layout details. From the generation side (the digital domain), coping with the large amount of noise generators can be solved by macromodeling. On the other hand, the impact of substrate noise on the analog circuits requires careful modeling at the level of transistors and parasitics of layout, power supply, package, PCB, Comparison to measurements of macromodeling at the digital side and careful modeling at the analog side, shows that both the generation and the impact of substrate noise can be predicted with an accuracy of a few dB. In addition, this combination of macromodeling at the digital side and careful modeling at the analog side leads to an understanding of the problem, which can be used for digital low-noise design techniques to minimize the generation of noise, and substrate noise immune design of analog/RF circuits.

Energy Saving Glass Lamination via Selective Radio Frequency Heating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Allan, Shawn M; Baranova, Inessa; Poley, Joseph

2012-02-27

This project focused on advancing radio-frequency (RF) lamination technology closer to commercial implementation, in order to reduce the energy intensity of glass lamination by up to 90%. Lamination comprises a wide range of products including autoglass, architectural safety and innovative design glass, transparent armor (e.g. bullet proof glass), smart glass, mirrors, and encapsulation of photovoltaics. Lamination is also the fastest growing segment of glass manufacturing, with photovoltaics, architectural needs, and an anticipated transition to laminated side windows in vehicles. The state-of-the-art for glass lamination is to use autoclaves, which apply heat and uniform gas pressure to bond the laminates overmore » the course of 1 to 18 hours. Laminates consist of layers of glass or other materials bonded with vinyl or urethane interlayers. In autoclaving, significant heat energy is lost heating the chamber, pressurized air, glass racks, and the glass. In RF lamination, the heat is generated directly in the vinyl interlayer, causing it to heat and melt quickly, in just 1 to 10 minutes, without significantly heating the glass or the equipment. The main purpose of this project was to provide evidence that low energy, rapid RF lamination quality met the same standards as conventionally autoclaved windows. The development of concepts for laminating curved glass with RF lamination was a major goal. Other primary goals included developing a stronger understanding of the lamination product markets described above, and to refine the potential benefits of commercial implementation. The scope of the project was to complete implementation concept studies in preparation for continuation into advanced development, pilot studies, and commercial implementation. The project consisted of 6 main tasks. The first dealt with lamination with poly-vinyl butyral (PVB) interlayers, which prior work had shown difficulties in achieving good quality laminates, working with Pilkington North America. The second task dealt with a study of current lamination processes in the various laminate industries, and development of concepts for integrating RF lamination into new or existing processes. The third task explored the use of a non-destructive technique for analyzing laminate adhesion with the University of Illinois at Urbana-Champaign. The fourth task focused on developing concepts for curved glass lamination using RF lamination. The fifth and sixth tasks together comprised an analysis of laminate product markets, ranking for applicability and commercialization potential, and the development of commercialization strategies for those products. In addition, throughout the project as new experimental data and conventional process data were obtained, the benefits analysis of RF lamination was refined. The goals of the project described above were achieved, positioning RF lamination for the next stage growth envisioned in the original Industrial Grand Challenge proposal. Working with Pilkington North America, lamination of flat autoglass with PVB was achieved, meeting all 16 stringent industry tests. In particular, PVB laminates made with RF lamination passed environmental tests including the high temperature, 120°C bake test, without significant formation of bubbles (defects). The adhesion of PVB to glass was measured using the pummel method. Adhesion values ranging from 1 to 7 out of 10 were obtained. The significant process parameters affecting the environmental and adhesion performance were identified through a designed experiment. Pre-lamination process variables including PVB storage humidity and the de-airing process (vacuum or nip rolling) were significant, as well as the level of pressure applied to the laminate during the RF process. Analysis of manufacturing with RF lamination equipment, based on the processes developed indicated that 3 RF presses could replace a typical auto-industry autoclave to achieve equal or greater throughput with possibly less capital cost and smaller footprint. Concepts for curved lamination identifying castable molds for prototyping were developed, which allowed Ceralink to obtain commitment to begin curved tooling development. The project significantly helped to advance RF lamination past the feasibility and novelty stage and into the realm of commercial acceptance as a viable alternative to autoclaves. The demonstration of autoclave-quality autoglass produced in just 1 minute with RF lamination, with validation by Pilkington, has fueled industry motivation to seriously consider RF lamination. The industry and other contacts and outreach made in the study of laminate markets (including 3 technical publications and 5 conference presentations), has resulted in a recent surge in RF lamination activity.« less

Energy Saving Glass Lamination via Selective Radio Frequency Heating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Allan, Shawn M.

2012-02-27

This project focused on advancing radio-frequency (RF) lamination technology closer to commercial implementation, in order to reduce the energy intensity of glass lamination by up to 90%. Lamination comprises a wide range of products including autoglass, architectural safety and innovative design glass, transparent armor (e.g. bullet proof glass), smart glass, mirrors, and encapsulation of photovoltaics. Lamination is also the fastest growing segment of glass manufacturing, with photovoltaics, architectural needs, and an anticipated transition to laminated side windows in vehicles. The state-of-the-art for glass lamination is to use autoclaves, which apply heat and uniform gas pressure to bond the laminates overmore » the course of 1 to 18 hours. Laminates consist of layers of glass or other materials bonded with vinyl or urethane interlayers. In autoclaving, significant heat energy is lost heating the chamber, pressurized air, glass racks, and the glass. In RF lamination, the heat is generated directly in the vinyl interlayer, causing it to heat and melt quickly, in just 1 to 10 minutes, without significantly heating the glass or the equipment. The main purpose of this project was to provide evidence that low energy, rapid RF lamination quality met the same standards as conventionally autoclaved windows. The development of concepts for laminating curved glass with RF lamination was a major goal. Other primary goals included developing a stronger understanding of the lamination product markets described above, and to refine the potential benefits of commercial implementation. The scope of the project was to complete implementation concept studies in preparation for continuation into advanced development, pilot studies, and commercial implementation. The project consisted of 6 main tasks. The first dealt with lamination with poly-vinyl butyral (PVB) interlayers, which prior work had shown difficulties in achieving good quality laminates, working with Pilkington North America. The second task dealt with a study of current lamination processes in the various laminate industries, and development of concepts for integrating RF lamination into new or existing processes. The third task explored the use of a non-destructive technique for analyzing laminate adhesion with the University of Illinois at Urbana-Champaign. The fourth task focused on developing concepts for curved glass lamination using RF lamination. The fifth and sixth tasks together comprised an analysis of laminate product markets, ranking for applicability and commercialization potential, and the development of commercialization strategies for those products. In addition, throughout the project as new experimental data and conventional process data were obtained, the benefits analysis of RF lamination was refined. The goals of the project described above were achieved, positioning RF lamination for the next stage growth envisioned in the original Industrial Grand Challenge proposal. Working with Pilkington North America, lamination of flat autoglass with PVB was achieved, meeting all 16 stringent industry tests. In particular, PVB laminates made with RF lamination passed environmental tests including the high temperature, 120 C bake test, without significant formation of bubbles (defects). The adhesion of PVB to glass was measured using the pummel method. Adhesion values ranging from 1 to 7 out of 10 were obtained. The significant process parameters affecting the environmental and adhesion performance were identified through a designed experiment. Pre-lamination process variables including PVB storage humidity and the de-airing process (vacuum or nip rolling) were significant, as well as the level of pressure applied to the laminate during the RF process. Analysis of manufacturing with RF lamination equipment, based on the processes developed indicated that 3 RF presses could replace a typical auto-industry autoclave to achieve equal or greater throughput with possibly less capital cost and smaller footprint. Concepts for curved lamination identifying castable molds for prototyping were developed, which allowed Ceralink to obtain commitment to begin curved tooling development. The project significantly helped to advance RF lamination past the feasibility and novelty stage and into the realm of commercial acceptance as a viable alternative to autoclaves. The demonstration of autoclave-quality autoglass produced in just 1 minute with RF lamination, with validation by Pilkington, has fueled industry motivation to seriously consider RF lamination. The industry and other contacts and outreach made in the study of laminate markets (including 3 technical publications and 5 conference presentations), has resulted in a recent surge in RF lamination activity.« less

A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

PubMed Central

Chen, Chun-Chi; Lin, Shih-Hao

2013-01-01

This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-μm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 μW at a sample rate of 10 samples/s. PMID:23385403

Fabrication and characterization of SU-8-based capacitive micromachined ultrasonic transducer for airborne applications

NASA Astrophysics Data System (ADS)

Joseph, Jose; Singh, Shiv Govind; Vanjari, Siva Rama Krishna

2018-01-01

We present a successful fabrication and characterization of a capacitive micromachined ultrasonic transducer (CMUT) with SU-8 as the membrane material. The goal of this research is to develop a post-CMOS compatible CMUT that can be monolithically integrated with the CMOS circuitry. The fabrication is based on a simple, three mask process, with all wet etching steps involved so that the device can be realized with minimal laboratory conditions. The maximum temperature involved in the whole process flow was 140°C, and hence, it is post-CMOS compatible. The fabricated device exhibited a resonant frequency of 835 kHz with bandwidth 62 kHz, when characterized in air. The pull-in and snapback characteristics of the device were analyzed. The influence of membrane radius on the center frequency and bandwidth was also experimentally evaluated by fabricating CMUTs with membrane radius varying from 30 to 54 μm with an interval of 4 μm. These devices were vibrating at frequencies from 5.2 to 1.8 MHz with an average Q-factor of 23.41. Acoustic characterization of the fabricated devices was performed in air, demonstrating the applicability of SU-8 CMUTs in airborne applications.

A robust color signal processing with wide dynamic range WRGB CMOS image sensor

NASA Astrophysics Data System (ADS)

Kawada, Shun; Kuroda, Rihito; Sugawa, Shigetoshi

2011-01-01

We have developed a robust color reproduction methodology by a simple calculation with a new color matrix using the formerly developed wide dynamic range WRGB lateral overflow integration capacitor (LOFIC) CMOS image sensor. The image sensor was fabricated through a 0.18 μm CMOS technology and has a 45 degrees oblique pixel array, the 4.2 μm effective pixel pitch and the W pixels. A W pixel was formed by replacing one of the two G pixels in the Bayer RGB color filter. The W pixel has a high sensitivity through the visible light waveband. An emerald green and yellow (EGY) signal is generated from the difference between the W signal and the sum of RGB signals. This EGY signal mainly includes emerald green and yellow lights. These colors are difficult to be reproduced accurately by the conventional simple linear matrix because their wave lengths are in the valleys of the spectral sensitivity characteristics of the RGB pixels. A new linear matrix based on the EGY-RGB signal was developed. Using this simple matrix, a highly accurate color processing with a large margin to the sensitivity fluctuation and noise has been achieved.

A CMOS active pixel sensor for retinal stimulation

NASA Astrophysics Data System (ADS)

Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

2006-02-01

Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

PubMed

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

PubMed Central

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, James; Gunawan, Ferry; Dosluoglu, Taner; Tower, John; McCaffrey, Niel

2002-08-01

High performance CMOS pixels are introduced; and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantagesof these options for scientific CMOS pixels are examined.Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, J.; Gunawan, F.; Dosluoglu, T.; Tower, J.; McCaffrey, N.

High performance CMOS pixels are introduced and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantages of these options for scientific CMOS pixels are examined. Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Optical design of microlens array for CMOS image sensors

NASA Astrophysics Data System (ADS)

Zhang, Rongzhu; Lai, Liping

2016-10-01

The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Process control monitoring systems, industrial plants, and process control monitoring methods

DOEpatents

Skorpik, James R [Kennewick, WA; Gosselin, Stephen R [Richland, WA; Harris, Joe C [Kennewick, WA

2010-09-07

A system comprises a valve; a plurality of RFID sensor assemblies coupled to the valve to monitor a plurality of parameters associated with the valve; a control tag configured to wirelessly communicate with the respective tags that are coupled to the valve, the control tag being further configured to communicate with an RF reader; and an RF reader configured to selectively communicate with the control tag, the reader including an RF receiver. Other systems and methods are also provided.

High-κ gate dielectrics: Current status and materials properties considerations

NASA Astrophysics Data System (ADS)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications

PubMed Central

Park, Keunyeol; Song, Minkyu

2018-01-01

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm2 with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency. PMID:29495273

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications.

PubMed

Park, Keunyeol; Song, Minkyu; Kim, Soo Youn

2018-02-24

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm² with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency.

Digital approach to stabilizing optical frequency combs and beat notes of CW lasers

NASA Astrophysics Data System (ADS)

Čížek, Martin; Číp, Ondřej; Å míd, Radek; Hrabina, Jan; Mikel, Břetislav; Lazar, Josef

2013-10-01

In cases when it is necessary to lock optical frequencies generated by an optical frequency comb to a precise radio frequency (RF) standard (GPS-disciplined oscillator, H-maser, etc.) the usual practice is to implement phase and frequency-locked loops. Such system takes the signal generated by the RF standard (usually 10 MHz or 100 MHz) as a reference and stabilizes the repetition and offset frequencies of the comb contained in the RF output of the f-2f interferometer. These control loops are usually built around analog electronic circuits processing the output signals from photo detectors. This results in transferring the stability of the standard from RF to optical frequency domain. The presented work describes a different approach based on digital signal processing and software-defined radio algorithms used for processing the f-2f and beat-note signals. Several applications of digital phase and frequency locks to a RF standard are demonstrated: the repetition (frep) and offset frequency (fceo) of the comb, and the frequency of the beat note between a CW laser source and a single component of the optical frequency comb spectrum.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

PubMed

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.