Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

PubMed

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

PubMed

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.

Organic printed photonics: From microring lasers to integrated circuits

PubMed Central

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-01-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

Organic printed photonics: From microring lasers to integrated circuits.

PubMed

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-09-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system

NASA Astrophysics Data System (ADS)

Liu, Yang; Wang, Sheng; Liu, Huaping; Peng, Lian-Mao

2017-06-01

Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

Computer-aided design of large-scale integrated circuits - A concept

NASA Technical Reports Server (NTRS)

Schansman, T. T.

1971-01-01

Circuit design and mask development sequence are improved by using general purpose computer with interactive graphics capability establishing efficient two way communications link between design engineer and system. Interactive graphics capability places design engineer in direct control of circuit development.

Packaging Of Control Circuits In A Robot Arm

NASA Technical Reports Server (NTRS)

Kast, William

1994-01-01

Packaging system houses and connects control circuitry mounted on circuit boards within shoulder, upper section, and lower section of seven-degree-of-freedom robot arm. Has modular design that incorporates surface-mount technology, multilayer circuit boards, large-scale integrated circuits, and multi-layer flat cables between sections for compactness. Three sections of robot arm contain circuit modules in form of stardardized circuit boards. Each module contains two printed-circuit cards, one of each face.

Integrated Circuit-Based Biofabrication with Common Biomaterials for Probing Cellular Biomechanics.

PubMed

Sung, Chun-Yen; Yang, Chung-Yao; Yeh, J Andrew; Cheng, Chao-Min

2016-02-01

Recent advances in bioengineering have enabled the development of biomedical tools with modifiable surface features (small-scale architecture) to mimic extracellular matrices and aid in the development of well-controlled platforms that allow for the application of mechanical stimulation for studying cellular biomechanics. An overview of recent developments in common biomaterials that can be manufactured using integrated circuit-based biofabrication is presented. Integrated circuit-based biofabrication possesses advantages including mass and diverse production capacities for fabricating in vitro biomedical devices. This review highlights the use of common biomaterials that have been most frequently used to study cellular biomechanics. In addition, the influence of various small-scale characteristics on common biomaterial surfaces for a range of different cell types is discussed. Copyright © 2015 Elsevier Ltd. All rights reserved.

Photonic Integrated Circuits

NASA Technical Reports Server (NTRS)

Krainak, Michael; Merritt, Scott

2016-01-01

Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

PubMed

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Making A D-Latch Sensitive To Alpha Particles

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Nixon, Robert H.

1994-01-01

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

On-chip detection of non-classical light by scalable integration of single-photon detectors

PubMed Central

Najafi, Faraz; Mower, Jacob; Harris, Nicholas C.; Bellei, Francesco; Dane, Andrew; Lee, Catherine; Hu, Xiaolong; Kharel, Prashanta; Marsili, Francesco; Assefa, Solomon; Berggren, Karl K.; Englund, Dirk

2015-01-01

Photonic-integrated circuits have emerged as a scalable platform for complex quantum systems. A central goal is to integrate single-photon detectors to reduce optical losses, latency and wiring complexity associated with off-chip detectors. Superconducting nanowire single-photon detectors (SNSPDs) are particularly attractive because of high detection efficiency, sub-50-ps jitter and nanosecond-scale reset time. However, while single detectors have been incorporated into individual waveguides, the system detection efficiency of multiple SNSPDs in one photonic circuit—required for scalable quantum photonic circuits—has been limited to <0.2%. Here we introduce a micrometer-scale flip-chip process that enables scalable integration of SNSPDs on a range of photonic circuits. Ten low-jitter detectors are integrated on one circuit with 100% device yield. With an average system detection efficiency beyond 10%, and estimated on-chip detection efficiency of 14–52% for four detectors operated simultaneously, we demonstrate, to the best of our knowledge, the first on-chip photon correlation measurements of non-classical light. PMID:25575346

On-chip synthesis of circularly polarized emission of light with integrated photonic circuits.

PubMed

He, Li; Li, Mo

2014-05-01

The helicity of circularly polarized (CP) light plays an important role in the light-matter interaction in magnetic and quantum material systems. Exploiting CP light in integrated photonic circuits could lead to on-chip integration of novel optical helicity-dependent devices for applications ranging from spintronics to quantum optics. In this Letter, we demonstrate a silicon photonic circuit coupled with a 2D grating emitter operating at a telecom wavelength to synthesize vertically emitting, CP light from a quasi-TE waveguide mode. Handedness of the emitted circular polarized light can be thermally controlled with an integrated microheater. The compact device footprint enables a small beam diameter, which is desirable for large-scale integration.

Integrated Electrode Arrays for Neuro-Prosthetic Implants

NASA Technical Reports Server (NTRS)

Brandon, Erik; Mojarradi, Mohammede

2003-01-01

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Development of Nanomechanical Sensors for Breast Cancer Biomarkers

DTIC Science & Technology

2008-06-01

semiconductor industry in developing large scale integrated circuits at very lost cost can lead to similar breakthroughs in array sensors for biomolecules of...insulated from the serum or buffer. The entire device is mounted onto a semiconductor chip carrier, for easy integration with electronics. Figure 3...Keithley 2400 source meter. The ac modulation and the dc bias are added by a noninverting summing circuit, which is integrated with the preamplifier

75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-08-23

... Integrated Circuit Semiconductor Chips and Products Containing the Same; Notice of Commission Decision Not To... semiconductor chips and products containing same by reason of infringement of certain claims of U.S. Patent Nos. 5,933,364 and 6,834,336. The complaint further alleges the existence of a domestic industry. The...

Maximum Temperature Detection System for Integrated Circuits

NASA Astrophysics Data System (ADS)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Design of micro-ring optical sensors and circuits for integration on optical printed circuit boards (O-PCBs)

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, Hyun S.; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.

2007-05-01

We report on the design of micro-ring resonator optical sensors for integration on what we call optical printed circuit boards (O-PCBs). The objective is to realize application-specific O-PCBs, either on hard board or on flexible board, by integrating micro/nano-scale optical sensors for compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly processing of information. The O-PCBs consist of two-dimensional planar arrays of micro/nano-scale optical wires, circuits and devices that are interconnected and integrated to perform the functions of sensing and then storing, transporting, processing, switching, routing and distributing optical signals that have been collected by means of sensors. For fabrication, the polymer and organic optical wires and waveguides are first fabricated on a board and are used to interconnect and integrate sensors and other micro/ nano-scale photonic devices. Here, in our study, we focus on the sensors based on the micro-ring structures. We designed bio-sensors using silicon based micro-ring resonator. We investigate the characteristics such as sensitivity and selectivity (or quality factor) of micro-ring resonator for their use in bio-sensing application. We performed simulation studies on the quality factor of micro-ring resonators by varying the radius of the ring resonators and the separation between adjacent waveguides. We introduce the effective coupling coefficient as a realistic value to describe the strength of the coupling in micro-ring resonators.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

PubMed

Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

2016-01-21

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

Spiers Memorial Lecture. Molecular mechanics and molecular electronics.

PubMed

Beckman, Robert; Beverly, Kris; Boukai, Akram; Bunimovich, Yuri; Choi, Jang Wook; DeIonno, Erica; Green, Johnny; Johnston-Halperin, Ezekiel; Luo, Yi; Sheriff, Bonnie; Stoddart, Fraser; Heath, James R

2006-01-01

We describe our research into building integrated molecular electronics circuitry for a diverse set of functions, and with a focus on the fundamental scientific issues that surround this project. In particular, we discuss experiments aimed at understanding the function of bistable rotaxane molecular electronic switches by correlating the switching kinetics and ground state thermodynamic properties of those switches in various environments, ranging from the solution phase to a Langmuir monolayer of the switching molecules sandwiched between two electrodes. We discuss various devices, low bit-density memory circuits, and ultra-high density memory circuits that utilize the electrochemical switching characteristics of these molecules in conjunction with novel patterning methods. We also discuss interconnect schemes that are capable of bridging the micrometre to submicrometre length scales of conventional patterning approaches to the near-molecular length scales of the ultra-dense memory circuits. Finally, we discuss some of the challenges associated with fabricated ultra-dense molecular electronic integrated circuits.

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

NASA Technical Reports Server (NTRS)

Aanstoos, J. V.; Snyder, W. E.

1981-01-01

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Scaling of graphene integrated circuits.

PubMed

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

PubMed

Penchovsky, Robert

2012-10-19

Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

Integrated Circuit Stellar Magnitude Simulator

ERIC Educational Resources Information Center

Blackburn, James A.

1978-01-01

Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

Neural Networks For Demodulation Of Phase-Modulated Signals

NASA Technical Reports Server (NTRS)

Altes, Richard A.

1995-01-01

Hopfield neural networks proposed for demodulating quadrature phase-shift-keyed (QPSK) signals carrying digital information. Networks solve nonlinear integral equations prior demodulation circuits cannot solve. Consists of set of N operational amplifiers connected in parallel, with weighted feedback from output terminal of each amplifier to input terminals of other amplifiers. Used to solve signal processing problems. Implemented as analog very-large-scale integrated circuit that achieves rapid convergence. Alternatively, implemented as digital simulation of such circuit. Also used to improve phase estimation performance over that of phase-locked loop.

Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

PubMed

Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

2016-01-01

A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits.

PubMed

Ghavami, Behnam; Raji, Mohsen; Pedram, Hossein

2011-08-26

Carbon nanotube field-effect transistors (CNFETs) show great promise as building blocks of future integrated circuits. However, synthesizing single-walled carbon nanotubes (CNTs) with accurate chirality and exact positioning control has been widely acknowledged as an exceedingly complex task. Indeed, density and chirality variations in CNT growth can compromise the reliability of CNFET-based circuits. In this paper, we present a novel statistical compact model to estimate the failure probability of CNFETs to provide some material and process guidelines for the design of CNFETs in gigascale integrated circuits. We use measured CNT spacing distributions within the framework of detailed failure analysis to demonstrate that both the CNT density and the ratio of metallic to semiconducting CNTs play dominant roles in defining the failure probability of CNFETs. Besides, it is argued that the large-scale integration of these devices within an integrated circuit will be feasible only if a specific range of CNT density with an acceptable ratio of semiconducting to metallic CNTs can be adjusted in a typical synthesis process.

Readout circuit with novel background suppression for long wavelength infrared focal plane arrays

NASA Astrophysics Data System (ADS)

Xie, L.; Xia, X. J.; Zhou, Y. F.; Wen, Y.; Sun, W. F.; Shi, L. X.

2011-02-01

In this article, a novel pixel readout circuit using a switched-capacitor integrator mode background suppression technique is presented for long wavelength infrared focal plane arrays. This circuit can improve dynamic range and signal-to-noise ratio by suppressing the large background current during integration. Compared with other background suppression techniques, the new background suppression technique is less sensitive to the process mismatch and has no additional shot noise. The proposed circuit is theoretically analysed and simulated while taking into account the non-ideal characteristics. The result shows that the background suppression non-uniformity is ultra-low even for a large process mismatch. The background suppression non-uniformity of the proposed circuit can also remain very small with technology scaling.

Hierarchical hybrid control of manipulators: Artificial intelligence in large scale integrated circuits

NASA Technical Reports Server (NTRS)

Greene, P. H.

1972-01-01

Both in practical engineering and in control of muscular systems, low level subsystems automatically provide crude approximations to the proper response. Through low level tuning of these approximations, the proper response variant can emerge from standardized high level commands. Such systems are expressly suited to emerging large scale integrated circuit technology. A computer, using symbolic descriptions of subsystem responses, can select and shape responses of low level digital or analog microcircuits. A mathematical theory that reveals significant informational units in this style of control and software for realizing such information structures are formulated.

VLSI (Very Large Scale Integrated) Design of a 16 Bit Very Fast Pipelined Carry Look Ahead Adder.

DTIC Science & Technology

1983-09-01

the ability for systems engineers to custom design digital integrated circuits. Until recently, the design of integrated circuits has been...traditionally carried out by a select group of logic designers working in semiconductor laboratories. Systems engineers had to "make do" or "fit in" the...products of these labs to realize their designs. The systems engineers had little participation in the actual design of the chip. The MED and CONWAY design

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Reproducible Operating Margins on a 72800-Device Digital Superconducting Chip (Open Access)

DTIC Science & Technology

2015-10-28

superconductor digital logic. Keywords: flux trapping, yield, digital Superconductor digital technology offers fundamental advantages over conventional...trapping in the superconductor films can degrade or preclude correct circuit operation. Scaling superconductor technology is now possible due to recent...advances in circuit design embodied in reciprocal quantum logic (RQL) [2, 3] and recent advances in superconductor integrated circuit fabrication, which

Photolithography-Based Patterning of Liquid Metal Interconnects for Monolithically Integrated Stretchable Circuits.

PubMed

Park, Chan Woo; Moon, Yu Gyeong; Seong, Hyejeong; Jung, Soon Won; Oh, Ji-Young; Na, Bock Soon; Park, Nae-Man; Lee, Sang Seok; Im, Sung Gap; Koo, Jae Bon

2016-06-22

We demonstrate a new patterning technique for gallium-based liquid metals on flat substrates, which can provide both high pattern resolution (∼20 μm) and alignment precision as required for highly integrated circuits. In a very similar manner as in the patterning of solid metal films by photolithography and lift-off processes, the liquid metal layer painted over the whole substrate area can be selectively removed by dissolving the underlying photoresist layer, leaving behind robust liquid patterns as defined by the photolithography. This quick and simple method makes it possible to integrate fine-scale interconnects with preformed devices precisely, which is indispensable for realizing monolithically integrated stretchable circuits. As a way for constructing stretchable integrated circuits, we propose a hybrid configuration composed of rigid device regions and liquid interconnects, which is constructed on a rigid substrate first but highly stretchable after being transferred onto an elastomeric substrate. This new method can be useful in various applications requiring both high-resolution and precisely aligned patterning of gallium-based liquid metals.

Interfacing spin qubits in quantum dots and donors—hot, dense, and coherent

NASA Astrophysics Data System (ADS)

Vandersypen, L. M. K.; Bluhm, H.; Clarke, J. S.; Dzurak, A. S.; Ishihara, R.; Morello, A.; Reilly, D. J.; Schreiber, L. R.; Veldhorst, M.

2017-09-01

Semiconductor spins are one of the few qubit realizations that remain a serious candidate for the implementation of large-scale quantum circuits. Excellent scalability is often argued for spin qubits defined by lithography and controlled via electrical signals, based on the success of conventional semiconductor integrated circuits. However, the wiring and interconnect requirements for quantum circuits are completely different from those for classical circuits, as individual direct current, pulsed and in some cases microwave control signals need to be routed from external sources to every qubit. This is further complicated by the requirement that these spin qubits currently operate at temperatures below 100 mK. Here, we review several strategies that are considered to address this crucial challenge in scaling quantum circuits based on electron spin qubits. Key assets of spin qubits include the potential to operate at 1 to 4 K, the high density of quantum dots or donors combined with possibilities to space them apart as needed, the extremely long-spin coherence times, and the rich options for integration with classical electronics based on the same technology.

A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

NASA Astrophysics Data System (ADS)

Smith, Michael John Sebastian

Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

Calendar of Selected Aeronautical and Space Meetings (Calendrier des Manifestations Aeronautiques et Spatiales (Selection)).

DTIC Science & Technology

1983-01-01

Physique de l’Atmosphire et Environnement terrestre 71 09 - Information, Documentation et Informatique 74 10 - Thimes gin~raux (pluridisciplinaires) et...March Louisiana (US) Fiber Communication Optical Communications IEEE Fibre Optics Electro-Optics 02-08 7-9 March Baden-Baden VDE -IEEE Specialists...Conference on Very Large Electronic Systems VDE (GE) Scale Integrated Circuits Solid State Devices IEEE Integrated Circuits Engineering Design Fabrication

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip

PubMed Central

Schuck, C.; Guo, X.; Fan, L.; Ma, X.; Poot, M.; Tang, H. X.

2016-01-01

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips. PMID:26792424

New dynamic FET logic and serial memory circuits for VLSI GaAs technology

NASA Technical Reports Server (NTRS)

Eldin, A. G.

1991-01-01

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

Plasmonic integrated circuits comprising metal waveguides, multiplexer/demultiplexer, detectors, and logic circuits on a silicon substrate

NASA Astrophysics Data System (ADS)

Fukuda, M.; Ota, M.; Sumimura, A.; Okahisa, S.; Ito, M.; Ishii, Y.; Ishiyama, T.

2017-05-01

A plasmonic integrated circuit configuration comprising plasmonic and electronic components is presented and the feasibility for high-speed signal processing applications is discussed. In integrated circuits, plasmonic signals transmit data at high transfer rates with light velocity. Plasmonic and electronic components such as wavelength-divisionmultiplexing (WDM) networks comprising metal wires, plasmonic multiplexers/demultiplexers, and crossing metal wires are connected via plasmonic waveguides on the nanometer or micrometer scales. To merge plasmonic and electronic components, several types of plasmonic components were developed. To ensure that the plasmonic components could be easily fabricated and monolithically integrated onto a silicon substrate using silicon complementary metal-oxide-semiconductor (CMOS)-compatible processes, the components were fabricated on a Si substrate and made from silicon, silicon oxides, and metal; no other materials were used in the fabrication. The plasmonic components operated in the 1300- and 1550-nm-wavelength bands, which are typically employed in optical fiber communication systems. The plasmonic logic circuits were formed by patterning a silicon oxide film on a metal film, and the operation as a half adder was confirmed. The computed plasmonic signals can propagate through the plasmonic WDM networks and be connected to electronic integrated circuits at high data-transfer rates.

Metallization failures

NASA Technical Reports Server (NTRS)

Beatty, R.

1971-01-01

Metallization-related failure mechanisms were shown to be a major cause of integrated circuit failures under accelerated stress conditions, as well as in actual use under field operation. The integrated circuit industry is aware of the problem and is attempting to solve it in one of two ways: (1) better understanding of the aluminum system, which is the most widely used metallization material for silicon integrated circuits both as a single level and multilevel metallization, or (2) evaluating alternative metal systems. Aluminum metallization offers many advantages, but also has limitations particularly at elevated temperatures and high current densities. As an alternative, multilayer systems of the general form, silicon device-metal-inorganic insulator-metal, are being considered to produce large scale integrated arrays. The merits and restrictions of metallization systems in current usage and systems under development are defined.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, D.B.

1985-06-24

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, David B.

1987-01-01

In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, David B.

1989-01-01

In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, D.B.

1985-08-23

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, D.B.

1989-03-21

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration. 6 figs.

Electrically driven monolithic subwavelength plasmonic interconnect circuits

PubMed Central

Liu, Yang; Zhang, Jiasen; Liu, Huaping; Wang, Sheng; Peng, Lian-Mao

2017-01-01

In the post-Moore era, an electrically driven monolithic optoelectronic integrated circuit (OEIC) fabricated from a single material is pursued globally to enable the construction of wafer-scale compact computing systems with powerful processing capabilities and low-power consumption. We report a monolithic plasmonic interconnect circuit (PIC) consisting of a photovoltaic (PV) cascading detector, Au-strip waveguides, and electrically driven surface plasmon polariton (SPP) sources. These components are fabricated from carbon nanotubes (CNTs) via a CMOS (complementary metal-oxide semiconductor)–compatible doping-free technique in the same feature size, which can be reduced to deep-subwavelength scale (~λ/7 to λ/95, λ = 1340 nm) compared with the 14-nm technique node. An OEIC could potentially be configured as a repeater for data transport because of its “photovoltaic” operation mode to transform SPP energy directly into electricity to drive subsequent electronic circuits. Moreover, chip-scale throughput capability has also been demonstrated by fabricating a 20 × 20 PIC array on a 10 mm × 10 mm wafer. Tailoring photonics for monolithic integration with electronics beyond the diffraction limit opens a new era of chip-level nanoscale electronic-photonic systems, introducing a new path to innovate toward much faster, smaller, and cheaper computing frameworks. PMID:29062890

AC to DC Bridgeless Boost Converter for Ultra Low Input Energy Harvesting

NASA Astrophysics Data System (ADS)

Dawam, A. H. A.; Muhamad, M.

2018-03-01

This paper presents design of circuit which converts low input AC voltage to a higher output DC voltage. A buck-boost topology and boost topology are combined to condition cycle of an AC input voltage. the unique integration of a combining circuit of buck-boost and boost circuit have been proposed in order to introduce a new direct ac-dc power converter topology without conventional diode bridge rectifier. The converter achieved to convert a milli-volt scale of input AC voltage into a volt scale of output DC voltages which is from 400mV to 3.3V.

VLSI (Very Large Scale Integrated Circuits) Device Reliability Models.

DTIC Science & Technology

1984-12-01

CIRCUIT COMPLEXITY FAILURE RATES FOR... A- 40 MOS SSI/MSI DEVICES IN FAILURE PER 106 HOURS TABLE 5.1.2.5-19: C1 AND C2 CIRCUIT COMPLEXITY FAILURE RATES FOR...A- 40 MOS SSI/MSI DEVICES IN FAILURE PER 106 HOURS TABLE 5.1.2.5-19: Cl AND C2 CIRCUIT COMPLEXITY FAILURE RATES FOR... A-41 LINEAR DEVICES IN...19 National Semiconductor 20 Nitron 21 Raytheon 22 Sprague 23 Synertek 24 Teledyne Crystalonics 25 TRW Semiconductor 26 Zilog The following companies

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Photonic crystal ring resonator based optical filters for photonic integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robinson, S., E-mail: mail2robinson@gmail.com

In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 μm × 11.4 μm which ismore » highly suitable of photonic integrated circuits.« less

Effective algorithm for routing integral structures with twolayer switching

NASA Astrophysics Data System (ADS)

Nazarov, A. V.; Shakhnov, V. A.; Vlasov, A. I.; Novikov, A. N.

2018-05-01

The paper presents an algorithm for routing switching objects such as large-scale integrated circuits (LSICs) with two layers of metallization, embossed printed circuit boards, microboards with pairs of wiring layers on each side, and other similar constructs. The algorithm allows eliminating the effect of mutual blocking of routes in the classical wave algorithm by implementing a special circuit of digital wave motion in two layers of metallization, allowing direct intersections of all circuit conductors in a combined layer. However, information about the belonging of the topology elements to the circuits is sufficient for layering and minimizing the number of contact holes. In addition, the paper presents a specific example which shows that, in contrast to the known routing algorithms using a wave model, just one byte of memory per discrete of the work field is sufficient to implement the proposed algorithm.

Effect of Bypass Capacitor in Common-mode Noise Reduction Technique for Automobile PCB

NASA Astrophysics Data System (ADS)

Uno, Takanori; Ichikawa, Kouji; Mabuchi, Yuichi; Nakamura, Atushi

In this letter, we studied the use of common mode noise reduction technique for in-vehicle electronic equipment, each comprising large-scale integrated circuit (LSI), printed circuit board (PCB), wiring harnesses, and ground plane. We have improved the model circuit of the common mode noise that flows to the wire harness to add the effect of by-pass capacitors located near an LSI.

Layout-aware simulation of soft errors in sub-100 nm integrated circuits

NASA Astrophysics Data System (ADS)

Balbekov, A.; Gorbunov, M.; Bobkov, S.

2016-12-01

Single Event Transient (SET) caused by charged particle traveling through the sensitive volume of integral circuit (IC) may lead to different errors in digital circuits in some cases. In technologies below 180 nm, a single particle can affect multiple devices causing multiple SET. This fact adds the complexity to fault tolerant devices design, because the schematic design techniques become useless without their layout consideration. The most common layout mitigation technique is a spatial separation of sensitive nodes of hardened circuits. Spatial separation decreases the circuit performance and increases power consumption. Spacing should thus be reasonable and its scaling follows the device dimensions' scaling trend. This paper presents the development of the SET simulation approach comprised of SPICE simulation with "double exponent" current source as SET model. The technique uses layout in GDSII format to locate nearby devices that can be affected by a single particle and that can share the generated charge. The developed software tool automatizes multiple simulations and gathers the produced data to present it as the sensitivity map. The examples of conducted simulations of fault tolerant cells and their sensitivity maps are presented in this paper.

Planarization of metal films for multilevel interconnects by pulsed laser heating

DOEpatents

Tuckerman, David B.

1987-01-01

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Calculating Second-Order Effects in MOSFET's

NASA Technical Reports Server (NTRS)

Benumof, Reuben; Zoutendyk, John A.; Coss, James R.

1990-01-01

Collection of mathematical models includes second-order effects in n-channel, enhancement-mode, metal-oxide-semiconductor field-effect transistors (MOSFET's). When dimensions of circuit elements relatively large, effects neglected safely. However, as very-large-scale integration of microelectronic circuits leads to MOSFET's shorter or narrower than 2 micrometer, effects become significant in design and operation. Such computer programs as widely-used "Simulation Program With Integrated Circuit Emphasis, Version 2" (SPICE 2) include many of these effects. In second-order models of n-channel, enhancement-mode MOSFET, first-order gate-depletion region diminished by triangular-cross-section deletions on end and augmented by circular-wedge-cross-section bulges on sides.

Nonreciprocal frequency conversion in a multimode microwave optomechanical circuit

NASA Astrophysics Data System (ADS)

Feofanov, A. K.; Bernier, N. R.; Toth, L. D.; Koottandavida, A.; Kippenberg, T. J.

Nonreciprocal devices such as isolators, circulators, and directional amplifiers are pivotal to quantum signal processing with superconducting circuits. In the microwave domain, commercially available nonreciprocal devices are based on ferrite materials. They are barely compatible with superconducting quantum circuits, lossy, and cannot be integrated on chip. Significant potential exists for implementing non-magnetic chip-scale nonreciprocal devices using microwave optomechanical circuits. Here we demonstrate a possibility of nonreciprocal frequency conversion in a multimode microwave optomechanical circuit using solely optomechanical interaction between modes. The conversion scheme and the results reflecting the actual progress on the experimental implementation of the scheme will be presented.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liang-Yu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

An integrated circuit floating point accumulator

NASA Technical Reports Server (NTRS)

Goldsmith, T. C.

1977-01-01

Goddard Space Flight Center has developed a large scale integrated circuit (type 623) which can perform pulse counting, storage, floating point compression, and serial transmission, using a single monolithic device. Counts of 27 or 19 bits can be converted to transmitted values of 12 or 8 bits respectively. Use of the 623 has resulted in substantial savaings in weight, volume, and dollar resources on at least 11 scientific instruments to be flown on 4 NASA spacecraft. The design, construction, and application of the 623 are described.

Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling

NASA Astrophysics Data System (ADS)

Pour Aryan, N.; Heiß, L.; Schmitt-Landsiedel, D.; Georgakos, G.; Wirnshofer, M.

2012-09-01

In Adaptive Voltage Scaling (AVS) the supply voltage of digital circuits is tuned according to the circuit's actual operating condition, which enables dynamic compensation to PVTA variations. By exploiting the excessive safety margins added in state-of-the-art worst-case designs considerable power saving is achieved. In our approach, the operating condition of the circuit is monitored by in-situ delay monitors. This paper presents different designs to implement the in-situ delay monitors capable of detecting late but still non-erroneous transitions, called Pre-Errors. The developed Pre-Error monitors are integrated in a 16 bit multiplier test circuit and the resulting Pre-Error AVS system is modeled by a Markov chain in order to determine the power saving potential of each Pre-Error detection approach.

Speed-Up Techniques for Complementary Metal Oxide Semiconductor Very Large Scale Integration.

DTIC Science & Technology

1984-12-14

The input voltage at which the two transistors are in the constant current region at the same time marks the active operating region of the inverter...decoder precharge configurations. One circuit displayed a marked enhancement in operation while the other precharged circuit displyed degraded operation due...34 IEEE Journal of Solid State Circuits, SC-18: 457-462 (October 1983). 19. Cobbold , R. Theory and Applications of Field Effect Transistors, New York: John

Moving Beyond 3D Hetero-Integration and Towards Monolithic Integration of Phase-Change RF Switches with SiGe BiCMOS

DTIC Science & Technology

2016-03-31

Corporation, Linthicum, Maryland *Corresponding author: Pavel.Borodulin@ngc.com Abstract: A chip -scale, highly-reconfigurable transmitter and...the technology has been used in a chip -scale, reconfigurable receiver demonstration and ongoing efforts to increase the level of performance and...circuit (RF-FPGA). It consists of a heterogeneous assembly of a SiGe BiCMOS chip with multiple 3D-integrated, low-loss, phase-change switch chiplets

Multiplier Architecture for Coding Circuits

NASA Technical Reports Server (NTRS)

Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

Multipliers based on new algorithm for Galois-field (GF) arithmetic regular and expandable. Pipeline structures used for computing both multiplications and inverses. Designs suitable for implementation in very-large-scale integrated (VLSI) circuits. This general type of inverter and multiplier architecture especially useful in performing finite-field arithmetic of Reed-Solomon error-correcting codes and of some cryptographic algorithms.

LSI logic for phase-control rectifiers

NASA Technical Reports Server (NTRS)

Dolland, C.

1980-01-01

Signals for controlling phase-controlled rectifier circuit are generated by combinatorial logic than can be implemented in large-scale integration (LSI). LSI circuit saves space, weight, and assembly time compared to previous controls that employ one-shot multivibrators, latches, and capacitors. LSI logic functions by sensing three phases of ac power source and by comparing actual currents with intended currents.

PCSIM: A Parallel Simulation Environment for Neural Circuits Fully Integrated with Python

PubMed Central

Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

2008-01-01

The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations. PMID:19543450

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

PubMed

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

Impurity engineering of Czochralski silicon used for ultra large-scaled-integrated circuits

NASA Astrophysics Data System (ADS)

Yang, Deren; Chen, Jiahe; Ma, Xiangyang; Que, Duanlin

2009-01-01

Impurities in Czochralski silicon (Cz-Si) used for ultra large-scaled-integrated (ULSI) circuits have been believed to deteriorate the performance of devices. In this paper, a review of the recent processes from our investigation on internal gettering in Cz-Si wafers which were doped with nitrogen, germanium and/or high content of carbon is presented. It has been suggested that those impurities enhance oxygen precipitation, and create both denser bulk microdefects and enough denuded zone with the desirable width, which is benefit of the internal gettering of metal contamination. Based on the experimental facts, a potential mechanism of impurity doping on the internal gettering structure is interpreted and, a new concept of 'impurity engineering' for Cz-Si used for ULSI is proposed.

Limits on fundamental limits to computation.

PubMed

Markov, Igor L

2014-08-14

An indispensable part of our personal and working lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the past fifty years. Such Moore scaling now requires ever-increasing efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and increase our understanding of integrated-circuit scaling, here I review fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, I recapitulate how some limits were circumvented, and compare loose and tight limits. Engineering difficulties encountered by emerging technologies may indicate yet unknown limits.

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication.

PubMed

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-02-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

Microfabrication techniques for integrated sensors and microsystems.

PubMed

Wise, K D; Najafi, K

1991-11-29

Integrated sensors and actuators are rapidly evolving to provide an important link between very large scale integrated circuits and nonelectronic monitoring and control applications ranging from biomedicine to automated manufacturing. As they continue to expand, entire microsystems merging electrical, mechanical, thermal, optical, magnetic, and perhaps chemical components should be possible on a common substrate.

A large-scale circuit mechanism for hierarchical dynamical processing in the primate cortex

PubMed Central

Chaudhuri, Rishidev; Knoblauch, Kenneth; Gariel, Marie-Alice; Kennedy, Henry; Wang, Xiao-Jing

2015-01-01

We developed a large-scale dynamical model of the macaque neocortex, which is based on recently acquired directed- and weighted-connectivity data from tract-tracing experiments, and which incorporates heterogeneity across areas. A hierarchy of timescales naturally emerges from this system: sensory areas show brief, transient responses to input (appropriate for sensory processing), whereas association areas integrate inputs over time and exhibit persistent activity (suitable for decision-making and working memory). The model displays multiple temporal hierarchies, as evidenced by contrasting responses to visual versus somatosensory stimulation. Moreover, slower prefrontal and temporal areas have a disproportionate impact on global brain dynamics. These findings establish a circuit mechanism for “temporal receptive windows” that are progressively enlarged along the cortical hierarchy, suggest an extension of time integration in decision-making from local to large circuits, and should prompt a re-evaluation of the analysis of functional connectivity (measured by fMRI or EEG/MEG) by taking into account inter-areal heterogeneity. PMID:26439530

Highly localized distributed Brillouin scattering response in a photonic integrated circuit

NASA Astrophysics Data System (ADS)

Zarifi, Atiyeh; Stiller, Birgit; Merklein, Moritz; Li, Neuton; Vu, Khu; Choi, Duk-Yong; Ma, Pan; Madden, Stephen J.; Eggleton, Benjamin J.

2018-03-01

The interaction of optical and acoustic waves via stimulated Brillouin scattering (SBS) has recently reached on-chip platforms, which has opened new fields of applications ranging from integrated microwave photonics and on-chip narrow-linewidth lasers, to phonon-based optical delay and signal processing schemes. Since SBS is an effect that scales exponentially with interaction length, on-chip implementation on a short length scale is challenging, requiring carefully designed waveguides with optimized opto-acoustic overlap. In this work, we use the principle of Brillouin optical correlation domain analysis to locally measure the SBS spectrum with high spatial resolution of 800 μm and perform a distributed measurement of the Brillouin spectrum along a spiral waveguide in a photonic integrated circuit. This approach gives access to local opto-acoustic properties of the waveguides, including the Brillouin frequency shift and linewidth, essential information for the further development of high quality photonic-phononic waveguides for SBS applications.

Bidirectional Neural Interfaces

PubMed Central

Masters, Matthew R.; Thakor, Nitish V.

2016-01-01

A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very-large-scale integration (VLSI) has advanced the design of complex integrated circuits. System-on-chip (SoC) devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems. PMID:26753776

A monolithically integrated polarization entangled photon pair source on a silicon chip

PubMed Central

Matsuda, Nobuyuki; Le Jeannic, Hanna; Fukuda, Hiroshi; Tsuchizawa, Tai; Munro, William John; Shimizu, Kaoru; Yamada, Koji; Tokura, Yasuhiro; Takesue, Hiroki

2012-01-01

Integrated photonic circuits are one of the most promising platforms for large-scale photonic quantum information systems due to their small physical size and stable interferometers with near-perfect lateral-mode overlaps. Since many quantum information protocols are based on qubits defined by the polarization of photons, we must develop integrated building blocks to generate, manipulate, and measure the polarization-encoded quantum state on a chip. The generation unit is particularly important. Here we show the first integrated polarization-entangled photon pair source on a chip. We have implemented the source as a simple and stable silicon-on-insulator photonic circuit that generates an entangled state with 91 ± 2% fidelity. The source is equipped with versatile interfaces for silica-on-silicon or other types of waveguide platforms that accommodate the polarization manipulation and projection devices as well as pump light sources. Therefore, we are ready for the full-scale implementation of photonic quantum information systems on a chip. PMID:23150781

Uncertain behaviours of integrated circuits improve computational performance.

PubMed

Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

2015-11-20

Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

Concept For Generation Of Long Pseudorandom Sequences

NASA Technical Reports Server (NTRS)

Wang, C. C.

1990-01-01

Conceptual very-large-scale integrated (VLSI) digital circuit performs exponentiation in finite field. Algorithm that generates unusually long sequences of pseudorandom numbers executed by digital processor that includes such circuits. Concepts particularly advantageous for such applications as spread-spectrum communications, cryptography, and generation of ranging codes, synthetic noise, and test data, where usually desirable to make pseudorandom sequences as long as possible.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

System Modeling of a MEMS Vibratory Gyroscope and Integration to Circuit Simulation.

PubMed

Kwon, Hyukjin J; Seok, Seyeong; Lim, Geunbae

2017-11-18

Recently, consumer applications have dramatically created the demand for low-cost and compact gyroscopes. Therefore, on the basis of microelectromechanical systems (MEMS) technology, many gyroscopes have been developed and successfully commercialized. A MEMS gyroscope consists of a MEMS device and an electrical circuit for self-oscillation and angular-rate detection. Since the MEMS device and circuit are interactively related, the entire system should be analyzed together to design or test the gyroscope. In this study, a MEMS vibratory gyroscope is analyzed based on the system dynamic modeling; thus, it can be mathematically expressed and integrated into a circuit simulator. A behavioral simulation of the entire system was conducted to prove the self-oscillation and angular-rate detection and to determine the circuit parameters to be optimized. From the simulation, the operating characteristic according to the vacuum pressure and scale factor was obtained, which indicated similar trends compared with those of the experimental results. The simulation method presented in this paper can be generalized to a wide range of MEMS devices.

Experimental Verification of Guided-Wave Lumped Circuits Using Waveguide Metamaterials

NASA Astrophysics Data System (ADS)

Li, Yue; Zhang, Zhijun

2018-04-01

Through the construction and characterization in microwave frequencies, we experimentally demonstrate our recently developed theory of waveguide lumped circuits, i.e., waveguide metatronics [Sci. Adv. 2, e1501790 (2016), 10.1126/sciadv.1501790], as a method to design subwavelength-scaled analog circuits. In the paradigm of waveguide metatronics, numbers of lumped inductors and capacitors are easily integrated functionally inside the waveguide, which is an irreplaceable transmission line in millimeter-wave and terahertz systems with the advantages of low radiation loss and low crosstalk. An example of multiple-ordered metatronic filters with layered structures is fabricated utilizing the technique of substrate integrated waveguides, which can be easily constructed by the printed-circuit-board process. The materials used in the construction are also typical microwave materials with positive permittivity, low loss, and negligible dispersion, imitating the plasmonic materials with negative permittivity in the optical domain. The results verify the theory of waveguide metatronics, which provides an efficient platform of functional lumped circuit design for guided-wave processing.

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

PubMed Central

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-01-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes. PMID:28145513

Radiation Testing and Evaluation Issues for Modern Integrated Circuits

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lew M.

2005-01-01

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

From Whole-Brain Data to Functional Circuit Models: The Zebrafish Optomotor Response.

PubMed

Naumann, Eva A; Fitzgerald, James E; Dunn, Timothy W; Rihel, Jason; Sompolinsky, Haim; Engert, Florian

2016-11-03

Detailed descriptions of brain-scale sensorimotor circuits underlying vertebrate behavior remain elusive. Recent advances in zebrafish neuroscience offer new opportunities to dissect such circuits via whole-brain imaging, behavioral analysis, functional perturbations, and network modeling. Here, we harness these tools to generate a brain-scale circuit model of the optomotor response, an orienting behavior evoked by visual motion. We show that such motion is processed by diverse neural response types distributed across multiple brain regions. To transform sensory input into action, these regions sequentially integrate eye- and direction-specific sensory streams, refine representations via interhemispheric inhibition, and demix locomotor instructions to independently drive turning and forward swimming. While experiments revealed many neural response types throughout the brain, modeling identified the dimensions of functional connectivity most critical for the behavior. We thus reveal how distributed neurons collaborate to generate behavior and illustrate a paradigm for distilling functional circuit models from whole-brain data. Copyright © 2016 Elsevier Inc. All rights reserved.

Multiscale mechanobiology: computational models for integrating molecules to multicellular systems

PubMed Central

Mak, Michael; Kim, Taeyoon

2015-01-01

Mechanical signals exist throughout the biological landscape. Across all scales, these signals, in the form of force, stiffness, and deformations, are generated and processed, resulting in an active mechanobiological circuit that controls many fundamental aspects of life, from protein unfolding and cytoskeletal remodeling to collective cell motions. The multiple scales and complex feedback involved present a challenge for fully understanding the nature of this circuit, particularly in development and disease in which it has been implicated. Computational models that accurately predict and are based on experimental data enable a means to integrate basic principles and explore fine details of mechanosensing and mechanotransduction in and across all levels of biological systems. Here we review recent advances in these models along with supporting and emerging experimental findings. PMID:26019013

Design of a 16 gray scales 320 × 240 pixels OLED-on-silicon driving circuit

NASA Astrophysics Data System (ADS)

Ran, Huang; Xiaohui, Wang; Wenbo, Wang; Huan, Du; Zhengsheng, Han

2009-01-01

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4 × 28.4 μm2 and the display area is 10.7 × 8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.

Integration of micro-/nano-/quantum-scale photonic devices: scientific and technological considerations

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, Seung-Gol; O, Beom Hoan; Park, Se Geun

2004-08-01

Scientific and technological issues and considerations regarding the integration of miniaturized microphotonic devices, circuits and systems in micron, submicron, and quantum scale, are presented. First, we examine the issues regarding the miniaturization of photonic devices including the size effect, proximity effect, energy confinement effect, microcavity effect, optical and quantum interference effect, high field effect, nonlinear effect, noise effect, quantum optical effect, and chaotic effect. Secondly, we examine the issues regarding the interconnection including the optical alignment, minimizing the interconnection losses, and maintaining optical modes. Thirdly, we address the issues regarding the two-dimensional or three-dimensional integration either in a hybrid format or in a monolithic format between active devices and passive devices of varying functions. We find that the concept of optical printed circuit board (O-PCB) that we propose is highly attractive as a platform for micro/nano/quantum-scale photonic integration. We examine the technological issues to be addressed in the process of fabrication, characterization, and packaging for actual implementation of the miniaturization, interconnection and integration. Devices that we have used for our study include: mode conversion schemes, micro-ring and micro-racetrack resonator devices, multimode interference devices, lasers, vertical cavity surface emitting microlasers, and their arrays. Future prospects are also discussed.

Large-scale, high-density (up to 512 channels) recording of local circuits in behaving animals

PubMed Central

Berényi, Antal; Somogyvári, Zoltán; Nagy, Anett J.; Roux, Lisa; Long, John D.; Fujisawa, Shigeyoshi; Stark, Eran; Leonardo, Anthony; Harris, Timothy D.

2013-01-01

Monitoring representative fractions of neurons from multiple brain circuits in behaving animals is necessary for understanding neuronal computation. Here, we describe a system that allows high-channel-count recordings from a small volume of neuronal tissue using a lightweight signal multiplexing headstage that permits free behavior of small rodents. The system integrates multishank, high-density recording silicon probes, ultraflexible interconnects, and a miniaturized microdrive. These improvements allowed for simultaneous recordings of local field potentials and unit activity from hundreds of sites without confining free movements of the animal. The advantages of large-scale recordings are illustrated by determining the electroanatomic boundaries of layers and regions in the hippocampus and neocortex and constructing a circuit diagram of functional connections among neurons in real anatomic space. These methods will allow the investigation of circuit operations and behavior-dependent interregional interactions for testing hypotheses of neural networks and brain function. PMID:24353300

Development of High Level Electrical Stress Failure Threshold and Prediction Model for Small Scale Junction Integrated Circuits

DTIC Science & Technology

1978-09-01

AWACS EMP Guidelines presents two different models to predict the damage pcwer of the dev-ce and the circuit damage EMP voltage ( VEMP ). Neither of...calculated as K P~ I V BD 6. The damage EMP voltage ( VEMP ) is calculated KZ EMP +IZ =D +BD VBD1F 7. The damage EMP voltage is calculated for collector

Large-scale quantum photonic circuits in silicon

NASA Astrophysics Data System (ADS)

Harris, Nicholas C.; Bunandar, Darius; Pant, Mihir; Steinbrecher, Greg R.; Mower, Jacob; Prabhu, Mihika; Baehr-Jones, Tom; Hochberg, Michael; Englund, Dirk

2016-08-01

Quantum information science offers inherently more powerful methods for communication, computation, and precision measurement that take advantage of quantum superposition and entanglement. In recent years, theoretical and experimental advances in quantum computing and simulation with photons have spurred great interest in developing large photonic entangled states that challenge today's classical computers. As experiments have increased in complexity, there has been an increasing need to transition bulk optics experiments to integrated photonics platforms to control more spatial modes with higher fidelity and phase stability. The silicon-on-insulator (SOI) nanophotonics platform offers new possibilities for quantum optics, including the integration of bright, nonclassical light sources, based on the large third-order nonlinearity (χ(3)) of silicon, alongside quantum state manipulation circuits with thousands of optical elements, all on a single phase-stable chip. How large do these photonic systems need to be? Recent theoretical work on Boson Sampling suggests that even the problem of sampling from e30 identical photons, having passed through an interferometer of hundreds of modes, becomes challenging for classical computers. While experiments of this size are still challenging, the SOI platform has the required component density to enable low-loss and programmable interferometers for manipulating hundreds of spatial modes. Here, we discuss the SOI nanophotonics platform for quantum photonic circuits with hundreds-to-thousands of optical elements and the associated challenges. We compare SOI to competing technologies in terms of requirements for quantum optical systems. We review recent results on large-scale quantum state evolution circuits and strategies for realizing high-fidelity heralded gates with imperfect, practical systems. Next, we review recent results on silicon photonics-based photon-pair sources and device architectures, and we discuss a path towards large-scale source integration. Finally, we review monolithic integration strategies for single-photon detectors and their essential role in on-chip feed forward operations.

A procedural method for the efficient implementation of full-custom VLSI designs

NASA Technical Reports Server (NTRS)

Belk, P.; Hickey, N.

1987-01-01

An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system.

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

NASA Technical Reports Server (NTRS)

Alt, Shannon

2016-01-01

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

Printed dose-recording tag based on organic complementary circuits and ferroelectric nonvolatile memories

PubMed Central

Nga Ng, Tse; Schwartz, David E.; Mei, Ping; Krusor, Brent; Kor, Sivkheng; Veres, Janos; Bröms, Per; Eriksson, Torbjörn; Wang, Yong; Hagel, Olle; Karlsson, Christer

2015-01-01

We have demonstrated a printed electronic tag that monitors time-integrated sensor signals and writes to nonvolatile memories for later readout. The tag is additively fabricated on flexible plastic foil and comprises a thermistor divider, complementary organic circuits, and two nonvolatile memory cells. With a supply voltage below 30 V, the threshold temperatures can be tuned between 0 °C and 80 °C. The time-temperature dose measurement is calibrated for minute-scale integration. The two memory bits are sequentially written in a thermometer code to provide an accumulated dose record. PMID:26307438

IIIV/Si Nanoscale Lasers and Their Integration with Silicon Photonics

NASA Astrophysics Data System (ADS)

Bondarenko, Olesya

The rapidly evolving global information infrastructure requires ever faster data transfer within computer networks and stations. Integrated chip scale photonics can pave the way to accelerated signal manipulation and boost bandwidth capacity of optical interconnects in a compact and ergonomic arrangement. A key building block for integrated photonic circuits is an on-chip laser. In this dissertation we explore ways to reduce the physical footprint of semiconductor lasers and make them suitable for high density integration on silicon, a standard material platform for today's integrated circuits. We demonstrated the first room temperature metalo-dielectric nanolaser, sub-wavelength in all three dimensions. Next, we demonstrated a nanolaser on silicon, showing the feasibility of its integration with this platform. We also designed and realized an ultracompact feedback laser with edge-emitting structure, amenable for in-plane coupling with a standard silicon waveguide. Finally, we discuss the challenges and propose solutions for improvement of the device performance and practicality.

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

DTIC Science & Technology

2015-10-13

transistors. There are several reasons for this gigantic disparity: insufficient funding and lack of profit-driven investments in superconductor ...Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers,” IEEE Trans. Appl. Supercond., vol...vol. 25, No. 3, 1301704, June 2015. [7] V. Ambegaokar and A. Baratoff, “Tunneling between superconductors ,” Phys. Rev. Lett., vol. 10, no. 11, pp

Chemical Processing of Electrons and Holes.

ERIC Educational Resources Information Center

Anderson, Timothy J.

1990-01-01

Presents a synopsis of four lectures given in an elective senior-level electronic material processing course to introduce solid state electronics. Provides comparisons of a large scale chemical processing plant and an integrated circuit. (YP)

Nanowire nanocomputer as a finite-state machine.

PubMed

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2014-02-18

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.

Nanowire nanocomputer as a finite-state machine

PubMed Central

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F.; Ellenbogen, James C.; Lieber, Charles M.

2014-01-01

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom–up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future. PMID:24469812

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

NASA Astrophysics Data System (ADS)

Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

2017-02-01

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

High accuracy digital aging monitor based on PLL-VCO circuit

NASA Astrophysics Data System (ADS)

Yuejun, Zhang; Zhidi, Jiang; Pengjun, Wang; Xuelong, Zhang

2015-01-01

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

PubMed

Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

2017-02-15

An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si₃N₄) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si₃N₄ and the LN-Si₃N₄ waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

Tomography experiment of an integrated circuit specimen using 3 MeV electrons in the transmission electron microscope.

PubMed

Zhang, Hai-Bo; Zhang, Xiang-Liang; Wang, Yong; Takaoka, Akio

2007-01-01

The possibility of utilizing high-energy electron tomography to characterize the micron-scale three dimensional (3D) structures of integrated circuits has been demonstrated experimentally. First, electron transmission through a tilted SiO(2) film was measured with an ultrahigh-voltage electron microscope (ultra-HVEM) and analyzed from the point of view of elastic scattering of electrons, showing that linear attenuation of the logarithmic electron transmission still holds valid for effective specimen thicknesses up to 5 microm under 2 MV accelerating voltages. Electron tomography of a micron-order thick integrated circuit specimen including the Cu/via interconnect was then tried with 3 MeV electrons in the ultra-HVEM. Serial projection images of the specimen tilted at different angles over the range of +/-90 degrees were acquired, and 3D reconstruction was performed with the images by means of the IMOD software package. Consequently, the 3D structures of the Cu lines, via and void, were revealed by cross sections and surface rendering.

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

PubMed Central

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-01-01

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

PubMed

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-04-13

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics†

PubMed Central

Muluneh, Melaku

2015-01-01

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm2 microfluidic chip that incorporated a commercial 565 × 1145 μm2 IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series. PMID:25284502

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.

PubMed

Muluneh, Melaku; Issadore, David

2014-12-07

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm(2) microfluidic chip that incorporated a commercial 565 × 1145 μm(2) IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series.

Three-dimensional integrated circuits for lab-on-chip dielectrophoresis of nanometer scale particles

NASA Astrophysics Data System (ADS)

Dickerson, Samuel J.; Noyola, Arnaldo J.; Levitan, Steven P.; Chiarulli, Donald M.

2007-01-01

In this paper, we present a mixed-technology micro-system for electronically manipulating and optically detecting virusscale particles in fluids that is designed using 3D integrated circuit technology. During the 3D fabrication process, the top-most chip tier is assembled upside down and the substrate material is removed. This places the polysilicon layer, which is used to create geometries with the process' minimum feature size, in close proximity to a fluid channel etched into the top of the stack. By taking advantage of these processing features inherent to "3D chip-stacking" technology, we create electrode arrays that have a gap spacing of 270 nm. Using 3D CMOS technology also provides the ability to densely integrate analog and digital control circuitry for the electrodes by using the additional levels of the chip stack. We show simulations of the system with a physical model of a Kaposi's sarcoma-associated herpes virus, which has a radius of approximately 125 nm, being dielectrophoretically arranged into striped patterns. We also discuss how these striped patterns of trapped nanometer scale particles create an effective diffraction grating which can then be sensed with macro-scale optical techniques.

A fast low-power optical memory based on coupled micro-ring lasers

NASA Astrophysics Data System (ADS)

Hill, Martin T.; Dorren, Harmen J. S.; de Vries, Tjibbe; Leijtens, Xaveer J. M.; den Besten, Jan Hendrik; Smalbrugge, Barry; Oei, Yok-Siang; Binsma, Hans; Khoe, Giok-Djan; Smit, Meint K.

2004-11-01

The increasing speed of fibre-optic-based telecommunications has focused attention on high-speed optical processing of digital information. Complex optical processing requires a high-density, high-speed, low-power optical memory that can be integrated with planar semiconductor technology for buffering of decisions and telecommunication data. Recently, ring lasers with extremely small size and low operating power have been made, and we demonstrate here a memory element constructed by interconnecting these microscopic lasers. Our device occupies an area of 18 × 40µm2 on an InP/InGaAsP photonic integrated circuit, and switches within 20ps with 5.5fJ optical switching energy. Simulations show that the element has the potential for much smaller dimensions and switching times. Large numbers of such memory elements can be densely integrated and interconnected on a photonic integrated circuit: fast digital optical information processing systems employing large-scale integration should now be viable.

Erbium-doped zinc-oxide waveguide amplifiers for hybrid photonic integrated circuits

NASA Astrophysics Data System (ADS)

O'Neal, Lawrence; Anthony, Deion; Bonner, Carl; Geddis, Demetris

2016-02-01

CMOS logic circuits have entered the sub-100nm regime, and research is on-going to investigate the quantum effects that are apparent at this dimension. To avoid some of the constraints imposed by fabrication, entropy, energy, and interference considerations for nano-scale devices, many have begun designing hybrid and/or photonic integrated circuits. These circuits consist of transistors, light emitters, photodetectors, and electrical and optical waveguides. As attenuation is a limiting factor in any communications system, it is advantageous to integrate a signal amplifier. There are numerous examples of electrical amplifiers, but in order to take advantage of the benefits provided by optically integrated systems, optical amplifiers are necessary. The erbium doped fiber amplifier is an example of an optical amplifier which is commercially available now, but the distance between the amplifier and the device benefitting from amplification can be decreased and provide greater functionality by providing local, on-chip amplification. Zinc oxide is an attractive material due to its electrical and optical properties. Its wide bandgap (≍3.4 eV) and high refractive index (≍2) make it an excellent choice for integrated optics systems. Moreover, erbium doped zinc oxide (Er:ZnO) is a suitable candidate for optical waveguide amplifiers because of its compatibility with semiconductor processing technology, 1.54 μm luminescence, transparency, low resistivity, and amplification characteristics. This research presents the characterization of radio frequency magnetron sputtered Er:ZnO, the design and fabrication of integrated waveguide amplifiers, and device analysis.

Arrays of Carbon Nanotubes as RF Filters in Waveguides

NASA Technical Reports Server (NTRS)

Hoppe, Daniel; Hunt, Brian; Hoenk, Michael; Noca, Flavio; Xu, Jimmy

2003-01-01

Brushlike arrays of carbon nanotubes embedded in microstrip waveguides provide highly efficient (high-Q) mechanical resonators that will enable ultraminiature radio-frequency (RF) integrated circuits. In its basic form, this invention is an RF filter based on a carbon nanotube array embedded in a microstrip (or coplanar) waveguide, as shown in Figure 1. In addition, arrays of these nanotube-based RF filters can be used as an RF filter bank. Applications of this new nanotube array device include a variety of communications and signal-processing technologies. High-Q resonators are essential for stable, low-noise communications, and radar applications. Mechanical oscillators can exhibit orders of magnitude higher Qs than electronic resonant circuits, which are limited by resistive losses. This has motivated the development of a variety of mechanical resonators, including bulk acoustic wave (BAW) resonators, surface acoustic wave (SAW) resonators, and Si and SiC micromachined resonators (known as microelectromechanical systems or MEMS). There is also a strong push to extend the resonant frequencies of these oscillators into the GHz regime of state-of-the-art electronics. Unfortunately, the BAW and SAW devices tend to be large and are not easily integrated into electronic circuits. MEMS structures have been integrated into circuits, but efforts to extend MEMS resonant frequencies into the GHz regime have been difficult because of scaling problems with the capacitively-coupled drive and readout. In contrast, the proposed devices would be much smaller and hence could be more readily incorporated into advanced RF (more specifically, microwave) integrated circuits.

Packaging of electro-microfluidic devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Zamora, David Lee; Watson, Robert D.

2003-04-15

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Packaging of electro-microfluidic devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Watson, Robert D.

2002-01-01

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

PubMed Central

Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

2016-01-01

The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

The Department of Defense Very High Speed Integrated Circuit (VHSIC) Technology Availability Program Plan for the Committees on Armed Services United States Congress.

DTIC Science & Technology

1986-06-30

features of computer aided design systems and statistical quality control procedures that are generic to chip sets and processes. RADIATION HARDNESS -The...System PSP Programmable Signal Processor SSI Small Scale Integration ." TOW Tube Launched, Optically Tracked, Wire Guided TTL Transistor Transitor Logic

Techniques for control of long-term reliability of complex integrated circuits. I - Reliability assurance by test vehicle qualification.

NASA Technical Reports Server (NTRS)

Van Vonno, N. W.

1972-01-01

Development of an alternate approach to the conventional methods of reliability assurance for large-scale integrated circuits. The product treated is a large-scale T squared L array designed for space applications. The concept used is that of qualification of product by evaluation of the basic processing used in fabricating the product, providing an insight into its potential reliability. Test vehicles are described which enable evaluation of device characteristics, surface condition, and various parameters of the two-level metallization system used. Evaluation of these test vehicles is performed on a lot qualification basis, with the lot consisting of one wafer. Assembled test vehicles are evaluated by high temperature stress at 300 C for short time durations. Stressing at these temperatures provides a rapid method of evaluation and permits a go/no go decision to be made on the wafer lot in a timely fashion.

Unfolding an electronic integrate-and-fire circuit.

PubMed

Carrillo, Humberto; Hoppensteadt, Frank

2010-01-01

Many physical and biological phenomena involve accumulation and discharge processes that can occur on significantly different time scales. Models of these processes have contributed to understand excitability self-sustained oscillations and synchronization in arrays of oscillators. Integrate-and-fire (I+F) models are popular minimal fill-and-flush mathematical models. They are used in neuroscience to study spiking and phase locking in single neuron membranes, large scale neural networks, and in a variety of applications in physics and electrical engineering. We show here how the classical first-order I+F model fits into the theory of nonlinear oscillators of van der Pol type by demonstrating that a particular second-order oscillator having small parameters converges in a singular perturbation limit to the I+F model. In this sense, our study provides a novel unfolding of such models and it identifies a constructible electronic circuit that is closely related to I+F.

Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits

NASA Astrophysics Data System (ADS)

Abbaspour, R.; Brown, D. K.; Bakir, M. S.

2017-02-01

This paper presents the fabrication and electrical characterization of high aspect-ratio (AR) sub-micron diameter through silicon vias (TSVs) for densely interconnected three-dimensional (3D) stacked integrated circuits (ICs). The fabricated TSV technology features an AR of 16:1 with 680 nm diameter copper (Cu) core and 920 nm overall diameter. To address the challenges in scaling TSVs, scallop-free low roughness nano-Bosch silicon etching and direct Cu electroplating on a titanium-nitride (TiN) diffusion barrier layer have been developed as key enabling modules. The electrical resistance of the sub-micron TSVs is measured to be on average 1.2 Ω, and the Cu resistivity is extracted to be approximately 2.95 µΩ cm. Furthermore, the maximum achievable current-carrying capacity (CCC) of the scaled TSVs is characterized to be approximately 360 µA for the 680 nm Cu core.

Flexible circuits with integrated switches for robotic shape sensing

NASA Astrophysics Data System (ADS)

Harnett, C. K.

2016-05-01

Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

Novel high-gain, improved-bandwidth, finned-ladder V-band Traveling-Wave Tube slow-wave circuit design

NASA Technical Reports Server (NTRS)

Kory, Carol L.; Wilson, Jeffrey D.

1994-01-01

The V-band frequency range of 59-64 GHz is a region of the millimeter-wave spectrum that has been designated for inter-satellite communications. As a first effort to develop a high-efficiency V-band Traveling-Wave Tube (TWT), variations on a ring-plane slow-wave circuit were computationally investigated to develop an alternative to the more conventional ferruled coupled-cavity circuit. The ring-plane circuit was chosen because of its high interaction impedance, large beam aperture, and excellent thermal dissipation properties. Despite these advantages, however, low bandwidth and high voltage requirements have, until now, prevented its acceptance outside the laboratory. In this paper, the three-dimensional electrodynamic simulation code MAFIA (solution of MAxwell's Equation by the Finite-Integration-Algorithm) is used to investigate methods of increasing the bandwidth and lowering the operating voltage of the ring-plane circuit. Calculations of frequency-phase dispersion, beam on-axis interaction impedance, attenuation and small-signal gain per wavelength were performed for various geometric variations and loading distributions of the ring-plane TWT slow-wave circuit. Based on the results of the variations, a circuit termed the finned-ladder TWT slow-wave circuit was designed and is compared here to the scaled prototype ring-plane and a conventional ferruled coupled-cavity TWT circuit over the V-band frequency range. The simulation results indicate that this circuit has a much higher gain, significantly wider bandwidth, and a much lower voltage requirement than the scaled ring-plane prototype circuit, while retaining its excellent thermal dissipation properties. The finned-ladder circuit has a much larger small-signal gain per wavelength than the ferruled coupled-cavity circuit, but with a moderate sacrifice in bandwidth.

An Engineering Methodology for Implementing and Testing VLSI (Very Large Scale Integrated) Circuits

DTIC Science & Technology

1989-03-01

the pad frame and associated routing, conducted additional testing. and submitted the finished design effort to MOSIS for manufacturing. Throughout...register bank TSTCON Allows the XNOR circuitry to enter the TEST register bank PADIN Test signal to check operation of the input pad VCC Power connection...MOSSIM II simulation program. but the design offered little observability within the circuit. The initial design used 35 pins of a 40 pin pad frame

Organic field effect transistor with ultra high amplification

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio

2016-09-01

High-gain transistors are essential for the large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show organic transistors fabricated on plastic foils enabling unipolar amplifiers with ultra-gain. The proposed approach is general and opens up new opportunities for ultra-large signal amplification in organic circuits and sensors.

Out Flying the Eagle: China’s Drive for Domestic Economic Innovation and Its Impact on U.S.-China Relations

DTIC Science & Technology

2014-03-01

wind turbines from General Electric. China recognizes the issues with IPR but it is something that will take time to fix. It will be a significant...Large aircraft  Large-scale oil and gas exploration  Manned space, including lunar exploration  Next-generation broadband wireless ...circuits, and building an innovation system for China’s integrated circuit (IC) manufacturing industry. 3. New generation broadband wireless mobile

Identifying behavioral circuits in Drosophila melanogaster: moving targets in a flying insect.

PubMed

Griffith, Leslie C

2012-08-01

Drosophila melanogaster has historically been the premier model system for understanding the molecular and genetic bases of complex behaviors. In the last decade technical advances, in the form of new genetic tools and electrophysiological and optical methods, have allowed investigators to begin to dissect the neuronal circuits that generate behavior in the adult. The blossoming of circuit analysis in this organism has also reinforced our appreciation of the inadequacy of wiring diagrams for specifying complex behavior. Neuromodulation and neuronal plasticity act to reconfigure circuits on both short and long time scales. These processes act on the connectome, providing context by integrating external and internal cues that are relevant for behavioral choices. New approaches in the fly are providing insight into these basic principles of circuit function. Copyright © 2012 Elsevier Ltd. All rights reserved.

[Not Available].

PubMed

Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

2009-01-01

The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations.

Nanoelectronics from the bottom up.

PubMed

Lu, Wei; Lieber, Charles M

2007-11-01

Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

Defense Acquisitions Acronyms and Terms

DTIC Science & Technology

2012-12-01

Computer-Aided Design CADD Computer-Aided Design and Drafting CAE Component Acquisition Executive; Computer-Aided Engineering CAIV Cost As an...Radiation to Ordnance HFE Human Factors Engineering HHA Health Hazard Assessment HNA Host-Nation Approval HNS Host-Nation Support HOL High -Order...Engineering Change Proposal VHSIC Very High Speed Integrated Circuit VLSI Very Large Scale Integration VOC Volatile Organic Compound W WAN Wide

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

2016-11-01

Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

Associative Pattern Recognition In Analog VLSI Circuits

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1995-01-01

Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

An integrated semiconductor device enabling non-optical genome sequencing.

PubMed

Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

2011-07-20

The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

Method Of Packaging And Assembling Electro-Microfluidic Devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Zamora, David Lee; Watson, Robert D.

2004-11-23

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Experimental study of an adaptive elastic metamaterial controlled by electric circuits

NASA Astrophysics Data System (ADS)

Zhu, R.; Chen, Y. Y.; Barnhart, M. V.; Hu, G. K.; Sun, C. T.; Huang, G. L.

2016-01-01

The ability to control elastic wave propagation at a deep subwavelength scale makes locally resonant elastic metamaterials very relevant. A number of abilities have been demonstrated such as frequency filtering, wave guiding, and negative refraction. Unfortunately, few metamaterials develop into practical devices due to their lack of tunability for specific frequencies. With the help of multi-physics numerical modeling, experimental validation of an adaptive elastic metamaterial integrated with shunted piezoelectric patches has been performed in a deep subwavelength scale. The tunable bandgap capacity, as high as 45%, is physically realized by using both hardening and softening shunted circuits. It is also demonstrated that the effective mass density of the metamaterial can be fully tailored by adjusting parameters of the shunted electric circuits. Finally, to illustrate a practical application, transient wave propagation tests of the adaptive metamaterial subjected to impact loads are conducted to validate their tunable wave mitigation abilities in real-time.

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

PubMed

Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas

2016-10-12

Two-dimensional electronics based on single-layer (SL) MoS 2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS 2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS 2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Convergence of circuit dysfunction in ASD: a common bridge between diverse genetic and environmental risk factors and common clinical electrophysiology.

PubMed

Port, Russell G; Gandal, Michael J; Roberts, Timothy P L; Siegel, Steven J; Carlson, Gregory C

2014-01-01

Most recent estimates indicate that 1 in 68 children are affected by an autism spectrum disorder (ASD). Though decades of research have uncovered much about these disorders, the pathological mechanism remains unknown. Hampering efforts is the seeming inability to integrate findings over the micro to macro scales of study, from changes in molecular, synaptic and cellular function to large-scale brain dysfunction impacting sensory, communicative, motor and cognitive activity. In this review, we describe how studies focusing on neuronal circuit function provide unique context for identifying common neurobiological disease mechanisms of ASD. We discuss how recent EEG and MEG studies in subjects with ASD have repeatedly shown alterations in ensemble population recordings (both in simple evoked related potential latencies and specific frequency subcomponents). Because these disease-associated electrophysiological abnormalities have been recapitulated in rodent models, studying circuit differences in these models may provide access to abnormal circuit function found in ASD. We then identify emerging in vivo and ex vivo techniques, focusing on how these assays can characterize circuit level dysfunction and determine if these abnormalities underlie abnormal clinical electrophysiology. Such circuit level study in animal models may help us understand how diverse genetic and environmental risks can produce a common set of EEG, MEG and anatomical abnormalities found in ASD.

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Beheim, Glenn M.; Okojie, Robert S.; Chang, Carl W.; Meredith, Roger D.; Ferrier, Terry L.; Evans, Laura J.; Krasowski, Michael J.;

Interpolator for numerically controlled machine tools

DOEpatents

Bowers, Gary L.; Davenport, Clyde M.; Stephens, Albert E.

1976-01-01

A digital differential analyzer circuit is provided that depending on the embodiment chosen can carry out linear, parabolic, circular or cubic interpolation. In the embodiment for parabolic interpolations, the circuit provides pulse trains for the X and Y slide motors of a two-axis machine to effect tool motion along a parabolic path. The pulse trains are generated by the circuit in such a way that parabolic tool motion is obtained from information contained in only one block of binary input data. A part contour may be approximated by one or more parabolic arcs. Acceleration and initial velocity values from a data block are set in fixed bit size registers for each axis separately but simultaneously and the values are integrated to obtain the movement along the respective axis as a function of time. Integration is performed by continual addition at a specified rate of an integrand value stored in one register to the remainder temporarily stored in another identical size register. Overflows from the addition process are indicative of the integral. The overflow output pulses from the second integration may be applied to motors which position the respective machine slides according to a parabolic motion in time to produce a parabolic machine tool motion in space. An additional register for each axis is provided in the circuit to allow "floating" of the radix points of the integrand registers and the velocity increment to improve position accuracy and to reduce errors encountered when the acceleration integrand magnitudes are small when compared to the velocity integrands. A divider circuit is provided in the output of the circuit to smooth the output pulse spacing and prevent motor stall, because the overflow pulses produced in the binary addition process are spaced unevenly in time. The divider has the effect of passing only every nth motor drive pulse, with n being specifiable. The circuit inputs (integrands, rates, etc.) are scaled to give exactly n times the desired number of pulses out, in order to compensate for the divider.

Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

1995-01-01

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

ISITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI (Very Large Scale Integrated) Circuits

DTIC Science & Technology

1989-12-01

rows and columns should be minimized. There are two methodologies for achieving this objective, namely, logic minimization to I I I 15 I A B C D E T...type and N-type polysilicon (Figure 2.5( b )) and interconnecting the gates with metal at a later I processing step. The two layers of aluminum available...polysiliconI ...... .. ... .. .. . .. ... .. ... .. I N polysilicon Iii~~iiiiiiii~~iiiiii (a) ( b ) 3 Figure 2.5. Controlling the Threshold Voltage in

A grid amplifier

NASA Technical Reports Server (NTRS)

Kim, Moonil; Weikle, Robert M., II; Hacker, Jonathan B.; Delisio, Michael P.; Rutledge, David B.; Rosenberg, James J.; Smith, R. P.

1991-01-01

A 50-MESFET grid amplifier is reported that has a gain of 11 dB at 3.3 GHz. The grid isolates the input from the output by using vertical polarization for the input beam and horizontal polarization for the transmitted output beam. The grid unit cell is a two-MESFET differential amplifier. A simple calibration procedure allows the gain to be calculated from a relative power measurement. This grid is a hybrid circuit, but the structure is suitable for fabrication as a monolithic wafer-scale integrated circuit, particularly at millimeter wavelengths.

Soldering Tool for Integrated Circuits

NASA Technical Reports Server (NTRS)

Takahashi, Ted H.

1987-01-01

Many connections soldered simultaneously in confined spaces. Improved soldering tool bonds integrated circuits onto printed-circuit boards. Intended especially for use with so-called "leadless-carrier" integrated circuits.

Measurement and Analysis of Multiple Output Transient Propagation in BJT Analog Circuits

NASA Astrophysics Data System (ADS)

Roche, Nicolas J.-H.; Khachatrian, A.; Warner, J. H.; Buchner, S. P.; McMorrow, D.; Clymer, D. A.

2016-08-01

The propagation of Analog Single Event Transients (ASETs) to multiple outputs of Bipolar Junction Transistor (BJTs) Integrated Circuits (ICs) is reported for the first time. The results demonstrate that ASETs can appear at several outputs of a BJT amplifier or comparator as a result of a single ion or single laser pulse strike at a single physical location on the chip of a large-scale integrated BJT analog circuit. This is independent of interconnect cross-talk or charge-sharing effects. Laser experiments, together with SPICE simulations and analysis of the ASET's propagation in the s-domain are used to explain how multiple-output transients (MOTs) are generated and propagate in the device. This study demonstrates that both the charge collection associated with an ASET and the ASET's shape, commonly used to characterize the propagation of SETs in devices and systems, are unable to explain quantitatively how MOTs propagate through an integrated analog circuit. The analysis methodology adopted here involves combining the Fourier transform of the propagating signal and the current-source transfer function in the s-domain. This approach reveals the mechanisms involved in the transient signal propagation from its point of generation to one or more outputs without the signal following a continuous interconnect path.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Reconfigurable exciton-plasmon interconversion for nanophotonic circuits

PubMed Central

Lee, Hyun Seok; Luong, Dinh Hoa; Kim, Min Su; Jin, Youngjo; Kim, Hyun; Yun, Seokjoon; Lee, Young Hee

2016-01-01

The recent challenges for improving the operation speed of nanoelectronics have motivated research on manipulating light in on-chip integrated circuits. Hybrid plasmonic waveguides with low-dimensional semiconductors, including quantum dots and quantum wells, are a promising platform for realizing sub-diffraction limited optical components. Meanwhile, two-dimensional transition metal dichalcogenides (TMDs) have received broad interest in optoelectronics owing to tightly bound excitons at room temperature, strong light-matter and exciton-plasmon interactions, available top-down wafer-scale integration, and band-gap tunability. Here, we demonstrate principal functionalities for on-chip optical communications via reconfigurable exciton-plasmon interconversions in ∼200-nm-diameter Ag-nanowires overlapping onto TMD transistors. By varying device configurations for each operation purpose, three active components for optical communications are realized: field-effect exciton transistors with a channel length of ∼32 μm, field-effect exciton multiplexers transmitting multiple signals through a single NW and electrical detectors of propagating plasmons with a high On/Off ratio of∼190. Our results illustrate the unique merits of two-dimensional semiconductors for constructing reconfigurable device architectures in integrated nanophotonic circuits. PMID:27892463

Chip-scale sensor system integration for portable health monitoring.

PubMed

Jokerst, Nan M; Brooke, Martin A; Cho, Sang-Yeon; Shang, Allan B

2007-12-01

The revolution in integrated circuits over the past 50 yr has produced inexpensive computing and communications systems that are powerful and portable. The technologies for these integrated chip-scale sensing systems, which will be miniature, lightweight, and portable, are emerging with the integration of sensors with electronics, optical systems, micromachines, microfluidics, and the integration of chemical and biological materials (soft/wet material integration with traditional dry/hard semiconductor materials). Hence, we stand at a threshold for health monitoring technology that promises to provide wearable biochemical sensing systems that are comfortable, inauspicious, wireless, and battery-operated, yet that continuously monitor health status, and can transmit compressed data signals at regular intervals, or alarm conditions immediately. In this paper, we explore recent results in chip-scale sensor integration technology for health monitoring. The development of inexpensive chip-scale biochemical optical sensors, such as microresonators, that are customizable for high sensitivity coupled with rapid prototyping will be discussed. Ground-breaking work in the integration of chip-scale optical systems to support these optical sensors will be highlighted, and the development of inexpensive Si complementary metal-oxide semiconductor circuitry (which makes up the vast majority of computational systems today) for signal processing and wireless communication with local receivers that lie directly on the chip-scale sensor head itself will be examined.

Modular electron transfer circuits for synthetic biology

PubMed Central

Agapakis, Christina M

2010-01-01

Electron transfer is central to a wide range of essential metabolic pathways, from photosynthesis to fermentation. The evolutionary diversity and conservation of proteins that transfer electrons makes these pathways a valuable platform for engineered metabolic circuits in synthetic biology. Rational engineering of electron transfer pathways containing hydrogenases has the potential to lead to industrial scale production of hydrogen as an alternative source of clean fuel and experimental assays for understanding the complex interactions of multiple electron transfer proteins in vivo. We designed and implemented a synthetic hydrogen metabolism circuit in Escherichia coli that creates an electron transfer pathway both orthogonal to and integrated within existing metabolism. The design of such modular electron transfer circuits allows for facile characterization of in vivo system parameters with applications toward further engineering for alternative energy production. PMID:21468209

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

19 CFR 10.14 - Fabricated components subject to the exemption.

Code of Federal Regulations, 2010 CFR

2010-04-01

... assembled, such as transistors, diodes, integrated circuits, machinery parts, or precut parts of wearing..., or integrated circuit wafers containing individual integrated circuit dice which have been scribed or... resulted in a substantial transformation of the foreign copper ingots. Example 2. An integrated circuit...

Corticostriatal circuit mechanisms of value-based action selection: Implementation of reinforcement learning algorithms and beyond.

PubMed

Morita, Kenji; Jitsev, Jenia; Morrison, Abigail

2016-09-15

Value-based action selection has been suggested to be realized in the corticostriatal local circuits through competition among neural populations. In this article, we review theoretical and experimental studies that have constructed and verified this notion, and provide new perspectives on how the local-circuit selection mechanisms implement reinforcement learning (RL) algorithms and computations beyond them. The striatal neurons are mostly inhibitory, and lateral inhibition among them has been classically proposed to realize "Winner-Take-All (WTA)" selection of the maximum-valued action (i.e., 'max' operation). Although this view has been challenged by the revealed weakness, sparseness, and asymmetry of lateral inhibition, which suggest more complex dynamics, WTA-like competition could still occur on short time scales. Unlike the striatal circuit, the cortical circuit contains recurrent excitation, which may enable retention or temporal integration of information and probabilistic "soft-max" selection. The striatal "max" circuit and the cortical "soft-max" circuit might co-implement an RL algorithm called Q-learning; the cortical circuit might also similarly serve for other algorithms such as SARSA. In these implementations, the cortical circuit presumably sustains activity representing the executed action, which negatively impacts dopamine neurons so that they can calculate reward-prediction-error. Regarding the suggested more complex dynamics of striatal, as well as cortical, circuits on long time scales, which could be viewed as a sequence of short WTA fragments, computational roles remain open: such a sequence might represent (1) sequential state-action-state transitions, constituting replay or simulation of the internal model, (2) a single state/action by the whole trajectory, or (3) probabilistic sampling of state/action. Copyright © 2016. Published by Elsevier B.V.

Students' Misconceptions about Medium-Scale Integrated Circuits

ERIC Educational Resources Information Center

Herman, G. L.; Loui, M. C.; Zilles, C.

2011-01-01

To improve instruction in computer engineering and computer science, instructors must better understand how their students learn. Unfortunately, little is known about how students learn the fundamental concepts in computing. To investigate student conceptions and misconceptions about digital logic concepts, the authors conducted a qualitative…

Microprocessor Seminar, phase 2

NASA Technical Reports Server (NTRS)

Scott, W. R.

1977-01-01

Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed.

Recent patents on Cu/low-k dielectrics interconnects in integrated circuits.

PubMed

Jiang, Qing; Zhu, Yong F; Zhao, Ming

2007-01-01

In past decades, the development of microelectronics has moved along with constant speed of scaling to maximize transistor density as driven by the need for electrical and functional performance. For further development, the propagation velocity of electromagnetic waves becomes increasingly important due to their unyielding constraints on interconnect delay. To minimize it, it was forced to the introduction of the Cu/low-k dielectric interconnects to very large scale integrated circuits (VLSI) where k denotes the dielectric constant. In addition, reliable barrier structures, which are the thinnest part among the device parts to maximize space availability for the actual Cu IWs, are required to prevent penetration of different materials. In light of the above statements, this review will focus recent patents and some studies on Cu interconnects including Cu interconnect wires, low-k dielectrics and related barrier materials as well manufacturing techniques in VLSI, which are one of the most essential concerns in microelectronic industry and decides the further development of VLSI. In addition, possible future development in this field is considered.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors.

PubMed

Prezioso, M; Merrikh-Bayat, F; Hoskins, B D; Adam, G C; Likharev, K K; Strukov, D B

2015-05-07

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Lithography for enabling advances in integrated circuits and devices.

PubMed

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Fabrication of superconductor-ferromagnet-insulator-superconductor Josephson junctions with critical current uniformity applicable to integrated circuits

NASA Astrophysics Data System (ADS)

Ito, Hiroshi; Taniguchi, Soya; Ishikawa, Kouta; Akaike, Hiroyuki; Fujimaki, Akira

2017-03-01

Nb Josephson junctions (JJs) were fabricated with a Pd89Ni11 ferromagnetic interlayer and an AlO x tunnel barrier layer for use in large-scale superconducting integrated circuits. The junctions had a small critical current (I c) spread, where the standard deviation 1σ was less than 2% at 4.2 K for junctions with the same designed size. It was observed that the electrical behavior of the junctions could be controlled by manipulating the film thickness of the PdNi interlayer. The junctions behaved as a π-JJ for thicknesses of 9 and 11 nm, showing 1σ in the I c spread of 1.2% for 9 nm.

Scaling prospects in mechanical energy harvesting with piezo nanowires

NASA Astrophysics Data System (ADS)

Ardila, Gustavo; Hinchet, Ronan; Mouis, Mireille; Montès, Laurent

2013-07-01

The combination of 3D processing technologies, low power circuits and new materials integration makes it conceivable to build autonomous integrated systems, which would harvest their energy from the environment. In this paper, we focus on mechanical energy harvesting and discuss its scaling prospects toward the use of piezoelectric nanostructures, able to be integrated in a CMOS environment. It is shown that direct scaling of present MEMS-based methodologies would be beneficial for high-frequency applications only. For the range of applications which is presently foreseen, a different approach is needed, based on energy harvesting from direct real-time deformation instead of energy harvesting from vibration modes at or close to resonance. We discuss the prospects of such an approach based on simple scaling rules Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Convergence of circuit dysfunction in ASD: a common bridge between diverse genetic and environmental risk factors and common clinical electrophysiology

PubMed Central

Port, Russell G.; Gandal, Michael J.; Roberts, Timothy P. L.; Siegel, Steven J.; Carlson, Gregory C.

2014-01-01

Most recent estimates indicate that 1 in 68 children are affected by an autism spectrum disorder (ASD). Though decades of research have uncovered much about these disorders, the pathological mechanism remains unknown. Hampering efforts is the seeming inability to integrate findings over the micro to macro scales of study, from changes in molecular, synaptic and cellular function to large-scale brain dysfunction impacting sensory, communicative, motor and cognitive activity. In this review, we describe how studies focusing on neuronal circuit function provide unique context for identifying common neurobiological disease mechanisms of ASD. We discuss how recent EEG and MEG studies in subjects with ASD have repeatedly shown alterations in ensemble population recordings (both in simple evoked related potential latencies and specific frequency subcomponents). Because these disease-associated electrophysiological abnormalities have been recapitulated in rodent models, studying circuit differences in these models may provide access to abnormal circuit function found in ASD. We then identify emerging in vivo and ex vivo techniques, focusing on how these assays can characterize circuit level dysfunction and determine if these abnormalities underlie abnormal clinical electrophysiology. Such circuit level study in animal models may help us understand how diverse genetic and environmental risks can produce a common set of EEG, MEG and anatomical abnormalities found in ASD. PMID:25538564

Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

DTIC Science & Technology

2013-12-01

Prototype Board SBU single bit upset SDK software development kit SDRAM synchronous dynamic random-access memory SEB single-event burnout ...current VHDL VHSIC hardware description language VHSIC very-high-speed integrated circuits VLSI very-large- scale integration VQFP very...transient pulse, called a single-event transient (SET), or even cause permanent damage to the device in the form of a burnout or gate rupture. The SEE

FAST: a framework for simulation and analysis of large-scale protein-silicon biosensor circuits.

PubMed

Gu, Ming; Chakrabartty, Shantanu

2013-08-01

This paper presents a computer aided design (CAD) framework for verification and reliability analysis of protein-silicon hybrid circuits used in biosensors. It is envisioned that similar to integrated circuit (IC) CAD design tools, the proposed framework will be useful for system level optimization of biosensors and for discovery of new sensing modalities without resorting to laborious fabrication and experimental procedures. The framework referred to as FAST analyzes protein-based circuits by solving inverse problems involving stochastic functional elements that admit non-linear relationships between different circuit variables. In this regard, FAST uses a factor-graph netlist as a user interface and solving the inverse problem entails passing messages/signals between the internal nodes of the netlist. Stochastic analysis techniques like density evolution are used to understand the dynamics of the circuit and estimate the reliability of the solution. As an example, we present a complete design flow using FAST for synthesis, analysis and verification of our previously reported conductometric immunoassay that uses antibody-based circuits to implement forward error-correction (FEC).

Calculation of transient potential rise on the wind turbine struck by lightning.

PubMed

Xiaoqing, Zhang

2014-01-01

A circuit model is proposed in this paper for calculating the transient potential rise on the wind turbine struck by lightning. The model integrates the blade, sliding contact site, and tower and grounding system of the wind turbine into an equivalent circuit. The lightning current path from the attachment point to the ground can be fully described by the equivalent circuit. The transient potential responses are obtained in the different positions on the wind turbine by solving the circuit equations. In order to check the validity of the model, the laboratory measurement is made with a reduced-scale wind turbine. The measured potential waveform is compared with the calculated one and a better agreement is shown between them. The practical applicability of the model is also examined by a numerical example of a 2 MW Chinese-built wind turbine.

Scalable Manufacturing of Solderable and Stretchable Physiologic Sensing Systems.

PubMed

Kim, Yun-Soung; Lu, Jesse; Shih, Benjamin; Gharibans, Armen; Zou, Zhanan; Matsuno, Kristen; Aguilera, Roman; Han, Yoonjae; Meek, Ann; Xiao, Jianliang; Tolley, Michael T; Coleman, Todd P

2017-10-01

Methods for microfabrication of solderable and stretchable sensing systems (S4s) and a scaled production of adhesive-integrated active S4s for health monitoring are presented. S4s' excellent solderability is achieved by the sputter-deposited nickel-vanadium and gold pad metal layers and copper interconnection. The donor substrate, which is modified with "PI islands" to become selectively adhesive for the S4s, allows the heterogeneous devices to be integrated with large-area adhesives for packaging. The feasibility for S4-based health monitoring is demonstrated by developing an S4 integrated with a strain gauge and an onboard optical indication circuit. Owing to S4s' compatibility with the standard printed circuit board assembly processes, a variety of commercially available surface mount chip components, such as the wafer level chip scale packages, chip resistors, and light-emitting diodes, can be reflow-soldered onto S4s without modifications, demonstrating the versatile and modular nature of S4s. Tegaderm-integrated S4 respiration sensors are tested for robustness for cyclic deformation, maximum stretchability, durability, and biocompatibility for multiday wear time. The results of the tests and demonstration of the respiration sensing indicate that the adhesive-integrated S4s can provide end users a way for unobtrusive health monitoring. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Interchip link system using an optical wiring method.

PubMed

Cho, In-Kui; Ryu, Jin-Hwa; Jeong, Myung-Yung

2008-08-15

A chip-scale optical link system is presented with a transmitter/receiver and optical wire link. The interchip link system consists of a metal optical bench, a printed circuit board module, a driver/receiver integrated circuit, a vertical cavity surface-emitting laser/photodiode array, and an optical wire link composed of plastic optical fibers (POFs). We have developed a downsized POF and an optical wiring method that allows on-site installation with a simple annealing as optical wiring technologies for achieving high-density optical interchip interconnection within such devices. Successful data transfer measurements are presented.

Minimizing the area required for time constants in integrated circuits

NASA Technical Reports Server (NTRS)

Lyons, J. C.

1972-01-01

When a medium- or large-scale integrated circuit is designed, efforts are usually made to avoid the use of resistor-capacitor time constant generators. The capacitor needed for this circuit usually takes up more surface area on the chip than several resistors and transistors. When the use of this network is unavoidable, the designer usually makes an effort to see that the choice of resistor and capacitor combinations is such that a minimum amount of surface area is consumed. The optimum ratio of resistance to capacitance that will result in this minimum area is equal to the ratio of resistance to capacitance which may be obtained from a unit of surface area for the particular process being used. The minimum area required is a function of the square root of the reciprocal of the products of the resistance and capacitance per unit area. This minimum occurs when the area required by the resistor is equal to the area required by the capacitor.

Integrated bio-photonics to revolutionize health care enabled through PIX4life and PIXAPP

NASA Astrophysics Data System (ADS)

Jans, Hilde; O'Brien, Peter; Artundo, Iñigo; Porcel, Marco A. G.; Hoofman, Romano; Geuzebroek, Douwe; Dumon, Pieter; van der Vliet, Marcel; Witzens, Jeremy; Bourguignon, Eric; Van Dorpe, Pol; Lagae, Liesbet

2018-02-01

Photonics has become critical to life sciences. However, the field is far from benefiting fully from photonics' capabilities. Today, bulky and expensive optical systems dominate biomedical photonics, even though robust optical functionality can be realized cost-effectively on single photonic integrated circuits (PICs). Such chips are commercially available mostly for telecom applications, and at infrared wavelengths. Although proof-of-concept demonstrations for PICs in life sciences, using visible wavelengths are abundant, the gating factor for wider adoption is limited in resource capacity. Two European pilot lines, PIX4life and PIXAPP, were established to facilitate European R and D in biophotonics, by helping European companies and universities bridge the gap between research and industrial development. Through creation of an open-access model, PIX4life aims to lower barriers to entry for prototyping and validating biophotonics concepts for larger scale production. In addition, PIXAPP enables the assembly and packaging of photonic integrated circuits.

Biosensor system-on-a-chip including CMOS-based signal processing circuits and 64 carbon nanotube-based sensors for the detection of a neurotransmitter.

PubMed

Lee, Byung Yang; Seo, Sung Min; Lee, Dong Joon; Lee, Minbaek; Lee, Joohyung; Cheon, Jun-Ho; Cho, Eunju; Lee, Hyunjoong; Chung, In-Young; Park, Young June; Kim, Suhwan; Hong, Seunghun

2010-04-07

We developed a carbon nanotube (CNT)-based biosensor system-on-a-chip (SoC) for the detection of a neurotransmitter. Here, 64 CNT-based sensors were integrated with silicon-based signal processing circuits in a single chip, which was made possible by combining several technological breakthroughs such as efficient signal processing, uniform CNT networks, and biocompatible functionalization of CNT-based sensors. The chip was utilized to detect glutamate, a neurotransmitter, where ammonia, a byproduct of the enzymatic reaction of glutamate and glutamate oxidase on CNT-based sensors, modulated the conductance signals to the CNT-based sensors. This is a major technological advancement in the integration of CNT-based sensors with microelectronics, and this chip can be readily integrated with larger scale lab-on-a-chip (LoC) systems for various applications such as LoC systems for neural networks.

S-MMICs: Sub-mm-Wave Transistors and Integrated Circuits

DTIC Science & Technology

2008-09-01

Research Lab BAA DAAD19-03-R-0017 Research area 2.35: RF devices—Dr. Alfred Hung Submitted by: Mark Rodwell, Department of Electrical and Computer ...MOTIVATION / APPLICATION 3 TECHNOLOGY STATUS 4 TRANSISTOR SCALING LAWS 5 256 NM GENERATION 6 HBT POWER AMPLIFIER DEVELOPMENT 7 DRY-ETCHED EMITTER...TECHNOLOGY: 256 NM GENERATION 9 SCALED EPITAXY 11 CONCLUSIONS 12 20081103013 Executive Summary Transistor and power amplifier IC technology was

Design automation for integrated nonlinear logic circuits (Conference Presentation)

NASA Astrophysics Data System (ADS)

Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

2016-05-01

A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite PCells (modules) which consist of primitive building-block PCells (components). To automatically produce layouts, we built on a construct provided by Luceda called a PlaceAndAutoRoute cell: we create a module component by supplying a list of child cells, and a list of the desired connections between the cells (e.g. the out0 port of a microring is connected to a grating coupler). This functionality allowed us to write algorithms to automatically lay out the components: for instance, by laying out the first component and walking through the list of connections to check to see if the next component is already placed or not. The placement and orientation of the new component is determined by minimizing the length of a connecting waveguide. Our photonic circuits also utilize electrical signals to tune the photonic elements (setting propagation phases or microring resonant frequencies via thermo-optical tuning): the algorithm also routes the contacts for the metal heaters to contact pads at the edge of the circuit being designed where it can be contacted by electrical probes. We are currently validating a test run fabricated over the summer, and will use detailed characterization results to prepare our final design cycle in which we aim to demonstrate complex operational logic circuits containing ~50-100 nonlinear resonators.

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

NASA Technical Reports Server (NTRS)

1975-01-01

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

Parallelism in integrated fluidic circuits

NASA Astrophysics Data System (ADS)

Bousse, Luc J.; Kopf-Sill, Anne R.; Parce, J. W.

1998-04-01

Many research groups around the world are working on integrated microfluidics. The goal of these projects is to automate and integrate the handling of liquid samples and reagents for measurement and assay procedures in chemistry and biology. Ultimately, it is hoped that this will lead to a revolution in chemical and biological procedures similar to that caused in electronics by the invention of the integrated circuit. The optimal size scale of channels for liquid flow is determined by basic constraints to be somewhere between 10 and 100 micrometers . In larger channels, mixing by diffusion takes too long; in smaller channels, the number of molecules present is so low it makes detection difficult. At Caliper, we are making fluidic systems in glass chips with channels in this size range, based on electroosmotic flow, and fluorescence detection. One application of this technology is rapid assays for drug screening, such as enzyme assays and binding assays. A further challenge in this area is to perform multiple functions on a chip in parallel, without a large increase in the number of inputs and outputs. A first step in this direction is a fluidic serial-to-parallel converter. Fluidic circuits will be shown with the ability to distribute an incoming serial sample stream to multiple parallel channels.

Automatic visual inspection system for microelectronics

NASA Technical Reports Server (NTRS)

Micka, E. Z. (Inventor)

1975-01-01

A system for automatically inspecting an integrated circuit was developed. A device for shining a scanning narrow light beam at an integrated circuit to be inspected and another light beam at an accepted integrated circuit was included. A pair of photodetectors that receive light reflected from these integrated circuits, and a comparing system compares the outputs of the photodetectors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Design structure for in-system redundant array repair in integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.

PubMed

Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

2015-02-01

We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (<30 μm), and high-density (up to ~500 μF/mm(2)) micro-supercapacitors are formed on an ultrathin (~20 μm) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications.

Laser Integration on Silicon Photonic Circuits Through Transfer Printing

DTIC Science & Technology

2017-03-10

AFRL-AFOSR-UK-TR-2017-0019 Laser integration on silicon photonic circuits through transfer printing Gunther Roelkens UNIVERSITEIT GENT VZW Final...TYPE Final 3. DATES COVERED (From - To) 15 Sep 2015 to 14 Sep 2016 4. TITLE AND SUBTITLE Laser integration on silicon photonic circuits through...parallel integration of III-V lasers on silicon photonic integrated circuits. The report discusses the technological process that has been developed as

Analog Binaural Circuits for Detecting and Locating Leaks

NASA Technical Reports Server (NTRS)

Hartley, Frank T.

2003-01-01

Very-large-scale integrated (VLSI) analog binaural signal-processing circuits have been proposed for use in detecting and locating leaks that emit noise in the ultrasonic frequency range. These circuits would be designed to function even in the presence of intense lower-frequency background noise that could include sounds associated with flow and pumping. Each of the proposed circuits would include the approximate electronic equivalent of a right and a left cochlea plus correlator circuits. A pair of transducers (microphones or accelerometers), corresponding to right and left ears, would provide the inputs to their respective cochleas from different locations (e.g., from different positions along a pipe). The correlation circuits plus some additional external circuits would determine the difference between the times of arrival of a common leak sound at the two transducers. Then the distance along the pipe from either transducer to the leak could be estimated from the time difference and the speed of sound along the pipe. If three or more pairs of transducers and cochlear/correlator circuits were available and could suitably be positioned, it should be possible to locate a leak in three dimensions by use of sound propagating through air.

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

PubMed

Gao, Pingqi; Zhang, Qing

2014-02-14

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

High density circuit technology, part 2

NASA Technical Reports Server (NTRS)

Wade, T. E.

1982-01-01

A multilevel metal interconnection system for very large scale integration (VLSI) systems utilizing polyimides as the interlayer dielectric material is described. A complete characterization of polyimide materials is given as well as experimental methods accomplished using a double level metal test pattern. A low temperature, double exposure polyimide patterning procedure is also presented.

Nuclear resonant scattering measurements on (57)Fe by multichannel scaling with a 64-pixel silicon avalanche photodiode linear-array detector.

PubMed

Kishimoto, S; Mitsui, T; Haruki, R; Yoda, Y; Taniguchi, T; Shimazaki, S; Ikeno, M; Saito, M; Tanaka, M

2014-11-01

We developed a silicon avalanche photodiode (Si-APD) linear-array detector for use in nuclear resonant scattering experiments using synchrotron X-rays. The Si-APD linear array consists of 64 pixels (pixel size: 100 × 200 μm(2)) with a pixel pitch of 150 μm and depletion depth of 10 μm. An ultrafast frontend circuit allows the X-ray detector to obtain a high output rate of >10(7) cps per pixel. High-performance integrated circuits achieve multichannel scaling over 1024 continuous time bins with a 1 ns resolution for each pixel without dead time. The multichannel scaling method enabled us to record a time spectrum of the 14.4 keV nuclear radiation at each pixel with a time resolution of 1.4 ns (FWHM). This method was successfully applied to nuclear forward scattering and nuclear small-angle scattering on (57)Fe.

Circuit-Host Coupling Induces Multifaceted Behavioral Modulations of a Gene Switch.

PubMed

Blanchard, Andrew E; Liao, Chen; Lu, Ting

2018-02-06

Quantitative modeling of gene circuits is fundamentally important to synthetic biology, as it offers the potential to transform circuit engineering from trial-and-error construction to rational design and, hence, facilitates the advance of the field. Currently, typical models regard gene circuits as isolated entities and focus only on the biochemical processes within the circuits. However, such a standard paradigm is getting challenged by increasing experimental evidence suggesting that circuits and their host are intimately connected, and their interactions can potentially impact circuit behaviors. Here we systematically examined the roles of circuit-host coupling in shaping circuit dynamics by using a self-activating gene switch as a model circuit. Through a combination of deterministic modeling, stochastic simulation, and Fokker-Planck equation formalism, we found that circuit-host coupling alters switch behaviors across multiple scales. At the single-cell level, it slows the switch dynamics in the high protein production regime and enlarges the difference between stable steady-state values. At the population level, it favors cells with low protein production through differential growth amplification. Together, the two-level coupling effects induce both quantitative and qualitative modulations of the switch, with the primary component of the effects determined by the circuit's architectural parameters. This study illustrates the complexity and importance of circuit-host coupling in modulating circuit behaviors, demonstrating the need for a new paradigm-integrated modeling of the circuit-host system-for quantitative understanding of engineered gene networks. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

Graphene radio frequency receiver integrated circuit.

PubMed

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Graphene radio frequency receiver integrated circuit

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A.; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Monolithically integrated bacteriorhodopsin/semiconductor opto-electronic integrated circuit for a bio-photoreceiver.

PubMed

Xu, J; Bhattacharya, P; Váró, G

2004-03-15

The light-sensitive protein, bacteriorhodopsin (BR), is monolithically integrated with an InP-based amplifier circuit to realize a novel opto-electronic integrated circuit (OEIC) which performs as a high-speed photoreceiver. The circuit is realized by epitaxial growth of the field-effect transistors, currently used semiconductor device and circuit fabrication techniques, and selective area BR electro-deposition. The integrated photoreceiver has a responsivity of 175 V/W and linear photoresponse, with a dynamic range of 16 dB, with 594 nm photoexcitation. The dynamics of the photochemical cycle of BR has also been modeled and a proposed equivalent circuit simulates the measured BR photoresponse with good agreement.

Advanced On-Board Processor (AOP). [for future spacecraft applications

NASA Technical Reports Server (NTRS)

1973-01-01

Advanced On-board Processor the (AOP) uses large scale integration throughout and is the most advanced space qualified computer of its class in existence today. It was designed to satisfy most spacecraft requirements which are anticipated over the next several years. The AOP design utilizes custom metallized multigate arrays (CMMA) which have been designed specifically for this computer. This approach provides the most efficient use of circuits, reduces volume, weight, assembly costs and provides for a significant increase in reliability by the significant reduction in conventional circuit interconnections. The required 69 CMMA packages are assembled on a single multilayer printed circuit board which together with associated connectors constitutes the complete AOP. This approach also reduces conventional interconnections thus further reducing weight, volume and assembly costs.

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, Anthony F.

1993-01-01

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multichip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, A.F.

1993-06-08

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multi chip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

Photonic Integrated Circuits for Cost-Effective, High Port Density, and Higher Capacity Optical Communications Systems

NASA Astrophysics Data System (ADS)

Chiappa, Pierangelo

Bandwidth-hungry services, such as higher speed Internet, voice over IP (VoIP), and IPTV, allow people to exchange and store huge amounts of data among worldwide locations. In the age of global communications, domestic users, companies, and organizations around the world generate new contents making bandwidth needs grow exponentially, along with the need for new services. These bandwidth and connectivity demands represent a concern for operators who require innovative technologies to be ready for scaling. To respond efficiently to these demands, Alcatel-Lucent is fast moving toward photonic integration circuits technologies as the key to address best performances at the lowest "bit per second" cost. This article describes Alcatel-Lucent's contribution in strategic directions or achievements, as well as possible new developments.

Nanotubes May Break Through "Chip Wall"

NASA Technical Reports Server (NTRS)

Laufenberg, Larry

2003-01-01

In 1965, just four years after the first planar integrated circuit (IC) was discovered, Cordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law" For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that may soon block the continued scaling predicted by by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known manufacturable solution exists. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.

Optogenetic interrogation of neural circuits: technology for probing mammalian brain structures

PubMed Central

Zhang, Feng; Gradinaru, Viviana; Adamantidis, Antoine R; Durand, Remy; Airan, Raag D; de Lecea, Luis; Deisseroth, Karl

2015-01-01

Elucidation of the neural substrates underlying complex animal behaviors depends on precise activity control tools, as well as compatible readout methods. Recent developments in optogenetics have addressed this need, opening up new possibilities for systems neuroscience. Interrogation of even deep neural circuits can be conducted by directly probing the necessity and sufficiency of defined circuit elements with millisecond-scale, cell type-specific optical perturbations, coupled with suitable readouts such as electrophysiology, optical circuit dynamics measures and freely moving behavior in mammals. Here we collect in detail our strategies for delivering microbial opsin genes to deep mammalian brain structures in vivo, along with protocols for integrating the resulting optical control with compatible readouts (electrophysiological, optical and behavioral). The procedures described here, from initial virus preparation to systems-level functional readout, can be completed within 4–5 weeks. Together, these methods may help in providing circuit-level insight into the dynamics underlying complex mammalian behaviors in health and disease. PMID:20203662

Molecular-Scale Electronics: From Concept to Function.

PubMed

Xiang, Dong; Wang, Xiaolong; Jia, Chuancheng; Lee, Takhee; Guo, Xuefeng

2016-04-13

Creating functional electrical circuits using individual or ensemble molecules, often termed as "molecular-scale electronics", not only meets the increasing technical demands of the miniaturization of traditional Si-based electronic devices, but also provides an ideal window of exploring the intrinsic properties of materials at the molecular level. This Review covers the major advances with the most general applicability and emphasizes new insights into the development of efficient platform methodologies for building reliable molecular electronic devices with desired functionalities through the combination of programmed bottom-up self-assembly and sophisticated top-down device fabrication. First, we summarize a number of different approaches of forming molecular-scale junctions and discuss various experimental techniques for examining these nanoscale circuits in details. We then give a full introduction of characterization techniques and theoretical simulations for molecular electronics. Third, we highlight the major contributions and new concepts of integrating molecular functionalities into electrical circuits. Finally, we provide a critical discussion of limitations and main challenges that still exist for the development of molecular electronics. These analyses should be valuable for deeply understanding charge transport through molecular junctions, the device fabrication process, and the roadmap for future practical molecular electronics.

Calculation of Transient Potential Rise on the Wind Turbine Struck by Lightning

PubMed Central

Xiaoqing, Zhang

2014-01-01

A circuit model is proposed in this paper for calculating the transient potential rise on the wind turbine struck by lightning. The model integrates the blade, sliding contact site, and tower and grounding system of the wind turbine into an equivalent circuit. The lightning current path from the attachment point to the ground can be fully described by the equivalent circuit. The transient potential responses are obtained in the different positions on the wind turbine by solving the circuit equations. In order to check the validity of the model, the laboratory measurement is made with a reduced-scale wind turbine. The measured potential waveform is compared with the calculated one and a better agreement is shown between them. The practical applicability of the model is also examined by a numerical example of a 2 MW Chinese-built wind turbine. PMID:25254231

Ultra-smooth glassy graphene thin films for flexible transparent circuits

PubMed Central

Dai, Xiao; Wu, Jiang; Qian, Zhicheng; Wang, Haiyan; Jian, Jie; Cao, Yingjie; Rummeli, Mark H.; Yi, Qinghua; Liu, Huiyun; Zou, Guifu

2016-01-01

Large-area graphene thin films are prized in flexible and transparent devices. We report on a type of glassy graphene that is in an intermediate state between glassy carbon and graphene and that has high crystallinity but curly lattice planes. A polymer-assisted approach is introduced to grow an ultra-smooth (roughness, <0.7 nm) glassy graphene thin film at the inch scale. Owing to the advantages inherited by the glassy graphene thin film from graphene and glassy carbon, the glassy graphene thin film exhibits conductivity, transparency, and flexibility comparable to those of graphene, as well as glassy carbon–like mechanical and chemical stability. Moreover, glassy graphene–based circuits are fabricated using a laser direct writing approach. The circuits are transferred to flexible substrates and are shown to perform reliably. The glassy graphene thin film should stimulate the application of flexible transparent conductive materials in integrated circuits. PMID:28138535

Nonreciprocal signal routing in an active quantum network

NASA Astrophysics Data System (ADS)

Metelmann, A.; Türeci, H. E.

2018-04-01

As superconductor quantum technologies are moving towards large-scale integrated circuits, a robust and flexible approach to routing photons at the quantum level becomes a critical problem. Active circuits, which contain parametrically driven elements selectively embedded in the circuit, offer a viable solution. Here, we present a general strategy for routing nonreciprocally quantum signals between two sites of a given lattice of oscillators, implementable with existing superconducting circuit components. Our approach makes use of a dual lattice of overdamped oscillators linking the nodes of the main lattice. Solutions for spatially selective driving of the lattice elements can be found, which optimally balance coherent and dissipative hopping of microwave photons to nonreciprocally route signals between two given nodes. In certain lattices these optimal solutions are obtained at the exceptional point of the dynamical matrix of the network. We also demonstrate that signal and noise transmission characteristics can be separately optimized.

George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

NASA Astrophysics Data System (ADS)

Doering, Robert

In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

Imbalance aware lithography hotspot detection: a deep learning approach

NASA Astrophysics Data System (ADS)

Yang, Haoyu; Luo, Luyang; Su, Jing; Lin, Chenxi; Yu, Bei

2017-07-01

With the advancement of very large scale integrated circuits (VLSI) technology nodes, lithographic hotspots become a serious problem that affects manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with the extreme scaling of transistor feature size and layout patterns growing in complexity, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. We present a deep convolutional neural network (CNN) that targets representative feature learning in lithography hotspot detection. We carefully analyze the impact and effectiveness of different CNN hyperparameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always in the minority in VLSI mask design, the training dataset is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from a high number of false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply hotspot upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

Compact component for integrated quantum optic processing

PubMed Central

Sahu, Partha Pratim

2015-01-01

Quantum interference is indispensable to derive integrated quantum optic technologies (1–2). For further progress in large scale integration of quantum optic circuit, we have introduced first time two mode interference (TMI) coupler as an ultra compact component. The quantum interference varying with coupling length corresponding to the coupling ratio is studied and the larger HOM dip with peak visibility ~0.963 ± 0.009 is found at half coupling length of TMI coupler. Our results also demonstrate complex quantum interference with high fabrication tolerance and quantum visibility in TMI coupler. PMID:26584759

Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-12-09

Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Electro-optical Probing Of Terahertz Integrated Circuits

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

1990-01-01

Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

Monolithic Microwave Integrated Circuits Based on GaAs Mesfet Technology

NASA Astrophysics Data System (ADS)

Bahl, Inder J.

Advanced military microwave systems are demanding increased integration, reliability, radiation hardness, compact size and lower cost when produced in large volume, whereas the microwave commercial market, including wireless communications, mandates low cost circuits. Monolithic Microwave Integrated Circuit (MMIC) technology provides an economically viable approach to meeting these needs. In this paper the design considerations for several types of MMICs and their performance status are presented. Multifunction integrated circuits that advance the MMIC technology are described, including integrated microwave/digital functions and a highly integrated transceiver at C-band.

Wide-band polarization controller for Si photonic integrated circuits.

PubMed

Velha, P; Sorianello, V; Preite, M V; De Angelis, G; Cassese, T; Bianchi, A; Testa, F; Romagnoli, M

2016-12-15

A circuit for the management of any arbitrary polarization state of light is demonstrated on an integrated silicon (Si) photonics platform. This circuit allows us to adapt any polarization into the standard fundamental TE mode of a Si waveguide and, conversely, to control the polarization and set it to any arbitrary polarization state. In addition, the integrated thermal tuning allows kilohertz speed which can be used to perform a polarization scrambler. The circuit was used in a WDM link and successfully used to adapt four channels into a standard Si photonic integrated circuit.

Hybrid VLSI/QCA Architecture for Computing FFTs

NASA Technical Reports Server (NTRS)

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Hard and flexible optical printed circuit board

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, Hyun Sik; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.

2007-02-01

We report on the design and fabrication of hard and flexible optical printed circuit boards (O-PCBs). The objective is to realize generic and application-specific O-PCBs, either in hard form or flexible form, that are compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly, for low-cost and high-volume universal applications. The O-PCBs consist of 2-dimensional planar arrays of micro/nano-scale optical wires, circuits and devices that are interconnected and integrated to perform the functions of sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards. For fabrication, the polymer and organic optical wires and waveguides are first fabricated on a board and are used to interconnect and integrate micro/nano-scale photonic devices. The micro/nano-optical functional devices include lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices. For flexible boards, the optical waveguide arrays are fabricated on flexible poly-ethylen terephthalate (PET) substrates by UV embossing. Electrical layer carrying VCSEL and PD array is laminated with the optical layer carrying waveguide arrays. Both hard and flexible electrical lines are replaced with high speed optical interconnection between chips over four waveguide channels up to 10Gbps on each. We discuss uses of hard or flexible O-PCBs for telecommunication systems, computer systems, transportation systems, space/avionic systems, and bio-sensor systems.

General technique for the integration of MIC/MMIC'S with waveguides

NASA Technical Reports Server (NTRS)

Geller, Bernard D. (Inventor); Zaghloul, Amir I. (Inventor)

1987-01-01

A technique for packaging and integrating of a microwave integrated circuit (MIC) or monolithic microwave integrated circuit (MMIC) with a waveguide uses a printed conductive circuit pattern on a dielectric substrate to transform impedance and mode of propagation between the MIC/MMIC and the waveguide. The virtually coplanar circuit pattern lies on an equipotential surface within the waveguide and therefore makes possible single or dual polarized mode structures.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

The Quartz Analog Watch: A Wonder Machine.

ERIC Educational Resources Information Center

Crane, H. Richard, Ed.

1993-01-01

Summarizes how a quartz watch works. Discusses the quartz crystal, its form, and how its frequency is set to a standard; the integrated circuit chip that drives the crystal in vibration, scales its frequency down, and forms pulses that turn the motor; and the motor that drives the gear train that turns the hands. (ZWH)

Interactionist Neuroscience.

PubMed

Badre, David; Frank, Michael J; Moore, Christopher I

2015-12-02

We argue that bidirectional interaction between animal and human studies is essential for understanding the human brain. The revolution in meso-scale study of circuits in non-human species provides a historical opportunity. However, to fully realize its potential requires integration with human neuroscience. We describe three strategies for successful interactionist neuroscience. Copyright © 2015 Elsevier Inc. All rights reserved.

Parallel stitching of 2D materials

DOE PAGES

Ling, Xi; Wu, Lijun; Lin, Yuxuan; ...

2016-01-27

Diverse parallel stitched 2D heterostructures, including metal–semiconductor, semiconductor–semiconductor, and insulator–semiconductor, are synthesized directly through selective “sowing” of aromatic molecules as the seeds in the chemical vapor deposition (CVD) method. Lastly, the methodology enables the large-scale fabrication of lateral heterostructures, which offers tremendous potential for its application in integrated circuits.

A Microcomputer-Based Program for Printing Check Plots of Integrated Circuits Specified in Caltech Intermediate Form.

DTIC Science & Technology

1984-12-01

only four transistors[5]. Each year since that time, the semiconductor industry has con- sistently improved the quality of the fabrication tech- niques...rarely took place at universities and was almost exclusively confined to industry . IC design techniques were developed, tested, and taught only in the...community, it is not uncommon for industry to borrow ideas and even particular programs from these university designed tools. The Very Large Scale Integration

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET

NASA Astrophysics Data System (ADS)

Maity, Subir Kr.; Pandit, Soumya

2017-11-01

InGaAs is an attractive choice as alternate channel material in n-channel metal oxide semiconductor transistor for high-performance applications. However, electrostatic integrity of such device is poor. In this paper, we present a comprehensive technology computer-aided design simulation-based study of the effect of scaling the thickness of the buried oxide (BOX) region and varying the dielectric constant of BOX material on the electrostatic integrity, analogue/radio frequency (RF) performance and circuit performance of InGaAs-on-Insulator device. Device with thin BOX layer gives better drain-induced barrier lowering performance which enhances output resistance. The carrier mobility remains almost constant with thinning of BOX layer up to certain value. By lowering the dielectric constant of the BOX material, it is further possible to improve the analogue and RF performance. Effect of BOX thickness scaling and role of BOX dielectric material on gain-frequency response of common source amplifier is also studied. It is observed that frequency response of the amplifier improves for thin BOX and with low dielectric constant-based material.

Laser drilling of vias in dielectric for high density multilayer LSHI thick film circuits

NASA Technical Reports Server (NTRS)

Cocca, T.; Dakesian, S.

1977-01-01

A design analysis of a high density multilevel thick film digital microcircuit used for large scale integration is presented. The circuit employs 4 mil lines, 4 mil spaces and requires 4 mil diameter vias. Present screened and fired thick film technology is limited on a production basis to 16 mil square vias. A process whereby 4 mil diameter vias can be fabricated in production using laser technology was described along with a process to produce 4 mil diameter vias for conductor patterns which have 4 mil lines and 4 mil spacings.

Thermooptic two-mode interference device for reconfigurable quantum optic circuits

NASA Astrophysics Data System (ADS)

Sahu, Partha Pratim

2018-06-01

Reconfigurable large-scale integrated quantum optic circuits require compact component having capability of accurate manipulation of quantum entanglement for quantum communication and information processing applications. Here, a thermooptic two-mode interference coupler has been introduced as a compact component for generation of reconfigurable complex multi-photons quantum interference. Both theoretical and experimental approaches are used for the demonstration of two-photon and four-photon quantum entanglement manipulated with thermooptic phase change in TMI region. Our results demonstrate complex multi-photon quantum interference with high fabrication tolerance and quantum fidelity in smaller dimension than previous thermooptic Mach-Zehnder implementations.

Current limiter circuit system

DOEpatents

Witcher, Joseph Brandon; Bredemann, Michael V.

2017-09-05

An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

Integrated circuits, and design and manufacture thereof

DOEpatents

Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

2006-04-18

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

PubMed

Nakazato, Kazuo

2014-03-28

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

PubMed

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

Reusable vibration resistant integrated circuit mounting socket

DOEpatents

Evans, Craig N.

1995-01-01

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

PubMed

Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

PubMed Central

Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V.

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification. PMID:26798055

Macromodels of digital integrated circuits for program packages of circuit engineering design

NASA Astrophysics Data System (ADS)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

Integrated coherent matter wave circuits

DOE PAGES

Ryu, C.; Boshier, M. G.

2015-09-21

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

Neuromorphic Silicon Neuron Circuits

PubMed Central

Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

2011-01-01

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

Methods of fabricating applique circuits

DOEpatents

Dimos, Duane B.; Garino, Terry J.

1999-09-14

Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

A simple structure wavelet transform circuit employing function link neural networks and SI filters

NASA Astrophysics Data System (ADS)

Mu, Li; Yigang, He

2016-12-01

Signal processing by means of analog circuits offers advantages from a power consumption viewpoint. Implementing wavelet transform (WT) using analog circuits is of great interest when low-power consumption becomes an important issue. In this article, a novel simple structure WT circuit in analog domain is presented by employing functional link neural network (FLNN) and switched-current (SI) filters. First, the wavelet base is approximated using FLNN algorithms for giving a filter transfer function that is suitable for simple structure WT circuit implementation. Next, the WT circuit is constructed with the wavelet filter bank, whose impulse response is the approximated wavelet and its dilations. The filter design that follows is based on a follow-the-leader feedback (FLF) structure with multiple output bilinear SI integrators and current mirrors as the main building blocks. SI filter is well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by the clock frequency of the circuit with the same system architecture. Finally, to illustrate the design procedure, a seventh-order FLNN-approximated Gaussian wavelet is implemented as an example. Simulations have successfully verified that the designed simple structure WT circuit has low sensitivity, low-power consumption and litter effect to the imperfections.

A closed-loop compressive-sensing-based neural recording system.

PubMed

Zhang, Jie; Mitra, Srinjoy; Suo, Yuanming; Cheng, Andrew; Xiong, Tao; Michon, Frederic; Welkenhuysen, Marleen; Kloosterman, Fabian; Chin, Peter S; Hsiao, Steven; Tran, Trac D; Yazicioglu, Firat; Etienne-Cummings, Ralph

2015-06-01

This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device. The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases. Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500-6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm(2)/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode. Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording.

Low-loss, compact, and fabrication-tolerant Si-wire 90° waveguide bend using clothoid and normal curves for large scale photonic integrated circuits.

PubMed

Fujisawa, Takeshi; Makino, Shuntaro; Sato, Takanori; Saitoh, Kunimasa

2017-04-17

Ultimately low-loss 90° waveguide bend composed of clothoid and normal curves is proposed for dense optical interconnect photonic integrated circuits. By using clothoid curves at the input and output of 90° waveguide bend, straight and bent waveguides are smoothly connected without increasing the footprint. We found that there is an optimum ratio of clothoid curves in the bend and the bending loss can be significantly reduced compared with normal bend. 90% reduction of the bending loss for the bending radius of 4 μm is experimentally demonstrated with excellent agreement between theory and experiment. The performance is compared with the waveguide bend with offset, and the proposed bend is superior to the waveguide bend with offset in terms of fabrication tolerance.

Force-controlled inorganic crystallization lithography.

PubMed

Cheng, Chao-Min; LeDuc, Philip R

2006-09-20

Lithography plays a key role in integrated circuits, optics, information technology, biomedical applications, catalysis, and separation technologies. However, inorganic lithography techniques remain of limited utility for applications outside of the typical foci of integrated circuit manufacturing. In this communication, we have developed a novel stamping method that applies pressure on the upper surface of the stamp to regulate the dewetting process of the inorganic buffer and the evaporation rate of the solvent in this buffer between the substrate and the surface of the stamp. We focused on generating inorganic microstructures with specific locations and also on enabling the ability to pattern gradients during the crystallization of the inorganic salts. This approach utilized a combination of lithography with bottom-up growth and assembly of inorganic crystals. This work has potential applications in a variety of fields, including studying inorganic material patterning and small-scale fabrication technology.

Adaptive neuro fuzzy inference system-based power estimation method for CMOS VLSI circuits

NASA Astrophysics Data System (ADS)

Vellingiri, Govindaraj; Jayabalan, Ramesh

2018-03-01

Recent advancements in very large scale integration (VLSI) technologies have made it feasible to integrate millions of transistors on a single chip. This greatly increases the circuit complexity and hence there is a growing need for less-tedious and low-cost power estimation techniques. The proposed work employs Back-Propagation Neural Network (BPNN) and Adaptive Neuro Fuzzy Inference System (ANFIS), which are capable of estimating the power precisely for the complementary metal oxide semiconductor (CMOS) VLSI circuits, without requiring any knowledge on circuit structure and interconnections. The ANFIS to power estimation application is relatively new. Power estimation using ANFIS is carried out by creating initial FIS modes using hybrid optimisation and back-propagation (BP) techniques employing constant and linear methods. It is inferred that ANFIS with the hybrid optimisation technique employing the linear method produces better results in terms of testing error that varies from 0% to 0.86% when compared to BPNN as it takes the initial fuzzy model and tunes it by means of a hybrid technique combining gradient descent BP and mean least-squares optimisation algorithms. ANFIS is the best suited for power estimation application with a low RMSE of 0.0002075 and a high coefficient of determination (R) of 0.99961.

Optimization Methods for Spiking Neurons and Networks

PubMed Central

Russell, Alexander; Orchard, Garrick; Dong, Yi; Mihalaş, Ştefan; Niebur, Ernst; Tapson, Jonathan; Etienne-Cummings, Ralph

2011-01-01

Spiking neurons and spiking neural circuits are finding uses in a multitude of tasks such as robotic locomotion control, neuroprosthetics, visual sensory processing, and audition. The desired neural output is achieved through the use of complex neuron models, or by combining multiple simple neurons into a network. In either case, a means for configuring the neuron or neural circuit is required. Manual manipulation of parameters is both time consuming and non-intuitive due to the nonlinear relationship between parameters and the neuron’s output. The complexity rises even further as the neurons are networked and the systems often become mathematically intractable. In large circuits, the desired behavior and timing of action potential trains may be known but the timing of the individual action potentials is unknown and unimportant, whereas in single neuron systems the timing of individual action potentials is critical. In this paper, we automate the process of finding parameters. To configure a single neuron we derive a maximum likelihood method for configuring a neuron model, specifically the Mihalas–Niebur Neuron. Similarly, to configure neural circuits, we show how we use genetic algorithms (GAs) to configure parameters for a network of simple integrate and fire with adaptation neurons. The GA approach is demonstrated both in software simulation and hardware implementation on a reconfigurable custom very large scale integration chip. PMID:20959265

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

PubMed

Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

2012-07-01

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

Quantum cascade lasers grown on silicon.

PubMed

Nguyen-Van, Hoang; Baranov, Alexei N; Loghmari, Zeineb; Cerutti, Laurent; Rodriguez, Jean-Baptiste; Tournet, Julie; Narcy, Gregoire; Boissier, Guilhem; Patriarche, Gilles; Bahriz, Michael; Tournié, Eric; Teissier, Roland

2018-05-08

Technological platforms offering efficient integration of III-V semiconductor lasers with silicon electronics are eagerly awaited by industry. The availability of optoelectronic circuits combining III-V light sources with Si-based photonic and electronic components in a single chip will enable, in particular, the development of ultra-compact spectroscopic systems for mass scale applications. The first circuits of such type were fabricated using heterogeneous integration of semiconductor lasers by bonding the III-V chips onto silicon substrates. Direct epitaxial growth of interband III-V laser diodes on silicon substrates has also been reported, whereas intersubband emitters grown on Si have not yet been demonstrated. We report the first quantum cascade lasers (QCLs) directly grown on a silicon substrate. These InAs/AlSb QCLs grown on Si exhibit high performances, comparable with those of the devices fabricated on their native InAs substrate. The lasers emit near 11 µm, the longest emission wavelength of any laser integrated on Si. Given the wavelength range reachable with InAs/AlSb QCLs, these results open the way to the development of a wide variety of integrated sensors.

Power management circuits for self-powered systems based on micro-scale solar energy harvesting

NASA Astrophysics Data System (ADS)

Yoon, Eun-Jung; Yu, Chong-Gun

2016-03-01

In this paper, two types of power management circuits for self-powered systems based on micro-scale solar energy harvesting are proposed. First, if a solar cell outputs a very low voltage, less than 0.5 V, as in miniature solar cells or monolithic integrated solar cells, such that it cannot directly power the load, a voltage booster is employed to step up the solar cell's output voltage, and then a power management unit (PMU) delivers the boosted voltage to the load. Second, if the output voltage of a solar cell is enough to drive the load, the PMU directly supplies the load with solar energy. The proposed power management systems are designed and fabricated in a 0.18-μm complementary metal-oxide-semiconductor process, and their performances are compared and analysed through measurements.

Investigation of a Hybrid Wafer Scale Integration Technique that Mounts Discrete Integrated Circuit Die in a Silicon Substrate.

DTIC Science & Technology

1988-03-01

Polyimides as Planarizing and Insulative Coatings 2-21 III. Experimental Procedure, Equipment, and Materials 3-1 Wet Orientation Dependent Etching Study 3...1 Die Bond Adhesives Study .3-7 Fabrication of Samples for Electrical Testing 3-21 Evaluation of the Final Samples 3-45 IV. Experimental Results and...Discussion .. 4-1 We :ientation Dependent Etching Study Results 4-1 Die Attach Adhesives Study Results 4-21 Fabrication of Samples for Electrical

Effect of automated tube voltage selection, integrated circuit detector and advanced iterative reconstruction on radiation dose and image quality of 3rd generation dual-source aortic CT angiography: An intra-individual comparison.

PubMed

Mangold, Stefanie; De Cecco, Carlo N; Wichmann, Julian L; Canstein, Christian; Varga-Szemes, Akos; Caruso, Damiano; Fuller, Stephen R; Bamberg, Fabian; Nikolaou, Konstantin; Schoepf, U Joseph

2016-05-01

To compare, on an intra-individual basis, the effect of automated tube voltage selection (ATVS), integrated circuit detector and advanced iterative reconstruction on radiation dose and image quality of aortic CTA studies using 2nd and 3rd generation dual-source CT (DSCT). We retrospectively evaluated 32 patients who had undergone CTA of the entire aorta with both 2nd generation DSCT at 120kV using filtered back projection (FBP) (protocol 1) and 3rd generation DSCT using ATVS, an integrated circuit detector and advanced iterative reconstruction (protocol 2). Contrast-to-noise ratio (CNR) was calculated. Image quality was subjectively evaluated using a five-point scale. Radiation dose parameters were recorded. All studies were considered of diagnostic image quality. CNR was significantly higher with protocol 2 (15.0±5.2 vs 11.0±4.2; p<.0001). Subjective image quality analysis revealed no significant differences for evaluation of attenuation (p=0.08501) but image noise was rated significantly lower with protocol 2 (p=0.0005). Mean tube voltage and effective dose were 94.7±14.1kV and 6.7±3.9mSv with protocol 2; 120±0kV and 11.5±5.2mSv with protocol 1 (p<0.0001, respectively). Aortic CTA performed with 3rd generation DSCT, ATVS, integrated circuit detector, and advanced iterative reconstruction allow a substantial reduction of radiation exposure while improving image quality in comparison to 120kV imaging with FBP. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

Conjugate-Gradient Algorithms For Dynamics Of Manipulators

NASA Technical Reports Server (NTRS)

Fijany, Amir; Scheid, Robert E.

1993-01-01

Algorithms for serial and parallel computation of forward dynamics of multiple-link robotic manipulators by conjugate-gradient method developed. Parallel algorithms have potential for speedup of computations on multiple linked, specialized processors implemented in very-large-scale integrated circuits. Such processors used to stimulate dynamics, possibly faster than in real time, for purposes of planning and control.

Fast Neural Solution Of A Nonlinear Wave Equation

NASA Technical Reports Server (NTRS)

Barhen, Jacob; Toomarian, Nikzad

1996-01-01

Neural algorithm for simulation of class of nonlinear wave phenomena devised. Numerically solves special one-dimensional case of Korteweg-deVries equation. Intended to be executed rapidly by neural network implemented as charge-coupled-device/charge-injection device, very-large-scale integrated-circuit analog data processor of type described in "CCD/CID Processors Would Offer Greater Precision" (NPO-18972).

Molecular Electronic Shift Registers

NASA Technical Reports Server (NTRS)

Beratan, David N.; Onuchic, Jose N.

1990-01-01

Molecular-scale shift registers eventually constructed as parts of high-density integrated memory circuits. In principle, variety of organic molecules makes possible large number of different configurations and modes of operation for such shift-register devices. Several classes of devices and implementations in some specific types of molecules proposed. All based on transfer of electrons or holes along chains of repeating molecular units.

Piecewise Linear Approach for Timing Simulation of VLSI (Very-Large-Scale-Integrated) Circuits on Serial and Parallel Computers.

DTIC Science & Technology

1987-12-01

8217ftp.. *,*IS ~. ~bw ~ ft.. p ’ft ’ft ft.. ’ft *I~ P* ’ft ’p 0n-I ci via 1 ca j I .11’ ft~ ’ fttH vialca *- ’ft ft..I ft. ’ft ft.. --ft ..ft ’ft ftp

A Circuit Extraction System and Graphical Display for VLSI (Very Large Scale Integrated) Design.

DTIC Science & Technology

1989-12-01

understandable as a net-list. The file contains information on the different physical layers of a polysilicon chip, not how these layers combine to form...yperc; struct vwsurf vsurf =DEFAULT_VWSURF(pixwt-ndd); stt-uct vwsurf vsurf2 DEFAULT-VWSURF(pixwfLndd); ma in) another[ Ol =IV while (anothler[0O = ’y

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

PubMed Central

Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-01-01

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. PMID:28672813

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

NASA Astrophysics Data System (ADS)

Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.

2003-10-01

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Wafer-scale pixelated detector system

DOEpatents

Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

2017-10-17

A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Differential transimpedance amplifier circuit for correlated differential amplification

DOEpatents

Gresham, Christopher A [Albuquerque, NM; Denton, M Bonner [Tucson, AZ; Sperline, Roger P [Tucson, AZ

2008-07-22

A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

Integrating Magnetics for On-Chip Power: A Perspective

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sullivan, CR; Harburg, DV; Qiu, JZ

Integration of efficient power converters requires technology for efficient, high-power on-chip inductors and transformers. Increases in switching frequency, facilitated by advances in circuit designs and silicon or wide-bandgap semiconductors, can enable miniaturization, but only if the magnetics technology works well at the higher frequencies. Technologies, geometries, and scaling of air-core and magnetic-core inductors and transformers are examined, and their potential for integration is discussed. Air-core inductors can use simpler fabrication, and increasing frequency can always be used to decrease their size, but magnetic cores can decrease the required thickness without requiring as high a frequency.

CMOL: A New Concept for Nanoelectronics

NASA Astrophysics Data System (ADS)

Likharev, Konstantin

2005-03-01

I will review the recent work on devices and architectures for future hybrid semiconductor/molecular integrated circuits, in particular those of ``CMOL'' variety [1]. Such circuits would combine an advanced CMOS subsystem fabricated by the usual lithographic patterning, two layers of parallel metallic nanowires formed, e.g., by nanoimprint, and two-terminal molecular devices self-assembled on the nanowire crosspoints. Estimates show that this powerful combination may allow CMOL circuits to reach an unparalleled density (up to 10^12 functions per cm^2) and ultrahigh rate of information processing (up to 10^20 operations per second on a single chip), at acceptable power dissipation. The main challenges on the way toward practical CMOL technology are: (i) reliable chemically-directed self-assembly of mid-size organic molecules, and (ii) the development of efficient defect-tolerant architectures for CMOL circuits. Our recent work has shown that such architectures may be developed not only for terabit-scale memories and naturally defect-tolerant mixed-signal neuromorphic networks, but (rather unexpectedly) also for FPGA-style digital Boolean circuits. [1] For details, see http://rsfq1.physics.sunysb.edu/˜likharev/nano/Springer04.pdf

Synthetic analog computation in living cells.

PubMed

Daniel, Ramiz; Rubens, Jacob R; Sarpeshkar, Rahul; Lu, Timothy K

2013-05-30

A central goal of synthetic biology is to achieve multi-signal integration and processing in living cells for diagnostic, therapeutic and biotechnology applications. Digital logic has been used to build small-scale circuits, but other frameworks may be needed for efficient computation in the resource-limited environments of cells. Here we demonstrate that synthetic analog gene circuits can be engineered to execute sophisticated computational functions in living cells using just three transcription factors. Such synthetic analog gene circuits exploit feedback to implement logarithmically linear sensing, addition, ratiometric and power-law computations. The circuits exhibit Weber's law behaviour as in natural biological systems, operate over a wide dynamic range of up to four orders of magnitude and can be designed to have tunable transfer functions. Our circuits can be composed to implement higher-order functions that are well described by both intricate biochemical models and simple mathematical functions. By exploiting analog building-block functions that are already naturally present in cells, this approach efficiently implements arithmetic operations and complex functions in the logarithmic domain. Such circuits may lead to new applications for synthetic biology and biotechnology that require complex computations with limited parts, need wide-dynamic-range biosensing or would benefit from the fine control of gene expression.

A photonic circuit for complementary frequency shifting, in-phase quadrature/single sideband modulation and frequency multiplication: analysis and integration feasibility

NASA Astrophysics Data System (ADS)

Hasan, Mehedi; Hu, Jianqi; Nikkhah, Hamdam; Hall, Trevor

2017-08-01

A novel photonic integrated circuit architecture for implementing orthogonal frequency division multiplexing by means of photonic generation of phase-correlated sub-carriers is proposed. The circuit can also be used for implementing complex modulation, frequency up-conversion of the electrical signal to the optical domain and frequency multiplication. The principles of operation of the circuit are expounded using transmission matrices and the predictions of the analysis are verified by computer simulation using an industry-standard software tool. Non-ideal scenarios that may affect the correct function of the circuit are taken into consideration and quantified. The discussion of integration feasibility is illustrated by a photonic integrated circuit that has been fabricated using 'library' components and which features most of the elements of the proposed circuit architecture. The circuit is found to be practical and may be fabricated in any material platform that offers a linear electro-optic modulator such as organic or ferroelectric thin films hybridized with silicon photonics.

The circuit architecture of whole brains at the mesoscopic scale.

PubMed

Mitra, Partha P

2014-09-17

Vertebrate brains of even moderate size are composed of astronomically large numbers of neurons and show a great degree of individual variability at the microscopic scale. This variation is presumably the result of phenotypic plasticity and individual experience. At a larger scale, however, relatively stable species-typical spatial patterns are observed in neuronal architecture, e.g., the spatial distributions of somata and axonal projection patterns, probably the result of a genetically encoded developmental program. The mesoscopic scale of analysis of brain architecture is the transitional point between a microscopic scale where individual variation is prominent and the macroscopic level where a stable, species-typical neural architecture is observed. The empirical existence of this scale, implicit in neuroanatomical atlases, combined with advances in computational resources, makes studying the circuit architecture of entire brains a practical task. A methodology has previously been proposed that employs a shotgun-like grid-based approach to systematically cover entire brain volumes with injections of neuronal tracers. This methodology is being employed to obtain mesoscale circuit maps in mouse and should be applicable to other vertebrate taxa. The resulting large data sets raise issues of data representation, analysis, and interpretation, which must be resolved. Even for data representation the challenges are nontrivial: the conventional approach using regional connectivity matrices fails to capture the collateral branching patterns of projection neurons. Future success of this promising research enterprise depends on the integration of previous neuroanatomical knowledge, partly through the development of suitable computational tools that encapsulate such expertise. Copyright © 2014 Elsevier Inc. All rights reserved.

GaAs Optoelectronic Integrated-Circuit Neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

1992-01-01

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

NASA Space Engineering Research Center for VLSI systems design

NASA Technical Reports Server (NTRS)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Waferscale nanophotonic circuits made from diamond-on-insulator substrates.

PubMed

Rath, P; Gruhler, N; Khasminskaya, S; Nebel, C; Wild, C; Pernice, W H P

2013-05-06

Wide bandgap dielectrics are attractive materials for the fabrication of photonic devices because they allow broadband optical operation and do not suffer from free-carrier absorption. Here we show that polycrystalline diamond thin films deposited by chemical vapor deposition provide a promising platform for the realization of large scale integrated photonic circuits. We present a full suite of photonic components required for the investigation of on-chip devices, including input grating couplers, millimeter long nanophotonic waveguides and microcavities. In microring resonators we measure loaded optical quality factors up to 11,000. Corresponding propagation loss of 5 dB/mm is also confirmed by measuring transmission through long waveguides.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Selective Processing Techniques for Electronics and Opto-Electronic Applications: Quantum-Well Devices and Integrated Optic Circuits

DTIC Science & Technology

1993-02-10

new technology is to have sufficient control of processing to *- describable by an appropriate elecromagnetic model . build useful devices. For example...3. W aveguide Modulators .................................. 7 B. Integrated Optical Device and Circuit Modeling ... ................... .. 10 C...following categories: A. Integrated Optical Devices and Technology B. Integrated Optical Device and Circuit Modeling C. Cryogenic Etching for Low

Semicustom integrated circuits and the standard transistor array radix (STAR)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The development, application, pros and cons of the semicustom and custom approach to the integration of circuits are described. Improvements in terms of cost, reliability, secrecy, power, and size reduction are examined. Also presented is the standard transistor array radix, a semicustom approach to digital integrated circuits that offers the advantages of both custom and semicustom approaches to integration.

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

NASA Astrophysics Data System (ADS)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits

NASA Astrophysics Data System (ADS)

Patil, Ganesh C.; Bonge, Vijaysinh H.; Malode, Mayur M.; Jain, Rahul G.

2016-02-01

In this paper, δ-doped partially insulated junctionless transistor (δ-Pi-OXJLT) has been proposed which shows that, employing highly doped δ-region below the channel not only reduces the off-state leakage current (IOFF) and short channel effects (SCEs) but also reduce the requirements of scaling channel thickness of junctionless transistor (JLT). The comparative analysis of digital and analog circuit performance of proposed δ-Pi-OXJLT, bulk planar (BP) JLT and silicon-on-insulator (SOI) JLT has also been carried out. The digital parameters analyzed in this work are, on-state drive current (ION), IOFF, ION/IOFF ratio, static power dissipation (PSTAT) whereas the analog parameters analyzed includes, transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) of the devices. In addition, scaling behavior of the devices is studied for various channel lengths by using the parameters such as drain induced barrier lowering (DIBL) and sub-threshold swing (SS). It has been found that, the proposed δ-Pi-OXJLT shows significant reduction in IOFF, DIBL and SS over BPJLT and SOIJLT devices. Further, ION and ION/IOFF ratio in the case of proposed δ-Pi-OXJLT also improves over the BPJLT device. Furthermore, the improvement in analog figures of merit, GM, GM/IDS, GMRO and fT in the case of proposed δ-Pi-OXJLT clearly shows that the proposed δ-Pi-OXJLT is the promising device for mixed signal integrated circuits.

Subsurface microscopy of interconnect layers of an integrated circuit.

PubMed

Köklü, F Hakan; Unlü, M Selim

2010-01-15

We apply the NA-increasing lens technique to confocal and wide-field backside microscopy of integrated circuits. We demonstrate 325 nm (lambda(0)/4) lateral spatial resolution while imaging metal structures located inside the interconnect layer of an integrated circuit. Vectorial field calculations are presented justifying our findings.

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-01

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... No. 6,847,904 (``the '904 patent''). The complaint further alleges that an industry in the United...

77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-29

... INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and... Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is soliciting comments on... Commission's electronic docket (EDIS) at http://edis.usitc.gov , and will be available for inspection during...

77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-06

... INTERNATIONAL TRADE COMMISSION [Docket No. 2899] Certain Integrated Circuit Packages Provided With... complaint entitled Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and..., telephone (202) 205-2000. The public version of the complaint can be accessed on the Commission's electronic...

A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

PubMed

Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

2008-02-01

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

Label-Free Direct Electronic Detection of Biomolecules with Amorphous Silicon Nanostructures

PubMed Central

Lund, John; Mehta, Ranjana; Parviz, Babak A.

2007-01-01

We present the fabrication and characterization of a nano-scale sensor made of amorphous silicon for the label-free, electronic detection of three classes of biologically important molecules: ions, oligonucleotides, and proteins. The sensor structure has an active element which is a 50 nm wide amorphous silicon semicircle and has a total footprint of less than 4 μm2. We demonstrate the functionalization of the sensor with receptor molecules and the electronic detection of three targets: H+ ions, short single-stranded DNAs, and streptavidin. The sensor is able to reliably distinguish single base-pair mismatches in 12 base long strands of DNA and monitor the introduction and identification of straptavidin in real-time. The versatile sensor structure can be readily functionalized with a wide range of receptor molecules and is suitable for integration with high-speed electronic circuits as a post-process on an integrated circuit chip. PMID:17292148

Real-time fast physical random number generator with a photonic integrated circuit.

PubMed

Ugajin, Kazusa; Terashima, Yuta; Iwakawa, Kento; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki; Inubushi, Masanobu

2017-03-20

Random number generators are essential for applications in information security and numerical simulations. Most optical-chaos-based random number generators produce random bit sequences by offline post-processing with large optical components. We demonstrate a real-time hardware implementation of a fast physical random number generator with a photonic integrated circuit and a field programmable gate array (FPGA) electronic board. We generate 1-Tbit random bit sequences and evaluate their statistical randomness using NIST Special Publication 800-22 and TestU01. All of the BigCrush tests in TestU01 are passed using 410-Gbit random bit sequences. A maximum real-time generation rate of 21.1 Gb/s is achieved for random bit sequences in binary format stored in a computer, which can be directly used for applications involving secret keys in cryptography and random seeds in large-scale numerical simulations.

Engineering integrated photonics for heralded quantum gates

NASA Astrophysics Data System (ADS)

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-06-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

Moore's law and the impact on trusted and radiation-hardened microelectronics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ma, Kwok Kee

2011-12-01

In 1965 Gordon Moore wrote an article claiming that integrated circuit density would scale exponentially. His prediction has remained valid for more than four decades. Integrated circuits have changed all aspects of everyday life. They are also the 'heart and soul' of modern systems for defense, national infrastructure, and intelligence applications. The United States government needs an assured and trusted microelectronics supply for military systems. However, migration of microelectronics design and manufacturing from the United States to other countries in recent years has placed the supply of trusted microelectronics in jeopardy. Prevailing wisdom dictates that it is necessary to usemore » microelectronics fabricated in a state-of-the-art technology for highest performance and military system superiority. Close examination of silicon microelectronics technology evolution and Moore's Law reveals that this prevailing wisdom is not necessarily true. This presents the US government the possibility of a totally new approach to acquire trusted microelectronics.« less

The spatial structure of a nonlinear receptive field.

PubMed

Schwartz, Gregory W; Okawa, Haruhisa; Dunn, Felice A; Morgan, Josh L; Kerschensteiner, Daniel; Wong, Rachel O; Rieke, Fred

2012-11-01

Understanding a sensory system implies the ability to predict responses to a variety of inputs from a common model. In the retina, this includes predicting how the integration of signals across visual space shapes the outputs of retinal ganglion cells. Existing models of this process generalize poorly to predict responses to new stimuli. This failure arises in part from properties of the ganglion cell response that are not well captured by standard receptive-field mapping techniques: nonlinear spatial integration and fine-scale heterogeneities in spatial sampling. Here we characterize a ganglion cell's spatial receptive field using a mechanistic model based on measurements of the physiological properties and connectivity of only the primary excitatory circuitry of the retina. The resulting simplified circuit model successfully predicts ganglion-cell responses to a variety of spatial patterns and thus provides a direct correspondence between circuit connectivity and retinal output.

INTEGRATED CIRCUITS FROM MOBILE PHONES AS POSSIBLE EMERGENCY OSL/TL DOSIMETERS.

PubMed

Sholom, S; McKeever, S W S

2016-09-01

In this article, optically stimulated luminescence (OSL) data are presented from integrated circuits (ICs) extracted from mobile phones. The purpose is to evaluate the potential of using OSL from components in personal electronic devices such as smart phones as a means of emergency dosimetry in the event of a large-scale radiological incident. ICs were extracted from five different makes and models of mobile phone. Sample preparation procedures are described, and OSL from the IC samples following irradiation using a (90)Sr/(90)Y source is presented. Repeatability, sensitivity, dose responses, minimum measureable doses, stability and fading data were examined and are described. A protocol for measuring absorbed dose is presented, and it was concluded that OSL from these components is a viable method for assessing dose in the days following a radiological incident. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Engineering integrated photonics for heralded quantum gates

PubMed Central

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-01-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process. PMID:27282928

Engineering integrated photonics for heralded quantum gates.

PubMed

Meany, Thomas; Biggerstaff, Devon N; Broome, Matthew A; Fedrizzi, Alessandro; Delanty, Michael; Steel, M J; Gilchrist, Alexei; Marshall, Graham D; White, Andrew G; Withford, Michael J

2016-06-10

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

Fabrication of Circuit QED Quantum Processors, Part 2: Advanced Semiconductor Manufacturing Perspectives

NASA Astrophysics Data System (ADS)

Michalak, D. J.; Bruno, A.; Caudillo, R.; Elsherbini, A. A.; Falcon, J. A.; Nam, Y. S.; Poletto, S.; Roberts, J.; Thomas, N. K.; Yoscovits, Z. R.; Dicarlo, L.; Clarke, J. S.

Experimental quantum computing is rapidly approaching the integration of sufficient numbers of quantum bits for interesting applications, but many challenges still remain. These challenges include: realization of an extensible design for large array scale up, sufficient material process control, and discovery of integration schemes compatible with industrial 300 mm fabrication. We present recent developments in extensible circuits with vertical delivery. Toward the goal of developing a high-volume manufacturing process, we will present recent results on a new Josephson junction process that is compatible with current tooling. We will then present the improvements in NbTiN material uniformity that typical 300 mm fabrication tooling can provide. While initial results on few-qubit systems are encouraging, advanced processing control is expected to deliver the improvements in qubit uniformity, coherence time, and control required for larger systems. Research funded by Intel Corporation.

Monolithic microwave integrated circuit water vapor radiometer

NASA Technical Reports Server (NTRS)

Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

1991-01-01

A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

Compact earth stations, hubs for energy industry expanding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shimabukuro, T.

1992-02-01

That paper reports that advances in gallium arsenide (GaAs) technology, monolithic microwave integrated circuits (MMIC) and large scale integrated (VLSF) circuits, have contributed to the mass production of very reliable small aperture terminals (VSATs). Less publicized, but equally important to multinational energy organizations, are recent developments in compact earth station design and solid-state hubs for VSAT networks made possible by the new technology. Many applications are suited for the energy industry that involve compact earth station terminals and hubs. The first group of applications describes the use of GTE's ACES earth station for the Zaire Gulf Oil Co. in Zairemore » and for AMOCO in Trinidad. The second group of applications describes the compact hub for VSAT networks, which could potentially have a number of data communication uses in the energy industry, such as, IBM/SNA, X.25, or supervisory control an data acquisition (SCADA) applications.« less

Method for producing a hybridization of detector array and integrated circuit for readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

1993-01-01

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Energy-efficient neuron, synapse and STDP integrated circuits.

PubMed

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

Miniaturized ultrasound imaging probes enabled by CMUT arrays with integrated frontend electronic circuits.

PubMed

Khuri-Yakub, B T; Oralkan, Omer; Nikoozadeh, Amin; Wygant, Ira O; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O'Donnell, Matthew; Truong, Uyen; Sahn, David J

2010-01-01

Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics.

Robustness, evolvability, and the logic of genetic regulation.

PubMed

Payne, Joshua L; Moore, Jason H; Wagner, Andreas

2014-01-01

In gene regulatory circuits, the expression of individual genes is commonly modulated by a set of regulating gene products, which bind to a gene's cis-regulatory region. This region encodes an input-output function, referred to as signal-integration logic, that maps a specific combination of regulatory signals (inputs) to a particular expression state (output) of a gene. The space of all possible signal-integration functions is vast and the mapping from input to output is many-to-one: For the same set of inputs, many functions (genotypes) yield the same expression output (phenotype). Here, we exhaustively enumerate the set of signal-integration functions that yield identical gene expression patterns within a computational model of gene regulatory circuits. Our goal is to characterize the relationship between robustness and evolvability in the signal-integration space of regulatory circuits, and to understand how these properties vary between the genotypic and phenotypic scales. Among other results, we find that the distributions of genotypic robustness are skewed, so that the majority of signal-integration functions are robust to perturbation. We show that the connected set of genotypes that make up a given phenotype are constrained to specific regions of the space of all possible signal-integration functions, but that as the distance between genotypes increases, so does their capacity for unique innovations. In addition, we find that robust phenotypes are (i) evolvable, (ii) easily identified by random mutation, and (iii) mutationally biased toward other robust phenotypes. We explore the implications of these latter observations for mutation-based evolution by conducting random walks between randomly chosen source and target phenotypes. We demonstrate that the time required to identify the target phenotype is independent of the properties of the source phenotype.

Robustness, Evolvability, and the Logic of Genetic Regulation

PubMed Central

Moore, Jason H.; Wagner, Andreas

2014-01-01

In gene regulatory circuits, the expression of individual genes is commonly modulated by a set of regulating gene products, which bind to a gene’s cis-regulatory region. This region encodes an input-output function, referred to as signal-integration logic, that maps a specific combination of regulatory signals (inputs) to a particular expression state (output) of a gene. The space of all possible signal-integration functions is vast and the mapping from input to output is many-to-one: for the same set of inputs, many functions (genotypes) yield the same expression output (phenotype). Here, we exhaustively enumerate the set of signal-integration functions that yield idential gene expression patterns within a computational model of gene regulatory circuits. Our goal is to characterize the relationship between robustness and evolvability in the signal-integration space of regulatory circuits, and to understand how these properties vary between the genotypic and phenotypic scales. Among other results, we find that the distributions of genotypic robustness are skewed, such that the majority of signal-integration functions are robust to perturbation. We show that the connected set of genotypes that make up a given phenotype are constrained to specific regions of the space of all possible signal-integration functions, but that as the distance between genotypes increases, so does their capacity for unique innovations. In addition, we find that robust phenotypes are (i) evolvable, (ii) easily identified by random mutation, and (iii) mutationally biased toward other robust phenotypes. We explore the implications of these latter observations for mutation-based evolution by conducting random walks between randomly chosen source and target phenotypes. We demonstrate that the time required to identify the target phenotype is independent of the properties of the source phenotype. PMID:23373974

The 1991 3rd NASA Symposium on VLSI Design

NASA Technical Reports Server (NTRS)

Maki, Gary K.

1991-01-01

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

ERIC Educational Resources Information Center

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Lue, Jaw-Chyng

2009-01-01

A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

Silicon Compilation: A Solution to the Complexity of VLSI (Very Large-Scale Integrated) Circuit Design.

DTIC Science & Technology

1985-09-01

Design Language Xi." International Conference on Computer Design, pp. 652-655. 1983. [GAJ 84] D. D. Gajski and J. J. Bozek. "ARSENIC: Methodology and...Report R-1015 UIUL-ENG 84-2209. August 1984. [LUR 84] C. Lursinsap and D. Gajski , "Cell Compilation with Constraints." Proceedings of the 21st Design

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kishimoto, S., E-mail: syunji.kishimoto@kek.jp; Haruki, R.; Mitsui, T.

We developed a silicon avalanche photodiode (Si-APD) linear-array detector for use in nuclear resonant scattering experiments using synchrotron X-rays. The Si-APD linear array consists of 64 pixels (pixel size: 100 × 200 μm{sup 2}) with a pixel pitch of 150 μm and depletion depth of 10 μm. An ultrafast frontend circuit allows the X-ray detector to obtain a high output rate of >10{sup 7} cps per pixel. High-performance integrated circuits achieve multichannel scaling over 1024 continuous time bins with a 1 ns resolution for each pixel without dead time. The multichannel scaling method enabled us to record a time spectrummore » of the 14.4 keV nuclear radiation at each pixel with a time resolution of 1.4 ns (FWHM). This method was successfully applied to nuclear forward scattering and nuclear small-angle scattering on {sup 57}Fe.« less

75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-02-04

... Semiconductor Integrated Circuits and Products Containing Same; Notice of Commission Determination To Review in... importation of certain semiconductor integrated circuits and products containing same by reason of... that there exists a domestic industry with respect to each of the asserted patents. The complaint named...

Multichannel, Active Low-Pass Filters

NASA Technical Reports Server (NTRS)

Lev, James J.

1989-01-01

Multichannel integrated circuits cascaded to obtain matched characteristics. Gain and phase characteristics of channels of multichannel, multistage, active, low-pass filter matched by making filter of cascaded multichannel integrated-circuit operational amplifiers. Concept takes advantage of inherent equality of electrical characteristics of nominally-identical circuit elements made on same integrated-circuit chip. Characteristics of channels vary identically with changes in temperature. If additional matched channels needed, chips containing more than two operational amplifiers apiece (e.g., commercial quad operational amplifliers) used. Concept applicable to variety of equipment requiring matched gain and phase in multiple channels - radar, test instruments, communication circuits, and equipment for electronic countermeasures.

Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

NASA Astrophysics Data System (ADS)

Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

2014-12-01

A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

Reusable vibration resistant integrated circuit mounting socket

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evans, C.N.

1993-12-31

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuitmore » lead can be removed from the socket without damage either to the lead or to the socket components.« less

Reusable vibration resistant integrated circuit mounting socket

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evans, C.N.

1995-08-29

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuitmore » lead can be removed from the socket without damage either to the lead or to the socket components. 11 figs.« less

A Differential Monolithically Integrated Inductive Linear Displacement Measurement Microsystem

PubMed Central

Podhraški, Matija; Trontelj, Janez

2016-01-01

An inductive linear displacement measurement microsystem realized as a monolithic Application-Specific Integrated Circuit (ASIC) is presented. The system comprises integrated microtransformers as sensing elements, and analog front-end electronics for signal processing and demodulation, both jointly fabricated in a conventional commercially available four-metal 350-nm CMOS process. The key novelty of the presented system is its full integration, straightforward fabrication, and ease of application, requiring no external light or magnetic field source. Such systems therefore have the possibility of substituting certain conventional position encoder types. The microtransformers are excited by an AC signal in MHz range. The displacement information is modulated into the AC signal by a metal grating scale placed over the microsystem, employing a differential measurement principle. Homodyne mixing is used for the demodulation of the scale displacement information, returned by the ASIC as a DC signal in two quadrature channels allowing the determination of linear position of the target scale. The microsystem design, simulations, and characterization are presented. Various system operating conditions such as frequency, phase, target scale material and distance have been experimentally evaluated. The best results have been achieved at 4 MHz, demonstrating a linear resolution of 20 µm with steel and copper scale, having respective sensitivities of 0.71 V/mm and 0.99 V/mm. PMID:26999146

A Differential Monolithically Integrated Inductive Linear Displacement Measurement Microsystem.

PubMed

Podhraški, Matija; Trontelj, Janez

2016-03-17

An inductive linear displacement measurement microsystem realized as a monolithic Application-Specific Integrated Circuit (ASIC) is presented. The system comprises integrated microtransformers as sensing elements, and analog front-end electronics for signal processing and demodulation, both jointly fabricated in a conventional commercially available four-metal 350-nm CMOS process. The key novelty of the presented system is its full integration, straightforward fabrication, and ease of application, requiring no external light or magnetic field source. Such systems therefore have the possibility of substituting certain conventional position encoder types. The microtransformers are excited by an AC signal in MHz range. The displacement information is modulated into the AC signal by a metal grating scale placed over the microsystem, employing a differential measurement principle. Homodyne mixing is used for the demodulation of the scale displacement information, returned by the ASIC as a DC signal in two quadrature channels allowing the determination of linear position of the target scale. The microsystem design, simulations, and characterization are presented. Various system operating conditions such as frequency, phase, target scale material and distance have been experimentally evaluated. The best results have been achieved at 4 MHz, demonstrating a linear resolution of 20 µm with steel and copper scale, having respective sensitivities of 0.71 V/mm and 0.99 V/mm.

Integrated plasticity at inhibitory and excitatory synapses in the cerebellar circuit.

PubMed

Mapelli, Lisa; Pagani, Martina; Garrido, Jesus A; D'Angelo, Egidio

2015-01-01

The way long-term potentiation (LTP) and depression (LTD) are integrated within the different synapses of brain neuronal circuits is poorly understood. In order to progress beyond the identification of specific molecular mechanisms, a system in which multiple forms of plasticity can be correlated with large-scale neural processing is required. In this paper we take as an example the cerebellar network, in which extensive investigations have revealed LTP and LTD at several excitatory and inhibitory synapses. Cerebellar LTP and LTD occur in all three main cerebellar subcircuits (granular layer, molecular layer, deep cerebellar nuclei) and correspondingly regulate the function of their three main neurons: granule cells (GrCs), Purkinje cells (PCs) and deep cerebellar nuclear (DCN) cells. All these neurons, in addition to be excited, are reached by feed-forward and feed-back inhibitory connections, in which LTP and LTD may either operate synergistically or homeostatically in order to control information flow through the circuit. Although the investigation of individual synaptic plasticities in vitro is essential to prove their existence and mechanisms, it is insufficient to generate a coherent view of their impact on network functioning in vivo. Recent computational models and cell-specific genetic mutations in mice are shedding light on how plasticity at multiple excitatory and inhibitory synapses might regulate neuronal activities in the cerebellar circuit and contribute to learning and memory and behavioral control.

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

PubMed

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Design, Fabrication, and Characterization of Carbon Nanotube Field Emission Devices for Advanced Applications

NASA Astrophysics Data System (ADS)

Radauscher, Erich Justin

Carbon nanotubes (CNTs) have recently emerged as promising candidates for electron field emission (FE) cathodes in integrated FE devices. These nanostructured carbon materials possess exceptional properties and their synthesis can be thoroughly controlled. Their integration into advanced electronic devices, including not only FE cathodes, but sensors, energy storage devices, and circuit components, has seen rapid growth in recent years. The results of the studies presented here demonstrate that the CNT field emitter is an excellent candidate for next generation vacuum microelectronics and related electron emission devices in several advanced applications. The work presented in this study addresses determining factors that currently confine the performance and application of CNT-FE devices. Characterization studies and improvements to the FE properties of CNTs, along with Micro-Electro-Mechanical Systems (MEMS) design and fabrication, were utilized in achieving these goals. Important performance limiting parameters, including emitter lifetime and failure from poor substrate adhesion, are examined. The compatibility and integration of CNT emitters with the governing MEMS substrate (i.e., polycrystalline silicon), and its impact on these performance limiting parameters, are reported. CNT growth mechanisms and kinetics were investigated and compared to silicon (100) to improve the design of CNT emitter integrated MEMS based electronic devices, specifically in vacuum microelectronic device (VMD) applications. Improved growth allowed for design and development of novel cold-cathode FE devices utilizing CNT field emitters. A chemical ionization (CI) source based on a CNT-FE electron source was developed and evaluated in a commercial desktop mass spectrometer for explosives trace detection. This work demonstrated the first reported use of a CNT-based ion source capable of collecting CI mass spectra. The CNT-FE source demonstrated low power requirements, pulsing capabilities, and average lifetimes of over 320 hours when operated in constant emission mode under elevated pressures, without sacrificing performance. Additionally, a novel packaged ion source for miniature mass spectrometer applications using CNT emitters, a MEMS based Nier-type geometry, and a Low Temperature Cofired Ceramic (LTCC) 3D scaffold with integrated ion optics were developed and characterized. While previous research has shown other devices capable of collecting ion currents on chip, this LTCC packaged MEMS micro-ion source demonstrated improvements in energy and angular dispersion as well as the ability to direct the ions out of the packaged source and towards a mass analyzer. Simulations and experimental design, fabrication, and characterization were used to make these improvements. Finally, novel CNT-FE devices were developed to investigate their potential to perform as active circuit elements in VMD circuits. Difficulty integrating devices at micron-scales has hindered the use of vacuum electronic devices in integrated circuits, despite the unique advantages they offer in select applications. Using a combination of particle trajectory simulation and experimental characterization, device performance in an integrated platform was investigated. Solutions to the difficulties in operating multiple devices in close proximity and enhancing electron transmission (i.e., reducing grid loss) are explored in detail. A systematic and iterative process was used to develop isolation structures that reduced crosstalk between neighboring devices from 15% on average, to nearly zero. Innovative geometries and a new operational mode reduced grid loss by nearly threefold, thereby improving transmission of the emitted cathode current to the anode from 25% in initial designs to 70% on average. These performance enhancements are important enablers for larger scale integration and for the realization of complex vacuum microelectronic circuits.

Photonic content-addressable memory system that uses a parallel-readout optical disk

NASA Astrophysics Data System (ADS)

Krishnamoorthy, Ashok V.; Marchand, Philippe J.; Yayla, Gökçe; Esener, Sadik C.

1995-11-01

We describe a high-performance associative-memory system that can be implemented by means of an optical disk modified for parallel readout and a custom-designed silicon integrated circuit with parallel optical input. The system can achieve associative recall on 128 \\times 128 bit images and also on variable-size subimages. The system's behavior and performance are evaluated on the basis of experimental results on a motionless-head parallel-readout optical-disk system, logic simulations of the very-large-scale integrated chip, and a software emulation of the overall system.

Subwavelength hybrid terahertz waveguides.

PubMed

Nam, Sung Hyun; Taylor, Antoinette J; Efimov, Anatoly

2009-12-07

We introduce and present general properties of hybrid terahertz waveguides. Weakly confined Zenneck waves on a metal-dielectric interface at terahertz frequencies can be transformed to a strongly confined yet low-loss subwavelength mode through coupling with a photonic mode of a nearby high-index dielectric strip. We analyze confinement, attenuation, and dispersion properties of this mode. The proposed design is suitable for planar integration and allows easy fabrication on chip scale. The superior waveguiding properties at terahertz frequencies could enable the hybrid terahertz waveguides as building blocks for terahertz integrated circuits.

Merging parallel optics packaging and surface mount technologies

NASA Astrophysics Data System (ADS)

Kopp, Christophe; Volpert, Marion; Routin, Julien; Bernabé, Stéphane; Rossat, Cyrille; Tournaire, Myriam; Hamelin, Régis

2008-02-01

Optical links are well known to present significant advantages over electrical links for very high-speed data rate at 10Gpbs and above per channel. However, the transition towards optical interconnects solutions for short and very short reach applications requires the development of innovative packaging solutions that would deal with very high volume production capability and very low cost per unit. Moreover, the optoelectronic transceiver components must be able to move from the edge to anywhere on the printed circuit board, for instance close to integrated circuits with high speed IO. In this paper, we present an original packaging design to manufacture parallel optic transceivers that are surface mount devices. The package combines highly integrated Multi-Chip-Module on glass and usual IC ceramics packaging. The use of ceramic and the development of sealing technologies achieve hermetic requirements. Moreover, thanks to a chip scale package approach the final device exhibits a much minimized footprint. One of the main advantages of the package is its flexibility to be soldered or plugged anywhere on the printed circuit board as any other electronic device. As a demonstrator we present a 2 by 4 10Gbps transceiver operating at 850nm.

Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

PubMed Central

Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

2010-01-01

Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

Frequency Control of Single Quantum Emitters in Integrated Photonic Circuits

NASA Astrophysics Data System (ADS)

Schmidgall, Emma R.; Chakravarthi, Srivatsa; Gould, Michael; Christen, Ian R.; Hestroffer, Karine; Hatami, Fariba; Fu, Kai-Mei C.

2018-02-01

Generating entangled graph states of qubits requires high entanglement rates, with efficient detection of multiple indistinguishable photons from separate qubits. Integrating defect-based qubits into photonic devices results in an enhanced photon collection efficiency, however, typically at the cost of a reduced defect emission energy homogeneity. Here, we demonstrate that the reduction in defect homogeneity in an integrated device can be partially offset by electric field tuning. Using photonic device-coupled implanted nitrogen vacancy (NV) centers in a GaP-on-diamond platform, we demonstrate large field-dependent tuning ranges and partial stabilization of defect emission energies. These results address some of the challenges of chip-scale entanglement generation.

Frequency Control of Single Quantum Emitters in Integrated Photonic Circuits.

PubMed

Schmidgall, Emma R; Chakravarthi, Srivatsa; Gould, Michael; Christen, Ian R; Hestroffer, Karine; Hatami, Fariba; Fu, Kai-Mei C

2018-02-14

Generating entangled graph states of qubits requires high entanglement rates with efficient detection of multiple indistinguishable photons from separate qubits. Integrating defect-based qubits into photonic devices results in an enhanced photon collection efficiency, however, typically at the cost of a reduced defect emission energy homogeneity. Here, we demonstrate that the reduction in defect homogeneity in an integrated device can be partially offset by electric field tuning. Using photonic device-coupled implanted nitrogen vacancy (NV) centers in a GaP-on-diamond platform, we demonstrate large field-dependent tuning ranges and partial stabilization of defect emission energies. These results address some of the challenges of chip-scale entanglement generation.

A chip-scale integrated cavity-electro-optomechanics platform.

PubMed

Winger, M; Blasius, T D; Mayer Alegre, T P; Safavi-Naeini, A H; Meenehan, S; Cohen, J; Stobbe, S; Painter, O

2011-12-05

We present an integrated optomechanical and electromechanical nanocavity, in which a common mechanical degree of freedom is coupled to an ultrahigh-Q photonic crystal defect cavity and an electrical circuit. The system allows for wide-range, fast electrical tuning of the optical nanocavity resonances, and for electrical control of optical radiation pressure back-action effects such as mechanical amplification (phonon lasing), cooling, and stiffening. These sort of integrated devices offer a new means to efficiently interconvert weak microwave and optical signals, and are expected to pave the way for a new class of micro-sensors utilizing optomechanical back-action for thermal noise reduction and low-noise optical read-out.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Coupling control based on Adiabatic elimination for densely integrated nano-photonics

NASA Astrophysics Data System (ADS)

Mrejen, Michael; Suchowski, Haim; Hatakeyama, Taiki; Wu, Chihhui; Feng, Liang; O'Brien, Kevin; Wang, Yuan; Zhang, Xiang

2015-03-01

The ever growing need for energy-efficient and fast communications is driving the development of highly integrated photonic circuits where controlling light at the nanoscale becomes the most critical aspect of information transfer. Here we develop a unique scheme of adiabatic elimination (AE) modulation to actively control the coupling among waveguides for densely integrated photonics. Analogous to atomic systems, AE is achieved by applying a decomposition on a three waveguide coupler, where the two outer waveguides serve as an effective two-mode system with an effective coupling of Veff = [(V*13 + V*23V*12/Δβ12) (V13-V23V12/Δβ23) ]1/2,and the middle waveguide is the equivalent to the intermediate level `dark state'. We experimentally demonstrate the first all optical AE modulation and its ability to control the coupling between the two waveguides by manipulating the mode index of the decoupled middle one. In addition, we show that the strong modes interactions allowed at the nano-scale offer a unique configuration of zero-coupling between all the waveguides, a phenomena that paves the way for ultra-high density photonic integrated circuits where small footprint is of crucial importance.

Flexible integration of free-standing nanowires into silicon photonics.

PubMed

Chen, Bigeng; Wu, Hao; Xin, Chenguang; Dai, Daoxin; Tong, Limin

2017-06-14

Silicon photonics has been developed successfully with a top-down fabrication technique to enable large-scale photonic integrated circuits with high reproducibility, but is limited intrinsically by the material capability for active or nonlinear applications. On the other hand, free-standing nanowires synthesized via a bottom-up growth present great material diversity and structural uniformity, but precisely assembling free-standing nanowires for on-demand photonic functionality remains a great challenge. Here we report hybrid integration of free-standing nanowires into silicon photonics with high flexibility by coupling free-standing nanowires onto target silicon waveguides that are simultaneously used for precise positioning. Coupling efficiency between a free-standing nanowire and a silicon waveguide is up to ~97% in the telecommunication band. A hybrid nonlinear-free-standing nanowires-silicon waveguides Mach-Zehnder interferometer and a racetrack resonator for significantly enhanced optical modulation are experimentally demonstrated, as well as hybrid active-free-standing nanowires-silicon waveguides circuits for light generation. These results suggest an alternative approach to flexible multifunctional on-chip nanophotonic devices.Precisely assembling free-standing nanowires for on-demand photonic functionality remains a challenge. Here, Chen et al. integrate free-standing nanowires into silicon waveguides and show all-optical modulation and light generation on silicon photonic chips.

LEC GaAs for integrated circuit applications

NASA Technical Reports Server (NTRS)

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

NASA Technical Reports Server (NTRS)

Johnston, Allan H.; Rax, Bernard G.

2006-01-01

This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

Modeling selective attention using a neuromorphic analog VLSI device.

PubMed

Indiveri, G

2000-12-01

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

Ka-band to L-band frequency down-conversion based on III-V-on-silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Van Gasse, K.; Wang, Z.; Uvin, S.; De Deckere, B.; Mariën, J.; Thomassen, L.; Roelkens, G.

2017-12-01

In this work, we present the design, simulation and characterization of a frequency down-converter based on III-V-on-silicon photonic integrated circuit technology. We first demonstrate the concept using commercial discrete components, after which we demonstrate frequency conversion using an integrated mode-locked laser and integrated modulator. In our experiments, five channels in the Ka-band (27.5-30 GHz) with 500 MHz bandwidth are down-converted to the L-band (1.5 GHz). The breadboard demonstration shows a conversion efficiency of - 20 dB and a flat response over the 500 MHz bandwidth. The simulation of a fully integrated circuit indicates that a positive conversion gain can be obtained on a millimeter-sized photonic integrated circuit.

Microwave GaAs Integrated Circuits On Quartz Substrates

NASA Technical Reports Server (NTRS)

Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

1994-01-01

Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

Superradiance of cold atoms coupled to a superconducting circuit

NASA Astrophysics Data System (ADS)

Braun, Daniel; Hoffman, Jonathan; Tiesinga, Eite

2011-06-01

We investigate superradiance of an ensemble of atoms coupled to an integrated superconducting LC circuit. Particular attention is paid to the effect of inhomogeneous coupling constants. Combining perturbation theory in the inhomogeneity and numerical simulations, we show that inhomogeneous coupling constants can significantly affect the superradiant relaxation process. Incomplete relaxation terminating in “dark states” can occur, from which the only escape is through individual spontaneous emission on a much longer time scale. The relaxation dynamics can be significantly accelerated or retarded, depending on the distribution of the coupling constants. On the technical side, we also generalize the previously known propagator of superradiance for identical couplings in the completely symmetric sector to the full exponentially large Hilbert space.

Prototype Focal-Plane-Array Optoelectronic Image Processor

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Shaw, Timothy; Yu, Jeffrey

1995-01-01

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

A simple device for long-term radar cross section recordings.

PubMed

Eskelinen, Pekka; Ruoskanen, Jukka; Peltonen, Jouni

2009-05-01

A sample and hold circuit with settable delay can be used for recording of radar echo amplitude variations having time scales up to 100 s at the selected range bin in systems utilizing short rf pulses. The design is based on two integrated circuits and gives 1% uncertainty for 70 ns pulses. The key benefit is a real-time display of lengthy amplitude variations because the sample rate is defined by the radar pulse repetition frequency. Additionally we get a reduction in file size at least by the inverse of the radar's duty cycle. Examples of 10 and 100 s recordings with a Ka-band short pulse radar are described.

An analog silicon retina with multichip configuration.

PubMed

Kameda, Seiji; Yagi, Tetsuya

2006-01-01

The neuromorphic silicon retina is a novel analog very large scale integrated circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina, in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study [1]. The applications of this silicon retina, however, are limited because of a low spatial resolution and computational variability. In this paper, we have fabricated a multichip silicon retina in which the functional network circuits are divided into two chips: the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the P chip are transferred to the H chip with analog voltages through the line-parallel transfer bus. The sample/hold circuits embedded in the P and H chips compensate for the pattern noise generated on the circuits, including the analog communication pathway. Using the multichip silicon retina together with an off-chip differential amplifier, spatial filtering of the image with an odd- and an even-symmetric orientation selective receptive fields was carried out in real time. The analog data transfer method in the present multichip silicon retina is useful to design analog neuromorphic multichip systems that mimic the hierarchical structure of neuronal networks in the visual system.

Computer Simulation of Microwave Devices

NASA Technical Reports Server (NTRS)

Kory, Carol L.

1997-01-01

The accurate simulation of cold-test results including dispersion, on-axis beam interaction impedance, and attenuation of a helix traveling-wave tube (TWT) slow-wave circuit using the three-dimensional code MAFIA (Maxwell's Equations Solved by the Finite Integration Algorithm) was demonstrated for the first time. Obtaining these results is a critical step in the design of TWT's. A well-established procedure to acquire these parameters is to actually build and test a model or a scale model of the circuit. However, this procedure is time-consuming and expensive, and it limits freedom to examine new variations to the basic circuit. These limitations make the need for computational methods crucial since they can lower costs, reduce tube development time, and lessen limitations on novel designs. Computer simulation has been used to accurately obtain cold-test parameters for several slow-wave circuits. Although the helix slow-wave circuit remains the mainstay of the TWT industry because of its exceptionally wide bandwidth, until recently it has been impossible to accurately analyze a helical TWT using its exact dimensions because of the complexity of its geometrical structure. A new computer modeling technique developed at the NASA Lewis Research Center overcomes these difficulties. The MAFIA three-dimensional mesh for a C-band helix slow-wave circuit is shown.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

PubMed

Reagor, James A; Holt, David W

2016-03-01

Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

Nonvolatile Array Of Synapses For Neural Network

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1993-01-01

Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.

Stacked Metal Silicide/Silicon Far-Infrared Detectors

NASA Technical Reports Server (NTRS)

Maserjian, Joseph

1988-01-01

Selective doping of silicon in proposed metal silicide/silicon Schottky-barrier infrared photodetector increases maximum detectable wavelength. Stacking layers to form multiple Schottky barriers increases quantum efficiency of detector. Detectors of new type enhance capabilities of far-infrared imaging arrays. Grows by molecular-beam epitaxy on silicon waferscontaining very-large-scale integrated circuits. Imaging arrays of detectors made in monolithic units with image-preprocessing circuitry.

Defining biotypes for depression and anxiety based on large-scale circuit dysfunction: A theoretical review of the evidence and future directions for clinical translation

PubMed Central

Williams, Leanne M

2016-01-01

Complex emotional, cognitive and self-reflective functions rely on the activation and connectivity of large-scale neural circuits. These circuits offer a relevant scale of focus for conceptualizing a taxonomy for depression and anxiety based on specific profiles (or biotypes) of neural circuit dysfunction. Here, the theoretical review first outlined the current consensus as to what constitutes the organization of large-scale circuits in the human brain identified using parcellation and meta-analysis. The focus is on neural circuits implicated in resting reflection (“default mode”), detection of “salience”, affective processing (“threat” and “reward”), “attention” and “cognitive control”. Next, the current evidence regarding which type of dysfunctions in these circuits characterize depression and anxiety disorders was reviewed, with an emphasis on published meta-analyses and reviews of circuit dysfunctions that have been identified in at least two well-powered case:control studies. Grounded in the review of these topics, a conceptual framework is proposed for considering neural circuit-defined “biotypes”. In this framework, biotypes are defined by profiles of extent of dysfunction on each large-scale circuit. The clinical implications of a biotype approach for guiding classification and treatment of depression and anxiety is considered. Future research directions will develop the validity and clinical utility of a neural circuit biotype model that spans diagnostic categories and helps to translate neuroscience into clinical practice in the real world. PMID:27653321

High performance genetic algorithm for VLSI circuit partitioning

NASA Astrophysics Data System (ADS)

Dinu, Simona

2016-12-01

Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

Technical Reliability Studies. EOS/ESD Technology Abstracts

DTIC Science & Technology

1982-01-01

RESISTANT BIPOLAR TRANSISTOR DESIGN AND ITS APPLICATIONS TO LINEAR INTEGRATED CIRCUITS 16145 MODULE ELECTROSTATIC DISCHARGE SIMULATOR 15786 SOME...T.M. 16476 STATIC DISCHARGE MODELING TECHNIQUES FOR EVALUATION OF INTEGRATED (FET) CIRCUIT DESTRUCTION 16145 MODULE ELECTAOSTATIC DISCHARGE SIMULATOR...PLASTIC LSI CIRCUITS PRklE, L.A., II 16145 MODULE ELECTROSTATIC DISCHARGE SIMULATOR PRICE, R.D. 13455 EVALUATION OF PLASTIC LSI CIRCUITS PSHAENICH, A

Silicon millimetre-wave integrated-circuit (SIMMWIC) SPST switch

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-10-01

The first silicon millimetre-wave integrated circuit (SIMMWIC) has been successfully fabricated. This circuit is a monolithic SPST switch with a 3 dB bandwidth of 20 percent and a minimum isolation of 21.6 dB across the band (centre frequency is 36.75 GHz). This monolithic circuit is a low-cost reproducible building block for all millimetre-wave control applications.

Multidimensional quantum entanglement with large-scale integrated optics.

PubMed

Wang, Jianwei; Paesani, Stefano; Ding, Yunhong; Santagati, Raffaele; Skrzypczyk, Paul; Salavrakos, Alexia; Tura, Jordi; Augusiak, Remigiusz; Mančinska, Laura; Bacco, Davide; Bonneau, Damien; Silverstone, Joshua W; Gong, Qihuang; Acín, Antonio; Rottwitt, Karsten; Oxenløwe, Leif K; O'Brien, Jeremy L; Laing, Anthony; Thompson, Mark G

2018-04-20

The ability to control multidimensional quantum systems is central to the development of advanced quantum technologies. We demonstrate a multidimensional integrated quantum photonic platform able to generate, control, and analyze high-dimensional entanglement. A programmable bipartite entangled system is realized with dimensions up to 15 × 15 on a large-scale silicon photonics quantum circuit. The device integrates more than 550 photonic components on a single chip, including 16 identical photon-pair sources. We verify the high precision, generality, and controllability of our multidimensional technology, and further exploit these abilities to demonstrate previously unexplored quantum applications, such as quantum randomness expansion and self-testing on multidimensional states. Our work provides an experimental platform for the development of multidimensional quantum technologies. Copyright © 2018 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

DTIC Science & Technology

2015-12-24

Signal to Noise Ratio SPICE Simulation Program with Integrated Circuit Emphasis TIFF Tagged Image File Format USC University of Southern California xvii...sources can create errors in digital circuits. These effects can be simulated using Simulation Program with Integrated Circuit Emphasis ( SPICE ) or...compute summary statistics. 4.1 Circuit Simulations Noisy analog circuits can be simulated in SPICE or Cadence SpectreTM software via noisy voltage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ryu, C.; Boshier, M. G.

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

Integrated testing system FiTest for diagnosis of PCBA

NASA Astrophysics Data System (ADS)

Bogdan, Arkadiusz; Lesniak, Adam

2016-12-01

This article presents the innovative integrated testing system FiTest for automatic, quick inspection of printed circuit board assemblies (PCBA) manufactured in Surface Mount Technology (SMT). Integration of Automatic Optical Inspection (AOI), In-Circuit Tests (ICT) and Functional Circuit Tests (FCT) resulted in universal hardware platform for testing variety of electronic circuits. The platform provides increased test coverage, decreased level of false calls and optimization of test duration. The platform is equipped with powerful algorithms performing tests in a stable and repetitive way and providing effective management of diagnosis.

International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

NASA Astrophysics Data System (ADS)

Ostrowsky, D. B.; Sriram, S.

Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

Analog integrated circuits design for processing physiological signals.

PubMed

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

Nanoelectronics: Opportunities for future space applications

NASA Technical Reports Server (NTRS)

Frazier, Gary

1995-01-01

Further improvements in the performance of integrated electronics will eventually halt due to practical fundamental limits on our ability to downsize transistors and interconnect wiring. Avoiding these limits requires a revolutionary approach to switching device technology and computing architecture. Nanoelectronics, the technology of exploiting physics on the nanometer scale for computation and communication, attempts to avoid conventional limits by developing new approaches to switching, circuitry, and system integration. This presentation overviews the basic principles that operate on the nanometer scale that can be assembled into practical devices and circuits. Quantum resonant tunneling (RT) is used as the center-piece of the overview since RT devices already operate at high temperature (120 degrees C) and can be scaled, in principle, to a few nanometers in semiconductors. Near- and long-term applications of GaAs and silicon quantum devices are suggested for signal and information processing, memory, optoelectronics, and radio frequency (RF) communication.

A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

The Effects of Space Radiation on Linear Integrated Circuit

NASA Technical Reports Server (NTRS)

Johnston, A.

2000-01-01

Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.

35 GHz integrated circuit rectifying antenna with 33 percent efficiency

NASA Technical Reports Server (NTRS)

Yoo, T.-W.; Chang, K.

1991-01-01

A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

Recent Progress in the Development of Printed Thin-Film Transistors and Circuits with High-Resolution Printing Technology.

PubMed

Fukuda, Kenjiro; Someya, Takao

2017-07-01

Printed electronics enable the fabrication of large-scale, low-cost electronic devices and systems, and thus offer significant possibilities in terms of developing new electronics/optics applications in various fields. Almost all electronic applications require information processing using logic circuits. Hence, realizing the high-speed operation of logic circuits is also important for printed devices. This report summarizes recent progress in the development of printed thin-film transistors (TFTs) and integrated circuits in terms of materials, printing technologies, and applications. The first part of this report gives an overview of the development of functional inks such as semiconductors, electrodes, and dielectrics. The second part discusses high-resolution printing technologies and strategies to enable high-resolution patterning. The main focus of this report is on obtaining printed electrodes with high-resolution patterning and the electrical performance of printed TFTs using such printed electrodes. In the final part, some applications of printed electronics are introduced to exemplify their potential. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

PubMed

Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

2015-06-01

Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

Material Targets for Scaling All-Spin Logic

NASA Astrophysics Data System (ADS)

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

2016-01-01

All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

VLSI technology for smaller, cheaper, faster return link systems

NASA Technical Reports Server (NTRS)

Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

1994-01-01

Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

Nanomagnet Logic: Architectures, design, and benchmarking

NASA Astrophysics Data System (ADS)

Kurtz, Steven J.

Nanomagnet Logic (NML) is an emerging technology being studied as a possible replacement or supplementary device for Complimentary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FET) by the year 2020. NML devices offer numerous potential advantages including: low energy operation, steady state non-volatility, radiation hardness and a clear path to fabrication and integration with CMOS. However, maintaining both low-energy operation and non-volatility while scaling from the device to the architectural level is non-trivial as (i) nearest neighbor interactions within NML circuits complicate the modeling of ensemble nanomagnet behavior and (ii) the energy intensive clock structures required for re-evaluation and NML's relatively high latency challenge its ability to offer system-level performance wins against other emerging nanotechnologies. Thus, further research efforts are required to model more complex circuits while also identifying circuit design techniques that balance low-energy operation with steady state non-volatility. In addition, further work is needed to design and model low-power on-chip clocks while simultaneously identifying application spaces where NML systems (including clock overhead) offer sufficient energy savings to merit their inclusion in future processors. This dissertation presents research advancing the understanding and modeling of NML at all levels including devices, circuits, and line clock structures while also benchmarking NML against both scaled CMOS and tunneling FETs (TFET) devices. This is accomplished through the development of design tools and methodologies for (i) quantifying both energy and stability in NML circuits and (ii) evaluating line-clocked NML system performance. The application of these newly developed tools improves the understanding of ideal design criteria (i.e., magnet size, clock wire geometry, etc.) for NML architectures. Finally, the system-level performance evaluation tool offers the ability to project what advancements are required for NML to realize performance improvements over scaled-CMOS hardware equivalents at the functional unit and/or application-level.

Genetic programs constructed from layered logic gates in single cells

PubMed Central

Moon, Tae Seok; Lou, Chunbo; Tamsir, Alvin; Stanton, Brynne C.; Voigt, Christopher A.

2014-01-01

Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics1. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits2–6, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits1,7. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator–chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells. PMID:23041931

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Developing Avionics Hardware and Software for Rocket Engine Testing

NASA Technical Reports Server (NTRS)

Aberg, Bryce Robert

2014-01-01

My summer was spent working as an intern at Kennedy Space Center in the Propulsion Avionics Branch of the NASA Engineering Directorate Avionics Division. The work that I was involved with was part of Rocket University's Project Neo, a small scale liquid rocket engine test bed. I began by learning about the layout of Neo in order to more fully understand what was required of me. I then developed software in LabView to gather and scale data from two flowmeters and integrated that code into the main control software. Next, I developed more LabView code to control an igniter circuit and integrated that into the main software, as well. Throughout the internship, I performed work that mechanics and technicians would do in order to maintain and assemble the engine.

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

PubMed Central

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed

2017-01-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz. PMID:28763043

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit.

PubMed

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed; Kanaya, Haruichi

2017-08-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for -4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

Micromachined integrated quantum circuit containing a superconducting qubit

NASA Astrophysics Data System (ADS)

Brecht, Teresa; Chu, Yiwen; Axline, Christopher; Pfaff, Wolfgang; Blumoff, Jacob; Chou, Kevin; Krayzman, Lev; Frunzio, Luigi; Schoelkopf, Robert

We demonstrate a functional multilayer microwave integrated quantum circuit (MMIQC). This novel hardware architecture combines the high coherence and isolation of three-dimensional structures with the advantages of integrated circuits made with lithographic techniques. We present fabrication and measurement of a two-cavity/one-qubit prototype, including a transmon coupled to a three-dimensional microwave cavity micromachined in a silicon wafer. It comprises a simple MMIQC with competitive lifetimes and the ability to perform circuit QED operations in the strong dispersive regime. Furthermore, the design and fabrication techniques that we have developed are extensible to more complex quantum information processing devices.

Power system with an integrated lubrication circuit

DOEpatents

Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

2009-11-10

A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

Very Large Scale Integrated Circuits for Military Systems.

DTIC Science & Technology

1981-01-01

ABBREVIATIONS A/D Analog-to-digital C AGC Automatic Gain Control A A/J Anti-jam ASP Advanced Signal Processor AU Arithmetic Units C.AD Computer-Aided...ESM) equipments (Ref. 23); in lieu of an adequate automatic proces- sing capability, the function is now performed manually (Ref. 24), which involves...a human operator, displays, etc., and a sacrifice in performance (acquisition speed, saturation signal density). Various automatic processing

VHSIC Electronics and the Cost of Air Force Avionics in the 1990s

DTIC Science & Technology

1990-11-01

circuit. LRM Line replaceable module. LRU Line replaceable unit. LSI Large-scale integration. LSTTL Tow-power Schottky Transitor -to-Transistor Logic...displays, communications/navigation/identification, electronic combat equipment, dispensers, and computers. These CERs, which statistically relate the...some of the reliability numbers, and adding the F-15 and F-16 to obtain the data sample shown in Table 6. Both suite costs and reliability statistics

QCDOC: A 10-teraflops scale computer for lattice QCD

NASA Astrophysics Data System (ADS)

Chen, D.; Christ, N. H.; Cristian, C.; Dong, Z.; Gara, A.; Garg, K.; Joo, B.; Kim, C.; Levkova, L.; Liao, X.; Mawhinney, R. D.; Ohta, S.; Wettig, T.

2001-03-01

The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from "QCD On a Chip".

Low loss fusion splicing of micron scale silica fibers.

PubMed

Pal, Parama; Knox, Wayne H

2008-07-21

Tapered micron-sized optical fibers may be important in the future for development of microscale integrated photonic devices. Complex photonic circuits require many devices and a robust technique for interconnection. We demonstrate splicing of four micron diameter step-index air-clad silica microfibers using a CO2 laser. We obtain splice losses lower than 0.3%. Compared with evanescent coupling of microfibers, our splices are more mechanically stable and efficient.

Low-power integrated-circuit driver for ferrite-memory word lines

NASA Technical Reports Server (NTRS)

Katz, S.

1970-01-01

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Aluminum heat sink enables power transistors to be mounted integrally with printed circuit board

NASA Technical Reports Server (NTRS)

Seaward, R. C.

1967-01-01

Power transistor is provided with an integral flat plate aluminum heat sink which mounts directly on a printed circuit board containing associated circuitry. Standoff spacers are used to attach the heat sink to the printed circuit board containing the remainder of the circuitry.

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-10-04

... Circuit Devices and Products Containing Same; Notice of Commission Determination Not To Review an Initial... public record for this investigation may be viewed on the Commission's electronic docket (EDIS) at http... certain semiconductor integrated circuit devices and products containing same by reason of infringement of...

Multi-lead heat sink

DOEpatents

Roose, L.D.

1984-07-03

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again. 4 figs.

Multi-lead heat sink

DOEpatents

Roose, Lars D.

1984-01-01

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again.

Multi-lead heat sink

DOEpatents

Roose, L.D.

1982-08-25

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-02-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design.

Test aspects of the JPL Viterbi decoder

NASA Technical Reports Server (NTRS)

Breuer, M. A.

1989-01-01

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Dimension scaling effects on the yield sensitivity of HEMT digital circuits

NASA Technical Reports Server (NTRS)

Sarker, Jogendra C.; Purviance, John E.

1992-01-01

In our previous works, using a graphical tool, yield factor histograms, we studied the yield sensitivity of High Electron Mobility Transistors (HEMT) and HEMT circuit performance with the variation of process parameters. This work studies the scaling effects of process parameters on yield sensitivity of HEMT digital circuits. The results from two HEMT circuits are presented.

Superior model for fault tolerance computation in designing nano-sized circuit systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, N. S. S., E-mail: narinderjit@petronas.com.my; Muthuvalu, M. S., E-mail: msmuthuvalu@gmail.com; Asirvadam, V. S., E-mail: vijanth-sagayan@petronas.com.my

2014-10-24

As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalizationmore » of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.« less

Tunable quantum interference in a 3D integrated circuit.

PubMed

Chaboyer, Zachary; Meany, Thomas; Helt, L G; Withford, Michael J; Steel, M J

2015-04-27

Integrated photonics promises solutions to questions of stability, complexity, and size in quantum optics. Advances in tunable and non-planar integrated platforms, such as laser-inscribed photonics, continue to bring the realisation of quantum advantages in computation and metrology ever closer, perhaps most easily seen in multi-path interferometry. Here we demonstrate control of two-photon interference in a chip-scale 3D multi-path interferometer, showing a reduced periodicity and enhanced visibility compared to single photon measurements. Observed non-classical visibilities are widely tunable, and explained well by theoretical predictions based on classical measurements. With these predictions we extract Fisher information approaching a theoretical maximum. Our results open a path to quantum enhanced phase measurements.

The Need for Optical Means as an Alternative for Electronic Computing

NASA Technical Reports Server (NTRS)

Adbeldayem, Hossin; Frazier, Donald; Witherow, William; Paley, Steve; Penn, Benjamin; Bank, Curtis; Whitaker, Ann F. (Technical Monitor)

2001-01-01

An increasing demand for faster computers is rapidly growing to encounter the fast growing rate of Internet, space communication, and robotic industry. Unfortunately, the Very Large Scale Integration technology is approaching its fundamental limits beyond which the device will be unreliable. Optical interconnections and optical integrated circuits are strongly believed to provide the way out of the extreme limitations imposed on the growth of speed and complexity of nowadays computations by conventional electronics. This paper demonstrates two ultra-fast, all-optical logic gates and a high-density storage medium, which are essential components in building the future optical computer.

From behavior to neural dynamics: An integrated theory of attention

PubMed Central

Buschman, Timothy J.; Kastner, Sabine

2015-01-01

The brain has a limited capacity and therefore needs mechanisms to selectively enhance the information most relevant to one’s current behavior. We refer to these mechanisms as ‘attention’. Attention acts by increasing the strength of selected neural representations and preferentially routing them through the brain’s large-scale network. This is a critical component of cognition and therefore has been a central topic in cognitive neuroscience. Here we review a diverse literature that has studied attention at the level of behavior, networks, circuits and neurons. We then integrate these disparate results into a unified theory of attention. PMID:26447577

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oler, Kiri J.; Miller, Carl H.

In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.

Preface: Special Topic on Frontiers in Molecular Scale Electronics

NASA Astrophysics Data System (ADS)

Evers, Ferdinand; Venkataraman, Latha

2017-03-01

The electronic, mechanical, and thermoelectric properties of molecular scale devices have fascinated scientists across several disciplines in natural sciences and engineering. The interest is partially technological, driven by the fast miniaturization of integrated circuits that now have reached characteristic features at the nanometer scale. Equally important, a very strong incentive also exists to elucidate the fundamental aspects of structure-function relations for nanoscale devices, which utilize molecular building blocks as functional units. Thus motivated, a rich research field has established itself, broadly termed "Molecular Electronics," that hosts a plethora of activities devoted to this goal in chemistry, physics, and electrical engineering. This Special Topic on Frontiers of Molecular Scale Electronics captures recent theoretical and experimental advances in the field.

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Process design kit and circuits at a 2 µm technology node for flexible wearable electronics applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Torres-Miranda, Miguel; Petritz, Andreas; Gold, Herbert; Stadlober, Barbara

2016-09-01

In this work we present our most advanced technology node of organic thin film transistors (OTFTs) manufactured with a channel length as short as 2 μm by contact photolithography and a self-alignment process directly on a plastic substrate. Our process design kit (PDK) is described with P-type transistors, capacitors and 3 metal layers for connections of complex circuits. The OTFTs are composed of a double dielectric layer with a photopatternable ultra thin polymer (PNDPE) and alumina, with a thickness on the order of 100 nm. The organic semiconductor is either Pentacene or DNTT, which have a stable average mobility up to 0.1 cm2/Vs. Finally, a polymer (e.g.: Parylene-C) is used as a passivation layer. We describe also our design rules for the placement of standard circuit cells. A "plastic wafer" is fabricated containing 49 dies. Each die of 1 cm2 has between 25 to 50 devices, proving larger scale integration in such a small space, unique in organic technologies. Finally, we present the design (by simulations using a Spice model for OTFTs) and the test of analog and digital basic circuits: amplifiers with DC gains of about 20 dB, comparators, inverters and logic gates working in the frequency range of 1-10 kHz. These standard circuit cells could be used for signal conditioning and integrated as active matrices for flexible sensors from 3rd party institutions, thus opening our fab to new ideas and sophisticated pre-industrial low cost applications for the emerging fields of biomedical devices and wearable electronics for virtual/augmented reality.

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Addressable-Matrix Integrated-Circuit Test Structure

NASA Technical Reports Server (NTRS)

Sayah, Hoshyar R.; Buehler, Martin G.

1991-01-01

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

System-Level Integrated Circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

System-level integrated circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

Free-world microelectronic manufacturing equipment

NASA Astrophysics Data System (ADS)

Kilby, J. S.; Arnold, W. H.; Booth, W. T.; Cunningham, J. A.; Hutcheson, J. D.; Owen, R. W.; Runyan, W. R.; McKenney, Barbara L.; McGrain, Moira; Taub, Renee G.

1988-12-01

Equipment is examined and evaluated for the manufacture of microelectronic integrated circuit devices and sources for that equipment within the Free World. Equipment suitable for the following are examined: single-crystal silicon slice manufacturing and processing; required lithographic processes; wafer processing; device packaging; and test of digital integrated circuits. Availability of the equipment is also discussed, now and in the near future. Very adequate equipment for most stages of the integrated circuit manufacturing process is available from several sources, in different countries, although the best and most widely used versions of most manufacturing equipment are made in the United States or Japan. There is also an active market in used equipment, suitable for manufacture of capable integrated circuits with performance somewhat short of the present state of the art.

Chemical sensors fabricated by a photonic integrated circuit foundry

NASA Astrophysics Data System (ADS)

Stievater, Todd H.; Koo, Kee; Tyndall, Nathan F.; Holmstrom, Scott A.; Kozak, Dmitry A.; Goetz, Peter G.; McGill, R. Andrew; Pruessner, Marcel W.

2018-02-01

We describe the detection of trace concentrations of chemical agents using waveguide-enhanced Raman spectroscopy in a photonic integrated circuit fabricated by AIM Photonics. The photonic integrated circuit is based on a five-centimeter long silicon nitride waveguide with a trench etched in the top cladding to allow access to the evanescent field of the propagating mode by analyte molecules. This waveguide transducer is coated with a sorbent polymer to enhance detection sensitivity and placed between low-loss edge couplers. The photonic integrated circuit is laid-out using the AIM Photonics Process Design Kit and fabricated on a Multi-Project Wafer. We detect chemical warfare agent simulants at sub parts-per-million levels in times of less than a minute. We also discuss anticipated improvements in the level of integration for photonic chemical sensors, as well as existing challenges.

Hybrid stretchable circuits on silicone substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robinson, A., E-mail: adam.1.robinson@nokia.com; Aziz, A., E-mail: a.aziz1@lancaster.ac.uk; Liu, Q.

When rigid and stretchable components are integrated onto a single elastic carrier substrate, large strain heterogeneities appear in the vicinity of the deformable-non-deformable interfaces. In this paper, we report on a generic approach to manufacture hybrid stretchable circuits where commercial electronic components can be mounted on a stretchable circuit board. Similar to printed circuit board development, the components are electrically bonded on the elastic substrate and interconnected with stretchable electrical traces. The substrate—a silicone matrix carrying concentric rigid disks—ensures both the circuit elasticity and the mechanical integrity of the most fragile materials.

An Electronics Course Emphasizing Circuit Design

ERIC Educational Resources Information Center

Bergeson, Haven E.

1975-01-01

Describes a one-quarter introductory electronics course in which the students use a variety of inexpensive integrated circuits to design and construct a large number of useful circuits. Presents the subject matter of the course in three parts: linear circuits, digital circuits, and more complex circuits. (GS)

Periodic binary sequence generators: VLSI circuits considerations

NASA Technical Reports Server (NTRS)

Perlman, M.

1984-01-01

Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

The dialectic of Hebb and homeostasis.

PubMed

Turrigiano, Gina G

2017-03-05

It has become widely accepted that homeostatic and Hebbian plasticity mechanisms work hand in glove to refine neural circuit function. Nonetheless, our understanding of how these fundamentally distinct forms of plasticity compliment (and under some circumstances interfere with) each other remains rudimentary. Here, I describe some of the recent progress of the field, as well as some of the deep puzzles that remain. These include unravelling the spatial and temporal scales of different homeostatic and Hebbian mechanisms, determining which aspects of network function are under homeostatic control, and understanding when and how homeostatic and Hebbian mechanisms must be segregated within neural circuits to prevent interference.This article is part of the themed issue 'Integrating Hebbian and homeostatic plasticity'. © 2017 The Author(s).

Metasurface polarization splitter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Slovick, Brian A.; Zhou, You; Yu, Zhi Gang

Polarization beam splitters, devices that separate the two orthogonal polarizations of light into different propagation directions, are among the most ubiquitous optical elements. However, traditionally polarization splitters rely on bulky optical materials, while emerging optoelectronic and photonic circuits require compact, chip-scale polarization splitters. Here, we show that a rectangular lattice of cylindrical silicon Mie resonators functions as a polarization splitter, efficiently reflecting one polarization while transmitting the other. We show that the polarization splitting arises from the anisotropic permittivity and permeability of the metasurface due to the twofold rotational symmetry of the rectangular unit cell. Lastly, the high polarization efficiency,more » low loss and low profile make these metasurface polarization splitters ideally suited for monolithic integration with optoelectronic and photonic circuits.« less

Metasurface polarization splitter

DOE PAGES

Slovick, Brian A.; Zhou, You; Yu, Zhi Gang; ...

2017-02-20

Polarization beam splitters, devices that separate the two orthogonal polarizations of light into different propagation directions, are among the most ubiquitous optical elements. However, traditionally polarization splitters rely on bulky optical materials, while emerging optoelectronic and photonic circuits require compact, chip-scale polarization splitters. Here, we show that a rectangular lattice of cylindrical silicon Mie resonators functions as a polarization splitter, efficiently reflecting one polarization while transmitting the other. We show that the polarization splitting arises from the anisotropic permittivity and permeability of the metasurface due to the twofold rotational symmetry of the rectangular unit cell. Lastly, the high polarization efficiency,more » low loss and low profile make these metasurface polarization splitters ideally suited for monolithic integration with optoelectronic and photonic circuits.« less

Low frequency ac waveform generator

DOEpatents

Bilharz, O.W.

1983-11-22

Low frequency sine, cosine, triangle and square waves are synthesized in circuitry which allows variation in the waveform amplitude and frequency while exhibiting good stability and without requiring significant stablization time. A triangle waveform is formed by a ramped integration process controlled by a saturation amplifier circuit which produces the necessary hysteresis for the triangle waveform. The output of the saturation circuit is tapped to produce the square waveform. The sine waveform is synthesized by taking the absolute value of the triangular waveform, raising this absolute value to a predetermined power, multiplying the raised absolute value of the triangle wave with the triangle wave itself and properly scaling the resultant waveform and subtracting it from the triangular waveform to a predetermined power and adding the squared waveform raised to the predetermined power with a DC reference and subtracting the squared waveform therefrom, with all waveforms properly scaled. The resultant waveform is then multiplied with a square wave in order to correct the polarity and produce the resultant cosine waveform.

Imaging detectors and electronics—a view of the future

NASA Astrophysics Data System (ADS)

Spieler, Helmuth

2004-09-01

Imaging sensors and readout electronics have made tremendous strides in the past two decades. The application of modern semiconductor fabrication techniques and the introduction of customized monolithic integrated circuits have made large-scale imaging systems routine in high-energy physics. This technology is now finding its way into other areas, such as space missions, synchrotron light sources, and medical imaging. I review current developments and discuss the promise and limits of new technologies. Several detector systems are described as examples of future trends. The discussion emphasizes semiconductor detector systems, but I also include recent developments for large-scale superconducting detector arrays.

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Integrated-Circuit Pseudorandom-Number Generator

NASA Technical Reports Server (NTRS)

Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

1992-01-01

Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

Long life assurance study for manned spacecraft long life hardware. Volume 2: Long life assurance studies of EEE parts and packaging

NASA Technical Reports Server (NTRS)

1972-01-01

Guidelines for the design, development, and fabrication of electronic components and circuits for use in spacecraft construction are presented. The subjects discussed involve quality control procedures and test methodology for the following subjects: (1) monolithic integrated circuits, (2) hybrid integrated circuits, (3) transistors, (4) diodes, (5) tantalum capacitors, (6) electromechanical relays, (7) switches and circuit breakers, and (8) electronic packaging.

Asymmetric Memory Circuit Would Resist Soft Errors

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Perlman, Marvin

1990-01-01

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Radiation damage in MOS integrated circuits, Part 1

NASA Technical Reports Server (NTRS)

Danchenko, V.

1971-01-01

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Monolithic microwave integrated circuits for sensors, radar, and communications systems; Proceedings of the Meeting, Orlando, FL, Apr. 2-4, 1991

NASA Technical Reports Server (NTRS)

Leonard, Regis F. (Editor); Bhasin, Kul B. (Editor)

1991-01-01

Consideration is given to MMICs for airborne phased arrays, monolithic GaAs integrated circuit millimeter wave imaging sensors, accurate design of multiport low-noise MMICs up to 20 GHz, an ultralinear low-noise amplifier technology for space communications, variable-gain MMIC module for space applications, a high-efficiency dual-band power amplifier for radar applications, a high-density circuit approach for low-cost MMIC circuits, coplanar SIMMWIC circuits, recent advances in monolithic phased arrays, and system-level integrated circuit development for phased-array antenna applications. Consideration is also given to performance enhancement in future communications satellites with MMIC technology insertion, application of Ka-band MMIC technology for an Orbiter/ACTS communications experiment, a space-based millimeter wave debris tracking radar, low-noise high-yield octave-band feedback amplifiers to 20 GHz, quasi-optical MESFET VCOs, and a high-dynamic-range mixer using novel balun structure.

Silicon Carbide Integrated Circuit Chip

NASA Image and Video Library

2015-02-17

A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mitra, Kalyan Yoti, E-mail: kalyan-yoti.mitra@mb.tu-chemnitz.de, E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico, E-mail: kalyan-yoti.mitra@mb.tu-chemnitz.de, E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme

Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (frommore » Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.« less

Electronic Switch Arrays for Managing Microbattery Arrays

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Alahmad, Mahmoud; Sukumar, Vinesh; Zghoul, Fadi; Buck, Kevin; Hess, Herbert; Li, Harry; Cox, David

2008-01-01

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

PubMed Central

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-01-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design. PMID:28145438

Improving Unipolar Resistive Switching Uniformity with Cone-Shaped Conducting Filaments and Its Logic-In-Memory Application.

PubMed

Gao, Shuang; Liu, Gang; Chen, Qilai; Xue, Wuhong; Yang, Huali; Shang, Jie; Chen, Bin; Zeng, Fei; Song, Cheng; Pan, Feng; Li, Run-Wei

2018-02-21

Resistive random access memory (RRAM) with inherent logic-in-memory capability exhibits great potential to construct beyond von-Neumann computers. Particularly, unipolar RRAM is more promising because its single polarity operation enables large-scale crossbar logic-in-memory circuits with the highest integration density and simpler peripheral control circuits. However, unipolar RRAM usually exhibits poor switching uniformity because of random activation of conducting filaments and consequently cannot meet the strict uniformity requirement for logic-in-memory application. In this contribution, a new methodology that constructs cone-shaped conducting filaments by using chemically a active metal cathode is proposed to improve unipolar switching uniformity. Such a peculiar metal cathode will react spontaneously with the oxide switching layer to form an interfacial layer, which together with the metal cathode itself can act as a load resistor to prevent the overgrowth of conducting filaments and thus make them more cone-like. In this way, the rupture of conducting filaments can be strictly limited to the tip region, making their residual parts favorable locations for subsequent filament growth and thus suppressing their random regeneration. As such, a novel "one switch + one unipolar RRAM cell" hybrid structure is capable to realize all 16 Boolean logic functions for large-scale logic-in-memory circuits.

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

PubMed

Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

2010-01-01

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e(-) for the simple integration CMS and 75 dB and 2.2 e(-) for the folding integration CMS, respectively, are obtained.

Computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems

NASA Astrophysics Data System (ADS)

Ku, Walter H.

1989-05-01

The objectives of this research are to develop analytical and computer aided design techniques for monolithic microwave and millimeter wave integrated circuits (MMIC and MIMIC) and subsystems and to design and fabricate those ICs. Emphasis was placed on heterojunction-based devices, especially the High Electron Mobility Transition (HEMT), for both low noise and medium power microwave and millimeter wave applications. Circuits to be considered include monolithic low noise amplifiers, power amplifiers, and distributed and feedback amplifiers. Interactive computer aided design programs were developed, which include large signal models of InP MISFETs and InGaAs HEMTs. Further, a new unconstrained optimization algorithm POSM was developed and implemented in the general Analysis and Design program for Integrated Circuit (ADIC) for assistance in the design of largesignal nonlinear circuits.

Development, Integration and Testing of Automated Triggering Circuit for Hybrid DC Circuit Breaker

NASA Astrophysics Data System (ADS)

Kanabar, Deven; Roy, Swati; Dodiya, Chiragkumar; Pradhan, Subrata

2017-04-01

A novel concept of Hybrid DC circuit breaker having combination of mechanical switch and static switch provides arc-less current commutation into the dump resistor during quench in superconducting magnet operation. The triggering of mechanical and static switches in Hybrid DC breaker can be automatized which can effectively reduce the overall current commutation time of hybrid DC circuit breaker and make the operation independent of opening time of mechanical switch. With this view, a dedicated control circuit (auto-triggering circuit) has been developed which can decide the timing and pulse duration for mechanical switch as well as static switch from the operating parameters. This circuit has been tested with dummy parameters and thereafter integrated with the actual test set up of hybrid DC circuit breaker. This paper deals with the conceptual design of the auto-triggering circuit, its control logic and operation. The test results of Hybrid DC circuit breaker using this circuit have also been discussed.

Hybrid integrated biological-solid-state system powered with adenosine triphosphate.

PubMed

Roseman, Jared M; Lin, Jianxun; Ramakrishnan, Siddharth; Rosenstein, Jacob K; Shepard, Kenneth L

2015-12-07

There is enormous potential in combining the capabilities of the biological and the solid state to create hybrid engineered systems. While there have been recent efforts to harness power from naturally occurring potentials in living systems in plants and animals to power complementary metal-oxide-semiconductor integrated circuits, here we report the first successful effort to isolate the energetics of an electrogenic ion pump in an engineered in vitro environment to power such an artificial system. An integrated circuit is powered by adenosine triphosphate through the action of Na(+)/K(+) adenosine triphosphatases in an integrated in vitro lipid bilayer membrane. The ion pumps (active in the membrane at numbers exceeding 2 × 10(6) mm(-2)) are able to sustain a short-circuit current of 32.6 pA mm(-2) and an open-circuit voltage of 78 mV, providing for a maximum power transfer of 1.27 pW mm(-2) from a single bilayer. Two series-stacked bilayers provide a voltage sufficient to operate an integrated circuit with a conversion efficiency of chemical to electrical energy of 14.9%.

Triggerable electro-optic amplitude modulator bias stabilizer for integrated optical devices

DOEpatents

Conder, A.D.; Haigh, R.E.; Hugenberg, K.F.

1995-09-26

An improved Mach-Zehnder integrated optical electro-optic modulator is achieved by application and incorporation of a DC bias box containing a laser synchronized trigger circuit, a DC ramp and hold circuit, a modulator transfer function negative peak detector circuit, and an adjustable delay circuit. The DC bias box ramps the DC bias along the transfer function curve to any desired phase or point of operation at which point the RF modulation takes place. 7 figs.

Triggerable electro-optic amplitude modulator bias stabilizer for integrated optical devices

DOEpatents

Conder, Alan D.; Haigh, Ronald E.; Hugenberg, Keith F.

1995-01-01

An improved Mach-Zehnder integrated optical electro-optic modulator is achieved by application and incorporation of a DC bias box containing a laser synchronized trigger circuit, a DC ramp and hold circuit, a modulator transfer function negative peak detector circuit, and an adjustable delay circuit. The DC bias box ramps the DC bias along the transfer function curve to any desired phase or point of operation at which point the RF modulation takes place.

Cost optimization in low volume VLSI circuits

NASA Technical Reports Server (NTRS)

Cook, K. B., Jr.; Kerns, D. V., Jr.

1982-01-01

The relationship of integrated circuit (IC) cost to electronic system cost is developed using models for integrated circuit cost which are based on design/fabrication approach. Emphasis is on understanding the relationship between cost and volume for custom circuits suitable for NASA applications. In this report, reliability is a major consideration in the models developed. Results are given for several typical IC designs using off the shelf, full custom, and semicustom IC's with single and double level metallization.

Gated integrator with signal baseline subtraction

DOEpatents

Wang, X.

1996-12-17

An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window. 5 figs.

Gated integrator with signal baseline subtraction

DOEpatents

Wang, Xucheng

1996-01-01

An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

PubMed

Asano, Sho; Muroyama, Masanori; Nakayama, Takahiro; Hata, Yoshiyuki; Nonomura, Yutaka; Tanaka, Shuji

2017-10-25

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer †

PubMed Central

Asano, Sho; Nakayama, Takahiro; Hata, Yoshiyuki; Tanaka, Shuji

2017-01-01

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively. PMID:29068429

Disposable photonic integrated circuits for evanescent wave sensors by ultra-high volume roll-to-roll method.

PubMed

Aikio, Sanna; Hiltunen, Jussi; Hiitola-Keinänen, Johanna; Hiltunen, Marianne; Kontturi, Ville; Siitonen, Samuli; Puustinen, Jarkko; Karioja, Pentti

2016-02-08

Flexible photonic integrated circuit technology is an emerging field expanding the usage possibilities of photonics, particularly in sensor applications, by enabling the realization of conformable devices and introduction of new alternative production methods. Here, we demonstrate that disposable polymeric photonic integrated circuit devices can be produced in lengths of hundreds of meters by ultra-high volume roll-to-roll methods on a flexible carrier. Attenuation properties of hundreds of individual devices were measured confirming that waveguides with good and repeatable performance were fabricated. We also demonstrate the applicability of the devices for the evanescent wave sensing of ambient refractive index. The production of integrated photonic devices using ultra-high volume fabrication, in a similar manner as paper is produced, may inherently expand methods of manufacturing low-cost disposable photonic integrated circuits for a wide range of sensor applications.

Package for integrated optic circuit and method

DOEpatents

Kravitz, Stanley H.; Hadley, G. Ronald; Warren, Mial E.; Carson, Richard F.; Armendariz, Marcelino G.

1998-01-01

A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-29

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-08

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

2007-12-18

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Package for integrated optic circuit and method

DOEpatents

Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

1998-08-04

A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

Silica Integrated Optical Circuits Based on Glass Photosensitivity

NASA Technical Reports Server (NTRS)

Abushagur, Mustafa A. G.

1999-01-01

Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

Jig For Stereoscopic Photography

NASA Technical Reports Server (NTRS)

Nielsen, David J.

1990-01-01

Separations between views adjusted precisely for best results. Simple jig adjusted to set precisely, distance between right and left positions of camera used to make stereoscopic photographs. Camera slides in slot between extreme positions, where it takes stereoscopic pictures. Distance between extreme positions set reproducibly with micrometer. In view of trend toward very-large-scale integration of electronic circuits, training method and jig used to make training photographs useful to many companies to reduce cost of training manufacturing personnel.

Programmable Direct-Memory-Access Controller

NASA Technical Reports Server (NTRS)

Hendry, David F.

1990-01-01

Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

III-V Semiconductor Optical Micro-Ring Resonators

NASA Astrophysics Data System (ADS)

Grover, Rohit; Absil, Philippe P.; Ibrahim, Tarek A.; Ho, Ping-Tong

2004-05-01

We describe the theory of optical ring resonators, and our work on GaAs-AlGaAs and GaInAsP-InP optical micro-ring resonators. These devices are promising building blocks for future all-optical signal processing and photonic logic circuits. Their versatility allows the fabrication of ultra-compact multiplexers/demultiplexers, optical channel dropping filters, lasers, amplifiers, and logic gates (to name a few), which will enable large-scale monolithic integration for optics.

Read-In Integrated Circuits for Large-Format Multi-Chip Emitter Arrays

DTIC Science & Technology

2015-03-31

chip has been designed and fabricated using ONSEMI C5N process to verify our approach. Keywords: Large scale arrays; Tiling; Mosaic; Abutment ...required. X and y addressing is not a sustainable and easily expanded addressing architecture nor will it work well with abutted RIICs. Abutment Method... Abutting RIICs into an array is challenging because of the precise positioning required to achieve a uniform image. This problem is a new design

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

ERIC Educational Resources Information Center

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Exchange circuits for FASTBUS slaves

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bratskii, A.A.; Matseev, M.Y.; Rybakov, V.G.

1985-09-01

This paper describes general-purpose circuits for FASTBUS interfacing of the functional part of a slave device. The circuits contain buffered receivers and transmitters, addressrecognition and data-transfer logic, and the required control/status registers. The described circuits are implemented with series-K500 integrated circuits.

TOFPET 2: A high-performance circuit for PET time-of-flight

NASA Astrophysics Data System (ADS)

Di Francesco, Agostino; Bugalho, Ricardo; Oliveira, Luis; Rivetti, Angelo; Rolo, Manuel; Silva, Jose C.; Varela, Joao

2016-07-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

Neural circuits. Labeling of active neural circuits in vivo with designed calcium integrators.

PubMed

Fosque, Benjamin F; Sun, Yi; Dana, Hod; Yang, Chao-Tsung; Ohyama, Tomoko; Tadross, Michael R; Patel, Ronak; Zlatic, Marta; Kim, Douglas S; Ahrens, Misha B; Jayaraman, Vivek; Looger, Loren L; Schreiter, Eric R

2015-02-13

The identification of active neurons and circuits in vivo is a fundamental challenge in understanding the neural basis of behavior. Genetically encoded calcium (Ca(2+)) indicators (GECIs) enable quantitative monitoring of cellular-resolution activity during behavior. However, such indicators require online monitoring within a limited field of view. Alternatively, post hoc staining of immediate early genes (IEGs) indicates highly active cells within the entire brain, albeit with poor temporal resolution. We designed a fluorescent sensor, CaMPARI, that combines the genetic targetability and quantitative link to neural activity of GECIs with the permanent, large-scale labeling of IEGs, allowing a temporally precise "activity snapshot" of a large tissue volume. CaMPARI undergoes efficient and irreversible green-to-red conversion only when elevated intracellular Ca(2+) and experimenter-controlled illumination coincide. We demonstrate the utility of CaMPARI in freely moving larvae of zebrafish and flies, and in head-fixed mice and adult flies. Copyright © 2015, American Association for the Advancement of Science.

Energy efficient circuit design using nanoelectromechanical relays

NASA Astrophysics Data System (ADS)

Venkatasubramanian, Ramakrishnan

Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS. This dissertation demonstrates NEM relay based charge pump and NEM-CMOS heterogeneous discontinuous conduction mode (DCM) buck regulator and the results are compared against a standard commercial 0.35μm CMOS implementation. It is shown that NEM-CMOS heterogeneous DC-DC converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100mA. NEM relays offers unprecedented 10X-30X energy efficiency improvement in logic design for low frequency operation and has the potential to break the CMOS efficiency barrier in power electronic circuits as well. The practical aspects of NEM Relay integration are evaluated and algorithms for synthesis and development of large NEM relay based logic circuits are explored.

In situ fabricated 3D micro-lenses for photonic integrated circuits.

PubMed

Thomas, R; Li, J; Ladak, Sam; Barrow, D; Smowton, P M

2018-05-14

Aspheric astigmatic polymer micro-lenses were fabricated directly onto photonic integrated circuits using two-photon lithography. We observed a 12.6 dB improvement in the free space coupling efficiency between integrated ridge laser pairs with micro-lenses to those without.

Multipurpose instrumentation cable provides integral thermocouple circuit

NASA Technical Reports Server (NTRS)

Zellner, G.

1967-01-01

Multipurpose cable with an integral thermocouple circuit measures strain, vibration, pressure, throughout a wide temperature range. This cable reduces bulky and complex circuitry by eliminating separate thermocouples for each transducer.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2006-12-12

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2004-05-18

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Investigation for connecting waveguide in off-planar integrated circuits.

PubMed

Lin, Jie; Feng, Zhifang

2017-09-01

The transmission properties of a vertical waveguide connected by different devices in off-planar integrated circuits are designed, investigated, and analyzed in detail by the finite-difference time-domain method. The results show that both guide bandwidth and transmission efficiency can be adjusted effectively by shifting the vertical waveguide continuously. Surprisingly, the wide guide band (0.385[c/a]∼0.407[c/a]) and well transmission (-6  dB) are observed simultaneously in several directions when the vertical waveguide is located at a specific location. The results are very important for all-optical integrated circuits, especially in compact integration.

Development of a 2K x 2K GaAs QWIP Focal Plane Array

NASA Technical Reports Server (NTRS)

Jhabvala, M.; Choi, K.; Jhabvala, C.; Kelly, D.; Hess, L.; Ewin, A.; La, A.; Wacynski, A.; Sun, J.; Adachi, T.;

Fault tolerant system based on IDDQ testing

NASA Astrophysics Data System (ADS)

Guibane, Badi; Hamdi, Belgacem; Mtibaa, Abdellatif; Bensalem, Brahim

2018-06-01

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.

Toward a fully integrated neurostimulator with inductive power recovery front-end.

PubMed

Mounaïm, Fayçal; Sawan, Mohamad

2012-08-01

In order to investigate new neurostimulation strategies for micturition recovery in spinal cord injured patients, custom implantable stimulators are required to carry-on chronic animal experiments. However, higher integration of the neurostimulator becomes increasingly necessary for miniaturization purposes, power consumption reduction, and for increasing the number of stimulation channels. As a first step towards total integration, we present in this paper the design of a highly-integrated neurostimulator that can be assembled on a 21-mm diameter printed circuit board. The prototype is based on three custom integrated circuits fabricated in High-Voltage (HV) CMOS technology, and a low-power small-scale commercially available FPGA. Using a step-down approach where the inductive voltage is left free up to 20 V, the inductive power and data recovery front-end is fully integrated. In particular, the front-end includes a bridge rectifier, a 20-V voltage limiter, an adjustable series regulator (5 to 12 V), a switched-capacitor step-down DC/DC converter (1:3, 1:2, or 2:3 ratio), as well as data recovery. Measurements show that the DC/DC converter achieves more than 86% power efficiency while providing around 3.9-V from a 12-V input at 1-mA load, 1:3 conversion ratio, and 50-kHz switching frequency. With such efficiency, the proposed step-down inductive power recovery topology is more advantageous than its conventional step-up counterpart. Experimental results confirm good overall functionality of the system.

Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

PubMed

LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

2014-06-02

We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

A programmable heater control circuit for spacecraft

NASA Technical Reports Server (NTRS)

Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

1994-01-01

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

Final report for CCS cross-layer reliability visioning study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Dehon, Andre; Carter, Nicj

The geometric rate of improvement of transistor size and integrated circuit performance known as Moore's Law has been an engine of growth for our economy, enabling new products and services, creating new value and wealth, increasing safety, and removing menial tasks from our daily lives. Affordable, highly integrated components have enabled both life-saving technologies and rich entertainment applications. Anti-lock brakes, insulin monitors, and GPS-enabled emergency response systems save lives. Cell phones, internet appliances, virtual worlds, realistic video games, and mp3 players enrich our lives and connect us together. Over the past 40 years of silicon scaling, the increasing capabilities ofmore » inexpensive computation have transformed our society through automation and ubiquitous communications. Looking forward, increasing unpredictability threatens our ability to continue scaling integrated circuits at Moore's Law rates. As the transistors and wires that make up integrated circuits become smaller, they display both greater differences in behavior among devices designed to be identical and greater vulnerability to transient and permanent faults. Conventional design techniques expend energy to tolerate this unpredictability by adding safety margins to a circuit's operating voltage, clock frequency or charge stored per bit. However, the rising energy costs needed to compensate for increasing unpredictability are rapidly becoming unacceptable in today's environment where power consumption is often the limiting factor on integrated circuit performance and energy efficiency is a national concern. Reliability and energy consumption are both reaching key inflection points that, together, threaten to reduce or end the benefits of feature size reduction. To continue beneficial scaling, we must use a cross-layer, Jull-system-design approach to reliability. Unlike current systems, which charge every device a substantial energy tax in order to guarantee correct operation in spite of rare events, such as one high-threshold transistor in a billion or one erroneous gate evaluation in an hour of computation, cross-layer reliability schemes make reliability management a cooperative effort across the system stack, sharing information across layers so that they only expend energy on reliability when an error actually occurs. Figure 1 illustrates an example of such a system that uses a combination of information from the application and cheap architecture-level techniques to detect errors. When an error occurs, mechanisms at higher levels in the stack correct the error, efficiently delivering correct operation to the user in spite of errors at the device or circuit levels. In the realms of memory and communication, engineers have a long history of success in tolerating unpredictable effects such as fabrication variability, transient upsets, and lifetime wear using information sharing, limited redundancy, and cross-layer approaches that anticipate, accommodate, and suppress errors. Networks use a combination of hardware and software to guarantee end-toend correctness. Error-detection and correction codes use additional information to correct the most common errors, single-bit transmission errors. When errors occur that cannot be corrected by these codes, the network protocol requests re-transmission of one or more packets until the correct data is received. Similarly, computer memory systems exploit a cross-layer division of labor to achieve high performance with modest hardware. Rather than demanding that hardware alone provide the virtual memory abstraction, software page-fault and TLB-miss handlers allow a modest piece of hardware, the TLB, to handle the common-case operations on a cyc1e-by-cycle basis while infrequent misses are handled in system software. Unfortunately, mitigating logic errors is not as simple or as well researched as memory or communication systems. This lack of understanding has led to very expensive solutions. For example, triple-modular redundancy masks errors by triplicating computations in either time or area. This mitigation methods imposes a 200% increase in energy consumption for every operation, not just the uncommon failure cases. At a time when computation is rapidly becoming part of our critical civilian and military infrastructure and decreasing costsfor computation are fueling our economy and our well being, we cannot afford increasingly unreliable electronics or a stagnation in capabilities per dollar, watt, or cubic meter. If researchers are able to develop techniques that tolerate the growing unpredictability of silicon devices, Moore's Law scaling should continue until at least 2022. During this 12-year time period, transistors, which are the building blocks of electronic devices, will scale their dimensions (feature sizes) from 45nm to 4.5nm.« less

A 14 × 14 μm2 footprint polarization-encoded quantum controlled-NOT gate based on hybrid waveguide

PubMed Central

Wang, S. M.; Cheng, Q. Q.; Gong, Y. X.; Xu, P.; Sun, C.; Li, L.; Li, T.; Zhu, S. N.

2016-01-01

Photonic quantum information processing system has been widely used in communication, metrology and lithography. The recent emphasis on the miniaturized photonic platform is thus motivated by the urgent need for realizing large-scale information processing and computing. Although the integrated quantum logic gates and quantum algorithms based on path encoding have been successfully demonstrated, the technology for handling another commonly used polarization-encoded qubits has yet to be fully developed. Here, we show the implementation of a polarization-dependent beam-splitter in the hybrid waveguide system. With precisely design, the polarization-encoded controlled-NOT gate can be implemented using only single such polarization-dependent beam-splitter with the significant size reduction of the overall device footprint to 14 × 14 μm2. The experimental demonstration of the highly integrated controlled-NOT gate sets the stage to develop large-scale quantum information processing system. Our hybrid design also establishes the new capabilities in controlling the polarization modes in integrated photonic circuits. PMID:27142992

Hybrid integration of III-V semiconductor lasers on silicon waveguides using optofluidic microbubble manipulation

PubMed Central

Jung, Youngho; Shim, Jaeho; Kwon, Kyungmook; You, Jong-Bum; Choi, Kyunghan; Yu, Kyoungsik

2016-01-01

Optofluidic manipulation mechanisms have been successfully applied to micro/nano-scale assembly and handling applications in biophysics, electronics, and photonics. Here, we extend the laser-based optofluidic microbubble manipulation technique to achieve hybrid integration of compound semiconductor microdisk lasers on the silicon photonic circuit platform. The microscale compound semiconductor block trapped on the microbubble surface can be precisely assembled on a desired position using photothermocapillary convective flows induced by focused laser beam illumination. Strong light absorption within the micro-scale compound semiconductor object allows real-time and on-demand microbubble generation. After the assembly process, we verify that electromagnetic radiation from the optically-pumped InGaAsP microdisk laser can be efficiently coupled to the single-mode silicon waveguide through vertical evanescent coupling. Our simple and accurate microbubble-based manipulation technique may provide a new pathway for realizing high precision fluidic assembly schemes for heterogeneously integrated photonic/electronic platforms as well as microelectromechanical systems. PMID:27431769

A 14 × 14 μm(2) footprint polarization-encoded quantum controlled-NOT gate based on hybrid waveguide.

PubMed

Wang, S M; Cheng, Q Q; Gong, Y X; Xu, P; Sun, C; Li, L; Li, T; Zhu, S N

2016-05-04

Photonic quantum information processing system has been widely used in communication, metrology and lithography. The recent emphasis on the miniaturized photonic platform is thus motivated by the urgent need for realizing large-scale information processing and computing. Although the integrated quantum logic gates and quantum algorithms based on path encoding have been successfully demonstrated, the technology for handling another commonly used polarization-encoded qubits has yet to be fully developed. Here, we show the implementation of a polarization-dependent beam-splitter in the hybrid waveguide system. With precisely design, the polarization-encoded controlled-NOT gate can be implemented using only single such polarization-dependent beam-splitter with the significant size reduction of the overall device footprint to 14 × 14 μm(2). The experimental demonstration of the highly integrated controlled-NOT gate sets the stage to develop large-scale quantum information processing system. Our hybrid design also establishes the new capabilities in controlling the polarization modes in integrated photonic circuits.

A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

NASA Astrophysics Data System (ADS)

Arefin, Md Shamsul; Bulut Coskun, M.; Alan, Tuncay; Redoute, Jean-Michel; Neild, Adrian; Rasit Yuce, Mehmet

2014-06-01

This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0-5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

Multislice imaging of integrated circuits by precession X-ray ptychography.

PubMed

Shimomura, Kei; Hirose, Makoto; Takahashi, Yukio

2018-01-01

A method for nondestructively visualizing multisection nanostructures of integrated circuits by X-ray ptychography with a multislice approach is proposed. In this study, tilt-series ptychographic diffraction data sets of a two-layered circuit with a ∼1.4 µm gap at nine incident angles are collected in a wide Q range and then artifact-reduced phase images of each layer are successfully reconstructed at ∼10 nm resolution. The present method has great potential for the three-dimensional observation of flat specimens with thickness on the order of 100 µm, such as three-dimensional stacked integrated circuits based on through-silicon vias, without laborious sample preparation.

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Smart Power: New power integrated circuit technologies and their applications

NASA Astrophysics Data System (ADS)

Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

1992-05-01

Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

The Management of Cognitive Load During Complex Cognitive Skill Acquisition by Means of Computer-Simulated Problem Solving

ERIC Educational Resources Information Center

Kester, Liesbeth; Kirschner, Paul A.; van Merrienboer, Jeroen J.G.

2005-01-01

This study compared the effects of two information presentation formats on learning to solve problems in electrical circuits. In one condition, the split-source format, information relating to procedural aspects of the functioning of an electrical circuit was not integrated in a circuit diagram, while information in the integrated format condition…

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Cascade photonic integrated circuit architecture for electro-optic in-phase quadrature/single sideband modulation or frequency conversion.

PubMed

Hasan, Mehedi; Hall, Trevor

2015-11-01

A photonic integrated circuit architecture for implementing frequency upconversion is proposed. The circuit consists of a 1×2 splitter and 2×1 combiner interconnected by two stages of differentially driven phase modulators having 2×2 multimode interference coupler between the stages. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. The intrinsic conversion efficiency of the proposed design is improved by 6 dB over the alternative functionally equivalent circuit based on dual parallel Mach-Zehnder modulators known in the prior art. A two-tone analysis is presented to study the linearity of the proposed circuit, and a comparison is provided over the alternative. The proposed circuit is suitable for integration in any platform that offers linear electro-optic phase modulation such as LiNbO(3), silicon, III-V, or hybrid technology.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Dual-function photonic integrated circuit for frequency octo-tupling or single-side-band modulation.

PubMed

Hasan, Mehedi; Maldonado-Basilio, Ramón; Hall, Trevor J

2015-06-01

A dual-function photonic integrated circuit for microwave photonic applications is proposed. The circuit consists of four linear electro-optic phase modulators connected optically in parallel within a generalized Mach-Zehnder interferometer architecture. The photonic circuit is arranged to have two separate output ports. A first port provides frequency up-conversion of a microwave signal from the electrical to the optical domain; equivalently single-side-band modulation. A second port provides tunable millimeter wave carriers by frequency octo-tupling of an appropriate amplitude RF carrier. The circuit exploits the intrinsic relative phases between the ports of multi-mode interference couplers to provide substantially all the static optical phases needed. The operation of the proposed dual-function photonic integrated circuit is verified by computer simulations. The performance of the frequency octo-tupling and up-conversion functions is analyzed in terms of the electrical signal to harmonic distortion ratio and the optical single side band to unwanted harmonics ratio, respectively.

THz-circuits driven by photo-thermoelectric, gate-tunable graphene-junctions

NASA Astrophysics Data System (ADS)

Brenneis, Andreas; Schade, Felix; Drieschner, Simon; Heimbach, Florian; Karl, Helmut; Garrido, Jose A.; Holleitner, Alexander W.

2016-10-01

For future on-chip communication schemes, it is essential to integrate nanoscale materials with an ultrafast optoelectronic functionality into high-frequency circuits. The atomically thin graphene has been widely demonstrated to be suitable for photovoltaic and optoelectronic devices because of its broadband optical absorption and its high electron mobility. Moreover, the ultrafast relaxation of photogenerated charge carriers has been verified in graphene. Here, we show that dual-gated graphene junctions can be functional parts of THz-circuits. As the underlying optoelectronic process, we exploit ultrafast photo-thermoelectric currents. We describe an immediate photo-thermoelectric current of the unbiased device following a femtosecond laser excitation. For a picosecond time-scale after the optical excitation, an additional photo-thermoelectric contribution shows up, which exhibits the fingerprint of a spatially inverted temperature profile. The latter can be understood by the different time-constants and thermal coupling mechanisms of the electron and phonon baths within graphene to the substrate and the metal contacts. The interplay of the processes gives rise to ultrafast electromagnetic transients in high-frequency circuits, and it is equally important for a fundamental understanding of graphene-based ultrafast photodetectors and switches.

THz-circuits driven by photo-thermoelectric, gate-tunable graphene-junctions

PubMed Central

Brenneis, Andreas; Schade, Felix; Drieschner, Simon; Heimbach, Florian; Karl, Helmut; Garrido, Jose A.; Holleitner, Alexander W.

2016-01-01

For future on-chip communication schemes, it is essential to integrate nanoscale materials with an ultrafast optoelectronic functionality into high-frequency circuits. The atomically thin graphene has been widely demonstrated to be suitable for photovoltaic and optoelectronic devices because of its broadband optical absorption and its high electron mobility. Moreover, the ultrafast relaxation of photogenerated charge carriers has been verified in graphene. Here, we show that dual-gated graphene junctions can be functional parts of THz-circuits. As the underlying optoelectronic process, we exploit ultrafast photo-thermoelectric currents. We describe an immediate photo-thermoelectric current of the unbiased device following a femtosecond laser excitation. For a picosecond time-scale after the optical excitation, an additional photo-thermoelectric contribution shows up, which exhibits the fingerprint of a spatially inverted temperature profile. The latter can be understood by the different time-constants and thermal coupling mechanisms of the electron and phonon baths within graphene to the substrate and the metal contacts. The interplay of the processes gives rise to ultrafast electromagnetic transients in high-frequency circuits, and it is equally important for a fundamental understanding of graphene-based ultrafast photodetectors and switches. PMID:27762291

THz-circuits driven by photo-thermoelectric, gate-tunable graphene-junctions.

PubMed

Brenneis, Andreas; Schade, Felix; Drieschner, Simon; Heimbach, Florian; Karl, Helmut; Garrido, Jose A; Holleitner, Alexander W

2016-10-20

For future on-chip communication schemes, it is essential to integrate nanoscale materials with an ultrafast optoelectronic functionality into high-frequency circuits. The atomically thin graphene has been widely demonstrated to be suitable for photovoltaic and optoelectronic devices because of its broadband optical absorption and its high electron mobility. Moreover, the ultrafast relaxation of photogenerated charge carriers has been verified in graphene. Here, we show that dual-gated graphene junctions can be functional parts of THz-circuits. As the underlying optoelectronic process, we exploit ultrafast photo-thermoelectric currents. We describe an immediate photo-thermoelectric current of the unbiased device following a femtosecond laser excitation. For a picosecond time-scale after the optical excitation, an additional photo-thermoelectric contribution shows up, which exhibits the fingerprint of a spatially inverted temperature profile. The latter can be understood by the different time-constants and thermal coupling mechanisms of the electron and phonon baths within graphene to the substrate and the metal contacts. The interplay of the processes gives rise to ultrafast electromagnetic transients in high-frequency circuits, and it is equally important for a fundamental understanding of graphene-based ultrafast photodetectors and switches.

Nonreciprocal Signal Routing in an Active Quantum Network

NASA Astrophysics Data System (ADS)

Tureci, Hakan E.; Metelmann, Anja

As superconductor quantum technologies are moving towards large-scale integrated circuits, a robust and flexible approach to routing photons at the quantum level becomes a critical problem. Active circuits, which contain driven linear or non-linear elements judiciously embedded in the circuit offer a viable solution. We present a general strategy for routing non-reciprocally quantum signals between two sites of a given lattice of resonators, implementable with existing superconducting circuit components. Our approach makes use of a dual lattice of superconducting non-linear elements on the links connecting the nodes of the main lattice. Solutions for spatially selective driving of the link-elements can be found, which optimally balance coherent and dissipative hopping of microwave photons to non-reciprocally route signals between two given nodes. In certain lattices these optimal solutions are obtained at the exceptional point of the scattering matrix of the network. The presented strategy provides a design space that is governed by a dynamically tunable non-Hermitian generator that can be used to minimize the added quantum noise as well. This work was supported by the U.S. Army Research Office (ARO) under Grant No. W911NF-15-1-0299.

Communication and wiring in the cortical connectome

PubMed Central

Budd, Julian M. L.; Kisvárday, Zoltán F.

2012-01-01

In cerebral cortex, the huge mass of axonal wiring that carries information between near and distant neurons is thought to provide the neural substrate for cognitive and perceptual function. The goal of mapping the connectivity of cortical axons at different spatial scales, the cortical connectome, is to trace the paths of information flow in cerebral cortex. To appreciate the relationship between the connectome and cortical function, we need to discover the nature and purpose of the wiring principles underlying cortical connectivity. A popular explanation has been that axonal length is strictly minimized both within and between cortical regions. In contrast, we have hypothesized the existence of a multi-scale principle of cortical wiring where to optimize communication there is a trade-off between spatial (construction) and temporal (routing) costs. Here, using recent evidence concerning cortical spatial networks we critically evaluate this hypothesis at neuron, local circuit, and pathway scales. We report three main conclusions. First, the axonal and dendritic arbor morphology of single neocortical neurons may be governed by a similar wiring principle, one that balances the conservation of cellular material and conduction delay. Second, the same principle may be observed for fiber tracts connecting cortical regions. Third, the absence of sufficient local circuit data currently prohibits any meaningful assessment of the hypothesis at this scale of cortical organization. To avoid neglecting neuron and microcircuit levels of cortical organization, the connectome framework should incorporate more morphological description. In addition, structural analyses of temporal cost for cortical circuits should take account of both axonal conduction and neuronal integration delays, which appear mostly of the same order of magnitude. We conclude the hypothesized trade-off between spatial and temporal costs may potentially offer a powerful explanation for cortical wiring patterns. PMID:23087619

Compensated gain control circuit for buck regulator command charge circuit

DOEpatents

Barrett, David M.

1996-01-01

A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit.

Compensated gain control circuit for buck regulator command charge circuit

DOEpatents

Barrett, D.M.

1996-11-05

A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit. 5 figs.

An integrated circuit switch

NASA Technical Reports Server (NTRS)

Bonin, E. L.

1969-01-01

Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

Chemical etching for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1981-01-01

Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

Multiple network interface core apparatus and method

DOEpatents

Underwood, Keith D [Albuquerque, NM; Hemmert, Karl Scott [Albuquerque, NM

2011-04-26

A network interface controller and network interface control method comprising providing a single integrated circuit as a network interface controller and employing a plurality of network interface cores on the single integrated circuit.

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

PubMed

Dutta, Sangya; Kumar, Vinay; Shukla, Aditya; Mohapatra, Nihar R; Ganguly, Udayan

2017-08-15

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~10 11 neuron based) large neural networks.

Functional Laser Trimming Of Thin Film Resistors On Silicon ICs

NASA Astrophysics Data System (ADS)

Mueller, Michael J.; Mickanin, Wes

1986-07-01

Modern Laser Wafer Trimming (LWT) technology achieves exceptional analog circuit performance and precision while maintain-ing the advantages of high production throughput and yield. Microprocessor-driven instrumentation has both emphasized the role of data conversion circuits and demanded sophisticated signal conditioning functions. Advanced analog semiconductor circuits with bandwidths over 1 GHz, and high precision, trimmable, thin-film resistors meet many of todays emerging circuit requirements. Critical to meeting these requirements are optimum choices of laser characteristics, proper materials, trimming process control, accurate modeling of trimmed resistor performance, and appropriate circuit design. Once limited exclusively to hand-crafted, custom integrated circuits, designs are now available in semi-custom circuit configurations. These are similar to those provided for digital designs and supported by computer-aided design (CAD) tools. Integrated with fully automated measurement and trimming systems, these quality circuits can now be produced in quantity to meet the requirements of communications, instrumentation, and signal processing markets.

The scientific data acquisition system of the GAMMA-400 space project

NASA Astrophysics Data System (ADS)

Bobkov, S. G.; Serdin, O. V.; Gorbunov, M. S.; Arkhangelskiy, A. I.; Topchiev, N. P.

2016-02-01

The description of scientific data acquisition system (SDAS) designed by SRISA for the GAMMA-400 space project is presented. We consider the problem of different level electronics unification: the set of reliable fault-tolerant integrated circuits fabricated on Silicon-on-Insulator 0.25 mkm CMOS technology and the high-speed interfaces and reliable modules used in the space instruments. The characteristics of reliable fault-tolerant very large scale integration (VLSI) technology designed by SRISA for the developing of computation systems for space applications are considered. The scalable net structure of SDAS based on Serial RapidIO interface including real-time operating system BAGET is described too.

Video data compression using artificial neural network differential vector quantization

NASA Technical Reports Server (NTRS)

Krishnamurthy, Ashok K.; Bibyk, Steven B.; Ahalt, Stanley C.

1991-01-01

An artificial neural network vector quantizer is developed for use in data compression applications such as Digital Video. Differential Vector Quantization is used to preserve edge features, and a new adaptive algorithm, known as Frequency-Sensitive Competitive Learning, is used to develop the vector quantizer codebook. To develop real time performance, a custom Very Large Scale Integration Application Specific Integrated Circuit (VLSI ASIC) is being developed to realize the associative memory functions needed in the vector quantization algorithm. By using vector quantization, the need for Huffman coding can be eliminated, resulting in superior performance against channel bit errors than methods that use variable length codes.

Smart integrated microsystems: the energy efficiency challenge (Conference Presentation) (Plenary Presentation)

NASA Astrophysics Data System (ADS)

Benini, Luca

2017-06-01

The "internet of everything" envisions trillions of connected objects loaded with high-bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. From the computational viewpoint, the challenge is formidable and can be addressed only by pushing computing fabrics toward massive parallelism and brain-like energy efficiency levels. CMOS technology can still take us a long way toward this goal, but technology scaling is losing steam. Energy efficiency improvement will increasingly hinge on architecture, circuits, design techniques such as heterogeneous 3D integration, mixed-signal preprocessing, event-based approximate computing and non-Von-Neumann architectures for scalable acceleration.

Pass-transistor very large scale integration

NASA Technical Reports Server (NTRS)

Maki, Gary K. (Inventor); Bhatia, Prakash R. (Inventor)

2004-01-01

Logic elements are provided that permit reductions in layout size and avoidance of hazards. Such logic elements may be included in libraries of logic cells. A logical function to be implemented by the logic element is decomposed about logical variables to identify factors corresponding to combinations of the logical variables and their complements. A pass transistor network is provided for implementing the pass network function in accordance with this decomposition. The pass transistor network includes ordered arrangements of pass transistors that correspond to the combinations of variables and complements resulting from the logical decomposition. The logic elements may act as selection circuits and be integrated with memory and buffer elements.

Metasurface polarization splitter

PubMed Central

Slovick, Brian A.; Zhou, You; Yu, Zhi Gang; Kravchenko, Ivan I.; Briggs, Dayrl P.; Moitra, Parikshit; Krishnamurthy, Srini

2017-01-01

Polarization beam splitters, devices that separate the two orthogonal polarizations of light into different propagation directions, are among the most ubiquitous optical elements. However, traditionally polarization splitters rely on bulky optical materials, while emerging optoelectronic and photonic circuits require compact, chip-scale polarization splitters. Here, we show that a rectangular lattice of cylindrical silicon Mie resonators functions as a polarization splitter, efficiently reflecting one polarization while transmitting the other. We show that the polarization splitting arises from the anisotropic permittivity and permeability of the metasurface due to the twofold rotational symmetry of the rectangular unit cell. The high polarization efficiency, low loss and low profile make these metasurface polarization splitters ideally suited for monolithic integration with optoelectronic and photonic circuits. This article is part of the themed issue ‘New horizons for nanophotonics’. PMID:28220002

Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology

NASA Technical Reports Server (NTRS)

Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

1981-01-01

Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

Synaptic Scaling Enables Dynamically Distinct Short- and Long-Term Memory Formation

PubMed Central

Tetzlaff, Christian; Kolodziejski, Christoph; Timme, Marc; Tsodyks, Misha; Wörgötter, Florentin

2013-01-01

Memory storage in the brain relies on mechanisms acting on time scales from minutes, for long-term synaptic potentiation, to days, for memory consolidation. During such processes, neural circuits distinguish synapses relevant for forming a long-term storage, which are consolidated, from synapses of short-term storage, which fade. How time scale integration and synaptic differentiation is simultaneously achieved remains unclear. Here we show that synaptic scaling – a slow process usually associated with the maintenance of activity homeostasis – combined with synaptic plasticity may simultaneously achieve both, thereby providing a natural separation of short- from long-term storage. The interaction between plasticity and scaling provides also an explanation for an established paradox where memory consolidation critically depends on the exact order of learning and recall. These results indicate that scaling may be fundamental for stabilizing memories, providing a dynamic link between early and late memory formation processes. PMID:24204240

Synaptic scaling enables dynamically distinct short- and long-term memory formation.

PubMed

Tetzlaff, Christian; Kolodziejski, Christoph; Timme, Marc; Tsodyks, Misha; Wörgötter, Florentin

2013-10-01

Memory storage in the brain relies on mechanisms acting on time scales from minutes, for long-term synaptic potentiation, to days, for memory consolidation. During such processes, neural circuits distinguish synapses relevant for forming a long-term storage, which are consolidated, from synapses of short-term storage, which fade. How time scale integration and synaptic differentiation is simultaneously achieved remains unclear. Here we show that synaptic scaling - a slow process usually associated with the maintenance of activity homeostasis - combined with synaptic plasticity may simultaneously achieve both, thereby providing a natural separation of short- from long-term storage. The interaction between plasticity and scaling provides also an explanation for an established paradox where memory consolidation critically depends on the exact order of learning and recall. These results indicate that scaling may be fundamental for stabilizing memories, providing a dynamic link between early and late memory formation processes.

Circuits and Systems for Low-Power Miniaturized Wireless Sensors

NASA Astrophysics Data System (ADS)

Nagaraju, Manohar

The field of electronic sensors has witnessed a tremendous growth over the last decade particularly with the proliferation of mobile devices. New applications in Internet of Things (IoT), wearable technology, are further expected to fuel the demand for sensors from current numbers in the range of billions to trillions in the next decade. The main challenges for a trillion sensors are continued miniaturization, low-cost and large-scale manufacturing process, and low power consumption. Traditional integration and circuit design techniques in sensor systems are not suitable for applications in smart dust, IoT etc. The first part of this thesis demonstrates an example sensor system for biosignal recording and illustrates the tradeoffs in the design of low-power miniaturized sensors. The different components of the sensor system are integrated at the board level. The second part of the thesis demonstrates fully integrated sensors that enable extreme miniaturization of a sensing system with the sensor element, processing circuitry, a frequency reference for communication and the communication circuitry in a single hermetically sealed die. Design techniques to reduce the power consumption of the sensor interface circuitry at the architecture and circuit level are demonstrated. The principles are used to design sensors for two of the most common physical variables, mass and pressure. A low-power wireless mass and pressure sensor suitable for a wide variety of biological/chemical sensing applications and Tire Pressure Monitoring Systems (TPMS) respectively are demonstrated. Further, the idea of using high-Q resonators for a Voltage Controlled Oscillator (VCO) is proposed and a low-noise, wide bandwidth FBAR-based VCO is presented.

PUZZLE - A program for computer-aided design of printed circuit artwork

NASA Technical Reports Server (NTRS)

Harrell, D. A. W.; Zane, R.

1971-01-01

Program assists in solving spacing problems encountered in printed circuit /PC/ design. It is intended to have maximum use for two-sided PC boards carrying integrated circuits, and also aids design of discrete component circuits.

Open-loop digital frequency multiplier

NASA Technical Reports Server (NTRS)

Moore, R. C.

1977-01-01

Monostable multivibrator is implemented by using digital integrated circuits where multiplier constant is too large for conventional phase-locked-loop integrated circuit. A 400 Hz clock is generated by divide-by-N counter from 1 Hz timing reference.

Extraction of MOS VLSI (Very-Large-Scale-Integrated) Circuit Models Including Critical Interconnect Parasitics.

DTIC Science & Technology

1987-09-01

can be reduced substantially, compared to using numerical methods to model inter - " connect parasitics. Although some accuracy might be lost with...conductor widths and spacings listed in Table 2 1 , have been employed for simulation. In the first set of the simulations, planar dielectric inter ...model, there are no restrictions on the iumber ol diele-iric and conductors. andl the shape of the conductors and the dielectric inter - a.e,, In the

Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates

DOEpatents

Rogers, John A; Cao, Qing; Alam, Muhammad; Pimparkar, Ninad

2015-02-03

The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.

Some Practical Universal Noiseless Coding Techniques

NASA Technical Reports Server (NTRS)

Rice, Robert F.

1994-01-01

Report discusses noiseless data-compression-coding algorithms, performance characteristics and practical consideration in implementation of algorithms in coding modules composed of very-large-scale integrated circuits. Report also has value as tutorial document on data-compression-coding concepts. Coding techniques and concepts in question "universal" in sense that, in principle, applicable to streams of data from variety of sources. However, discussion oriented toward compression of high-rate data generated by spaceborne sensors for lower-rate transmission back to earth.