Semiconductor laser having a non-absorbing passive region with beam guiding

NASA Technical Reports Server (NTRS)

Botez, Dan (Inventor)

1986-01-01

A laser comprises a semiconductor body having a pair of end faces and including an active region comprising adjacent active and guide layers which is spaced a distance from the end face and a passive region comprising adjacent non-absorbing guide and mode control layers which extends between the active region and the end face. The combination of the guide and mode control layers provides a weak positive index waveguide in the lateral direction thereby providing lateral mode control in the passive region between the active region and the end face.

Semiconductor structures having electrically insulating and conducting portions formed from an AlSb-alloy layer

DOEpatents

Spahn, Olga B.; Lear, Kevin L.

1998-01-01

A semiconductor structure. The semiconductor structure comprises a plurality of semiconductor layers formed on a substrate including at least one layer of a III-V compound semiconductor alloy comprising aluminum (Al) and antimony (Sb), with at least a part of the AlSb-alloy layer being chemically converted by an oxidation process to form superposed electrically insulating and electrically conducting portions. The electrically insulating portion formed from the AlSb-alloy layer comprises an oxide of aluminum (e.g. Al.sub.2 O.sub.3), while the electrically conducting portion comprises Sb. A lateral oxidation process allows formation of the superposed insulating and conducting portions below monocrystalline semiconductor layers for forming many different types of semiconductor structures having particular utility for optoelectronic devices such as light-emitting diodes, edge-emitting lasers, vertical-cavity surface-emitting lasers, photodetectors and optical modulators (waveguide and surface normal), and for electronic devices such as heterojunction bipolar transistors, field-effect transistors and quantum-effect devices. The invention is expected to be particularly useful for forming light-emitting devices for use in the 1.3-1.6 .mu.m wavelength range, with the AlSb-alloy layer acting to define an active region of the device and to effectively channel an electrical current therein for efficient light generation.

Multifunctional Organic-Semiconductor Interfacial Layers for Solution-Processed Oxide-Semiconductor Thin-Film Transistor.

PubMed

Kwon, Guhyun; Kim, Keetae; Choi, Byung Doo; Roh, Jeongkyun; Lee, Changhee; Noh, Yong-Young; Seo, SungYong; Kim, Myung-Gil; Kim, Choongik

2017-06-01

The stabilization and control of the electrical properties in solution-processed amorphous-oxide semiconductors (AOSs) is crucial for the realization of cost-effective, high-performance, large-area electronics. In particular, impurity diffusion, electrical instability, and the lack of a general substitutional doping strategy for the active layer hinder the industrial implementation of copper electrodes and the fine tuning of the electrical parameters of AOS-based thin-film transistors (TFTs). In this study, the authors employ a multifunctional organic-semiconductor (OSC) interlayer as a solution-processed thin-film passivation layer and a charge-transfer dopant. As an electrically active impurity blocking layer, the OSC interlayer enhances the electrical stability of AOS TFTs by suppressing the adsorption of environmental gas species and copper-ion diffusion. Moreover, charge transfer between the organic interlayer and the AOS allows the fine tuning of the electrical properties and the passivation of the electrical defects in the AOS TFTs. The development of a multifunctional solution-processed organic interlayer enables the production of low-cost, high-performance oxide semiconductor-based circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Semiconductor laser devices having lateral refractive index tailoring

DOEpatents

Ashby, Carol I. H.; Hadley, G. Ronald; Hohimer, John P.; Owyoung, Adelbert

1990-01-01

A broad-area semiconductor laser diode includes an active lasing region interposed between an upper and a lower cladding layer, the laser diode further comprising structure for controllably varying a lateral refractive index profile of the diode to substantially compensate for an effect of junction heating during operation. In embodiments disclosed the controlling structure comprises resistive heating strips or non-radiative linear junctions disposed parallel to the active region. Another embodiment discloses a multi-layered upper cladding region selectively disordered by implanted or diffused dopant impurities. Still another embodiment discloses an upper cladding layer of variable thickness that is convex in shape and symmetrically disposed about a central axis of the active region. The teaching of the invention is also shown to be applicable to arrays of semiconductor laser diodes.

Monolayer-Mediated Growth of Organic Semiconductor Films with Improved Device Performance.

PubMed

Huang, Lizhen; Hu, Xiaorong; Chi, Lifeng

2015-09-15

Increased interest in wearable and smart electronics is driving numerous research works on organic electronics. The control of film growth and patterning is of great importance when targeting high-performance organic semiconductor devices. In this Feature Article, we summarize our recent work focusing on the growth, crystallization, and device operation of organic semiconductors intermediated by ultrathin organic films (in most cases, only a monolayer). The site-selective growth, modified crystallization and morphology, and improved device performance of organic semiconductor films are demonstrated with the help of the inducing layers, including patterned and uniform Langmuir-Blodgett monolayers, crystalline ultrathin organic films, and self-assembled polymer brush films. The introduction of the inducing layers could dramatically change the diffusion of the organic semiconductors on the surface and the interactions between the active layer with the inducing layer, leading to improved aggregation/crystallization behavior and device performance.

Broadband light-emitting diode

DOEpatents

Fritz, Ian J.; Klem, John F.; Hafich, Michael J.

1998-01-01

A broadband light-emitting diode. The broadband light-emitting diode (LED) comprises a plurality of III-V compound semiconductor layers grown on a semiconductor substrate, with the semiconductor layers including a pair of cladding layers sandwiched about a strained-quantum-well active region having a plurality of different energy bandgaps for generating light in a wavelength range of about 1.3-2 .mu.m. In one embodiment of the present invention, the active region may comprise a first-grown quantum-well layer and a last-grown quantum-well layer that are oppositely strained; whereas in another embodiment of the invention, the active region is formed from a short-period superlattice structure (i.e. a pseudo alloy) comprising alternating thin layers of InGaAs and InGaAlAs. The use a short-period superlattice structure for the active region allows different layers within the active region to be simply and accurately grown by repetitively opening and closing one or more shutters in an MBE growth apparatus to repetitively switch between different growth states therein. The broadband LED may be formed as either a surface-emitting LED or as an edge-emitting LED for use in applications such as chemical sensing, fiber optic gyroscopes, wavelength-division-multiplexed (WDM) fiber-optic data links, and WDM fiber-optic sensor networks for automobiles and aircraft.

Broadband light-emitting diode

DOEpatents

Fritz, I.J.; Klem, J.F.; Hafich, M.J.

1998-07-14

A broadband light-emitting diode is disclosed. The broadband light-emitting diode (LED) comprises a plurality of III-V compound semiconductor layers grown on a semiconductor substrate, with the semiconductor layers including a pair of cladding layers sandwiched about a strained-quantum-well active region having a plurality of different energy bandgaps for generating light in a wavelength range of about 1.3--2 {micro}m. In one embodiment of the present invention, the active region may comprise a first-grown quantum-well layer and a last-grown quantum-well layer that are oppositely strained; whereas in another embodiment of the invention, the active region is formed from a short-period superlattice structure (i.e. a pseudo alloy) comprising alternating thin layers of InGaAs and InGaAlAs. The use a short-period superlattice structure for the active region allows different layers within the active region to be simply and accurately grown by repetitively opening and closing one or more shutters in an MBE growth apparatus to repetitively switch between different growth states therein. The broadband LED may be formed as either a surface-emitting LED or as an edge-emitting LED for use in applications such as chemical sensing, fiber optic gyroscopes, wavelength-divisionmultiplexed (WDM) fiber-optic data links, and WDM fiber-optic sensor networks for automobiles and aircraft. 10 figs.

Infrared emitting device and method

DOEpatents

Kurtz, S.R.; Biefeld, R.M.; Dawson, L.R.; Howard, A.J.; Baucom, K.C.

1997-04-29

The infrared emitting device comprises a III-V compound semiconductor substrate upon which are grown a quantum-well active region having a plurality of quantum-well layers formed of a ternary alloy comprising InAsSb sandwiched between barrier layers formed of a ternary alloy having a smaller lattice constant and a larger energy bandgap than the quantum-well layers. The quantum-well layers are preferably compressively strained to increase the threshold energy for Auger recombination; and a method is provided for determining the preferred thickness for the quantum-well layers. Embodiments of the present invention are described having at least one cladding layer to increase the optical and carrier confinement in the active region, and to provide for waveguiding of the light generated within the active region. Examples have been set forth showing embodiments of the present invention as surface- and edge-emitting light emitting diodes (LEDs), an optically-pumped semiconductor laser, and an electrically-injected semiconductor diode laser. The light emission from each of the infrared emitting devices of the present invention is in the midwave infrared region of the spectrum from about 2 to 6 microns. 8 figs.

Semiconductor structures having electrically insulating and conducting portions formed from an AlSb-alloy layer

DOEpatents

Spahn, O.B.; Lear, K.L.

1998-03-10

The semiconductor structure comprises a plurality of semiconductor layers formed on a substrate including at least one layer of a III-V compound semiconductor alloy comprising aluminum (Al) and antimony (Sb), with at least a part of the AlSb-alloy layer being chemically converted by an oxidation process to form superposed electrically insulating and electrically conducting portions. The electrically insulating portion formed from the AlSb-alloy layer comprises an oxide of aluminum (e.g., Al{sub 2}O{sub 3}), while the electrically conducting portion comprises Sb. A lateral oxidation process allows formation of the superposed insulating and conducting portions below monocrystalline semiconductor layers for forming many different types of semiconductor structures having particular utility for optoelectronic devices such as light-emitting diodes, edge-emitting lasers, vertical-cavity surface-emitting lasers, photodetectors and optical modulators (waveguide and surface normal), and for electronic devices such as heterojunction bipolar transistors, field-effect transistors and quantum-effect devices. The invention is expected to be particularly useful for forming light-emitting devices for use in the 1.3--1.6 {mu}m wavelength range, with the AlSb-alloy layer acting to define an active region of the device and to effectively channel an electrical current therein for efficient light generation. 10 figs.

Visible-wavelength semiconductor lasers and arrays

DOEpatents

Schneider, Jr., Richard P.; Crawford, Mary H.

1996-01-01

A visible semiconductor laser. The visible semiconductor laser includes an InAlGaP active region surrounded by one or more AlGaAs layers on each side, with carbon as the sole p-type dopant. Embodiments of the invention are provided as vertical-cavity surface-emitting lasers (VCSELs) and as edge-emitting lasers (EELs). One or more transition layers comprised of a substantially indium-free semiconductor alloy such as AlAsP, AlGaAsP, or the like may be provided between the InAlGaP active region and the AlGaAS DBR mirrors or confinement layers to improve carrier injection and device efficiency by reducing any band offsets. Visible VCSEL devices fabricated according to the invention with a one-wavelength-thick (1.lambda.) optical cavity operate continuous-wave (cw) with lasing output powers up to 8 mW, and a peak power conversion efficiency of up to 11%.

Infrared nanoantenna apparatus and method for the manufacture thereof

DOEpatents

Peters, David W.; Davids, Paul; Leonhardt, Darin; Kim, Jin K.; Wendt, Joel R.; Klem, John F.

2014-06-10

An exemplary embodiment of the present invention is a photodetector comprising a semiconductor body, a periodically patterned metal nanoantenna disposed on a surface of the semiconductor body, and at least one electrode separate from the nanoantenna. The semiconductor body comprises an active layer in sufficient proximity to the nanoantenna for plasmonic coupling thereto. The nanoantenna is dimensioned to absorb electromagnetic radiation in at least some wavelengths not more than 12 .mu.m that are effective for plasmonic coupling into the active layer. The electrode is part of an electrode arrangement for obtaining a photovoltage or photocurrent in operation under appropriate stimulation.

Novel nano-semiconductor film layer supported nano-Pd Complex Nanostructured Catalyst Pd/Ⓕ-MeOx/AC for High Efficient Selective Hydrogenation of Phenol to Cyclohexanone.

PubMed

Si, Jiaqi; Ouyang, Wenbing; Zhang, Yanji; Xu, Wentao; Zhou, Jicheng

2017-04-28

Supported metal as a type of heterogeneous catalysts are the most widely used in industrial processes. High dispersion of the metal particles of supported catalyst is a key factor in determining the performance of such catalysts. Here we report a novel catalyst Pd/Ⓕ-MeO x /AC with complex nanostructured, Pd nanoparticles supported on the platelike nano-semiconductor film/activated carbon, prepared by the photocatalytic reduction method, which exhibited high efficient catalytic performance for selective hydrogenation of phenol to cyclohexanone. Conversion of phenol achieved up to more than 99% with a lower mole ratio (0.5%) of active components Pd and phenol within 2 h at 70 °C. The synergistic effect of metal nanoparticles and nano-semiconductors support layer and the greatly increasing of contact interface of nano-metal-semiconductors may be responsible for the high efficiency. This work provides a clear demonstration that complex nanostructured catalysts with nano-metal and nano-semiconductor film layer supported on high specific surface AC can yield enhanced catalytic activity and can afford promising approach for developing new supported catalyst.

Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps

PubMed Central

Mei, Yaochuan; Diemer, Peter J.; Niazi, Muhammad R.; Hallani, Rawad K.; Jarolimek, Karol; Day, Cynthia S.; Risko, Chad; Anthony, John E.; Amassian, Aram

2017-01-01

The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms. PMID:28739934

Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps.

PubMed

Mei, Yaochuan; Diemer, Peter J; Niazi, Muhammad R; Hallani, Rawad K; Jarolimek, Karol; Day, Cynthia S; Risko, Chad; Anthony, John E; Amassian, Aram; Jurchescu, Oana D

2017-08-15

The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms.

Semiconductor structure and recess formation etch technique

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Bin; Sun, Min; Palacios, Tomas Apostol

2017-02-14

A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching processmore » stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.« less

Method of making photovoltaic cell

DOEpatents

Cruz-Campa, Jose Luis; Zhou, Xiaowang; Zubia, David

2017-06-20

A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.

Multi-junction solar cell device

DOEpatents

Friedman, Daniel J.; Geisz, John F.

2007-12-18

A multi-junction solar cell device (10) is provided. The multi-junction solar cell device (10) comprises either two or three active solar cells connected in series in a monolithic structure. The multi-junction device (10) comprises a bottom active cell (20) having a single-crystal silicon substrate base and an emitter layer (23). The multi-junction device (10) further comprises one or two subsequent active cells each having a base layer (32) and an emitter layer (23) with interconnecting tunnel junctions between each active cell. At least one layer that forms each of the top and middle active cells is composed of a single-crystal III-V semiconductor alloy that is substantially lattice-matched to the silicon substrate (22). The polarity of the active p-n junction cells is either p-on-n or n-on-p. The present invention further includes a method for substantially lattice matching single-crystal III-V semiconductor layers with the silicon substrate (22) by including boron and/or nitrogen in the chemical structure of these layers.

Optically switched graphene/4H-SiC junction bipolar transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chandrashekhar, MVS; Sudarshan, Tangali S.; Omar, Sabih U.

A bi-polar device is provided, along with methods of making the same. The bi-polar device can include a semiconductor substrate doped with a first dopant, a semiconductor layer on the first surface of the semiconductor substrate, and a Schottky barrier layer on the semiconductor layer. The method of forming a bi-polar device can include: forming a semiconductor layer on a first surface of a semiconductor substrate, where the semiconductor substrate comprises a first dopant and where the semiconductor layer comprises a second dopant that has an opposite polarity than the first dopant; and forming a Schottky barrier layer on amore » first portion of the semiconductor layer while leaving a second portion of the semiconductor layer exposed.« less

Gain in three-dimensional metamaterials utilizing semiconductor quantum structures

NASA Astrophysics Data System (ADS)

Schwaiger, Stephan; Klingbeil, Matthias; Kerbst, Jochen; Rottler, Andreas; Costa, Ricardo; Koitmäe, Aune; Bröll, Markus; Heyn, Christian; Stark, Yuliya; Heitmann, Detlef; Mendach, Stefan

2011-10-01

We demonstrate gain in a three-dimensional metal/semiconductor metamaterial by the integration of optically active semiconductor quantum structures. The rolling-up of a metallic structure on top of strained semiconductor layers containing a quantum well allows us to achieve a tightly bent superlattice consisting of alternating layers of lossy metallic and amplifying gain material. We show that the transmission through the superlattice can be enhanced by exciting the quantum well optically under both pulsed or continuous wave excitation. This points out that our structures can be used as a starting point for arbitrary three-dimensional metamaterials including gain.

Infrared emitting device and method

DOEpatents

Kurtz, Steven R.; Biefeld, Robert M.; Dawson, L. Ralph; Howard, Arnold J.; Baucom, Kevin C.

1997-01-01

An infrared emitting device and method. The infrared emitting device comprises a III-V compound semiconductor substrate upon which are grown a quantum-well active region having a plurality of quantum-well layers formed of a ternary alloy comprising InAsSb sandwiched between barrier layers formed of a ternary alloy having a smaller lattice constant and a larger energy bandgap than the quantum-well layers. The quantum-well layers are preferably compressively strained to increase the threshold energy for Auger recombination; and a method is provided for determining the preferred thickness for the quantum-well layers. Embodiments of the present invention are described having at least one cladding layer to increase the optical and carrier confinement in the active region, and to provide for waveguiding of the light generated within the active region. Examples have been set forth showing embodiments of the present invention as surface- and edge-emitting light emitting diodes (LEDs), an optically-pumped semiconductor laser, and an electrically-injected semiconductor diode laser. The light emission from each of the infrared emitting devices of the present invention is in the midwave infrared region of the spectrum from about 2 to 6 microns.

Photovoltaic cell with nano-patterned substrate

DOEpatents

Cruz-Campa, Jose Luis; Zhou, Xiaowang; Zubia, David

2016-10-18

A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.

Method of making silicon on insalator material using oxygen implantation

DOEpatents

Hite, Larry R.; Houston, Ted; Matloubian, Mishel

1989-01-01

The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth

DOEpatents

Fan, John C. C.; Tsaur, Bor-Yeu; Gale, Ronald P.; Davis, Frances M.

1992-02-25

Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth

DOEpatents

Fan, John C. C.; Tsaur, Bor-Yeu; Gale, Ronald P.; Davis, Frances M.

1986-12-30

Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dahal, Rajendra P.; Bhat, Ishwara B.; Chow, Tat-Sing

Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.

Visible-wavelength semiconductor lasers and arrays

DOEpatents

Schneider, R.P. Jr.; Crawford, M.H.

1996-09-17

The visible semiconductor laser includes an InAlGaP active region surrounded by one or more AlGaAs layers on each side, with carbon as the sole p-type dopant. Embodiments of the invention are provided as vertical-cavity surface-emitting lasers (VCSELs) and as edge-emitting lasers (EELs). One or more transition layers comprised of a substantially indium-free semiconductor alloy such as AlAsP, AlGaAsP, or the like may be provided between the InAlGaP active region and the AlGaAS DBR mirrors or confinement layers to improve carrier injection and device efficiency by reducing any band offsets. Visible VCSEL devices fabricated according to the invention with a one-wavelength-thick (1{lambda}) optical cavity operate continuous-wave (cw) with lasing output powers up to 8 mW, and a peak power conversion efficiency of up to 11%. 5 figs.

Improved Stability and Performance of Visible Photoelectrochemical Water Splitting on Solution-Processed Organic Semiconductor Thin Films by Ultrathin Metal Oxide Passivation

DOE PAGES

Wang, Lei; Yan, Danhua; Shaffer, David W.; ...

2017-12-27

Solution-processable organic semiconductors have potentials as visible photoelectrochemical (PEC) water splitting photoelectrodes due to their tunable small band gap and electronic energy levels, but they are typically limited by poor stability and photocatalytic activity. In this study, we demonstrate the direct visible PEC water oxidation on solution-processed organic semiconductor thin films with improved stability and performance by ultrathin metal oxide passivation layers. N-type fullerene-derivative thin films passivated by sub-2 nm ZnO via atomic layer deposition enabled the visible PEC water oxidation at wavelengths longer than 600 nm in harsh alkaline electrolyte environments with up to 30 μA/cm 2 photocurrents atmore » the thermodynamic water-oxidation equilibrium potential and the photoanode half-lifetime extended to ~1000 s. The systematic investigation reveals the enhanced water oxidation catalytic activity afforded by ZnO passivation and the charge tunneling governing the hole transfer through passivation layers. Further enhanced PEC performances were realized by improving the bottom ohmic contact to the organic semiconductor, achieving ~60 μA/cm 2 water oxidation photocurrent at the equilibrium potential, the highest values reported for organic semiconductor thin films to our knowledge. The improved stability and performance of passivated organic photoelectrodes and discovered design rationales provide useful guidelines for realizing the stable visible solar PEC water splitting based on organic semiconductor thin films.« less

Improved Stability and Performance of Visible Photoelectrochemical Water Splitting on Solution-Processed Organic Semiconductor Thin Films by Ultrathin Metal Oxide Passivation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Lei; Yan, Danhua; Shaffer, David W.

Solution-processable organic semiconductors have potentials as visible photoelectrochemical (PEC) water splitting photoelectrodes due to their tunable small band gap and electronic energy levels, but they are typically limited by poor stability and photocatalytic activity. In this study, we demonstrate the direct visible PEC water oxidation on solution-processed organic semiconductor thin films with improved stability and performance by ultrathin metal oxide passivation layers. N-type fullerene-derivative thin films passivated by sub-2 nm ZnO via atomic layer deposition enabled the visible PEC water oxidation at wavelengths longer than 600 nm in harsh alkaline electrolyte environments with up to 30 μA/cm 2 photocurrents atmore » the thermodynamic water-oxidation equilibrium potential and the photoanode half-lifetime extended to ~1000 s. The systematic investigation reveals the enhanced water oxidation catalytic activity afforded by ZnO passivation and the charge tunneling governing the hole transfer through passivation layers. Further enhanced PEC performances were realized by improving the bottom ohmic contact to the organic semiconductor, achieving ~60 μA/cm 2 water oxidation photocurrent at the equilibrium potential, the highest values reported for organic semiconductor thin films to our knowledge. The improved stability and performance of passivated organic photoelectrodes and discovered design rationales provide useful guidelines for realizing the stable visible solar PEC water splitting based on organic semiconductor thin films.« less

Architectures and criteria for the design of high efficiency organic photovoltaic cells

DOEpatents

Rand, Barry; Forrest, Stephen R; Burk, Diana Pendergrast

2015-03-24

An organic photovoltaic cell includes an anode and a cathode, and a plurality of organic semiconductor layers between the anode and the cathode. At least one of the anode and the cathode is transparent. Each two adjacent layers of the plurality of organic semiconductor layers are in direct contact. The plurality of organic semiconductor layers includes an intermediate layer consisting essentially of a photoconductive material, and two sets of at least three layers. A first set of at least three layers is between the intermediate layer and the anode. Each layer of the first set consists essentially of a different organic semiconductor material having a higher LUMO and a higher HOMO, relative to the material of an adjacent layer of the plurality of organic semiconductor layers closer to the cathode. A second set of at least three layers is between the intermediate layer and the cathode. Each layer of the second set consists essentially of a different organic semiconductor material having a lower LUMO and a lower HOMO, relative to the material of an adjacent layer of the plurality of organic semiconductor layers closer to the anode.

Method of producing strained-layer semiconductor devices via subsurface-patterning

DOEpatents

Dodson, Brian W.

1993-01-01

A method is described for patterning subsurface features in a semiconductor device, wherein the semiconductor device includes an internal strained layer. The method comprises creating a pattern of semiconductor material over the semiconductor device, the semiconductor material having a predetermined thickness which stabilizes areas of the strained semiconductor layer that lie beneath the pattern. Subsequently, a heating step is applied to the semiconductor device to cause a relaxation in areas of the strained layer which do not lie beneath the semiconductor material pattern, whereby dislocations result in the relaxed areas and impair electrical transport therethrough.

Method of transferring a thin crystalline semiconductor layer

DOEpatents

Nastasi, Michael A [Sante Fe, NM; Shao, Lin [Los Alamos, NM; Theodore, N David [Mesa, AZ

2006-12-26

A method for transferring a thin semiconductor layer from one substrate to another substrate involves depositing a thin epitaxial monocrystalline semiconductor layer on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the thin semiconductor layer is bonded to a second substrate and the thin layer is separated away at the interface, which results in transferring the thin epitaxial semiconductor layer from one substrate to the other substrate.

Variable temperature semiconductor film deposition

DOEpatents

Li, X.; Sheldon, P.

1998-01-27

A method of depositing a semiconductor material on a substrate is disclosed. The method sequentially comprises (a) providing the semiconductor material in a depositable state such as a vapor for deposition on the substrate; (b) depositing the semiconductor material on the substrate while heating the substrate to a first temperature sufficient to cause the semiconductor material to form a first film layer having a first grain size; (c) continually depositing the semiconductor material on the substrate while cooling the substrate to a second temperature sufficient to cause the semiconductor material to form a second film layer deposited on the first film layer and having a second grain size smaller than the first grain size; and (d) raising the substrate temperature, while either continuing or not continuing to deposit semiconductor material to form a third film layer, to thereby anneal the film layers into a single layer having favorable efficiency characteristics in photovoltaic applications. A preferred semiconductor material is cadmium telluride deposited on a glass/tin oxide substrate already having thereon a film layer of cadmium sulfide.

Variable temperature semiconductor film deposition

DOEpatents

Li, Xiaonan; Sheldon, Peter

1998-01-01

A method of depositing a semiconductor material on a substrate. The method sequentially comprises (a) providing the semiconductor material in a depositable state such as a vapor for deposition on the substrate; (b) depositing the semiconductor material on the substrate while heating the substrate to a first temperature sufficient to cause the semiconductor material to form a first film layer having a first grain size; (c) continually depositing the semiconductor material on the substrate while cooling the substrate to a second temperature sufficient to cause the semiconductor material to form a second film layer deposited on the first film layer and having a second grain size smaller than the first grain size; and (d) raising the substrate temperature, while either continuing or not continuing to deposit semiconductor material to form a third film layer, to thereby anneal the film layers into a single layer having favorable efficiency characteristics in photovoltaic applications. A preferred semiconductor material is cadmium telluride deposited on a glass/tin oxide substrate already having thereon a film layer of cadmium sulfide.

On a chaotic potential at the surface of a compensated semiconductor under conditions of the self-assembly of electrically active defects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bondarenko, V. B., E-mail: enter@spbstu.ru; Filimonov, A. V.

2015-09-15

Natural irregularities of the electric potential on the surface of a semiconductor under conditions of the partial self-assembly of electrically active defects, i.e., on the formation of donor–acceptor pairs in depletion layers, are studied. The amplitude and character of the spatial distribution of the chaotic potential on the surface of a semiconductor in the cases of localized and delocalized states are determined. The dependence of the amplitude of the chaotic potential on the degree of compensation of the semiconductor is obtained.

Electroless silver plating of the surface of organic semiconductors.

PubMed

Campione, Marcello; Parravicini, Matteo; Moret, Massimo; Papagni, Antonio; Schröter, Bernd; Fritz, Torsten

2011-10-04

The integration of nanoscale processes and devices demands fabrication routes involving rapid, cost-effective steps, preferably carried out under ambient conditions. The realization of the metal/organic semiconductor interface is one of the most demanding steps of device fabrication, since it requires mechanical and/or thermal treatments which increment costs and are often harmful in respect to the active layer. Here, we provide a microscopic analysis of a room temperature, electroless process aimed at the deposition of a nanostructured metallic silver layer with controlled coverage atop the surface of single crystals and thin films of organic semiconductors. This process relies on the reaction of aqueous AgF solutions with the nonwettable crystalline surface of donor-type organic semiconductors. It is observed that the formation of a uniform layer of silver nanoparticles can be accomplished within 20 min contact time. The electrical characterization of two-terminal devices performed before and after the aforementioned treatment shows that the metal deposition process is associated with a redox reaction causing the p-doping of the semiconductor. © 2011 American Chemical Society

Suppression of planar defects in the molecular beam epitaxy of GaAs/ErAs/GaAs heterostructures

NASA Astrophysics Data System (ADS)

Crook, Adam M.; Nair, Hari P.; Ferrer, Domingo A.; Bank, Seth R.

2011-08-01

We present a growth method that overcomes the mismatch in rotational symmetry of ErAs and conventional III-V semiconductors, allowing for epitaxially integrated semimetal/semiconductor heterostructures. Transmission electron microscopy and reflection high-energy electron diffraction reveal defect-free overgrowth of ErAs layers, consisting of >2× the total amount of ErAs that can be embedded with conventional layer-by-layer growth methods. We utilize epitaxial ErAs nanoparticles, overgrown with GaAs, as a seed to grow full films of ErAs. Growth proceeds by diffusion of erbium atoms through the GaAs spacer, which remains registered to the underlying substrate, preventing planar defect formation during subsequent GaAs growth. This growth method is promising for metal/semiconductor heterostructures that serve as embedded Ohmic contacts to epitaxial layers and epitaxially integrated active plasmonic devices.

Semiconductor nanocrystal-based phagokinetic tracking

DOEpatents

Alivisatos, A Paul; Larabell, Carolyn A; Parak, Wolfgang J; Le Gros, Mark; Boudreau, Rosanne

2014-11-18

Methods for determining metabolic properties of living cells through the uptake of semiconductor nanocrystals by cells. Generally the methods require a layer of neutral or hydrophilic semiconductor nanocrystals and a layer of cells seeded onto a culture surface and changes in the layer of semiconductor nanocrystals are detected. The observed changes made to the layer of semiconductor nanocrystals can be correlated to such metabolic properties as metastatic potential, cell motility or migration.

Group I-III-VI.sub.2 semiconductor films for solar cell application

DOEpatents

Basol, Bulent M.; Kapur, Vijay K.

1991-01-01

This invention relates to an improved thin film solar cell with excellent electrical and mechanical integrity. The device comprises a substrate, a Group I-III-VI.sub.2 semiconductor absorber layer and a transparent window layer. The mechanical bond between the substrate and the Group I-III-VI.sub.2 semiconductor layer is enhanced by an intermediate layer between the substrate and the Group I-III-VI.sub.2 semiconductor film being grown. The intermediate layer contains tellurium or substitutes therefor, such as Se, Sn, or Pb. The intermediate layer improves the morphology and electrical characteristics of the Group I-III-VI.sub.2 semiconductor layer.

Buried Porous Silicon-Germanium Layers in Monocrystalline Silicon Lattices

NASA Technical Reports Server (NTRS)

Fathauer, Robert W. (Inventor); George, Thomas (Inventor); Jones, Eric W. (Inventor)

1998-01-01

Monocrystalline semiconductor lattices with a buried porous semiconductor layer having different chemical composition is discussed and monocrystalline semiconductor superlattices with a buried porous semiconductor layers having different chemical composition than that of its monocrystalline semiconductor superlattice are discussed. Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si-Ge layers followed by patterning into mesa structures. The mesa structures are strain etched resulting in porosification of the Si-Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si-Ge layers produced in a similar manner emitted visible light at room temperature.

Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction

DOEpatents

Tauke-Pedretti, Anna; Nielson, Gregory N; Cederberg, Jeffrey G; Cruz-Campa, Jose Luis

2015-05-12

A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.

Strained layer Fabry-Perot device

DOEpatents

Brennan, Thomas M.; Fritz, Ian J.; Hammons, Burrell E.

1994-01-01

An asymmetric Fabry-Perot reflectance modulator (AFPM) consists of an active region between top and bottom mirrors, the bottom mirror being affixed to a substrate by a buffer layer. The active region comprises a strained-layer region having a bandgap and thickness chosen for resonance at the Fabry-Perot frequency. The mirrors are lattice matched to the active region, and the buffer layer is lattice matched to the mirror at the interface. The device operates at wavelengths of commercially available semiconductor lasers.

Conductive layer for biaxially oriented semiconductor film growth

DOEpatents

Findikoglu, Alp T.; Matias, Vladimir

2007-10-30

A conductive layer for biaxially oriented semiconductor film growth and a thin film semiconductor structure such as, for example, a photodetector, a photovoltaic cell, or a light emitting diode (LED) that includes a crystallographically oriented semiconducting film disposed on the conductive layer. The thin film semiconductor structure includes: a substrate; a first electrode deposited on the substrate; and a semiconducting layer epitaxially deposited on the first electrode. The first electrode includes a template layer deposited on the substrate and a buffer layer epitaxially deposited on the template layer. The template layer includes a first metal nitride that is electrically conductive and has a rock salt crystal structure, and the buffer layer includes a second metal nitride that is electrically conductive. The semiconducting layer is epitaxially deposited on the buffer layer. A method of making such a thin film semiconductor structure is also described.

Field-effect P-N junction

DOEpatents

Regan, William; Zettl, Alexander

2015-05-05

This disclosure provides systems, methods, and apparatus related to field-effect p-n junctions. In one aspect, a device includes an ohmic contact, a semiconductor layer disposed on the ohmic contact, at least one rectifying contact disposed on the semiconductor layer, a gate including a layer disposed on the at least one rectifying contact and the semiconductor layer and a gate contact disposed on the layer. A lateral width of the rectifying contact is less than a semiconductor depletion width of the semiconductor layer. The gate contact is electrically connected to the ohmic contact to create a self-gating feedback loop that is configured to maintain a gate electric field of the gate.

Organic photosensitive cells grown on rough electrode with nano-scale morphology control

DOEpatents

Yang, Fan [Piscataway, NJ; Forrest, Stephen R [Ann Arbor, MI

2011-06-07

An optoelectronic device and a method for fabricating the optoelectronic device includes a first electrode disposed on a substrate, an exposed surface of the first electrode having a root mean square roughness of at least 30 nm and a height variation of at least 200 nm, the first electrode being transparent. A conformal layer of a first organic semiconductor material is deposited onto the first electrode by organic vapor phase deposition, the first organic semiconductor material being a small molecule material. A layer of a second organic semiconductor material is deposited over the conformal layer. At least some of the layer of the second organic semiconductor material directly contacts the conformal layer. A second electrode is deposited over the layer of the second organic semiconductor material. The first organic semiconductor material is of a donor-type or an acceptor-type relative to the second organic semiconductor material, which is of the other material type.

Intracavity double diode structures with GaInP barrier layers for thermophotonic cooling

NASA Astrophysics Data System (ADS)

Tiira, Jonna; Radevici, Ivan; Haggren, Tuomas; Hakkarainen, Teemu; Kivisaari, Pyry; Lyytikäinen, Jari; Aho, Arto; Tukiainen, Antti; Guina, Mircea; Oksanen, Jani

2017-02-01

Optical cooling of semiconductors has recently been demonstrated both for optically pumped CdS nanobelts and for electrically injected GaInAsSb LEDs at very low powers. To enable cooling at larger power and to understand and overcome the main obstacles in optical cooling of conventional semiconductor structures, we study thermophotonic (TPX) heat transport in cavity coupled light emitters. Our structures consist of a double heterojunction (DHJ) LED with a GaAs active layer and a corresponding DHJ or a p-n-homojunction photodiode, enclosed within a single semiconductor cavity to eliminate the light extraction challenges. Our presently studied double diode structures (DDS) use GaInP barriers around the GaAs active layer instead of the AlGaAs barriers used in our previous structures. We characterize our updated double diode structures by four point probe IV- measurements and measure how the material modifications affect the recombination parameters and coupling quantum efficiencies in the structures. The coupling quantum efficiency of the new devices with InGaP barrier layers is found to be approximately 10 % larger than for the structures with AlGaAs barriers at the point of maximum efficiency.

Numerical investigation of metal-semiconductor-insulator-semiconductor passivated hole contacts based on atomic layer deposited AlO x

NASA Astrophysics Data System (ADS)

Ke, Cangming; Xin, Zheng; Ling, Zhi Peng; Aberle, Armin G.; Stangl, Rolf

2017-08-01

Excellent c-Si tunnel layer surface passivation has been obtained recently in our lab, using atomic layer deposited aluminium oxide (ALD AlO x ) in the tunnel layer regime of 0.9 to 1.5 nm, investigated to be applied for contact passivation. Using the correspondingly measured interface properties, this paper compares the theoretical collection efficiency of a conventional metal-semiconductor (MS) contact on diffused p+ Si to a metal-semiconductor-insulator-semiconductor (MSIS) contact on diffused p+ Si or on undoped n-type c-Si. The influences of (1) the tunnel layer passivation quality at the tunnel oxide interface (Q f and D it), (2) the tunnel layer thickness and the electron and hole tunnelling mass, (3) the tunnel oxide material, and (4) the semiconductor capping layer material properties are investigated numerically by evaluation of solar cell efficiency, open-circuit voltage, and fill factor.

Method for removing semiconductor layers from salt substrates

DOEpatents

Shuskus, Alexander J.; Cowher, Melvyn E.

1985-08-27

A method is described for removing a CVD semiconductor layer from an alkali halide salt substrate following the deposition of the semiconductor layer. The semiconductor-substrate combination is supported on a material such as tungsten which is readily wet by the molten alkali halide. The temperature of the semiconductor-substrate combination is raised to a temperature greater than the melting temperature of the substrate but less than the temperature of the semiconductor and the substrate is melted and removed from the semiconductor by capillary action of the wettable support.

Alpha voltaic batteries and methods thereof

NASA Technical Reports Server (NTRS)

Jenkins, Phillip (Inventor); Scheiman, David (Inventor); Castro, Stephanie (Inventor); Raffaelle, Ryne P. (Inventor); Wilt, David (Inventor); Chubb, Donald (Inventor)

2011-01-01

An alpha voltaic battery includes at least one layer of a semiconductor material comprising at least one p/n junction, at least one absorption and conversion layer on the at least one layer of semiconductor layer, and at least one alpha particle emitter. The absorption and conversion layer prevents at least a portion of alpha particles from the alpha particle emitter from damaging the p/n junction in the layer of semiconductor material. The absorption and conversion layer also converts at least a portion of energy from the alpha particles into electron-hole pairs for collection by the one p/n junction in the layer of semiconductor material.

Controlled growth of larger heterojunction interface area for organic photosensitive devices

DOEpatents

Yang, Fan [Somerset, NJ; Forrest, Stephen R [Ann Arbor, MI

2009-12-29

An optoelectronic device and a method of fabricating a photosensitive optoelectronic device includes depositing a first organic semiconductor material on a first electrode to form a continuous first layer having protrusions, a side of the first layer opposite the first electrode having a surface area at least three times greater than an underlying lateral cross-sectional area; depositing a second organic semiconductor material directly on the first layer to form a discontinuous second layer, portions of the first layer remaining exposed; depositing a third organic semiconductor material directly on the second layer to form a discontinuous third layer, portions of at least the second layer remaining exposed; depositing a fourth organic semiconductor material on the third layer to form a continuous fourth layer, filling any exposed gaps and recesses in the first, second, and third layers; and depositing a second electrode on the fourth layer, wherein at least one of the first electrode and the second electrode is transparent, and the first and third organic semiconductor materials are both of a donor-type or an acceptor-type relative to second and fourth organic semiconductor materials, which are of the other material type.

High efficiency, low cost, thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

2001-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

1999-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

Semiconductor films on flexible iridium substrates

DOEpatents

Goyal, Amit

2005-03-29

A laminate semiconductor article includes a flexible substrate, an optional biaxially textured oxide buffer system on the flexible substrate, a biaxially textured Ir-based buffer layer on the substrate or the buffer system, and an epitaxial layer of a semiconductor. Ir can serve as a substrate with an epitaxial layer of a semiconductor thereon.

Circular electrode geometry metal-semiconductor-metal photodetectors

NASA Technical Reports Server (NTRS)

Mcaddo, James A. (Inventor); Towe, Elias (Inventor); Bishop, William L. (Inventor); Wang, Liang-Guo (Inventor)

1994-01-01

The invention comprises a high speed, metal-semiconductor-metal photodetector which comprises a pair of generally circular, electrically conductive electrodes formed on an optically active semiconductor layer. Various embodiments of the invention include a spiral, intercoiled electrode geometry and an electrode geometry comprised of substantially circular, concentric electrodes which are interposed. These electrode geometries result in photodetectors with lower capacitances, dark currents and lower inductance which reduces the ringing seen in the optical pulse response.

Light emitting diode with porous SiC substrate and method for fabricating

DOEpatents

Li, Ting; Ibbetson, James; Keller, Bernd

2005-12-06

A method and apparatus for forming a porous layer on the surface of a semiconductor material wherein an electrolyte is provided and is placed in contact with one or more surfaces of a layer of semiconductor material. The electrolyte is heated and a bias is introduced across said electrolyte and the semiconductor material causing a current to flow between the electrolyte and the semiconductor material. The current forms a porous layer on the one or more surfaces of the semiconductor material in contact with the electrolyte. The semiconductor material with its porous layer can serve as a substrate for a light emitter. A semiconductor emission region can be formed on the substrate. The emission region is capable of emitting light omnidirectionally in response to a bias, with the porous layer enhancing extraction of the emitting region light passing through the substrate.

Photovoltaic healing of non-uniformities in semiconductor devices

DOEpatents

Karpov, Victor G.; Roussillon, Yann; Shvydka, Diana; Compaan, Alvin D.; Giolando, Dean M.

2006-08-29

A method of making a photovoltaic device using light energy and a solution to normalize electric potential variations in the device. A semiconductor layer having nonuniformities comprising areas of aberrant electric potential deviating from the electric potential of the top surface of the semiconductor is deposited onto a substrate layer. A solution containing an electrolyte, at least one bonding material, and positive and negative ions is applied over the top surface of the semiconductor. Light energy is applied to generate photovoltage in the semiconductor, causing a redistribution of the ions and the bonding material to the areas of aberrant electric potential. The bonding material selectively bonds to the nonuniformities in a manner such that the electric potential of the nonuniformities is normalized relative to the electric potential of the top surface of the semiconductor layer. A conductive electrode layer is then deposited over the top surface of the semiconductor layer.

Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates

DOEpatents

Norman, Andrew G; Ptak, Aaron J

2013-08-13

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

Intermediate-band photosensitive device with quantum dots embedded in energy fence barrier

DOEpatents

Forrest, Stephen R.; Wei, Guodan

2010-07-06

A plurality of layers of a first semiconductor material and a plurality of dots-in-a-fence barriers disposed in a stack between a first electrode and a second electrode. Each dots-in-a-fence barrier consists essentially of a plurality of quantum dots of a second semiconductor material embedded between and in direct contact with two layers of a third semiconductor material. Wave functions of the quantum dots overlap as at least one intermediate band. The layers of the third semiconductor material are arranged as tunneling barriers to require a first electron and/or a first hole in a layer of the first material to perform quantum mechanical tunneling to reach the second material within a respective quantum dot, and to require a second electron and/or a second hole in a layer of the first semiconductor material to perform quantum mechanical tunneling to reach another layer of the first semiconductor material.

TiOx-based thin-film transistors prepared by femtosecond laser pre-annealing

NASA Astrophysics Data System (ADS)

Shan, Fei; Kim, Sung-Jin

2018-02-01

We report on thin-film transistors (TFTs) based on titanium oxide (TiOx) prepared using femtosecond laser pre-annealing for electrical application of n-type channel oxide transparent TFTs. Amorphous TFTs using TiOx semiconductors as an active layer have a low-temperature process and show remarkable electrical performance. And the femtosecond laser pre-annealing process has greater flexibility and development space for semiconductor production activity, with a fast preparation method. TFTs with a TiOx semiconductor pre-annealed via femtosecond laser at 3 W have a pinhole-free and smooth surface without crystal grains.

Energy resolution in semiconductor gamma radiation detectors using heterojunctions and methods of use and preparation thereof

DOEpatents

Nikolic, Rebecca J.; Conway, Adam M.; Nelson, Art J.; Payne, Stephen A.

2012-09-04

In one embodiment, a system comprises a semiconductor gamma detector material and a hole blocking layer adjacent the gamma detector material, the hole blocking layer resisting passage of holes therethrough. In another embodiment, a system comprises a semiconductor gamma detector material, and an electron blocking layer adjacent the gamma detector material, the electron blocking layer resisting passage of electrons therethrough, wherein the electron blocking layer comprises undoped HgCdTe. In another embodiment, a method comprises forming a hole blocking layer adjacent a semiconductor gamma detector material, the hole blocking layer resisting passage of holes therethrough. Additional systems and methods are also presented.

Semiconductor light-emitting devices having concave microstructures providing improved light extraction efficiency and method for producing same

DOEpatents

Tansu, Nelson; Gilchrist, James F; Ee, Yik-Khoon; Kumnorkaew, Pisist

2013-11-19

A conventional semiconductor LED is modified to include a microlens layer over its light-emitting surface. The LED may have an active layer including at least one quantum well layer of InGaN and GaN. The microlens layer includes a plurality of concave microstructures that cause light rays emanating from the LED to diffuse outwardly, leading to an increase in the light extraction efficiency of the LED. The concave microstructures may be arranged in a substantially uniform array, such as a close-packed hexagonal array. The microlens layer is preferably constructed of curable material, such as polydimethylsiloxane (PDMS), and is formed by soft-lithography imprinting by contacting fluid material of the microlens layer with a template bearing a monolayer of homogeneous microsphere crystals, to cause concave impressions, and then curing the material to fix the concave microstructures in the microlens layer and provide relatively uniform surface roughness.

Lattice matched semiconductor growth on crystalline metallic substrates

DOEpatents

Norman, Andrew G; Ptak, Aaron J; McMahon, William E

2013-11-05

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, B.L.

1999-04-27

A semiconductor device is described having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer. 9 figs.

Exchanging Ohmic Losses in Metamaterial Absorbers with Useful Optical Absorption for Photovoltaics

PubMed Central

Vora, Ankit; Gwamuri, Jephias; Pala, Nezih; Kulkarni, Anand; Pearce, Joshua M.; Güney, Durdu Ö.

2014-01-01

Using metamaterial absorbers, we have shown that metallic layers in the absorbers do not necessarily constitute undesired resistive heating problem for photovoltaics. Tailoring the geometric skin depth of metals and employing the natural bulk absorbance characteristics of the semiconductors in those absorbers can enable the exchange of undesired resistive losses with the useful optical absorbance in the active semiconductors. Thus, Ohmic loss dominated metamaterial absorbers can be converted into photovoltaic near-perfect absorbers with the advantage of harvesting the full potential of light management offered by the metamaterial absorbers. Based on experimental permittivity data for indium gallium nitride, we have shown that between 75%–95% absorbance can be achieved in the semiconductor layers of the converted metamaterial absorbers. Besides other metamaterial and plasmonic devices, our results may also apply to photodectors and other metal or semiconductor based optical devices where resistive losses and power consumption are important pertaining to the device performance. PMID:24811322

Effect of active-layer composition and structure on device performance of coplanar top-gate amorphous oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Yue, Lan; Meng, Fanxin; Chen, Jiarong

2018-01-01

The thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) active layer were prepared by dip coating method. The dependence of properties of TFTs on the active-layer composition and structure was investigated. The results indicate that Al atoms acted as a carrier suppressor in IZO films. Meanwhile, it was found that the on/off current ratio (I on/off) of TFT was improved by embedding a high-resistivity AIZO layer between the low-resistivity AIZO layer and gate insulator. The improvement in I on/off was attributed to the decrease in off-state current of double-active-layer TFT due to an increase in the active-layer resistance and the contact resistance between active layer and source/drain electrode. Moreover, on-state current and threshold voltage (V th) can be mainly controlled through thickness and Al content of the low-resistivity AIZO layer. In addition, the saturation mobility (μ sat) of TFTs was improved with reducing the size of channel width or/and length, which was attributed to the decrease in trap states in the semiconductor and at the semiconductor/gate-insulator interface with the smaller channel width or/and shorter channel length. Thus, we can demonstrate excellent TFTs via the design of active-layer composition and structure by utilizing a low cost solution-processed method. The resulting TFT, operating in enhancement mode, has a high μ sat of 14.16 cm2 V-1 s-1, a small SS of 0.40 V/decade, a close-to-zero V th of 0.50 V, and I on/off of more than 105.

Thin film photovoltaic device with multilayer substrate

DOEpatents

Catalano, Anthony W.; Bhushan, Manjul

1984-01-01

A thin film photovoltaic device which utilizes at least one compound semiconductor layer chosen from Groups IIB and VA of the Periodic Table is formed on a multilayer substrate The substrate includes a lowermost support layer on which all of the other layers of the device are formed. Additionally, an uppermost carbide or silicon layer is adjacent to the semiconductor layer. Below the carbide or silicon layer is a metal layer of high conductivity and expansion coefficient equal to or slightly greater than that of the semiconductor layer.

Electroluminescent devices formed using semiconductor nanocrystals as an electron transport media and method of making such electroluminescent devices

DOEpatents

Alivisatos, A. Paul; Colvin, Vickie

1996-01-01

An electroluminescent device is described, as well as a method of making same, wherein the device is characterized by a semiconductor nanocrystal electron transport layer capable of emitting visible light in response to a voltage applied to the device. The wavelength of the light emitted by the device may be changed by changing either the size or the type of semiconductor nanocrystals used in forming the electron transport layer. In a preferred embodiment the device is further characterized by the capability of emitting visible light of varying wavelengths in response to changes in the voltage applied to the device. The device comprises a hole processing structure capable of injecting and transporting holes, and usually comprising a hole injecting layer and a hole transporting layer; an electron transport layer in contact with the hole processing structure and comprising one or more layers of semiconductor nanocrystals; and an electron injecting layer in contact with the electron transport layer for injecting electrons into the electron transport layer. The capability of emitting visible light of various wavelengths is principally based on the variations in voltage applied thereto, but the type of semiconductor nanocrystals used and the size of the semiconductor nanocrystals in the layers of semiconductor nanometer crystals may also play a role in color change, in combination with the change in voltage.

Tunnel barrier schottky

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chu, Rongming; Cao, Yu; Li, Zijian

2018-02-20

A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.

Determination of the effective refractive index spectrum of a quantum-well semiconductor laser diode from the measured modal gain spectrum

NASA Astrophysics Data System (ADS)

Wu, Linzhang; Tian, Wei; Gao, Feng

2004-09-01

This paper presents a self-consistent method to directly determine the effective refractive-index spectrum of a semiconductor quantum-well (QW) laser diode from the measured modal gain spectrum for a given current. The dispersion spectra of the optical waveguide confinement factor and the strongly carrier-density-dependent refractive index of the QW active layer of the test laser are also accurately obtained. The experimental result from a single QW GaInP/AlGaInP laser diode, which has 6 nm thick compressively strained Ga0.4InP active layer sandwiched by two 80 nm thick Al0.33GaInP, is presented.

Voltage-matched, monolithic, multi-band-gap devices

DOEpatents

Wanlass, Mark W.; Mascarenhas, Angelo

2006-08-22

Monolithic, tandem, photonic cells include at least a first semiconductor layer and a second semiconductor layer, wherein each semiconductor layer includes an n-type region, a p-type region, and a given band-gap energy. Formed within each semiconductor layer is a sting of electrically connected photonic sub-cells. By carefully selecting the numbers of photonic sub-cells in the first and second layer photonic sub-cell string(s), and by carefully selecting the manner in which the sub-cells in a first and second layer photonic sub-cell string(s) are electrically connected, each of the first and second layer sub-cell strings may be made to achieve one or more substantially identical electrical characteristics.

Voltage-Matched, Monolithic, Multi-Band-Gap Devices

DOEpatents

Wanlass, M. W.; Mascarenhas, A.

2006-08-22

Monolithic, tandem, photonic cells include at least a first semiconductor layer and a second semiconductor layer, wherein each semiconductor layer includes an n-type region, a p-type region, and a given band-gap energy. Formed within each semiconductor layer is a string of electrically connected photonic sub-cells. By carefully selecting the numbers of photonic sub-cells in the first and second layer photonic sub-cell string(s), and by carefully selecting the manner in which the sub-cells in a first and second layer photonic sub-cell string(s) are electrically connected, each of the first and second layer sub-cell strings may be made to achieve one or more substantially identical electrical characteristics.

Photovoltaic devices comprising zinc stannate buffer layer and method for making

DOEpatents

Wu, Xuanzhi; Sheldon, Peter; Coutts, Timothy J.

2001-01-01

A photovoltaic device has a buffer layer zinc stannate Zn.sub.2 SnO.sub.4 disposed between the semiconductor junction structure and the transparent conducting oxide (TCO) layer to prevent formation of localized junctions with the TCO through a thin window semiconductor layer, to prevent shunting through etched grain boundaries of semiconductors, and to relieve stresses and improve adhesion between these layers.

Large-area, laterally-grown epitaxial semiconductor layers

DOEpatents

Han, Jung; Song, Jie; Chen, Danti

2017-07-18

Structures and methods for confined lateral-guided growth of a large-area semiconductor layer on an insulating layer are described. The semiconductor layer may be formed by heteroepitaxial growth from a selective growth area in a vertically-confined, lateral-growth guiding structure. Lateral-growth guiding structures may be formed in arrays over a region of a substrate, so as to cover a majority of the substrate region with laterally-grown epitaxial semiconductor tiles. Quality regions of low-defect, stress-free GaN may be grown on silicon.

340 Ghz Multipixel Transceiver

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam (Inventor); Cooper, Ken B. (Inventor); Decrossas, Emmanuel (Inventor); Gill, John J. (Inventor); Jung-Kubiak, Cecile (Inventor); Lee, Choonsup (Inventor); Lin, Robert (Inventor); Mehdi, Imran (Inventor); Peralta, Alejandro (Inventor); Reck, Theodore (Inventor)

2017-01-01

A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.

Photovoltaic Device Including A Boron Doping Profile In An I-Type Layer

DOEpatents

Yang, Liyou

1993-10-26

A photovoltaic cell for use in a single junction or multijunction photovoltaic device, which includes a p-type layer of a semiconductor compound including silicon, an i-type layer of an amorphous semiconductor compound including silicon, and an n-type layer of a semiconductor compound including silicon formed on the i-type layer. The i-type layer including an undoped first sublayer formed on the p-type layer, and a boron-doped second sublayer formed on the first sublayer.

Near-Unity Absorption in van der Waals Semiconductors for Ultrathin Optoelectronics.

PubMed

Jariwala, Deep; Davoyan, Artur R; Tagliabue, Giulia; Sherrott, Michelle C; Wong, Joeson; Atwater, Harry A

2016-09-14

We demonstrate near-unity, broadband absorbing optoelectronic devices using sub-15 nm thick transition metal dichalcogenides (TMDCs) of molybdenum and tungsten as van der Waals semiconductor active layers. Specifically, we report that near-unity light absorption is possible in extremely thin (<15 nm) van der Waals semiconductor structures by coupling to strongly damped optical modes of semiconductor/metal heterostructures. We further fabricate Schottky junction devices using these highly absorbing heterostructures and characterize their optoelectronic performance. Our work addresses one of the key criteria to enable TMDCs as potential candidates to achieve high optoelectronic efficiency.

Inkjet-Printed Organic Transistors Based on Organic Semiconductor/Insulating Polymer Blends.

PubMed

Kwon, Yoon-Jung; Park, Yeong Don; Lee, Wi Hyoung

2016-08-02

Recent advances in inkjet-printed organic field-effect transistors (OFETs) based on organic semiconductor/insulating polymer blends are reviewed in this article. Organic semiconductor/insulating polymer blends are attractive ink candidates for enhancing the jetting properties, inducing uniform film morphologies, and/or controlling crystallization behaviors of organic semiconductors. Representative studies using soluble acene/insulating polymer blends as an inkjet-printed active layer in OFETs are introduced with special attention paid to the phase separation characteristics of such blended films. In addition, inkjet-printed semiconducting/insulating polymer blends for fabricating high performance printed OFETs are reviewed.

Inkjet-Printed Organic Transistors Based on Organic Semiconductor/Insulating Polymer Blends

PubMed Central

Kwon, Yoon-Jung; Park, Yeong Don; Lee, Wi Hyoung

2016-01-01

Recent advances in inkjet-printed organic field-effect transistors (OFETs) based on organic semiconductor/insulating polymer blends are reviewed in this article. Organic semiconductor/insulating polymer blends are attractive ink candidates for enhancing the jetting properties, inducing uniform film morphologies, and/or controlling crystallization behaviors of organic semiconductors. Representative studies using soluble acene/insulating polymer blends as an inkjet-printed active layer in OFETs are introduced with special attention paid to the phase separation characteristics of such blended films. In addition, inkjet-printed semiconducting/insulating polymer blends for fabricating high performance printed OFETs are reviewed. PMID:28773772

Method of making diode structures

DOEpatents

Compaan, Alvin D.; Gupta, Akhlesh

2006-11-28

A method of making a diode structure includes the step of depositing a transparent electrode layer of any one or more of the group ZnO, ZnS and CdO onto a substrate layer, and depositing an active semiconductor junction having an n-type layer and a p-type layer onto the transparent electrode layer under process conditions that avoid substantial degradation of the electrode layer. A back electrode coating layer is applied to form a diode structure.

Methods of producing free-standing semiconductors using sacrificial buffer layers and recyclable substrates

DOEpatents

Ptak, Aaron Joseph; Lin, Yong; Norman, Andrew; Alberi, Kirstin

2015-05-26

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices. The low-defect density semiconductor materials produced using this method result in the enhanced performance of the semiconductor devices that incorporate the semiconductor materials.

Use of layer strains in strained-layer superlattices to make devices for operation in new wavelength ranges, E. G. , InAsSb at 8 to 12. mu. m. [InAs/sub 1-x/Sb/sub x/

DOEpatents

Osbourn, G.C.

1983-10-06

An intrinsic semiconductor electro-optical device comprises a p-n junction intrinsically responsive, when cooled, to electromagnetic radiation in the wavelength range of 8 to 12 ..mu..m. This radiation responsive p-n junction comprises a strained-layer superlattice (SLS) of alternating layers of two different III-V semiconductors. The lattice constants of the two semiconductors are mismatched, whereby a total strain is imposed on each pair of alternating semiconductor layers in the SLS structure, the proportion of the total strain which acts on each layer of the pair being proportional to the ratio of the layer thicknesses of each layer in the pair.

Plasmon absorption modulator systems and methods

DOEpatents

Kekatpure, Rohan Deodatta; Davids, Paul

2014-07-15

Plasmon absorption modulator systems and methods are disclosed. A plasmon absorption modulator system includes a semiconductor substrate, a plurality of quantum well layers stacked on a top surface of the semiconductor substrate, and a metal layer formed on a top surface of the stack of quantum well layers. A method for modulating plasmonic current includes enabling propagation of the plasmonic current along a metal layer, and applying a voltage across the stack of quantum well layers to cause absorption of a portion of energy of the plasmonic current by the stack of quantum well layers. A metamaterial switching system includes a semiconductor substrate, a plurality of quantum well layers stacked on a top surface of the semiconductor substrate, and at least one metamaterial structure formed on a top surface of the stack of quantum well layers.

Surface preparation of substances for continuous convective assembly of fine particles

DOEpatents

Rossi, Robert

2003-01-01

A method for producing periodic nanometer-scale arrays of metal or semiconductor junctions on a clean semiconductor substrate surface is provided comprising the steps of: etching the substrate surface to make it hydrophilic, forming, under an inert atmosphere, a crystalline colloid layer on the substrate surface, depositing a metal or semiconductor material through the colloid layer onto the surface of the substrate, and removing the colloid from the substrate surface. The colloid layer is grown on the clean semiconductor surface by withdrawing the semiconductor substrate from a sol of colloid particles.

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures.

PubMed

Chen, Ruei-San; Tang, Chih-Che; Shen, Wei-Chu; Huang, Ying-Sheng

2015-12-05

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal-semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 Ω(-) (1) cm(-) (1), with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2.

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

PubMed Central

Chen, Ruei-San; Tang, Chih-Che; Shen, Wei-Chu; Huang, Ying-Sheng

2015-01-01

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal–semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 Ω−1 cm−1, with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2. PMID:26710105

Thin-film solar cell fabricated on a flexible metallic substrate

DOEpatents

Tuttle, John R.; Noufi, Rommel; Hasoon, Falah S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

Thin-Film Solar Cell Fabricated on a Flexible Metallic Substrate

DOEpatents

Tuttle, J. R.; Noufi, R.; Hasoon, F. S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

Infrared light sources with semimetal electron injection

DOEpatents

Kurtz, Steven R.; Biefeld, Robert M.; Allerman, Andrew A.

1999-01-01

An infrared light source is disclosed that comprises a layered semiconductor active region having a semimetal region and at least one quantum-well layer. The semimetal region, formed at an interface between a GaAsSb or GalnSb layer and an InAsSb layer, provides electrons and holes to the quantum-well layer to generate infrared light at a predetermined wavelength in the range of 2-6 .mu.m. Embodiments of the invention can be formed as electrically-activated light-emitting diodes (LEDs) or lasers, and as optically-pumped lasers. Since the active region is unipolar, multiple active regions can be stacked to form a broadband or multiple-wavelength infrared light source.

Interconnected semiconductor devices

DOEpatents

Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

1990-10-23

Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

Single-layer ZnMN2 (M = Si, Ge, Sn) zinc nitrides as promising photocatalysts.

PubMed

Bai, Yujie; Luo, Gaixia; Meng, Lijuan; Zhang, Qinfang; Xu, Ning; Zhang, Haiyang; Wu, Xiuqiang; Kong, Fanjie; Wang, Baolin

2018-05-30

Searching for two-dimensional semiconductor materials that are suitable for visible-light photocatalytic water splitting provides a sustainable solution to deal with the future energy crisis and environmental problems. Herein, based on first-principles calculations, single-layer ZnMN2 (M = Si, Ge, Sn) zinc nitrides are proposed as efficient photocatalysts for water splitting. Stability analyses show that the single-layer ZnMN2 zinc nitrides exhibit energetic and dynamical stability. The electronic properties reveal that all of the single-layer ZnMN2 zinc nitrides are semiconductors. Interestingly, single-layer ZnSnN2 is a direct band gap semiconductor with a desirable band gap (1.74 eV), and the optical adsorption spectrum confirms its optical absorption in the visible light region. The hydrogen evolution reaction (HER) calculations show that the catalytic activity for single-layer ZnMN2 (M = Ge, Sn) is better than that of single-layer ZnSiN2. Furthermore, the band gaps and band edge positions for the single-layer ZnMN2 zinc nitrides can be effectively tuned by biaxial strain. Especially, single-layer ZnGeN2 can be effectively tuned to match better with the redox potentials of water and enhance the light absorption in the visible light region at a tensile strain of 5%, which is confirmed by the corresponding optical absorption spectrum. Our results provide guidance for experimental synthesis efforts and future searches for single-layer materials suitable for photocatalytic water splitting.

Tunable molecular orientation and elevated thermal stability of vapor-deposited organic semiconductors

PubMed Central

Walters, Diane M.; Lyubimov, Ivan; de Pablo, Juan J.; Ediger, M. D.

2015-01-01

Physical vapor deposition is commonly used to prepare organic glasses that serve as the active layers in light-emitting diodes, photovoltaics, and other devices. Recent work has shown that orienting the molecules in such organic semiconductors can significantly enhance device performance. We apply a high-throughput characterization scheme to investigate the effect of the substrate temperature (Tsubstrate) on glasses of three organic molecules used as semiconductors. The optical and material properties are evaluated with spectroscopic ellipsometry. We find that molecular orientation in these glasses is continuously tunable and controlled by Tsubstrate/Tg, where Tg is the glass transition temperature. All three molecules can produce highly anisotropic glasses; the dependence of molecular orientation upon substrate temperature is remarkably similar and nearly independent of molecular length. All three compounds form “stable glasses” with high density and thermal stability, and have properties similar to stable glasses prepared from model glass formers. Simulations reproduce the experimental trends and explain molecular orientation in the deposited glasses in terms of the surface properties of the equilibrium liquid. By showing that organic semiconductors form stable glasses, these results provide an avenue for systematic performance optimization of active layers in organic electronics. PMID:25831545

High speed all optical logic gates based on quantum dot semiconductor optical amplifiers.

PubMed

Ma, Shaozhen; Chen, Zhe; Sun, Hongzhi; Dutta, Niloy K

2010-03-29

A scheme to realize all-optical Boolean logic functions AND, XOR and NOT using semiconductor optical amplifiers with quantum-dot active layers is studied. nonlinear dynamics including carrier heating and spectral hole-burning are taken into account together with the rate equations scheme. Results show with QD excited state and wetting layer serving as dual-reservoir of carriers, as well as the ultra fast carrier relaxation of the QD device, this scheme is suitable for high speed Boolean logic operations. Logic operation can be carried out up to speed of 250 Gb/s.

Method for depositing high-quality microcrystalline semiconductor materials

DOEpatents

Guha, Subhendu [Bloomfield Hills, MI; Yang, Chi C [Troy, MI; Yan, Baojie [Rochester Hills, MI

2011-03-08

A process for the plasma deposition of a layer of a microcrystalline semiconductor material is carried out by energizing a process gas which includes a precursor of the semiconductor material and a diluent with electromagnetic energy so as to create a plasma therefrom. The plasma deposits a layer of the microcrystalline semiconductor material onto the substrate. The concentration of the diluent in the process gas is varied as a function of the thickness of the layer of microcrystalline semiconductor material which has been deposited. Also disclosed is the use of the process for the preparation of an N-I-P type photovoltaic device.

Surface hole gas enabled transparent deep ultraviolet light-emitting diode

NASA Astrophysics Data System (ADS)

Zhang, Jianping; Gao, Ying; Zhou, Ling; Gil, Young-Un; Kim, Kyoung-Min

2018-07-01

The inherent deep-level nature of acceptors in wide-band-gap semiconductors makes p-ohmic contact formation and hole supply difficult, impeding progress for short-wavelength optoelectronics and high-power high-temperature bipolar electronics. We provide a general solution by demonstrating an ultrathin rather than a bulk wide-band-gap semiconductor to be a successful hole supplier and ohmic contact layer. Free holes in this ultrathin semiconductor are assisted to activate from deep acceptors and swept to surface to form hole gases by a large electric field, which can be provided by engineered spontaneous and piezoelectric polarizations. Experimentally, a 6 nm thick AlN layer with surface hole gas had formed p-ohmic contact to metals and provided sufficient hole injection to a 280 nm light-emitting diode, demonstrating a record electrical-optical conversion efficiency exceeding 8.5% at 20 mA (55 A cm‑2). Our approach of forming p-type wide-band-gap semiconductor ohmic contact is critical to realizing high-efficiency ultraviolet optoelectronic devices.

Low temperature production of large-grain polycrystalline semiconductors

DOEpatents

Naseem, Hameed A [Fayetteville, AR; Albarghouti, Marwan [Loudonville, NY

2007-04-10

An oxide or nitride layer is provided on an amorphous semiconductor layer prior to performing metal-induced crystallization of the semiconductor layer. The oxide or nitride layer facilitates conversion of the amorphous material into large grain polycrystalline material. Hence, a native silicon dioxide layer provided on hydrogenated amorphous silicon (a-Si:H), followed by deposited Al permits induced crystallization at temperatures far below the solid phase crystallization temperature of a-Si. Solar cells and thin film transistors can be prepared using this method.

Progress in MOSFET double-layer metalization

NASA Technical Reports Server (NTRS)

Gassaway, J. D.; Trotter, J. D.; Wade, T. E.

1980-01-01

Report describes one-year research effort in VLSL fabrication. Four activities are described: theoretical study of two-dimensional diffusion in SOS (silicon-on-sapphire); setup of sputtering system, furnaces, and photolithography equipment; experiments on double layer metal; and investigation of two-dimensional modeling of MOSFET's (metal-oxide-semiconductor field-effect transistors).

Method for growing low defect, high purity crystalline layers utilizing lateral overgrowth of a patterned mask

NASA Technical Reports Server (NTRS)

Morrison, Andrew D. (Inventor); Daud, Taher (Inventor)

1986-01-01

A method for growing a high purity, low defect layer of semiconductor is described. This method involves depositing a patterned mask of a material impervious to impurities of the semiconductor on a surface of a blank. When a layer of semiconductor is grown on the mask, the semiconductor will first grow from the surface portions exposed by the openings in the mask and will bridge the connecting portions of the mask to form a continuous layer having improved purity, since only the portions overlying the openings are exposed to defects and impurities. The process can be iterated and the mask translated to further improve the quality of grown layers.

Laser pumping of thyristors for fast high current rise-times

DOEpatents

Glidden, Steven C.; Sanders, Howard D.

2013-06-11

An optically triggered semiconductor switch includes an anode metallization layer; a cathode metallization layer; a semiconductor between the anode metallization layer and the cathode metallization layer and a photon source. The semiconductor includes at least four layers of alternating doping in the form P-N-P-N, in which an outer layer adjacent to the anode metallization layer forms an anode and an outer layer adjacent the cathode metallization layer forms a cathode and in which the anode metallization layer has a window pattern of optically transparent material exposing the anode layer to light. The photon source emits light having a wavelength, with the light from the photon source being configured to match the window pattern of the anode metallization layer.

Optical devices featuring textured semiconductor layers

DOEpatents

Moustakas, Theodore D [Dover, MA; Cabalu, Jasper S [Cary, NC

2011-10-11

A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor.

Optical devices featuring textured semiconductor layers

DOEpatents

Moustakas, Theodore D [Dover, MA; Cabalu, Jasper S [Cary, NC

2012-08-07

A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor.

Back-side readout semiconductor photomultiplier

DOEpatents

Choong, Woon-Seng; Holland, Stephen E

2014-05-20

This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region.

Sintered silver joints via controlled topography of electronic packaging subcomponents

DOEpatents

Wereszczak, Andrew A.

2014-09-02

Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.

Method for fabricating an interconnected array of semiconductor devices

DOEpatents

Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

1989-10-10

Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

High-resolution parallel-detection sensor array using piezo-phototronics effect

DOEpatents

Wang, Zhong L.; Pan, Caofeng

2015-07-28

A pressure sensor element includes a substrate, a first type of semiconductor material layer and an array of elongated light-emitting piezoelectric nanostructures extending upwardly from the first type of semiconductor material layer. A p-n junction is formed between each nanostructure and the first type semiconductor layer. An insulative resilient medium layer is infused around each of the elongated light-emitting piezoelectric nanostructures. A transparent planar electrode, disposed on the resilient medium layer, is electrically coupled to the top of each nanostructure. A voltage source is coupled to the first type of semiconductor material layer and the transparent planar electrode and applies a biasing voltage across each of the nanostructures. Each nanostructure emits light in an intensity that is proportional to an amount of compressive strain applied thereto.

On the Effect of Confinement on the Structure and Properties of Small-Molecular Organic Semiconductors

DOE PAGES

Martín, Jaime; Dyson, Matthew; Reid, Obadiah G.; ...

2017-12-11

Many typical organic optoelectronic devices, such as light-emitting diodes, field-effect transistors, and photovoltaic cells, use an ultrathin active layer where the organic semiconductor is confined within nanoscale dimensions. However, the question of how this spatial constraint impacts the active material is rarely addressed, although it may have a drastic influence on the phase behavior and microstructure of the active layer and hence the final performance. Here, the small-molecule semiconductor p-DTS(FBTTh 2) 2 is used as a model system to illustrate how sensitive this class of material can be to spatial confinement on device-relevant length scales. It is also shown thatmore » this effect can be exploited; it is demonstrated, for instance, that spatial confinement is an efficient tool to direct the crystal orientation and overall texture of p-DTS(FBTTh 2) 2 structures in a controlled manner, allowing for the manipulation of properties including photoluminescence and charge transport characteristics. This insight should be widely applicable as the temperature/confinement phase diagrams established via differential scanning calorimetry and grazing-incidence X-ray diffraction are used to identify specific processing routes that can be directly extrapolated to other functional organic materials, such as polymeric semiconductors, ferroelectrics or high-refractive-index polymers, to induce desired crystal textures or specific (potentially new) polymorphs.« less

On the Effect of Confinement on the Structure and Properties of Small-Molecular Organic Semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Martín, Jaime; Dyson, Matthew; Reid, Obadiah G.

Many typical organic optoelectronic devices, such as light-emitting diodes, field-effect transistors, and photovoltaic cells, use an ultrathin active layer where the organic semiconductor is confined within nanoscale dimensions. However, the question of how this spatial constraint impacts the active material is rarely addressed, although it may have a drastic influence on the phase behavior and microstructure of the active layer and hence the final performance. Here, the small-molecule semiconductor p-DTS(FBTTh 2) 2 is used as a model system to illustrate how sensitive this class of material can be to spatial confinement on device-relevant length scales. It is also shown thatmore » this effect can be exploited; it is demonstrated, for instance, that spatial confinement is an efficient tool to direct the crystal orientation and overall texture of p-DTS(FBTTh 2) 2 structures in a controlled manner, allowing for the manipulation of properties including photoluminescence and charge transport characteristics. This insight should be widely applicable as the temperature/confinement phase diagrams established via differential scanning calorimetry and grazing-incidence X-ray diffraction are used to identify specific processing routes that can be directly extrapolated to other functional organic materials, such as polymeric semiconductors, ferroelectrics or high-refractive-index polymers, to induce desired crystal textures or specific (potentially new) polymorphs.« less

Effective coupled optoelectrical design method for fully infiltrated semiconductor nanowires based hybrid solar cells.

PubMed

Wu, Dan; Tang, Xiaohong; Wang, Kai; Li, Xianqiang

2016-10-31

We present a novel coupled design method that both optimizes light absorption and predicts electrical performance of fully infiltrated inorganic semiconductor nanowires (NWs) based hybrid solar cells (HSC). This method provides a thorough insight of hybrid photovoltaic process as a function of geometrical parameters of NWs. An active layer consisting of GaAs NWs as acceptor and poly(3-hexylthiophene-2,5-diyl) (P3HT) as donor were used as a design example. Absorption spectra features were studied by the evolution of the leaky modes and Fabry-Perot resonance with wavelength focusing firstly on the GaAs/air layer before extending to GaAs/P3HT hybrid active layer. The highest absorption efficiency reached 39% for the hybrid active layer of 2 μm thickness under AM 1.5G illumination. Combined with the optical absorption analysis, our method further codesigns the energy harvesting to predict electrical performance of HSC considering exciton dissociation efficiencies within both inorganic NWs and a polymeric shell of 20 nm thickness. The validity of the simulation model was also proved by the well agreement of the simulation results with the published experimental work indicating an effective guidance for future high performance HSC design.

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

1984-04-19

In a field-effect transistor comprising a semiconductor having therein a source, a drain, a channel and a gate in operational relationship, there is provided an improvement wherein said semiconductor is a superlattice comprising alternating quantum well and barrier layers, the quantum well layers comprising a first direct gap semiconductor material which in bulk form has a certain bandgap and a curve of electron velocity versus applied electric field which has a maximum electron velocity at a certain electric field, the barrier layers comprising a second semiconductor material having a bandgap wider than that of said first semiconductor material, wherein the layer thicknesses of said quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice having a curve of electron velocity versus applied electric field which has a maximum electron velocity at a certain electric field, and wherein the thicknesses of said quantum well layers are selected to provide a superlattice curve of electron velocity versus applied electric field whereby, at applied electric fields higher than that at which the maximum electron velocity occurs in said first material when in bulk form, the electron velocities are higher in said superlattice than they are in said first semiconductor material in bulk form.

Precise, Self-Limited Epitaxy of Ultrathin Organic Semiconductors and Heterojunctions Tailored by van der Waals Interactions.

PubMed

Wu, Bing; Zhao, Yinghe; Nan, Haiyan; Yang, Ziyi; Zhang, Yuhan; Zhao, Huijuan; He, Daowei; Jiang, Zonglin; Liu, Xiaolong; Li, Yun; Shi, Yi; Ni, Zhenhua; Wang, Jinlan; Xu, Jian-Bin; Wang, Xinran

2016-06-08

Precise assembly of semiconductor heterojunctions is the key to realize many optoelectronic devices. By exploiting the strong and tunable van der Waals (vdW) forces between graphene and organic small molecules, we demonstrate layer-by-layer epitaxy of ultrathin organic semiconductors and heterostructures with unprecedented precision with well-defined number of layers and self-limited characteristics. We further demonstrate organic p-n heterojunctions with molecularly flat interface, which exhibit excellent rectifying behavior and photovoltaic responses. The self-limited organic molecular beam epitaxy (SLOMBE) is generically applicable for many layered small-molecule semiconductors and may lead to advanced organic optoelectronic devices beyond bulk heterojunctions.

Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

DOEpatents

Wu, Xuanzhi; Coutts, Timothy J.; Sheldon, Peter; Rose, Douglas H.

1999-01-01

A photovoltaic device having a substrate, a layer of Cd.sub.2 SnO.sub.4 disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd.sub.2 SnO.sub.4, and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd.sub.2 SnO.sub.4 layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd.sub.2 SnO.sub.4, and depositing an electrically conductive film onto the thin film of semiconductor materials.

Porous silicon carbide (SiC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

Study of various n-type organic semiconductors on ultraviolet detective and electroluminescent properties of optoelectronic integrated device

NASA Astrophysics Data System (ADS)

Deng, Chaoxu; Shao, Bingyao; Zhao, Dan; Zhou, Dianli; Yu, Junsheng

2017-11-01

Organic optoelectronic integrated device (OID) with both ultraviolet (UV) detective and electroluminescent (EL) properties was fabricated by using a thermally activated delayed fluorescence (TADF) semiconductor of (4s, 6s)-2,4,5,6-tetra(9H-carbazol-9-yl)isophthalonitrile (4CzIPN) as an emitter. The effect of five kinds of n-type organic semiconductors (OSCs) on the enhancement of UV detective and EL properties of OID was systematically studied. The result shows that two orders of magnitude in UV detectivity from 109 to 1011 Jones and 3.3 folds of luminance from 2499 to 8233 cd m-2 could be achieved. The result shows that not only the difference of lowest unoccupied molecular orbital (LUMO) between active layer and OSC but also the variety of electron mobility have a significant effect on the UV detective and EL performance through adjusting electron injection/transport. Additionally, the optimized OSC thickness is beneficial to confine the leaking of holes from the active layer to cathode, leading to the decrease of dark current for high detective performance. This work provides a useful method on broadening OSC material selection and device architecture construction for the realization of high performance OID.

Efficient semiconductor light-emitting device and method

DOEpatents

Choquette, Kent D.; Lear, Kevin L.; Schneider, Jr., Richard P.

1996-01-01

A semiconductor light-emitting device and method. The semiconductor light-emitting device is provided with at least one control layer or control region which includes an annular oxidized portion thereof to channel an injection current into the active region, and to provide a lateral refractive index profile for index guiding the light generated within the device. A periodic composition grading of at least one of the mirror stacks in the device provides a reduced operating voltage of the device. The semiconductor light-emitting device has a high efficiency for light generation, and may be formed either as a resonant-cavity light-emitting diode (RCLED) or as a vertical-cavity surface-emitting laser (VCSEL).

Efficient semiconductor light-emitting device and method

DOEpatents

Choquette, K.D.; Lear, K.L.; Schneider, R.P. Jr.

1996-02-20

A semiconductor light-emitting device and method are disclosed. The semiconductor light-emitting device is provided with at least one control layer or control region which includes an annular oxidized portion thereof to channel an injection current into the active region, and to provide a lateral refractive index profile for index guiding the light generated within the device. A periodic composition grading of at least one of the mirror stacks in the device provides a reduced operating voltage of the device. The semiconductor light-emitting device has a high efficiency for light generation, and may be formed either as a resonant-cavity light-emitting diode (RCLED) or as a vertical-cavity surface-emitting laser (VCSEL). 12 figs.

Enhancing surface plasmon leakage at the metal/semiconductor interface: towards increased light outcoupling efficiency in organic optoelectronics.

PubMed

Kohl, Jesse; Pantina, Joseph A; O'Carroll, Deirdre M

2014-04-07

The light outcoupling efficiency of organic light-emitting optoelectronic devices is severely limited by excitation of tightly bound surface plasmon polaritons at the metal electrodes. We present a theoretical study of an organic semiconductor-silver-SiO(2) waveguide and demonstrate that by simple tuning of metal film thickness and the emission regime of the organic semiconductor, a significant fraction of surface plasmon polariton mode amplitude is leaked into the active semiconductor layer, thereby decreasing the amount of optical energy trapped by the metal. At visible wavelengths, mode leakage increases by factors of up to 3.8 and 88 by tuning metal film thickness and by addition of gain, respectively.

Ion-implanted planar-buried-heterostructure diode laser

DOEpatents

Brennan, Thomas M.; Hammons, Burrell E.; Myers, David R.; Vawter, Gregory A.

1991-01-01

A Planar-Buried-Heterostructure, Graded-Index, Separate-Confinement-Heterostructure semiconductor diode laser 10 includes a single quantum well or multi-quantum well active stripe 12 disposed between a p-type compositionally graded Group III-V cladding layer 14 and an n-type compositionally graded Group III-V cladding layer 16. The laser 10 includes an ion implanted n-type region 28 within the p-type cladding layer 14 and further includes an ion implanted p-type region 26 within the n-type cladding layer 16. The ion implanted regions are disposed for defining a lateral extent of the active stripe.

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Tunable molecular orientation and elevated thermal stability of vapor-deposited organic semiconductors

DOE PAGES

Dalal, Shakeel S.; Walters, Diane M.; Lyubimov, Ivan; ...

2015-03-23

Physical vapor deposition is commonly used to prepare organic glasses that serve as the active layers in light-emitting diodes, photovoltaics, and other devices. Recent work has shown that orienting the molecules in such organic semiconductors can significantly enhance device performance. In this paper, we apply a high-throughput characterization scheme to investigate the effect of the substrate temperature (T substrate) on glasses of three organic molecules used as semiconductors. The optical and material properties are evaluated with spectroscopic ellipsometry. We find that molecular orientation in these glasses is continuously tunable and controlled by T substrate/T g, where T g is themore » glass transition temperature. All three molecules can produce highly anisotropic glasses; the dependence of molecular orientation upon substrate temperature is remarkably similar and nearly independent of molecular length. All three compounds form “stable glasses” with high density and thermal stability, and have properties similar to stable glasses prepared from model glass formers. Simulations reproduce the experimental trends and explain molecular orientation in the deposited glasses in terms of the surface properties of the equilibrium liquid. Finally, by showing that organic semiconductors form stable glasses, these results provide an avenue for systematic performance optimization of active layers in organic electronics.« less

Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

DOEpatents

Wu, X.; Coutts, T.J.; Sheldon, P.; Rose, D.H.

1999-07-13

A photovoltaic device is disclosed having a substrate, a layer of Cd[sub 2]SnO[sub 4] disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd[sub 2]SnO[sub 4], and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd[sub 2]SnO[sub 4] layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd[sub 2]SnO[sub 4], and depositing an electrically conductive film onto the thin film of semiconductor materials. 10 figs.

Structure and properties of small molecule-polymer blend semiconductors for organic thin film transistors.

PubMed

Kang, Jihoon; Shin, Nayool; Jang, Do Young; Prabhu, Vivek M; Yoon, Do Y

2008-09-17

A comprehensive structural and electrical characterization of solution-processed blend films of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) semiconductor and poly(alpha-methylstyrene) (PalphaMS) insulator was performed to understand and optimize the blend semiconductor films, which are very attractive as the active layer in solution-processed organic thin-film transistors (OTFTs). Our study, based on careful measurements of specular neutron reflectivity and grazing-incidence X-ray diffraction, showed that the blends with a low molecular-mass PalphaMS exhibited a strong segregation of TIPS-pentacene only at the air interface, but surprisingly the blends with a high molecular-mass PalphaMS showed a strong segregation of TIPS-pentacene at both air and bottom substrate interfaces with high crystallinity and desired orientation. This finding led to the preparation of a TIPS-pentacene/PalphaMS blend active layer with superior performance characteristics (field-effect mobility, on/off ratio, and threshold voltage) over those of neat TIPS-pentacene, as well as the solution-processability of technologically attractive bottom-gate/bottom-contact OTFT devices.

INTERNATIONAL CONFERENCE ON SEMICONDUCTOR INJECTION LASERS SELCO-87: High-performance 1.3-μm InGaAsP/InP heterostructures formed by two-phase liquid epitaxy

NASA Astrophysics Data System (ADS)

Novotný, J.; Procházková, O.; Šrobár, F.; Zelinka, J.

1988-11-01

A description is given of a two-phase liquid epitaxy method used to grow InGaAsP/InP heterostructures intended for injection lasers emitting in the 1.3-μm range. A study was made of heterostructures of three types: double, with an additional quaternary layer (λ approx 1.1 μm) adjoining the active layer; with two quaternary layers between the active layer and the InP confining layers. The configuration with two flanking quaternary layers was found to be the best from the point of view of the threshold current density, optical output power, and reproducibility.

Beating the thermodynamic limit with photo-activation of n-doping in organic semiconductors

NASA Astrophysics Data System (ADS)

Lin, Xin; Wegner, Berthold; Lee, Kyung Min; Fusella, Michael A.; Zhang, Fengyu; Moudgil, Karttikay; Rand, Barry P.; Barlow, Stephen; Marder, Seth R.; Koch, Norbert; Kahn, Antoine

2017-12-01

Chemical doping of organic semiconductors using molecular dopants plays a key role in the fabrication of efficient organic electronic devices. Although a variety of stable molecular p-dopants have been developed and successfully deployed in devices in the past decade, air-stable molecular n-dopants suitable for materials with low electron affinity are still elusive. Here we demonstrate that photo-activation of a cleavable air-stable dimeric dopant can result in kinetically stable and efficient n-doping of host semiconductors, whose reduction potentials are beyond the thermodynamic reach of the dimer’s effective reducing strength. Electron-transport layers doped in this manner are used to fabricate high-efficiency organic light-emitting diodes. Our strategy thus enables a new paradigm for using air-stable molecular dopants to improve conductivity in, and provide ohmic contacts to, organic semiconductors with very low electron affinity.

Optical activity in chiral stacks of 2D semiconductors

NASA Astrophysics Data System (ADS)

Poshakinskiy, Alexander V.; Kazanov, Dmitrii R.; Shubina, Tatiana V.; Tarasenko, Sergey A.

2018-03-01

We show that the stacks of two-dimensional semiconductor crystals with the chiral packing exhibit optical activity and circular dichroism. We develop a microscopic theory of these phenomena in the spectral range of exciton transitions that takes into account the spin-dependent hopping of excitons between the layers in the stack and the interlayer coupling of excitons via electromagnetic field. For the stacks of realistic two-dimensional semiconductors such as transition metal dichalcogenides, we calculate the rotation and ellipticity angles of radiation transmitted through such structures. The angles are resonantly enhanced at the frequencies of both bright and dark exciton modes in the stack. We also study the photoluminescence of chiral stacks and show that it is circularly polarized.

Dry texturing of solar cells

DOEpatents

Sopori, B.L.

1994-10-25

A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer. The result is a textured backside on an optically reflective, low resistivity alloy interface between the semiconductor substrate and the metal electrical contact layer. 9 figs.

Dry texturing of solar cells

DOEpatents

Sopori, Bhushan L.

1994-01-01

A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer. The result is a textured backside an optically reflective, low resistivity alloy interface between the semiconductor substrate and the metal electrical contact layer.

Nanomembrane structures having mixed crystalline orientations and compositions

DOEpatents

Lagally, Max G.; Scott, Shelley A.; Savage, Donald E.

2014-08-12

The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but which differs from the nanomembrane semiconductor materials in composition, crystal orientation, or both.

Die singulation method

DOEpatents

Swiler, Thomas P.; Garcia, Ernest J.; Francis, Kathryn M.

2013-06-11

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Die singulation method

DOEpatents

Swiler, Thomas P [Albuquerque, NM; Garcia, Ernest J [Albuquerque, NM; Francis, Kathryn M [Rio Rancho, NM

2014-01-07

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with a HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Method for depositing layers of high quality semiconductor material

DOEpatents

Guha, Subhendu; Yang, Chi C.

2001-08-14

Plasma deposition of substantially amorphous semiconductor materials is carried out under a set of deposition parameters which are selected so that the process operates near the amorphous/microcrystalline threshold. This threshold varies as a function of the thickness of the depositing semiconductor layer; and, deposition parameters, such as diluent gas concentrations, must be adjusted as a function of layer thickness. Also, this threshold varies as a function of the composition of the depositing layer, and in those instances where the layer composition is profiled throughout its thickness, deposition parameters must be adjusted accordingly so as to maintain the amorphous/microcrystalline threshold.

Amorphous semiconductor solar cell

DOEpatents

Dalal, Vikram L.

1981-01-01

A solar cell comprising a back electrical contact, amorphous silicon semiconductor base and junction layers and a top electrical contact includes in its manufacture the step of heat treating the physical junction between the base layer and junction layer to diffuse the dopant species at the physical junction into the base layer.

Semiconductor activated terahertz metamaterials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Hou-Tong

Metamaterials have been developed as a new class of artificial effective media realizing many exotic phenomena and unique properties not normally found in nature. Metamaterials enable functionality through structure design, facilitating applications by addressing the severe material issues in the terahertz frequency range. Consequently, prototype functional terahertz devices have been demonstrated, including filters, antireflection coatings, perfect absorbers, polarization converters, and arbitrary wavefront shaping devices. Further integration of functional materials into metamaterial structures have enabled actively and dynamically switchable and frequency tunable terahertz metamaterials through the application of external stimuli. The enhanced light-matter interactions in active terahertz metamaterials may result inmore » unprecedented control and manipulation of terahertz radiation, forming the foundation of many terahertz applications. In this paper, we review the progress during the past few years in this rapidly growing research field. We particularly focus on the design principles and realization of functionalities using single-layer and few-layer terahertz planar metamaterials, and active terahertz metamaterials through the integration of semiconductors to achieve switchable and frequency-tunable response.« less

Semiconductor activated terahertz metamaterials

DOE PAGES

Chen, Hou-Tong

2014-08-01

Metamaterials have been developed as a new class of artificial effective media realizing many exotic phenomena and unique properties not normally found in nature. Metamaterials enable functionality through structure design, facilitating applications by addressing the severe material issues in the terahertz frequency range. Consequently, prototype functional terahertz devices have been demonstrated, including filters, antireflection coatings, perfect absorbers, polarization converters, and arbitrary wavefront shaping devices. Further integration of functional materials into metamaterial structures have enabled actively and dynamically switchable and frequency tunable terahertz metamaterials through the application of external stimuli. The enhanced light-matter interactions in active terahertz metamaterials may result inmore » unprecedented control and manipulation of terahertz radiation, forming the foundation of many terahertz applications. In this paper, we review the progress during the past few years in this rapidly growing research field. We particularly focus on the design principles and realization of functionalities using single-layer and few-layer terahertz planar metamaterials, and active terahertz metamaterials through the integration of semiconductors to achieve switchable and frequency-tunable response.« less

Nanocrystal structures

DOEpatents

Eisler, Hans J [Stoneham, MA; Sundar, Vikram C [Stoneham, MA; Walsh, Michael E [Everett, MA; Klimov, Victor I [Los Alamos, NM; Bawendi, Moungi G [Cambridge, MA; Smith, Henry I [Sudbury, MA

2008-12-30

A structure including a grating and a semiconductor nanocrystal layer on the grating, can be a laser. The semiconductor nanocrystal layer can include a plurality of semiconductor nanocrystals including a Group II-VI compound, the nanocrystals being distributed in a metal oxide matrix. The grating can have a periodicity from 200 nm to 500 nm.

Nanocrystal structures

DOEpatents

Eisler, Hans J.; Sundar, Vikram C.; Walsh, Michael E.; Klimov, Victor I.; Bawendi, Moungi G.; Smith, Henry I.

2006-12-19

A structure including a grating and a semiconductor nanocrystal layer on the grating, can be a laser. The semiconductor nanocrystal layer can include a plurality of semiconductor nanocrystals including a Group II–VI compound, the nanocrystals being distributed in a metal oxide matrix. The grating can have a periodicity from 200 nm to 500 nm.

Optical devices featuring nonpolar textured semiconductor layers

DOEpatents

Moustakas, Theodore D; Moldawer, Adam; Bhattacharyya, Anirban; Abell, Joshua

2013-11-26

A semiconductor emitter, or precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of nonpolar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the invention can be 70-80% or higher. The invention provides highly efficient light emitting diodes suitable for solid state lighting.

SCB initiator

DOEpatents

Bickes Jr., Robert W.; Renlund, Anita M.; Stanton, Philip L.

1994-11-01

A detonator for high explosives initiated by mechanical impact includes a cylindrical barrel, a layer of flyer material mechanically covering the barrel at one end, and a semiconductor bridge ignitor including a pair of electrically conductive pads connected by a semiconductor bridge. The bridge is in operational contact with the layer, whereby ignition of said bridge forces a portion of the layer through the barrel to detonate the explosive. Input means are provided for igniting the semiconductor bridge ignitor.

SCB initiator

DOEpatents

Bickes, Jr., Robert W.; Renlund, Anita M.; Stanton, Philip L.

1994-01-01

A detonator for high explosives initiated by mechanical impact includes a cylindrical barrel, a layer of flyer material mechanically covering the barrel at one end, and a semiconductor bridge ignitor including a pair of electrically conductive pads connected by a semiconductor bridge. The bridge is in operational contact with the layer, whereby ignition of said bridge forces a portion of the layer through the barrel to detonate the explosive. Input means are provided for igniting the semiconductor bridge ignitor.

Electron gas grid semiconductor radiation detectors

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

An electron gas grid semiconductor radiation detector (EGGSRAD) useful for gamma-ray and x-ray spectrometers and imaging systems is described. The radiation detector employs doping of the semiconductor and variation of the semiconductor detector material to form a two-dimensional electron gas, and to allow transistor action within the detector. This radiation detector provides superior energy resolution and radiation detection sensitivity over the conventional semiconductor radiation detector and the "electron-only" semiconductor radiation detectors which utilize a grid electrode near the anode. In a first embodiment, the EGGSRAD incorporates delta-doped layers adjacent the anode which produce an internal free electron grid well to which an external grid electrode can be attached. In a second embodiment, a quantum well is formed between two of the delta-doped layers, and the quantum well forms the internal free electron gas grid to which an external grid electrode can be attached. Two other embodiments which are similar to the first and second embodiment involve a graded bandgap formed by changing the composition of the semiconductor material near the first and last of the delta-doped layers to increase or decrease the conduction band energy adjacent to the delta-doped layers.

Method of transferring strained semiconductor structure

DOEpatents

Nastasi, Michael A [Santa Fe, NM; Shao, Lin [College Station, TX

2009-12-29

The transfer of strained semiconductor layers from one substrate to another substrate involves depositing a multilayer structure on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the deposited multilayer structure is bonded to a second substrate and is separated away at the interface, which results in transferring a multilayer structure from one substrate to the other substrate. The multilayer structure includes at least one strained semiconductor layer and at least one strain-induced seed layer. The strain-induced seed layer can be optionally etched away after the layer transfer.

Organic solar cells with graded absorber layers processed from nanoparticle dispersions.

PubMed

Gärtner, Stefan; Reich, Stefan; Bruns, Michael; Czolk, Jens; Colsmann, Alexander

2016-03-28

The fabrication of organic solar cells with advanced multi-layer architectures from solution is often limited by the choice of solvents since most organic semiconductors dissolve in the same aromatic agents. In this work, we investigate multi-pass deposition of organic semiconductors from eco-friendly ethanol dispersion. Once applied, the nanoparticles are insoluble in the deposition agent, allowing for the application of further nanoparticulate layers and hence for building poly(3-hexylthiophene-2,5-diyl):indene-C60 bisadduct absorber layers with vertically graded polymer and conversely graded fullerene concentration. Upon thermal annealing, we observe some degrees of polymer/fullerene interdiffusion by means of X-ray photoelectron spectroscopy and Kelvin probe force microscopy. Replacing the common bulk-heterojunction by such a graded photo-active layer yields an enhanced fill factor of the solar cell due to an improved charge carrier extraction, and consequently an overall power conversion efficiency beyond 4%. Wet processing of such advanced device architectures paves the way for a versatile, eco-friendly and industrially feasible future fabrication of organic solar cells with advanced multi-layer architectures.

InP solar cell with window layer

NASA Technical Reports Server (NTRS)

Jain, Raj K. (Inventor); Landis, Geoffrey A. (Inventor)

1994-01-01

The invention features a thin light transmissive layer of the ternary semiconductor indium aluminum arsenide (InAlAs) as a front surface passivation or 'window' layer for p-on-n InP solar cells. The window layers of the invention effectively reduce front surface recombination of the object semiconductors thereby increasing the efficiency of the cells.

Color-selective photodetection from intermediate colloidal quantum dots buried in amorphous-oxide semiconductors.

PubMed

Cho, Kyung-Sang; Heo, Keun; Baik, Chan-Wook; Choi, Jun Young; Jeong, Heejeong; Hwang, Sungwoo; Lee, Sang Yeol

2017-10-10

We report color-selective photodetection from intermediate, monolayered, quantum dots buried in between amorphous-oxide semiconductors. The proposed active channel in phototransistors is a hybrid configuration of oxide-quantum dot-oxide layers, where the gate-tunable electrical property of silicon-doped, indium-zinc-oxide layers is incorporated with the color-selective properties of quantum dots. A remarkably high detectivity (8.1 × 10 13 Jones) is obtained, along with three major findings: fast charge separation in monolayered quantum dots; efficient charge transport through high-mobility oxide layers (20 cm 2  V -1  s -1 ); and gate-tunable drain-current modulation. Particularly, the fast charge separation rate of 3.3 ns -1 measured with time-resolved photoluminescence is attributed to the intermediate quantum dots buried in oxide layers. These results facilitate the realization of efficient color-selective detection exhibiting a photoconductive gain of 10 7 , obtained using a room-temperature deposition of oxide layers and a solution process of quantum dots. This work offers promising opportunities in emerging applications for color detection with sensitivity, transparency, and flexibility.The development of highly sensitive photodetectors is important for image sensing and optical communication applications. Cho et al., report ultra-sensitive photodetectors based on monolayered quantum dots buried in between amorphous-oxide semiconductors and demonstrate color-detecting logic gates.

Fabrication of optically reflecting ohmic contacts for semiconductor devices

DOEpatents

Sopori, Bhushan L.

1995-01-01

A method is provided to produce a low-resistivity ohmic contact having high optical reflectivity on one side of a semiconductor device. The contact is formed by coating the semiconductor substrate with a thin metal film on the back reflecting side and then optically processing the wafer by illuminating it with electromagnetic radiation of a predetermined wavelength and energy level through the front side of the wafer for a predetermined period of time. This method produces a thin epitaxial alloy layer between the semiconductor substrate and the metal layer when a crystalline substrate is used. The alloy layer provides both a low-resistivity ohmic contact and high optical reflectance.

Solid state photosensitive devices which employ isolated photosynthetic complexes

DOEpatents

Peumans, Peter; Forrest, Stephen R.

2009-09-22

Solid state photosensitive devices including photovoltaic devices are provided which comprise a first electrode and a second electrode in superposed relation; and at least one isolated Light Harvesting Complex (LHC) between the electrodes. Preferred photosensitive devices comprise an electron transport layer formed of a first photoconductive organic semiconductor material, adjacent to the LHC, disposed between the first electrode and the LHC; and a hole transport layer formed of a second photoconductive organic semiconductor material, adjacent to the LHC, disposed between the second electrode and the LHC. Solid state photosensitive devices of the present invention may comprise at least one additional layer of photoconductive organic semiconductor material disposed between the first electrode and the electron transport layer; and at least one additional layer of photoconductive organic semiconductor material, disposed between the second electrode and the hole transport layer. Methods of generating photocurrent are provided which comprise exposing a photovoltaic device of the present invention to light. Electronic devices are provided which comprise a solid state photosensitive device of the present invention.

All-vapor processing of p-type tellurium-containing II-VI semiconductor and ohmic contacts thereof

DOEpatents

McCandless, Brian E.

2001-06-26

An all dry method for producing solar cells is provided comprising first heat-annealing a II-VI semiconductor; enhancing the conductivity and grain size of the annealed layer; modifying the surface and depositing a tellurium layer onto the enhanced layer; and then depositing copper onto the tellurium layer so as to produce a copper tellurium compound on the layer.

Deposition of dopant impurities and pulsed energy drive-in

DOEpatents

Wickboldt, Paul; Carey, Paul G.; Smith, Patrick M.; Ellingboe, Albert R.

2008-01-01

A semiconductor doping process which enhances the dopant incorporation achievable using the Gas Immersion Laser Doping (GILD) technique. The enhanced doping is achieved by first depositing a thin layer of dopant atoms on a semiconductor surface followed by exposure to one or more pulses from either a laser or an ion-beam which melt a portion of the semiconductor to a desired depth, thus causing the dopant atoms to be incorporated into the molten region. After the molten region recrystallizes the dopant atoms are electrically active. The dopant atoms are deposited by plasma enhanced chemical vapor deposition (PECVD) or other known deposition techniques.

Deposition of dopant impurities and pulsed energy drive-in

DOEpatents

Wickboldt, Paul; Carey, Paul G.; Smith, Patrick M.; Ellingboe, Albert R.

1999-01-01

A semiconductor doping process which enhances the dopant incorporation achievable using the Gas Immersion Laser Doping (GILD) technique. The enhanced doping is achieved by first depositing a thin layer of dopant atoms on a semiconductor surface followed by exposure to one or more pulses from either a laser or an ion-beam which melt a portion of the semiconductor to a desired depth, thus causing the dopant atoms to be incorporated into the molten region. After the molten region recrystallizes the dopant atoms are electrically active. The dopant atoms are deposited by plasma enhanced chemical vapor deposition (PECVD) or other known deposition techniques.

Deposition of dopant impurities and pulsed energy drive-in

DOEpatents

Wickboldt, P.; Carey, P.G.; Smith, P.M.; Ellingboe, A.R.

1999-06-29

A semiconductor doping process which enhances the dopant incorporation achievable using the Gas Immersion Laser Doping (GILD) technique is disclosed. The enhanced doping is achieved by first depositing a thin layer of dopant atoms on a semiconductor surface followed by exposure to one or more pulses from either a laser or an ion-beam which melt a portion of the semiconductor to a desired depth, thus causing the dopant atoms to be incorporated into the molten region. After the molten region recrystallizes the dopant atoms are electrically active. The dopant atoms are deposited by plasma enhanced chemical vapor deposition (PECVD) or other known deposition techniques. 2 figs.

Processes for multi-layer devices utilizing layer transfer

DOEpatents

Nielson, Gregory N; Sanchez, Carlos Anthony; Tauke-Pedretti, Anna; Kim, Bongsang; Cederberg, Jeffrey; Okandan, Murat; Cruz-Campa, Jose Luis; Resnick, Paul J

2015-02-03

A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, T.B.

1985-09-30

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron tunneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, Tomas B.

1987-01-01

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron funneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, T.B.

1987-06-23

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron funneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner. 2 figs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Usanov, D. A., E-mail: UsanovDA@info.sgu.ru; Nikitov, S. A.; Skripal, A. V.

A method is proposed for the measurement of the electrophysical characteristics of semiconductor structures: the electrical conductivity of the n layer, which plays the role of substrate for a semiconductor structure, and the thickness and electrical conductivity of the strongly doped epitaxial n{sup +} layer. The method is based on the use of a one-dimensional microwave photonic crystal with a violation of periodicity containing the semiconductor structure under investigation. The characteristics of epitaxial gallium-arsenide structures consisting of an epitaxial layer and the semi-insulating substrate measured by this method are presented.

Selective epitaxy using the gild process

DOEpatents

Weiner, Kurt H.

1992-01-01

The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.1-x grown over silicon. Such a process may be used to manufacture small transistors that have a narrow base, heavy doping, and high gain. The narrowness allows a faster transistor, and the heavy doping reduces the resistance of the narrow layer. The process does not require high temperature annealing; therefore materials such as aluminum can be used. Furthermore, the process may be used to fabricate diodes that have a high reverse breakdown voltage and a low reverse leakage current.

Epitaxial MoS2/GaN structures to enable vertical 2D/3D semiconductor heterostructure devices

NASA Astrophysics Data System (ADS)

Ruzmetov, D.; Zhang, K.; Stan, G.; Kalanyan, B.; Eichfeld, S.; Burke, R.; Shah, P.; O'Regan, T.; Crowne, F.; Birdwell, A. G.; Robinson, J.; Davydov, A.; Ivanov, T.

MoS2/GaN structures are investigated as a building block for vertical 2D/3D semiconductor heterostructure devices that utilize a 3D substrate (GaN) as an active component of the semiconductor device without the need of mechanical transfer of the 2D layer. Our CVD-grown monolayer MoS2 has been shown to be epitaxially aligned to the GaN lattice which is a pre-requisite for high quality 2D/3D interfaces desired for efficient vertical transport and large area growth. The MoS2 coverage is nearly 50 % including isolated triangles and monolayer islands. The GaN template is a double-layer grown by MOCVD on sapphire and allows for measurement of transport perpendicular to the 2D layer. Photoluminescence, Raman, XPS, Kelvin force probe microscopy, and SEM analysis identified high quality monolayer MoS2. The MoS2/GaN structures electrically conduct in the out-of-plane direction and across the van der Waals gap, as measured with conducting AFM (CAFM). The CAFM current maps and I-V characteristics are analyzed to estimate the MoS2/GaN contact resistivity to be less than 4 Ω-cm2 and current spreading in the MoS2 monolayer to be approx. 1 μm in diameter. Epitaxial MoS2/GaN heterostructures present a promising platform for the design of energy-efficient, high-speed vertical devices incorporating 2D layered materials with 3D semiconductors.

Method of making an ion-implanted planar-buried-heterostructure diode laser

DOEpatents

Brennan, Thomas M.; Hammons, Burrell E.; Myers, David R.; Vawter, Gregory A.

1992-01-01

Planar-buried-heterostructure, graded-index, separate-confinement-heterostructure semiconductor diode laser 10 includes a single quantum well or multi-quantum well active stripe 12 disposed between a p-type compositionally graded Group III-V cladding lever 14 and an n-type compositionally graded Group III-V cladding layer 16. The laser 10 includes an iion implanted n-type region 28 within the p-type cladding layer 14 and further includes an ion implanted p-type region 26 within the n-type cladding layer 16. The ion implanted regions are disposed for defining a lateral extent of the active stripe.

Semiconductor devices incorporating multilayer interference regions

DOEpatents

Biefeld, Robert M.; Drummond, Timothy J.; Gourley, Paul L.; Zipperian, Thomas E.

1990-01-01

A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration.

Increased photocatalytic activity induced by TiO2/Pt/SnO2 heterostructured films

NASA Astrophysics Data System (ADS)

Testoni, Glaucio O.; Amoresi, Rafael A. C.; Lustosa, Glauco M. M. M.; Costa, João P. C.; Nogueira, Marcelo V.; Ruiz, Miguel; Zaghete, Maria A.; Perazolli, Leinig A.

2018-02-01

In this work, a high photocatalytic activity was attained by intercalating a Pt layer between SnO2 and TiO2 semiconductors, which yielded a TiO2/Pt/SnO2 - type heterostructure used in the discoloration of blue methylene (MB) solution. The porous films and platinum layer were obtained by electrophoretic deposition and DC Sputtering, respectively, and were both characterized morphologically and structurally by FE-SEM and XRD. The films with the Pt interlayer were evaluated by photocatalytic activity through exposure to UV light. An increase in efficiency of 22% was obtained for these films compared to those without platinum deposition. Studies on the reutilization of the films pointed out high efficiency and recovery of the photocatalyst, rendering the methodology favorable for the construction of fixed bed photocatalytic reactors. A proposal associated with the mechanism is discussed in this work in terms of the difference in Schottky barrier between the semiconductors and the electrons transfer and trapping cycle. These are fundamental factors for boosting photocatalytic efficiency.

Coincident site lattice-matched growth of semiconductors on substrates using compliant buffer layers

DOEpatents

Norman, Andrew

2016-08-23

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.

Nanoimprinted Hybrid Metal-Semiconductor Plasmonic Multilayers with Controlled Surface Nano Architecture for Applications in NIR Detectors

PubMed Central

Khosroabadi, Akram A.; Gangopadhyay, Palash; Hernandez, Steven; Kim, Kyungjo; Peyghambarian, Nasser; Norwood, Robert A.

2015-01-01

We present a proof of concept for tunable plasmon resonance frequencies in a core shell nano-architectured hybrid metal-semiconductor multilayer structure, with Ag as the active shell and ITO as the dielectric modulation media. Our method relies on the collective change in the dielectric function within the metal semiconductor interface to control the surface. Here we report fabrication and optical spectroscopy studies of large-area, nanostructured, hybrid silver and indium tin oxide (ITO) structures, with feature sizes below 100 nm and a controlled surface architecture. The optical and electrical properties of these core shell electrodes, including the surface plasmon frequency, can be tuned by suitably changing the order and thickness of the dielectric layers. By varying the dimensions of the nanopillars, the surface plasmon wavelength of the nanopillar Ag can be tuned from 650 to 690 nm. Adding layers of ITO to the structure further shifts the resonance wavelength toward the IR region and, depending on the sequence and thickness of the layers within the structure, we show that such structures can be applied in sensing devices including enhancing silicon as a photodetection material. PMID:28793489

Nanoscale observation of organic thin film by atomic force microscopy

NASA Astrophysics Data System (ADS)

Mochizuki, Shota; Uruma, Takeshi; Satoh, Nobuo; Saravanan, Shanmugam; Soga, Tetsuo

2017-08-01

Organic photovoltaics (OPVs) fabricated using organic semiconductors and hybrid solar cells (HSCs) based on organic semiconductors/quantum dots (QDs) have been attracting significant attention owing to their potential use in low-cost solar energy-harvesting applications and flexible, light-weight, colorful, large-area devices. In this study, we observed and evaluated the surface of a photoelectric conversion layer (active layer) of the OPVs and HSCs based on phenyl-C61-butyric acid methyl ester (PCBM), poly(3-hexylthiophene) (P3HT), and zinc oxide (ZnO) nanoparticles. The experiment was performed using atomic force microscopy (AFM) combined with a frequency modulation detector (FM detector) and a contact potential difference (CPD) detection circuit. We experimentally confirmed the changes in film thickness and surface potential, as affected by the ZnO nanoparticle concentration. From the experimental results, we confirmed that ZnO nanoparticles possibly affect the structures of PCBM and P3HT. Also, we prepared an energy band diagram on the basis of the observation results, and analyzed the energy distribution inside the active layer.

Method of manufacturing semiconductor having group II-group VI compounds doped with nitrogen

DOEpatents

Compaan, Alvin D.; Price, Kent J.; Ma, Xianda; Makhratchev, Konstantin

2005-02-08

A method of making a semiconductor comprises depositing a group II-group VI compound onto a substrate in the presence of nitrogen using sputtering to produce a nitrogen-doped semiconductor. This method can be used for making a photovoltaic cell using sputtering to apply a back contact layer of group II-group VI compound to a substrate in the presence of nitrogen, the back coating layer being doped with nitrogen. A semiconductor comprising a group II-group VI compound doped with nitrogen, and a photovoltaic cell comprising a substrate on which is deposited a layer of a group II-group VI compound doped with nitrogen, are also included.

Fabrication of optically reflecting ohmic contacts for semiconductor devices

DOEpatents

Sopori, B.L.

1995-07-04

A method is provided to produce a low-resistivity ohmic contact having high optical reflectivity on one side of a semiconductor device. The contact is formed by coating the semiconductor substrate with a thin metal film on the back reflecting side and then optically processing the wafer by illuminating it with electromagnetic radiation of a predetermined wavelength and energy level through the front side of the wafer for a predetermined period of time. This method produces a thin epitaxial alloy layer between the semiconductor substrate and the metal layer when a crystalline substrate is used. The alloy layer provides both a low-resistivity ohmic contact and high optical reflectance. 5 figs.

Semiconductor devices incorporating multilayer interference regions

DOEpatents

Biefeld, R.M.; Drummond, T.J.; Gourley, P.L.; Zipperian, T.E.

1987-08-31

A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration. 8 figs.

Whiskerless Schottky diode

NASA Technical Reports Server (NTRS)

Bishop, William L. (Inventor); Mcleod, Kathleen A. (Inventor); Mattauch, Robert J. (Inventor)

1991-01-01

A Schottky diode for millimeter and submillimeter wave applications is comprised of a multi-layered structure including active layers of gallium arsenide on a semi-insulating gallium arsenide substrate with first and second insulating layers of silicon dioxide on the active layers of gallium arsenide. An ohmic contact pad lays on the silicon dioxide layers. An anode is formed in a window which is in and through the silicon dioxide layers. An elongated contact finger extends from the pad to the anode and a trench, preferably a transverse channel or trench of predetermined width, is formed in the active layers of the diode structure under the contact finger. The channel extends through the active layers to or substantially to the interface of the semi-insulating gallium arsenide substrate and the adjacent gallium arsenide layer which constitutes a buffer layer. Such a structure minimizes the effect of the major source of shunt capacitance by interrupting the current path between the conductive layers beneath the anode contact pad and the ohmic contact. Other embodiments of the diode may substitute various insulating or semi-insulating materials for the silicon dioxide, various semi-conductors for the active layers of gallium arsenide, and other materials for the substrate, which may be insulating or semi-insulating.

Technology and characterization of Thin-Film Transistors (TFTs) with a-IGZO semiconductor and high-k dielectric layer

NASA Astrophysics Data System (ADS)

Mroczyński, R.; Wachnicki, Ł.; Gierałtowska, S.

2016-12-01

In this work, we present the design of the technology and fabrication of TFTs with amorphous IGZO semiconductor and high-k gate dielectric layer in the form of hafnium oxide (HfOx). In the course of this work, the IGZO fabrication was optimized by means of Taguchi orthogonal tables approach in order to obtain an active semiconductor with reasonable high concentration of charge carriers, low roughness and relatively high mobility. The obtained Thin-Film Transistors can be characterized by very good electrical parameters, i.e., the effective mobility (μeff ≍ 12.8 cm2V-1s-1) significantly higher than that for a-Si TFTs (μeff ≍ 1 cm2V-1s-1). However, the value of sub-threshold swing (i.e., 640 mV/dec) points that the interfacial properties of IGZO/HfOx stack is characterized by high value of interface states density (Dit) which, in turn, demands further optimization for future applications of the demonstrated TFT structures.

Surface acceptor states in MBE-grown CdTe layers

NASA Astrophysics Data System (ADS)

Wichrowska, Karolina; Wosinski, Tadeusz; Tkaczyk, Zbigniew; Kolkovsky, Valery; Karczewski, Grzegorz

2018-04-01

A deep-level hole trap associated with surface defect states has been revealed with deep-level transient spectroscopy investigations of metal-semiconductor junctions fabricated on nitrogen doped p-type CdTe layers grown by the molecular-beam epitaxy technique. The trap displayed the hole-emission activation energy of 0.33 eV and the logarithmic capture kinetics indicating its relation to extended defect states at the metal-semiconductor interface. Strong electric-field-induced enhancement of the thermal emission rate of holes from the trap has been attributed to the phonon-assisted tunneling effect from defect states involving very large lattice relaxation around the defect and metastability of its occupied state. Passivation with ammonium sulfide of the CdTe surface, prior to metallization, results in a significant decrease in the trap density. It also results in a distinct reduction in the width of the surface-acceptor-state-induced hysteresis loops in the capacitance vs. voltage characteristics of the metal-semiconductor junctions.

Effects of Contact-Induced Doping on the Behaviors of Organic Photovoltaic Devices

DOE PAGES

Wang, Jian; Xu, Liang; Lee, Yun -Ju; ...

2015-10-09

Substrates can significantly affect the electronic properties of organic semiconductors. In this paper, we report the effects of contact-induced doping, arising from charge transfer between a high work function hole extraction layer (HEL) and the organic active layer, on organic photovoltaic device performance. Employing a high work function HEL is found to increase doping in the active layer and decrease photocurrent. Combined experimental and modeling investigations reveal that higher doping increases polaron–exciton quenching and carrier recombination within the field-free region. Consequently, there exists an optimal HEL work function that enables a large built-in field while keeping the active layer dopingmore » low. This value is found to be ~0.4 eV larger than the pinning level of the active layer material. As a result, these understandings establish a criterion for optimal design of the HEL when adapting a new active layer system and can shed light on optimizing performance in other organic electronic devices.« less

Context-based automated defect classification system using multiple morphological masks

DOEpatents

Gleason, Shaun S.; Hunt, Martin A.; Sari-Sarraf, Hamed

2002-01-01

Automatic detection of defects during the fabrication of semiconductor wafers is largely automated, but the classification of those defects is still performed manually by technicians. This invention includes novel digital image analysis techniques that generate unique feature vector descriptions of semiconductor defects as well as classifiers that use these descriptions to automatically categorize the defects into one of a set of pre-defined classes. Feature extraction techniques based on multiple-focus images, multiple-defect mask images, and segmented semiconductor wafer images are used to create unique feature-based descriptions of the semiconductor defects. These feature-based defect descriptions are subsequently classified by a defect classifier into categories that depend on defect characteristics and defect contextual information, that is, the semiconductor process layer(s) with which the defect comes in contact. At the heart of the system is a knowledge database that stores and distributes historical semiconductor wafer and defect data to guide the feature extraction and classification processes. In summary, this invention takes as its input a set of images containing semiconductor defect information, and generates as its output a classification for the defect that describes not only the defect itself, but also the location of that defect with respect to the semiconductor process layers.

Real Time Imaging Analysis Using a Terahertz Quantum Cascade Laser and a Microbolometer Focal Plane Array

DTIC Science & Technology

2008-12-01

evident from Figure 7 that, if the applied bias is not correct, it is very likely that electrons will not tunnel into their intended energy state...the theoretical laser contrasts sharply to that of semiconductor lasers. Semiconductor lasers rely on electron hole recombination or interband ...the active layer of a forward- biased pn junction [26]. In contrast to this, the QCL is a unipolar device that uses a quantum well (QW) structure

Semiconductor ferroelectric compositions and their use in photovoltaic devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rappe, Andrew M; Davies, Peter K; Spanier, Jonathan E

Disclosed herein are ferroelectric perovskites characterized as having a band gap, Egap, of less than 2.5 eV. Also disclosed are compounds comprising a solid solution of KNbO3 and BaNi1/2Nb1/2O3-delta, wherein delta is in the range of from 0 to about 1. The specification also discloses photovoltaic devices comprising one or more solar absorbing layers, wherein at least one of the solar absorbing layers comprises a semiconducting ferroelectric layer. Finally, this patent application provides solar cell, comprising: a heterojunction of n- and p-type semiconductors characterized as comprising an interface layer disposed between the n- and p-type semiconductors, the interface layer comprisingmore » a semiconducting ferroelectric absorber layer capable of enhancing light absorption and carrier separation.« less

Integrated Broadband Quantum Cascade Laser

NASA Technical Reports Server (NTRS)

Mansour, Kamjou (Inventor); Soibel, Alexander (Inventor)

2016-01-01

A broadband, integrated quantum cascade laser is disclosed, comprising ridge waveguide quantum cascade lasers formed by applying standard semiconductor process techniques to a monolithic structure of alternating layers of claddings and active region layers. The resulting ridge waveguide quantum cascade lasers may be individually controlled by independent voltage potentials, resulting in control of the overall spectrum of the integrated quantum cascade laser source. Other embodiments are described and claimed.

High Performance and Highly Reliable ZnO Thin Film Transistor Fabricated by Atomic Layer Deposition for Next Generation Displays

DTIC Science & Technology

2011-08-19

zinc oxide ( ZnO ) thin film as an active channel layer in TFT has become of great interest owing to their specific...630-0192 Japan Phone: +81-743-72-6060 Fax: +81-743-72-6069 E-mail: uraoka@ms.naist.jp Keywords: zinc oxide , thin film transistors , atomic layer...deposition Symposium topic: Transparent Semiconductors Oxides [Abstract] In this study, we fabricated TFTs using ZnO thin film as the

High efficiency photovoltaic device

DOEpatents

Guha, Subhendu; Yang, Chi C.; Xu, Xi Xiang

1999-11-02

An N-I-P type photovoltaic device includes a multi-layered body of N-doped semiconductor material which has an amorphous, N doped layer in contact with the amorphous body of intrinsic semiconductor material, and a microcrystalline, N doped layer overlying the amorphous, N doped material. A tandem device comprising stacked N-I-P cells may further include a second amorphous, N doped layer interposed between the microcrystalline, N doped layer and a microcrystalline P doped layer. Photovoltaic devices thus configured manifest improved performance, particularly when configured as tandem devices.

Effect of the waveguide layer thickness on output characteristics of semiconductor lasers with emission wavelength from 1500 to 1600 nm

NASA Astrophysics Data System (ADS)

Marmalyuk, A. A.; Ryaboshtan, Yu L.; Gorlachuk, P. V.; Ladugin, M. A.; Padalitsa, A. A.; Slipchenko, S. O.; Lyutetskiy, A. V.; Veselov, D. A.; Pikhtin, N. A.

2018-03-01

The effect of the waveguide layer thickness on output characteristics of AlGaInAs/InP quantum-well semiconductor lasers is analysed. The samples of semiconductor lasers with narrow and wide waveguides are experimentally fabricated. Their comparison is carried out and the advantages of particular constructions depending on the current pump are demonstrated.

Flat-lying semiconductor-insulator interfacial layer in DNTT thin films.

PubMed

Jung, Min-Cherl; Leyden, Matthew R; Nikiforov, Gueorgui O; Lee, Michael V; Lee, Han-Koo; Shin, Tae Joo; Takimiya, Kazuo; Qi, Yabing

2015-01-28

The molecular order of organic semiconductors at the gate dielectric is the most critical factor determining carrier mobility in thin film transistors since the conducting channel forms at the dielectric interface. Despite its fundamental importance, this semiconductor-insulator interface is not well understood, primarily because it is buried within the device. We fabricated dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) thin film transistors by thermal evaporation in vacuum onto substrates held at different temperatures and systematically correlated the extracted charge mobility to the crystal grain size and crystal orientation. As a result, we identify a molecular layer of flat-lying DNTT molecules at the semiconductor-insulator interface. It is likely that such a layer might form in other material systems as well, and could be one of the factors reducing charge transport. Controlling this interfacial flat-lying layer may raise the ultimate possible device performance for thin film devices.

Wavelength-division multiplexed optical integrated circuit with vertical diffraction grating

NASA Technical Reports Server (NTRS)

Lang, Robert J. (Inventor); Forouhar, Siamak (Inventor)

1994-01-01

A semiconductor optical integrated circuit for wave division multiplexing has a semiconductor waveguide layer, a succession of diffraction grating points in the waveguide layer along a predetermined diffraction grating contour, a semiconductor diode array in the waveguide layer having plural optical ports facing the succession of diffraction grating points along a first direction, respective semiconductor diodes in the array corresponding to respective ones of a predetermined succession of wavelengths, an optical fiber having one end thereof terminated at the waveguide layer, the one end of the optical fiber facing the succession of diffraction grating points along a second direction, wherein the diffraction grating points are spatially distributed along the predetermined contour in such a manner that the succession of diffraction grating points diffracts light of respective ones of the succession of wavelengths between the one end of the optical fiber and corresponding ones of the optical ports.

Dye-sensitized solar cells

DOEpatents

Skotheim, T.A.

1980-03-04

A low-cost dye-sensitized Schottky barrier solar cell is comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent. 3 figs.

Dye-sensitized solar cells

DOEpatents

Skotheim, Terje A. [Berkeley, CA

1980-03-04

A low-cost dye-sensitized Schottky barrier solar cell comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent.

Dye-sensitized Schottky barrier solar cells

DOEpatents

Skotheim, Terje A.

1978-01-01

A low-cost dye-sensitized Schottky barrier solar cell comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent.

Controlled Chemical Doping of Semiconductor Nanocrystals Using Redox Buffers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Engel, Jesse H.; Surendranath, Yogesh; Alivisatos, Paul

Semiconductor nanocrystal solids are attractive materials for active layers in next-generation optoelectronic devices; however, their efficient implementation has been impeded by the lack of precise control over dopant concentrations. Herein we demonstrate a chemical strategy for the controlled doping of nanocrystal solids under equilibrium conditions. Exposing lead selenide nanocrystal thin films to solutions containing varying proportions of decamethylferrocene and decamethylferrocenium incrementally and reversibly increased the carrier concentration in the solid by 2 orders of magnitude from their native values. This application of redox buffers for controlled doping provides a new method for the precise control of the majority carrier concentrationmore » in porous semiconductor thin films.« less

Quantum well multijunction photovoltaic cell

DOEpatents

Chaffin, R.J.; Osbourn, G.C.

1983-07-08

A monolithic, quantum well, multilayer photovoltaic cell comprises a p-n junction comprising a p-region on one side and an n-region on the other side, each of which regions comprises a series of at least three semiconductor layers, all p-type in the p-region and all n-type in the n-region; each of said series of layers comprising alternating barrier and quantum well layers, each barrier layer comprising a semiconductor material having a first bandgap and each quantum well layer comprising a semiconductor material having a second bandgap when in bulk thickness which is narrower than said first bandgap, the barrier layers sandwiching each quantum well layer and each quantum well layer being sufficiently thin that the width of its bandgap is between said first and second bandgaps, such that radiation incident on said cell and above an energy determined by the bandgap of the quantum well layers will be absorbed and will produce an electrical potential across said junction.

Quantum well multijunction photovoltaic cell

DOEpatents

Chaffin, Roger J.; Osbourn, Gordon C.

1987-01-01

A monolithic, quantum well, multilayer photovoltaic cell comprises a p-n junction comprising a p-region on one side and an n-region on the other side, each of which regions comprises a series of at least three semiconductor layers, all p-type in the p-region and all n-type in the n-region; each of said series of layers comprising alternating barrier and quantum well layers, each barrier layer comprising a semiconductor material having a first bandgap and each quantum well layer comprising a semiconductor material having a second bandgap when in bulk thickness which is narrower than said first bandgap, the barrier layers sandwiching each quantum well layer and each quantum well layer being sufficiently thin that the width of its bandgap is between said first and second bandgaps, such that radiation incident on said cell and above an energy determined by the bandgap of the quantum well layers will be absorbed and will produce an electrical potential across said junction.

Mixed ternary heterojunction solar cell

DOEpatents

Chen, Wen S.; Stewart, John M.

1992-08-25

A thin film heterojunction solar cell and a method of making it has a p-type layer of mixed ternary I-III-VI.sub.2 semiconductor material in contact with an n-type layer of mixed binary II-VI semiconductor material. The p-type semiconductor material includes a low resistivity copper-rich region adjacent the back metal contact of the cell and a composition gradient providing a minority carrier mirror that improves the photovoltaic performance of the cell. The p-type semiconductor material preferably is CuInGaSe.sub.2 or CuIn(SSe).sub.2.

Photoelectrochemical cells for conversion of solar energy to electricity and methods of their manufacture

DOEpatents

Skotheim, Terje

1984-04-10

A photoelectric device is disclosed which comprises first and second layers of semiconductive material, each of a different bandgap, with a layer of dry solid polymer electrolyte disposed between the two semiconductor layers. A layer of a polymer blend of a highly conductive polymer and a solid polymer electrolyte is further interposed between the dry solid polymer electrolyte and the first semiconductor layer. A method of manufacturing such devices is also disclosed.

Role of order and disorder on the electronic performances of oxide semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Martins, R.; Barquinha, P.; Ferreira, I.; Pereira, L.; Gonçalves, G.; Fortunato, E.

2007-02-01

The role of order and disorder on the electronic performances of n-type ionic oxides such as zinc oxide, gallium zinc oxide, and indium zinc oxide used as active (channel) or passive (drain/source) layers in thin film transistors (TFTs) processed at room temperature are discussed, taking as reference the known behavior observed in conventional covalent semiconductors such as silicon. The work performed shows that while in the oxide semiconductors the Fermi level can be pinned up within the conduction band, independent of the state of order, the same does not happen with silicon. Besides, in the oxide semiconductors the carrier mobility is not bandtail limited and so disorder does not affect so strongly the mobility as it happens in covalent semiconductors. The electrical properties of the oxide films (resistivity, carrier concentration, and mobility) are highly dependent on the oxygen vacancies (source of free carriers), which can be controlled by changing the oxygen partial pressure during the deposition process and/or by adding other metal ions to the matrix. In this case, we make the oxide matrix less sensitive to the presence of oxygen, widening the range of oxygen partial pressures that can be used and thus improving the process control of the film resistivity. The results obtained in fully transparent TFT using polycrystalline ZnO or amorphous indium zinc oxide (IZO) as channel layers and highly conductive poly/nanocrystalline ZGO films or amorphous IZO as drain/source layers show that both devices work in the enhancement mode, but the TFT with the highest electronic saturation mobility and on/off ratio 49.9cm2/Vs and 4.3×108, respectively, are the ones in which the active and passive layers are amorphous. The ZnO TFT whose channel is based on polycrystalline ZnO, the mobility and on/off ratio are, respectively, 26cm2/Vs and 3×106. This behavior is attributed to the fact that the electronic transport is governed by the s-like metal cation conduction bands, not significantly affected by any type of angular disorder promoted by the 2p O states related to the valence band, or small amounts of incorporated metal impurities that lead to a better control of vacancies and of the TFT off current.

Near single-crystalline, high-carrier-mobility silicon thin film on a polycrystalline/amorphous substrate

DOEpatents

Findikoglu, Alp T [Los Alamos, NM; Jia, Quanxi [Los Alamos, NM; Arendt, Paul N [Los Alamos, NM; Matias, Vladimir [Santa Fe, NM; Choi, Woong [Los Alamos, NM

2009-10-27

A template article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material; is provided, together with a semiconductor article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material, and, a top-layer of semiconductor material upon the buffer material layer.

Method for sputtering a PIN microcrystalline/amorphous silicon semiconductor device with the P and N-layers sputtered from boron and phosphorous heavily doped targets

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-04-02

A silicon PIN microcrystalline/amorphous silicon semiconductor device is constructed by the sputtering of N, and P layers of silicon from silicon doped targets and the I layer from an undoped target, and at least one semi-transparent ohmic electrode.

Electrodynamic properties of a hypercrystal with ferrite and semiconductor layers in an external magnetic field

NASA Astrophysics Data System (ADS)

Fedorin, Illia V.

2018-01-01

Electrodynamic properties of a photonic hypercrystal formed by periodically alternating two types of anisotropic metamaterials are studied. The first metamaterial consists of ferrite and dielectric layers, while the second metamaterial consists of semiconductor and dielectric layers. The system is assumed to be placed in an external magnetic field, which applied parallel to the boundaries of the layers. An effective medium theory which is suitable for calculation of properties of long-wavelength electromagnetic modes is applied in order to derive averaged expressions for effective constitutive parameters. It has been shown that providing a conscious choice of the constitutive parameters and material fractions of magnetic, semiconductor, and dielectric layers, the system under study shows hypercrystal properties for both TE and TM waves in the different frequency ranges.

Process for fabricating polycrystalline semiconductor thin-film solar cells, and cells produced thereby

DOEpatents

Wu, Xuanzhi; Sheldon, Peter

2000-01-01

A novel, simplified method for fabricating a thin-film semiconductor heterojunction photovoltaic device includes initial steps of depositing a layer of cadmium stannate and a layer of zinc stannate on a transparent substrate, both by radio frequency sputtering at ambient temperature, followed by the depositing of dissimilar layers of semiconductors such as cadmium sulfide and cadmium telluride, and heat treatment to convert the cadmium stannate to a substantially single-phase material of a spinel crystal structure. Preferably, the cadmium sulfide layer is also deposited by radio frequency sputtering at ambient temperature, and the cadmium telluride layer is deposited by close space sublimation at an elevated temperature effective to convert the amorphous cadmium stannate to the polycrystalline cadmium stannate with single-phase spinel structure.

Architectures and criteria for the design of high efficiency organic photovoltaic cells

DOEpatents

Rand, Barry; Forrest, Stephen R; Pendergrast Burk, Diane

2015-03-31

A method for fabricating an organic photovoltaic cell includes providing a first electrode; depositing a series of at least seven layers onto the first electrode, each layer consisting essentially of a different organic semiconductor material, the organic semiconductor material of at least an intermediate layer of the sequence being a photoconductive material; and depositing a second electrode onto the sequence of at least seven layers. One of the first electrode and the second electrode is an anode and the other is a cathode. The organic semiconductor materials of the series of at least seven layers are arranged to provide a sequence of decreasing lowest unoccupied molecular orbitals (LUMOs) and a sequence of decreasing highest occupied molecular orbitals (HOMOs) across the series from the anode to the cathode.

Charge dissipative dielectric for cryogenic devices

NASA Technical Reports Server (NTRS)

Cantor, Robin Harold (Inventor); Hall, John Addison (Inventor)

2007-01-01

A Superconducting Quantum Interference Device (SQUID) is disclosed comprising a pair of resistively shunted Josephson junctions connected in parallel within a superconducting loop and biased by an external direct current (dc) source. The SQUID comprises a semiconductor substrate and at least one superconducting layer. The metal layer(s) are separated by or covered with a semiconductor material layer having the properties of a conductor at room temperature and the properties of an insulator at operating temperatures (generally less than 100 Kelvins). The properties of the semiconductor material layer greatly reduces the risk of electrostatic discharge that can damage the device during normal handling of the device at room temperature, while still providing the insulating properties desired to allow normal functioning of the device at its operating temperature. A method of manufacturing the SQUID device is also disclosed.

Ambipolar Small-Molecule:Polymer Blend Semiconductors for Solution-Processable Organic Field-Effect Transistors.

PubMed

Kang, Minji; Hwang, Hansu; Park, Won-Tae; Khim, Dongyoon; Yeo, Jun-Seok; Kim, Yunseul; Kim, Yeon-Ju; Noh, Yong-Young; Kim, Dong-Yu

2017-01-25

We report on the fabrication of an organic thin-film semiconductor formed using a blend solution of soluble ambipolar small molecules and an insulating polymer binder that exhibits vertical phase separation and uniform film formation. The semiconductor thin films are produced in a single step from a mixture containing a small molecular semiconductor, namely, quinoidal biselenophene (QBS), and a binder polymer, namely, poly(2-vinylnaphthalene) (PVN). Organic field-effect transistors (OFETs) based on QBS/PVN blend semiconductor are then assembled using top-gate/bottom-contact device configuration, which achieve almost four times higher mobility than the neat QBS semiconductor. Depth profile via secondary ion mass spectrometry and atomic force microscopy images indicate that the QBS domains in the films made from the blend are evenly distributed with a smooth morphology at the bottom of the PVN layer. Bias stress test and variable-temperature measurements on QBS-based OFETs reveal that the QBS/PVN blend semiconductor remarkably reduces the number of trap sites at the gate dielectric/semiconductor interface and the activation energy in the transistor channel. This work provides a one-step solution processing technique, which makes use of soluble ambipolar small molecules to form a thin-film semiconductor for application in high-performance OFETs.

Back wall solar cell

NASA Technical Reports Server (NTRS)

Brandhorst, H. W., Jr. (Inventor)

1978-01-01

A solar cell is disclosed which comprises a first semiconductor material of one conductivity type with one face having the same conductivity type but more heavily doped to form a field region arranged to receive the radiant energy to be converted to electrical energy, and a layer of a second semiconductor material, preferably highly doped, of opposite conductivity type on the first semiconductor material adjacent the first semiconductor material at an interface remote from the heavily doped field region. Instead of the opposite conductivity layer, a metallic Schottky diode layer may be used, in which case no additional back contact is needed. A contact such as a gridded contact, previous to the radiant energy may be applied to the heavily doped field region of the more heavily doped, same conductivity material for its contact.

Use of separate ZnTe interface layers to form ohmic contacts to p-CdTe films

DOEpatents

Gessert, T.A.

1999-06-01

A method of is disclosed improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising: depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurium-containing II-VI semiconductor, but thin enough to minimize affects of series resistance; depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; and depositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact. 11 figs.

Use of separate ZnTe interface layers to form OHMIC contacts to p-CdTe films

DOEpatents

Gessert, Timothy A.

1999-01-01

A method of improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising: depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurim-containing II-VI semiconductor, but thin enough to minimize affects of series resistance; depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; and depositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact.

Methodological comparison on hybrid nano organic solar cell fabrication

NASA Astrophysics Data System (ADS)

Vairavan, Rajendaran; Hambali, Nor Azura Malini Ahmad; Wahid, Mohamad Halim Abd; Retnasamy, Vithyacharan; Shahimin, Mukhzeer Mohamad

2018-02-01

The development of low cost solar cells has been the main focus in recent years. This has lead to the generation of photovoltaic cells based on hybrid of nanoparticle-organic polymer materials. This type of hybrid photovoltaic cells can overcome the problem of polymeric devices having low optical absorption and carrier mobilities. The hybrid cell has the potential of bridging the efficiency gap, which in present in organic and inorganic semiconductor materials. This project focuses on obtaining an hybrid active layer consisting of nanoparticles and organic polymer, to understand the parameter involved in obtaining this active layer and finally to investigate if the addition of nano particles in to the active layer could enhance the output of the hybrid solar cell. The hybrid active layer have will be deposited using the spin coating technique by using CdTe, CdS nano particles mixed with poly (2-methoxy,5-(2-ethyl-hexyloxy)-p-phenylvinylene)MEH-PPV.

A Designed Room Temperature Multilayered Magnetic Semiconductor

NASA Astrophysics Data System (ADS)

Bouma, Dinah Simone; Charilaou, Michalis; Bordel, Catherine; Duchin, Ryan; Barriga, Alexander; Farmer, Adam; Hellman, Frances; Materials Science Division, Lawrence Berkeley National Lab Team

2015-03-01

A room temperature magnetic semiconductor has been designed and fabricated by using an epitaxial antiferromagnet (NiO) grown in the (111) orientation, which gives surface uncompensated magnetism for an odd number of planes, layered with the lightly doped semiconductor Al-doped ZnO (AZO). Magnetization and Hall effect measurements of multilayers of NiO and AZO are presented for varying thickness of each. The magnetic properties vary as a function of the number of Ni planes in each NiO layer; an odd number of Ni planes yields on each NiO layer an uncompensated moment which is RKKY-coupled to the moments on adjacent NiO layers via the carriers in the AZO. This RKKY coupling oscillates with the AZO layer thickness, and it disappears entirely in samples where the AZO is replaced with undoped ZnO. The anomalous Hall effect data indicate that the carriers in the AZO are spin-polarized according to the direction of the applied field at both low temperature and room temperature. NiO/AZO multilayers are therefore a promising candidate for spintronic applications demanding a room-temperature semiconductor.

High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

NASA Astrophysics Data System (ADS)

Houin, G.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

2016-09-01

The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance with hysteresis-free characteristics. A number of approaches were applied to simplify the process, improve device performance and decrease the operating voltage: they include an oxide interfacial layer to decrease contact resistance; a polymer passivation layer to optimize semiconductor/dielectric interface and an anodized high-k oxide as dielectric layer for low voltage operation. The devices fabricated on plastic substrate yielded excellent electrical characteristics, showing mobility of 1.6 cm2/Vs, lack of hysteresis, operation below 5 V and on/off current ratio above 105. An OFET model based on variable ranging hopping theory was used to extract the relevant parameters from the transfer and output characteristics, which enabled us to simulate our devices achieving reasonable agreement with the measurements

Amorphous oxide alloys as interfacial layers with broadly tunable electronic structures for organic photovoltaic cells.

PubMed

Zhou, Nanjia; Kim, Myung-Gil; Loser, Stephen; Smith, Jeremy; Yoshida, Hiroyuki; Guo, Xugang; Song, Charles; Jin, Hosub; Chen, Zhihua; Yoon, Seok Min; Freeman, Arthur J; Chang, Robert P H; Facchetti, Antonio; Marks, Tobin J

2015-06-30

In diverse classes of organic optoelectronic devices, controlling charge injection, extraction, and blocking across organic semiconductor-inorganic electrode interfaces is crucial for enhancing quantum efficiency and output voltage. To this end, the strategy of inserting engineered interfacial layers (IFLs) between electrical contacts and organic semiconductors has significantly advanced organic light-emitting diode and organic thin film transistor performance. For organic photovoltaic (OPV) devices, an electronically flexible IFL design strategy to incrementally tune energy level matching between the inorganic electrode system and the organic photoactive components without varying the surface chemistry would permit OPV cells to adapt to ever-changing generations of photoactive materials. Here we report the implementation of chemically/environmentally robust, low-temperature solution-processed amorphous transparent semiconducting oxide alloys, In-Ga-O and Ga-Zn-Sn-O, as IFLs for inverted OPVs. Continuous variation of the IFL compositions tunes the conduction band minima over a broad range, affording optimized OPV power conversion efficiencies for multiple classes of organic active layer materials and establishing clear correlations between IFL/photoactive layer energetics and device performance.

Abrupt Depletion Layer Approximation for the Metal Insulator Semiconductor Diode.

ERIC Educational Resources Information Center

Jones, Kenneth

1979-01-01

Determines the excess surface change carrier density, surface potential, and relative capacitance of a metal insulator semiconductor diode as a function of the gate voltage, using the precise questions and the equations derived with the abrupt depletion layer approximation. (Author/GA)

Excellent sun-light-driven photocatalytic activity by aurivillius layered perovskites, Bi₅-xLaxTi₃FeO₁₅ (x = 1, 2).

PubMed

Naresh, Gollapally; Mandal, Tapas Kumar

2014-12-10

Aurivillius phase layered perovskites, Bi5-xLaxTi3FeO15 (x = 1, 2) are synthesized by solid-state reaction. The compounds are characterized by powder X-ray diffraction (PXD), field-emission scanning electron microscopy (FE-SEM), energy-dispersive X-ray spectroscopy (EDS), UV-vis diffuse reflectance (UV-vis DRS), and photoluminescence (PL) spectroscopy. UV-vis DRS data revealed that the compounds are visible light absorbing semiconductors with band gaps ranging from ∼2.0-2.7 eV. Photocatalytic activity studies by Rhodamine B (RhB) degradation under sun-light irradiation showed that these layered oxides are very efficient photocatalysts in mild acidic medium. Scavenger test studies demonstrated that the photogenerated holes and superoxide radicals (O2(•-)) are the active species responsible for RhB degradation over the Aurivillius layered perovskites. Comparison of PL intensity, dye adsorption and ζ-potential suggested that a slow e(-)-h(+) recombination and effective dye adsorption are crucial for the degradation process over these photocatalysts. Moreover, relative positioning of the valence and conduction band edges of the semiconductors, O2/O2(•-), (•)OH/H2O potential and HOMO-LUMO levels of RhB appears to be responsible for making the degradation hole-specific. Photocatalytic cycle tests indicated high stability of the catalysts in the reaction medium without any observable loss of activity. This work shows great potential in developing novel photocatalysts with layered structures for sun-light-driven oxidation and degradation processes largely driven by holes and without any intervention of hydroxyl radicals, which is one of the most common reactive oxygen species (ROS) in many advanced oxidation processes.

Resistive switching of Cu/Cu2O junction fabricated using simple thermal oxidation at 423 K for memristor application

NASA Astrophysics Data System (ADS)

Ani, M. H.; Helmi, F.; Herman, S. H.; Noh, S.

2018-01-01

Recently, extensive researches have been done on memristor to replace current memory storage technologies. Study on active layer of memristor mostly involving n-type semiconductor oxide such as TiO2 and ZnO. This paper highlight a simple water vapour oxidation method at 423 K to form Cu/Cu2O electronic junction as a new type of memristor. Cu2O is a p-type semiconductor oxide, was used as the active layer of memristor. Cu/Cu2O/Au memristor was fabricated by thermal oxidation of copper foil, followed by sputtering of gold. Structural, morphological and memristive properties were characterized using XRD, FESEM, and current-voltage, I-V measurement respectively. Its memristivity was indentified by pinch hysteresis loop and measurement of high resistance state (HRS) and low resistance state (LRS) of the sample. The Cu/Cu2O/Au memristor demonstrates comparable performances to previous studies using other methods.

SLS complementary logic devices with increase carrier mobility

DOEpatents

Chaffin, R.J.; Osbourn, G.C.; Zipperian, T.E.

1991-07-09

In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated. 5 figures.

SLS complementary logic devices with increase carrier mobility

DOEpatents

Chaffin, Roger J.; Osbourn, Gordon C.; Zipperian, Thomas E.

1991-01-01

In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubenko, E. B., E-mail: eugene.chubenko@gmail.com; Redko, S. V.; Sherstnyov, A. I.

2016-03-15

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materialsmore » on the basis of porous silicon and nanostructures with a high aspect ratio.« less

Phase-separated, epitaxial composite cap layers for electronic device applications and method of making the same

DOEpatents

Aytug, Tolga [Knoxville, TN; Paranthaman, Mariappan Parans [Knoxville, TN; Polat, Ozgur [Knoxville, TN

2012-07-17

An electronic component that includes a substrate and a phase-separated layer supported on the substrate and a method of forming the same are disclosed. The phase-separated layer includes a first phase comprising lanthanum manganate (LMO) and a second phase selected from a metal oxide (MO), metal nitride (MN), a metal (Me), and combinations thereof. The phase-separated material can be an epitaxial layer and an upper surface of the phase-separated layer can include interfaces between the first phase and the second phase. The phase-separated layer can be supported on a buffer layer comprising a composition selected from the group consisting of IBAD MgO, LMO/IBAD-MgO, homoepi-IBAD MgO and LMO/homoepi-MgO. The electronic component can also include an electronically active layer supported on the phase-separated layer. The electronically active layer can be a superconducting material, a ferroelectric material, a multiferroic material, a magnetic material, a photovoltaic material, an electrical storage material, and a semiconductor material.

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

Traditional Semiconductors in the Two-Dimensional Limit.

PubMed

Lucking, Michael C; Xie, Weiyu; Choe, Duk-Hyun; West, Damien; Lu, Toh-Ming; Zhang, S B

2018-02-23

Interest in two-dimensional materials has exploded in recent years. Not only are they studied due to their novel electronic properties, such as the emergent Dirac fermion in graphene, but also as a new paradigm in which stacking layers of distinct two-dimensional materials may enable different functionality or devices. Here, through first-principles theory, we reveal a large new class of two-dimensional materials which are derived from traditional III-V, II-VI, and I-VII semiconductors. It is found that in the ultrathin limit the great majority of traditional binary semiconductors studied (a series of 28 semiconductors) are not only kinetically stable in a two-dimensional double layer honeycomb structure, but more energetically stable than the truncated wurtzite or zinc-blende structures associated with three dimensional bulk. These findings both greatly increase the landscape of two-dimensional materials and also demonstrate that in the double layer honeycomb form, even ordinary semiconductors, such as GaAs, can exhibit exotic topological properties.

Long wavelength, high gain InAsSb strained-layer superlattice photoconductive detectors

DOEpatents

Biefeld, Robert M.; Dawson, L. Ralph; Fritz, Ian J.; Kurtz, Steven R.; Zipperian, Thomas E.

1991-01-01

A high gain photoconductive device for 8 to 12 .mu.m wavelength radiation including an active semiconductor region extending from a substrate to an exposed face, the region comprising a strained-layer superlattice of alternating layers of two different InAs.sub.1-x Sb.sub.x compounds having x>0.75. A pair of spaced electrodes are provided on the exposed face, and changes in 8 to 12 .mu.m radiation on the exposed face cause a large photoconductive gain between the spaced electrodes.

Cadmium-free junction fabrication process for CuInSe.sub.2 thin film solar cells

DOEpatents

Ramanathan, Kannan V.; Contreras, Miguel A.; Bhattacharya, Raghu N.; Keane, James; Noufi, Rommel

1999-01-01

The present invention provides an economical, simple, dry and controllable semiconductor layer junction forming process to make cadmium free high efficiency photovoltaic cells having a first layer comprised primarily of copper indium diselenide having a thin doped copper indium diselenide n-type region, generated by thermal diffusion with a group II(b) element such as zinc, and a halide, such as chlorine, and a second layer comprised of a conventional zinc oxide bilayer. A photovoltaic device according the present invention includes a first thin film layer of semiconductor material formed primarily from copper indium diselenide. Doping of the copper indium diselenide with zinc chloride is accomplished using either a zinc chloride solution or a solid zinc chloride material. Thermal diffusion of zinc chloride into the copper indium diselenide upper region creates the thin n-type copper indium diselenide surface. A second thin film layer of semiconductor material comprising zinc oxide is then applied in two layers. The first layer comprises a thin layer of high resistivity zinc oxide. The second relatively thick layer of zinc oxide is doped to exhibit low resistivity.

Scalable quantum computer architecture with coupled donor-quantum dot qubits

DOEpatents

Schenkel, Thomas; Lo, Cheuk Chi; Weis, Christoph; Lyon, Stephen; Tyryshkin, Alexei; Bokor, Jeffrey

2014-08-26

A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, wherein a first voltage applied across at least one pair of the aligned quantum dot and donor atom controls a donor-quantum dot coupling. A method of performing quantum computing in a scalable architecture quantum computing apparatus includes arranging a pattern of single spin memory donor atoms in a semiconductor layer, forming a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, applying a first voltage across at least one aligned pair of a quantum dot and donor atom to control a donor-quantum dot coupling, and applying a second voltage between one or more quantum dots to control a Heisenberg exchange J coupling between quantum dots and to cause transport of a single spin polarized electron between quantum dots.

Self-cleaning and surface chemical reactions during hafnium dioxide atomic layer deposition on indium arsenide.

PubMed

Timm, Rainer; Head, Ashley R; Yngman, Sofie; Knutsson, Johan V; Hjort, Martin; McKibbin, Sarah R; Troian, Andrea; Persson, Olof; Urpelainen, Samuli; Knudsen, Jan; Schnadt, Joachim; Mikkelsen, Anders

2018-04-12

Atomic layer deposition (ALD) enables the ultrathin high-quality oxide layers that are central to all modern metal-oxide-semiconductor circuits. Crucial to achieving superior device performance are the chemical reactions during the first deposition cycle, which could ultimately result in atomic-scale perfection of the semiconductor-oxide interface. Here, we directly observe the chemical reactions at the surface during the first cycle of hafnium dioxide deposition on indium arsenide under realistic synthesis conditions using photoelectron spectroscopy. We find that the widely used ligand exchange model of the ALD process for the removal of native oxide on the semiconductor and the simultaneous formation of the first hafnium dioxide layer must be significantly revised. Our study provides substantial evidence that the efficiency of the self-cleaning process and the quality of the resulting semiconductor-oxide interface can be controlled by the molecular adsorption process of the ALD precursors, rather than the subsequent oxide formation.

Measuring the complete cross-cell carrier mobility distributions in bulk heterojunction solar cells

NASA Astrophysics Data System (ADS)

Seifter, Jason; Sun, Yanming; Choi, Hyosung; Lee, Byoung Hoon; Heeger, Alan

2015-03-01

Carbon nanotube-enabled, vertical, organic field effect transistors (CN-VFETs) based on the small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) have demonstrated high current, low-power operation suitable for driving active matix organic light emitting diode (AMOLED) displays. This performance is achieved without the need for costly high-resolution patterning, despite the low mobility of the organic semiconductor, by employing sub-micron channel widths, defined in the vertical devices by the thickness of the semiconducting layer. Replacing the thermally evaporated small molecule semiconductor with a solution-processed polymer would possibly further simplify the fabrication process and reduce manufacturing cost. Here we investigate several polymer systems as wide bandgap semiconducting channel layers for potentially air stable and transparent CN-VFETs. The field effect mobility and optical transparency of the polymer layers are determined, and the performance and air stability of CN-VFET devices are measured. A. S. gratefully acknowledges support from the National Science Foundation under DMR-1156737.

Digital Alloy Absorber for Photodetectors

NASA Technical Reports Server (NTRS)

Hill, Cory J. (Inventor); Ting, David Z. (Inventor); Gunapala, Sarath D. (Inventor)

2016-01-01

In order to increase the spectral response range and improve the mobility of the photo-generated carriers (e.g. in an nBn photodetector), a digital alloy absorber may be employed by embedding one (or fraction thereof) to several monolayers of a semiconductor material (insert layers) periodically into a different host semiconductor material of the absorber layer. The semiconductor material of the insert layer and the host semiconductor materials may have lattice constants that are substantially mismatched. For example, this may performed by periodically embedding monolayers of InSb into an InAsSb host as the absorption region to extend the cutoff wavelength of InAsSb photodetectors, such as InAsSb based nBn devices. The described technique allows for simultaneous control of alloy composition and net strain, which are both key parameters for the photodetector operation.

GUARD RING SEMICONDUCTOR JUNCTION

DOEpatents

Goulding, F.S.; Hansen, W.L.

1963-12-01

A semiconductor diode having a very low noise characteristic when used under reverse bias is described. Surface leakage currents, which in conventional diodes greatly contribute to noise, are prevented from mixing with the desired signal currents. A p-n junction is formed with a thin layer of heavily doped semiconductor material disposed on a lightly doped, physically thick base material. An annular groove cuts through the thin layer and into the base for a short distance, dividing the thin layer into a peripheral guard ring that encircles the central region. Noise signal currents are shunted through the guard ring, leaving the central region free from such currents. (AEC)

Self bleaching photoelectrochemical-electrochromic device

DOEpatents

Bechinger, Clemens S.; Gregg, Brian A.

2002-04-09

A photoelectrochemical-electrochromic device comprising a first transparent electrode and a second transparent electrode in parallel, spaced relation to each other. The first transparent electrode is electrically connected to the second transparent electrode. An electrochromic material is applied to the first transparent electrode and a nanoporous semiconductor film having a dye adsorbed therein is applied to the second transparent electrode. An electrolyte layer contacts the electrochromic material and the nanoporous semiconductor film. The electrolyte layer has a redox couple whereby upon application of light, the nanoporous semiconductor layer dye absorbs the light and the redox couple oxidizes producing an electric field across the device modulating the effective light transmittance through the device.

Mechanisms of Current Transfer in Electrodeposited Layers of Submicron Semiconductor Particles

NASA Astrophysics Data System (ADS)

Zhukov, N. D.; Mosiyash, D. S.; Sinev, I. V.; Khazanov, A. A.; Smirnov, A. V.; Lapshin, I. V.

2017-12-01

Current-voltage ( I- V) characteristics of conductance in multigrain layers of submicron particles of silicon, gallium arsenide, indium arsenide, and indium antimonide have been studied. Nanoparticles of all semiconductors were obtained by processing initial single crystals in a ball mill and applied after sedimentation onto substrates by means of electrodeposition. Detailed analysis of the I- V curves of electrodeposited layers shows that their behavior is determined by the mechanism of intergranular tunneling emission from near-surface electron states of submicron particles. Parameters of this emission process have been determined. The proposed multigrain semiconductor structures can be used in gas sensors, optical detectors, IR imagers, etc.

Lithium-drifted silicon detector with segmented contacts

DOEpatents

Tindall, Craig S.; Luke, Paul N.

2006-06-13

A method and apparatus for creating both segmented and unsegmented radiation detectors which can operate at room temperature. The devices include a metal contact layer, and an n-type blocking contact formed from a thin layer of amorphous semiconductor. In one embodiment the material beneath the n-type contact is n-type material, such as lithium compensated silicon that forms the active region of the device. The active layer has been compensated to a degree at which the device may be fully depleted at low bias voltages. A p-type blocking contact layer, or a p-type donor material can be formed beneath a second metal contact layer to complete the device structure. When the contacts to the device are segmented, the device is capable of position sensitive detection and spectroscopy of ionizing radiation, such as photons, electrons, and ions.

Two-dimensional layered semiconductor/graphene heterostructures for solar photovoltaic applications.

PubMed

Shanmugam, Mariyappan; Jacobs-Gedrim, Robin; Song, Eui Sang; Yu, Bin

2014-11-07

Schottky barriers formed by graphene (monolayer, bilayer, and multilayer) on 2D layered semiconductor tungsten disulfide (WS2) nanosheets are explored for solar energy harvesting. The characteristics of the graphene-WS2 Schottky junction vary significantly with the number of graphene layers on WS2, resulting in differences in solar cell performance. Compared with monolayer or stacked bilayer graphene, multilayer graphene helps in achieving improved solar cell performance due to superior electrical conductivity. The all-layered-material Schottky barrier solar cell employing WS2 as a photoactive semiconductor exhibits efficient photon absorption in the visible spectral range, yielding 3.3% photoelectric conversion efficiency with multilayer graphene as the Schottky contact. Carrier transport at the graphene/WS2 interface and the interfacial recombination process in the Schottky barrier solar cells are examined.

Proximity charge sensing for semiconductor detectors

DOEpatents

Luke, Paul N; Tindall, Craig S; Amman, Mark

2013-10-08

A non-contact charge sensor includes a semiconductor detector having a first surface and an opposing second surface. The detector includes a high resistivity electrode layer on the first surface and a low resistivity electrode on the high resistivity electrode layer. A portion of the low resistivity first surface electrode is deleted to expose the high resistivity electrode layer in a portion of the area. A low resistivity electrode layer is disposed on the second surface of the semiconductor detector. A voltage applied between the first surface low resistivity electrode and the second surface low resistivity electrode causes a free charge to drift toward the first or second surface according to a polarity of the free charge and the voltage. A charge sensitive preamplifier coupled to a non-contact electrode disposed at a distance from the exposed high resistivity electrode layer outputs a signal in response to movement of free charge within the detector.

Heterogeneous Semiconductor Shells Sequentially Coated on Upconversion Nanoplates for NIR-Light Enhanced Photocatalysis.

PubMed

Cui, Cao; Tou, Meijie; Li, Mohua; Luo, Zhenguo; Xiao, Lingbo; Bai, Song; Li, Zhengquan

2017-02-20

Combination of upconversion nanocrystals (UCNs) with CeO 2 is a decent choice to construct NIR-activated photocatalysts for utilizing the NIR light in the solar spectrum. Herein we present a facile approach to deposit a CeO 2 layer with controllable thickness on the plate-shaped NaYF 4 :Yb,Tm UCNs. The developed core-shell nanocomposites display obvious photocatalytic activity under the NIR light and exhibit enhanced activity under the full solar spectrum. For enhancing the separation of photogenerated electrons and holes on the CeO 2 surface, we sequentially coat a ZnO shell on the nanocomposites so as to form a heterojunction structure for achieving a better activity. The developed hybrid photocatalysts have been characterized with TEM, SEM, PL, etc., and the working mechanism of such UCN-semiconductor heterojunction photocatalysts has been proposed.

Conversion of type of quantum well structure

NASA Technical Reports Server (NTRS)

Ning, Cun-Zheng (Inventor)

2007-01-01

A method for converting a Type 2 quantum well semiconductor material to a Type 1 material. A second layer of undoped material is placed between first and third layers of selectively doped material, which are separated from the second layer by undoped layers having small widths. Doping profiles are chosen so that a first electrical potential increment across a first layer-second layer interface is equal to a first selected value and/or a second electrical potential increment across a second layer-third layer interface is equal to a second selected value. The semiconductor structure thus produced is useful as a laser material and as an incident light detector material in various wavelength regions, such as a mid-infrared region.

Conversion of Type of Quantum Well Structure

NASA Technical Reports Server (NTRS)

Ning, Cun-Zheng (Inventor)

2007-01-01

A method for converting a Type 2 quantum well semiconductor material to a Type 1 material. A second layer of undoped material is placed between first and third layers of selectively doped material, which are separated from the second layer by undoped layers having small widths. Doping profiles are chosen so that a first electrical potential increment across a first layer-second layer interface is equal to a first selected value and/or a second electrical potential increment across a second layer-third layer interface is equal to a second selected value. The semiconductor structure thus produced is useful as a laser material and as an incident light detector material in various wavelength regions, such as a mid-infrared region.

Electrically tunable infrared metamaterial devices

DOEpatents

Brener, Igal; Jun, Young Chul

2015-07-21

A wavelength-tunable, depletion-type infrared metamaterial optical device is provided. The device includes a thin, highly doped epilayer whose electrical permittivity can become negative at some infrared wavelengths. This highly-doped buried layer optically couples with a metamaterial layer. Changes in the transmission spectrum of the device can be induced via the electrical control of this optical coupling. An embodiment includes a contact layer of semiconductor material that is sufficiently doped for operation as a contact layer and that is effectively transparent to an operating range of infrared wavelengths, a thin, highly doped buried layer of epitaxially grown semiconductor material that overlies the contact layer, and a metallized layer overlying the buried layer and patterned as a resonant metamaterial.

Thick layered semiconductor devices with water top-gates: High on-off ratio field-effect transistors and aqueous sensors.

PubMed

Huang, Yuan; Sutter, Eli; Wu, Liangmei; Xu, Hong; Bao, Lihong; Gao, Hong-Jun; Zhou, Xingjiang; Sutter, Peter

2018-06-21

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal sub-threshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels where such control is difficult to realize with conventional back-gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Method for producing a hybridization of detector array and integrated circuit for readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

1993-01-01

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Method and structure for passivating semiconductor material

DOEpatents

Pankove, Jacques I.

1981-01-01

A structure for passivating semiconductor material comprises a substrate of crystalline semiconductor material, a relatively thin film of carbon disposed on a surface of the crystalline material, and a layer of hydrogenated amorphous silicon deposited on the carbon film.

Tungsten polyoxometalate molecules as active nodes for dynamic carrier exchange in hybrid molecular/semiconductor capacitors

NASA Astrophysics Data System (ADS)

Balliou, A.; Douvas, A. M.; Normand, P.; Tsikritzis, D.; Kennou, S.; Argitis, P.; Glezos, N.

2014-10-01

In this work we study the utilization of molecular transition metal oxides known as polyoxometalates (POMs), in particular the Keggin structure anions of the formula PW12O403-, as active nodes for potential switching and/or fast writing memory applications. The active molecules are being integrated in hybrid Metal-Insulator/POM molecules-Semiconductor capacitors, which serve as prototypes allowing investigation of critical performance characteristics towards the design of more sophisticated devices. The charging ability as well as the electronic structure of the molecular layer is probed by means of electrical characterization, namely, capacitance-voltage and current-voltage measurements, as well as transient capacitance measurements, C (t), under step voltage polarization. It is argued that the transient current peaks observed are manifestations of dynamic carrier exchange between the gate electrode and specific molecular levels, while the transient C (t) curves under conditions of molecular charging can supply information for the rate of change of the charge that is being trapped and de-trapped within the molecular layer. Structural characterization via surface and cross sectional scanning electron microscopy as well as atomic force microscopy, spectroscopic ellipsometry, UV and Fourier-transform IR spectroscopies, UPS, and XPS contribute to the extraction of accurate electronic structure characteristics and open the path for the design of new devices with on-demand tuning of their interfacial properties via the controlled preparation of the POM layer.

Release strategies for making transferable semiconductor structures, devices and device components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rogers, John A.; Nuzzo, Ralph G.; Meitl, Matthew

2016-05-24

Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Controlled growth of semiconductor crystals

DOEpatents

Bourret-Courchesne, Edith D.

1992-01-01

A method for growth of III-V, II-VI and related semiconductor single crystals that suppresses random nucleation and sticking of the semiconductor melt at the crucible walls. Small pieces of an oxide of boron B.sub.x O.sub.y are dispersed throughout the comminuted solid semiconductor charge in the crucible, with the oxide of boron preferably having water content of at least 600 ppm. The crucible temperature is first raised to a temperature greater than the melt temperature T.sub.m1 of the oxide of boron (T.sub.m1 =723.degree. K. for boron oxide B.sub.2 O.sub.3), and the oxide of boron is allowed to melt and form a reasonably uniform liquid layer between the crucible walls and bottom surfaces and the still-solid semiconductor charge. The temperature is then raised to approximately the melt temperature T.sub.m2 of the semiconductor charge material, and crystal growth proceeds by a liquid encapsulated, vertical gradient freeze process. About half of the crystals grown have a dislocation density of less than 1000/cm.sup.2. If the oxide of boron has water content less than 600 ppm, the crucible material should include boron nitride, a layer of the inner surface of the crucible should be oxidized before the oxide of boron in the crucible charge is melted, and the sum of thicknesses of the solid boron oxide layer and liquid boron oxide layer should be at least 50 .mu.m.

Controlled growth of semiconductor crystals

DOEpatents

Bourret-Courchesne, E.D.

1992-07-21

A method is disclosed for growth of III-V, II-VI and related semiconductor single crystals that suppresses random nucleation and sticking of the semiconductor melt at the crucible walls. Small pieces of an oxide of boron B[sub x]O[sub y] are dispersed throughout the comminuted solid semiconductor charge in the crucible, with the oxide of boron preferably having water content of at least 600 ppm. The crucible temperature is first raised to a temperature greater than the melt temperature T[sub m1] of the oxide of boron (T[sub m1]=723 K for boron oxide B[sub 2]O[sub 3]), and the oxide of boron is allowed to melt and form a reasonably uniform liquid layer between the crucible walls and bottom surfaces and the still-solid semiconductor charge. The temperature is then raised to approximately the melt temperature T[sub m2] of the semiconductor charge material, and crystal growth proceeds by a liquid encapsulated, vertical gradient freeze process. About half of the crystals grown have a dislocation density of less than 1000/cm[sup 2]. If the oxide of boron has water content less than 600 ppm, the crucible material should include boron nitride, a layer of the inner surface of the crucible should be oxidized before the oxide of boron in the crucible charge is melted, and the sum of thicknesses of the solid boron oxide layer and liquid boron oxide layer should be at least 50 [mu]m. 7 figs.

The preparation method of terahertz monolithic integrated device

NASA Astrophysics Data System (ADS)

Zhang, Cong; Su, Bo; He, Jingsuo; Zhang, Hongfei; Wu, Yaxiong; Zhang, Shengbo; Zhang, Cunlin

2018-01-01

The terahertz monolithic integrated device is to integrate the pumping area of the terahertz generation, the detection area of the terahertz receiving and the metal waveguide of terahertz transmission on the same substrate. The terahertz generation and detection device use a photoconductive antenna structure the metal waveguide use a microstrip line structure. The evanescent terahertz-bandwidth electric field extending above the terahertz transmission line interacts with, and is modified by, overlaid dielectric samples, thus enabling the characteristic vibrational absorption resonances in the sample to be probed. In this device structure, since the semiconductor substrate of the photoconductive antenna is located between the strip conductor and the dielectric layer of the microstrip line, and the semiconductor substrate cannot grow on the dielectric layer directly. So how to prepare the semiconductor substrate of the photoconductive antenna and how to bond the semiconductor substrate to the dielectric layer of the microstrip line is a key step in the terahertz monolithic integrated device. In order to solve this critical problem, the epitaxial wafer structure of the two semiconductor substrates is given and transferred to the desired substrate by two methods, respectively.

Photoprecursor Approach Enables Preparation of Well-Performing Bulk-Heterojunction Layers Comprising a Highly Aggregating Molecular Semiconductor.

PubMed

Suzuki, Mitsuharu; Yamaguchi, Yuji; Takahashi, Kohei; Takahira, Katsuya; Koganezawa, Tomoyuki; Masuo, Sadahiro; Nakayama, Ken-ichi; Yamada, Hiroko

2016-04-06

Active-layer morphology critically affects the performance of organic photovoltaic cells, and thus its optimization is a key toward the achievement of high-efficiency devices. However, the optimization of active-layer morphology is sometimes challenging because of the intrinsic properties of materials such as strong self-aggregating nature or low miscibility. This study postulates that the "photoprecursor approach" can serve as an effective means to prepare well-performing bulk-heterojunction (BHJ) layers containing highly aggregating molecular semiconductors. In the photoprecursor approach, a photoreactive precursor compound is solution-deposited and then converted in situ to a semiconducting material. This study employs 2,6-di(2-thienyl)anthracene (DTA) and [6,6]-phenyl-C71-butyric acid methyl ester as p- and n-type materials, respectively, in which DTA is generated by the photoprecursor approach from the corresponding α-diketone-type derivative DTADK. When only chloroform is used as a cast solvent, the photovoltaic performance of the resulting BHJ films is severely limited because of unfavorable film morphology. The addition of a high-boiling-point cosolvent, o-dichlorobenzene (o-DCB), to the cast solution leads to significant improvement such that the resulting active layers afford up to approximately 5 times higher power conversion efficiencies. The film structure is investigated by two-dimensional grazing-incident wide-angle X-ray diffraction, atomic force microscopy, and fluorescence microspectroscopy to demonstrate that the use of o-DCB leads to improvement in film crystallinity and increase in charge-carrier generation efficiency. The change in film structure is assumed to originate from dynamic molecular motion enabled by the existence of solvent during the in situ photoreaction. The unique features of the photoprecursor approach will be beneficial in extending the material and processing scopes for the development of organic thin-film devices.

Casimir Pressure in Mds-Structures

NASA Astrophysics Data System (ADS)

Yurova, V. A.; Bukina, M. N.; Churkin, Yu. V.; Fedortsov, A. B.; Klimchitskaya, G. L.

2012-07-01

The Casimir pressure on the dielectric layer in metal-dielectric-semiconductor (MDS) structures is calculated in the framework of the Lifshitz theory at nonzero temperature. In this calculation the standard parameters of semiconductor devices with a thin dielectric layer are used. We consider the thickness of a layer decreasing from 40 to 1 nm. At the shortest thickness the Casimir pressure achieves 8 MPa. At small thicknesses the results are compared with the predictions of nonrelativistic theory.

Graphene-on-semiconductor substrates for analog electronics

DOEpatents

Lagally, Max G.; Cavallo, Francesca; Rojas-Delgado, Richard

2016-04-26

Electrically conductive material structures, analog electronic devices incorporating the structures and methods for making the structures are provided. The structures include a layer of graphene on a semiconductor substrate. The graphene layer and the substrate are separated by an interfacial region that promotes transfer of charge carriers from the surface of the substrate to the graphene.

Low temperature junction growth using hot-wire chemical vapor deposition

DOEpatents

Wang, Qi; Page, Matthew; Iwaniczko, Eugene; Wang, Tihu; Yan, Yanfa

2014-02-04

A system and a process for forming a semi-conductor device, and solar cells (10) formed thereby. The process includes preparing a substrate (12) for deposition of a junction layer (14); forming the junction layer (14) on the substrate (12) using hot wire chemical vapor deposition; and, finishing the semi-conductor device.

Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

DOEpatents

Fitzgerald, Jr., Eugene A.; Ast, Dieter G.

1992-01-01

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10.times. critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers

DOEpatents

Fitzgerald, Jr., Eugene A.; Ast, Dieter G.

1991-01-01

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10x critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

DOEpatents

Fitzgerald, E.A. Jr.; Ast, D.G.

1992-10-20

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10[times] critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In[sub 0.05]Ga[sub 0.95]As/(001)GaAs interface was controlled by fabricating 2-[mu]m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500 [angstrom] of In[sub 0.05]Ga[sub 0.95]As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-[mu]m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 [mu]m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density. 7 figs.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

OPS laser EPI design for different wavelengths

NASA Astrophysics Data System (ADS)

Moloney, J. V.; Hader, J.; Li, H.; Kaneda, Y.; Wang, T. S.; Yarborough, M.; Koch, S. W.; Stolz, W.; Kunert, B.; Bueckers, C.; Chaterjee, S.; Hardesty, G.

2009-02-01

Design of optimized semiconductor optically-pumped semiconductor lasers (OPSLs) depends on many ingredients starting from the quantum wells, barrier and cladding layers all the way through to the resonant-periodic gain (RPG) and high reflectivity Bragg mirror (DBR) making up the OPSL active mirror. Accurate growth of the individual layers making up the RPG region is critical if performance degradation due to cavity misalignment is to be avoided. Optimization of the RPG+DBR structure requires knowledge of the heat generation and heating sinking of the active mirror. Nonlinear Control Strategies SimuLaseTM software, based on rigorous many-body calculations of the semiconductor optical response, allows for quantum well and barrier optimization by correlating low intensity photoluminescence spectra computed for the design, with direct experimentally measured wafer-level edge and surface PL spectra. Consequently, an OPSL device optimization procedure ideally requires a direct iterative interaction between designer and grower. In this article, we discuss the application of the many-body microscopic approach to OPSL devices lasing at 850nm, 1040nm and 2μm. The latter device involves and application of the many-body approach to mid-IR OPSLs based on antimonide materials. Finally we will present results on based on structural modifications of the epitaxial structure and/or novel material combinations that offer the potential to extend OPSL technology to new wavelength ranges.

Ring-shaped active mode-locked tunable laser using quantum-dot semiconductor optical amplifier

NASA Astrophysics Data System (ADS)

Zhang, Mingxiao; Wang, Yongjun; Liu, Xinyu

2018-03-01

In this paper, a lot of simulations has been done for ring-shaped active mode-locked lasers with quantum-dot semiconductor optical amplifier (QD-SOA). Based on the simulation model of QD-SOA, we discussed about the influence towards mode-locked waveform frequency and pulse caused by QD-SOA maximum mode peak gain, active layer loss coefficient, bias current, incident light pulse, fiber nonlinear coefficient. In the meantime, we also take the tunable performance of the laser into consideration. Results showed QD-SOA a better performance than original semiconductor optical amplifier (SOA) in recovery time, line width, and nonlinear coefficients, which makes it possible to output a locked-mode impulse that has a higher impulse power, narrower impulse width as well as the phase is more easily controlled. After a lot of simulations, this laser can realize a 20GHz better locked-mode output pulse after 200 loops, where the power is above 17.5mW, impulse width is less than 2.7ps, moreover, the tunable wavelength range is between 1540nm-1580nm.

p-Type semiconducting nickel oxide as an efficiency-enhancing anode interfacial layer in polymer bulk-heterojunction solar cells

PubMed Central

Irwin, Michael D.; Buchholz, D. Bruce; Hains, Alexander W.; Chang, Robert P. H.; Marks, Tobin J.

2008-01-01

To minimize interfacial power losses, thin (5–80 nm) layers of NiO, a p-type oxide semiconductor, are inserted between the active organic layer, poly(3-hexylthiophene) (P3HT) + [6,6]-phenyl-C61 butyric acid methyl ester (PCBM), and the ITO (tin-doped indium oxide) anode of bulk-heterojunction ITO/P3HT:PCBM/LiF/Al solar cells. The interfacial NiO layer is deposited by pulsed laser deposition directly onto cleaned ITO, and the active layer is subsequently deposited by spin-coating. Insertion of the NiO layer affords cell power conversion efficiencies as high as 5.2% and enhances the fill factor to 69% and the open-circuit voltage (Voc) to 638 mV versus an ITO/P3HT:PCBM/LiF/Al control device. The value of such hole-transporting/electron-blocking interfacial layers is clearly demonstrated and should be applicable to other organic photovoltaics.

A multifunctional biphasic water splitting catalyst tailored for integration with high-performance semiconductor photoanodes

NASA Astrophysics Data System (ADS)

Yang, Jinhui; Cooper, Jason K.; Toma, Francesca M.; Walczak, Karl A.; Favaro, Marco; Beeman, Jeffrey W.; Hess, Lucas H.; Wang, Cheng; Zhu, Chenhui; Gul, Sheraz; Yano, Junko; Kisielowski, Christian; Schwartzberg, Adam; Sharp, Ian D.

2017-03-01

Artificial photosystems are advanced by the development of conformal catalytic materials that promote desired chemical transformations, while also maintaining stability and minimizing parasitic light absorption for integration on surfaces of semiconductor light absorbers. Here, we demonstrate that multifunctional, nanoscale catalysts that enable high-performance photoelectrochemical energy conversion can be engineered by plasma-enhanced atomic layer deposition. The collective properties of tailored Co3O4/Co(OH)2 thin films simultaneously provide high activity for water splitting, permit efficient interfacial charge transport from semiconductor substrates, and enhance durability of chemically sensitive interfaces. These films comprise compact and continuous nanocrystalline Co3O4 spinel that is impervious to phase transformation and impermeable to ions, thereby providing effective protection of the underlying substrate. Moreover, a secondary phase of structurally disordered and chemically labile Co(OH)2 is introduced to ensure a high concentration of catalytically active sites. Application of this coating to photovoltaic p+n-Si junctions yields best reported performance characteristics for crystalline Si photoanodes.

Narrow energy band gap gallium arsenide nitride semi-conductors and an ion-cut-synthesis method for producing the same

DOEpatents

Weng, Xiaojun; Goldman, Rachel S.

2006-06-06

A method for forming a semi-conductor material is provided that comprises forming a donor substrate constructed of GaAs, providing a receiver substrate, implanting nitrogen into the donor substrate to form an implanted layer comprising GaAs and nitrogen. The implanted layer is bonded to the receiver substrate and annealed to form GaAsN and nitrogen micro-blisters in the implanted layer. The micro-blisters allow the implanted layer to be cleaved from the donor substrate.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y. Simon; Deb, Satyen K.

1990-01-01

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

Low resistance barrier layer for isolating, adhering, and passivating copper metal in semiconductor fabrication

DOEpatents

Weihs, Timothy P.; Barbee, Jr., Troy W.

2002-01-01

Cubic or metastable cubic refractory metal carbides act as barrier layers to isolate, adhere, and passivate copper in semiconductor fabrication. One or more barrier layers of the metal carbide are deposited in conjunction with copper metallizations to form a multilayer characterized by a cubic crystal structure with a strong (100) texture. Suitable barrier layer materials include refractory transition metal carbides such as vanadium carbide (VC), niobium carbide (NbC), tantalum carbide (TaC), chromium carbide (Cr.sub.3 C.sub.2), tungsten carbide (WC), and molybdenum carbide (MoC).

Miniaturized Metal (Metal Alloy)/PdO(x)/SiC Hydrogen and Hydrocarbon Gas Sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO(x)). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600 C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sided sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Megahertz organic/polymer diodes

DOEpatents

Katz, Howard Edan; Sun, Jia; Pal, Nath Bhola

2012-12-11

Featured is an organic/polymer diode having a first layer composed essentially of one of an organic semiconductor material or a polymeric semiconductor material and a second layer formed on the first layer and being electrically coupled to the first layer such that current flows through the layers in one direction when a voltage is applied in one direction. The second layer is essentially composed of a material whose characteristics and properties are such that when formed on the first layer, the diode is capable of high frequency rectifications on the order of megahertz rectifications such as for example rectifications at one of above 100KHz, 500KhZ, IMHz, or 10 MHz. In further embodiments, the layers are arranged so as to be exposed to atmosphere.

Comparative study on degradation and trap density-of-states of p type and n type organic semiconductors

NASA Astrophysics Data System (ADS)

Shijeesh, M. R.; Vikas, L. S.; Jayaraj, M. K.; Puigdollers, J.

2014-10-01

The OTFTs with both p type and n type channel layers were fabricated using the inverted-staggered (top contact) structure by thermal vapour deposition on Si/SiO2 substrate. Pentacene and N,N'-Dioctyl- 3,4,9,10- perylenedicarboximide (PTCDI-C8) were used as channel layer for the fabrications of p type and n type OTFTs respectively. A comparative study on the degradation and density of states (DOS) of p type and n type organic semiconductors have been carried out. In order to compare the stability and degradation of pentacene and PTCDI-C8 OTFTs, the devices were exposed to air for 2 h before performing electrical measurements in air. The DOS measurements revealed that a level with defect density of 1020 cm-3 was formed only in PTCDI C8 layer on exposure to air. The oxygen adsorption into the PTCDI-C8 active layer can be attributed to the formation of this level at 0.15 eV above the LUMO level. The electrical charge transport is strongly affected by the oxygen traps and hence n type organic materials are less stable than p type organic materials.

Photoelectrochemical cell including Ga(Sb.sub.x)N.sub.1-x semiconductor electrode

DOEpatents

Menon, Madhu; Sheetz, Michael; Sunkara, Mahendra Kumar; Pendyala, Chandrashekhar; Sunkara, Swathi; Jasinski, Jacek B.

2017-09-05

The composition of matter comprising Ga(Sb.sub.x)N.sub.1-x where x=0.01 to 0.06 is characterized by a band gap between 2.4 and 1.7 eV. A semiconductor device includes a semiconductor layer of that composition. A photoelectric cell includes that semiconductor device.

Surface and Interface Engineering of Organometallic and Two Dimensional Semiconductor

NASA Astrophysics Data System (ADS)

Park, Jun Hong

For over half a century, inorganic Si and III-V materials have led the modern semiconductor industry, expanding to logic transistor and optoelectronic applications. However, these inorganic materials have faced two different fundamental limitations, flexibility for wearable applications and scaling limitation as logic transistors. As a result, the organic and two dimensional have been studied intentionally for various fields. In the present dissertation, three different studies will be presented with followed order; (1) the chemical response of organic semiconductor in NO2 exposure. (2) The surface and stability of WSe2 in ambient air. (3) Deposition of dielectric on two dimensional materials using organometallic seeding layer. The organic molecules rely on the van der Waals interaction during growth of thin films, contrast to covalent bond inorganic semiconductors. Therefore, the morphology and electronic property at surface of organic semiconductor in micro scale is more sensitive to change in gaseous conditions. In addition, metal phthalocyanine, which is one of organic semiconductor materials, change their electronic property as reaction with gaseous analytes, suggesting as potential chemical sensing platforms. In the present part, the growth behavior of metal phthalocyanine and surface response to gaseous condition will be elucidated using scanning tunneling microscopy (STM). In second part, the surface of layered transition metal dichalcogenides and their chemical response to exposure ambient air will be investigated, using STM. Layered transition metal dichalcogenides (TMDs) have attracted widespread attention in the scientific community for electronic device applications because improved electrostatic gate control and suppression of short channel leakage resulted from their atomic thin body. To fabricate the transistor based on TMDs, TMDs should be exposed to ambient conditions, while the effect of air exposure has not been understood fully. In this part, the effect of ambient air on TMDs will be investigated and partial oxidation of TMDs. In the last part, uniform deposition of dielectric layers on 2D materials will be presented, employing organic seedling layer. Although 2D materials have been expected as next generation semiconductor platform, direct deposition of dielectric is still challenging and induces leakage current commonly, because inertness of their surface resulted from absent of dangling bond. Here, metal phthalocyanine monolayer (ML) is employed as seedling layers and the growth of atomic layer deposition (ALD) dielectric is investigated in each step using STM.

Lateral electrochemical etching of III-nitride materials for microfabrication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Han, Jung

Conductivity-selective lateral etching of III-nitride materials is described. Methods and structures for making vertical cavity surface emitting lasers with distributed Bragg reflectors via electrochemical etching are described. Layer-selective, lateral electrochemical etching of multi-layer stacks is employed to form semiconductor/air DBR structures adjacent active multiple quantum well regions of the lasers. The electrochemical etching techniques are suitable for high-volume production of lasers and other III-nitride devices, such as lasers, HEMT transistors, power transistors, MEMs structures, and LEDs.

Transparent contacts for stacked compound photovoltaic cells

DOEpatents

Tauke-Pedretti, Anna; Cederberg, Jeffrey; Nielson, Gregory N.; Okandan, Murat; Cruz-Campa, Jose Luis

2016-11-29

A microsystems-enabled multi-junction photovoltaic (MEM-PV) cell includes a first photovoltaic cell having a first junction, the first photovoltaic cell including a first semiconductor material employed to form the first junction, the first semiconductor material having a first bandgap. The MEM-PV cell also includes a second photovoltaic cell comprising a second junction. The second photovoltaic cell comprises a second semiconductor material employed to form the second junction, the second semiconductor material having a second bandgap that is less than the first bandgap, the second photovoltaic cell further comprising a first contact layer disposed between the first junction of the first photovoltaic cell and the second junction of the second photovoltaic cell, the first contact layer composed of a third semiconductor material having a third bandgap, the third bandgap being greater than or equal to the first bandgap.

Design and fabrication of 6.1-.ANG. family semiconductor devices using semi-insulating A1Sb substrate

DOEpatents

Sherohman, John W [Livermore, CA; Coombs, III, Arthur W.; Yee, Jick Hong [Livermore, CA; Wu, Kuang Jen J [Cupertino, CA

2007-05-29

For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-.ANG. family heterostructure devices.

Dry etching method for compound semiconductors

DOEpatents

Shul, Randy J.; Constantine, Christopher

1997-01-01

A dry etching method. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators.

Dry etching method for compound semiconductors

DOEpatents

Shul, R.J.; Constantine, C.

1997-04-29

A dry etching method is disclosed. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators. 1 fig.

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Photodetector with enhanced light absorption

DOEpatents

Kane, James

1985-01-01

A photodetector including a light transmissive electrically conducting layer having a textured surface with a semiconductor body thereon. This layer traps incident light thereby enhancing the absorption of light by the semiconductor body. A photodetector comprising a textured light transmissive electrically conducting layer of SnO.sub.2 and a body of hydrogenated amorphous silicon has a conversion efficiency about fifty percent greater than that of comparative cells. The invention also includes a method of fabricating the photodetector of the invention.

Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-07-09

A high efficiency amorphous silicon PIN semiconductor device having partially crystallized (microcrystalline) P and N layers is constructed by the sequential sputtering of N, I and P layers and at least one semi-transparent ohmic electrode. The method of construction produces a PIN device, exhibiting enhanced electrical and optical properties, improved physical integrity, and facilitates the preparation in a singular vacuum system and vacuum pump down procedure.

Tuneable photonic device including an array of metamaterial resonators

DOEpatents

Brener, Igal; Wanke, Michael; Benz, Alexander

2017-03-14

A photonic apparatus includes a metamaterial resonator array overlying and electromagnetically coupled to a vertically stacked plurality of quantum wells defined in a semiconductor body. An arrangement of electrical contact layers is provided for facilitating the application of a bias voltage across the quantum well stack. Those portions of the semiconductor body that lie between the electrical contact layers are conformed to provide an electrically conductive path between the contact layers and through the quantum well stack.

Apparatus and method of manufacture for an imager equipped with a cross-talk barrier

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2012-01-01

An imager apparatus and associated starting material are provided. In one embodiment, an imager is provided including a silicon layer of a first conductivity type acting as a junction anode. Such silicon layer is adapted to convert light to photoelectrons. Also included is a semiconductor well of a second conductivity type formed in the silicon layer for acting as a junction cathode. Still yet, a barrier is formed adjacent to the semiconductor well. In another embodiment, a starting material is provided including a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Also included is a second silicon layer disposed adjacent to the oxide layer opposite the first silicon layer. Such second silicon layer is further equipped with an associated passivation layer and/or barrier.

Observation of turnover of spontaneous polarization in ferroelectric layer of pentacene/poly-(vinylidene-trifluoroethylene) double-layer capacitor under photo illumination by optical second-harmonic generation measurement

NASA Astrophysics Data System (ADS)

Shi, Zhemin; Taguchi, Dai; Manaka, Takaaki; Iwamoto, Mitsumasa

2016-04-01

The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial charging in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.

van der Waals epitaxial two-dimensional CdSxSe(1-x) semiconductor alloys with tunable-composition and application to flexible optoelectronics.

PubMed

Xia, Jing; Zhao, Yun-Xuan; Wang, Lei; Li, Xuan-Ze; Gu, Yi-Yi; Cheng, Hua-Qiu; Meng, Xiang-Min

2017-09-21

Despite the substantial progress in the development of two-dimensional (2D) materials from conventional layered crystals, it still remains particularly challenging to produce high-quality 2D non-layered semiconductor alloys which may bring in some unique properties and new functions. In this work, the synthesis of well-oriented 2D non-layered CdS x Se (1-x) semiconductor alloy flakes with tunable compositions and optical properties is established. Structural analysis reveals that the 2D non-layered alloys follow an incommensurate van der Waals epitaxial growth pattern. Photoluminescence measurements show that the 2D alloys have composition-dependent direct bandgaps with the emission peak varying from 1.8 eV to 2.3 eV, coinciding well with the density functional theory calculations. Furthermore, photodetectors based on the CdS x Se (1-x) flakes exhibit a high photoresponsivity of 703 A W -1 with an external quantum efficiency of 1.94 × 10 3 and a response time of 39 ms. Flexible devices fabricated on a thin mica substrate display good mechanical stability upon repeated bending. This work suggests a facile and general method to produce high-quality 2D non-layered semiconductor alloys for next-generation optoelectronic devices.

Tantalum-based semiconductors for solar water splitting.

PubMed

Zhang, Peng; Zhang, Jijie; Gong, Jinlong

2014-07-07

Solar energy utilization is one of the most promising solutions for the energy crises. Among all the possible means to make use of solar energy, solar water splitting is remarkable since it can accomplish the conversion of solar energy into chemical energy. The produced hydrogen is clean and sustainable which could be used in various areas. For the past decades, numerous efforts have been put into this research area with many important achievements. Improving the overall efficiency and stability of semiconductor photocatalysts are the research focuses for the solar water splitting. Tantalum-based semiconductors, including tantalum oxide, tantalate and tantalum (oxy)nitride, are among the most important photocatalysts. Tantalum oxide has the band gap energy that is suitable for the overall solar water splitting. The more negative conduction band minimum of tantalum oxide provides photogenerated electrons with higher potential for the hydrogen generation reaction. Tantalates, with tunable compositions, show high activities owning to their layered perovskite structure. (Oxy)nitrides, especially TaON and Ta3N5, have small band gaps to respond to visible-light, whereas they can still realize overall solar water splitting with the proper positions of conduction band minimum and valence band maximum. This review describes recent progress regarding the improvement of photocatalytic activities of tantalum-based semiconductors. Basic concepts and principles of solar water splitting will be discussed in the introduction section, followed by the three main categories regarding to the different types of tantalum-based semiconductors. In each category, synthetic methodologies, influencing factors on the photocatalytic activities, strategies to enhance the efficiencies of photocatalysts and morphology control of tantalum-based materials will be discussed in detail. Future directions to further explore the research area of tantalum-based semiconductors for solar water splitting are also discussed.

INTERNATIONAL CONFERENCE ON SEMICONDUCTOR INJECTION LASERS SELCO-87: Refractive indices of superlattices made of III-V semiconductor compounds and their solid solutions and semiconductor waveguide laser structures

NASA Astrophysics Data System (ADS)

Unger, K.

1988-11-01

An analysis is made of the theoretical problems encountered in precision calculations of refractive indices of semiconductor materials arising in connection with the use of superlattices as active layers in double-heterostructure lasers and in connection with the use of the impurity-induced disordering effect, i.e., the ability to transform selectively a superlattice into a corresponding solid solution. This can be done by diffusion or ion implantation. A review is given of calculations of refractive indices based on the knowledge of the energy band structure and the role of disorder is considered particularly. An anomaly observed in the (InAl)As system is considered. It is shown that the local field effects and exciton transitions are important. A reasonable approach is clearly a direct calculation of the difference between the refractive indices of superlattices based on compounds and of those based on their solid solutions.

Device and method for luminescence enhancement by resonant energy transfer from an absorptive thin film

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akselrod, Gleb M.; Bawendi, Moungi G.; Bulovic, Vladimir

Disclosed are a device and a method for the design and fabrication of the device for enhancing the brightness of luminescent molecules, nanostructures, and thin films. The device includes a mirror, a dielectric medium or spacer, an absorptive layer, and a luminescent layer. The absorptive layer is a continuous thin film of a strongly absorbing organic or inorganic material. The luminescent layer may be a continuous luminescent thin film or an arrangement of isolated luminescent species, e.g., organic or metal-organic dye molecules, semiconductor quantum dots, or other semiconductor nanostructures, supported on top of the absorptive layer.

Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

DOEpatents

Seager, C.H.; Evans, J.T. Jr.

1998-11-24

A method is described for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100 C and 300 C for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer. 1 fig.

Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

DOEpatents

Seager, Carleton H.; Evans, Jr., Joseph Tate

1998-01-01

A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.

Conduit for high temperature transfer of molten semiconductor crystalline material

NASA Technical Reports Server (NTRS)

Fiegl, George (Inventor); Torbet, Walter (Inventor)

1983-01-01

A conduit for high temperature transfer of molten semiconductor crystalline material consists of a composite structure incorporating a quartz transfer tube as the innermost member, with an outer thermally insulating layer designed to serve the dual purposes of minimizing heat losses from the quartz tube and maintaining mechanical strength and rigidity of the conduit at the elevated temperatures encountered. The composite structure ensures that the molten semiconductor material only comes in contact with a material (quartz) with which it is compatible, while the outer layer structure reinforces the quartz tube, which becomes somewhat soft at molten semiconductor temperatures. To further aid in preventing cooling of the molten semiconductor, a distributed, electric resistance heater is in contact with the surface of the quartz tube over most of its length. The quartz tube has short end portions which extend through the surface of the semiconductor melt and which are lef bare of the thermal insulation. The heater is designed to provide an increased heat input per unit area in the region adjacent these end portions.

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2011-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x ). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Xu, Jennifer C. (Inventor); Hunter, Gary W. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Estimation of carrier mobility and charge behaviors of organic semiconductor films in metal-insulator-semiconductor diodes consisting of high-k oxide/organic semiconductor double layers

NASA Astrophysics Data System (ADS)

Chosei, Naoya; Itoh, Eiji

2018-02-01

We have comparatively studied the charge behaviors of organic semiconductor films based on charge extraction by linearly increasing voltage in a metal-insulator-semiconductor (MIS) diode structure (MIS-CELIV) and by classical capacitance-voltage measurement. The MIS-CELIV technique allows the selective measurement of electron and hole mobilities of n- and p-type organic films with thicknesses representative of those of actual devices. We used an anodic oxidized sputtered Ta or Hf electrode as a high-k layer, and it effectively blocked holes at the insulator/semiconductor interface. We estimated the hole mobilities of the polythiophene derivatives regioregular poly(3-hexylthiophene) (P3HT) and poly(3,3‧‧‧-didodecylquarterthiophene) (PQT-12) before and after heat treatment in the ITO/high-k/(thin polymer insulator)/semiconductor/MoO3/Ag device structure. The hole mobility of PQT-12 was improved from 1.1 × 10-5 to 2.1 × 10-5 cm2 V-1 s-1 by the heat treatment of the device at 100 °C for 30 min. An almost two orders of magnitude higher mobility was obtained in MIS diodes with P3HT as the p-type layer. We also determined the capacitance from the displacement current in MIS diodes at a relatively low-voltage sweep, and it corresponded well to the classical capacitance-voltage and frequency measurement results.

Method for making a photodetector with enhanced light absorption

DOEpatents

Kane, James

1987-05-05

A photodetector including a light transmissive electrically conducting layer having a textured surface with a semiconductor body thereon. This layer traps incident light thereby enhancing the absorption of light by the semiconductor body. A photodetector comprising a textured light transmissive electrically conducting layer of SnO.sub.2 and a body of hydrogenated amorphous silicon has a conversion efficiency about fifty percent greater than that of comparative cells. The invention also includes a method of fabricating the photodetector of the invention.

Epitaxial growth of CoO films on semiconductor and metal substrates by constructing a complex heterostructure

NASA Astrophysics Data System (ADS)

Entani, S.; Kiguchi, M.; Saiki, K.; Koma, A.

2003-01-01

Epitaxial growth of CoO films was studied using reflection high-energy electron diffraction (RHEED), electron energy loss spectroscopy (EELS), ultraviolet photoelectron spectroscopy (UPS) and Auger electron spectroscopy (AES). The RHEED results indicated that an epitaxial CoO film grew on semiconductor and metal substrates (CoO (0 0 1)∥GaAs (0 0 1), Cu (0 0 1), Ag (0 0 1) and [1 0 0]CoO∥[1 0 0] substrates) by constructing a complex heterostructure with two alkali halide buffer layers. The AES, EELS and UPS results showed that the grown CoO film had almost the same electronic structure as bulk CoO. We could show that use of alkali halide buffer layers was a good way to grow metal oxide films on semiconductor and metal substrates in an O 2 atmosphere. The alkali halide layers not only works as glue to connect very dissimilar materials but also prevents oxidation of metal and semiconductor substrates.

Photoelectrical Stimulation of Neuronal Cells by an Organic Semiconductor-Electrolyte Interface.

PubMed

Abdullaeva, Oliya S; Schulz, Matthias; Balzer, Frank; Parisi, Jürgen; Lützen, Arne; Dedek, Karin; Schiek, Manuela

2016-08-23

As a step toward the realization of neuroprosthetics for vision restoration, we follow an electrophysiological patch-clamp approach to study the fundamental photoelectrical stimulation mechanism of neuronal model cells by an organic semiconductor-electrolyte interface. Our photoactive layer consisting of an anilino-squaraine donor blended with a fullerene acceptor is supporting the growth of the neuronal model cell line (N2A cells) without an adhesion layer on it and is not impairing cell viability. The transient photocurrent signal upon illumination from the semiconductor-electrolyte layer is able to trigger a passive response of the neuronal cells under physiological conditions via a capacitive coupling mechanism. We study the dynamics of the capacitive transmembrane currents by patch-clamp recordings and compare them to the dynamics of the photocurrent signal and its spectral responsivity. Furthermore, we characterize the morphology of the semiconductor-electrolyte interface by atomic force microscopy and study the stability of the interface in dark and under illuminated conditions.

Microscopic properties of ionic liquid/organic semiconductor interfaces revealed by molecular dynamics simulations.

PubMed

Yokota, Yasuyuki; Miyamoto, Hiroo; Imanishi, Akihito; Takeya, Jun; Inagaki, Kouji; Morikawa, Yoshitada; Fukui, Ken-Ichi

2018-05-09

Electric double-layer transistors based on ionic liquid/organic semiconductor interfaces have been extensively studied during the past decade because of their high carrier densities at low operation voltages. Microscopic structures and the dynamics of ionic liquids likely determine the device performance; however, knowledge of these is limited by a lack of appropriate experimental tools. In this study, we investigated ionic liquid/organic semiconductor interfaces using molecular dynamics to reveal the microscopic properties of ionic liquids. The organic semiconductors include pentacene, rubrene, fullerene, and 7,7,8,8-tetracyanoquinodimethane (TCNQ). While ionic liquids close to the substrate always form the specific layered structures, the surface properties of organic semiconductors drastically alter the ionic dynamics. Ionic liquids at the fullerene interface behave as a two-dimensional ionic crystal because of the energy gain derived from the favorable electrostatic interaction on the corrugated periodic substrate.

The role of ultra-thin SiO2 layers in metal-insulator-semiconductor (MIS) photoelectrochemical devices (Presentation Recording)

NASA Astrophysics Data System (ADS)

Esposito, Daniel V.

2015-08-01

Solid-state junctions based on a metal-insulator-semiconductor (MIS) architecture are of great interest for a number of optoelectronic applications such as photovoltaics, photoelectrochemical cells, and photodetection. One major advantage of the MIS junction compared to the closely related metal-semiconductor junction, or Schottky junction, is that the thin insulating layer (1-3 nm thick) that separates the metal and semiconductor can significantly reduce the density of undesirable interfacial mid-gap states. The reduction in mid-gap states helps "un-pin" the junction, allowing for significantly higher built-in-voltages to be achieved. A second major advantage of the MIS junction is that the thin insulating layer can also protect the underlying semiconductor from corrosion in an electrochemical environment, making the MIS architecture well-suited for application in (photo)electrochemical applications. In this presentation, discontinuous Si-based MIS junctions immersed in electrolyte are explored for use as i.) photoelectrodes for solar-water splitting in photoelectrochemical cells (PECs) and ii.) position-sensitive photodetectors. The development and optimization of MIS photoelectrodes for both of these applications relies heavily on understanding how processing of the thin SiO2 layer impacts the properties of nano- and micro-scale MIS junctions, as well as the interactions of the insulating layer with the electrolyte. In this work, we systematically explore the effects of insulator thickness, synthesis method, and chemical treatment on the photoelectrochemical and electrochemical properties of these MIS devices. It is shown that electrolyte-induced inversion plays a critical role in determining the charge carrier dynamics within the MIS photoelectrodes for both applications.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y.S.; Deb, S.K.

1990-10-02

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

Improved method of preparing p-i-n junctions in amorphous silicon semiconductors

DOEpatents

Madan, A.

1984-12-10

A method of preparing p/sup +/-i-n/sup +/ junctions for amorphous silicon semiconductors includes depositing amorphous silicon on a thin layer of trivalent material, such as aluminum, indium, or gallium at a temperature in the range of 200/sup 0/C to 250/sup 0/C. At this temperature, the layer of trivalent material diffuses into the amorphous silicon to form a graded p/sup +/-i junction. A layer of n-type doped material is then deposited onto the intrinsic amorphous silicon layer in a conventional manner to finish forming the p/sup +/-i-n/sup +/ junction.

Release strategies for making transferable semiconductor structures, devices and device components

DOEpatents

Rogers, John A; Nuzzo, Ralph G; Meitl, Matthew; Ko, Heung Cho; Yoon, Jongseung; Menard, Etienne; Baca, Alfred J

2014-11-25

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Release strategies for making transferable semiconductor structures, devices and device components

DOEpatents

Rogers, John A [Champaign, IL; Nuzzo, Ralph G [Champaign, IL; Meitl, Matthew [Raleigh, NC; Ko, Heung Cho [Urbana, IL; Yoon, Jongseung [Urbana, IL; Menard, Etienne [Durham, NC; Baca, Alfred J [Urbana, IL

2011-04-26

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Enhanced electrical properties of oxide semiconductor thin-film transistors with high conductivity thin layer insertion for the channel region

NASA Astrophysics Data System (ADS)

Nguyen, Cam Phu Thi; Raja, Jayapal; Kim, Sunbo; Jang, Kyungsoo; Le, Anh Huy Tuan; Lee, Youn-Jung; Yi, Junsin

2017-02-01

This study examined the performance and the stability of indium tin zinc oxide (ITZO) thin film transistors (TFTs) by inserting an ultra-thin indium tin oxide (ITO) layer at the active/insulator interface. The electrical properties of the double channel device (ITO thickness of 5 nm) were improved in comparison with the single channel ITZO or ITO devices. The TFT characteristics of the device with an ITO thickness of less than 5 nm were degraded due to the formation of an island-like morphology and the carriers scattering at the active/insulator interface. The 5 nm-thick ITO inserted ITZO TFTs (optimal condition) exhibited a superior field effect mobility (∼95 cm2/V·s) compared with the ITZO-only TFTs (∼34 cm2/V·s). The best characteristics of the TFT devices with double channel layer are due to the lowest surface roughness (0.14 nm) and contact angle (50.1°) that result in the highest hydrophicility, and the most effective adhesion at the surface. Furthermore, the threshold voltage shifts for the ITO/ITZO double layer device decreased to 0.80 and -2.39 V compared with 6.10 and -6.79 V (for the ITZO only device) under positive and negative bias stress, respectively. The falling rates of EA were 0.38 eV/V and 0.54 eV/V for the ITZO and ITO/ITZO bi-layer devices, respectively. The faster falling rate of the double channel devices suggests that the trap density, including interface trap and semiconductor bulk trap, can be decreased by the ion insertion of a very thin ITO film into the ITZO/SiO2 reference device. These results demonstrate that the double active layer TFT can potentially be applied to the flat panel display.

Probing dynamic behavior of electric fields and band diagrams in complex semiconductor heterostructures

NASA Astrophysics Data System (ADS)

Turkulets, Yury; Shalish, Ilan

2018-01-01

Modern bandgap engineered electronic devices are typically made of multi-semiconductor multi-layer heterostructures that pose a major challenge to silicon-era characterization methods. As a result, contemporary bandgap engineering relies mostly on simulated band structures that are hardly ever verified experimentally. Here, we present a method that experimentally evaluates bandgap, band offsets, and electric fields, in complex multi-semiconductor layered structures, and it does so simultaneously in all the layers. The method uses a modest optical photocurrent spectroscopy setup at ambient conditions. The results are analyzed using a simple model for electro-absorption. As an example, we apply the method to a typical GaN high electron mobility transistor structure. Measurements under various external electric fields allow us to experimentally construct band diagrams, not only at equilibrium but also under any other working conditions of the device. The electric fields are then used to obtain the charge carrier density and mobility in the quantum well as a function of the gate voltage over the entire range of operating conditions of the device. The principles exemplified here may serve as guidelines for the development of methods for simultaneous characterization of all the layers in complex, multi-semiconductor structures.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Interface and gate bias dependence responses of sensing organic thin-film transistors.

PubMed

Tanese, Maria Cristina; Fine, Daniel; Dodabalapur, Ananth; Torsi, Luisa

2005-11-15

The effects of the exposure of organic thin-film transistors, comprising different organic semiconductors and gate dielectrics, to 1-pentanol are investigated. The transistor sensors exhibited an increase or a decrease of the transient source-drain current in the presence of the analyte, most likely as a result of a trapping or of a doping process of the organic active layer. The occurrence of these two effects, that can also coexist, depend on the gate-dielectric/organic semiconductor interface and on the applied gate field. Evidence of a systematic and sizable response enhancement for an OTFT sensor operated in the enhanced mode is also presented.

Plasma Reflection in Multigrain Layers of Narrow-Bandgap Semiconductors

NASA Astrophysics Data System (ADS)

Zhukov, N. D.; Shishkin, M. I.; Rokakh, A. G.

2018-04-01

Qualitatively similar spectral characteristics of plasma-resonance reflection in the region of 15-25 μm were obtained for layers of electrodeposited submicron particles of InSb, InAs, and GaAs and plates of these semiconductors ground with M1-grade diamond powder. The most narrow-bandgap semiconductor InSb (intrinsic absorption edge ˜7 μm) is characterized by an absorption band at 2.1-2.3 μm, which is interpreted in terms of the model of optical excitation of electrons coupled by the Coulomb interaction. The spectra of a multigrain layer of chemically deposited PbS nanoparticles (50-70 nm) exhibited absorption maxima at 7, 10, and 17 μm, which can be explained by electron transitions obeying the energy-quantization rules for quantum dots.

Metal-Insulator-Semiconductor Diode Consisting of Two-Dimensional Nanomaterials.

PubMed

Jeong, Hyun; Oh, Hye Min; Bang, Seungho; Jeong, Hyeon Jun; An, Sung-Jin; Han, Gang Hee; Kim, Hyun; Yun, Seok Joon; Kim, Ki Kang; Park, Jin Cheol; Lee, Young Hee; Lerondel, Gilles; Jeong, Mun Seok

2016-03-09

We present a novel metal-insulator-semiconductor (MIS) diode consisting of graphene, hexagonal BN, and monolayer MoS2 for application in ultrathin nanoelectronics. The MIS heterojunction structure was fabricated by vertically stacking layered materials using a simple wet chemical transfer method. The stacking of each layer was confirmed by confocal scanning Raman spectroscopy and device performance was evaluated using current versus voltage (I-V) and photocurrent measurements. We clearly observed better current rectification and much higher current flow in the MIS diode than in the p-n junction and the metal-semiconductor diodes made of layered materials. The I-V characteristic curve of the MIS diode indicates that current flows mainly across interfaces as a result of carrier tunneling. Moreover, we observed considerably high photocurrent from the MIS diode under visible light illumination.

37 CFR 211.5 - Deposit of identifying material.

Code of Federal Regulations, 2011 CFR

2011-07-01

... fixed in the form of the semiconductor chip product in which it was first commercially exploited... photograph of each layer of the work fixed in a semiconductor chip product. The visually perceptible... complete form of the mask work as fixed in a semiconductor product. (ii) Where the mask work contribution...

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

1987-06-08

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space. The layer thicknesses of the quantum well layers are selected to provide a superlattice L/sub 2D/-valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley. 2 figs.

Plastic Schottky barrier solar cells

DOEpatents

Waldrop, James R.; Cohen, Marshall J.

1984-01-24

A photovoltaic cell structure is fabricated from an active medium including an undoped, intrinsically p-type organic semiconductor comprising polyacetylene. When a film of such material is in rectifying contact with a magnesium electrode, a Schottky-barrier junction is obtained within the body of the cell structure. Also, a gold overlayer passivates the magnesium layer on the undoped polyacetylene film.

Influence of the Compositional Grading on Concentration of Majority Charge Carriers in Near-Surface Layers of n(p)-HgCdTe Grown by Molecular Beam Epitaxy

NASA Astrophysics Data System (ADS)

Voitsekhovskii, A. V.; Nesmelov, S. N.; Dzyadukh, S. M.

2018-02-01

The capacitive characteristics of metal-insulator-semiconductor (MIS) structures based on the compositionally graded Hg1-xCdxTe created by molecular beam epitaxy have been experimentally investigated in a wide temperature range (8-77 K). A program has been developed for numerical simulation of ideal capacitance-voltage (C-V) characteristics in the low-frequency and high-frequency approximations. The concentrations of the majority carriers in the near-surface semiconductor layer are determined from the values of the capacitances in the minima of low-frequency C-V curves. For MIS structures based on p-Hg1-xCdxTe, the effect of the presence of the compositionally graded layer on the hole concentration in the near-surface semiconductor layer, determined from capacitive measurements, has not been established. Perhaps this is due to the fact that the concentration of holes in the near-surface layer largely depends on the type of dielectric coating and the regimes of its application. For MIS structures based on n-Hg1-x Cd x Te (x = 0.22-0.23) without a graded-gap layer, the electron concentration determined by the proposed method is close to the average concentration determined by the Hall measurements. The electron concentration in the near-surface semiconductor layer of the compositionally graded n-Hg1-x Cd x Te (x = 0.22-0.23) found from the minimum capacitance value is much higher than the average electron concentration determined by the Hall measurements. The results are qualitatively explained by the creation of additional intrinsic donor-type defects in the near-surface compositionally graded layer of n-Hg1-x Cd x Te.

Synthesis of chemicals using solar energy with stable photoelectrochemically active heterostructures.

PubMed

Mubeen, Syed; Singh, Nirala; Lee, Joun; Stucky, Galen D; Moskovits, Martin; McFarland, Eric W

2013-05-08

Efficient and cost-effective conversion of solar energy to useful chemicals and fuels could lead to a significant reduction in fossil hydrocarbon use. Artificial systems that use solar energy to produce chemicals have been reported for more than a century. However the most efficient devices demonstrated, based on traditionally fabricated compound semiconductors, have extremely short working lifetimes due to photocorrosion by the electrolyte. Here we report a stable, scalable design and molecular level fabrication strategy to create photoelectrochemically active heterostructure (PAH) units consisting of an efficient semiconductor light absorber in contact with oxidation and reduction electrocatalysts and otherwise protected by alumina. The functional heterostructures are fabricated by layer-by-layer, template-directed, electrochemical synthesis in porous anodic aluminum oxide membranes to produce high density arrays of electronically autonomous, nanostructured, corrosion resistant, photoactive units (~10(9)-10(10) PAHs per cm(2)). Each PAH unit is isolated from its neighbor by the transparent electrically insulating oxide cellular enclosure that makes the overall assembly fault tolerant. When illuminated with visible light, the free floating devices have been demonstrated to produce hydrogen at a stable rate for over 24 h in corrosive hydroiodic acid electrolyte with light as the only input. The quantum efficiency (averaged over the solar spectrum) for absorbed photons-to-hydrogen conversion was 7.4% and solar-to-hydrogen energy efficiency of incident light was 0.9%. The fabrication approach is scalable for commercial manufacturing and readily adaptable to a variety of earth abundant semiconductors which might otherwise be unstable as photoelectrocatalysts.

Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor)

2011-01-01

Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.

Planar varactor frequency multiplier devices with blocking barrier

NASA Technical Reports Server (NTRS)

Lieneweg, Udo (Inventor); Frerking, Margaret A. (Inventor); Maserjian, Joseph (Inventor)

1994-01-01

The invention relates to planar varactor frequency multiplier devices with a heterojunction blocking barrier for near millimeter wave radiation of moderate power from a fundamental input wave. The space charge limitation of the submillimeter frequency multiplier devices of the BIN(sup +) type is overcome by a diode structure comprising an n(sup +) doped layer of semiconductor material functioning as a low resistance back contact, a layer of semiconductor material with n-type doping functioning as a drift region grown on the back contact layer, a delta doping sheet forming a positive charge at the interface of the drift region layer with a barrier layer, and a surface metal contact. The layers thus formed on an n(sup +) doped layer may be divided into two isolated back-to-back BNN(sup +) diodes by separately depositing two surface metal contacts. By repeating the sequence of the drift region layer and the barrier layer with the delta doping sheet at the interfaces between the drift and barrier layers, a plurality of stacked diodes is formed. The novelty of the invention resides in providing n-type semiconductor material for the drift region in a GaAs/AlGaAs structure, and in stacking a plurality of such BNN(sup +) diodes stacked for greater output power with and connected back-to-back with the n(sup +) GaAs layer as an internal back contact and separate metal contact over an AlGaAs barrier layer on top of each stack.

Fast optical detecting media based on semiconductor nanostructures for recording images obtained using charges of free photocarriers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kasherininov, P. G., E-mail: peter.kasherininov@mail.ioffe.ru; Tomasov, A. A.; Beregulin, E. V.

2011-01-15

Available published data on the properties of optical recording media based on semiconductor structures are reviewed. The principles of operation, structure, parameters, and the range of application for optical recording media based on MIS structures formed of photorefractive crystals with a thick layer of insulator and MIS structures with a liquid crystal as the insulator (the MIS LC modulators), as well as the effect of optical bistability in semiconductor structures (semiconductor MIS structures with nanodimensionally thin insulator (TI) layer, M(TI)S nanostructures). Special attention is paid to recording media based on the M(TI)S nanostructures promising for fast processing of highly informativemore » images and to fabrication of optoelectronic correlators of images for noncoherent light.« less

Low temperature thin films formed from nanocrystal precursors

DOEpatents

Alivisatos, A. Paul; Goldstein, Avery N.

1993-01-01

Nanocrystals of semiconductor compounds are produced. When they are applied as a contiguous layer onto a substrate and heated they fuse into a continuous layer at temperatures as much as 250, 500, 750 or even 1000.degree. K below their bulk melting point. This allows continuous semiconductor films in the 0.25 to 25 nm thickness range to be formed with minimal thermal exposure.

Low temperature thin films formed from nanocrystal precursors

DOEpatents

Alivisatos, A.P.; Goldstein, A.N.

1993-11-16

Nanocrystals of semiconductor compounds are produced. When they are applied as a contiguous layer onto a substrate and heated they fuse into a continuous layer at temperatures as much as 250, 500, 750 or even 1000 K below their bulk melting point. This allows continuous semiconductor films in the 0.25 to 25 nm thickness range to be formed with minimal thermal exposure. 9 figures.

Deposition method for producing silicon carbide high-temperature semiconductors

DOEpatents

Hsu, George C.; Rohatgi, Naresh K.

1987-01-01

An improved deposition method for producing silicon carbide high-temperature semiconductor material comprising placing a semiconductor substrate composed of silicon carbide in a fluidized bed silicon carbide deposition reactor, fluidizing the bed particles by hydrogen gas in a mildly bubbling mode through a gas distributor and heating the substrate at temperatures around 1200.degree.-1500.degree. C. thereby depositing a layer of silicon carbide on the semiconductor substrate.

Layered semiconductor neutron detectors

DOEpatents

Mao, Samuel S; Perry, Dale L

2013-12-10

Room temperature operating solid state hand held neutron detectors integrate one or more relatively thin layers of a high neutron interaction cross-section element or materials with semiconductor detectors. The high neutron interaction cross-section element (e.g., Gd, B or Li) or materials comprising at least one high neutron interaction cross-section element can be in the form of unstructured layers or micro- or nano-structured arrays. Such architecture provides high efficiency neutron detector devices by capturing substantially more carriers produced from high energy .alpha.-particles or .gamma.-photons generated by neutron interaction.

Tuning the Performance of Organic Spintronic Devices Using X-Ray Generated Traps

DTIC Science & Technology

2012-08-16

observed in organic devices using the same organic semiconductor, namely tris(8-hydroxyquinoli- nato)aluminium ( Alq3 ) [5,15]. Here we will show that the...manufacturing steps were carried out in a deposition chamber located inside a nitrogen glovebox. Next, the organic layer Alq3 (70 to 100 nm) followed by the...As the organic semiconductor spacer layer, the Alq3 layer was fabricated by thermal evaporation in a vacuum of 10Ś mbar at a rate of 0:1 nm=s. The Fe

Photo-voltaic power generating means and methods

DOEpatents

Kroger, Ferdinand A.; Rod, Robert L.; Panicker, M. P. Ramachandra

1983-08-23

A photo-voltaic power cell based on a photoelectric semiconductor compound and the method of using and making the same. The semiconductor compound in the photo-voltaic power cell of the present invention can be electrolytically formed at a cathode in an electrolytic solution by causing discharge or decomposition of ions or molecules of a non-metallic component with deposition of the non-metallic component on the cathode and simultaneously providing ions of a metal component which discharge and combine with the non-metallic component at the cathode thereby forming the semiconductor compound film material thereon. By stoichiometrically adjusting the amounts of the components, or otherwise by introducing dopants into the desired amounts, an N-type layer can be formed and thereafter a P-type layer can be formed with a junction therebetween. The invention is effective in producing homojunction semiconductor materials and heterojunction semiconductor materials. The present invention also provides a method of using three electrodes in order to form the semiconductor compound material on one of these electrodes. Various examples are given for manufacturing different photo-voltaic cells in accordance with the present invention.

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Photo-voltaic power generating means and methods

DOEpatents

Kroger, Ferdinand A.; Rod, Robert L.; Panicker, Ramachandra M. P.; Knaster, Mark B.

1984-01-10

A photo-voltaic power cell based on a photoelectric semiconductor compound and the method of using and making the same. The semiconductor compound in the photo-voltaic power cell of the present invention can be electrolytically formed at a cathode in an electrolytic solution by causing discharge or decomposition of ions or molecules of a non-metallic component with deposition of the non-metallic component on the cathode and simultaneously providing ions of a metal component which discharge and combine with the non-metallic component at the cathode thereby forming the semiconductor compound film material thereon. By stoichiometrically adjusting the amounts of the components, or otherwise by introducing dopants into the desired amounts, an N-type layer can be formed and thereafter a P-type layer can be formed with a junction therebetween. The invention is effective in producing homojunction semiconductor materials and heterojunction semiconductor materials. The present invention also provides a method of using three electrodes in order to form the semiconductor compound material on one of these electrodes. Various examples are given for manufacturing different photo-voltaic cells in accordance with the present invention.

Time-Resolved Photoluminescence Microscopy for the Analysis of Semiconductor-Based Paint Layers

PubMed Central

Mosca, Sara; Gonzalez, Victor; Eveno, Myriam

2017-01-01

In conservation, science semiconductors occur as the constituent matter of the so-called semiconductor pigments, produced following the Industrial Revolution and extensively used by modern painters. With recent research highlighting the occurrence of various degradation phenomena in semiconductor paints, it is clear that their detection by conventional optical fluorescence imaging and microscopy is limited by the complexity of historical painting materials. Here, we illustrate and prove the capabilities of time-resolved photoluminescence (TRPL) microscopy, equipped with both spectral and lifetime sensitivity at timescales ranging from nanoseconds to hundreds of microseconds, for the analysis of cross-sections of paint layers made of luminescent semiconductor pigments. The method is sensitive to heterogeneities within micro-samples and provides valuable information for the interpretation of the nature of the emissions in samples. A case study is presented on micro samples from a painting by Henri Matisse and serves to demonstrate how TRPL can be used to identify the semiconductor pigments zinc white and cadmium yellow, and to inform future investigations of the degradation of a cadmium yellow paint. PMID:29160862

Surface Passivation by Quantum Exclusion Using Multiple Layers

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor)

2015-01-01

A semiconductor device has a multilayer doping to provide improved passivation by quantum exclusion. The multilayer doping includes at least two doped layers fabricated using MBE methods. The dopant sheet densities in the doped layers need not be the same, but in principle can be selected to be the same sheet densities or to be different sheet densities. The electrically active dopant sheet densities are quite high, reaching more than 1.times.10.sup.14 cm.sup.-2, and locally exceeding 10.sup.22 per cubic centimeter. It has been found that silicon detector devices that have two or more such dopant layers exhibit improved resistance to degradation by UV radiation, at least at wavelengths of 193 nm, as compared to conventional silicon p-on-n devices.

Blending crystalline/liquid crystalline small molecule semiconductors: A strategy towards high performance organic thin film transistors

NASA Astrophysics Data System (ADS)

He, Chao; He, Yaowu; Li, Aiyuan; Zhang, Dongwei; Meng, Hong

2016-10-01

Solution processed small molecule polycrystalline thin films often suffer from the problems of inhomogeneity and discontinuity. Here, we describe a strategy to solve these problems through deposition of the active layer from a blended solution of crystalline (2-phenyl[1]benzothieno[3,2-b][1]benzothiophene, Ph-BTBT) and liquid crystalline (2-(4-dodecylphenyl) [1]benzothieno[3,2-b]benzothiophene, C12-Ph-BTBT) small molecule semiconductors with the hot spin-coating method. Organic thin film transistors with average hole mobility approaching 1 cm2/V s, much higher than that of single component devices, have been demonstrated, mainly due to the improved uniformity, continuity, crystallinity, and stronger intermolecular π-π stacking in blend thin films. Our results indicate that the crystalline/liquid crystalline semiconductor blend method is an effective way to enhance the performance of organic transistors.

Bonding and electronics of the MoTe2/Ge interface under strain

NASA Astrophysics Data System (ADS)

Szary, Maciej J.; Michalewicz, Marek T.; Radny, Marian W.

2017-05-01

Understanding the interface formation of a conventional semiconductor with a monolayer of transition-metal dichalcogenides provides a necessary platform for the anticipated applications of dichalcogenides in electronics and optoelectronics. We report here, based on the density functional theory, that under in-plane tensile strain, a 2H semiconducting phase of the molybdenum ditelluride (MoTe2) monolayer undergoes a semiconductor-to-metal transition and in this form bonds covalently to bilayers of Ge stacked in the [111] crystal direction. This gives rise to the stable bonding configuration of the MoTe2/Ge interface with the ±K valley metallic, electronic interface states exclusively of a Mo 4 d character. The atomically sharp Mo layer represents therefore an electrically active (conductive) subsurface δ -like two-dimensional profile that can exhibit a valley-Hall effect. Such system can develop into a key element of advanced semiconductor technology or a novel device concept.

The initial stages of ZnO atomic layer deposition on atomically flat In0.53Ga0.47As substrates.

PubMed

Skopin, Evgeniy V; Rapenne, Laetitia; Roussel, Hervé; Deschanvres, Jean-Luc; Blanquet, Elisabeth; Ciatto, Gianluca; Fong, Dillon D; Richard, Marie-Ingrid; Renevier, Hubert

2018-06-21

InGaAs is one of the III-V active semiconductors used in modern high-electron-mobility transistors or high-speed electronics. ZnO is a good candidate material to be inserted as a tunneling insulator layer at the metal-semiconductor junction. A key consideration in many modern devices is the atomic structure of the hetero-interface, which often ultimately governs the electronic or chemical process of interest. Here, a complementary suite of in situ synchrotron X-ray techniques (fluorescence, reflectivity and absorption) as well as modeling is used to investigate both structural and chemical evolution during the initial growth of ZnO by atomic layer deposition (ALD) on In0.53Ga0.47As substrates. Prior to steady-state growth behavior, we discover a transient regime characterized by two stages. First, substrate-inhibited ZnO growth takes place on InGaAs terraces. This leads eventually to the formation of a 1 nm-thick, two-dimensional (2D) amorphous layer. Second, the growth behavior and its modeling suggest the occurrence of dense island formation, with an aspect ratio and surface roughness that depends sensitively on the growth condition. Finally, ZnO ALD on In0.53Ga0.47As is characterized by 2D steady-state growth with a linear growth rate of 0.21 nm cy-1, as expected for layer-by-layer ZnO ALD.

A multifunctional biphasic water splitting catalyst tailored for integration with high-performance semiconductor photoanodes

DOE PAGES

Yang, Jinhui; Cooper, Jason K.; Toma, Francesca M.; ...

2016-11-07

Artificial photosystems are advanced by the development of conformal catalytic materials that promote desired chemical transformations, while also maintaining stability and minimizing parasitic light absorption for integration on surfaces of semiconductor light absorbers. We demonstrate that multifunctional, nanoscale catalysts that enable high-performance photoelectrochemical energy conversion can be engineered by plasma-enhanced atomic layer deposition. The collective properties of tailored Co 3 O 4 /Co(OH) 2 thin films simultaneously provide high activity for water splitting, permit efficient interfacial charge transport from semiconductor substrates, and enhance durability of chemically sensitive interfaces. Furthermore, these films comprise compact and continuous nanocrystalline Co 3 O 4more » spinel that is impervious to phase transformation and impermeable to ions, thereby providing effective protection of the underlying substrate. Moreover, a secondary phase of structurally disordered and chemically labile Co(OH) 2 is introduced to ensure a high concentration of catalytically active sites. Application of this coating to photovoltaic p + n-Si junctions yields best reported performance characteristics for crystalline Si photoanodes.« less

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Semiconductor cylinder fiber laser

NASA Astrophysics Data System (ADS)

Sandupatla, Abhinay; Flattery, James; Kornreich, Philipp

2015-12-01

We fabricated a fiber laser that uses a thin semiconductor layer surrounding the glass core as the gain medium. This is a completely new type of laser. The In2Te3 semiconductor layer is about 15-nm thick. The fiber laser has a core diameter of 14.2 μm, an outside diameter of 126 μm, and it is 25-mm long. The laser mirrors consist of a thick vacuum-deposited aluminum layer at one end and a thin semitransparent aluminum layer deposited at the other end of the fiber. The laser is pumped from the side with either light from a halogen tungsten incandescent lamp or a blue light emitting diode flash light. Both the In2Te3 gain medium and the aluminum mirrors have a wide bandwidth. Therefore, the output spectrum consists of a pedestal from a wavelength of about 454 to 623 nm with several peaks. There is a main peak at 545 nm. The main peak has an amplitude of 16.5 dB above the noise level of -73 dB.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

PubMed Central

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

Apparatus and methods for memory using in-plane polarization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Junwei; Chang, Kai; Ji, Shuai-Hua

A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process ismore » non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.« less

Metal-oxide-semiconductor devices using Ga2O3 dielectrics on n-type GaN

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Chen, Hong-Wei; Lee, Hsin-Ying

2003-06-01

Using a photoelectrochemical method involving a He-Cd laser, Ga2O3 oxide layers were directly grown on n-type GaN. We demonstrated the performance of the resultant metal-oxide-semiconductor devices based on the grown Ga2O3 layer. An extremely low reverse leakage current of 200 pA was achieved when devices operated at -20 V. Furthermore, high forward and reverse breakdown electric fields of 2.80 MV/cm and 5.70 MV/cm, respectively, were obtained. Using a photoassisted current-voltage method, a low interface state density of 2.53×1011 cm-2 eV-1 was estimated. The varactor devices permit formation of inversion layers, so that they may be applied for the fabrication of metal-oxide-semiconductor field-effect transistors.

Prediction of weak topological insulators in layered semiconductors.

PubMed

Yan, Binghai; Müchler, Lukas; Felser, Claudia

2012-09-14

We report the discovery of weak topological insulators by ab initio calculations in a honeycomb lattice. We propose a structure with an odd number of layers in the primitive unit cell as a prerequisite for forming weak topological insulators. Here, the single-layered KHgSb is the most suitable candidate for its large bulk energy gap of 0.24 eV. Its side surface hosts metallic surface states, forming two anisotropic Dirac cones. Although the stacking of even-layered structures leads to trivial insulators, the structures can host a quantum spin Hall layer with a large bulk gap, if an additional single layer exists as a stacking fault in the crystal. The reported honeycomb compounds can serve as prototypes to aid in the finding of new weak topological insulators in layered small-gap semiconductors.

Ultrafast and Ultrasensitive Gas Sensors Derived from a Large Fermi-Level Shift in the Schottky Junction with Sieve-Layer Modulation.

PubMed

Cheng, Ching-Cheng; Wu, Chia-Lin; Liao, Yu-Ming; Chen, Yang-Fang

2016-07-13

Gas sensors play an important role in numerous fields, covering a wide range of applications, including intelligent systems and detection of harmful and toxic gases. Even though they have attracted much attention, the response time on the order of seconds to minutes is still very slow. To circumvent the existing problems, here, we provide a seminal attempt with the integration of graphene, semiconductor, and an addition sieve layer forming a nanocomposite gas sensor with ultrahigh sensitivity and ultrafast response. The designed sieve layer has a suitable band structure that can serve as a blocking layer to prevent transfer of the charges induced by adsorbed gas molecules into the underlying semiconductor layer. We found that the sensitivity can be reduced to the parts per million level, and the ultrafast response of around 60 ms is unprecedented compared with published graphene-based gas sensors. The achieved high performance can be interpreted well by the large change of the Fermi level of graphene due to its inherent nature of the low density of states and blocking of the sieve layer to prevent charge transfer from graphene to the underlying semiconductor layer. Accordingly, our work is very useful and timely for the development of gas sensors with high performance for practical applications.

Method and apparatus for increasing the durability and yield of thin film photovoltaic devices

DOEpatents

Phillips, J.E.; Lasswell, P.G.

1987-02-03

Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device. 10 figs.

Method and apparatus for increasing the durability and yield of thin film photovoltaic devices

DOEpatents

Phillips, James E.; Lasswell, Patrick G.

1987-01-01

Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device.

Investigations on Substrate Temperature-Induced Growth Modes of Organic Semiconductors at Dielectric/semiconductor Interface and Their Correlation with Threshold Voltage Stability in Organic Field-Effect Transistors.

PubMed

Padma, Narayanan; Maheshwari, Priya; Bhattacharya, Debarati; Tokas, Raj B; Sen, Shashwati; Honda, Yoshihide; Basu, Saibal; Pujari, Pradeep Kumar; Rao, T V Chandrasekhar

2016-02-10

Influence of substrate temperature on growth modes of copper phthalocyanine (CuPc) thin films at the dielectric/semiconductor interface in organic field effect transistors (OFETs) is investigated. Atomic force microscopy (AFM) imaging at the interface reveals a change from 'layer+island' to "island" growth mode with increasing substrate temperatures, further confirmed by probing the buried interfaces using X-ray reflectivity (XRR) and positron annihilation spectroscopic (PAS) techniques. PAS depth profiling provides insight into the details of molecular ordering while positron lifetime measurements reveal the difference in packing modes of CuPc molecules at the interface. XRR measurements show systematic increase in interface width and electron density correlating well with the change from layer + island to coalesced huge 3D islands at higher substrate temperatures. Study demonstrates the usefulness of XRR and PAS techniques to study growth modes at buried interfaces and reveals the influence of growth modes of semiconductor at the interface on hole and electron trap concentrations individually, thereby affecting hysteresis and threshold voltage stability. Minimum hole trapping is correlated to near layer by layer formation close to the interface at 100 °C and maximum to the island formation with large voids between the grains at 225 °C.

Pump-probe surface photovoltage spectroscopy measurements on semiconductor epitaxial layers.

PubMed

Jana, Dipankar; Porwal, S; Sharma, T K; Kumar, Shailendra; Oak, S M

2014-04-01

Pump-probe Surface Photovoltage Spectroscopy (SPS) measurements are performed on semiconductor epitaxial layers. Here, an additional sub-bandgap cw pump laser beam is used in a conventional chopped light geometry SPS setup under the pump-probe configuration. The main role of pump laser beam is to saturate the sub-bandgap localized states whose contribution otherwise swamp the information related to the bandgap of material. It also affects the magnitude of Dember voltage in case of semi-insulating (SI) semiconductor substrates. Pump-probe SPS technique enables an accurate determination of the bandgap of semiconductor epitaxial layers even under the strong influence of localized sub-bandgap states. The pump beam is found to be very effective in suppressing the effect of surface/interface and bulk trap states. The overall magnitude of SPV signal is decided by the dependence of charge separation mechanisms on the intensity of the pump beam. On the contrary, an above bandgap cw pump laser can be used to distinguish the signatures of sub-bandgap states by suppressing the band edge related feature. Usefulness of the pump-probe SPS technique is established by unambiguously determining the bandgap of p-GaAs epitaxial layers grown on SI-GaAs substrates, SI-InP wafers, and p-GaN epilayers grown on Sapphire substrates.

Highly efficient quantum dot-based photoconductive THz materials and devices

NASA Astrophysics Data System (ADS)

Rafailov, E. U.; Leyman, R.; Carnegie, D.; Bazieva, N.

2013-09-01

We demonstrate Terahertz (THz) signal sources based on photoconductive (PC) antenna devices comprising active layers of InAs semiconductor quantum dots (QDs) on GaAs. Antenna structures comprised of multiple active layers of InAs:GaAs PC materials are optically pumped using ultrashort pulses generated by a Ti:Sapphire laser and CW dualwavelength laser diodes. We also characterised THz output signals using a two-antenna coherent detection system. We discuss preliminary performance data from such InAs:GaAs THz devices which exhibit efficient emission of both pulsed and continuous wave (CW) THz signals and significant optical-to-THz conversion at both absorption wavelength ranges, <=850 nm and <=1300 nm.

Nanoscale semiconductor Pb1-xSnxSe (x = 0.2) thin films synthesized by electrochemical atomic layer deposition

NASA Astrophysics Data System (ADS)

Lin, Shaoxiong; Zhang, Xin; Shi, Xuezhao; Wei, Jinping; Lu, Daban; Zhang, Yuzhen; Kou, Huanhuan; Wang, Chunming

2011-04-01

In this paper the fabrication and characterization of IV-VI semiconductor Pb1-xSnxSe (x = 0.2) thin films on gold substrate by electrochemical atomic layer deposition (EC-ALD) method at room temperature are reported. Cyclic voltammetry (CV) is used to determine approximate deposition potentials for each element. The amperometric I-t technique is used to fabricate the semiconductor alloy. The elements are deposited in the following sequence: (Se/Pb/Se/Pb/Se/Pb/Se/Pb/Se/Sn …), each period is formed using four ALD cycles of PbSe followed by one cycle of SnSe. Then the deposition manner above is cyclic repeated till a satisfactory film with expected thickness of Pb1-xSnxSe is obtained. The morphology of the deposit is observed by field emission scanning electron microscopy (FE-SEM). X-ray diffraction (XRD) pattern is used to study its crystalline structure; X-ray photoelectron spectroscopy (XPS) of the deposit indicates an approximate ratio 1.0:0.8:0.2 of Se, Pb and Sn, as the expected stoichiometry for the deposit. Open-circuit potential (OCP) studies indicate a good p-type property, and the good optical activity makes it suitable for fabricating a photoelectric switch.

The AMOS cell - An improved metal-semiconductor solar cell. [Antireflection coated Metal Oxide Semiconductor

NASA Technical Reports Server (NTRS)

Stirn, R. J.; Yeh, Y.-C. M.

1975-01-01

A new fabrication process is being developed which significantly improves the efficiency of metal-semiconductor solar cells. The resultant effect, a marked increase in the open-circuit voltage, is produced by the addition of an interfacial layer oxide on the semiconductor. Cells using gold on n-type gallium arsenide have been made in small areas (0.17 sq cm) with conversion efficiencies of 15% in terrestrial sunlight.

Materials Science and Device Physics of 2-Dimensional Semiconductors

NASA Astrophysics Data System (ADS)

Fang, Hui

Materials and device innovations are the keys to future technology revolution. For MOSFET scaling in particular, semiconductors with ultra-thin thickness on insulator platform is currently of great interest, due to the potential of integrating excellent channel materials with the industrially mature Si processing. Meanwhile, ultra-thin thickness also induces strong quantum confinement which in turn affect most of the material properties of these 2-dimensional (2-D) semiconductors, providing unprecedented opportunities for emerging technologies. In this thesis, multiple novel 2-D material systems are explored. Chapter one introduces the present challenges faced by MOSFET scaling. Chapter two covers the integration of ultrathin III V membranes with Si. Free standing ultrathin III-V is studied to enable high performance III-V on Si MOSFETs with strain engineering and alloying. Chapter three studies the light absorption in 2-D membranes. Experimental results and theoretical analysis reveal that light absorption in the 2-D quantum membranes is quantized into a fundamental physical constant, where we call it the quantum unit of light absorption, irrelevant of most of the material dependent parameters. Chapter four starts to focus on another 2-D system, atomic thin layered chalcogenides. Single and few layered chalcogenides are first explored as channel materials, with focuses in engineering the contacts for high performance MOSFETs. Contact treatment by molecular doping methods reveals that many layered chalcogenides other than MoS2 exhibit good transport properties at single layer limit. Finally, Chapter five investigated 2-D van der Waals heterostructures built from different single layer chalcogenides. The investigation in a WSe2/MoS2 hetero-bilayer shows a large Stokes like shift between photoluminescence peak and lowest absorption peak, as well as strong photoluminescence intensity, consistent with spatially indirect transition in a type II band alignment in this van der Waals heterostructure. This result enables new family of semiconductor heterostructures having tunable optoelectronic properties with customized composite layers and highlights the ability to build van der Waals semiconductor heterostructure lasers/LEDs.

Magnetism in Mn-nanowires and -clusters as δ-doped layers in group IV semiconductors (Si, Ge)

NASA Astrophysics Data System (ADS)

Simov, K. R.; Glans, P.-A.; Jenkins, C. A.; Liberati, M.; Reinke, P.

2018-01-01

Mn doping of group-IV semiconductors (Si/Ge) is achieved by embedding nanostructured Mn-layers in group-IV matrix. The Mn-nanostructures are monoatomic Mn-wires or Mn-clusters and capped with an amorphous Si or Ge layer. The precise fabrication of δ-doped Mn-layers is combined with element-specific detection of the magnetic signature with x-ray magnetic circular dichroism. The largest moment (2.5 μB/Mn) is measured for Mn-wires with ionic bonding character and a-Ge overlayer cap; a-Si capping reduces the moment due to variations of bonding in agreement with theoretical predictions. The moments in δ-doped layers dominated by clusters is quenched with an antiferromagnetic component from Mn-Mn bonding.

Ultra-thin ohmic contacts for p-type nitride light emitting devices

DOEpatents

Raffetto, Mark; Bharathan, Jayesh; Haberern, Kevin; Bergmann, Michael; Emerson, David; Ibbetson, James; Li, Ting

2014-06-24

A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 .ANG.. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

A lead-halide perovskite molecular ferroelectric semiconductor

PubMed Central

Liao, Wei-Qiang; Zhang, Yi; Hu, Chun-Li; Mao, Jiang-Gao; Ye, Heng-Yun; Li, Peng-Fei; Huang, Songping D.; Xiong, Ren-Gen

2015-01-01

Inorganic semiconductor ferroelectrics such as BiFeO3 have shown great potential in photovoltaic and other applications. Currently, semiconducting properties and the corresponding application in optoelectronic devices of hybrid organo-plumbate or stannate are a hot topic of academic research; more and more of such hybrids have been synthesized. Structurally, these hybrids are suitable for exploration of ferroelectricity. Therefore, the design of molecular ferroelectric semiconductors based on these hybrids provides a possibility to obtain new or high-performance semiconductor ferroelectrics. Here we investigated Pb-layered perovskites, and found the layer perovskite (benzylammonium)2PbCl4 is ferroelectric with semiconducting behaviours. It has a larger ferroelectric spontaneous polarization Ps=13 μC cm−2 and a higher Curie temperature Tc=438 K with a band gap of 3.65 eV. This finding throws light on the new properties of the hybrid organo-plumbate or stannate compounds and provides a new way to develop new semiconductor ferroelectrics. PMID:26021758

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2017-01-01

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2016-01-01

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Interface engineering of colloidal CdSe quantum dots thin films as acid-stable photocathodes for solar-driven hydrogen evolution

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Hui; Wen, Peng; Hoxie, Adam

Colloidal semiconductor quantum dots-based (CQD) photocathodes for solar-driven hydrogen evolution have attracted significant attention due to their tunable size, nanostructured morphology, crystalline orientation, and band-gap. Here, we report a thin film heterojunction photocathode composed of organic PEDOT:PSS as a hole transport layer, CdSe CQDs as a semiconductor light absorber, and conformal Pt layer deposited by atomic layer deposition (ALD) serving as both a passivation layer and cocatalyst for hydrogen evolution. In neutral aqueous solution, a PEDOT:PSS/CdSe/Pt heterogeneous photocathode with 200 cycles of ALD Pt produces a photocurrent density of -1.08 mA/cm 2 (AM1.5G, 100 mW/cm 2) at a potential ofmore » 0 V vs. RHE (j 0) in neutral aqueous solution, which is nearly 12 times that of the pristine CdSe photocathode. This composite photocathode shows an onset potential for water reduction at +0.46 V vs. RHE and long-term stability with negligible degradation. In acidic electrolyte (pH = 1), where the hydrogen evolution reaction is more favorable but stability is limited due to photocorrosion, a thicker Pt film (300 cycles) is shown to greatly improve the device stability and a j 0 of -2.14 mA/cm 2 is obtained with only 8.3% activity degradation after 6 h, compared to 80% degradation under the same conditions when the less conformal electrodeposition method is used to deposit the Pt layer. Electrochemical impedance spectroscopy and time-resolved photoluminescence results indicate that these enhancements stem from a lower bulk charge recombination rate, higher interfacial charge transfer rate, and faster reaction kinetics. In conclusion, we believe that these interface engineering strategies can be extended to other colloidal semiconductors to construct more efficient and stable heterogeneous photoelectrodes for solar fuel production.« less

Interface engineering of colloidal CdSe quantum dots thin films as acid-stable photocathodes for solar-driven hydrogen evolution

DOE PAGES

Li, Hui; Wen, Peng; Hoxie, Adam; ...

2018-04-30

Colloidal semiconductor quantum dots-based (CQD) photocathodes for solar-driven hydrogen evolution have attracted significant attention due to their tunable size, nanostructured morphology, crystalline orientation, and band-gap. Here, we report a thin film heterojunction photocathode composed of organic PEDOT:PSS as a hole transport layer, CdSe CQDs as a semiconductor light absorber, and conformal Pt layer deposited by atomic layer deposition (ALD) serving as both a passivation layer and cocatalyst for hydrogen evolution. In neutral aqueous solution, a PEDOT:PSS/CdSe/Pt heterogeneous photocathode with 200 cycles of ALD Pt produces a photocurrent density of -1.08 mA/cm 2 (AM1.5G, 100 mW/cm 2) at a potential ofmore » 0 V vs. RHE (j 0) in neutral aqueous solution, which is nearly 12 times that of the pristine CdSe photocathode. This composite photocathode shows an onset potential for water reduction at +0.46 V vs. RHE and long-term stability with negligible degradation. In acidic electrolyte (pH = 1), where the hydrogen evolution reaction is more favorable but stability is limited due to photocorrosion, a thicker Pt film (300 cycles) is shown to greatly improve the device stability and a j 0 of -2.14 mA/cm 2 is obtained with only 8.3% activity degradation after 6 h, compared to 80% degradation under the same conditions when the less conformal electrodeposition method is used to deposit the Pt layer. Electrochemical impedance spectroscopy and time-resolved photoluminescence results indicate that these enhancements stem from a lower bulk charge recombination rate, higher interfacial charge transfer rate, and faster reaction kinetics. In conclusion, we believe that these interface engineering strategies can be extended to other colloidal semiconductors to construct more efficient and stable heterogeneous photoelectrodes for solar fuel production.« less

Interface Engineering of Colloidal CdSe Quantum Dot Thin Films as Acid-Stable Photocathodes for Solar-Driven Hydrogen Evolution.

PubMed

Li, Hui; Wen, Peng; Hoxie, Adam; Dun, Chaochao; Adhikari, Shiba; Li, Qi; Lu, Chang; Itanze, Dominique S; Jiang, Lin; Carroll, David; Lachgar, Abdou; Qiu, Yejun; Geyer, Scott M

2018-05-23

Colloidal semiconductor quantum dot (CQD)-based photocathodes for solar-driven hydrogen evolution have attracted significant attention because of their tunable size, nanostructured morphology, crystalline orientation, and band gap. Here, we report a thin film heterojunction photocathode composed of organic PEDOT:PSS as a hole transport layer, CdSe CQDs as a semiconductor light absorber, and conformal Pt layer deposited by atomic layer deposition (ALD) serving as both a passivation layer and cocatalyst for hydrogen evolution. In neutral aqueous solution, a PEDOT:PSS/CdSe/Pt heterogeneous photocathode with 200 cycles of ALD Pt produces a photocurrent density of -1.08 mA/cm 2 (AM-1.5G, 100 mW/cm 2 ) at a potential of 0 V versus reversible hydrogen electrode (RHE) ( j 0 ) in neutral aqueous solution, which is nearly 12 times that of the pristine CdSe photocathode. This composite photocathode shows an onset potential for water reduction at +0.46 V versus RHE and long-term stability with negligible degradation. In the acidic electrolyte (pH = 1), where the hydrogen evolution reaction is more favorable but stability is limited because of photocorrosion, a thicker Pt film (300 cycles) is shown to greatly improve the device stability and a j 0 of -2.14 mA/cm 2 is obtained with only 8.3% activity degradation after 6 h, compared with 80% degradation under the same conditions when the less conformal electrodeposition method is used to deposit the Pt layer. Electrochemical impedance spectroscopy and time-resolved photoluminescence results indicate that these enhancements stem from a lower bulk charge recombination rate, higher interfacial charge-transfer rate, and faster reaction kinetics. We believe that these interface engineering strategies can be extended to other colloidal semiconductors to construct more efficient and stable heterogeneous photoelectrodes for solar fuel production.

Optical properties of wide gap semiconductors studied by means of cathodoluminescence

NASA Astrophysics Data System (ADS)

Fischer Ponce, Alec Mirco

III-nitride semiconductors have been found to be a suitable material for the fabrication of light-emitting diodes (LEDs) emitting in the visible and ultraviolet range through the use of indium gallium nitride (InGaN) active layers. Yet, achieving high-efficient and long lasting LEDs in the long wavelength range, especially in the green spectral region, is limited by difficulties of growth of InGaN layers with high indium content. Additionally, device efficiency is strongly dependent on the formation of low-resistive p-type gallium nitride (GaN)-based layers. In this dissertation, the optical properties of wide gap semiconductor are analyzed using cathodoluminescence imaging and spectroscopy, and time-resolved spectroscopic techniques. A transition at 3.2 eV in magnesium (Mg)-doped GaN has been revealed and it has been identified as a Mg-related donor-acceptor pair, which may be responsible for the increase in intensity with increasing magnesium concentration in the commonly observed donor-acceptor pair region. In a separate study, a decrease of the Mg acceptor energy level and the bulk resistivity in Mg-doped InGaN with increasing indium composition is observed, implying that InGaN p-layers should improve the device performance. Next, Mg-doped GaN and InGaN capping layers in LED structures grown under different ambient gases are shown to alter the quantum well (QW) luminescence. QWs grown with InGaN p-layers exhibit an improvement in the luminescence efficiency and a blue-shift due to reduction of the compressive misfit strain in the QWs. However, p-GaN layers grown under hydrogen ambient gas present a blue-shift of the QW emission. Hydrogen diffusion occurring after thermal annealing of the p-GaN layer may explain the reduction of piezoelectric field effects in polar InGaN quantum wells. In another study, InGaN QWs with high indium content grown in non-polar m-plane GaN were found to exhibit stacking faults originating at the first QW, relaxing the misfit strain in the subsequent layers. Finally, the optical and structural properties of highly luminescent zinc oxide (ZnO) tetrapod powders emitting in the visible green spectral range were studied with high spatial resolution. ZnO nanostructures are strong candidates for devices emitting light with very high efficiencies.

Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

NASA Astrophysics Data System (ADS)

Biyikli, Necmi; Haider, Ali

2017-09-01

In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

Method of passivating semiconductor surfaces

DOEpatents

Wanlass, M.W.

1990-06-19

A method is described for passivating Group III-V or II-VI semiconductor compound surfaces. The method includes selecting a passivating material having a lattice constant substantially mismatched to the lattice constant of the semiconductor compound. The passivating material is then grown as an ultrathin layer of passivating material on the surface of the Group III-V or II-VI semiconductor compound. The passivating material is grown to a thickness sufficient to maintain a coherent interface between the ultrathin passivating material and the semiconductor compound. In addition, a device formed from such method is also disclosed.

High resolution three-dimensional doping profiler

DOEpatents

Thundat, Thomas G.; Warmack, Robert J.

1999-01-01

A semiconductor doping profiler provides a Schottky contact at one surface and an ohmic contact at the other. While the two contacts are coupled to a power source, thereby establishing an electrical bias in the semiconductor, a localized light source illuminates the semiconductor to induce a photocurrent. The photocurrent changes in accordance with the doping characteristics of the semiconductor in the illuminated region. By changing the voltage of the power source the depth of the depletion layer can be varied to provide a three dimensional view of the local properties of the semiconductor.

Method of passivating semiconductor surfaces

DOEpatents

Wanlass, Mark W.

1990-01-01

A method of passivating Group III-V or II-VI semiconductor compound surfaces. The method includes selecting a passivating material having a lattice constant substantially mismatched to the lattice constant of the semiconductor compound. The passivating material is then grown as an ultrathin layer of passivating material on the surface of the Group III-V or II-VI semiconductor compound. The passivating material is grown to a thickness sufficient to maintain a coherent interface between the ultrathin passivating material and the semiconductor compound. In addition, a device formed from such method is also disclosed.

Phosphorus Doping Effect in a Zinc Oxide Channel Layer to Improve the Performance of Oxide Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Han, Dong-Suk; Moon, Yeon-Keon; Lee, Sih; Kim, Kyung-Taek; Moon, Dae-Yong; Lee, Sang-Ho; Kim, Woong-Sun; Park, Jong-Wan

2012-09-01

In this study, we fabricated phosphorus-doped zinc oxide-based thin-film transistors (TFTs) using direct current (DC) magnetron sputtering at a relatively low temperature of 100°C. To improve the TFT device performance, including field-effect mobility and bias stress stability, phosphorus dopants were employed to suppress the generation of intrinsic defects in the ZnO-based semiconductor. The positive and negative bias stress stabilities were dramatically improved by introducing the phosphorus dopants, which could prevent turn-on voltage ( V ON) shift in the TFTs caused by charge trapping within the active channel layer. The study showed that phosphorus doping in ZnO was an effective method to control the electrical properties of the active channel layers and improve the bias stress stability of oxide-based TFTs.

In situ growth of metal particles on 3D urchin-like WO3 nanostructures.

PubMed

Xi, Guangcheng; Ye, Jinhua; Ma, Qiang; Su, Ning; Bai, Hua; Wang, Chao

2012-04-18

Metal/semiconductor hybrid materials of various sizes and morphologies have many applications in areas such as catalysis and sensing. Various organic agents are necessary to stabilize metal nanoparticles during synthesis, which leads to a layer of organic compounds present at the interfaces between the metal particles and the semiconductor supports. Generally, high-temperature oxidative treatment is used to remove the organics, which can extensively change the size and morphology of the particles, in turn altering their activity. Here we report a facile method for direct growth of noble-metal particles on WO(3) through an in situ redox reaction between weakly reductive WO(2.72) and oxidative metal salts in aqueous solution. This synthetic strategy has the advantages that it takes place in one step and requires no foreign reducing agents, stabilizing agents, or pretreatment of the precursors, making it a practical method for the controlled synthesis of metal/semiconductor hybrid nanomaterials. This synthetic method may open up a new way to develop metal-nanoparticle-loaded semiconductor composites. © 2012 American Chemical Society

Photoresponse and photo-induced memory effect in the organic field-effect transistor based on AlOX nanoparticles at the interface of semiconductor/dielectric

NASA Astrophysics Data System (ADS)

Cheng, Yunfei; Wang, Wu

2017-10-01

In this work, the photoresponse and photo-induced memory effect were demonstrated in an organic field-effect transistor (OFET) with semiconductor pentacene and SiO2 as the active and gate dielectric layers, respectively. By inserting AlOX nanoparticles (NPs) at the interface of pentacene/SiO2, obvious enhancing photoresponse was obtained in the OFET with the maximum responsivity and photosensitivity of about 15 A/W and 100, respectively. Moreover, the stable photoinduced memory effect was achieved in the OFET, attributing to the photogenerated electrons captured by the interface traps of the AlOX NPs/SiO2.

Electric field induced spin-polarized current

DOEpatents

Murakami, Shuichi; Nagaosa, Naoto; Zhang, Shoucheng

2006-05-02

A device and a method for generating an electric-field-induced spin current are disclosed. A highly spin-polarized electric current is generated using a semiconductor structure and an applied electric field across the semiconductor structure. The semiconductor structure can be a hole-doped semiconductor having finite or zero bandgap or an undoped semiconductor of zero bandgap. In one embodiment, a device for injecting spin-polarized current into a current output terminal includes a semiconductor structure including first and second electrodes, along a first axis, receiving an applied electric field and a third electrode, along a direction perpendicular to the first axis, providing the spin-polarized current. The semiconductor structure includes a semiconductor material whose spin orbit coupling energy is greater than room temperature (300 Kelvin) times the Boltzmann constant. In one embodiment, the semiconductor structure is a hole-doped semiconductor structure, such as a p-type GaAs semiconductor layer.

Point Defects in Two-Dimensional Layered Semiconductors: Physics and Its Applications

NASA Astrophysics Data System (ADS)

Suh, Joonki

Recent advances in material science and semiconductor processing have been achieved largely based on in-depth understanding, efficient management and advanced application of point defects in host semiconductors, thus finding the relevant techniques such as doping and defect engineering as a traditional scientific and technological solution. Meanwhile, two- dimensional (2D) layered semiconductors currently draw tremendous attentions due to industrial needs and their rich physics at the nanoscale; as we approach the end of critical device dimensions in silicon-based technology, ultra-thin semiconductors have the potential as next- generation channel materials, and new physics also emerges at such reduced dimensions where confinement of electrons, phonons, and other quasi-particles is significant. It is therefore rewarding and interesting to understand and redefine the impact of lattice defects by investigating their interactions with energy/charge carriers of the host matter. Potentially, the established understanding will provide unprecedented opportunities for realizing new functionalities and enhancing the performance of energy harvesting and optoelectronic devices. In this thesis, multiple novel 2D layered semiconductors, such as bismuth and transition- metal chalcogenides, are explored. Following an introduction of conventional effects induced by point defects in semiconductors, the related physics of electronically active amphoteric defects is revisited in greater details. This can elucidate the complication of a two-dimensional electron gas coexisting with the topological states on the surface of bismuth chalcogenides, recently suggested as topological insulators. Therefore, native point defects are still one of the keys to understand and exploit topological insulators. In addition to from a fundamental science point of view, the effects of point defects on the integrated thermal-electrical transport, as well as the entropy-transporting process in thermoelectric materials are thoroughly investigated. Point defects can potentially beat the undesired coupling, often term "thermoelectric Bermuda triangle", among electrical conductivity, thermal conductivity and thermopower. The maximum thermoelectric performance is demonstrated with an intermediate density of defects when they beneficially and multi-functionally act as electron donors, as well as strongly energy-dependent electron and phonon scatterers. Therefore, this is a good example of how fundamental defect physics can be applied for practical devices toward renewable energy technology. Another interesting field of layered nanomaterials is on transition-metal dichalcogenides (TMDs), sensational candidates for 2D semiconductor physics and applications. At the reduced dimensionality of 2D where a far stronger correlation between point defects and charge carriers is expected, it is studied how chalcogen vacancies alter optical properties of monolayer TMDs. A new, sub-bandgap broad emission lines as well as increase in the overall photoluminescence intensity at low temperatures are reported as a result of high quantum efficiency of excitons, i.e., bound electron-hole pairs, localized at defect sites. On electrical transport, both n- and p-type materials are needed to form junctions and support bipolar carrier conduction while typically only one type of doping is stable for a particular TMD. For example, MoS2 is natively n-type, thus the lack of p-type doping hampers the development of charge-splitting p-n junctions of MoS2. To address this issue, we demonstrate stable p-type conduction in MoS2 by substitutional Nb doping up to the degenerate level. Proof-of-concept, van der Waals p-n homo-junctions based on vertically stacked MoS2 layers are also fabricated which enable gate-tuneable current rectification. Various electronic devices fabricated are stable in ambient air even without additional treatment such as capping layer protection, thanks to the substitutionality nature of the doping; this is in stark contrast to the existing approach of using molecular doping, which usually suffers from volatility and reactivity with air and/or water molecules.

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Producing Silicon Carbide for Semiconductor Devices

NASA Technical Reports Server (NTRS)

Hsu, G. C.; Rohatgi, N. K.

1986-01-01

Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

Inelastic tunnel diodes

NASA Technical Reports Server (NTRS)

Anderson, L. M. (Inventor)

1984-01-01

Power is extracted from plasmons, photons, or other guided electromagnetic waves at infrared to midultraviolet frequencies by inelastic tunneling in metal-insulator-semiconductor-metal diodes. Inelastic tunneling produces power by absorbing plasmons to pump electrons to higher potential. Specifically, an electron from a semiconductor layer absorbs a plasmon and simultaneously tunnels across an insulator into metal layer which is at higher potential. The diode voltage determines the fraction of energy extracted from the plasmons; any excess is lost to heat.

Stabilized CdSe-CoPi composite photoanode for light-assisted water oxidation by transformation of a CdSe/cobalt metal thin film.

PubMed

Costi, Ronny; Young, Elizabeth R; Bulović, Vladimir; Nocera, Daniel G

2013-04-10

Integration of water splitting catalysts with visible-light-absorbing semiconductors would enable direct solar-energy-to-fuel conversion schemes such as those based on water splitting. A disadvantage of some common semiconductors that possess desirable optical bandgaps is their chemical instability under the conditions needed for oxygen evolution reaction (OER). In this study, we demonstrate the dual benefits gained from using a cobalt metal thin-film as the precursor for the preparation of cobalt-phosphate (CoPi) OER catalyst on cadmium chalcogenide photoanodes. The cobalt layer protects the underlying semiconductor from oxidation and degradation while forming the catalyst and simultaneously facilitates the advantageous incorporation of the cadmium chalcogenide layer into the CoPi layer during continued processing of the electrode. The resulting hybrid material forms a stable photoactive anode for light-assisted water splitting.

Power module packaging with double sided planar interconnection and heat exchangers

DOEpatents

Liang, Zhenxian; Marlino, Laura D.; Ning, Puqi; Wang, Fei

2015-05-26

A double sided cooled power module package having a single phase leg topology includes two IGBT and two diode semiconductor dies. Each IGBT die is spaced apart from a diode semiconductor die, forming a switch unit. Two switch units are placed in a planar face-up and face-down configuration. A pair of DBC or other insulated metallic substrates is affixed to each side of the planar phase leg semiconductor dies to form a sandwich structure. Attachment layers are disposed on outer surfaces of the substrates and two heat exchangers are affixed to the substrates by rigid bond layers. The heat exchangers, made of copper or aluminum, have passages for carrying coolant. The power package is manufactured in a two-step assembly and heating process where direct bonds are formed for all bond layers by soldering, sintering, solid diffusion bonding or transient liquid diffusion bonding, with a specially designed jig and fixture.

Complexes of dipolar excitons in layered quasi-two-dimensional nanostructures

NASA Astrophysics Data System (ADS)

Bondarev, Igor V.; Vladimirova, Maria R.

2018-04-01

We discuss neutral and charged complexes (biexcitons and trions) formed by indirect excitons in layered quasi-two-dimensional semiconductor heterostructures. Indirect excitons—long-lived neutral Coulomb-bound pairs of electrons and holes of different layers—have been known for semiconductor coupled quantum wells and have recently been reported for van der Waals heterostructures such as double bilayer graphene and transition-metal dichalcogenides. Using the configuration space approach, we derive the analytical expressions for the trion and biexciton binding energies as a function of interlayer distance. The method captures essential kinematics of complex formation to reveal significant binding energies, up to a few tens of meV for typical interlayer distances ˜3 -5 Å , with the trion binding energy always being greater than that of the biexciton. Our results can contribute to the understanding of more complex many-body phenomena such as exciton Bose-Einstein condensation and Wigner-like electron-hole crystallization in layered semiconductor heterostructures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Zhemin; Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552; Taguchi, Dai

The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial chargingmore » in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.« less

Connecting Interface Structure to Energy Level Alignment at Aqueous Semiconductor Interfaces

NASA Astrophysics Data System (ADS)

Hybertsen, Mark

Understanding structure-function relationships at aqueous semiconductor interfaces presents fundamental challenges, including the discovery of the key interface structure motifs themselves. Important examples include the alignment of electrochemical redox levels with the semiconductor band edges and the identification of catalytic active sites. We have developed a multistep approach, initially demonstrated for GaN, ZnO and their alloys, motivated by measured high efficiency for photocatalytic water oxidation. The interface structure is simulated using ab initio molecular dynamics (AIMD). The calculated, average interface dipole is combined with the GW approach from many-body perturbation theory to calculate the energy level alignment between the semiconductor band edges and the centroid of the occupied 1b1 energy level of water and thus, the electrochemical levels. Cluster models are used to study reaction pathways. The emergent interface motif is the full (GaN) or partial (ZnO) dissociated interface water layer. Here I will focus on the aqueous interfaces to the stable TiO2 anatase (101) and rutile (110) facets. The AIMD calculations reveal interface water dissociation and reassociation processes through distinct pathways: one direct at the interface and the other via a spectator water molecule from the hydration layer. Comparisons between the two interfaces shows that the energy landscape for these pathways depends on the local hydrogen bonding patterns and the interplay with the interface template. Combined results from different initial conditions and AIMD temperatures demonstrate a partially dissociated interface water layer in both cases. Specifically for rutile, structure and the GW-based analysis of the interface energy level alignment agree with experiment. Finally, hole localization at different interface structure motifs will be discussed. Work performed in collaboration with J. Lyons, N. Kharche, M. Ertem and J. Muckerman, done in part at the CFN, which is a U.S. DOE Office of Science Facility, at BNL under Contract No. DE-SC0012704 and with resources from NERSC under Contract No. DE-AC02-05CH11231.

Strain-compensated infrared photodetector and photodetector array

DOEpatents

Kim, Jin K; Hawkins, Samuel D; Klem, John F; Cich, Michael J

2013-05-28

A photodetector is disclosed for the detection of infrared light with a long cutoff wavelength in the range of about 4.5-10 microns. The photodetector, which can be formed on a semiconductor substrate as an nBn device, has a light absorbing region which includes InAsSb light-absorbing layers and tensile-strained layers interspersed between the InAsSb light-absorbing layers. The tensile-strained layers can be formed from GaAs, InAs, InGaAs or a combination of these III-V compound semiconductor materials. A barrier layer in the photodetector can be formed from AlAsSb or AlGaAsSb; and a contact layer in the photodetector can be formed from InAs, GaSb or InAsSb. The photodetector is useful as an individual device, or to form a focal plane array.

Subnanosecond Scintillation Detector

NASA Technical Reports Server (NTRS)

Hoenk, Michael (Inventor); Hennessy, John (Inventor); Hitlin, David (Inventor)

2017-01-01

A scintillation detector, including a scintillator that emits scintillation; a semiconductor photodetector having a surface area for receiving the scintillation, wherein the surface area has a passivation layer configured to provide a peak quantum efficiency greater than 40% for a first component of the scintillation, and the semiconductor photodetector has built in gain through avalanche multiplication; a coating on the surface area, wherein the coating acts as a bandpass filter that transmits light within a range of wavelengths corresponding to the first component of the scintillation and suppresses transmission of light with wavelengths outside said range of wavelengths; and wherein the surface area, the passivation layer, and the coating are controlled to increase the temporal resolution of the semiconductor photodetector.

Laser ablation mechanism of transparent layers on semiconductors with ultrashort laser pulses

NASA Astrophysics Data System (ADS)

Rublack, Tino; Hartnauer, Stefan; Mergner, Michael; Muchow, Markus; Seifert, Gerhard

2011-12-01

Transparent dielectric layers on semiconductors are used as anti-reflection coatings both for photovoltaic applications and for mid-infrared optical elements. We have shown recently that selective ablation of such layers is possible using ultrashort laser pulses at wavelengths being absorbed by the semiconductor. To get a deeper understanding of the ablation mechanism, we have done ablation experiments for different transparent materials, in particular SiO2 and SixNy on silicon, using a broad range of wavelengths ranging from UV to IR, and pulse durations between 50 and 2000 fs. The characterization of the ablated regions was done by light microscopy and atomic force microscopy (AFM). Utilizing laser wavelengths above the silicon band gap, selective ablation of the dielectric layer without noticeable damage of the opened silicon surface is possible. In contrast, ultrashort pulses (1-2 ps) at mid-infrared wavelengths already cause damage in the silicon at lower intensities than in the dielectric layer, even when a vibrational resonance (e.g. at λ = 9.26 μm for SiO2) is addressed. The physical processes behind this, on the first glance counterintuitive, observation will be discussed.

The analytical approach to optimization of active region structure of quantum dot laser

NASA Astrophysics Data System (ADS)

Korenev, V. V.; Savelyev, A. V.; Zhukov, A. E.; Omelchenko, A. V.; Maximov, M. V.

2014-10-01

Using the analytical approach introduced in our previous papers we analyse the possibilities of optimization of size and structure of active region of semiconductor quantum dot lasers emitting via ground-state optical transitions. It is shown that there are optimal length' dispersion and number of QD layers in laser active region which allow one to obtain lasing spectrum of a given width at minimum injection current. Laser efficiency corresponding to the injection current optimized by the cavity length is practically equal to its maximum value.

Optoelectronics of supported and suspended 2D semiconductors

NASA Astrophysics Data System (ADS)

Bolotin, Kirill

2014-03-01

Two-dimensional semiconductors, materials such monolayer molybdenum disulfide (MoS2) are characterized by strong spin-orbit and electron-electron interactions. However, both electronic and optoelectronic properties of these materials are dominated by disorder-related scattering. In this talk, we investigate approaches to reduce scattering and explore physical phenomena arising in intrinsic 2D semiconductors. First, we discuss fabrication of pristine suspended monolayer MoS2 and use photocurrent spectroscopy measurements to study excitons in this material. We observe band-edge and van Hove singularity excitons and estimate their binding energies. Furthermore, we study dissociation of these excitons and uncover the mechanism of their contribution to photoresponse of MoS2. Second, we study strain-induced modification of bandstructures of 2D semiconductors. With increasing strain, we find large and controllable band gap reduction of both single- and bi-layer MoS2. We also detect experimental signatures consistent with strain-induced transition from direct to indirect band gap in monolayer MoS2. Finally, we fabricate heterostructures of dissimilar 2D semiconductors and study their photoresponse. For closely spaced 2D semiconductors we detect charge transfer, while for separation larger than 10nm we observe Forster-like energy transfer between excitations in different layers.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Veselov, D. A., E-mail: dmitriy90@list.ru; Shashkin, I. S.; Bakhvalov, K. V.

Semiconductor lasers based on MOCVD-grown AlGaInAs/InP separate-confinement heterostructures are studied. It is shown that raising only the energy-gap width of AlGaInAs-waveguides without the introduction of additional barriers results in more pronounced current leakage into the cladding layers. It is found that the introduction of additional barrier layers at the waveguide–cladding-layer interface blocks current leakage into the cladding layers, but results in an increase in the internal optical loss with increasing pump current. It is experimentally demonstrated that the introduction of blocking layers makes it possible to obtain maximum values of the internal quantum efficiency of stimulated emission (92%) and continuouswavemore » output optical power (3.2 W) in semiconductor lasers in the eye-safe wavelength range (1400–1600 nm).« less

Photo-Spectrometer Realized In A Standard Cmos Ic Process

DOEpatents

Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

1999-10-12

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Hetero-junction photovoltaic device and method of fabricating the device

DOEpatents

Aytug, Tolga; Christen, David K; Paranthaman, Mariappan Parans; Polat, Ozgur

2014-02-10

A hetero-junction device and fabrication method in which phase-separated n-type and p-type semiconductor pillars define vertically-oriented p-n junctions extending above a substrate. Semiconductor materials are selected for the p-type and n-type pillars that are thermodynamically stable and substantially insoluble in one another. An epitaxial deposition process is employed to form the pillars on a nucleation layer and the mutual insolubility drives phase separation of the materials. During the epitaxial deposition process, the orientation is such that the nucleation layer initiates propagation of vertical columns resulting in a substantially ordered, three-dimensional structure throughout the deposited material. An oxidation state of at least a portion of one of the p-type or the n-type semiconductor materials is altered relative to the other, such that the band-gap energy of the semiconductor materials differ with respect to stoichiometric compositions and the device preferentially absorbs particular selected bands of radiation.

Chitin Liquid-Crystal-Templated Oxide Semiconductor Aerogels.

PubMed

Chau, Trang The Lieu; Le, Dung Quang Tien; Le, Hoa Thi; Nguyen, Cuong Duc; Nguyen, Long Viet; Nguyen, Thanh-Dinh

2017-09-13

Chitin nanocrystals have been used as a liquid crystalline template to fabricate layered oxide semiconductor aerogels. Anisotropic chitin liquid crystals are transformed to sponge-like aerogels by hydrothermally cross-linked gelation and lyophilization-induced solidification. The hydrothermal gelation of chitin aqueous suspensions then proceeds with peroxotitanate to form hydrogel composites that recover to form aerogels after freeze-drying. The homogeneous peroxotitanate/chitin composites are calcined to generate freestanding titania aerogels that exhibit the nanostructural integrity of layered chitin template. Our extended investigations show that coassembling chitin nanocrystals with other metal-based precursors also yielded semiconductor aerogels of perovskite BaTiO 3 and CuO x nanocrystals. The potential of these materials is great to investigate these chitin sponges for biomedicine and these semiconductor aerogels for photocatalysis, gas sensing, and other applications. Our results present a new aerogel templating method of highly porous, ultralight materials with chitin liquid crystals.

Transparent Oxide Thin-Film Transistors: Production, Characterization and Integration

NASA Astrophysics Data System (ADS)

Barquinha, Pedro Miguel Candido

This dissertation is devoted to the study of the emerging area of transparent electronics, summarizing research work regarding the development of n-type thin-film transistors (TFTs) based on sputtered oxide semiconductors. All the materials are produced without intentional substrate heating, with annealing temperatures of only 150-200 °C being used to optimize transistor performance. The work is based on the study and optimization of active semiconductors from the gallium-indium-zinc oxide system, including both the binary compounds Ga2O3, In2O3 and ZnO, as well as ternary and quaternary oxides based on mixtures of those, such as IZO and GIZO with different atomic ratios. Several topics are explored, including the study and optimization of the oxide semiconductor thin films, their application as channel layers on TFTs and finally the implementation of the optimized processes to fabricate active matrix backplanes to be integrated in liquid crystal display (LCD) prototypes. Sputtered amorphous dielectrics with high dielectric constant (high-kappa) based on mixtures of tantalum-silicon or tantalum-aluminum oxides are also studied and used as the dielectric layers on fully transparent TFTs. These devices also include transparent and highly conducting IZO thin films as source, drain and gate electrodes. Given the flexibility of the sputtering technique, oxide semiconductors are analyzed regarding several deposition parameters, such as oxygen partial pressure and deposition pressure, as well as target composition. One of the most interesting features of multicomponent oxides such as IZO and GIZO is that, due to their unique electronic configuration and carrier transport mechanism, they allow to obtain amorphous structures with remarkable electrical properties, such as high hall-effect mobility that exceeds 60 cm2 V -1 s-1 for IZO. These properties can be easily tuned by changing the processing conditions and the atomic ratios of the multicomponent oxides, allowing to have amorphous oxides suitable to be used either as transparent semiconductors or as highly conducting electrodes. The amorphous structure, which is maintained even if the thin films are annealed at 500 °C, brings great advantages concerning interface quality and uniformity in large areas. A complete study comprising different deposition conditions of the semiconductor layer is also made regarding TFT electrical performance. Optimized devices present outstanding electrical performance, such as field-effect mobility (muFE) exceeding 20 cm2 V -1 s-1, turn-on voltage (Von) between -1 and 1 V, subthreshold slope (S) lower than 0.25 V dec-1 and On-Off ratio above 107 . Devices employing amorphous multicomponent oxides present largely improved properties when compared with the ones based on polycrystalline ZnO, mostly in terms of muFE. Within the compositional range where IZO and GIZO films are amorphous, TFT performance can be largely adjusted: for instance, high indium contents favor large mu FE but also highly negative Von, which can be compensated by proper amounts of zinc and gallium. Large oxygen concentrations during oxide semiconductor sputtering are found to be deleterious, decreasing muFE, shifting Von towards high values and turning the devices electrically unstable. It is also shown that semiconductor thickness (ds) has a very important role: for instance, by reducing ds to 10 nm it is possible to produce TFTs with Von≈0 V even using deposition conditions and/or target compositions that normally yield highly conducting films. Given the low ds of the films, this behavior is mostly related with surface states existent at the oxide semiconductor air-exposed back-surface, where depletion layers that can extend towards the dielectric/semiconductor interface are created due to the interaction with atmospheric oxygen. Different passivation layers on top of this air-exposed surface are studied, with SU-8 revealing to be to most effective one. Other important topics are source-drain contact resistance assessment and the effect of different annealing temperatures ( TA), being the properties of the TFTs dominated by TA rather than by the deposition conditions as TA increases. Fully transparent TFTs employing sputtered amorphous multicomponent dielectrics produced without intentional substrate heating present excellent electrical properties, that approach those exhibited by devices using PECVD SiO2 produced at 400 °C. Gate leakage current can be greatly reduced by using tantalum-silicon or tantalum-aluminum oxides rather than Ta2O5. A section of this dissertation is also devoted to the analysis of current stress stability and aging effects of the TFTs, being found that optimal devices exhibit recoverable threshold voltage shifts lower than 0.50 V after 24 h stress with constant drain current of 10 muA, as well as negligible aging effects during 18 months. The research work of this dissertation culminates in the fabrication of a backplane employing transparent TFTs and subsequent integration with a LCD frontplane by Hewlett-Packard. The successful operation of this initial 2.8h prototype with 128x128 pixels provides a solid demonstration that oxide semiconductor-based TFTs have the potential to largely contribute to a novel electronics era, where semiconductor materials away from conventional silicon are used to create fascinating applications, such as transparent electronic products.

Two-dimensional transition metal dichalcogenides as atomically thin semiconductors: opportunities and challenges.

PubMed

Duan, Xidong; Wang, Chen; Pan, Anlian; Yu, Ruqin; Duan, Xiangfeng

2015-12-21

The discovery of graphene has ignited intensive interest in two-dimensional layered materials (2DLMs). These 2DLMs represent a new class of nearly ideal 2D material systems for exploring fundamental chemistry and physics at the limit of single-atom thickness, and have the potential to open up totally new technological opportunities beyond the reach of existing materials. In general, there are a wide range of 2DLMs in which the atomic layers are weakly bonded together by van der Waals interactions and can be isolated into single or few-layer nanosheets. The van der Waals interactions between neighboring atomic layers could allow much more flexible integration of distinct materials to nearly arbitrarily combine and control different properties at the atomic scale. The transition metal dichalcogenides (TMDs) (e.g., MoS2, WSe2) represent a large family of layered materials, many of which exhibit tunable band gaps that can undergo a transition from an indirect band gap in bulk crystals to a direct band gap in monolayer nanosheets. These 2D-TMDs have thus emerged as an exciting class of atomically thin semiconductors for a new generation of electronic and optoelectronic devices. Recent studies have shown exciting potential of these atomically thin semiconductors, including the demonstration of atomically thin transistors, a new design of vertical transistors, as well as new types of optoelectronic devices such as tunable photovoltaic devices and light emitting devices. In parallel, there have also been considerable efforts in developing diverse synthetic approaches for the rational growth of various forms of 2D materials with precisely controlled chemical composition, physical dimension, and heterostructure interface. Here we review the recent efforts, progress, opportunities and challenges in exploring the layered TMDs as a new class of atomically thin semiconductors.

Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

NASA Astrophysics Data System (ADS)

Sheng, Jiazhen; Han, Ki-Lim; Hong, TaeHyun; Choi, Wan-Ho; Park, Jin-Seong

2018-01-01

The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors (TFTs), fabricating with atomic layer deposition (ALD) processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types (directions). The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields. Project supported by the National Research Foundation of Korea (NRF) (No. NRF-2017R1D1A1B03034035), the Ministry of Trade, Industry & Energy (No. #10051403), and the Korea Semiconductor Research Consortium.

Twisted bilayer blue phosphorene: A direct band gap semiconductor

NASA Astrophysics Data System (ADS)

Ospina, D. A.; Duque, C. A.; Correa, J. D.; Suárez Morell, Eric

2016-09-01

We report that two rotated layers of blue phosphorene behave as a direct band gap semiconductor. The optical spectrum shows absorption peaks in the visible region of the spectrum and in addition the energy of these peaks can be tuned with the rotational angle. These findings makes twisted bilayer blue phosphorene a strong candidate as a solar cell or photodetection device. Our results are based on ab initio calculations of several rotated blue phosphorene layers.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, Arthur W.; Ellingboe, Albert R.

1998-01-01

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18-0.35 mm or less.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, A.W.; Ellingboe, A.R.

1998-10-20

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18--0.35 mm or less. 16 figs.

High performance thin film transistor with ZnO channel layer deposited by DC magnetron sputtering.

PubMed

Moon, Yeon-Keon; Moon, Dae-Yong; Lee, Sang-Ho; Jeong, Chang-Oh; Park, Jong-Wan

2008-09-01

Research in large area electronics, especially for low-temperature plastic substrates, focuses commonly on limitations of the semiconductor in thin film transistors (TFTs), in particular its low mobility. ZnO is an emerging example of a semiconductor material for TFTs that can have high mobility, while a-Si and organic semiconductors have low mobility (<1 cm2/Vs). ZnO-based TFTs have achieved high mobility, along with low-voltage operation low off-state current, and low gate leakage current. In general, ZnO thin films for the channel layer of TFTs are deposited with RF magnetron sputtering methods. On the other hand, we studied ZnO thin films deposited with DC magnetron sputtering for the channel layer of TFTs. After analyzing the basic physical and chemical properties of ZnO thin films, we fabricated a TFT-unit cell using ZnO thin films for the channel layer. The field effect mobility (micro(sat)) of 1.8 cm2/Vs and threshold voltage (Vth) of -0.7 V were obtained.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

PubMed Central

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-01-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters. PMID:26842997

Photoactivated and patternable charge transport materials and their use in organic light-emitting devices

NASA Astrophysics Data System (ADS)

Liu, Jie; Lewis, Larry N.; Duggal, Anil R.

2007-06-01

Organic light-emitting devices (OLEDs) usually employ at least one organic semiconductor layer that acts as a hole-injection material. The prototypical example is a conjugated polymer such as poly(3,4-ethylenedioxythiophene) heavily p doped with polystyrene sulfonic acid. Here, the authors describe a chemical doping strategy for hole injection material formulation that enables spatial patterning of the material conductivity through optical activation. The strategy utilizes an organic photoacid generator (PAG) dispersed in a polymeric organic semiconductor host. Upon UV irradiation, the PAG decomposes and generates a strong protonic acid that subsequently p dopes the host. The authors demonstrate an OLED made with such a light-activated hole-injection material and show that arbitrary emission patterning can be accomplished. This approach may provide a simple, low cost path toward specialty lighting and signage applications for OLED technology.

Modeling electrochemical deposition inside nanotubes to obtain metal-semiconductor multiscale nanocables or conical nanopores.

PubMed

Lebedev, Konstantin; Mafé, Salvador; Stroeve, Pieter

2005-08-04

Nanocables with a radial metal-semiconductor heterostructure have recently been prepared by electrochemical deposition inside metal nanotubes. First, a bare nanoporous polycarbonate track-etched membrane is coated uniformly with a metal film by electroless deposition. The film forms a working electrode for further deposition of a semiconductor layer that grows radially inside the nanopore when the deposition rate is slow. We propose a new physical model for the nanocable synthesis and study the effects of the deposited species concentration, potential-dependent reaction rate, and nanopore dimensions on the electrochemical deposition. The problem involves both axial diffusion through the nanopore and radial transport to the nanopore surface, with a surface reaction rate that depends on the axial position and the time. This is so because the radial potential drop across the deposited semiconductor layer changes with the layer thickness through the nanopore. Since axially uniform nanocables are needed for most applications, we consider the relative role of reaction and axial diffusion rates on the deposition process. However, in those cases where partial, empty-core deposition should be desirable (e.g., for producing conical nanopores to be used in single nanoparticle detection), we give conditions where asymmetric geometries can be experimentally realized.

Multi-layer MOS capacitor based polarization insensitive electro-optic intensity modulator.

PubMed

Qiu, Xiaoming; Ruan, Xiaoke; Li, Yanping; Zhang, Fan

2018-05-28

In this study, a multi-layer metal-oxide-semiconductor capacitor (MLMOSC) polarization insensitive modulator is proposed. The design is validated by numerical simulation with commercial software LUMERICAL SOLUTION. Based on the epsilon-near-zero (ENZ) effect of indium tin oxide (ITO), the device manages to uniformly modulate both the transverse electric (TE) and the transverse magnetic (TM) modes. With a 20μm-long double-layer metal-oxide-semiconductor capacitor (DLMOSC) polarization insensitive modulator, in which two metal-oxide-semiconductor (MOS) structures are formed by the n-doped Si/HfO 2 /ITO/HfO 2 / n-doped Si stack, the extinction ratios (ERs) of both the TE and the TM modes can be over 20dB. The polarization dependent losses of the device can be as low as 0.05dB for the "OFF" state and 0.004dB for the "ON" state. Within 1dB polarization dependent loss, the device can operate with over 20dB ERs at the S, C, and L bands. The polarization insensitive modulator offers various merits including ultra-compact size, broadband spectrum, and complementary metal oxide semiconductor (CMOS) compatibility.

Effect of temperature on terahertz photonic and omnidirectional band gaps in one-dimensional quasi-periodic photonic crystals composed of semiconductor InSb.

PubMed

Singh, Bipin K; Pandey, Praveen C

2016-07-20

Engineering of thermally tunable terahertz photonic and omnidirectional bandgaps has been demonstrated theoretically in one-dimensional quasi-periodic photonic crystals (PCs) containing semiconductor and dielectric materials. The considered quasi-periodic structures are taken in the form of Fibonacci, Thue-Morse, and double periodic sequences. We have shown that the photonic and omnidirectional bandgaps in the quasi-periodic structures with semiconductor constituents are strongly depend on the temperature, thickness of the constituted semiconductor and dielectric material layers, and generations of the quasi-periodic sequences. It has been found that the number of photonic bandgaps increases with layer thickness and generation of the quasi-periodic sequences. Omnidirectional bandgaps in the structures have also been obtained. Results show that the bandwidths of photonic and omnidirectional bandgaps are tunable by changing the temperature and lattice parameters of the structures. The generation of quasi-periodic sequences can also change the properties of photonic and omnidirectional bandgaps remarkably. The frequency range of the photonic and omnidirectional bandgaps can be tuned by the change of temperature and layer thickness of the considered quasi-periodic structures. This work will be useful to design tunable terahertz PC devices.

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, deceased, Roger J.; Dawson, Ralph; Fritz, Ian J.; Osbourn, Gordon C.; Zipperian, Thomas E.

1989-01-01

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space which includes a lowest energy .GAMMA.-valley and a next lowest energy L-valley, each k-vector corresponding to one of the orthogonal directions defined by the planes of said layers and the directions perpendicular thereto. The layer thicknesses of the quantum well layers are selected to provide a superlattice L.sub.2D -valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley.

Method for manufacturing electrical contacts for a thin-film semiconductor device

DOEpatents

Carlson, David E.; Dickson, Charles R.; D'Aiello, Robert V.

1988-11-08

A method of fabricating spaced-apart back contacts on a thin film of semiconductor material by forming strips of buffer material on top of the semiconductor material in locations corresponding to the desired dividing lines between back contacts, forming a film of metal substantially covering the semiconductor material and buffer strips, and scribing portions of the metal film overlying the buffer strips with a laser without contacting the underlying semiconductor material to separate the metal layer into a plurality of back contacts. The buffer material serves to protect the underlying semiconductor material from being damaged during the laser scribing. Back contacts and multi-cell photovoltaic modules incorporating such back contacts also are disclosed.

Electrical contacts for a thin-film semiconductor device

DOEpatents

Carlson, David E.; Dickson, Charles R.; D'Aiello, Robert V.

1989-08-08

A method of fabricating spaced-apart back contacts on a thin film of semiconductor material by forming strips of buffer material on top of the semiconductor material in locations corresponding to the desired dividing lines between back contacts, forming a film of metal substantially covering the semiconductor material and buffer strips, and scribing portions of the metal film overlying the buffer strips with a laser without contacting the underlying semiconductor material to separate the metal layer into a plurality of back contacts. The buffer material serves to protect the underlying semiconductor material from being damaged during the laser scribing. Back contacts and multi-cell photovoltaic modules incorporating such back contacts also are disclosed.

Electro-optical SLS devices for operating at new wavelength ranges

DOEpatents

Osbourn, Gordon C.

1986-01-01

An intrinsic semiconductor electro-optical device includes a p-n junction intrinsically responsive, when cooled, to electromagnetic radiation in the wavelength range of 8-12 um. The junction consists of a strained-layer superlattice of alternating layers of two different III-V semiconductors having mismatched lattice constants when in bulk form. A first set of layers is either InAs.sub.1-x Sb.sub.x (where x is aobut 0.5 to 0.7) or In.sub.1-x Ga.sub.x As.sub.1-y Sb.sub.y (where x and y are chosen such that the bulk bandgap of the resulting layer is about the same as the minimum bandgap in the In.sub.1-x Ga.sub.x As.sub.1-y Sb.sub.y family). The second set of layers has a lattice constant larger than the lattice constant of the layers in the first set.

Charge-density study on layered oxyarsenides (LaO)MAs (M = Mn, Fe, Ni, Zn)

NASA Astrophysics Data System (ADS)

Takase, Kouichi; Hiramoto, Shozo; Fukushima, Tetsuya; Sato, Kazunori; Moriyoshi, Chikako; Kuroiwa, Yoshihiro

2017-12-01

Using synchrotron X-ray powder diffraction, we investigate the charge-density distributions of the layered oxypnictides (LaO)MnAs, (LaO)FeAs, (LaO)NiAs, and (LaO)ZnAs, which are an antiferromagnetic semiconductor, a parent material of an iron-based superconductor, a low-temperature superconductor, and a non-magnetic semiconductor, respectively. For the metallic samples, clear charge densities are observed in both the transition-metal pnictide layers and the rare-earth-oxide layers. However, in the semiconducting samples, there is no finite charge density between the transition-metal element and As. These differences in charge density reflect differences in physical properties. First-principles calculations using density functional theory reproduce the experimental results reasonably well.

Towards efficient and cost-effective inverted hybrid organic solar cells using inorganic semiconductor in the active layer

NASA Astrophysics Data System (ADS)

Imran, M.; Ikram, M.; Dilpazir, S.; Nafees, M.; Ali, S.; Geng, J.

2017-11-01

The article investigates the effects of NiO (p-type) and TiO2 (n-type) nanoparticles (NPs) on the performance of poly(3-hexylthiophene) (P3HT) and (phenyl-C61-butyric acid methylester) (PCBM) based devices with an inverse geometry. Various weight ratios of these nanoparticles were mixed in the polymer solution using 1,2-dichlorobenzene as solvent. An optimal amount of NPs-doped active layer exhibited higher power conversion efficiency (PCE) of 3.85% as compared to the reference cell, which exhibited an efficiency of 3.40% under white light illumination intensity of 100 mW/cm2. Enhanced PCE originates from increased film roughness and light harvesting due to increased absorption range upon mixing an optimal amount of NPs in the organic-based active layer. Further addition of NiO and TiO2 concentration relative to PCBM resulted in significant agglomeration of nanoparticles leading to degraded device parameters.

Stable surface passivation process for compound semiconductors

DOEpatents

Ashby, Carol I. H.

2001-01-01

A passivation process for a previously sulfided, selenided or tellurated III-V compound semiconductor surface. The concentration of undesired mid-gap surface states on a compound semiconductor surface is reduced by the formation of a near-monolayer of metal-(sulfur and/or selenium and/or tellurium)-semiconductor that is effective for long term passivation of the underlying semiconductor surface. Starting with the III-V compound semiconductor surface, any oxidation present thereon is substantially removed and the surface is then treated with sulfur, selenium or tellurium to form a near-monolayer of chalcogen-semiconductor of the surface in an oxygen-free atmosphere. This chalcogenated surface is then contacted with a solution of a metal that will form a low solubility chalcogenide to form a near-monolayer of metal-chalcogen-semiconductor. The resulting passivating layer provides long term protection for the underlying surface at or above the level achieved by a freshly chalcogenated compound semiconductor surface in an oxygen free atmosphere.

Progress towards a semiconductor Compton camera for prompt gamma imaging during proton beam therapy for range and dose verification

NASA Astrophysics Data System (ADS)

Gutierrez, A.; Baker, C.; Boston, H.; Chung, S.; Judson, D. S.; Kacperek, A.; Le Crom, B.; Moss, R.; Royle, G.; Speller, R.; Boston, A. J.

2018-01-01

The main objective of this work is to test a new semiconductor Compton camera for prompt gamma imaging. Our device is composed of three active layers: a Si(Li) detector as a scatterer and two high purity Germanium detectors as absorbers of high-energy gamma rays. We performed Monte Carlo simulations using the Geant4 toolkit to characterise the expected gamma field during proton beam therapy and have made experimental measurements of the gamma spectrum with a 60 MeV passive scattering beam irradiating a phantom. In this proceeding, we describe the status of the Compton camera and present the first preliminary measurements with radioactive sources and their corresponding reconstructed images.

Megavoltage imaging with a photoconductor based sensor

DOEpatents

Partain, Larry Dean [Los Altos, CA; Zentai, George [Mountain View, CA

2011-02-08

A photodetector for detecting megavoltage (MV) radiation comprises a semiconductor conversion layer having a first surface and a second surface disposed opposite the first surface, a first electrode coupled to the first surface, a second electrode coupled to the second surface, and a low density substrate including a detector array coupled to the second electrode opposite the semiconductor conversion layer. The photodetector includes a sufficient thickness of a high density material to create a sufficient number of photoelectrons from incident MV radiation, so that the photoelectrons can be received by the conversion layer and converted to a sufficient of recharge carriers for detection by the detector array.

Advancing semiconductor-electrocatalyst systems: application of surface transformation films and nanosphere lithography.

PubMed

Brinkert, Katharina; Richter, Matthias H; Akay, Ömer; Giersig, Michael; Fountaine, Katherine T; Lewerenz, Hans-Joachim

2018-05-24

Photoelectrochemical (PEC) cells offer the possibility of carbon-neutral solar fuel production through artificial photosynthesis. The pursued design involves technologically advanced III-V semiconductor absorbers coupled via an interfacial film to an electrocatalyst layer. These systems have been prepared by in situ surface transformations in electrochemical environments. High activity nanostructured electrocatalysts are required for an efficiently operating cell, optimized in their optical and electrical properties. We demonstrate that shadow nanosphere lithography (SNL) is an auspicious tool to systematically create three-dimensional electrocatalyst nanostructures on the semiconductor photoelectrode through controlling their morphology and optical properties. First results are demonstrated by means of the photoelectrochemical production of hydrogen on p-type InP photocathodes where hitherto applied photoelectrodeposition and SNL-deposited Rh electrocatalysts are compared based on their J-V and spectroscopic behavior. We show that smaller polystyrene particle masks achieve higher defect nanostructures of rhodium on the photoelectrode which leads to a higher catalytic activity and larger short circuit currents. Structural analyses including HRSEM and the analysis of the photoelectrode surface composition by using photoelectron spectroscopy support and complement the photoelectrochemical observations. The optical performance is further compared to theoretical models of the nanostructured photoelectrodes on light scattering and propagation.

Photon extraction from nitride ultraviolet light-emitting devices

DOEpatents

Schowalter, Leo J; Chen, Jianfeng; Grandusky, James R

2015-02-24

In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.

Single-layer group IV-V and group V-IV-III-VI semiconductors: Structural stability, electronic structures, optical properties, and photocatalysis

NASA Astrophysics Data System (ADS)

Lin, Jia-He; Zhang, Hong; Cheng, Xin-Lu; Miyamoto, Yoshiyuki

2017-07-01

Recently, single-layer group III monochalcogenides have attracted both theoretical and experimental interest at their potential applications in photonic devices, electronic devices, and solar energy conversion. Excited by this, we theoretically design two kinds of highly stable single-layer group IV-V (IV =Si ,Ge , and Sn; V =N and P) and group V-IV-III-VI (IV =Si ,Ge , and Sn; V =N and P; III =Al ,Ga , and In; VI =O and S) compounds with the same structures with single-layer group III monochalcogenides via first-principles simulations. By using accurate hybrid functional and quasiparticle methods, we show the single-layer group IV-V and group V-IV-III-VI are indirect bandgap semiconductors with their bandgaps and band edge positions conforming to the criteria of photocatalysts for water splitting. By applying a biaxial strain on single-layer group IV-V, single-layer group IV nitrides show a potential on mechanical sensors due to their bandgaps showing an almost linear response for strain. Furthermore, our calculations show that both single-layer group IV-V and group V-IV-III-VI have absorption from the visible light region to far-ultraviolet region, especially for single-layer SiN-AlO and SnN-InO, which have strong absorption in the visible light region, resulting in excellent potential for solar energy conversion and visible light photocatalytic water splitting. Our research provides valuable insight for finding more potential functional two-dimensional semiconductors applied in optoelectronics, solar energy conversion, and photocatalytic water splitting.

Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-12-09

Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.

Outline and comparison of the possible effects present in a metal-thin-film-insulator-semiconductor solar cell

NASA Technical Reports Server (NTRS)

Fonash, S. J.

1976-01-01

The advantages possible with the insertion of a thin-film insulating or semi-insulating layer between a metal and a semiconductor to form the MIS photovoltaic device have been presented previously in the literature. This MIS configuration may be considered as a specific example of a more general class of photovoltaic devices: electrode-thin-film-insulator-semiconductor devices. Since the advantages of the configuration were pointed out, there has been considerable experimental interest in these photovoltaic devices. Because the previous analysis showed that the introduction of the insulator layer could produce several different but advantageous effects, this paper presents a further outline giving a comparison of these effects together with their ramifications.

Intermediate type excitons in Schottky barriers of A3B6 layer semiconductors and UV photodetectors

NASA Astrophysics Data System (ADS)

Alekperov, O. Z.; Guseinov, N. M.; Nadjafov, A. I.

2006-09-01

Photoelectric and photovoltaic spectra of Schottky barrier (SB) structures of InSe, GaSe and GaS layered semiconductors (LS) are investigated at quantum energies from the band edge excitons of corresponding materials up to 6.5eV. Spectral dependences of photoconductivity (PC) of photo resistors and barrier structures are strongly different at the quantum energies corresponding to the intermediate type excitons (ITE) observed in these semiconductors. It was suggested that high UV photoconductivity of A3B6 LS is due to existence of high mobility light carriers in the depth of the band structure. It is shown that SB of semitransparent Au-InSe is high sensitive photo detector in UV region of spectra.

Donor impurity incorporation during layer growth of Zn II-VI semiconductors

NASA Astrophysics Data System (ADS)

Barlow, D. A.

2017-12-01

The maximum halogen donor concentration in Zn II-VI semiconductors during layer growth is studied using a standard model from statistical mechanics. Here the driving force for incorporation is an increase in entropy upon mixing of the donor impurity into the available anion lattice sites in the host binary. A formation energy opposes this increase and thus equilibrium is attained at some maximum concentration. Considering the halogen donor impurities within the Zn II-VI binary semiconductors ZnO, ZnS, ZnSe and ZnTe, a heat of reaction obtained from reported diatomic bond strengths is shown to be directly proportional to the log of maximum donor concentration. The formation energy can then be estimated and an expression for maximum donor concentration derived. Values for the maximum donor concentration with each of the halogen impurities, within the Zn II-VI compounds, are computed. This model predicts that the halogens will serve as electron donors in these compounds in order of increasing effectiveness as: F, Br, I, Cl. Finally, this result is taken to be equivalent to an alternative model where donor concentration depends upon impurity diffusion and the conduction band energy shift due to a depletion region at the growing crystal's surface. From this, we are able to estimate the diffusion activation energy for each of the impurities mentioned above. Comparisons are made with reported values and relevant conclusions presented.

MOVPE Growth of LWIR AlInAs/GaInAs/InP Quantum Cascade Lasers: Impact of Growth and Material Quality on Laser Performance

DTIC Science & Technology

2017-02-01

MOVPE Growth of LWIR AlInAs/GaInAs/InP Quantum Cascade Lasers: Impact of Growth and Material Quality on Laser Performance (Invited paper) Christine A...epitaxial layers in quantum cascade lasers (QCLs) has a primary impact on QCL operation, and establishing correlations between epitaxial growth and materials...QCLs emitting in this range. Index terms – Quantum cascade lasers, semiconductor growth, semiconductor epitaxial layers, infrared emitters. I

Effect of Al2O3 insulator thickness on the structural integrity of amorphous indium-gallium-zinc-oxide based thin film transistors.

PubMed

Kim, Hak-Jun; Hwang, In-Ju; Kim, Youn-Jea

2014-12-01

The current transparent oxide semiconductors (TOSs) technology provides flexibility and high performance. In this study, multi-stack nano-layers of TOSs were designed for three-dimensional analysis of amorphous indium-gallium-zinc-oxide (a-IGZO) based thin film transistors (TFTs). In particular, the effects of torsional and compressive stresses on the nano-sized active layers such as the a-IGZO layer were investigated. Numerical simulations were carried out to investigate the structural integrity of a-IGZO based TFTs with three different thicknesses of the aluminum oxide (Al2O3) insulator (δ = 10, 20, and 30 nm), respectively, using a commercial code, COMSOL Multiphysics. The results are graphically depicted for operating conditions.

Atomic Layer Deposited Thin Films for Dielectrics, Semiconductor Passivation, and Solid Oxide Fuel Cells

NASA Astrophysics Data System (ADS)

Xu, Runshen

Atomic layer deposition (ALD) utilizes sequential precursor gas pulses to deposit one monolayer or sub-monolayer of material per cycle based on its self-limiting surface reaction, which offers advantages, such as precise thickness control, thickness uniformity, and conformality. ALD is a powerful means of fabricating nanoscale features in future nanoelectronics, such as contemporary sub-45 nm metal-oxide-semiconductor field effect transistors, photovoltaic cells, near- and far-infrared detectors, and intermediate temperature solid oxide fuel cells. High dielectric constant, kappa, materials have been recognized to be promising candidates to replace traditional SiO2 and SiON, because they enable good scalability of sub-45 nm MOSFET (metal-oxide-semiconductor field-effect transistor) without inducing additional power consumption and heat dissipation. In addition to high dielectric constant, high-kappa materials must meet a number of other requirements, such as low leakage current, high mobility, good thermal and structure stability with Si to withstand high-temperature source-drain activation annealing. In this thesis, atomic layer deposited Er2O3 doped TiO2 is studied and proposed as a thermally stable amorphous high-kappa dielectric on Si substrate. The stabilization of TiO2 in its amorphous state is found to achieve a high permittivity of 36, a hysteresis voltage of less than 10 mV, and a low leakage current density of 10-8 A/cm-2 at -1 MV/cm. In III-V semiconductors, issues including unsatisfied dangling bonds and native oxides often result in inferior surface quality that yields non-negligible leakage currents and degrades the long-term performance of devices. The traditional means for passivating the surface of III-V semiconductors are based on the use of sulfide solutions; however, that only offers good protection against oxidation for a short-term (i.e., one day). In this work, in order to improve the chemical passivation efficacy of III-V semiconductors, ultra-thin layer of encapsulating ZnS is coated on the surface of GaSb and GaSb/InAs substrates. The 2 nm-thick ZnS film is found to provide a long-term protection against reoxidation for one order and a half longer times than prior reported passivation likely due to its amorphous structure without pinholes. Finally, a combination of binary ALD processes is developed and demonstrated for the growth of yttria-stabilized zirconia films using alkylamido-cyclopentadiengyls zirconium and tris(isopropyl-cyclopentadienyl)yttrium, as zirconium and yttrium precursors, respectively, with ozone being the oxidant. The desired cubic structure of YSZ films is apparently achieved after post-deposition annealing. Further, platinum is atomic layer deposited as electrode on YSZ (8 mol% of Yttria) within the same system. In order to control the morphology of as-deposited Pt thin structure, the nucleation behavior of Pt on amorphous and cubic YSZ is investigated. Three different morphologies of Pt are observed, including nanoparticle, porous and dense films, which are found to depend on the ALD cycle number and the structure and morphology of they underlying ALD YSZ films.

Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors

NASA Astrophysics Data System (ADS)

Marrs, Michael

A low temperature amorphous oxide thin film transistor (TFT) and amorphous silicon PIN diode backplane technology for large area flexible digital x-ray detectors has been developed to create 7.9-in. diagonal backplanes. The critical steps in the evolution of the backplane process include the qualification and optimization of the low temperature (200 °C) metal oxide TFT and a-Si PIN photodiode process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication and assembly of the flexible detectors. Mixed oxide semiconductor TFTs on flexible plastic substrates suffer from performance and stability issues related to the maximum processing temperature limitation of the polymer. A novel device architecture based upon a dual active layer improves both the performance and stability. Devices are directly fabricated below 200 ºC on a polyethylene naphthalate (PEN) substrate using mixed metal oxides of either zinc indium oxide (ZIO) or indium gallium zinc oxide (IGZO) as the active semiconductor. The dual active layer architecture allows for adjustment to the saturation mobility and threshold voltage stability without the requirement of high temperature annealing, which is not compatible with flexible plastic substrates like PEN. The device performance and stability is strongly dependent upon the composition of the mixed metal oxide; this dependency provides a simple route to improving the threshold voltage stability and drive performance. By switching from a single to a dual active layer, the saturation mobility increases from 1.2 cm2/V-s to 18.0 cm2/V-s, while the rate of the threshold voltage shift decreases by an order of magnitude. This approach could assist in enabling the production of devices on flexible substrates using amorphous oxide semiconductors. Low temperature (200°C) processed amorphous silicon photodiodes were developed successfully by balancing the tradeoffs between low temperature and low stress (less than -70 MPa compressive) and device performance. Devices with a dark current of less than 1.0 pA/mm2 and a quantum efficiency of 68% have been demonstrated. Alternative processing techniques, such as pixelating the PIN diode and using organic photodiodes have also been explored for applications where extreme flexibility is desired.

Process for selectively patterning epitaxial film growth on a semiconductor substrate

DOEpatents

Sheldon, P.; Hayes, R.E.

1984-12-04

Disclosed is a process for selectively patterning epitaxial film growth on a semiconductor substrate. The process includes forming a masking member on the surface of the substrate, the masking member having at least two layers including a first layer disposed on the substrate and the second layer covering the first layer. A window is then opened in a selected portion of the second layer by removing that portion to expose the first layer thereunder. The first layer is then subjected to an etchant introduced through the window to dissolve the first layer a sufficient amount to expose the substrate surface directly beneath the window, the first layer being adapted to preferentially dissolve at a substantially greater rate than the second layer so as to create an overhanging ledge portion with the second layer by undercutting the edges thereof adjacent the window. The epitaxial film is then deposited on the exposed substrate surface directly beneath the window. Finally, an etchant is introduced through the window to dissolve the remainder of the first layer so as to lift-off the second layer and materials deposited thereon to fully expose the balance of the substrate surface.

Process for selectively patterning epitaxial film growth on a semiconductor substrate

DOEpatents

Sheldon, Peter; Hayes, Russell E.

1986-01-01

A process is disclosed for selectively patterning epitaxial film growth on a semiconductor substrate. The process includes forming a masking member on the surface of the substrate, the masking member having at least two layers including a first layer disposed on the substrate and the second layer covering the first layer. A window is then opened in a selected portion of the second layer by removing that portion to expose the first layer thereunder. The first layer is then subjected to an etchant introduced through the window to dissolve a sufficient amount of the first layer to expose the substrate surface directly beneath the window, the first layer being adapted to preferentially dissolve at a substantially greater rate than the second layer so as to create an overhanging ledge portion with the second layer by undercutting the edges thereof adjacent to the window. The epitaxial film is then deposited on the exposed substrate surface directly beneath the window. Finally, an etchant is introduced through the window to dissolve the remainder of the first layer so as to lift-off the second layer and materials deposited thereon to fully expose the balance of the substrate surface.

Plastic Schottky-barrier solar cells

DOEpatents

Waldrop, J.R.; Cohen, M.J.

1981-12-30

A photovoltaic cell structure is fabricated from an active medium including an undoped polyacetylene, organic semiconductor. When a film of such material is in rectifying contact with a metallic area electrode, a Schottky-barrier junction is obtained within the body of the cell structure. Also, a gold overlayer passivates a magnesium layer on the undoped polyacetylene film. With the proper selection and location of elements a photovoltaic cell structure and solar cell are obtained.

Continuous wave terahertz radiation from an InAs/GaAs quantum-dot photomixer device

NASA Astrophysics Data System (ADS)

Kruczek, T.; Leyman, R.; Carnegie, D.; Bazieva, N.; Erbert, G.; Schulz, S.; Reardon, C.; Reynolds, S.; Rafailov, E. U.

2012-08-01

Generation of continuous wave radiation at terahertz (THz) frequencies from a heterodyne source based on quantum-dot (QD) semiconductor materials is reported. The source comprises an active region characterised by multiple alternating photoconductive and QD carrier trapping layers and is pumped by two infrared optical signals with slightly offset wavelengths, allowing photoconductive device switching at the signals' difference frequency ˜1 THz.

Quantifying resistances across nanoscale low- and high-angle interspherulite boundaries in solution-processed organic semiconductor thin films.

PubMed

Lee, Stephanie S; Mativetsky, Jeffrey M; Loth, Marsha A; Anthony, John E; Loo, Yueh-Lin

2012-11-27

The nanoscale boundaries formed when neighboring spherulites impinge in polycrystalline, solution-processed organic semiconductor thin films act as bottlenecks to charge transport, significantly reducing organic thin-film transistor mobility in devices comprising spherulitic thin films as the active layers. These interspherulite boundaries (ISBs) are structurally complex, with varying angles of molecular orientation mismatch along their lengths. We have successfully engineered exclusively low- and exclusively high-angle ISBs to elucidate how the angle of molecular orientation mismatch at ISBs affects their resistivities in triethylsilylethynyl anthradithiophene thin films. Conductive AFM and four-probe measurements reveal that current flow is unaffected by the presence of low-angle ISBs, whereas current flow is significantly disrupted across high-angle ISBs. In the latter case, we estimate the resistivity to be 22 MΩμm(2)/width of the ISB, only less than a quarter of the resistivity measured across low-angle grain boundaries in thermally evaporated sexithiophene thin films. This discrepancy in resistivities across ISBs in solution-processed organic semiconductor thin films and grain boundaries in thermally evaporated organic semiconductor thin films likely arises from inherent differences in the nature of film formation in the respective systems.

Effect of Water Vapor and Surface Morphology on the Low Temperature Response of Metal Oxide Semiconductor Gas Sensors

PubMed Central

Maier, Konrad; Helwig, Andreas; Müller, Gerhard; Hille, Pascal; Eickhoff, Martin

2015-01-01

In this work the low temperature response of metal oxide semiconductor gas sensors is analyzed. Important characteristics of this low-temperature response are a pronounced selectivity to acid- and base-forming gases and a large disparity of response and recovery time constants which often leads to an integrator-type of gas response. We show that this kind of sensor performance is related to the trend of semiconductor gas sensors to adsorb water vapor in multi-layer form and that this ability is sensitively influenced by the surface morphology. In particular we show that surface roughness in the nanometer range enhances desorption of water from multi-layer adsorbates, enabling them to respond more swiftly to changes in the ambient humidity. Further experiments reveal that reactive gases, such as NO2 and NH3, which are easily absorbed in the water adsorbate layers, are more easily exchanged across the liquid/air interface when the humidity in the ambient air is high. PMID:28793583

Regulation of depletion layer width in Pb(Zr,Ti)O3/Nb:SrTiO3 heterostructures

NASA Astrophysics Data System (ADS)

Bai, Yu; Jie Wang, Zhan; Cui, Jian Zhong; Zhang, Zhi Dong

2018-05-01

Improving the tunability of depletion layer width (DLW) in ferroelectric/semiconductor heterostructures is important for the performance of some devices. In this work, 200-nm-thick Pb(Zr0.4Ti0.6)O3 (PZT) films were deposited on different Nb-doped SrTiO3 (NSTO) substrates, and the tunability of DLW at PZT/NSTO interfaces were studied. Our results showed that the maximum tunability of the DLW was achieved at the NSTO substrate with 0.5 wt% Nb. On the basis of the modified capacitance model and the ferroelectric semiconductor theory, we suggest that the tunability of the DLW in PZT/NSTO heterostructures can be attributed to a delicate balance of the depletion layer charge and the ferroelectric polarization charge. Therefore, the performance of some devices related to the tunability of DLW in ferroelectric/semiconductor heterostructures can be improved by modulating the doping concentration in semiconducting electrode materials.

The effects of Bi4Ti3O12 interfacial ferroelectric layer on the dielectric properties of Au/n-Si structures

NASA Astrophysics Data System (ADS)

Gökçen, Muharrem; Yıldırım, Mert

2015-06-01

Au/n-Si metal-semiconductor (MS) and Au/Bi4Ti3O12/n-Si metal-ferroelectric-semiconductor (MFS) structures were fabricated and admittance measurements were held between 5 kHz and 1 MHz at room temperature so that dielectric properties of these structures could be investigated. The ferroelectric interfacial layer Bi4Ti3O12 decreased the polarization voltage by providing permanent dipoles at metal/semiconductor interface. Depending on different mechanisms, dispersion behavior was observed in dielectric constant, dielectric loss and loss tangent versus bias voltage plots of both MS and MFS structures. The real and imaginary parts of complex modulus of MFS structure take smaller values than those of MS structure, because permanent dipoles in ferroelectric layer cause a large spontaneous polarization mechanism. While the dispersion in AC conductivity versus frequency plots of MS structure was observed at high frequencies, for MFS structure it was observed at lower frequencies.

Formation of Ideal Rashba States on Layered Semiconductor Surfaces Steered by Strain Engineering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ming, Wenmei; Wang, Z. F.; Zhou, Miao

2015-12-10

Spin splitting of Rashba states in two-dimensional electron system provides a mechanism of spin manipulation for spintronics applications. However, Rashba states realized experimentally to date are often outnumbered by spin-degenerated substrate states at the same energy range, hindering their practical applications. Here, by density functional theory calculation, we show that Au one monolayer film deposition on a layered semiconductor surface β-InSe(0001) can possess “ideal” Rashba states with large spin splitting, which are completely situated inside the large band gap of the substrate. The position of the Rashba bands can be tuned over a wide range with respect to the substratemore » band edges by experimentally accessible strain. Furthermore, our nonequilibrium Green’s function transport calculation shows that this system may give rise to the long-sought strong current modulation when made into a device of Datta-Das transistor. Similar systems may be identified with other metal ultrathin films and layered semiconductor substrates to realize ideal Rashba states.« less

Development and characterization of semiconductor ion detectors for plasma diagnostics in the range over 0.3 keV

NASA Astrophysics Data System (ADS)

Cho, T.; Sakamoto, Y.; Hirata, M.; Kohagura, J.; Makino, K.; Kanke, S.; Takahashi, K.; Okamura, T.; Nakashima, Y.; Yatsu, K.; Tamano, T.; Miyoshi, S.

1997-01-01

For the purpose of plasma-ion-energy analyses in a wide-energy range from a few hundred eV to hundreds of keV, upgraded semiconductor detectors are newly fabricated and characterized using a test-ion-beam line from 0.3 to 12 keV. In particular, the detectable lowest-ion energy is drastically improved at least down to 0.3 keV; this energy is one to two orders-of-magnitude better than those for commercially available Si-surface-barrier diodes employed for previous plasma-ion diagnostics. A signal-to-noise ratio of two to three orders-of-magnitude better than that for usual metal-collector detectors is demonstrated for the compact-sized semiconductor along with the availability of the use under conditions of a good vacuum and a strong-magnetic field. Such characteristics are achieved due to the improving methods of the optimization of the thicknesses of a Si dead layer and a SiO2 layer, as well as the nitrogen-doping technique near the depletion layer along with minimizing impurity concentrations in Si. Such an upgraded capability of an extremely low-energy-ion detection with the low-noise characteristics enlarges research regimes of plasma-ion behavior using semiconductor detectors not only in the divertor regions of tokamaks but in wider spectra of open-field plasma devices including tandem mirrors. An application of the semiconductor ion detector for plasma-ion diagnostics is demonstrated in a specially designed ion-spectrometer structure.

Hot Carrier Extraction from Multilayer Graphene.

PubMed

Urcuyo, Roberto; Duong, Dinh Loc; Sailer, Patrick; Burghard, Marko; Kern, Klaus

2016-11-09

Hot carriers in semiconductor or metal nanostructures are relevant, for instance, to enhance the activity of oxide-supported metal catalysts or to achieve efficient photodetection using ultrathin semiconductor layers. Moreover, rapid collection of photoexcited hot carriers can improve the efficiency of solar cells, with a theoretical maximum of 85%. Because of the long lifetime of secondary excited electrons, graphene is an especially promising two-dimensional material to harness hot carriers for solar-to-electricity conversion. However, the photoresponse of thus far realized graphene photoelectric devices is mainly governed by thermal effects, which yield only a very small photovoltage. Here, we report a Gr-TiO x -Ti heterostructure wherein the photovoltaic effect is predominant. By doping the graphene, the open circuit voltage reaches values up to 0.30 V, 2 orders of magnitude larger than for devices relying upon the thermoelectric effect. The photocurrent turned out to be limited by trap states in the few-nanometer-thick TiO x layer. Our findings represent a first valuable step toward the integration of graphene into third-generation solar cells based upon hot carrier extraction.

Flexible black phosphorus ambipolar transistors, circuits and AM demodulator.

PubMed

Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

2015-03-11

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles.

Transparent amorphous oxide semiconductors for organic electronics: Application to inverted OLEDs

PubMed Central

Hosono, Hideo; Toda, Yoshitake; Kamiya, Toshio; Watanabe, Satoru

2017-01-01

Efficient electron transfer between a cathode and an active organic layer is one key to realizing high-performance organic devices, which require electron injection/transport materials with very low work functions. We developed two wide-bandgap amorphous (a-) oxide semiconductors, a-calcium aluminate electride (a-C12A7:e) and a-zinc silicate (a-ZSO). A-ZSO exhibits a low work function of 3.5 eV and high electron mobility of 1 cm2/(V · s); furthermore, it also forms an ohmic contact with not only conventional cathode materials but also anode materials. A-C12A7:e has an exceptionally low work function of 3.0 eV and is used to enhance the electron injection property from a-ZSO to an emission layer. The inverted electron-only and organic light-emitting diode (OLED) devices fabricated with these two materials exhibit excellent performance compared with the normal type with LiF/Al. This approach provides a solution to the problem of fabricating oxide thin-film transistor-driven OLEDs with both large size and high stability. PMID:28028243

Investigation of defect modes in a defective photonic crystal with a semiconductor metamaterial defect

NASA Astrophysics Data System (ADS)

Wu, Meng-Ru; Wu, Chien-Jang; Chang, Shoou-Jinn

2014-11-01

In this work, we theoretically investigate the properties of defect modes in a defective photonic crystal containing a semiconductor metamaterial defect. We consider the structure, (LH)N/DP/(LH)N, where N and P are respectively the stack numbers, L is SiO2, H is InP, and defect layer D is a semiconductor metamaterial composed of Al-doped ZnO (AZO) and ZnO. It is found that, within the photonic band gap, the number of defect modes (transmission peaks) will decrease as the defect thickness increases, in sharp contrast to the case of using usual dielectric defect. The peak height and position can be changed by the variation in the thickness of defect layer. In the angle-dependent defect mode, its position is shown to be blue-shifted as the angle of incidence increases for both TE and TM waves. The analysis of defect mode provides useful information for the design of tunable transmission filter in semiconductor optoelectronics.

Chemical-mechanical polishing of recessed microelectromechanical devices

DOEpatents

Barron, Carole C.; Hetherington, Dale L.; Montague, Stephen

1999-01-01

A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g. CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate.

Micro-fabricated integrated coil and magnetic circuit and method of manufacturing thereof

DOEpatents

Mihailovich, Robert E.; Papavasiliou, Alex P.; Mehrotra, Vivek; Stupar, Philip A.; Borwick, III, Robert L.; Ganguli, Rahul; DeNatale, Jeffrey F.

2017-03-28

A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material.

Chemical-mechanical polishing of recessed microelectromechanical devices

DOEpatents

Barron, C.C.; Hetherington, D.L.; Montague, S.

1999-07-06

A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g., CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate. 23 figs.

Charge transfer at organic-inorganic interfaces—Indoline layers on semiconductor substrates

NASA Astrophysics Data System (ADS)

Meyenburg, I.; Falgenhauer, J.; Rosemann, N. W.; Chatterjee, S.; Schlettwein, D.; Heimbrodt, W.

2016-12-01

We studied the electron transfer from excitons in adsorbed indoline dye layers across the organic-inorganic interface. The hybrids consist of indoline derivatives on the one hand and different inorganic substrates (TiO2, ZnO, SiO2(0001), fused silica) on the other. We reveal the electron transfer times from excitons in dye layers to the organic-inorganic interface by analyzing the photoluminescence transients of the dye layers after femtosecond excitation and applying kinetic model calculations. A correlation between the transfer times and four parameters have been found: (i) the number of anchoring groups, (ii) the distance between the dye and the organic-inorganic interface, which was varied by the alkyl-chain lengths between the carboxylate anchoring group and the dye, (iii) the thickness of the adsorbed dye layer, and (iv) the level alignment between the excited dye ( π* -level) and the conduction band minimum of the inorganic semiconductor.

INTERNATIONAL CONFERENCE ON SEMICONDUCTOR INJECTION LASERS SELCO-87: Relationship between the p-n junction position and the threshold current of stripe lasers emitting in the 1.3-μm range

NASA Astrophysics Data System (ADS)

Walachová, J.; Zelinka, J.

1988-11-01

The method of profiling with a probe was used to determine the p-n junction position in the active layer InP/GaInAsP double heterostructure lasers designed for operation in the region of 1.3 μm. Double heterostructures with different Zn concentrations in the upper GaInAsP layer were investigated. An explanation was provided of the shift or lack of shift of the p-n junction in different heterostructure lasers. The average threshold current was correlated with the p-n junction position.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

PubMed

Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2018-05-08

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

Superheating Suppresses Structural Disorder in Layered BiI3 Semiconductors Grown by the Bridgman Method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johns, Paul M.; Sulekar, Soumitra; Yeo, Shinyoung

2016-01-01

The susceptibility of layered structures to stacking faults is a problem in some of the more attractive semiconductor materials for ambient-temperature radiation detectors. In the work presented here, Bridgman-grown BiI3 layered single crystals are investigated to understand and eliminate this structural disorder, which reduces radiation detector performance. The use of superheating gradients has been shown to improve crystal quality in non-layered semiconductor crystals; thus the technique was here explored to improve the growth of BiI3. When investigating the homogeneity of non-superheated crystals, highly geometric void defects were found to populate the bulk of the crystals. Applying a superheating gradient tomore » the melt prior to crystal growth improved structural quality and decreased defect density from the order of 4600 voids per cm3 to 300 voids per cm3. Corresponding moderate improvements to electronic properties also resulted from the superheat gradient method of crystal growth. Comparative measurements through infrared microscopy, etch-pit density, x-ray rocking curves, and sheet resistivity readings show that superheat gradients in BiI3 growth led to higher quality crystals.« less

Optical bandgap of single- and multi-layered amorphous germanium ultra-thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Pei; Zaslavsky, Alexander; Longo, Paolo

2016-01-07

Accurate optical methods are required to determine the energy bandgap of amorphous semiconductors and elucidate the role of quantum confinement in nanometer-scale, ultra-thin absorbing layers. Here, we provide a critical comparison between well-established methods that are generally employed to determine the optical bandgap of thin-film amorphous semiconductors, starting from normal-incidence reflectance and transmittance measurements. First, we demonstrate that a more accurate estimate of the optical bandgap can be achieved by using a multiple-reflection interference model. We show that this model generates more reliable results compared to the widely accepted single-pass absorption method. Second, we compare two most representative methods (Taucmore » and Cody plots) that are extensively used to determine the optical bandgap of thin-film amorphous semiconductors starting from the extracted absorption coefficient. Analysis of the experimental absorption data acquired for ultra-thin amorphous germanium (a-Ge) layers demonstrates that the Cody model is able to provide a less ambiguous energy bandgap value. Finally, we apply our proposed method to experimentally determine the optical bandgap of a-Ge/SiO{sub 2} superlattices with single and multiple a-Ge layers down to 2 nm thickness.« less

Atomic-order thermal nitridation of group IV semiconductors for ultra-large-scale integration

NASA Astrophysics Data System (ADS)

Murota, Junichi; Le Thanh, Vinh

2015-03-01

One of the main requirements for ultra-large-scale integration (ULSI) is atomic-order control of process technology. Our concept of atomically controlled processing for group IV semiconductors is based on atomic-order surface reaction control in Si-based CVD epitaxial growth. On the atomic-order surface nitridation of a few nm-thick Ge/about 4 nm-thick Si0.5Ge0.5/Si(100) by NH3, it is found that N atoms diffuse through nm-order thick Ge layer into Si0.5Ge0.5/Si(100) substrate and form Si nitride, even at 500 °C. By subsequent H2 heat treatment, although N atomic amount in Ge layer is reduced drastically, the reduction of the Si nitride is slight. It is suggested that N diffusion in Ge layer is suppressed by the formation of Si nitride and that Ge/atomic-order N layer/Si1-xGex/Si (100) heterostructure is formed. These results demonstrate the capability of CVD technology for atomically controlled nitridation of group IV semiconductors for ultra-large-scale integration. Invited talk at the 7th International Workshop on Advanced Materials Science and Nanotechnology IWAMSN2014, 2-6 November, 2014, Ha Long, Vietnam.

Removal of GaAs growth substrates from II-VI semiconductor heterostructures

NASA Astrophysics Data System (ADS)

Bieker, S.; Hartmann, P. R.; Kießling, T.; Rüth, M.; Schumacher, C.; Gould, C.; Ossau, W.; Molenkamp, L. W.

2014-04-01

We report on a process that enables the removal of II-VI semiconductor epilayers from their GaAs growth substrate and their subsequent transfer to arbitrary host environments. The technique combines mechanical lapping and layer selective chemical wet etching and is generally applicable to any II-VI layer stack. We demonstrate the non-invasiveness of the method by transferring an all-II-VI magnetic resonant tunneling diode. High resolution x-ray diffraction proves that the crystal integrity of the heterostructure is preserved. Transport characterization confirms that the functionality of the device is maintained and even improved, which is ascribed to completely elastic strain relaxation of the tunnel barrier layer.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

Metal-insulator-semiconductor heterostructures for plasmonic hot-carrier optoelectronics.

PubMed

García de Arquer, F Pelayo; Konstantatos, Gerasimos

2015-06-01

Plasmonic hot-electron devices are attractive candidates for light-energy harvesting and photodetection applications. For solid state devices, the most compact and straightforward architecture is the metal-semiconductor Schottky junction. However convenient, this structure introduces limitations such as the elevated dark current associated to thermionic emission, or constraints for device design due to the finite choice of materials. In this work we theoretically consider the metal-insulator-semiconductor heterojunction as a candidate for plasmonic hot-carrier photodetection and solar cells. The presence of the insulating layer can significantly reduce the dark current, resulting in increased device performance with predicted solar power conversion efficiencies up to 9%. For photodetection, the sensitivity can be extended well into the infrared by a judicious choice of the insulating layer, with up to 300-fold expected enhancement in detectivity.

Ultrathin metal-semiconductor-metal resonator for angle invariant visible band transmission filters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Kyu-Tae; Seo, Sungyong; Yong Lee, Jae

We present transmission visible wavelength filters based on strong interference behaviors in an ultrathin semiconductor material between two metal layers. The proposed devices were fabricated on 2 cm × 2 cm glass substrate, and the transmission characteristics show good agreement with the design. Due to a significantly reduced light propagation phase change associated with the ultrathin semiconductor layer and the compensation in phase shift of light reflecting from the metal surface, the filters show an angle insensitive performance up to ±70°, thus, addressing one of the key challenges facing the previously reported photonic and plasmonic color filters. This principle, described in this paper, canmore » have potential for diverse applications ranging from color display devices to the image sensors.« less

Coaxial metal-oxide-semiconductor (MOS) Au/Ga2O3/GaN nanowires.

PubMed

Hsieh, Chin-Hua; Chang, Mu-Tung; Chien, Yu-Jen; Chou, Li-Jen; Chen, Lih-Juann; Chen, Chii-Dong

2008-10-01

Coaxial metal-oxide-semiconductor (MOS) Au-Ga2O3-GaN heterostructure nanowires were successfully fabricated by an in situ two-step process. The Au-Ga2O3 core-shell nanowires were first synthesized by the reaction of Ga powder, a mediated Au thin layer, and a SiO2 substrate at 800 degrees C. Subsequently, these core-shell nanowires were nitridized in ambient ammonia to form a GaN coating layer at 600 degrees C. The GaN shell is a single crystal, an atomic flat interface between the oxide and semiconductor that ensures that the high quality of the MOS device is achieved. These novel 1D nitride-based MOS nanowires may have promise as building blocks to the future nitride-based vertical nanodevices.

Layer-by-layer modification of thin-film metal-semiconductor multilayers with ultrashort laser pulses

NASA Astrophysics Data System (ADS)

Romashevskiy, S. A.; Tsygankov, P. A.; Ashitkov, S. I.; Agranat, M. B.

2018-05-01

The surface modifications in a multilayer thin-film structure (50-nm alternating layers of Si and Al) induced by a single Gaussian-shaped femtosecond laser pulse (350 fs, 1028 nm) in the air are investigated by means of atomic-force microscopy (AFM), scanning electron microscopy (SEM), and optical microscopy (OM). Depending on the laser fluence, various modifications of nanometer-scale metal and semiconductor layers, including localized formation of silicon/aluminum nanofoams and layer-by-layer removal, are found. While the nanofoams with cell sizes in the range of tens to hundreds of nanometers are produced only in the two top layers, layer-by-layer removal is observed for the four top layers under single pulse irradiation. The 50-nm films of the multilayer structure are found to be separated at their interfaces, resulting in a selective removal of several top layers (up to 4) in the form of step-like (concentric) craters. The observed phenomenon is associated with a thermo-mechanical ablation mechanism that results in splitting off at film-film interface, where the adhesion force is less than the bulk strength of the used materials, revealing linear dependence of threshold fluences on the film thickness.

Enhancement of light absorption in polyazomethines due to plasmon excitation on randomly distributed metal nanoparticles

NASA Astrophysics Data System (ADS)

Wróbel, P.; Antosiewicz, T. J.; Stefaniuk, T.; Ciesielski, A.; Iwan, A.; Wronkowska, A. A.; Wronkowski, A.; Szoplik, T.

2015-05-01

In photovoltaic devices, metal nanoparticles embedded in a semiconductor layer allow the enhancement of solar-toelectric energy conversion efficiency due to enhanced light absorption via a prolonged optical path, enhanced electric fields near the metallic inclusions, direct injection of hot electrons, or local heating. Here we pursue the first two avenues. In the first, light scattered at an angle beyond the critical angle for reflection is coupled into the semiconductor layer and confined within such planar waveguide up to possible exciton generation. In the second, light is trapped by the excitation of localized surface plasmons on metal nanoparticles leading to enhanced near-field plasmon-exciton coupling at the peak of the plasmon resonance. We report on results of a numerical experiment on light absorption in polymer- (fullerene derivative) blends, using the 3D FDTD method, where exact optical parameters of the materials involved are taken from our recent measurements. In simulations we investigate light absorption in randomly distributed metal nanoparticles dispersed in polyazomethine-(fullerene derivative) blends, which serve as active layers in bulkheterojunction polymer solar cells. In the study Ag and Al nanoparticles of different diameters and fill factors are diffused in two air-stable aromatic polyazomethines with different chemical structures (abbreviated S9POF and S15POF) mixed with phenyl-C61-butyric acid methyl ester (PCBM) or [6,6]-phenyl-C71-butyric acid methyl ester (PC71BM). The mixtures are spin coated on a 100 nm thick Al layer deposited on a fused silica substrate. Optical constants of the active layers are taken from spectroscopic ellipsometry and reflectance measurements using a rotating analyzer type ellipsometer with auto-retarder performed in the wavelength range from 225 nm to 2200 nm. The permittivities of Ag and Al particles of diameters from 20 to 60 nm are assumed to be equal to those measured on 100 to 200 nm thick metal films.

Heterogeneous integration based on low-temperature bonding for advanced optoelectronic devices

NASA Astrophysics Data System (ADS)

Higurashi, Eiji

2018-04-01

Heterogeneous integration is an attractive approach to manufacturing future optoelectronic devices. Recent progress in low-temperature bonding techniques such as plasma activation bonding (PAB) and surface-activated bonding (SAB) enables a new approach to integrating dissimilar materials for a wide range of photonics applications. In this paper, low-temperature direct bonding and intermediate layer bonding techniques are focused, and their state-of-the-art applications in optoelectronic devices are reviewed. First, we describe the room-temperature direct bonding of Ge/Ge and Ge/Si wafers for photodetectors and of GaAs/SiC wafers for high-power semiconductor lasers. Then, we describe low-temperature intermediate layer bonding using Au and lead-free Sn-3.0Ag-0.5Cu solders for optical sensors and MEMS packaging.

Photonic crystals for improving light absorption in organic solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Duché, D., E-mail: david.duche@im2np.fr; Le Rouzo, J.; Masclaux, C.

2015-02-07

We theoretically and experimentally study the structuration of organic solar cells in the shape of photonic crystal slabs. By taking advantage of the optical properties of photonic crystals slabs, we show the possibility to couple Bloch modes with very low group velocities in the active layer of the cells. These Bloch modes, also called slow Bloch modes (SBMs), allow increasing the lifetime of photons within the active layer. Finally, we present experimental demonstration performed by using nanoimprint to directly pattern the standard poly-3-hexylthiophène:[6,6]-phenyl-C61-butiryc acid methyl ester organic semiconductor blend in thin film form in the shape of a photonic crystalmore » able to couple SBMs. In agreement with the model, optical characterizations will demonstrate significant photonic absorption gains.« less

Low-Resistivity Zinc Selenide for Heterojunctions

NASA Technical Reports Server (NTRS)

Stirn, R. J.

1986-01-01

Magnetron reactive sputtering enables doping of this semiconductor. Proposed method of reactive sputtering combined with doping shows potential for yielding low-resistivity zinc selenide films. Zinc selenide attractive material for forming heterojunctions with other semiconductor compounds as zinc phosphide, cadmium telluride, and gallium arsenide. Semiconductor junctions promising for future optoelectronic devices, including solar cells and electroluminescent displays. Resistivities of zinc selenide layers deposited by evaporation or chemical vapor deposition too high to form practical heterojunctions.

Gas sensing in 2D materials

NASA Astrophysics Data System (ADS)

Yang, Shengxue; Jiang, Chengbao; Wei, Su-huai

2017-06-01

Two-dimensional (2D) layered inorganic nanomaterials have attracted huge attention due to their unique electronic structures, as well as extraordinary physical and chemical properties for use in electronics, optoelectronics, spintronics, catalysts, energy generation and storage, and chemical sensors. Graphene and related layered inorganic analogues have shown great potential for gas-sensing applications because of their large specific surface areas and strong surface activities. This review aims to discuss the latest advancements in the 2D layered inorganic materials for gas sensors. We first elaborate the gas-sensing mechanisms and introduce various types of gas-sensing devices. Then, we describe the basic parameters and influence factors of the gas sensors to further enhance their performance. Moreover, we systematically present the current gas-sensing applications based on graphene, graphene oxide (GO), reduced graphene oxide (rGO), functionalized GO or rGO, transition metal dichalcogenides, layered III-VI semiconductors, layered metal oxides, phosphorene, hexagonal boron nitride, etc. Finally, we conclude the future prospects of these layered inorganic materials in gas-sensing applications.

Highly improved photo-induced bias stability of sandwiched triple layer structure in sol-gel processed fluorine-doped indium zinc oxide thin film transistor

NASA Astrophysics Data System (ADS)

Kim, Dongha; Park, Hyungjin; Bae, Byeong-Soo

2016-03-01

In order to improve the reliability of TFT, an Al2O3 insulating layer is inserted between active fluorine doped indium zinc oxide (IZO:F) thin films to form a sandwiched triple layer. All the thin films were fabricated via low-cost sol-gel process. Due to its large energy bandgap and high bonding energy with oxygen atoms, the Al2O3 layer acts as a photo-induced positive charge blocking layer that effectively blocks the migration of both holes and V o2+ toward the interface between the gate insulator and the semiconductor. The inserted Al2O3 triple layer exhibits a noticeably low turn on voltage shift of -0.7 V under NBIS as well as the good TFT performance with a mobility of 10.9 cm2/V ṡ s. We anticipate that this approach can be used to solve the stability issues such as NBIS, which is caused by inescapable oxygen vacancies.

Inversion layer MOS solar cells

NASA Technical Reports Server (NTRS)

Ho, Fat Duen

1986-01-01

Inversion layer (IL) Metal Oxide Semiconductor (MOS) solar cells were fabricated. The fabrication technique and problems are discussed. A plan for modeling IL cells is presented. Future work in this area is addressed.

Planar heterostructures of single-layer transition metal dichalcogenides: Composite structures, Schottky junctions, tunneling barriers, and half metals

NASA Astrophysics Data System (ADS)

Aras, Mehmet; Kılıç, ćetin; Ciraci, S.

2017-02-01

Planar composite structures formed from the stripes of transition metal dichalcogenides joined commensurately along their zigzag or armchair edges can attain different states in a two-dimensional (2D), single-layer, such as a half metal, 2D or one-dimensional (1D) nonmagnetic metal and semiconductor. Widening of stripes induces metal-insulator transition through the confinements of electronic states to adjacent stripes, that results in the metal-semiconductor junction with a well-defined band lineup. Linear bending of the band edges of the semiconductor to form a Schottky barrier at the boundary between the metal and semiconductor is revealed. Unexpectedly, strictly 1D metallic states develop in a 2D system along the boundaries between stripes, which pins the Fermi level. Through the δ doping of a narrow metallic stripe one attains a nanowire in the 2D semiconducting sheet or narrow band semiconductor. A diverse combination of constituent stripes in either periodically repeating or finite-size heterostructures can acquire critical fundamental features and offer device capacities, such as Schottky junctions, nanocapacitors, resonant tunneling double barriers, and spin valves. These predictions are obtained from first-principles calculations performed in the framework of density functional theory.

Photon induced non-linear quantized double layer charging in quaternary semiconducting quantum dots.

PubMed

Nair, Vishnu; Ananthoju, Balakrishna; Mohapatra, Jeotikanta; Aslam, M

2018-03-15

Room temperature quantized double layer charging was observed in 2 nm Cu 2 ZnSnS 4 (CZTS) quantum dots. In addition to this we observed a distinct non-linearity in the quantized double layer charging arising from UV light modulation of double layer. UV light irradiation resulted in a 26% increase in the integral capacitance at the semiconductor-dielectric (CZTS-oleylamine) interface of the quantum dot without any change in its core size suggesting that the cause be photocapacitive. The increasing charge separation at the semiconductor-dielectric interface due to highly stable and mobile photogenerated carriers cause larger electrostatic forces between the quantum dot and electrolyte leading to an enhanced double layer. This idea was supported by a decrease in the differential capacitance possible due to an enhanced double layer. Furthermore the UV illumination enhanced double layer gives us an AC excitation dependent differential double layer capacitance which confirms that the charging process is non-linear. This ultimately illustrates the utility of a colloidal quantum dot-electrolyte interface as a non-linear photocapacitor. Copyright © 2017 Elsevier Inc. All rights reserved.

Determination of layer-dependent exciton binding energies in few-layer black phosphorus

PubMed Central

Zhang, Guowei; Chaves, Andrey; Huang, Shenyang; Wang, Fanjie; Xing, Qiaoxia; Low, Tony; Yan, Hugen

2018-01-01

The attraction between electrons and holes in semiconductors forms excitons, which largely determine the optical properties of the hosting material, and hence the device performance, especially for low-dimensional systems. Mono- and few-layer black phosphorus (BP) are emerging two-dimensional (2D) semiconductors. Despite its fundamental importance and technological interest, experimental investigation of exciton physics has been rather limited. We report the first systematic measurement of exciton binding energies in ultrahigh-quality few-layer BP by infrared absorption spectroscopy, with layer (L) thickness ranging from 2 to 6 layers. Our experiments allow us to determine the exciton binding energy, decreasing from 213 meV (2L) to 106 meV (6L). The scaling behavior with layer numbers can be well described by an analytical model, which takes into account the nonlocal screening effect. Extrapolation to free-standing monolayer yields a large binding energy of ~800 meV. Our study provides insights into 2D excitons and their crossover from 2D to 3D, and demonstrates that few-layer BP is a promising high-quality optoelectronic material for potential infrared applications. PMID:29556530

Semiconductor-based optical refrigerator

DOEpatents

Epstein, Richard I.; Edwards, Bradley C.; Sheik-Bahae, Mansoor

2002-01-01

Optical refrigerators using semiconductor material as a cooling medium, with layers of material in close proximity to the cooling medium that carries away heat from the cooling material and preventing radiation trapping. In addition to the use of semiconducting material, the invention can be used with ytterbium-doped glass optical refrigerators.

Efficient Suppression of Defects and Charge Trapping in High Density In-Sn-Zn-O Thin Film Transistor Prepared using Microwave-Assisted Sputter.

PubMed

Goh, Youngin; Ahn, Jaehan; Lee, Jeong Rak; Park, Wan Woo; Ko Park, Sang-Hee; Jeon, Sanghun

2017-10-25

Amorphous oxide semiconductor-based thin film transistors (TFTs) have been considered as excellent switching elements for driving active-matrix organic light-emitting diodes (AMOLED) owing to their high mobility and process compatibility. However, oxide semiconductors have inherent defects, causing fast transient charge trapping and device instability. For the next-generation displays such as flexible, wearable, or transparent displays, an active semiconductor layer with ultrahigh mobility and high reliability at low deposition temperature is required. Therefore, we introduced high density plasma microwave-assisted (MWA) sputtering method as a promising deposition tool for the formation of high density and high-performance oxide semiconductor films. In this paper, we present the effect of the MWA sputtering method on the defects and fast charge trapping in In-Sn-Zn-O (ITZO) TFTs using various AC device characterization methodologies including fast I-V, pulsed I-V, transient current, low frequency noise, and discharge current analysis. Using these methods, we were able to analyze the charge trapping mechanism and intrinsic electrical characteristics, and extract the subgap density of the states of oxide TFTs quantitatively. In comparison to conventional sputtered ITZO, high density plasma MWA-sputtered ITZO exhibits outstanding electrical performance, negligible charge trapping characteristics and low subgap density of states. High-density plasma MWA sputtering method has high deposition rate even at low working pressure and control the ion bombardment energy, resulting in forming low defect generation in ITZO and presenting high performance ITZO TFT. We expect the proposed high density plasma sputtering method to be applicable to a wide range of oxide semiconductor device applications.

In0.15Ga0.85N visible-light metal-semiconductor-metal photodetector with GaN interlayers deposited by pulsed NH3

NASA Astrophysics Data System (ADS)

Wang, Hongxia; Zhang, Xiaohan; Wang, Hailong; Lv, Zesheng; Li, Yongxian; Li, Bin; Yan, Huan; Qiu, Xinjia; Jiang, Hao

2018-05-01

InGaN visible-light metal-semiconductor-metal photodetectors with GaN interlayers deposited by pulsed NH3 were fabricated and characterized. By periodically inserting the GaN thin interlayers, the surface morphology of InGaN active layer is improved and the phase separation is suppressed. At 5 V bias, the dark current reduced from 7.0 × 10-11 A to 7.0 × 10-13 A by inserting the interlayers. A peak responsivity of 85.0 mA/W was measured at 420 nm and 5 V bias, corresponding to an external quantum efficiency of 25.1%. The insertion of GaN interlayers also lead to a sharper spectral response cutoff.

Monolithic integration of a vertical cavity surface emitting laser and a metal semiconductor field effect transistor

NASA Astrophysics Data System (ADS)

Yang, Y. J.; Dziura, T. G.; Bardin, T.; Wang, S. C.; Fernandez, R.; Liao, Andrew S. H.

1993-02-01

Monolithic integration of a vertical cavity surface emitting laser (VCSEL) and a metal semiconductor field effect transistor (MESFET) is reported for the first time. The epitaxial layers for both GaAs VCSELs and MESFETs are grown on an n-type GaAs substrate by molecular-beam epitaxy at the same time. The VCSELs with a 10-micron diam active region exhibit an average threshold current (Ith) of 6 mA and a continuous wave (CW) maximum power of 1.1 mW. The MESFETs with a 3-micron gate length have a transconductance of 50 mS/mm. The laser output is modulated by the gate voltage of the MESFETs and exhibits an optical/electrical conversion factor of 0.5 mW/V.

Silicon metal-semiconductor-metal photodetector

DOEpatents

Brueck, Steven R. J.; Myers, David R.; Sharma, Ashwani K.

1997-01-01

Silicon MSM photodiodes sensitive to radiation in the visible to near infrared spectral range are produced by altering the absorption characteristics of crystalline Si by ion implantation. The implantation produces a defected region below the surface of the silicon with the highest concentration of defects at its base which acts to reduce the contribution of charge carriers formed below the defected layer. The charge carriers generated by the radiation in the upper regions of the defected layer are very quickly collected between biased Schottky barrier electrodes which form a metal-semiconductor-metal structure for the photodiode.

Silicon metal-semiconductor-metal photodetector

DOEpatents

Brueck, Steven R. J.; Myers, David R.; Sharma, Ashwani K.

1995-01-01

Silicon MSM photodiodes sensitive to radiation in the visible to near infrared spectral range are produced by altering the absorption characteristics of crystalline Si by ion implantation. The implantation produces a defected region below the surface of the silicon with the highest concentration of defects at its base which acts to reduce the contribution of charge carriers formed below the defected layer. The charge carriers generated by the radiation in the upper regions of the defected layer are very quickly collected between biased Schottky barrier electrodes which form a metal-semiconductor-metal structure for the photodiode.

GaAs photoconductive semiconductor switch

DOEpatents

Loubriel, Guillermo M.; Baca, Albert G.; Zutavern, Fred J.

1998-01-01

A high gain, optically triggered, photoconductive semiconductor switch (PCSS) implemented in GaAs as a reverse-biased pin structure with a passivation layer above the intrinsic GaAs substrate in the gap between the two electrodes of the device. The reverse-biased configuration in combination with the addition of the passivation layer greatly reduces surface current leakage that has been a problem for prior PCSS devices and enables employment of the much less expensive and more reliable DC charging systems instead of the pulsed charging systems that needed to be used with prior PCSS devices.

Computational discovery of ferromagnetic semiconducting single-layer CrSnTe 3

DOE PAGES

Zhuang, Houlong L.; Xie, Yu; Kent, P. R. C.; ...

2015-07-06

Despite many single-layer materials being reported in the past decade, few of them exhibit magnetism. Here we perform first-principles calculations using accurate hybrid density functional methods (HSE06) to predict that single-layer CrSnTe 3 (CST) is a ferromagnetic semiconductor, with band gaps of 0.9 and 1.2 eV for the majority and minority spin channels, respectively. We determine the Curie temperature as 170 K, significantly higher than that of single-layer CrSiTe 3 (90K) and CrGeTe 3 (130 K). This is due to the enhanced ionicity of the Sn-Te bond, which in turn increases the superexchange coupling between the magnetic Cr atoms. Wemore » further explore the mechanical and dynamical stability and strain response of this single-layer material for possible epitaxial growth. Lastly, our study provides an intuitive approach to understand and design novel single-layer magnetic semiconductors for a wide range of spintronics and energy applications.« less

Single-Layer Halide Perovskite Light-Emitting Diodes with Sub-Band Gap Turn-On Voltage and High Brightness.

PubMed

Li, Junqiang; Shan, Xin; Bade, Sri Ganesh R; Geske, Thomas; Jiang, Qinglong; Yang, Xin; Yu, Zhibin

2016-10-03

Charge-carrier injection into an emissive semiconductor thin film can result in electroluminescence and is generally achieved by using a multilayer device structure, which requires an electron-injection layer (EIL) between the cathode and the emissive layer and a hole-injection layer (HIL) between the anode and the emissive layer. The recent advancement of halide perovskite semiconductors opens up a new path to electroluminescent devices with a greatly simplified device structure. We report cesium lead tribromide light-emitting diodes (LEDs) without the aid of an EIL or HIL. These so-called single-layer LEDs have exhibited a sub-band gap turn-on voltage. The devices obtained a brightness of 591 197 cd m -2 at 4.8 V, with an external quantum efficiency of 5.7% and a power efficiency of 14.1 lm W -1 . Such an advancement demonstrates that very high efficiency of electron and hole injection can be obtained in perovskite LEDs even without using an EIL or HIL.

Conference on Semi-Insulating III-V Materials (2nd), held 19-21 Apr 82, Evian (France),

DTIC Science & Technology

1983-02-28

Dist Special 19. KEY WORDS (Continue on reverse side If neceary mud Identity by block numb ) Semiconductor devices Field effect transitors Integrated...doped GaAs sub- 4 strates. The results showed no The catalog of defects includes statistically significant differ- vacancies, interstitials, anti...orientation also had high level profiles of GaAs active transconductance. In addition,the statistical scatter-uni-layers and their correlation to o m

Application of nanomaterials in two-terminal resistive-switching memory devices

PubMed Central

Ouyang, Jianyong

2010-01-01

Nanometer materials have been attracting strong attention due to their interesting structure and properties. Many important practical applications have been demonstrated for nanometer materials based on their unique properties. This article provides a review on the fabrication, electrical characterization, and memory application of two-terminal resistive-switching devices using nanomaterials as the active components, including metal and semiconductor nanoparticles (NPs), nanotubes, nanowires, and graphenes. There are mainly two types of device architectures for the two-terminal devices with NPs. One has a triple-layer structure with a metal film sandwiched between two organic semiconductor layers, and the other has a single polymer film blended with NPs. These devices can be electrically switched between two states with significant different resistances, i.e. the ‘ON’ and ‘OFF’ states. These render the devices important application as two-terminal non-volatile memory devices. The electrical behavior of these devices can be affected by the materials in the active layer and the electrodes. Though the mechanism for the electrical switches has been in argument, it is generally believed that the resistive switches are related to charge storage on the NPs. Resistive switches were also observed on crossbars formed by nanotubes, nanowires, and graphene ribbons. The resistive switches are due to nanoelectromechanical behavior of the materials. The Coulombic interaction of transient charges on the nanomaterials affects the configurable gap of the crossbars, which results into significant change in current through the crossbars. These nanoelectromechanical devices can be used as fast-response and high-density memory devices as well. PMID:22110862

Fabricating porous silicon carbide

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

The formation of porous SiC occurs under electrochemical anodization. A sample of SiC is contacted electrically with nickel and placed into an electrochemical cell which cell includes a counter electrode and a reference electrode. The sample is encapsulated so that only a bare semiconductor surface is exposed. The electrochemical cell is filled with an HF electrolyte which dissolves the SiC electrochemically. A potential is applied to the semiconductor and UV light illuminates the surface of the semiconductor. By controlling the light intensity, the potential and the doping level, a porous layer is formed in the semiconductor and thus one produces porous SiC.

Coherent phonon optics in a chip with an electrically controlled active device.

PubMed

Poyser, Caroline L; Akimov, Andrey V; Campion, Richard P; Kent, Anthony J

2015-02-05

Phonon optics concerns operations with high-frequency acoustic waves in solid media in a similar way to how traditional optics operates with the light beams (i.e. photons). Phonon optics experiments with coherent terahertz and sub-terahertz phonons promise a revolution in various technical applications related to high-frequency acoustics, imaging, and heat transport. Previously, phonon optics used passive methods for manipulations with propagating phonon beams that did not enable their external control. Here we fabricate a phononic chip, which includes a generator of coherent monochromatic phonons with frequency 378 GHz, a sensitive coherent phonon detector, and an active layer: a doped semiconductor superlattice, with electrical contacts, inserted into the phonon propagation path. In the experiments, we demonstrate the modulation of the coherent phonon flux by an external electrical bias applied to the active layer. Phonon optics using external control broadens the spectrum of prospective applications of phononics on the nanometer scale.

Observation of High-Harmonic Generation from an Atomically Thin Semiconductor [Observation of High Harmonics from and Atomically Thin Semiconductor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Hanzhe; Li, Yilei; You, Yongsing

We report the observation of nonperturbative high-harmonic generation from monolayer MoS 2. Here, the yield is higher in monolayer compared to a single layer of the bulk, an effect attributed to strong electron-hole interactions in the monolayer.

Observation of High-Harmonic Generation from an Atomically Thin Semiconductor [Observation of High Harmonics from and Atomically Thin Semiconductor

DOE PAGES

Liu, Hanzhe; Li, Yilei; You, Yongsing; ...

2016-01-01

We report the observation of nonperturbative high-harmonic generation from monolayer MoS 2. Here, the yield is higher in monolayer compared to a single layer of the bulk, an effect attributed to strong electron-hole interactions in the monolayer.

Suppression of electron overflow in 370-nm InGaN/AlGaN ultraviolet light emitting diodes with different insertion layer thicknesses

NASA Astrophysics Data System (ADS)

Wang, C. K.; Wang, Y. W.; Chiou, Y. Z.; Chang, S. H.; Jheng, J. S.; Chang, S. P.; Chang, S. J.

2017-06-01

In this study, the properties of 370-nm InGaN/AlGaN ultraviolet light emitting diodes (UV LEDs) with different thicknesses of un-doped Al0.3Ga0.7N insertion layer (IL) between the last quantum barrier and electron blocking layer (EBL) have been numerically simulated by Advance Physical Model of Semiconductor Devices (APSYS). The results show that the LEDs using the high Al composition IL can effectively improve the efficiency droop, light output power, and internal quantum efficiency (IQE) compared to the original structure. The improvements of the optical properties are mainly attributed to the energy band discontinuity and offset created by IL, which increase the potential barrier height of conduction band to suppress the electron overflow from the active region to the p-side layer.

Ion traps fabricated in a CMOS foundry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mehta, K. K.; Ram, R. J.; Eltony, A. M.

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size.more » This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.« less

Investigation of semiconductor clad optical waveguides

NASA Technical Reports Server (NTRS)

Batchman, T. E.; Carson, R. F.

1985-01-01

A variety of techniques have been proposed for fabricating integrated optical devices using semiconductors, lithium niobate, and glasses as waveguides and substrates. The use of glass waveguides and their interaction with thin semiconductor cladding layers was studied. Though the interactions of these multilayer waveguide structures have been analyzed here using glass, they may be applicable to other types of materials as well. The primary reason for using glass is that it provides a simple, inexpensive way to construct waveguides and devices.

Measuring the lateral charge-carrier mobility in metal-insulator-semiconductor capacitors via Kelvin-probe.

PubMed

Milotti, Valeria; Pietsch, Manuel; Strunk, Karl-Philipp; Melzer, Christian

2018-01-01

We report a Kelvin-probe method to investigate the lateral charge-transport properties of semiconductors, most notably the charge-carrier mobility. The method is based on successive charging and discharging of a pre-biased metal-insulator-semiconductor stack by an alternating voltage applied to one edge of a laterally confined semiconductor layer. The charge carriers spreading along the insulator-semiconductor interface are directly measured by a Kelvin-probe, following the time evolution of the surface potential. A model is presented, describing the device response for arbitrary applied biases allowing the extraction of the lateral charge-carrier mobility from experimentally measured surface potentials. The method is tested using the organic semiconductor poly(3-hexylthiophene), and the extracted mobilities are validated through current voltage measurements on respective field-effect transistors. Our widely applicable approach enables robust measurements of the lateral charge-carrier mobility in semiconductors with weak impact from the utilized contact materials.

Measuring the lateral charge-carrier mobility in metal-insulator-semiconductor capacitors via Kelvin-probe

NASA Astrophysics Data System (ADS)

Milotti, Valeria; Pietsch, Manuel; Strunk, Karl-Philipp; Melzer, Christian

2018-01-01

We report a Kelvin-probe method to investigate the lateral charge-transport properties of semiconductors, most notably the charge-carrier mobility. The method is based on successive charging and discharging of a pre-biased metal-insulator-semiconductor stack by an alternating voltage applied to one edge of a laterally confined semiconductor layer. The charge carriers spreading along the insulator-semiconductor interface are directly measured by a Kelvin-probe, following the time evolution of the surface potential. A model is presented, describing the device response for arbitrary applied biases allowing the extraction of the lateral charge-carrier mobility from experimentally measured surface potentials. The method is tested using the organic semiconductor poly(3-hexylthiophene), and the extracted mobilities are validated through current voltage measurements on respective field-effect transistors. Our widely applicable approach enables robust measurements of the lateral charge-carrier mobility in semiconductors with weak impact from the utilized contact materials.

Centro-Apical Self-Organization of Organic Semiconductors in a Line-Printed Organic Semiconductor: Polymer Blend for One-Step Printing Fabrication of Organic Field-Effect Transistors

PubMed Central

Jin Lee, Su; Kim, Yong-Jae; Young Yeo, So; Lee, Eunji; Sun Lim, Ho; Kim, Min; Song, Yong-Won; Cho, Jinhan; Ah Lim, Jung

2015-01-01

Here we report the first demonstration for centro-apical self-organization of organic semiconductors in a line-printed organic semiconductor: polymer blend. Key feature of this work is that organic semiconductor molecules were vertically segregated on top of the polymer phase and simultaneously crystallized at the center of the printed line pattern after solvent evaporation without an additive process. The thickness and width of the centro-apically segregated organic semiconductor crystalline stripe in the printed blend pattern were controlled by varying the relative content of the organic semiconductors, printing speed, and solution concentrations. The centro-apical self-organization of organic semiconductor molecules in a printed polymer blend may be attributed to the combination of an energetically favorable vertical phase-separation and hydrodynamic fluids inside the droplet during solvent evaporation. Finally, a centro-apically phase-separated bilayer structure of organic semiconductor: polymer blend was successfully demonstrated as a facile method to form the semiconductor and dielectric layer for OFETs in one- step. PMID:26359068

Centro-Apical Self-Organization of Organic Semiconductors in a Line-Printed Organic Semiconductor: Polymer Blend for One-Step Printing Fabrication of Organic Field-Effect Transistors.

PubMed

Lee, Su Jin; Kim, Yong-Jae; Yeo, So Young; Lee, Eunji; Lim, Ho Sun; Kim, Min; Song, Yong-Won; Cho, Jinhan; Lim, Jung Ah

2015-09-11

Here we report the first demonstration for centro-apical self-organization of organic semiconductors in a line-printed organic semiconductor: polymer blend. Key feature of this work is that organic semiconductor molecules were vertically segregated on top of the polymer phase and simultaneously crystallized at the center of the printed line pattern after solvent evaporation without an additive process. The thickness and width of the centro-apically segregated organic semiconductor crystalline stripe in the printed blend pattern were controlled by varying the relative content of the organic semiconductors, printing speed, and solution concentrations. The centro-apical self-organization of organic semiconductor molecules in a printed polymer blend may be attributed to the combination of an energetically favorable vertical phase-separation and hydrodynamic fluids inside the droplet during solvent evaporation. Finally, a centro-apically phase-separated bilayer structure of organic semiconductor: polymer blend was successfully demonstrated as a facile method to form the semiconductor and dielectric layer for OFETs in one- step.

Lead Halide Perovskites as Charge Generation Layers for Electron Mobility Measurement in Organic Semiconductors.

PubMed

Love, John A; Feuerstein, Markus; Wolff, Christian M; Facchetti, Antonio; Neher, Dieter

2017-12-06

Hybrid lead halide perovskites are introduced as charge generation layers (CGLs) for the accurate determination of electron mobilities in thin organic semiconductors. Such hybrid perovskites have become a widely studied photovoltaic material in their own right, for their high efficiencies, ease of processing from solution, strong absorption, and efficient photogeneration of charge. Time-of-flight (ToF) measurements on bilayer samples consisting of the perovskite CGL and an organic semiconductor layer of different thickness are shown to be determined by the carrier motion through the organic material, consistent with the much higher charge carrier mobility in the perovskite. Together with the efficient photon-to-electron conversion in the perovskite, this high mobility imbalance enables electron-only mobility measurement on relatively thin application-relevant organic films, which would not be possible with traditional ToF measurements. This architecture enables electron-selective mobility measurements in single components as well as bulk-heterojunction films as demonstrated in the prototypical polymer/fullerene blends. To further demonstrate the potential of this approach, electron mobilities were measured as a function of electric field and temperature in an only 127 nm thick layer of a prototypical electron-transporting perylene diimide-based polymer, and found to be consistent with an exponential trap distribution of ca. 60 meV. Our study furthermore highlights the importance of high mobility charge transporting layers when designing perovskite solar cells.

Deposit heterogeneity and the dynamics of the organic semiconductors P3HT and PCBM solution under evaporation

NASA Astrophysics Data System (ADS)

Yu, H. P.; Luo, H.; Liu, T. T.; Jing, G. Y.

2015-04-01

The formation of organic semiconductor layer is the key procedure in the manufacture of organic photovoltaic solar cell, in which the natural evaporation of the solvent from the polymer solution plays the essential role for the conversion efficiency. Here, poly(3-hexylthiophene) (P3HT) and fullerene derivative [6,6]-phenyl-C61-butyric acid methyl ester (PCBM), as two types of semiconductor polymers, were selected as the active layer to form the deposit by drying the blend solution drops on the substrate. We explored the influences of droplet size and solute concentration on the homogeneity of the deposit. Additionally, the spatial distribution of molecular chains and grains and the instability of the droplet morphology during the drying were investigated. The results showed that the "coffee-ring" phenomenon occurred forming an annular deposit at the outermost edge and the width of the annular ring increased linearly with the concentration of the P3HT solution, until a saturation plateau is approached. On the other hand, the PCBM deposition presented a circular disk at low concentration, but displayed a sudden instability for an irregular perimeter at a critical concentration and there existed a second critical concentration above which the deposit exhibited the return of the stable circular shape. The results have an instructive impact on the performance of the device and the formation of fine structures during the process of printing, film preparation and painting.

Polarization-induced transport in organic field-effect transistors: the role of ferroelectric dielectrics

NASA Astrophysics Data System (ADS)

Guha, Suchismita; Laudari, Amrit

2017-08-01

The ferroelectric nature of polymer ferroelectrics such as poly(vinylidene fluoride) (PVDF) has been known for over 45 years. However, its role in interfacial transport in organic/polymeric field-effect transistors (FETs) is not that well understood. Dielectrics based on PVDF and its copolymers are a perfect test-bed for conducting transport studies where a systematic tuning of the dielectric constant with temperature may be achieved. The charge transport mechanism in an organic semiconductor often occurs at the intersection of band-like coherent motion and incoherent hopping through localized states. By choosing two small molecule organic semiconductors - pentacene and 6,13 bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) - along with a copolymer of PVDF (PVDF-TrFe) as the dielectric layer, the transistor characteristics are monitored as a function of temperature. A negative coefficient of carrier mobility is observed in TIPS-pentacene upwards of 200 K with the ferroelectric dielectric. In contrast, TIPS-pentacene FETs show an activated transport with non-ferroelectric dielectrics. Pentacene FETs, on the other hand, show a weak temperature dependence of the charge carrier mobility in the ferroelectric phase of PVDF-TrFE, which is attributed to polarization fluctuation driven transport resulting from a coupling of the charge carriers to the surface phonons of the dielectric layer. Further, we show that there is a strong correlation between the nature of traps in the organic semiconductor and interfacial transport in organic FETs, especially in the presence of a ferroelectric dielectric.

Resonant cavity light-emitting diodes based on dielectric passive cavity structures

NASA Astrophysics Data System (ADS)

Ledentsov, N.; Shchukin, V. A.; Kropp, J.-R.; Zschiedrich, L.; Schmidt, F.; Ledentsov, N. N.

2017-02-01

A novel design for high brightness planar technology light-emitting diodes (LEDs) and LED on-wafer arrays on absorbing substrates is proposed. The design integrates features of passive dielectric cavity deposited on top of an oxide- semiconductor distributed Bragg reflector (DBR), the p-n junction with a light emitting region is introduced into the top semiconductor λ/4 DBR period. A multilayer dielectric structure containing a cavity layer and dielectric DBRs is further processed by etching into a micrometer-scale pattern. An oxide-confined aperture is further amended for current and light confinement. We study the impact of the placement of the active region into the maximum or minimum of the optical field intensity and study an impact of the active region positioning on light extraction efficiency. We also study an etching profile composed of symmetric rings in the etched passive cavity over the light emitting area. The bottom semiconductor is an AlGaAs-AlAs multilayer DBR selectively oxidized with the conversion of the AlAs layers into AlOx to increase the stopband width preventing the light from entering the semiconductor substrate. The approach allows to achieve very high light extraction efficiency in a narrow vertical angle keeping the reasonable thermal and current conductivity properties. As an example, a micro-LED structure has been modeled with AlGaAs-AlAs or AlGaAs-AlOx DBRs and an active region based on InGaAlP quantum well(s) emitting in the orange spectral range at 610 nm. A passive dielectric SiO2 cavity is confined by dielectric Ta2O5/SiO2 and AlGaAs-AlOx DBRs. Cylindrically-symmetric structures with multiple ring patterns are modeled. It is demonstrated that the extraction coefficient of light to the air can be increased from 1.3% up to above 90% in a narrow vertical angle (full width at half maximum (FWHM) below 20°). For very small oxide-confined apertures 100nm the narrowing of the FWHM for light extraction can be reduced down to 5°. Consequently high efficiency high brightness arrays of micro-LEDs becomes possible. For single emitters the approach is particularly interesting for oscillator strength engineering allowing high speed data transmission and for single photonics applying single quantum dot (QD) emitters and allowing >90% coupling of the emission into single mode fiber. We also note that for longer wavelength ( 1300nm) QDs the thickness of the layers and surface patterns significantly increase allowing greatly reduced processing tolerances and applying further simplifications due to the possibility of using high contrast GaAs-AlOx DBRs.

Photon and carrier management design for nonplanar thin-film copper indium gallium diselenide photovoltaics

DOEpatents

Atwater, Harry A.; Callahan, Dennis; Bukowsky, Colton

2017-11-21

Photovoltaic structures are disclosed. The structures can comprise randomly or periodically structured layers, a dielectric layer to reduce back diffusion of charge carriers, and a metallic layer to reflect photons back towards the absorbing semiconductor layers. This design can increase efficiency of photovoltaic structures. The structures can be fabricated by nanoimprint.

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Sung Ju; Park, Min; Kang, Hojin

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibilitymore » in transition metal dichalcogenide (TMD)-based electronics.« less

Systems and methods for producing low work function electrodes

DOEpatents

Kippelen, Bernard; Fuentes-Hernandez, Canek; Zhou, Yinhua; Kahn, Antoine; Meyer, Jens; Shim, Jae Won; Marder, Seth R.

2015-07-07

According to an exemplary embodiment of the invention, systems and methods are provided for producing low work function electrodes. According to an exemplary embodiment, a method is provided for reducing a work function of an electrode. The method includes applying, to at least a portion of the electrode, a solution comprising a Lewis basic oligomer or polymer; and based at least in part on applying the solution, forming an ultra-thin layer on a surface of the electrode, wherein the ultra-thin layer reduces the work function associated with the electrode by greater than 0.5 eV. According to another exemplary embodiment of the invention, a device is provided. The device includes a semiconductor; at least one electrode disposed adjacent to the semiconductor and configured to transport electrons in or out of the semiconductor.

Theoretical study in carrier mobility of two-dimensional materials

NASA Astrophysics Data System (ADS)

Huang, R.

2017-09-01

Recently, the theoretical prediction on carrier mobility of two-dimensional (2D) materials has aroused wild attention. At present, there is still a large gap between the theoretical prediction and the device performance of the semiconductor based on the 2D layer semiconductor materials such as graphene. It is particularly important to theoretically design and screen the high-performance 2D layered semiconductor materials with suitable band gap and high carrier mobility. This paper introduces some 2D materials with fine properties and deduces the formula for mobility of the isotropic materials on the basis of the deformation potential theory and Fermic golden rule under acoustic phonon scattering conditions, and then discusses the carrier mobility of anisotropic materials with Dirac cones. We point out the misconceptions in the existing literature and discuss the correct ones.

Density functional theory study of bulk and single-layer magnetic semiconductor CrPS4

NASA Astrophysics Data System (ADS)

Zhuang, Houlong L.; Zhou, Jia

2016-11-01

Searching for two-dimensional (2D) materials with multifunctionality is one of the main goals of current research in 2D materials. Magnetism and semiconducting are certainly two desirable functional properties for a single 2D material. In line with this goal, here we report a density functional theory (DFT) study of bulk and single-layer magnetic semiconductor CrPS4. We find that the ground-state magnetic structure of bulk CrPS4 exhibits the A-type antiferromagnetic ordering, which transforms to ferromagnetic (FM) ordering in single-layer CrPS4. The calculated formation energy and phonon spectrum confirm the stability of single-layer CrPS4. The band gaps of FM single-layer CrPS4 calculated with a hybrid density functional are within the visible-light range. We also study the effects of FM ordering on the optical absorption spectra and band alignments for water splitting, indicating that single-layer CrPS4 could be a potential photocatalyst. Our work opens up ample opportunities of energy-related applications of single-layer CrPS4.

Rhenium Dichalcogenides: Layered Semiconductors with Two Vertical Orientations.

PubMed

Hart, Lewis; Dale, Sara; Hoye, Sarah; Webb, James L; Wolverson, Daniel

2016-02-10

The rhenium and technetium diselenides and disulfides are van der Waals layered semiconductors in some respects similar to more well-known transition metal dichalcogenides (TMD) such as molybdenum sulfide. However, their symmetry is lower, consisting only of an inversion center, so that turning a layer upside-down (that is, applying a C2 rotation about an in-plane axis) is not a symmetry operation, but reverses the sign of the angle between the two nonequivalent in-plane crystallographic axes. A given layer thus can be placed on a substrate in two symmetrically nonequivalent (but energetically similar) ways. This has consequences for the exploitation of the anisotropic properties of these materials in TMD heterostructures and is expected to lead to a new source of domain structure in large-area layer growth. We produced few-layer ReS2 and ReSe2 samples with controlled "up" or "down" orientations by micromechanical cleavage and we show how polarized Raman microscopy can be used to distinguish these two orientations, thus establishing Raman as an essential tool for the characterization of large-area layers.

Facet-Selective Epitaxy of Compound Semiconductors on Faceted Silicon Nanowires.

PubMed

Mankin, Max N; Day, Robert W; Gao, Ruixuan; No, You-Shin; Kim, Sun-Kyung; McClelland, Arthur A; Bell, David C; Park, Hong-Gyu; Lieber, Charles M

2015-07-08

Integration of compound semiconductors with silicon (Si) has been a long-standing goal for the semiconductor industry, as direct band gap compound semiconductors offer, for example, attractive photonic properties not possible with Si devices. However, mismatches in lattice constant, thermal expansion coefficient, and polarity between Si and compound semiconductors render growth of epitaxial heterostructures challenging. Nanowires (NWs) are a promising platform for the integration of Si and compound semiconductors since their limited surface area can alleviate such material mismatch issues. Here, we demonstrate facet-selective growth of cadmium sulfide (CdS) on Si NWs. Aberration-corrected transmission electron microscopy analysis shows that crystalline CdS is grown epitaxially on the {111} and {110} surface facets of the Si NWs but that the Si{113} facets remain bare. Further analysis of CdS on Si NWs grown at higher deposition rates to yield a conformal shell reveals a thin oxide layer on the Si{113} facet. This observation and control experiments suggest that facet-selective growth is enabled by the formation of an oxide, which prevents subsequent shell growth on the Si{113} NW facets. Further studies of facet-selective epitaxial growth of CdS shells on micro-to-mesoscale wires, which allows tuning of the lateral width of the compound semiconductor layer without lithographic patterning, and InP shell growth on Si NWs demonstrate the generality of our growth technique. In addition, photoluminescence imaging and spectroscopy show that the epitaxial shells display strong and clean band edge emission, confirming their high photonic quality, and thus suggesting that facet-selective epitaxy on NW substrates represents a promising route to integration of compound semiconductors on Si.

FIBER AND INTEGRATED OPTICS: Emission properties of graded-index corrugated waveguides with a metal or semiconductor coating

NASA Astrophysics Data System (ADS)

Ataya, B. A.; Osovitskiĭ, A. N.

1992-02-01

A numerical method was used to investigate the emission of TE-polarized light from a graded-index corrugated waveguide coated with a metal or semiconductor and either with or without a buffer layer. The main emission characteristics of these systems were analyzed. In the case of metallized dielectric structures an optimal corrugation depth was established for which the emitted power is a maximum. It was found that when the parameters of a structure with a buffer layer were correctly chosen and a highly reflective metal coating was used, practically all the power in the waveguide wave could be emitted along a specified direction. A structure with a buffer layer and an aluminum coating was investigated experimentally.

Phosphorus doping a semiconductor particle

DOEpatents

Stevens, G.D.; Reynolds, J.S.

1999-07-20

A method of phosphorus doping a semiconductor particle using ammonium phosphate is disclosed. A p-doped silicon sphere is mixed with a diluted solution of ammonium phosphate having a predetermined concentration. These spheres are dried with the phosphorus then being diffused into the sphere to create either a shallow or deep p-n junction. A good PSG glass layer is formed on the surface of the sphere during the diffusion process. A subsequent segregation anneal process is utilized to strip metal impurities from near the p-n junction into the glass layer. A subsequent HF strip procedure is then utilized to removed the PSG layer. Ammonium phosphate is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirement. 1 fig.

Phosphorous doping a semiconductor particle

DOEpatents

Stevens, Gary Don; Reynolds, Jeffrey Scott

1999-07-20

A method (10) of phosphorus doping a semiconductor particle using ammonium phosphate. A p-doped silicon sphere is mixed with a diluted solution of ammonium phosphate having a predetermined concentration. These spheres are dried (16, 18), with the phosphorus then being diffused (20) into the sphere to create either a shallow or deep p-n junction. A good PSG glass layer is formed on the surface of the sphere during the diffusion process. A subsequent segregation anneal process is utilized to strip metal impurities from near the p-n junction into the glass layer. A subsequent HF strip procedure is then utilized to removed the PSG layer. Ammonium phosphate is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirement.

Method of forming thermally stable high-resistivity regions in n-type indium phosphide by oxygen implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Thompson, P.E.; Dietrich, H.B.

1985-12-12

Objects of this invention are: to form high-temperature stable isolation regions in InP; to provide InP wafers that allow greater flexibility in the design and fabrication of discrete devices; to provide new and improved InP semiconductor devices in n-type InP; to provide high-resisitivity isolation regions in InP; to extend the usefulness of damage-induced isolation in n-type InP by making possible processes in which the isolation implantation precedes the alloying of ohmic contacts; and to provide n-type InP substrates without unwanted conductive layers. The above and other object are realized by an InP wafer comprising a S.I. InP substrate; a n-typemore » InP active layer disposed on the substrate; and oxygen ion implanted isolation regions disposed in the active layer. The S.I. InP dopant may comprise either Fe or Cr.« less

Semiconductor photoelectrochemistry

NASA Technical Reports Server (NTRS)

Buoncristiani, A. M.; Byvik, C. E.

1983-01-01

Semiconductor photoelectrochemical reactions are investigated. A model of the charge transport processes in the semiconductor, based on semiconductor device theory, is presented. It incorporates the nonlinear processes characterizing the diffusion and reaction of charge carriers in the semiconductor. The model is used to study conditions limiting useful energy conversion, specifically the saturation of current flow due to high light intensity. Numerical results describing charge distributions in the semiconductor and its effects on the electrolyte are obtained. Experimental results include: an estimate rate at which a semiconductor photoelectrode is capable of converting electromagnetic energy into chemical energy; the effect of cell temperature on the efficiency; a method for determining the point of zero zeta potential for macroscopic semiconductor samples; a technique using platinized titanium dioxide powders and ultraviolet radiation to produce chlorine, bromine, and iodine from solutions containing their respective ions; the photoelectrochemical properties of a class of layered compounds called transition metal thiophosphates; and a technique used to produce high conversion efficiency from laser radiation to chemical energy.

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors

PubMed Central

Matsushima, Toshinori; Sandanayaka, Atula S. D.; Esaki, Yu; Adachi, Chihaya

2015-01-01

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10–2 cm2/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm2/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost. PMID:26416434

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors.

PubMed

Matsushima, Toshinori; Sandanayaka, Atula S D; Esaki, Yu; Adachi, Chihaya

2015-09-29

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10(-2) cm(2)/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm(2)/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost.

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors

NASA Astrophysics Data System (ADS)

Matsushima, Toshinori; Sandanayaka, Atula S. D.; Esaki, Yu; Adachi, Chihaya

2015-09-01

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10-2 cm2/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm2/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost.

Highly Crystalline C8-BTBT Thin-Film Transistors by Lateral Homo-Epitaxial Growth on Printed Templates.

PubMed

Janneck, Robby; Pilet, Nicolas; Bommanaboyena, Satya Prakash; Watts, Benjamin; Heremans, Paul; Genoe, Jan; Rolin, Cedric

2017-11-01

Highly crystalline thin films of organic semiconductors offer great potential for fundamental material studies as well as for realizing high-performance, low-cost flexible electronics. The fabrication of these films directly on inert substrates is typically done by meniscus-guided coating techniques. The resulting layers show morphological defects that hinder charge transport and induce large device-to-device variability. Here, a double-step method for organic semiconductor layers combining a solution-processed templating layer and a lateral homo-epitaxial growth by a thermal evaporation step is reported. The epitaxial regrowth repairs most of the morphological defects inherent to meniscus-guided coatings. The resulting film is highly crystalline and features a mobility increased by a factor of three and a relative spread in device characteristics improved by almost half an order of magnitude. This method is easily adaptable to other coating techniques and offers a route toward the fabrication of high-performance, large-area electronics based on highly crystalline thin films of organic semiconductors. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

SiGe derivatization by spontaneous reduction of aryl diazonium salts

NASA Astrophysics Data System (ADS)

Girard, A.; Geneste, F.; Coulon, N.; Cardinaud, C.; Mohammed-Brahim, T.

2013-10-01

Germanium semiconductors have interesting properties for FET-based biosensor applications since they possess high surface roughness allowing the immobilization of a high amount of receptors on a small surface area. Since SiGe combined low cost of Si and intrinsic properties of Ge with high mobility carriers, we focused the study on this particularly interesting material. The comparison of the efficiency of a functionalization process involving the spontaneous reduction of diazonium salts is studied on Si(1 0 0), SiGe and Ge semiconductors. XPS analysis of the functionalized surfaces reveals the presence of a covalent grafted layer on all the substrates that was confirmed by AFM. Interestingly, the modified Ge derivatives have still higher surface roughness after derivatization. To support the estimated thickness by XPS, a step measurement of the organic layers is done by AFM or by profilometer technique after a O2 plasma etching of the functionalized layer. This original method is well-adapted to measure the thickness of thin organic films on rough substrates such as germanium. The analyses show a higher chemical grafting on SiGe substrates compared with Si and Ge semiconductors.

Pure silver ohmic contacts to N- and P- type gallium arsenide materials

DOEpatents

Hogan, Stephen J.

1986-01-01

Disclosed is an improved process for manufacturing gallium arsenide semiconductor devices having as its components an n-type gallium arsenide substrate layer and a p-type gallium arsenide diffused layer. The improved process comprises forming a pure silver ohmic contact to both the diffused layer and the substrate layer, wherein the n-type layer comprises a substantially low doping carrier concentration.

37 CFR 211.5 - Deposit of identifying material.

Code of Federal Regulations, 2010 CFR

2010-07-01

... perceptible representation of each layer of the mask work consisting of: (i) Sets of plastic color overlay... photograph of each layer of the work fixed in a semiconductor chip product. The visually perceptible... chip product. (c) Trade secret protection. Where specific layers of a mask work fixed in a...