Sample records for semiconductor device processing

  1. Unitary lens semiconductor device

    DOEpatents

    Lear, Kevin L.

    1997-01-01

    A unitary lens semiconductor device and method. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors.

  2. Unitary lens semiconductor device

    DOEpatents

    Lear, K.L.

    1997-05-27

    A unitary lens semiconductor device and method are disclosed. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors. 9 figs.

  3. Optical processing for semiconductor device fabrication

    NASA Technical Reports Server (NTRS)

    Sopori, Bhushan L.

    1994-01-01

    A new technique for semiconductor device processing is described that uses optical energy to produce local heating/melting in the vicinity of a preselected interface of the device. This process, called optical processing, invokes assistance of photons to enhance interface reactions such as diffusion and melting, as compared to the use of thermal heating alone. Optical processing is performed in a 'cold wall' furnace, and requires considerably lower energies than furnace or rapid thermal annealing. This technique can produce some device structures with unique properties that cannot be produced by conventional thermal processing. Some applications of optical processing involving semiconductor-metal interfaces are described.

  4. Methods of Measurement for Semiconductor Materials, Process Control, and Devices

    NASA Technical Reports Server (NTRS)

    Bullis, W. M. (Editor)

    1973-01-01

    The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

  5. Electroluminescent devices formed using semiconductor nanocrystals as an electron transport media and method of making such electroluminescent devices

    DOEpatents

    Alivisatos, A. Paul; Colvin, Vickie

    1996-01-01

    An electroluminescent device is described, as well as a method of making same, wherein the device is characterized by a semiconductor nanocrystal electron transport layer capable of emitting visible light in response to a voltage applied to the device. The wavelength of the light emitted by the device may be changed by changing either the size or the type of semiconductor nanocrystals used in forming the electron transport layer. In a preferred embodiment the device is further characterized by the capability of emitting visible light of varying wavelengths in response to changes in the voltage applied to the device. The device comprises a hole processing structure capable of injecting and transporting holes, and usually comprising a hole injecting layer and a hole transporting layer; an electron transport layer in contact with the hole processing structure and comprising one or more layers of semiconductor nanocrystals; and an electron injecting layer in contact with the electron transport layer for injecting electrons into the electron transport layer. The capability of emitting visible light of various wavelengths is principally based on the variations in voltage applied thereto, but the type of semiconductor nanocrystals used and the size of the semiconductor nanocrystals in the layers of semiconductor nanometer crystals may also play a role in color change, in combination with the change in voltage.

  6. Fabrication and performance of pressure-sensing device consisting of electret film and organic semiconductor

    NASA Astrophysics Data System (ADS)

    Kodzasa, Takehito; Nobeshima, Daiki; Kuribara, Kazunori; Uemura, Sei; Yoshida, Manabu

    2017-04-01

    We propose a new concept of a pressure-sensitive device that consists of an organic electret film and an organic semiconductor. This device exhibits high sensitivity and selectivity against various types of pressure. The sensing mechanism of this device originates from a modulation of the electric conductivity of the organic semiconductor film induced by the interaction between the semiconductor film and the charged electret film placed face to face. It is expected that a complicated sensor array will be fabricated by using a roll-to-roll manufacturing system, because this device can be prepared by an all-printing and simple lamination process without high-level positional adjustment for printing processes. This also shows that this device with a simple structure is suitable for application to a highly flexible device array sheet for an Internet of Things (IoT) or wearable sensing system.

  7. Architectures for Improved Organic Semiconductor Devices

    NASA Astrophysics Data System (ADS)

    Beck, Jonathan H.

    Advancements in the microelectronics industry have brought increasing performance and decreasing prices to a wide range of users. Conventional silicon-based electronics have followed Moore's law to provide an ever-increasing integrated circuit transistor density, which drives processing power, solid-state memory density, and sensor technologies. As shrinking conventional integrated circuits became more challenging, researchers began exploring electronics with the potential to penetrate new applications with a low price of entry: "Electronics everywhere." The new generation of electronics is thin, light, flexible, and inexpensive. Organic electronics are part of the new generation of thin-film electronics, relying on the synthetic flexibility of carbon molecules to create organic semiconductors, absorbers, and emitters which perform useful tasks. Organic electronics can be fabricated with low energy input on a variety of novel substrates, including inexpensive plastic sheets. The potential ease of synthesis and fabrication of organic-based devices means that organic electronics can be made at very low cost. Successfully demonstrated organic semiconductor devices include photovoltaics, photodetectors, transistors, and light emitting diodes. Several challenges that face organic semiconductor devices are low performance relative to conventional devices, long-term device stability, and development of new organic-compatible processes and materials. While the absorption and emission performance of organic materials in photovoltaics and light emitting diodes is extraordinarily high for thin films, the charge conduction mobilities are generally low. Building highly efficient devices with low-mobility materials is one challenge. Many organic semiconductor films are unstable during fabrication, storage, and operation due to reactions with water, oxygen and hydroxide. A final challenge facing organic electronics is the need for new processes and materials for electrodes, semiconductors and substrates compatible with low-temperature, flexible, and oxygenated and aromatic solvent-free fabrication. Materials and processes must be capable of future high volume production in order to enable low costs. In this thesis we explore several techniques to improve organic semiconductor device performance and enable new fabrication processes. In Chapter 2, I describe the integration of sub-optical-wavelength nanostructured electrodes that improve fill factor and power conversion efficiency in organic photovoltaic devices. Photovoltaic fill factor performance is one of the primary challenges facing organic photovoltaics because most organic semiconductors have poor charge mobility. Our electrical and optical measurements and simulations indicate that nanostructured electrodes improve charge extraction in organic photovoltaics. In Chapter 3, I describe a general method for maximizing the efficiency of organic photovoltaic devices by simultaneously optimizing light absorption and charge carrier collection. We analyze the potential benefits of light trapping strategies for maximizing the overall power conversion efficiency of organic photovoltaic devices. This technique may be used to improve organic photovoltaic materials with low absorption, or short exciton diffusion and carrier-recombination lengths, opening up the device design space. In Chapter 4, I describe a process for high-quality graphene transfer onto chemically sensitive, weakly interacting organic semiconductor thin-films. Graphene is a promising flexible and highly transparent electrode for organic electronics; however, transferring graphene films onto organic semiconductor devices was previously impossible. We demonstrate a new transfer technique based on an elastomeric stamp coated with an fluorinated polymer release layer. We fabricate three classes of organic semiconductor devices: field effect transistors without high temperature annealing, transparent organic light-emitting diodes, and transparent small-molecule organic photovoltaic devices.

  8. Suppressing molecular vibrations in organic semiconductors by inducing strain

    PubMed Central

    Kubo, Takayoshi; Häusermann, Roger; Tsurumi, Junto; Soeda, Junshi; Okada, Yugo; Yamashita, Yu; Akamatsu, Norihisa; Shishido, Atsushi; Mitsui, Chikahiko; Okamoto, Toshihiro; Yanagisawa, Susumu; Matsui, Hiroyuki; Takeya, Jun

    2016-01-01

    Organic molecular semiconductors are solution processable, enabling the growth of large-area single-crystal semiconductors. Improving the performance of organic semiconductor devices by increasing the charge mobility is an ongoing quest, which calls for novel molecular and material design, and improved processing conditions. Here we show a method to increase the charge mobility in organic single-crystal field-effect transistors, by taking advantage of the inherent softness of organic semiconductors. We compress the crystal lattice uniaxially by bending the flexible devices, leading to an improved charge transport. The mobility increases from 9.7 to 16.5 cm2 V−1 s−1 by 70% under 3% strain. In-depth analysis indicates that compressing the crystal structure directly restricts the vibration of the molecules, thus suppresses dynamic disorder, a unique mechanism in organic semiconductors. Since strain can be easily induced during the fabrication process, we expect our method to be exploited to build high-performance organic devices. PMID:27040501

  9. Suppressing molecular vibrations in organic semiconductors by inducing strain.

    PubMed

    Kubo, Takayoshi; Häusermann, Roger; Tsurumi, Junto; Soeda, Junshi; Okada, Yugo; Yamashita, Yu; Akamatsu, Norihisa; Shishido, Atsushi; Mitsui, Chikahiko; Okamoto, Toshihiro; Yanagisawa, Susumu; Matsui, Hiroyuki; Takeya, Jun

    2016-04-04

    Organic molecular semiconductors are solution processable, enabling the growth of large-area single-crystal semiconductors. Improving the performance of organic semiconductor devices by increasing the charge mobility is an ongoing quest, which calls for novel molecular and material design, and improved processing conditions. Here we show a method to increase the charge mobility in organic single-crystal field-effect transistors, by taking advantage of the inherent softness of organic semiconductors. We compress the crystal lattice uniaxially by bending the flexible devices, leading to an improved charge transport. The mobility increases from 9.7 to 16.5 cm(2) V(-1) s(-1) by 70% under 3% strain. In-depth analysis indicates that compressing the crystal structure directly restricts the vibration of the molecules, thus suppresses dynamic disorder, a unique mechanism in organic semiconductors. Since strain can be easily induced during the fabrication process, we expect our method to be exploited to build high-performance organic devices.

  10. Ferroelectrics for semiconductor devices

    NASA Astrophysics Data System (ADS)

    Sayer, M.; Wu, Z.; Vasant Kumar, C. V. R.; Amm, D. T.; Griswold, E. M.

    1992-11-01

    The technology for the implementation of the integration of thin film ferroelectrics with silicon processing for various devices is described, and factors affecting the integration of ferroelectric films with semiconductor processing are discussed. Consideration is also given to film properties, the properties of electrode materials and structures, and the phenomena of ferroelectric fatigue and aging. Particular attention is given to the nonmemory device application of ferroelectrics.

  11. Semiconductor structures having electrically insulating and conducting portions formed from an AlSb-alloy layer

    DOEpatents

    Spahn, Olga B.; Lear, Kevin L.

    1998-01-01

    A semiconductor structure. The semiconductor structure comprises a plurality of semiconductor layers formed on a substrate including at least one layer of a III-V compound semiconductor alloy comprising aluminum (Al) and antimony (Sb), with at least a part of the AlSb-alloy layer being chemically converted by an oxidation process to form superposed electrically insulating and electrically conducting portions. The electrically insulating portion formed from the AlSb-alloy layer comprises an oxide of aluminum (e.g. Al.sub.2 O.sub.3), while the electrically conducting portion comprises Sb. A lateral oxidation process allows formation of the superposed insulating and conducting portions below monocrystalline semiconductor layers for forming many different types of semiconductor structures having particular utility for optoelectronic devices such as light-emitting diodes, edge-emitting lasers, vertical-cavity surface-emitting lasers, photodetectors and optical modulators (waveguide and surface normal), and for electronic devices such as heterojunction bipolar transistors, field-effect transistors and quantum-effect devices. The invention is expected to be particularly useful for forming light-emitting devices for use in the 1.3-1.6 .mu.m wavelength range, with the AlSb-alloy layer acting to define an active region of the device and to effectively channel an electrical current therein for efficient light generation.

  12. Methods of measurement for semiconductor materials, process control, and devices

    NASA Technical Reports Server (NTRS)

    Bullis, W. M. (Editor)

    1972-01-01

    Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Accomplishments include the determination of the reasons for differences in measurements of transistor delay time, identification of an energy level model for gold-doped silicon, and the finding of evidence that it does not appear to be necessary for an ultrasonic bonding tool to grip the wire and move it across the substrate metallization to make the bond. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; measurement of thermal properties of semiconductor devices, delay time, and related carrier transport properties in junction devices, and noise properties of microwave diodes; and characterization of silicon nuclear radiation detectors.

  13. A stable solution-processed polymer semiconductor with record high-mobility for printed transistors

    PubMed Central

    Li, Jun; Zhao, Yan; Tan, Huei Shuan; Guo, Yunlong; Di, Chong-An; Yu, Gui; Liu, Yunqi; Lin, Ming; Lim, Suo Hon; Zhou, Yuhua; Su, Haibin; Ong, Beng S.

    2012-01-01

    Microelectronic circuits/arrays produced via high-speed printing instead of traditional photolithographic processes offer an appealing approach to creating the long-sought after, low-cost, large-area flexible electronics. Foremost among critical enablers to propel this paradigm shift in manufacturing is a stable, solution-processable, high-performance semiconductor for printing functionally capable thin-film transistors — fundamental building blocks of microelectronics. We report herein the processing and optimisation of solution-processable polymer semiconductors for thin-film transistors, demonstrating very high field-effect mobility, high on/off ratio, and excellent shelf-life and operating stabilities under ambient conditions. Exceptionally high-gain inverters and functional ring oscillator devices on flexible substrates have been demonstrated. This optimised polymer semiconductor represents a significant progress in semiconductor development, dispelling prevalent skepticism surrounding practical usability of organic semiconductors for high-performance microelectronic devices, opening up application opportunities hitherto functionally or economically inaccessible with silicon technologies, and providing an excellent structural framework for fundamental studies of charge transport in organic systems. PMID:23082244

  14. Single photon detection with self-quenching multiplication

    NASA Technical Reports Server (NTRS)

    Zheng, Xinyu (Inventor); Cunningham, Thomas J. (Inventor); Pain, Bedabrata (Inventor)

    2011-01-01

    A photoelectronic device and an avalanche self-quenching process for a photoelectronic device are described. The photoelectronic device comprises a nanoscale semiconductor multiplication region and a nanoscale doped semiconductor quenching structure including a depletion region and an undepletion region. The photoelectronic device can act as a single photon detector or a single carrier multiplier. The avalanche self-quenching process allows electrical field reduction in the multiplication region by movement of the multiplication carriers, thus quenching the avalanche.

  15. Coincident site lattice-matched growth of semiconductors on substrates using compliant buffer layers

    DOEpatents

    Norman, Andrew

    2016-08-23

    A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.

  16. Semiconductor technology program. Progress briefs

    NASA Technical Reports Server (NTRS)

    Bullis, W. M.

    1980-01-01

    Measurement technology for semiconductor materials, process control, and devices is reviewed. Activities include: optical linewidth and thermal resistance measurements; device modeling; dopant density profiles; resonance ionization spectroscopy; and deep level measurements. Standardized oxide charge terminology is also described.

  17. Electroless silver plating of the surface of organic semiconductors.

    PubMed

    Campione, Marcello; Parravicini, Matteo; Moret, Massimo; Papagni, Antonio; Schröter, Bernd; Fritz, Torsten

    2011-10-04

    The integration of nanoscale processes and devices demands fabrication routes involving rapid, cost-effective steps, preferably carried out under ambient conditions. The realization of the metal/organic semiconductor interface is one of the most demanding steps of device fabrication, since it requires mechanical and/or thermal treatments which increment costs and are often harmful in respect to the active layer. Here, we provide a microscopic analysis of a room temperature, electroless process aimed at the deposition of a nanostructured metallic silver layer with controlled coverage atop the surface of single crystals and thin films of organic semiconductors. This process relies on the reaction of aqueous AgF solutions with the nonwettable crystalline surface of donor-type organic semiconductors. It is observed that the formation of a uniform layer of silver nanoparticles can be accomplished within 20 min contact time. The electrical characterization of two-terminal devices performed before and after the aforementioned treatment shows that the metal deposition process is associated with a redox reaction causing the p-doping of the semiconductor. © 2011 American Chemical Society

  18. Low temperature junction growth using hot-wire chemical vapor deposition

    DOEpatents

    Wang, Qi; Page, Matthew; Iwaniczko, Eugene; Wang, Tihu; Yan, Yanfa

    2014-02-04

    A system and a process for forming a semi-conductor device, and solar cells (10) formed thereby. The process includes preparing a substrate (12) for deposition of a junction layer (14); forming the junction layer (14) on the substrate (12) using hot wire chemical vapor deposition; and, finishing the semi-conductor device.

  19. Semiconductors: In Situ Processing of Photovoltaic Devices

    NASA Technical Reports Server (NTRS)

    Curreri, Peter A.

    1998-01-01

    The possible processing of semiconductor photovoltaic devices is discussed. The requirements for lunar PV cells is reviewed, and the key challenges involved in their manufacturing are investigated. A schematic diagram of a passivated emitter and rear cell (PERC) is presented. The possible fabrication of large photovoltaic arrays in space from lunar materials is also discussed.

  20. Hetero-junction photovoltaic device and method of fabricating the device

    DOEpatents

    Aytug, Tolga; Christen, David K; Paranthaman, Mariappan Parans; Polat, Ozgur

    2014-02-10

    A hetero-junction device and fabrication method in which phase-separated n-type and p-type semiconductor pillars define vertically-oriented p-n junctions extending above a substrate. Semiconductor materials are selected for the p-type and n-type pillars that are thermodynamically stable and substantially insoluble in one another. An epitaxial deposition process is employed to form the pillars on a nucleation layer and the mutual insolubility drives phase separation of the materials. During the epitaxial deposition process, the orientation is such that the nucleation layer initiates propagation of vertical columns resulting in a substantially ordered, three-dimensional structure throughout the deposited material. An oxidation state of at least a portion of one of the p-type or the n-type semiconductor materials is altered relative to the other, such that the band-gap energy of the semiconductor materials differ with respect to stoichiometric compositions and the device preferentially absorbs particular selected bands of radiation.

  1. Semiconductor structures having electrically insulating and conducting portions formed from an AlSb-alloy layer

    DOEpatents

    Spahn, O.B.; Lear, K.L.

    1998-03-10

    The semiconductor structure comprises a plurality of semiconductor layers formed on a substrate including at least one layer of a III-V compound semiconductor alloy comprising aluminum (Al) and antimony (Sb), with at least a part of the AlSb-alloy layer being chemically converted by an oxidation process to form superposed electrically insulating and electrically conducting portions. The electrically insulating portion formed from the AlSb-alloy layer comprises an oxide of aluminum (e.g., Al{sub 2}O{sub 3}), while the electrically conducting portion comprises Sb. A lateral oxidation process allows formation of the superposed insulating and conducting portions below monocrystalline semiconductor layers for forming many different types of semiconductor structures having particular utility for optoelectronic devices such as light-emitting diodes, edge-emitting lasers, vertical-cavity surface-emitting lasers, photodetectors and optical modulators (waveguide and surface normal), and for electronic devices such as heterojunction bipolar transistors, field-effect transistors and quantum-effect devices. The invention is expected to be particularly useful for forming light-emitting devices for use in the 1.3--1.6 {mu}m wavelength range, with the AlSb-alloy layer acting to define an active region of the device and to effectively channel an electrical current therein for efficient light generation. 10 figs.

  2. Hydrogen ion microlithography

    DOEpatents

    Tsuo, Y. Simon; Deb, Satyen K.

    1990-01-01

    Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

  3. Room-temperature semiconductor heterostructure refrigeration

    NASA Astrophysics Data System (ADS)

    Chao, K. A.; Larsson, Magnus; Mal'shukov, A. G.

    2005-07-01

    With the proper design of semiconductor tunneling barrier structures, we can inject low-energy electrons via resonant tunneling, and take out high-energy electrons via a thermionic process. This is the operation principle of our semiconductor heterostructure refrigerator (SHR) without the need of applying a temperature gradient across the device. Even for the bad thermoelectric material AlGaAs, our calculation shows that at room temperature, the SHR can easily lower the temperature by 5-7K. Such devices can be fabricated with the present semiconductor technology. Besides its use as a kitchen refrigerator, the SHR can efficiently cool microelectronic devices.

  4. Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

    PubMed

    Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

    2015-01-14

    The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

  5. Tungsten coating for improved wear resistance and reliability of microelectromechanical devices

    DOEpatents

    Fleming, James G.; Mani, Seethambal S.; Sniegowski, Jeffry J.; Blewer, Robert S.

    2001-01-01

    A process is disclosed whereby a 5-50-nanometer-thick conformal tungsten coating can be formed over exposed semiconductor surfaces (e.g. silicon, germanium or silicon carbide) within a microelectromechanical (MEM) device for improved wear resistance and reliability. The tungsten coating is formed after cleaning the semiconductor surfaces to remove any organic material and oxide film from the surface. A final in situ cleaning step is performed by heating a substrate containing the MEM device to a temperature in the range of 200-600 .degree. C. in the presence of gaseous nitrogen trifluoride (NF.sub.3). The tungsten coating can then be formed by a chemical reaction between the semiconductor surfaces and tungsten hexafluoride (WF.sub.6) at an elevated temperature, preferably about 450.degree. C. The tungsten deposition process is self-limiting and covers all exposed semiconductor surfaces including surfaces in close contact. The present invention can be applied to many different types of MEM devices including microrelays, micromirrors and microengines. Additionally, the tungsten wear-resistant coating of the present invention can be used to enhance the hardness, wear resistance, electrical conductivity, optical reflectivity and chemical inertness of one or more semiconductor surfaces within a MEM device.

  6. Processes for multi-layer devices utilizing layer transfer

    DOEpatents

    Nielson, Gregory N; Sanchez, Carlos Anthony; Tauke-Pedretti, Anna; Kim, Bongsang; Cederberg, Jeffrey; Okandan, Murat; Cruz-Campa, Jose Luis; Resnick, Paul J

    2015-02-03

    A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device.

  7. Porous silicon carbide (SiC) semiconductor device

    NASA Technical Reports Server (NTRS)

    Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

    1994-01-01

    A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

  8. Non- contacting capacitive diagnostic device

    DOEpatents

    Ellison, Timothy

    2005-07-12

    A non-contacting capacitive diagnostic device includes a pulsed light source for producing an electric field in a semiconductor or photovoltaic device or material to be evaluated and a circuit responsive to the electric field. The circuit is not in physical contact with the device or material being evaluated and produces an electrical signal characteristic of the electric field produced in the device or material. The diagnostic device permits quality control and evaluation of semiconductor or photovoltaic device properties in continuous manufacturing processes.

  9. Semiconductor with protective surface coating and method of manufacture thereof. [Patent application

    DOEpatents

    Hansen, W.L.; Haller, E.E.

    1980-09-19

    Passivation of predominantly crystalline semiconductor devices is provided for by a surface coating of sputtered hydrogenated amorphous semiconductor material. Passivation of a radiation detector germanium diode, for example, is realized by sputtering a coating of amorphous germanium onto the etched and quenched diode surface in a low pressure atmosphere of hydrogen and argon. Unlike prior germanium diode semiconductor devices, which must be maintained in vacuum at cryogenic temperatures to avoid deterioration, a diode processed in the described manner may be stored in air at room temperature or otherwise exposed to a variety of environmental conditions. The coating compensates for pre-existing undesirable surface states as well as protecting the semiconductor device against future impregnation with impurities.

  10. Ferrite film growth on semiconductor substrates towards microwave and millimeter wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Chen, Z.; Harris, V. G.

    2012-10-01

    It is widely recognized that as electronic systems' operating frequency shifts to microwave and millimeter wave bands, the integration of ferrite passive devices with semiconductor solid state active devices holds significant advantages in improved miniaturization, bandwidth, speed, power and production costs, among others. Traditionally, ferrites have been employed in discrete bulk form, despite attempts to integrate ferrite as films within microwave integrated circuits. Technical barriers remain centric to the incompatibility between ferrite and semiconductor materials and their processing protocols. In this review, we present past and present efforts at ferrite integration with semiconductor platforms with the aim to identify the most promising paths to realizing the complete integration of on-chip ferrite and semiconductor devices, assemblies and systems.

  11. Hydrogen ion microlithography

    DOEpatents

    Tsuo, Y.S.; Deb, S.K.

    1990-10-02

    Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

  12. Method for depositing high-quality microcrystalline semiconductor materials

    DOEpatents

    Guha, Subhendu [Bloomfield Hills, MI; Yang, Chi C [Troy, MI; Yan, Baojie [Rochester Hills, MI

    2011-03-08

    A process for the plasma deposition of a layer of a microcrystalline semiconductor material is carried out by energizing a process gas which includes a precursor of the semiconductor material and a diluent with electromagnetic energy so as to create a plasma therefrom. The plasma deposits a layer of the microcrystalline semiconductor material onto the substrate. The concentration of the diluent in the process gas is varied as a function of the thickness of the layer of microcrystalline semiconductor material which has been deposited. Also disclosed is the use of the process for the preparation of an N-I-P type photovoltaic device.

  13. Methods of measurement for semiconductor materials, process control, and devices

    NASA Technical Reports Server (NTRS)

    Bullis, W. M. (Editor)

    1973-01-01

    This progress report describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices. Significant accomplishments during this reporting period include design of a plan to provide standard silicon wafers for four-probe resistivity measurements for the industry, publication of a summary report on the photoconductive decay method for measuring carrier lifetime, publication of a comprehensive review of the field of wire bond fabrication and testing, and successful completion of organizational activity leading to the establishment of a new group on quality and hardness assurance in ASTM Committee F-1 on Electronics. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers in silicon; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.

  14. Semiconductor technology program: Progress briefs

    NASA Technical Reports Server (NTRS)

    Galloway, K. F.; Scace, R. I.; Walters, E. J.

    1981-01-01

    Measurement technology for semiconductor materials, process control, and devices, is discussed. Silicon and silicon based devices are emphasized. Highlighted activities include semiinsulating GaAs characterization, an automatic scanning spectroscopic ellipsometer, linewidth measurement and coherence, bandgap narrowing effects in silicon, the evaluation of electrical linewidth uniformity, and arsenicomplanted profiles in silicon.

  15. Screenable contact structure and method for semiconductor devices

    DOEpatents

    Ross, Bernd

    1980-08-26

    An ink composition for deposition upon the surface of a semiconductor device to provide a contact area for connection to external circuitry is disclosed, the composition comprising an ink system containing a metal powder, a binder and vehicle, and a metal frit. The ink is screened onto the semiconductor surface in the desired pattern and is heated to a temperature sufficient to cause the metal frit to become liquid. The metal frit dissolves some of the metal powder and densifies the structure by transporting the dissolved metal powder in a liquid sintering process. The sintering process typically may be carried out in any type of atmosphere. A small amount of dopant or semiconductor material may be added to the ink systems to achieve particular results if desired.

  16. Optical systems fabricated by printing-based assembly

    DOEpatents

    Rogers, John; Nuzzo, Ralph; Meitl, Matthew; Menard, Etienne; Baca, Alfred J; Motala, Michael; Ahn, Jong-Hyun; Park, Sang-Il; Yu, Chang-Jae; Ko, Heung Cho; Stoykovich, Mark; Yoon, Jongseung

    2014-05-13

    Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

  17. Optical systems fabricated by printing-based assembly

    DOEpatents

    Rogers, John [Champaign, IL; Nuzzo, Ralph [Champaign, IL; Meitl, Matthew [Durham, NC; Menard, Etienne [Durham, NC; Baca, Alfred J [Urbana, IL; Motala, Michael [Champaign, IL; Ahn, Jong-Hyun [Suwon, KR; Park, Sang-II [Savoy, IL; Yu,; Chang-Jae, [Urbana, IL; Ko, Heung-Cho [Gwangju, KR; Stoykovich,; Mark, [Dover, NH; Yoon, Jongseung [Urbana, IL

    2011-07-05

    Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

  18. Optical systems fabricated by printing-based assembly

    DOEpatents

    Rogers, John; Nuzzo, Ralph; Meitl, Matthew; Menard, Etienne; Baca, Alfred; Motala, Michael; Ahn, Jong -Hyun; Park, Sang -Il; Yu, Chang -Jae; Ko, Heung Cho; Stoykovich, Mark; Yoon, Jongseung

    2015-08-25

    Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

  19. Optical systems fabricated by printing-based assembly

    DOEpatents

    Rogers, John; Nuzzo, Ralph; Meitl, Matthew; Menard, Etienne; Baca, Alfred; Motala, Michael; Ahn, Jong-Hyun; Park, Sang-Il; Yu, Chang-Jae; Ko, Heung Cho; Stoykovich, Mark; Yoon, Jongseung

    2017-03-21

    Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

  20. Clean graphene electrodes on organic thin-film devices via orthogonal fluorinated chemistry.

    PubMed

    Beck, Jonathan H; Barton, Robert A; Cox, Marshall P; Alexandrou, Konstantinos; Petrone, Nicholas; Olivieri, Giorgia; Yang, Shyuan; Hone, James; Kymissis, Ioannis

    2015-04-08

    Graphene is a promising flexible, highly transparent, and elementally abundant electrode for organic electronics. Typical methods utilized to transfer large-area films of graphene synthesized by chemical vapor deposition on metal catalysts are not compatible with organic thin-films, limiting the integration of graphene into organic optoelectronic devices. This article describes a graphene transfer process onto chemically sensitive organic semiconductor thin-films. The process incorporates an elastomeric stamp with a fluorinated polymer release layer that can be removed, post-transfer, via a fluorinated solvent; neither fluorinated material adversely affects the organic semiconductor materials. We used Raman spectroscopy, atomic force microscopy, and scanning electron microscopy to show that chemical vapor deposition graphene can be successfully transferred without inducing defects in the graphene film. To demonstrate our transfer method's compatibility with organic semiconductors, we fabricate three classes of organic thin-film devices: graphene field effect transistors without additional cleaning processes, transparent organic light-emitting diodes, and transparent small-molecule organic photovoltaic devices. These experiments demonstrate the potential of hybrid graphene/organic devices in which graphene is deposited directly onto underlying organic thin-film structures.

  1. Process waste assessment: Petroleum jelly removal from semiconductor die using trichloroethylene

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Curtin, D.P.

    The process analyzed involves non-production, laboratory environment use of trichloroethylene for the cleaning of semiconductor devices. The option selection centered on the replacement of the trichloroethylene with a non-hazardous material. This process waste assessment was performed as part of a pilot project.

  2. Germanium detector passivated with hydrogenated amorphous germanium

    DOEpatents

    Hansen, William L.; Haller, Eugene E.

    1986-01-01

    Passivation of predominantly crystalline semiconductor devices (12) is provided for by a surface coating (21) of sputtered hydrogenated amorphous semiconductor material. Passivation of a radiation detector germanium diode, for example, is realized by sputtering a coating (21) of amorphous germanium onto the etched and quenched diode surface (11) in a low pressure atmosphere of hydrogen and argon. Unlike prior germanium diode semiconductor devices (12), which must be maintained in vacuum at cryogenic temperatures to avoid deterioration, a diode processed in the described manner may be stored in air at room temperature or otherwise exposed to a variety of environmental conditions. The coating (21) compensates for pre-existing undesirable surface states as well as protecting the semiconductor device (12) against future impregnation with impurities.

  3. Solution processed molecular floating gate for flexible flash memories

    NASA Astrophysics Data System (ADS)

    Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

    2013-10-01

    Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

  4. Solution processed molecular floating gate for flexible flash memories

    PubMed Central

    Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

    2013-01-01

    Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

  5. Electronic-carrier-controlled photochemical etching process in semiconductor device fabrication

    DOEpatents

    Ashby, C.I.H.; Myers, D.R.; Vook, F.L.

    1988-06-16

    An electronic-carrier-controlled photochemical etching process for carrying out patterning and selective removing of material in semiconductor device fabrication includes the steps of selective ion implanting, photochemical dry etching, and thermal annealing, in that order. In the selective ion implanting step, regions of the semiconductor material in a desired pattern are damaged and the remainder of the regions of the material not implanted are left undamaged. The rate of recombination of electrons and holes is increased in the damaged regions of the pattern compared to undamaged regions. In the photochemical dry etching step which follows ion implanting step, the material in the undamaged regions of the semiconductor are removed substantially faster than in the damaged regions representing the pattern, leaving the ion-implanted, damaged regions as raised surface structures on the semiconductor material. After completion of photochemical dry etching step, the thermal annealing step is used to restore the electrical conductivity of the damaged regions of the semiconductor material.

  6. Electronic-carrier-controlled photochemical etching process in semiconductor device fabrication

    DOEpatents

    Ashby, Carol I. H.; Myers, David R.; Vook, Frederick L.

    1989-01-01

    An electronic-carrier-controlled photochemical etching process for carrying out patterning and selective removing of material in semiconductor device fabrication includes the steps of selective ion implanting, photochemical dry etching, and thermal annealing, in that order. In the selective ion implanting step, regions of the semiconductor material in a desired pattern are damaged and the remainder of the regions of the material not implanted are left undamaged. The rate of recombination of electrons and holes is increased in the damaged regions of the pattern compared to undamaged regions. In the photochemical dry etching step which follows ion implanting step, the material in the undamaged regions of the semiconductor are removed substantially faster than in the damaged regions representing the pattern, leaving the ion-implanted, damaged regions as raised surface structures on the semiconductor material. After completion of photochemical dry etching step, the thermal annealing step is used to restore the electrical conductivity of the damaged regions of the semiconductor material.

  7. Technological and organizational diversity and technical advance in the early history of the American semiconductor industry

    NASA Astrophysics Data System (ADS)

    Cohen, W.; Holbrook, D.; Klepper, S.

    1994-06-01

    This study examines the early years of the semiconductor industry and focuses on the roles played by different size firms in technologically innovative processes. A large and diverse pool of firms participated in the growth of the industry. Three related technological areas were chosen for in-depth analysis: integrated circuits, materials technology, and device packaging. Large business producing vacuum tubes dominated the early production of semiconductor devices. As the market for new devices grew during the 1950's, new firms were founded and existing firms from other industries, e.g. aircraft builders and instrument makers, began to pursue semiconductor electronics. Small firms began to cater to the emerging industry by supplying materials and equipment. These firms contributed to the development of certain aspects of one thousand firms that were playing some part in the semiconductor industry.

  8. The Physics of Semiconductors

    NASA Astrophysics Data System (ADS)

    Brennan, Kevin F.

    1999-02-01

    Modern fabrication techniques have made it possible to produce semiconductor devices whose dimensions are so small that quantum mechanical effects dominate their behavior. This book describes the key elements of quantum mechanics, statistical mechanics, and solid-state physics that are necessary in understanding these modern semiconductor devices. The author begins with a review of elementary quantum mechanics, and then describes more advanced topics, such as multiple quantum wells. He then disusses equilibrium and nonequilibrium statistical mechanics. Following this introduction, he provides a thorough treatment of solid-state physics, covering electron motion in periodic potentials, electron-phonon interaction, and recombination processes. The final four chapters deal exclusively with real devices, such as semiconductor lasers, photodiodes, flat panel displays, and MOSFETs. The book contains many homework exercises and is suitable as a textbook for electrical engineering, materials science, or physics students taking courses in solid-state device physics. It will also be a valuable reference for practicing engineers in optoelectronics and related areas.

  9. A hybrid life cycle inventory of nano-scale semiconductor manufacturing.

    PubMed

    Krishnan, Nikhil; Boyd, Sarah; Somani, Ajay; Raoux, Sebastien; Clark, Daniel; Dornfeld, David

    2008-04-15

    The manufacturing of modern semiconductor devices involves a complex set of nanoscale fabrication processes that are energy and resource intensive, and generate significant waste. It is important to understand and reduce the environmental impacts of semiconductor manufacturing because these devices are ubiquitous components in electronics. Furthermore, the fabrication processes used in the semiconductor industry are finding increasing application in other products, such as microelectromechanical systems (MEMS), flat panel displays, and photovoltaics. In this work we develop a library of typical gate-to-gate materials and energy requirements, as well as emissions associated with a complete set of fabrication process models used in manufacturing a modern microprocessor. In addition, we evaluate upstream energy requirements associated with chemicals and materials using both existing process life cycle assessment (LCA) databases and an economic input-output (EIO) model. The result is a comprehensive data set and methodology that may be used to estimate and improve the environmental performance of a broad range of electronics and other emerging applications that involve nano and micro fabrication.

  10. Fabrication of optically reflecting ohmic contacts for semiconductor devices

    DOEpatents

    Sopori, Bhushan L.

    1995-01-01

    A method is provided to produce a low-resistivity ohmic contact having high optical reflectivity on one side of a semiconductor device. The contact is formed by coating the semiconductor substrate with a thin metal film on the back reflecting side and then optically processing the wafer by illuminating it with electromagnetic radiation of a predetermined wavelength and energy level through the front side of the wafer for a predetermined period of time. This method produces a thin epitaxial alloy layer between the semiconductor substrate and the metal layer when a crystalline substrate is used. The alloy layer provides both a low-resistivity ohmic contact and high optical reflectance.

  11. Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction

    DOEpatents

    Tauke-Pedretti, Anna; Nielson, Gregory N; Cederberg, Jeffrey G; Cruz-Campa, Jose Luis

    2015-05-12

    A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.

  12. Methods of measurement for semiconductor materials, process control, and devices

    NASA Technical Reports Server (NTRS)

    Bullis, W. M. (Editor)

    1972-01-01

    Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Topics investigated include: measurements of transistor delay time; application of the infrared response technique to the study of radiation-damaged, lithium-drifted silicon detectors; and identification of a condition that minimizes wire flexure and reduces the failure rate of wire bonds in transistors and integrated circuits under slow thermal cycling conditions. Supplementary data concerning staff, standards committee activities, technical services, and publications are included as appendixes.

  13. Methods of measurement for semiconductor materials, process control, and devices

    NASA Technical Reports Server (NTRS)

    Bullis, W. M. (Editor)

    1971-01-01

    The development of methods of measurement for semiconductor materials, process control, and devices is discussed. The following subjects are also presented: (1) demonstration of the high sensitivity of the infrared response technique by the identification of gold in a germanium diode, (2) verification that transient thermal response is significantly more sensitive to the presence of voids in die attachment than steady-state thermal resistance, and (3) development of equipment for determining susceptibility of transistors to hot spot formation by the current-gain technique.

  14. Tuning charge carrier transport and optical birefringence in liquid-crystalline thin films: A new design space for organic light-emitting diodes.

    PubMed

    Keum, Chang-Min; Liu, Shiyi; Al-Shadeedi, Akram; Kaphle, Vikash; Callens, Michiel Koen; Han, Lu; Neyts, Kristiaan; Zhao, Hongping; Gather, Malte C; Bunge, Scott D; Twieg, Robert J; Jakli, Antal; Lüssem, Björn

    2018-01-15

    Liquid-crystalline organic semiconductors exhibit unique properties that make them highly interesting for organic optoelectronic applications. Their optical and electrical anisotropies and the possibility to control the alignment of the liquid-crystalline semiconductor allow not only to optimize charge carrier transport, but to tune the optical property of organic thin-film devices as well. In this study, the molecular orientation in a liquid-crystalline semiconductor film is tuned by a novel blading process as well as by different annealing protocols. The altered alignment is verified by cross-polarized optical microscopy and spectroscopic ellipsometry. It is shown that a change in alignment of the liquid-crystalline semiconductor improves charge transport in single charge carrier devices profoundly. Comparing the current-voltage characteristics of single charge carrier devices with simulations shows an excellent agreement and from this an in-depth understanding of single charge carrier transport in two-terminal devices is obtained. Finally, p-i-n type organic light-emitting diodes (OLEDs) compatible with vacuum processing techniques used in state-of-the-art OLEDs are demonstrated employing liquid-crystalline host matrix in the emission layer.

  15. Electronic Materials and Processing: Proceedings of the First Electronic Materials and Processing Congress Held in Conjunction with the 1988 World Materials Congress, Chicago, Illinois, USA, 24-30 September 1988

    DTIC Science & Technology

    1988-01-01

    usually be traced to a combination of new semiconductors one on top of the other, then concepts, materials, and device principles, the process is called...example, growth techniques. New combinations of compound semiconductors such as GaAs have an materials called heterostructures can be made intrinsically...of combinations of metals, have direct energy band gaps that facilitate semiconductor, and insulators. Quantum the efficient recombination of

  16. Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

    PubMed Central

    Long, Rathnait D.; McIntyre, Paul C.

    2012-01-01

    The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

  17. 40 CFR 63.7188 - What are my monitoring installation, operation, and maintenance requirements?

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... Semiconductor Manufacturing Compliance Requirements § 63.7188 What are my monitoring installation, operation... emissions of your semiconductor process vent through a closed vent system to a control device, you must...

  18. 40 CFR 63.7188 - What are my monitoring installation, operation, and maintenance requirements?

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... Semiconductor Manufacturing Compliance Requirements § 63.7188 What are my monitoring installation, operation... emissions of your semiconductor process vent through a closed vent system to a control device, you must...

  19. Method of producing strained-layer semiconductor devices via subsurface-patterning

    DOEpatents

    Dodson, Brian W.

    1993-01-01

    A method is described for patterning subsurface features in a semiconductor device, wherein the semiconductor device includes an internal strained layer. The method comprises creating a pattern of semiconductor material over the semiconductor device, the semiconductor material having a predetermined thickness which stabilizes areas of the strained semiconductor layer that lie beneath the pattern. Subsequently, a heating step is applied to the semiconductor device to cause a relaxation in areas of the strained layer which do not lie beneath the semiconductor material pattern, whereby dislocations result in the relaxed areas and impair electrical transport therethrough.

  20. Graded junction termination extensions for electronic devices

    NASA Technical Reports Server (NTRS)

    Merrett, J. Neil (Inventor); Isaacs-Smith, Tamara (Inventor); Sheridan, David C. (Inventor); Williams, John R. (Inventor)

    2006-01-01

    A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

  1. Graded junction termination extensions for electronic devices

    NASA Technical Reports Server (NTRS)

    Merrett, J. Neil (Inventor); Isaacs-Smith, Tamara (Inventor); Sheridan, David C. (Inventor); Williams, John R. (Inventor)

    2007-01-01

    A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

  2. Environmentally benign semiconductor processing for dielectric etch

    NASA Astrophysics Data System (ADS)

    Liao, Marci Yi-Ting

    Semiconductor processing requires intensive usage of chemicals, electricity, and water. Such intensive resource usage leaves a large impact on the environment. For instance, in Silicon Valley, the semiconductor industry is responsible for 80% of the hazardous waste sites contaminated enough to require government assistance. Research on environmentally benign semiconductor processing is needed to reduce the environmental impact of the semiconductor industry. The focus of this dissertation is on the environmental impact of one aspect of semiconductor processing: patterning of dielectric materials. Plasma etching of silicon dioxide emits perfluorocarbons (PFCs) gases, like C2F6 and CF4, into the atmosphere. These gases are super global warming/greenhouse gases because of their extremely long atmospheric lifetimes and excellent infrared absorption properties. We developed the first inductively coupled plasma (ICP) abatement device for destroying PFCs downstream of a plasma etcher. Destruction efficiencies of 99% and 94% can be obtained for the above mentioned PFCs, by using O 2 as an additive gas. Our results have lead to extensive modeling in academia as well as commercialization of the ICP abatement system. Dielectric patterning of hi-k materials for future device technology brings different environment challenges. The uncertainty of the hi-k material selection and the patterning method need to be addressed. We have evaluated the environmental impact of three different dielectric patterning methods (plasma etch, wet etch and chemical-mechanical polishing), as well as, the transistor device performances associated with the patterning methods. Plasma etching was found to be the most environmentally benign patterning method, which also gives the best device performance. However, the environmental concern for plasma etching is the possibility of cross-contamination from low volatility etch by-products. Therefore, mass transfer in a plasma etcher for a promising hi-k dielectric material, ZrO2, was studied. A novel cross-contamination sampling technique was developed, along with a mass transfer model.

  3. Growth and device processing of hexagonal boron nitride epilayers for thermal neutron and deep ultraviolet detectors

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Doan, T. C.; Li, J.; Lin, J. Y.

    2016-07-15

    Solid-state neutron detectors with high performance are highly sought after for the detection of fissile materials. However, direct-conversion neutron detectors based on semiconductors with a measureable efficiency have not been realized. We report here the first successful demonstration of a direct-conversion semiconductor neutron detector with an overall detection efficiency for thermal neutrons of 4% and a charge collection efficiency as high as 83%. The detector is based on a 2.7 μm thick {sup 10}B-enriched hexagonal boron nitride (h-BN) epitaxial layer. The results represent a significant step towards the realization of practical neutron detectors based on h-BN epilayers. Neutron detectors basedmore » on h-BN are expected to possess all the advantages of semiconductor devices including wafer-scale processing, compact size, light weight, and ability to integrate with other functional devices.« less

  4. Engineering charge transport by heterostructuring solution-processed semiconductors

    NASA Astrophysics Data System (ADS)

    Voznyy, Oleksandr; Sutherland, Brandon R.; Ip, Alexander H.; Zhitomirsky, David; Sargent, Edward H.

    2017-06-01

    Solution-processed semiconductor devices are increasingly exploiting heterostructuring — an approach in which two or more materials with different energy landscapes are integrated into a composite system. Heterostructured materials offer an additional degree of freedom to control charge transport and recombination for more efficient optoelectronic devices. By exploiting energetic asymmetry, rationally engineered heterostructured materials can overcome weaknesses, augment strengths and introduce emergent physical phenomena that are otherwise inaccessible to single-material systems. These systems see benefit and application in two distinct branches of charge-carrier manipulation. First, they influence the balance between excitons and free charges to enhance electron extraction in solar cells and photodetectors. Second, they promote radiative recombination by spatially confining electrons and holes, which increases the quantum efficiency of light-emitting diodes. In this Review, we discuss advances in the design and composition of heterostructured materials, consider their implementation in semiconductor devices and examine unexplored paths for future advancement in the field.

  5. Process for making photovoltaic devices and resultant product

    DOEpatents

    Foote, James B.; Kaake, Steven A. F.; Meyers, Peter V.; Nolan, James F.

    1996-07-16

    A process and apparatus (70) for making a large area photovoltaic device (22) that is capable of generating low cost electrical power. The apparatus (70) for performing the process includes an enclosure (126) providing a controlled environment in which an oven (156) is located. At least one and preferably a plurality of deposition stations (74,76,78) provide heated vapors of semiconductor material within the oven (156) for continuous elevated temperature deposition of semiconductor material on a sheet substrate (24) including a glass sheet (26) conveyed within the oven. The sheet substrate (24) is conveyed on a roller conveyor (184) within the oven (156) and the semiconductor material whose main layer (82) is cadmium telluride is deposited on an upwardly facing surface (28) of the substrate by each deposition station from a location within the oven above the roller conveyor. A cooling station (86) rapidly cools the substrate (24) after deposition of the semiconductor material thereon to strengthen the glass sheet of the substrate.

  6. Process for making photovoltaic devices and resultant product

    DOEpatents

    Foote, James B.; Kaake, Steven A. F.; Meyers, Peter V.; Nolan, James F.

    1995-11-28

    A process and apparatus (70) for making a large area photovoltaic device (22) that is capable of generating low cost electrical power. The apparatus (70) for performing the process includes an enclosure (126) providing a controlled environment in which an oven (156) is located. At least one and preferably a plurality of deposition stations (74,76,78) provide heated vapors of semiconductor material within the oven (156) for continuous elevated temperature deposition of semiconductor material on a sheet substrate (24) including a glass sheet (26) conveyed within the oven. The sheet substrate (24) is conveyed on a roller conveyor (184) within the oven (156) and the semiconductor material whose main layer (82) is cadmium telluride is deposited on an upwardly facing surface (28) of the substrate by each deposition station from a location within the oven above the roller conveyor. A cooling station (86) rapidly cools the substrate (24) after deposition of the semiconductor material thereon to strengthen the glass sheet of the substrate.

  7. Process for making photovoltaic devices and resultant product

    DOEpatents

    Foote, James B.; Kaake, Steven A. F.; Meyers, Peter V.; Nolan, James F.

    1993-09-28

    A process and apparatus (70) for making a large area photovoltaic device (22) that is capable of generating low cost electrical power. The apparatus (70) for performing the process includes an enclosure (126) providing a controlled environment in which an oven (156) is located. At least one and preferably a plurality of deposition stations (74,76,78) provide heated vapors of semiconductor material within the oven (156) for continuous elevated temperature deposition of semiconductor material on a sheet substrate (24) including a glass sheet (26) conveyed within the oven. The sheet substrate (24) is conveyed on a roller conveyor (184) within the oven (156) and the semiconductor material whose main layer (82) is cadmium telluride is deposited on an upwardly facing surface (28) of the substrate by each deposition station from a location within the oven above the roller conveyor. A cooling station (86) rapidly cools the substrate (24) after deposition of the semiconductor material thereon to strengthen the glass sheet of the substrate.

  8. Impurity gettering in semiconductors

    DOEpatents

    Sopori, B.L.

    1995-06-20

    A process for impurity gettering in a semiconductor substrate or device such as a silicon substrate or device is disclosed. The process comprises hydrogenating the substrate or device at the back side thereof with sufficient intensity and for a time period sufficient to produce a damaged back side. Thereafter, the substrate or device is illuminated with electromagnetic radiation at an intensity and for a time period sufficient to cause the impurities to diffuse to the back side and alloy with a metal there present to form a contact and capture the impurities. The impurity gettering process also can function to simultaneously passivate defects within the substrate or device, with the defects likewise diffusing to the back side for simultaneous passivation. Simultaneously, substantially all hydrogen-induced damage on the back side of the substrate or device is likewise annihilated. Also taught is an alternate process comprising thermal treatment after hydrogenation of the substrate or device at a temperature of from about 500 C to about 700 C for a time period sufficient to cause the impurities to diffuse to the damaged back side thereof for subsequent capture by an alloying metal. 1 fig.

  9. Impurity gettering in semiconductors

    DOEpatents

    Sopori, Bhushan L.

    1995-01-01

    A process for impurity gettering in a semiconductor substrate or device such as a silicon substrate or device. The process comprises hydrogenating the substrate or device at the back side thereof with sufficient intensity and for a time period sufficient to produce a damaged back side. Thereafter, the substrate or device is illuminated with electromagnetic radiation at an intensity and for a time period sufficient to cause the impurities to diffuse to the back side and alloy with a metal there present to form a contact and capture the impurities. The impurity gettering process also can function to simultaneously passivate defects within the substrate or device, with the defects likewise diffusing to the back side for simultaneous passivation. Simultaneously, substantially all hydrogen-induced damage on the back side of the substrate or device is likewise annihilated. Also taught is an alternate process comprising thermal treatment after hydrogenation of the substrate or device at a temperature of from about 500.degree. C. to about 700.degree. C. for a time period sufficient to cause the impurities to diffuse to the damaged back side thereof for subsequent capture by an alloying metal.

  10. Fabrication of optically reflecting ohmic contacts for semiconductor devices

    DOEpatents

    Sopori, B.L.

    1995-07-04

    A method is provided to produce a low-resistivity ohmic contact having high optical reflectivity on one side of a semiconductor device. The contact is formed by coating the semiconductor substrate with a thin metal film on the back reflecting side and then optically processing the wafer by illuminating it with electromagnetic radiation of a predetermined wavelength and energy level through the front side of the wafer for a predetermined period of time. This method produces a thin epitaxial alloy layer between the semiconductor substrate and the metal layer when a crystalline substrate is used. The alloy layer provides both a low-resistivity ohmic contact and high optical reflectance. 5 figs.

  11. Roadmap on semiconductor-cell biointerfaces

    NASA Astrophysics Data System (ADS)

    Tian, Bozhi; Xu, Shuai; Rogers, John A.; Cestellos-Blanco, Stefano; Yang, Peidong; Carvalho-de-Souza, João L.; Bezanilla, Francisco; Liu, Jia; Bao, Zhenan; Hjort, Martin; Cao, Yuhong; Melosh, Nicholas; Lanzani, Guglielmo; Benfenati, Fabio; Galli, Giulia; Gygi, Francois; Kautz, Rylan; Gorodetsky, Alon A.; Kim, Samuel S.; Lu, Timothy K.; Anikeeva, Polina; Cifra, Michal; Krivosudský, Ondrej; Havelka, Daniel; Jiang, Yuanwen

    2018-05-01

    This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world.

  12. 3D analysis of semiconductor devices: A combination of 3D imaging and 3D elemental analysis

    NASA Astrophysics Data System (ADS)

    Fu, Bianzhu; Gribelyuk, Michael A.

    2018-04-01

    3D analysis of semiconductor devices using a combination of scanning transmission electron microscopy (STEM) Z-contrast tomography and energy dispersive spectroscopy (EDS) elemental tomography is presented. 3D STEM Z-contrast tomography is useful in revealing the depth information of the sample. However, it suffers from contrast problems between materials with similar atomic numbers. Examples of EDS elemental tomography are presented using an automated EDS tomography system with batch data processing, which greatly reduces the data collection and processing time. 3D EDS elemental tomography reveals more in-depth information about the defect origin in semiconductor failure analysis. The influence of detector shadowing and X-rays absorption on the EDS tomography's result is also discussed.

  13. Controlling Molecular Doping in Organic Semiconductors.

    PubMed

    Jacobs, Ian E; Moulé, Adam J

    2017-11-01

    The field of organic electronics thrives on the hope of enabling low-cost, solution-processed electronic devices with mechanical, optoelectronic, and chemical properties not available from inorganic semiconductors. A key to the success of these aspirations is the ability to controllably dope organic semiconductors with high spatial resolution. Here, recent progress in molecular doping of organic semiconductors is summarized, with an emphasis on solution-processed p-type doped polymeric semiconductors. Highlighted topics include how solution-processing techniques can control the distribution, diffusion, and density of dopants within the organic semiconductor, and, in turn, affect the electronic properties of the material. Research in these areas has recently intensified, thanks to advances in chemical synthesis, improved understanding of charged states in organic materials, and a focus on relating fabrication techniques to morphology. Significant disorder in these systems, along with complex interactions between doping and film morphology, is often responsible for charge trapping and low doping efficiency. However, the strong coupling between doping, solubility, and morphology can be harnessed to control crystallinity, create doping gradients, and pattern polymers. These breakthroughs suggest a role for molecular doping not only in device function but also in fabrication-applications beyond those directly analogous to inorganic doping. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  14. Producing Silicon Carbide for Semiconductor Devices

    NASA Technical Reports Server (NTRS)

    Hsu, G. C.; Rohatgi, N. K.

    1986-01-01

    Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

  15. Achieving Optimal Self-Adaptivity for Dynamic Tuning of Organic Semiconductors through Resonance Engineering.

    PubMed

    Tao, Ye; Xu, Lijia; Zhang, Zhen; Chen, Runfeng; Li, Huanhuan; Xu, Hui; Zheng, Chao; Huang, Wei

    2016-08-03

    Current static-state explorations of organic semiconductors for optimal material properties and device performance are hindered by limited insights into the dynamically changed molecular states and charge transport and energy transfer processes upon device operation. Here, we propose a simple yet successful strategy, resonance variation-based dynamic adaptation (RVDA), to realize optimized self-adaptive properties in donor-resonance-acceptor molecules by engineering the resonance variation for dynamic tuning of organic semiconductors. Organic light-emitting diodes hosted by these RVDA materials exhibit remarkably high performance, with external quantum efficiencies up to 21.7% and favorable device stability. Our approach, which supports simultaneous realization of dynamically adapted and selectively enhanced properties via resonance engineering, illustrates a feasible design map for the preparation of smart organic semiconductors capable of dynamic structure and property modulations, promoting the studies of organic electronics from static to dynamic.

  16. Sintered silver joints via controlled topography of electronic packaging subcomponents

    DOEpatents

    Wereszczak, Andrew A.

    2014-09-02

    Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.

  17. The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

    NASA Technical Reports Server (NTRS)

    Bouldin, D. L.; Eastes, R. W.; Feltner, W. R.; Hollis, B. R.; Routh, D. E.

    1979-01-01

    The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

  18. High performance printed oxide field-effect transistors processed using photonic curing.

    PubMed

    Garlapati, Suresh Kumar; Marques, Gabriel Cadilha; Gebauer, Julia Susanne; Dehm, Simone; Bruns, Michael; Winterer, Markus; Tahoori, Mehdi Baradaran; Aghassi-Hagmann, Jasmin; Hahn, Horst; Dasgupta, Subho

    2018-06-08

    Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV-visible light and UV-laser), we demonstrate facile fabrication of high performance In 2 O 3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.

  19. High performance printed oxide field-effect transistors processed using photonic curing

    NASA Astrophysics Data System (ADS)

    Garlapati, Suresh Kumar; Cadilha Marques, Gabriel; Gebauer, Julia Susanne; Dehm, Simone; Bruns, Michael; Winterer, Markus; Baradaran Tahoori, Mehdi; Aghassi-Hagmann, Jasmin; Hahn, Horst; Dasgupta, Subho

    2018-06-01

    Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV–visible light and UV-laser), we demonstrate facile fabrication of high performance In2O3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.

  20. Reducing leakage current in semiconductor devices

    DOEpatents

    Lu, Bin; Matioli, Elison de Nazareth; Palacios, Tomas Apostol

    2018-03-06

    A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals.

  1. High mobility and high stability glassy metal-oxynitride materials and devices

    NASA Astrophysics Data System (ADS)

    Lee, Eunha; Kim, Taeho; Benayad, Anass; Hur, Jihyun; Park, Gyeong-Su; Jeon, Sanghun

    2016-04-01

    In thin film technology, future semiconductor and display products with high performance, high density, large area, and ultra high definition with three-dimensional functionalities require high performance thin film transistors (TFTs) with high stability. Zinc oxynitride, a composite of zinc oxide and zinc nitride, has been conceded as a strong substitute to conventional semiconductor film such as silicon and indium gallium zinc oxide due to high mobility value. However, zinc oxynitride has been suffered from poor reproducibility due to relatively low binding energy of nitrogen with zinc, resulting in the instability of composition and its device performance. Here we performed post argon plasma process on zinc oxynitride film, forming nano-crystalline structure in stable amorphous matrix which hampers the reaction of oxygen with zinc. Therefore, material properties and device performance of zinc oxynitride are greatly enhanced, exhibiting robust compositional stability even exposure to air, uniform phase, high electron mobility, negligible fast transient charging and low noise characteristics. Furthermore, We expect high mobility and high stability zinc oxynitride customized by plasma process to be applicable to a broad range of semiconductor and display devices.

  2. Growth of Bulk Wide Bandgap Semiconductor Crystals and Their Potential Applications

    NASA Technical Reports Server (NTRS)

    Chen, Kuo-Tong; Shi, Detang; Morgan, S. H.; Collins, W. Eugene; Burger, Arnold

    1997-01-01

    Developments in bulk crystal growth research for electro-optical devices in the Center for Photonic Materials and Devices since its establishment have been reviewed. Purification processes and single crystal growth systems employing physical vapor transport and Bridgman methods were assembled and used to produce high purity and superior quality wide bandgap materials such as heavy metal halides and II-VI compound semiconductors. Comprehensive material characterization techniques have been employed to reveal the optical, electrical and thermodynamic properties of crystals, and the results were used to establish improved material processing procedures. Postgrowth treatments such as passivation, oxidation, chemical etching and metal contacting during the X-ray and gamma-ray device fabrication process have also been investigated and low noise threshold with improved energy resolution has been achieved.

  3. Influence of material quality and process-induced defects on semiconductor device performance and yield

    NASA Technical Reports Server (NTRS)

    Porter, W. A.; Mckee, W. R.

    1974-01-01

    An overview of major causes of device yield degradation is presented. The relationships of device types to critical processes and typical defects are discussed, and the influence of the defect on device yield and performance is demonstrated. Various defect characterization techniques are described and applied. A correlation of device failure, defect type, and cause of defect is presented in tabular form with accompanying illustrations.

  4. A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

    NASA Astrophysics Data System (ADS)

    Shiota, Koki; Kai, Kazuho; Nagaoka, Shiro; Tsuji, Takuto; Wakahara, Akihiro; Rusop, Mohamad

    2016-07-01

    The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As the result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.

  5. Methods and devices for fabricating and assembling printable semiconductor elements

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne

    The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

  6. Methods and devices for fabricating and assembling printable semiconductor elements

    DOEpatents

    Nuzzo, Ralph G; Rogers, John A; Menard, Etienne; Lee, Keon Jae; Khang, Dahl-Young; Sun, Yugang; Meitl, Matthew; Zhu, Zhengtao

    2014-03-04

    The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

  7. Chemically Derivatized Semiconductor Photoelectrodes.

    ERIC Educational Resources Information Center

    Wrighton, Mark S.

    1983-01-01

    Deliberate modification of semiconductor photoelectrodes to improve durability and enhance rate of desirable interfacial redox processes is discussed for a variety of systems. Modification with molecular-based systems or with metals/metal oxides yields results indicating an important role for surface modification in devices for fundamental study…

  8. Imaging the motion of electrons in 2D semiconductor heterostructures

    NASA Astrophysics Data System (ADS)

    Dani, Keshav

    Technological progress since the late 20th century has centered on semiconductor devices, such as transistors, diodes, and solar cells. At the heart of these devices, is the internal motion of electrons through semiconductor materials due to applied electric fields or by the excitation of photocarriers. Imaging the motion of these electrons would provide unprecedented insight into this important phenomenon, but requires high spatial and temporal resolution. Current studies of electron dynamics in semiconductors are generally limited by the spatial resolution of optical probes, or by the temporal resolution of electronic probes. In this talk, we combine femtosecond pump-probe techniques with spectroscopic photoemission electron microscopy to image the motion of photoexcited electrons from high-energy to low-energy states in a 2D InSe/GaAs heterostructure exhibiting a type-II band alignment. At the instant of photoexcitation, energy-resolved photoelectron images reveal a highly non-equilibrium distribution of photocarriers in space and energy. Thereafter, in response to the out-of-equilibrium photocarriers, we observe the spatial redistribution of charges, thus forming internal electric fields, bending the semiconductor bands, and finally impeding further charge transfer. By assembling images taken at different time-delays, we make a movie lasting a few tens of picoseconds of the electron transfer process in the photoexcited type-II heterostructure - a fundamental phenomenon in semiconductor devices like solar cells. Quantitative analysis and theoretical modeling of spatial variations in the video provide insight into future solar cells, electron dynamics in 2D materials, and other semiconductor devices.

  9. Imaging the motion of electrons across semiconductor heterojunctions.

    PubMed

    Man, Michael K L; Margiolakis, Athanasios; Deckoff-Jones, Skylar; Harada, Takaaki; Wong, E Laine; Krishna, M Bala Murali; Madéo, Julien; Winchester, Andrew; Lei, Sidong; Vajtai, Robert; Ajayan, Pulickel M; Dani, Keshav M

    2017-01-01

    Technological progress since the late twentieth century has centred on semiconductor devices, such as transistors, diodes and solar cells. At the heart of these devices is the internal motion of electrons through semiconductor materials due to applied electric fields or by the excitation of photocarriers. Imaging the motion of these electrons would provide unprecedented insight into this important phenomenon, but requires high spatial and temporal resolution. Current studies of electron dynamics in semiconductors are generally limited by the spatial resolution of optical probes, or by the temporal resolution of electronic probes. Here, by combining femtosecond pump-probe techniques with spectroscopic photoemission electron microscopy, we imaged the motion of photoexcited electrons from high-energy to low-energy states in a type-II 2D InSe/GaAs heterostructure. At the instant of photoexcitation, energy-resolved photoelectron images revealed a highly non-equilibrium distribution of photocarriers in space and energy. Thereafter, in response to the out-of-equilibrium photocarriers, we observed the spatial redistribution of charges, thus forming internal electric fields, bending the semiconductor bands, and finally impeding further charge transfer. By assembling images taken at different time-delays, we produced a movie lasting a few trillionths of a second of the electron-transfer process in the photoexcited type-II heterostructure-a fundamental phenomenon in semiconductor devices such as solar cells. Quantitative analysis and theoretical modelling of spatial variations in the movie provide insight into future solar cells, 2D materials and other semiconductor devices.

  10. Imaging the motion of electrons across semiconductor heterojunctions

    NASA Astrophysics Data System (ADS)

    Man, Michael K. L.; Margiolakis, Athanasios; Deckoff-Jones, Skylar; Harada, Takaaki; Wong, E. Laine; Krishna, M. Bala Murali; Madéo, Julien; Winchester, Andrew; Lei, Sidong; Vajtai, Robert; Ajayan, Pulickel M.; Dani, Keshav M.

    2017-01-01

    Technological progress since the late twentieth century has centred on semiconductor devices, such as transistors, diodes and solar cells. At the heart of these devices is the internal motion of electrons through semiconductor materials due to applied electric fields or by the excitation of photocarriers. Imaging the motion of these electrons would provide unprecedented insight into this important phenomenon, but requires high spatial and temporal resolution. Current studies of electron dynamics in semiconductors are generally limited by the spatial resolution of optical probes, or by the temporal resolution of electronic probes. Here, by combining femtosecond pump-probe techniques with spectroscopic photoemission electron microscopy, we imaged the motion of photoexcited electrons from high-energy to low-energy states in a type-II 2D InSe/GaAs heterostructure. At the instant of photoexcitation, energy-resolved photoelectron images revealed a highly non-equilibrium distribution of photocarriers in space and energy. Thereafter, in response to the out-of-equilibrium photocarriers, we observed the spatial redistribution of charges, thus forming internal electric fields, bending the semiconductor bands, and finally impeding further charge transfer. By assembling images taken at different time-delays, we produced a movie lasting a few trillionths of a second of the electron-transfer process in the photoexcited type-II heterostructure—a fundamental phenomenon in semiconductor devices such as solar cells. Quantitative analysis and theoretical modelling of spatial variations in the movie provide insight into future solar cells, 2D materials and other semiconductor devices.

  11. Abatement of waste gases and water during the processes of semiconductor fabrication.

    PubMed

    Wen, Rui-mei; Liang, Jun-wu

    2002-10-01

    The purpose of this article is to examine the methods and equipment for abating waste gases and water produced during the manufacture of semiconductor materials and devices. Three separating methods and equipment are used to control three different groups of electronic wastes. The first group includes arsine and phosphine emitted during the processes of semiconductor materials manufacture. The abatement procedure for this group of pollutants consists of adding iodates, cupric and manganese salts to a multiple shower tower (MST) structure. The second group includes pollutants containing arsenic, phosphorus, HF, HCl, NO2, and SO3 emitted during the manufacture of semiconductor materials and devices. The abatement procedure involves mixing oxidants and bases in an oval column with a separator in the middle. The third group consists of the ions of As, P and heavy metals contained in the waste water. The abatement procedure includes adding CaCO3 and ferric salts in a flocculation-sedimentation compact device equipment. Test results showed that all waste gases and water after the abatement procedures presented in this article passed the discharge standards set by the State Environmental Protection Administration of China.

  12. Methods of producing free-standing semiconductors using sacrificial buffer layers and recyclable substrates

    DOEpatents

    Ptak, Aaron Joseph; Lin, Yong; Norman, Andrew; Alberi, Kirstin

    2015-05-26

    A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices. The low-defect density semiconductor materials produced using this method result in the enhanced performance of the semiconductor devices that incorporate the semiconductor materials.

  13. Defect Characterization, Imaging, and Control in Wide-Bandgap Semiconductors and Devices

    NASA Astrophysics Data System (ADS)

    Brillson, L. J.; Foster, G. M.; Cox, J.; Ruane, W. T.; Jarjour, A. B.; Gao, H.; von Wenckstern, H.; Grundmann, M.; Wang, B.; Look, D. C.; Hyland, A.; Allen, M. W.

    2018-03-01

    Wide-bandgap semiconductors are now leading the way to new physical phenomena and device applications at nanoscale dimensions. The impact of defects on the electronic properties of these materials increases as their size decreases, motivating new techniques to characterize and begin to control these electronic states. Leading these advances have been the semiconductors ZnO, GaN, and related materials. This paper highlights the importance of native point defects in these semiconductors and describes how a complement of spatially localized surface science and spectroscopy techniques in three dimensions can characterize, image, and begin to control these electronic states at the nanoscale. A combination of characterization techniques including depth-resolved cathodoluminescence spectroscopy, surface photovoltage spectroscopy, and hyperspectral imaging can describe the nature and distribution of defects at interfaces at both bulk and nanoscale surfaces, their metal interfaces, and inside nanostructures themselves. These features as well as temperature and mechanical strain inside wide-bandgap device structures at the nanoscale can be measured even while these devices are operating. These advanced capabilities enable several new directions for describing defects at the nanoscale, showing how they contribute to device degradation, and guiding growth processes to control them.

  14. Methods of measurement for semiconductor materials, process control, and devices

    NASA Technical Reports Server (NTRS)

    Bullis, W. M. (Editor)

    1972-01-01

    Significant accomplishments include development of a procedure to correct for the substantial differences of transistor delay time as measured with different instruments or with the same instrument at different frequencies; association of infrared response spectra of poor quality germanium gamma ray detectors with spectra of detectors fabricated from portions of a good crystal that had been degraded in known ways; and confirmation of the excellent quality and cosmetic appearance of ultrasonic bonds made with aluminum ribbon wire. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon, development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.

  15. Andreev reflection enhancement in semiconductor-superconductor structures

    NASA Astrophysics Data System (ADS)

    Bouscher, Shlomi; Winik, Roni; Hayat, Alex

    2018-02-01

    We develop a theoretical approach for modeling a wide range of semiconductor-superconductor structures with arbitrary potential barriers and a spatially dependent superconducting order parameter. We demonstrate asymmetry in the conductance spectrum as a result of a Schottky barrier shape. We further show that the Andreev reflection process can be significantly enhanced through resonant tunneling with appropriate barrier configuration, which can incorporate the Schottky barrier as a contributing component of the device. Moreover, we show that resonant tunneling can be achieved in superlattice structures as well. These theoretically demonstrated effects along with our modeling approach enable much more efficient Cooper pair injection into semiconductor-superconductor structures, including superconducting optoelectronic devices.

  16. Method of Manufacturing a Light Emitting, Photovoltaic or Other Electronic Apparatus and System

    NASA Technical Reports Server (NTRS)

    Blanchard, Richard A. (Inventor); Lewandowski, Mark Allan (Inventor); Frazier, Donald Odell (Inventor); Ray, William Johnstone (Inventor); Fuller, Kirk A. (Inventor); Lowenthal, Mark David (Inventor); Shotton, Neil O. (Inventor)

    2014-01-01

    The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

  17. Method of manufacturing a light emitting, photovoltaic or other electronic apparatus and system

    NASA Technical Reports Server (NTRS)

    Fuller, Kirk A. (Inventor); Frazier, Donald Odell (Inventor); Blanchard, Richard A. (Inventor); Lowenthal, Mark D. (Inventor); Lewandowski, Mark Allan (Inventor); Ray, William Johnstone (Inventor); Shotton, Neil O. (Inventor)

    2012-01-01

    The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

  18. Semiconductor nanowire thermoelectric materials and devices, and processes for producing same

    DOEpatents

    Lagally, Max G; Evans, Paul G; Ritz, Clark S

    2013-09-17

    The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic compositional longitudinal modulation. The nanowires are constructed using lithographic techniques from thin semiconductor membranes, or "nanomembranes."

  19. Semiconductor nanowire thermoelectric materials and devices, and processes for producing same

    DOEpatents

    Lagally, Max G.; Evans, Paul G.; Ritz, Clark S.

    2015-11-17

    The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic compositional longitudinal modulation. The nanowires are constructed using lithographic techniques from thin semiconductor membranes, or "nanomembranes."

  20. Apparatus for making photovoltaic devices

    DOEpatents

    Foote, James B.; Kaake, Steven A. F.; Meyers, Peter V.; Nolan, James F.

    1994-12-13

    A process and apparatus (70) for making a large area photovoltaic device (22) that is capable of generating low cost electrical power. The apparatus (70) for performing the process includes an enclosure (126) providing a controlled environment in which an oven (156) is located. At least one and preferably a plurality of deposition stations (74,76,78) provide heated vapors of semiconductor material within the oven (156) for continuous elevated temperature deposition of semiconductor material on a sheet substrate (24) including a glass sheet (26) conveyed within the oven. The sheet substrate (24) is conveyed on a roller conveyor (184) within the oven (156) and the semiconductor material whose main layer (82) is cadmium telluride is deposited on an upwardly facing surface (28) of the substrate by each deposition station from a location within the oven above the roller conveyor. A cooling station (86) rapidly cools the substrate (24) after deposition of the semiconductor material thereon to strengthen the glass sheet of the substrate.

  1. The rates of charge separation and energy destructive charge recombination processes within an organic dyad in presence of metal-semiconductor core shell nanocomposites.

    PubMed

    Mandal, Gopa; Bhattacharya, Sudeshna; Das, Subrata; Ganguly, Tapan

    2012-01-01

    Steady state and time resolved spectroscopic measurements were made at the ambient temperature on an organic dyad, 1-(4-Chloro-phenyl)-3-(4-methoxy-naphthalen-1-yl)-propenone (MNCA), where the donor 1-methoxynaphthalene (1 MNT) is connected with the acceptor p-chloroacetophenone (PCA) by an unsaturated olefinic bond, in presence of Ag@TiO2 nanoparticles. Time resolved fluorescence and absorption measurements reveal that the rate parameters associated with charge separation, k(CS), within the dyad increases whereas charge recombination rate k(CR) reduces significantly when the surrounding medium is changed from only chloroform to mixture of chloroform and Ag@TiO2 (noble metal-semiconductor) nanocomposites. The observed results indicate that the dyad being combined with core-shell nanocomposites may form organic-inorganic nanocomposite system useful for developing light energy conversion devices. Use of metal-semiconductor nanoparticles may provide thus new ways to modulate charge recombination processes in light energy conversion devices. From comparison with the results obtained in our earlier investigations with only TiO2 nanoparticles, it is inferred that much improved version of light energy conversion device, where charge-separated species could be protected for longer period of time of the order of millisecond, could be designed by using metal-semiconductor core-shell nanocomposites rather than semiconductor nanoparticles only.

  2. Heavy-ion induced single-event upset in integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1991-01-01

    The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

  3. Electrical Characterization of Semiconductor Materials and Devices

    NASA Astrophysics Data System (ADS)

    Deen, M.; Pascal, Fabien

    Semiconductor materials and devices continue to occupy a preeminent technological position due to their importance when building integrated electronic systems used in a wide range of applications from computers, cell-phones, personal digital assistants, digital cameras and electronic entertainment systems, to electronic instrumentation for medical diagnositics and environmental monitoring. Key ingredients of this technological dominance have been the rapid advances made in the quality and processing of materials - semiconductors, conductors and dielectrics - which have given metal oxide semiconductor device technology its important characteristics of negligible standby power dissipation, good input-output isolation, surface potential control and reliable operation. However, when assessing material quality and device reliability, it is important to have fast, nondestructive, accurate and easy-to-use electrical characterization techniques available, so that important parameters such as carrier doping density, type and mobility of carriers, interface quality, oxide trap density, semiconductor bulk defect density, contact and other parasitic resistances and oxide electrical integrity can be determined. This chapter describes some of the more widely employed and popular techniques that are used to determine these important parameters. The techniques presented in this chapter range in both complexity and test structure requirements from simple current-voltage measurements to more sophisticated low-frequency noise, charge pumping and deep-level transient spectroscopy techniques.

  4. Technology development of high-quality semiconductor devices using solution-processed crystallization of pentacene

    NASA Astrophysics Data System (ADS)

    Liu, Hung-Wei

    Organic electronic materials and processing techniques have attracted considerable attention for developing organic thin-film transistors (OTFTs), since they may be patterned on flexible substrates which may be bent into a variety of shapes for applications such as displays, smart cards, solar devices and sensors Various fabrication methods for building pentacene-based OTFTs have been demonstrated. Traditional vacuum deposition and vapor deposition methods have been studied for deposition on plastic and paper, but these are unlikely to scale well to large area printing. Researchers have developed methods for processing OTFTs from solution because of the potential for low-cost and large area device manufacturing, such as through inkjet or offset printing. Most methods require the use of precursors which are used to make pentacene soluble, and these methods have typically produced much lower carrier mobility than the best vacuum deposited devices. We have investigated devices built from solution-processed pentacene that is locally crystallized at room temperature on the polymer substrates. Pentacene crystals grown in this manner are highly localized at pre-determined sites, have good crystallinity and show good carrier mobility, making this an attractive method for large area manufacturing of semiconductor devices.

  5. Process for leveling film surfaces and products thereof

    DOEpatents

    Birkmire, R.W.; McCandless, B.E.

    1990-03-20

    Semiconductor films and photovoltaic devices prepared therefrom are provided wherein the semiconductor films have a specular surface with a texture less than about 0.25 micron greater than the average planar film surface and wherein the semiconductor films are surface modified by exposing the surface to an aqueous solution of bromine containing an acid or salt and continuing such exposure for a time sufficient to etch the surface. 8 figs.

  6. Using the scanning electron microscope on the production line to assure quality semiconductors

    NASA Technical Reports Server (NTRS)

    Adolphsen, J. W.; Anstead, R. J.

    1972-01-01

    The use of the scanning electron microscope to detect metallization defects introduced during batch processing of semiconductor devices is discussed. A method of determining metallization integrity was developed which culminates in a procurement specification using the scanning microscope on the production line as a quality control tool. Batch process control of the metallization operation is monitored early in the manufacturing cycle.

  7. Advanced 3-V semiconductor technology assessment

    NASA Technical Reports Server (NTRS)

    Nowogrodzki, M.

    1983-01-01

    Components required for extensions of currently planned space communications systems are discussed for large antennas, crosslink systems, single sideband systems, Aerostat systems, and digital signal processing. Systems using advanced modulation concepts and new concepts in communications satellites are included. The current status and trends in materials technology are examined with emphasis on bulk growth of semi-insulating GaAs and InP, epitaxial growth, and ion implantation. Microwave solid state discrete active devices, multigigabit rate GaAs digital integrated circuits, microwave integrated circuits, and the exploratory development of GaInAs devices, heterojunction devices, and quasi-ballistic devices is considered. Competing technologies such as RF power generation, filter structures, and microwave circuit fabrication are discussed. The fundamental limits of semiconductor devices and problems in implementation are explored.

  8. Fully Solution-Processed Flexible Organic Thin Film Transistor Arrays with High Mobility and Exceptional Uniformity

    PubMed Central

    Fukuda, Kenjiro; Takeda, Yasunori; Mizukami, Makoto; Kumaki, Daisuke; Tokito, Shizuo

    2014-01-01

    Printing fully solution-processed organic electronic devices may potentially revolutionize production of flexible electronics for various applications. However, difficulties in forming thin, flat, uniform films through printing techniques have been responsible for poor device performance and low yields. Here, we report on fully solution-processed organic thin-film transistor (TFT) arrays with greatly improved performance and yields, achieved by layering solution-processable materials such as silver nanoparticle inks, organic semiconductors, and insulating polymers on thin plastic films. A treatment layer improves carrier injection between the source/drain electrodes and the semiconducting layer and dramatically reduces contact resistance. Furthermore, an organic semiconductor with large-crystal grains results in TFT devices with shorter channel lengths and higher field-effect mobilities. We obtained mobilities of over 1.2 cm2 V−1 s−1 in TFT devices with channel lengths shorter than 20 μm. By combining these fabrication techniques, we built highly uniform organic TFT arrays with average mobility levels as high as 0.80 cm2 V−1 s−1 and ideal threshold voltages of 0 V. These results represent major progress in the fabrication of fully solution-processed organic TFT device arrays. PMID:24492785

  9. High efficiency, low cost, thin film silicon solar cell design and method for making

    DOEpatents

    Sopori, Bhushan L.

    2001-01-01

    A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

  10. High efficiency low cost thin film silicon solar cell design and method for making

    DOEpatents

    Sopori, Bhushan L.

    1999-01-01

    A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

  11. Solution-Processed Wide-Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field-Effect Transistor Memory.

    PubMed

    Li, Wen; Guo, Fengning; Ling, Haifeng; Liu, Hui; Yi, Mingdong; Zhang, Peng; Wang, Wenjun; Xie, Linghai; Huang, Wei

    2018-01-01

    In this paper, the development of organic field-effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide-bandgap (WBG) small-molecule organic semiconductor material [2-(9-(4-(octyloxy)phenyl)-9H-fluoren-2-yl)thiophene]3 (WG 3 ) is reported. The WG 3 NSs are prepared from phase separation by spin-coating blend solutions of WG 3 /trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG 3 film, the device based on WG 3 NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10 4 s), and reliable switching properties. A quantitative study of the WG 3 NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge-exciton annihilation efficiency induced by increased contact area between the WG 3 NSs and pentacene layer. This versatile solution-processing approach to preparing WG 3 NSs arrays as charge trapping sites allows for fabrication of high-performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. Mechanical Properties of Organic Semiconductors for Stretchable, Highly Flexible, and Mechanically Robust Electronics.

    PubMed

    Root, Samuel E; Savagatrup, Suchol; Printz, Adam D; Rodriquez, Daniel; Lipomi, Darren J

    2017-05-10

    Mechanical deformability underpins many of the advantages of organic semiconductors. The mechanical properties of these materials are, however, diverse, and the molecular characteristics that permit charge transport can render the materials stiff and brittle. This review is a comprehensive description of the molecular and morphological parameters that govern the mechanical properties of organic semiconductors. Particular attention is paid to ways in which mechanical deformability and electronic performance can coexist. The review begins with a discussion of flexible and stretchable devices of all types, and in particular the unique characteristics of organic semiconductors. It then discusses the mechanical properties most relevant to deformable devices. In particular, it describes how low modulus, good adhesion, and absolute extensibility prior to fracture enable robust performance, along with mechanical "imperceptibility" if worn on the skin. A description of techniques of metrology precedes a discussion of the mechanical properties of three classes of organic semiconductors: π-conjugated polymers, small molecules, and composites. The discussion of each class of materials focuses on molecular structure and how this structure (and postdeposition processing) influences the solid-state packing structure and thus the mechanical properties. The review concludes with applications of organic semiconductor devices in which every component is intrinsically stretchable or highly flexible.

  13. Efficient p-n junction-based thermoelectric generator that can operate at extreme temperature conditions

    NASA Astrophysics Data System (ADS)

    Chavez, Ruben; Angst, Sebastian; Hall, Joseph; Maculewicz, Franziska; Stoetzel, Julia; Wiggers, Hartmut; Thanh Hung, Le; Van Nong, Ngo; Pryds, Nini; Span, Gerhard; Wolf, Dietrich E.; Schmechel, Roland; Schierning, Gabi

    2018-01-01

    In many industrial processes, a large proportion of energy is lost in the form of heat. Thermoelectric generators can convert this waste heat into electricity by means of the Seebeck effect. However, the use of thermoelectric generators in practical applications on an industrial scale is limited in part because electrical, thermal, and mechanical bonding contacts between the semiconductor materials and the metal electrodes in current designs are not capable of withstanding thermal-mechanical stress and alloying of the metal-semiconductor interface when exposed to the high temperatures occurring in many real-world applications. Here we demonstrate a concept for thermoelectric generators that can address this issue by replacing the metallization and electrode bonding on the hot side of the device by a p-n junction between the two semiconductor materials, making the device robust against temperature induced failure. In our proof-of-principle demonstration, a p-n junction device made from nanocrystalline silicon is at least comparable in its efficiency and power output to conventional devices of the same material and fabrication process, but with the advantage of sustaining high hot side temperatures and oxidative atmosphere.

  14. Apparatus and methods for memory using in-plane polarization

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Liu, Junwei; Chang, Kai; Ji, Shuai-Hua

    A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process ismore » non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.« less

  15. Semiconductor photoelectrochemistry

    NASA Technical Reports Server (NTRS)

    Buoncristiani, A. M.; Byvik, C. E.

    1983-01-01

    Semiconductor photoelectrochemical reactions are investigated. A model of the charge transport processes in the semiconductor, based on semiconductor device theory, is presented. It incorporates the nonlinear processes characterizing the diffusion and reaction of charge carriers in the semiconductor. The model is used to study conditions limiting useful energy conversion, specifically the saturation of current flow due to high light intensity. Numerical results describing charge distributions in the semiconductor and its effects on the electrolyte are obtained. Experimental results include: an estimate rate at which a semiconductor photoelectrode is capable of converting electromagnetic energy into chemical energy; the effect of cell temperature on the efficiency; a method for determining the point of zero zeta potential for macroscopic semiconductor samples; a technique using platinized titanium dioxide powders and ultraviolet radiation to produce chlorine, bromine, and iodine from solutions containing their respective ions; the photoelectrochemical properties of a class of layered compounds called transition metal thiophosphates; and a technique used to produce high conversion efficiency from laser radiation to chemical energy.

  16. A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Shiota, Koki, E-mail: a14510@sr.kagawa-nct.ac.jp; Kai, Kazuho; Nagaoka, Shiro, E-mail: nagaoka@es.kagawa-nct.ac.jp

    The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As themore » result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.« less

  17. Temperature control of power semiconductor devices in traction applications

    NASA Astrophysics Data System (ADS)

    Pugachev, A. A.; Strekalov, N. N.

    2017-02-01

    The peculiarity of thermal management of traction frequency converters of a railway rolling stock is highlighted. The topology and the operation principle of the automatic temperature control system of power semiconductor modules of the traction frequency converter are designed and discussed. The features of semiconductors as an object of temperature control are considered; the equivalent circuit of thermal processes in the semiconductors is suggested, the power losses in the two-level voltage source inverters are evaluated and analyzed. The dynamic properties and characteristics of the cooling fan induction motor electric drive with the scalar control are presented. The results of simulation in Matlab are shown for the steady state of thermal processes.

  18. Reduction of Charge Traps and Stability Enhancement in Solution-Processed Organic Field-Effect Transistors Based on a Blended n-Type Semiconductor.

    PubMed

    Campos, Antonio; Riera-Galindo, Sergi; Puigdollers, Joaquim; Mas-Torrent, Marta

    2018-05-09

    Solution-processed n-type organic field-effect transistors (OFETs) are essential elements for developing large-area, low-cost, and all organic logic/complementary circuits. Nonetheless, the development of air-stable n-type organic semiconductors (OSCs) lags behind their p-type counterparts. The trapping of electrons at the semiconductor-dielectric interface leads to a lower performance and operational stability. Herein, we report printed small-molecule n-type OFETs based on a blend with a binder polymer, which enhances the device stability due to the improvement of the semiconductor-dielectric interface quality and a self-encapsulation. Both combined effects prevent the fast deterioration of the OSC. Additionally, a complementary metal-oxide semiconductor-like inverter is fabricated depositing p-type and n-type OSCs simultaneously.

  19. Collective Poisson process with periodic rates: applications in physics from micro-to nanodevices.

    PubMed

    da Silva, Roberto; Lamb, Luis C; Wirth, Gilson Inacio

    2011-01-28

    Continuous reductions in the dimensions of semiconductor devices have led to an increasing number of noise sources, including random telegraph signals (RTS) due to the capture and emission of electrons by traps at random positions between oxide and semiconductor. The models traditionally used for microscopic devices become of limited validity in nano- and mesoscale systems since, in such systems, distributed quantities such as electron and trap densities, and concepts like electron mobility, become inadequate to model electrical behaviour. In addition, current experimental works have shown that RTS in semiconductor devices based on carbon nanotubes lead to giant current fluctuations. Therefore, the physics of this phenomenon and techniques to decrease the amplitudes of RTS need to be better understood. This problem can be described as a collective Poisson process under different, but time-independent, rates, τ(c) and τ(e), that control the capture and emission of electrons by traps distributed over the oxide. Thus, models that consider calculations performed under time-dependent periodic capture and emission rates should be of interest in order to model more efficient devices. We show a complete theoretical description of a model that is capable of showing a noise reduction of current fluctuations in the time domain, and a reduction of the power spectral density in the frequency domain, in semiconductor devices as predicted by previous experimental work. We do so through numerical integrations and a novel Monte Carlo Markov chain (MCMC) algorithm based on microscopic discrete values. The proposed model also handles the ballistic regime, relevant in nano- and mesoscale devices. Finally, we show that the ballistic regime leads to nonlinearity in the electrical behaviour.

  20. High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

    PubMed

    Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

    2014-05-21

    We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

  1. Photonic Switching Devices Using Light Bullets

    NASA Technical Reports Server (NTRS)

    Goorjian, Peter M. (Inventor)

    1999-01-01

    A unique ultra-fast, all-optical switching device or switch is made with readily available, relatively inexpensive, highly nonlinear optical materials. which includes highly nonlinear optical glasses, semiconductor crystals and/or multiple quantum well semiconductor materials. At the specified wavelengths. these optical materials have a sufficiently negative group velocity dispersion and high nonlinear index of refraction to support stable light bullets. The light bullets counter-propagate through, and interact within the waveguide to selectively change each others' directions of propagation into predetermined channels. In one embodiment, the switch utilizes a rectangularly planar slab waveguide. and further includes two central channels and a plurality of lateral channels for guiding the light bullets into and out of the waveguide. An advantage of the present all-optical switching device lies in its practical use of light bullets, thus preventing the degeneration of the pulses due to dispersion and diffraction at the front and back of the pulses. Another advantage of the switching device is the relative insensitivity of the collision process to the time difference in which the counter-propagating pulses enter the waveguide. since. contrary to conventional co-propagating spatial solitons, the relative phase of the colliding pulses does not affect the interaction of these pulses. Yet another feature of the present all-optical switching device is the selection of the light pulse parameters which enables the generation of light bullets in nonlinear optical materials. including highly nonlinear optical glasses and semiconductor materials such as semiconductor crystals and/or multiple quantum well semiconductor materials.

  2. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  3. Submicron Silicon MOSFET

    NASA Technical Reports Server (NTRS)

    Daud, T.

    1986-01-01

    Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

  4. Rapid thermal processing by stamping

    DOEpatents

    Stradins, Pauls; Wang, Qi

    2013-03-05

    A rapid thermal processing device and methods are provided for thermal processing of samples such as semiconductor wafers. The device has components including a stamp (35) having a stamping surface and a heater or cooler (40) to bring it to a selected processing temperature, a sample holder (20) for holding a sample (10) in position for intimate contact with the stamping surface; and positioning components (25) for moving the stamping surface and the stamp (35) in and away from intimate, substantially non-pressured contact. Methods for using and making such devices are also provided. These devices and methods allow inexpensive, efficient, easily controllable thermal processing.

  5. Space processing of crystalline materials: A study of known methods of electrical characterization of semiconductors

    NASA Technical Reports Server (NTRS)

    Castle, J. G.

    1976-01-01

    A literature survey is presented covering nondestructive methods of electrical characterization of semiconductors. A synopsis of each technique deals with the applicability of the techniques to various device parameters and to potential in-flight use before, during, and after growth experiments on space flights. It is concluded that the very recent surge in the commercial production of large scale integrated circuitry and other semiconductor arrays requiring uniformity on the scale of a few microns, involves nondestructive test procedures which could well be useful to NASA for in-flight use in space processing.

  6. Nondestructive SEM for surface and subsurface wafer imaging

    NASA Technical Reports Server (NTRS)

    Propst, Roy H.; Bagnell, C. Robert; Cole, Edward I., Jr.; Davies, Brian G.; Dibianca, Frank A.; Johnson, Darryl G.; Oxford, William V.; Smith, Craig A.

    1987-01-01

    The scanning electron microscope (SEM) is considered as a tool for both failure analysis as well as device characterization. A survey is made of various operational SEM modes and their applicability to image processing methods on semiconductor devices.

  7. Growth of Gallium Nitride Nanowires: A Study Using In Situ Transmission Electron Microscopy

    NASA Astrophysics Data System (ADS)

    Diaz Rivas, Rosa Estela

    Owing to their special characteristics, group III-Nitride semiconductors have attracted special attention for their application in a wide range of optoelectronic devices. Of particular interest are their direct and wide band gaps that span from ultraviolet to the infrared wavelengths. In addition, their stronger bonds relative to the other compound semiconductors makes them thermally more stable, which provides devices with longer life time. However, the lattice mismatch between these semiconductors and their substrates cause the as-grown films to have high dislocation densities, reducing the life time of devices that contain these materials. One possible solution for this problem is to substitute single crystal semiconductor nanowires for epitaxial films. Due to their dimensionality, semiconductor nanowires typically have stress-free surfaces and better physical properties. In order to employ semiconductor nanowires as building blocks for nanoscale devices, a precise control of the nanowires' crystallinity, morphology, and chemistry is necessary. This control can be achieved by first developing a deeper understanding of the processes involved in the synthesis of nanowires, and then by determining the effects of temperature and pressure on their growth. This dissertation focuses on understanding of the growth processes involved in the formation of GaN nanowires. Nucleation and growth events were observed in situ and controlled in real-time using an environmental transmission electron microscope. These observations provide a satisfactory elucidation of the underlying growth mechanism during the formation of GaN nanowires. Nucleation of these nanowires appears to follow the vapor-liquid-solid mechanism. However, nanowire growth is found to follow both the vapor-liquid-solid and vapor-solid-solid mechanisms. Direct evidence of the effects of III/V ratio on nanowire growth is also reported, which provides important information for tailoring the synthesis of GaN nanowires. These findings suggest in situ electron microscopy is a powerful tool to understand the growth of GaN nanowires and also that these experimental approach can be extended to study other binary semiconductor compound such as GaP, GaAs, and InP, or even ternary compounds such as InGaN. However, further experimental work is required to fully elucidate the kinetic effects on the growth process. A better control of the growth parameters is also recommended.

  8. Astronaut Peggy Whitson Installs SUBSA Experiment

    NASA Technical Reports Server (NTRS)

    2002-01-01

    Expedition Five flight engineer Peggy Whitson is shown installing the Solidification Using a Baffle in Sealed Ampoules (SUBSA) experiment in the Microgravity Science Glovebox (MSG) in the Destiny laboratory aboard the International Space Station (ISS). SUBSA examines the solidification of semiconductor crystals from a melted material. Semiconductor crystals are used for many products that touch our everyday lives. They are found in computer chips, integrated circuits, and a multitude of other electronic devices, such as sensors for medical imaging equipment and detectors of nuclear radiation. Materials scientists want to make better semiconductor crystals to be able to further reduce the size of high-tech devices. In the microgravity environment, convection and sedimentation are reduced, so fluids do not remove and deform. Thus, space laboratories provide an ideal environment of studying solidification from the melt. This investigation is expected to determine the mechanism causing fluid motion during production of semiconductors in space. It will provide insight into the role of the melt motion in production of semiconductor crystals, advancing our knowledge of the crystal growth process. This could lead to a reduction of defects in semiconductor crystals produced in space and on Earth.

  9. International Space Station (ISS)

    NASA Image and Video Library

    2002-07-05

    Expedition Five flight engineer Peggy Whitson is shown installing the Solidification Using a Baffle in Sealed Ampoules (SUBSA) experiment in the Microgravity Science Glovebox (MSG) in the Destiny laboratory aboard the International Space Station (ISS). SUBSA examines the solidification of semiconductor crystals from a melted material. Semiconductor crystals are used for many products that touch our everyday lives. They are found in computer chips, integrated circuits, and a multitude of other electronic devices, such as sensors for medical imaging equipment and detectors of nuclear radiation. Materials scientists want to make better semiconductor crystals to be able to further reduce the size of high-tech devices. In the microgravity environment, convection and sedimentation are reduced, so fluids do not remove and deform. Thus, space laboratories provide an ideal environment of studying solidification from the melt. This investigation is expected to determine the mechanism causing fluid motion during production of semiconductors in space. It will provide insight into the role of the melt motion in production of semiconductor crystals, advancing our knowledge of the crystal growth process. This could lead to a reduction of defects in semiconductor crystals produced in space and on Earth.

  10. Semiconductor nanowire thermoelectric materials and devices, and processes for producing same

    DOEpatents

    Lagally, Max G [Madison, WI; Evans, Paul G [Madison, WI; Ritz, Clark S [Middleton, WI

    2011-02-15

    The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic longitudinal modulation, which may be a compositional modulation or a strain-induced modulation. The nanowires are constructed using lithographic techniques from thin semiconductor membranes, or "nanomembranes."

  11. Plastic Deformation as a Means to Achieve Stretchable Polymer Semiconductors

    NASA Astrophysics Data System (ADS)

    O'Connor, Brendan

    Developing intrinsically stretchable semiconductors will seamlessly transition traditional devices into a stretchable platform. Polymer semiconductors are inherently soft materials due to the weak van der Waal intermolecular bonding allowing for flexible devices. However, these materials are not typically stretchable and when large strains are applied they either crack or plastically deform. Here, we study the use of repeated plastic deformation as a means of achieving stretchable films. In this talk, critical aspects of polymer semiconductor material selection, morphology and interface properties will be discussed that enable this approach of achieving stretchable films. We show that one can employ high performance donor-acceptor polymer semiconductors that are typically brittle through proper polymer blending to significantly increase ductility to achieve stretchable films. We demonstrate a polymer blend film that can be repeatedly deformed over 65%, while maintaining charge mobility consistently above 0.15 cm2/Vs. During the stretching process we show that the films follow a well-controlled repeated deformation pattern for over 100 stretching cycles.

  12. Electrically driven deep ultraviolet MgZnO lasers at room temperature

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Suja, Mohammad; Bashar, Sunayna Binte; Debnath, Bishwajit

    Semiconductor lasers in the deep ultraviolet (UV) range have numerous potential applications ranging from water purification and medical diagnosis to high-density data storage and flexible displays. Nevertheless, very little success was achieved in the realization of electrically driven deep UV semiconductor lasers to date. Here, we report the fabrication and characterization of deep UV MgZnO semiconductor lasers. These lasers are operated with continuous current mode at room temperature and the shortest wavelength reaches 284 nm. The wide bandgap MgZnO thin films with various Mg mole fractions were grown on c-sapphire substrate using radio-frequency plasma assisted molecular beam epitaxy. Metal-semiconductor-metal (MSM)more » random laser devices were fabricated using lithography and metallization processes. Besides the demonstration of scalable emission wavelength, very low threshold current densities of 29-33 A/cm 2 are achieved. Furthermore, numerical modeling reveals that impact ionization process is responsible for the generation of hole carriers in the MgZnO MSM devices. The interaction of electrons and holes leads to radiative excitonic recombination and subsequent coherent random lasing.« less

  13. Electrically driven deep ultraviolet MgZnO lasers at room temperature

    DOE PAGES

    Suja, Mohammad; Bashar, Sunayna Binte; Debnath, Bishwajit; ...

    2017-06-01

    Semiconductor lasers in the deep ultraviolet (UV) range have numerous potential applications ranging from water purification and medical diagnosis to high-density data storage and flexible displays. Nevertheless, very little success was achieved in the realization of electrically driven deep UV semiconductor lasers to date. Here, we report the fabrication and characterization of deep UV MgZnO semiconductor lasers. These lasers are operated with continuous current mode at room temperature and the shortest wavelength reaches 284 nm. The wide bandgap MgZnO thin films with various Mg mole fractions were grown on c-sapphire substrate using radio-frequency plasma assisted molecular beam epitaxy. Metal-semiconductor-metal (MSM)more » random laser devices were fabricated using lithography and metallization processes. Besides the demonstration of scalable emission wavelength, very low threshold current densities of 29-33 A/cm 2 are achieved. Furthermore, numerical modeling reveals that impact ionization process is responsible for the generation of hole carriers in the MgZnO MSM devices. The interaction of electrons and holes leads to radiative excitonic recombination and subsequent coherent random lasing.« less

  14. Low-Cost and Large-Area Electronics, Roll-to-Roll Processing and Beyond

    NASA Astrophysics Data System (ADS)

    Wiesenhütter, Katarzyna; Skorupa, Wolfgang

    In the following chapter, the authors conduct a literature survey of current advances in state-of-the-art low-cost, flexible electronics. A new emerging trend in the design of modern semiconductor devices dedicated to scaling-up, rather than reducing, their dimensions is presented. To realize volume manufacturing, alternative semiconductor materials with superior performance, fabricated by innovative processing methods, are essential. This review provides readers with a general overview of the material and technology evolution in the area of macroelectronics. Herein, the term macroelectronics (MEs) refers to electronic systems that can cover a large area of flexible media. In stark contrast to well-established micro- and nano-scale semiconductor devices, where property improvement is associated with downscaling the dimensions of the functional elements, in macroelectronic systems their overall size defines the ultimate performance (Sun and Rogers in Adv. Mater. 19:1897-1916, 2007). The major challenges of large-scale production are discussed. Particular attention has been focused on describing advanced, short-term heat treatment approaches, which offer a range of advantages compared to conventional annealing methods. There is no doubt that large-area, flexible electronic systems constitute an important research topic for the semiconductor industry. The ability to fabricate highly efficient macroelectronics by inexpensive processes will have a significant impact on a range of diverse technology sectors. A new era "towards semiconductor volume manufacturing…" has begun.

  15. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne

    The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

  16. Optically switched graphene/4H-SiC junction bipolar transistor

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Chandrashekhar, MVS; Sudarshan, Tangali S.; Omar, Sabih U.

    A bi-polar device is provided, along with methods of making the same. The bi-polar device can include a semiconductor substrate doped with a first dopant, a semiconductor layer on the first surface of the semiconductor substrate, and a Schottky barrier layer on the semiconductor layer. The method of forming a bi-polar device can include: forming a semiconductor layer on a first surface of a semiconductor substrate, where the semiconductor substrate comprises a first dopant and where the semiconductor layer comprises a second dopant that has an opposite polarity than the first dopant; and forming a Schottky barrier layer on amore » first portion of the semiconductor layer while leaving a second portion of the semiconductor layer exposed.« less

  17. Sub-ppb Oxygen Contaminant Detection in Semi-Conductor Processing

    NASA Technical Reports Server (NTRS)

    Man, K. F.

    1995-01-01

    Gaseous contaminants such as oxygen, water vapor, nitrogen and hydrocarbons are often present in the processing environment in semiconductor device fabrication and in containerless materials processing. The contaminants arise as a result of outgassing from hot surfaces or they may be part of the impurities in commercial ultra-high purity gases. Among these gaseous contaminants, oxygen is the most reactive and, therefore, has the most adverse effects on the end product. There has been an intense effort at the Jet Propulsion Laboratory to develop different types of oxygen sorbents to reduce oxygen concentration in a microgravity processing environment to sub-ppb (parts-per-billion) levels. Higher concentrations can lead to rapid surface oxide formation, hence reducing the quality of semiconductor devices. If the concentration of oxygen in a processing chamber at 1000oC is in the ppb level, it will only take approximately 10 seconds for an oxide layer to form on the surface of a sample. The interaction of oxygen with the water surface can lead to the formation of localized defects in semi-conductor devices, hence decreasing the manufacturing yield. For example, efficient production of 64 Mb RAM chips requires contaminations below ppb levels. This paper describes a technique for measuring trace quantities of oxygen contaminants by recording the monoatomic negative ions, O-, using mass spectrometry. The O- formation from the e--O2 interaction utilizes the electron dissociative attachment method that is greatly enhanced at the resonant energy (6.8 eV). The device combines a small gridded electron ionizer with a compact mass spectrometer. The concentrations of oxygen have been measured using the method of standard additions by diluting O2 in N2. The lowest detection limit obtained was 1.2 kHz (O- count rate) at a concentration of 10-10, corresponding to 0.1 ppb.

  18. Semiconductor devices having a recessed electrode structure

    DOEpatents

    Palacios, Tomas Apostol; Lu, Bin; Matioli, Elison de Nazareth

    2015-05-26

    An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

  19. Three- and Two-Dimensional Tin and Lead Halide Perovskite Semiconductors: Synthesis and Application in Photovoltaics

    NASA Astrophysics Data System (ADS)

    Cao, Duyen Hanh

    Halide perovskites, AMX3 (A = monocation, B = Ge, Sn, or Pb, and X = halogen), present a versatile class of solution-processable semiconductors made from earth abundant materials with outstanding electrical and optical properties. Their solar cell efficiencies have dramatically increased from 9% to 22% in less than five years since 2012, a rate that has never been seen before in photovoltaic research. Critical to the final goal of commercializing perovskite solar cell technology is achieving device long-term stability and eliminating toxic elements in device components. This thesis uses 3D AMX 3 perovskites as a stand-in to develop a new class of lead-free, moisture stable, functional and highly tunable 2D Ruddlesden-Popper (BA) 2(MA)n-1SnnI3n+1 (n is an integer) perovskite semiconductors. Synthesis, thin film fabrication, extensive characterization, and solar cell device structure-performance relationships are presented throughout the entire thesis.

  20. Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process.

    PubMed

    Swain, Basudev; Mishra, Chinmayee; Lee, Chan Gi; Park, Kyung-Soo; Lee, Kun-Jae

    2015-07-01

    Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga0.97N0.9O0.09 is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga0.97N0.9O0.09 of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4M HCl, 100°C and pulp density of 100 kg/m(3,) respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. Copyright © 2015 Elsevier Inc. All rights reserved.

  1. Control of GaAs Microwave Schottky Diode Electrical Characteristics by Contact Geometry: The Gap Diode.

    DTIC Science & Technology

    1982-05-01

    semiconductor Schottky-barrier contacts are used in many semiconductor devices, including switches, rectifiers, varactors , IMPATTs, mixer and detector...ionic materials such as most of the II-VI compound semiconductors (e.g. ZnS and ZnO) and the transition-metal oxides , the barrier height is strongly...the alloying process described above is nonuniformity, due to the incomplete removal of residual surface oxides prior to the evaporation of the metal

  2. High efficiency low cost thin film silicon solar cell design and method for making

    DOEpatents

    Sopori, B.L.

    1999-04-27

    A semiconductor device is described having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer. 9 figs.

  3. An integrated semiconductor device enabling non-optical genome sequencing.

    PubMed

    Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

    2011-07-20

    The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

  4. Charge carrier mobility in thin films of organic semiconductors by the gated van der Pauw method

    PubMed Central

    Rolin, Cedric; Kang, Enpu; Lee, Jeong-Hwan; Borghs, Gustaaf; Heremans, Paul; Genoe, Jan

    2017-01-01

    Thin film transistors based on high-mobility organic semiconductors are prone to contact problems that complicate the interpretation of their electrical characteristics and the extraction of important material parameters such as the charge carrier mobility. Here we report on the gated van der Pauw method for the simple and accurate determination of the electrical characteristics of thin semiconducting films, independently from contact effects. We test our method on thin films of seven high-mobility organic semiconductors of both polarities: device fabrication is fully compatible with common transistor process flows and device measurements deliver consistent and precise values for the charge carrier mobility and threshold voltage in the high-charge carrier density regime that is representative of transistor operation. The gated van der Pauw method is broadly applicable to thin films of semiconductors and enables a simple and clean parameter extraction independent from contact effects. PMID:28397852

  5. Plasma Properties of an Exploding Semiconductor Igniter

    NASA Astrophysics Data System (ADS)

    McGuirk, J. S.; Thomas, K. A.; Shaffer, E.; Malone, A. L.; Baginski, T.; Baginski, M. E.

    1997-11-01

    Requirements by the automotive industry for low-cost, pyrotechnic igniters for automotive airbags have led to the development of several semiconductor devices. The properties of the plasma produced by the vaporization of an exploding semiconductor are necessary in order to minimize the electrical energy requirements. This work considers two silicon-based semiconductor devices: the semiconductor bridge (SCB) and the semiconductor junction igniter both consisting of etched silicon with vapor deposited aluminum structures. Electrical current passing through the device heats a narrow junction region to the point of vaporization creating an aluminum and silicon low-temperature plasma. This work will investigate the electrical characteristics of both devices and infer the plasma properties. Furthermore optical spectral measurements will be taken of the exploding devices to estimate the temperature and density of the plasma.

  6. Fundamentals handbook of electrical and computer engineering. Volume 1 Circuits fields and electronics

    NASA Astrophysics Data System (ADS)

    Chang, S. S. L.

    State of the art technology in circuits, fields, and electronics is discussed. The principles and applications of these technologies to industry, digital processing, microwave semiconductors, and computer-aided design are explained. Important concepts and methodologies in mathematics and physics are reviewed, and basic engineering sciences and associated design methods are dealt with, including: circuit theory and the design of magnetic circuits and active filter synthesis; digital signal processing, including FIR and IIR digital filter design; transmission lines, electromagnetic wave propagation and surface acoustic wave devices. Also considered are: electronics technologies, including power electronics, microwave semiconductors, GaAs devices, and magnetic bubble memories; digital circuits and logic design.

  7. Silicon carbide, a semiconductor for space power electronics

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony; Matus, Lawrence G.

    1991-01-01

    After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

  8. Contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication

    DOEpatents

    Sopori, Bhushan

    2014-05-27

    Methods for contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication are provided. In one embodiment, a method for fabricating an electrical semiconductor device comprises: a first step that includes gettering of impurities from a semiconductor wafer and forming a backsurface field; and a second step that includes forming a front contact for the semiconductor wafer, wherein the second step is performed after completion of the first step.

  9. Continuous replenishment of molten semiconductor in a Czochralski-process, single-crystal-growing furnace

    NASA Technical Reports Server (NTRS)

    Fiegl, George (Inventor); Torbet, Walter (Inventor)

    1981-01-01

    A replenishment crucible is mounted adjacent the usual drawing crucible, from which a monocrystalline boule is drawn according to the Czochralski method. A siphon tube for molten semiconductor transfer extends from the replenishment crucible to the drawing crucible. Each crucible is enclosed within its own hermetic shell and is provided with its own heater. The siphon tube is initially filled with molten semiconductor by raising the inert atmospheric pressure in the shell surrounding the replenishment crucible above that surrounding the drawing crucible. Thereafter, adjustment of the level of molten semiconductor in the drawing crucible may be achieved by adjusting the level in either crucible, since the siphon tube will establish the same level in both crucibles. For continuous processing, solid semiconductor may be added to and melted in the replenishment crucible during the process of drawing crystals from the drawing crucible. A constant liquid level of melted semiconductor is maintained in the system by an optical monitoring device and any of several electromechanical controls of the rate of replenishment or crucible height.

  10. Substrate induced changes in atomically thin 2-dimensional semiconductors: Fundamentals, engineering, and applications

    NASA Astrophysics Data System (ADS)

    Sun, Yinghui; Wang, Rongming; Liu, Kai

    2017-03-01

    Substrate has great influences on materials syntheses, properties, and applications. The influences are particularly crucial for atomically thin 2-dimensional (2D) semiconductors. Their thicknesses are less than 1 nm; however, the lateral sizes can reach up to several inches or more. Therefore, these materials must be placed onto a variety of substrates before subsequent post-processing techniques for final electronic or optoelectronic devices. Recent studies reveal that substrates have been employed as ways to modulate the optical, electrical, mechanical, and chemical properties of 2D semiconductors. In this review, we summarize recent progress upon the effects of substrates on properties of 2D semiconductors, mostly focused on 2D transition metal dichalcogenides, through viewpoints of both fundamental physics and device applications. First, we discuss various effects of substrates, including interface strain, charge transfer, dielectric screening, and optical interference. Second, we show the modulation of 2D semiconductors by substrate engineering, including novel substrates (patterned substrates, 2D-material substrates, etc.) and active substrates (phase transition materials, ferroelectric materials, flexible substrates, etc.). Last, we present prospectives and challenges in this research field. This review provides a comprehensive understanding of the substrate effects, and may inspire new ideas of novel 2D devices based on substrate engineering.

  11. Enhanced adhesion of films to semiconductors or metals by high energy bombardment

    NASA Technical Reports Server (NTRS)

    Tombrello, Thomas A. (Inventor); Qiu, Yuanxun (Inventor); Mendenhall, Marcus H. (Inventor)

    1985-01-01

    Films (12) of a metal such as gold or other non-insulator materials are firmly bonded to other non-insulators such as semiconductor substrates (10), suitably silicon or gallium arsenide by irradiating the interface with high energy ions. The process results in improved adhesion without excessive doping and provides a low resistance contact to the semiconductor. Thick layers can be bonded by depositing or doping the interfacial surfaces with fissionable elements or alpha emitters. The process can be utilized to apply very small, low resistance electrodes (78) to light-emitting solid state laser diodes (60) to form a laser device 70.

  12. Efficient semiconductor light-emitting device and method

    DOEpatents

    Choquette, Kent D.; Lear, Kevin L.; Schneider, Jr., Richard P.

    1996-01-01

    A semiconductor light-emitting device and method. The semiconductor light-emitting device is provided with at least one control layer or control region which includes an annular oxidized portion thereof to channel an injection current into the active region, and to provide a lateral refractive index profile for index guiding the light generated within the device. A periodic composition grading of at least one of the mirror stacks in the device provides a reduced operating voltage of the device. The semiconductor light-emitting device has a high efficiency for light generation, and may be formed either as a resonant-cavity light-emitting diode (RCLED) or as a vertical-cavity surface-emitting laser (VCSEL).

  13. Efficient semiconductor light-emitting device and method

    DOEpatents

    Choquette, K.D.; Lear, K.L.; Schneider, R.P. Jr.

    1996-02-20

    A semiconductor light-emitting device and method are disclosed. The semiconductor light-emitting device is provided with at least one control layer or control region which includes an annular oxidized portion thereof to channel an injection current into the active region, and to provide a lateral refractive index profile for index guiding the light generated within the device. A periodic composition grading of at least one of the mirror stacks in the device provides a reduced operating voltage of the device. The semiconductor light-emitting device has a high efficiency for light generation, and may be formed either as a resonant-cavity light-emitting diode (RCLED) or as a vertical-cavity surface-emitting laser (VCSEL). 12 figs.

  14. Current injection and transport in polyfluorene

    NASA Astrophysics Data System (ADS)

    Yang, Chieh-Kai; Yang, Chia-Ming; Liao, Hua-Hsien; Horng, Sheng-Fu; Meng, Hsin-Fei

    2007-08-01

    A comprehensive numerical model is established for the electrical processes in a sandwich organic semiconductor device with high carrier injection barrier. The charge injection at the anode interface with 0.8eV energy barrier is dominated by the hopping among the gap states of the semiconductor caused by disorders. The Ohmic behavior at low voltage is demonstrated to be not due to the background doping but the filaments formed by conductive clusters. In bipolar devices with low work function cathode it is shown that near the anode the electron traps significantly enhance hole injection through Fowler-Nordheim tunneling, resulting in rapid increases of the hole carrier and current in comparison with the hole-only devices.

  15. Development of silicon carbide semiconductor devices for high temperature applications

    NASA Technical Reports Server (NTRS)

    Matus, Lawrence G.; Powell, J. Anthony; Petit, Jeremy B.

    1991-01-01

    The semiconducting properties of electronic grade silicon carbide crystals, such as wide energy bandgap, make it particularly attractive for high temperature applications. Applications for high temperature electronic devices include instrumentation for engines under development, engine control and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Discrete prototype SiC devices were fabricated and tested at elevated temperatures. Grown p-n junction diodes demonstrated very good rectification characteristics at 870 K. A depletion-mode metal-oxide-semiconductor field-effect transistor was also successfully fabricated and tested at 770 K. While optimization of SiC fabrication processes remain, it is believed that SiC is an enabling high temperature electronic technology.

  16. Active pixel sensor with intra-pixel charge transfer

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

    1995-01-01

    An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

  17. Active pixel sensor with intra-pixel charge transfer

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

    2003-01-01

    An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

  18. Active pixel sensor with intra-pixel charge transfer

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

    2004-01-01

    An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

  19. Plasma Processes for Semiconductor Fabrication

    NASA Astrophysics Data System (ADS)

    Hitchon, W. N. G.

    1999-01-01

    Plasma processing is a central technique in the fabrication of semiconductor devices. This self-contained book provides an up-to-date description of plasma etching and deposition in semiconductor fabrication. It presents the basic physics and chemistry of these processes, and shows how they can be accurately modeled. The author begins with an overview of plasma reactors and discusses the various models for understanding plasma processes. He then covers plasma chemistry, addressing the effects of different chemicals on the features being etched. Having presented the relevant background material, he then describes in detail the modeling of complex plasma systems, with reference to experimental results. The book closes with a useful glossary of technical terms. No prior knowledge of plasma physics is assumed in the book. It contains many homework exercises and serves as an ideal introduction to plasma processing and technology for graduate students of electrical engineering and materials science. It will also be a useful reference for practicing engineers in the semiconductor industry.

  20. Printable semiconductor structures and related methods of making and assembling

    DOEpatents

    Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne; Lee, Keon Jae; Khang; , Dahl-Young; Sun, Yugang; Meitl, Matthew; Zhu, Zhengtao; Ko, Heung Cho; Mack, Shawn

    2013-03-12

    The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.

  1. Printable semiconductor structures and related methods of making and assembling

    DOEpatents

    Nuzzo, Ralph G [Champaign, IL; Rogers, John A [Champaign, IL; Menard, Etienne [Durham, NC; Lee, Keon Jae [Tokyo, JP; Khang, Dahl-Young [Urbana, IL; Sun, Yugang [Westmont, IL; Meitl, Matthew [Raleigh, NC; Zhu, Zhengtao [Rapid City, SD; Ko, Heung Cho [Urbana, IL; Mack, Shawn [Goleta, CA

    2011-10-18

    The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.

  2. Printable semiconductor structures and related methods of making and assembling

    DOEpatents

    Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne; Lee, Keon Jae; Khang, Dahl-Young; Sun, Yugang; Meitl, Matthew; Zhu, Zhengtao; Ko, Heung Cho; Mack, Shawn

    2010-09-21

    The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.

  3. SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Semiconductor-laser Fourier processors of electric signals

    NASA Astrophysics Data System (ADS)

    Blok, A. S.; Bukhenskii, A. F.; Krupitskii, É. I.; Morozov, S. V.; Pelevin, V. Yu; Sergeenko, T. N.; Yakovlev, V. I.

    1995-10-01

    An investigation is reported of acousto-optical and fibre-optic Fourier processors of electric signals, based on semiconductor lasers. A description is given of practical acousto-optical processors with an analysis band 120 MHz wide, a resolution of 200 kHz, and 7 cm × 8 cm × 18 cm dimensions. Fibre-optic Fourier processors are considered: they represent a new class of devices which are promising for the processing of gigahertz signals.

  4. Mechanism of amino acid interaction with silicon nitride surface during chemical mechanical planarization

    NASA Astrophysics Data System (ADS)

    America, William George

    Chemical-Mechanical Planarization (CMP) has become an essential technology for making modern semiconductor devices. This technique was originally applied to overcome the depth of focus limitations of lithography tools during pattern development of metal and dielectric films. As features of the semiconductor device became smaller the lithographic process shifted to shorter exposure wavelengths and the useable depth of focus became smaller. The topography differences on the wafer's surface from all of the previous processing steps became greater than the exposure tools could properly project. CMP helped solve this problem by bringing the features of the wafer surface to the same plane. As semiconductor fabrication technology progressed further, CMP was applied to other areas of the process, including shallow trench isolation and metal line Damascene processing. In its simplest application, CMP polishes on features projecting upward and higher than the average surface. These projections experience more work and are polished faster. Given sufficient time the surface becomes essentially flat, on a micro-scale, and the lithographic projection tools has the same plane onto which to focus. Thus, the pattern is properly and uniformly exposed and subsequent reactive ion etching (RIE) steps are executed. This technique was initially applied to later steps in the wafer processing scheme to render a new flat surface at each metal layer. Building on this success, CMP has been applied to a broad range of steps in the wafer processing particularly where surface topography warrants and when RIE of dielectric or metallic films is not practical. CMP has seen its greatest application in semiconductor logic and memory devices and most recently, a Damascene processing for copper lines and shallow trench isolation. This pattern dependent CMP issue is explored in this thesis as it pertains primarily to shallow trench isolation CMP coupled with a highly selective slurry chemistry.

  5. Solution-based electrical doping of semiconducting polymer films over a limited depth

    NASA Astrophysics Data System (ADS)

    Kolesov, Vladimir A.; Fuentes-Hernandez, Canek; Chou, Wen-Fang; Aizawa, Naoya; Larrain, Felipe A.; Wang, Ming; Perrotta, Alberto; Choi, Sangmoo; Graham, Samuel; Bazan, Guillermo C.; Nguyen, Thuc-Quyen; Marder, Seth R.; Kippelen, Bernard

    2017-04-01

    Solution-based electrical doping protocols may allow more versatility in the design of organic electronic devices; yet, controlling the diffusion of dopants in organic semiconductors and their stability has proven challenging. Here we present a solution-based approach for electrical p-doping of films of donor conjugated organic semiconductors and their blends with acceptors over a limited depth with a decay constant of 10-20 nm by post-process immersion into a polyoxometalate solution (phosphomolybdic acid, PMA) in nitromethane. PMA-doped films show increased electrical conductivity and work function, reduced solubility in the processing solvent, and improved photo-oxidative stability in air. This approach is applicable to a variety of organic semiconductors used in photovoltaics and field-effect transistors. PMA doping over a limited depth of bulk heterojunction polymeric films, in which amine-containing polymers were mixed in the solution used for film formation, enables single-layer organic photovoltaic devices, processed at room temperature, with power conversion efficiencies up to 5.9 +/- 0.2% and stable performance on shelf-lifetime studies at 60 °C for at least 280 h.

  6. Polycrystalline silicon study: Low-cost silicon refining technology prospects and semiconductor-grade polycrystalline silicon availability through 1988

    NASA Technical Reports Server (NTRS)

    Costogue, E. N.; Ferber, R.; Lutwack, R.; Lorenz, J. H.; Pellin, R.

    1984-01-01

    Photovoltaic arrays that convert solar energy into electrical energy can become a cost effective bulk energy generation alternative, provided that an adequate supply of low cost materials is available. One of the key requirements for economic photovoltaic cells is reasonably priced silicon. At present, the photovoltaic industry is dependent upon polycrystalline silicon refined by the Siemens process primarily for integrated circuits, power devices, and discrete semiconductor devices. This dependency is expected to continue until the DOE sponsored low cost silicon refining technology developments have matured to the point where they are in commercial use. The photovoltaic industry can then develop its own source of supply. Silicon material availability and market pricing projections through 1988 are updated based on data collected early in 1984. The silicon refining industry plans to meet the increasing demands of the semiconductor device and photovoltaic product industries are overviewed. In addition, the DOE sponsored technology research for producing low cost polycrystalline silicon, probabilistic cost analysis for the two most promising production processes for achieving the DOE cost goals, and the impacts of the DOE photovoltaics program silicon refining research upon the commercial polycrystalline silicon refining industry are addressed.

  7. Solution Deposition Methods for Carbon Nanotube Field-Effect Transistors

    DTIC Science & Technology

    2009-06-01

    authorized documents. Citation of manufacturer’s or trade names does not constitute an official endorsement or approval of the use thereof. Destroy...processed into FETs using standard microelectronics processing techniques. The resulting devices were characterized using a semiconductor parameter...method will help to determine which conditions are useful for producing CNT devices for chemical sensing and electronic applications. 15. SUBJECT TERMS

  8. Cameras for semiconductor process control

    NASA Technical Reports Server (NTRS)

    Porter, W. A.; Parker, D. L.

    1977-01-01

    The application of X-ray topography to semiconductor process control is described, considering the novel features of the high speed camera and the difficulties associated with this technique. The most significant results on the effects of material defects on device performance are presented, including results obtained using wafers processed entirely within this institute. Defects were identified using the X-ray camera and correlations made with probe data. Also included are temperature dependent effects of material defects. Recent applications and improvements of X-ray topographs of silicon-on-sapphire and gallium arsenide are presented with a description of a real time TV system prototype and of the most recent vacuum chuck design. Discussion is included of our promotion of the use of the camera by various semiconductor manufacturers.

  9. A review of the semiconductor storage of television signals. Part 2: Applications 1975-1986

    NASA Astrophysics Data System (ADS)

    Riley, J. L.

    1987-08-01

    This is the second of two reports. In the first, the emerging semiconductor memory technology over the last two decades and some of the important operational characteristics of each ensuing generation of device are described together with the design philosophy for forming the devices into useful tools for the storage of television signals. The second of these reports describes some of the applications. These include improved television synchronizers, high quality PAL decoders, television noise reducers, film dirt concealment equipment and buffer storage for television picture processing equipment such as stills stores. The continuing developments in the technology promise still further increases of memory capacity and there is a proposal to build a mass semiconductor television picture sequence store, initially as a research tool.

  10. Vacuum-processed polyethylene as a dielectric for low operating voltage organic field effect transistors

    PubMed Central

    Kanbur, Yasin; Irimia-Vladu, Mihai; Głowacki, Eric D.; Voss, Gundula; Baumgartner, Melanie; Schwabegger, Günther; Leonat, Lucia; Ullah, Mujeeb; Sarica, Hizir; Erten-Ela, Sule; Schwödiauer, Reinhard; Sitter, Helmut; Küçükyavuz, Zuhal; Bauer, Siegfried; Sariciftci, Niyazi Serdar

    2012-01-01

    We report on the fabrication and performance of vacuum-processed organic field effect transistors utilizing evaporated low-density polyethylene (LD-PE) as a dielectric layer. With C60 as the organic semiconductor, we demonstrate low operating voltage transistors with field effect mobilities in excess of 4 cm2/Vs. Devices with pentacene showed a mobility of 0.16 cm2/Vs. Devices using tyrian Purple as semiconductor show low-voltage ambipolar operation with equal electron and hole mobilities of ∼0.3 cm2/Vs. These devices demonstrate low hysteresis and operational stability over at least several months. Grazing-angle infrared spectroscopy of evaporated thin films shows that the structure of the polyethylene is similar to solution-cast films. We report also on the morphological and dielectric properties of these films. Our experiments demonstrate that polyethylene is a stable dielectric supporting both hole and electron channels. PMID:23483783

  11. Preface of 16th International conference on Defects, Recognition, Imaging and Physics in Semiconductors

    NASA Astrophysics Data System (ADS)

    Yang, Deren; Xu, Ke

    2016-11-01

    The 16th International conference on Defects-Recognition, Imaging and Physics in Semiconductors (DRIP-XVI) was held at the Worldhotel Grand Dushulake in Suzhou, China from 6th to 10th September 2015, around the 30th anniversary of the first DRIP conference. It was hosted by the Suzhou Institute of Nano-tech and Nano-bionics (SINANO), Chinese Academy of Sciences. On this occasion, about one hundred participants from nineteen countries attended the event. And a wide range of subjects were addressed during the conference: physics of point and extended defects in semiconductors: origin, electrical, optical and magnetic properties of defects; diagnostics techniques of crystal growth and processing of semiconductor materials (in-situ and process control); device imaging and mapping to evaluate performance and reliability; defect analysis in degraded optoelectronic and electronic devices; imaging techniques and instruments (proximity probe, x-ray, electron beam, non-contact electrical, optical and thermal imaging techniques, etc.); new frontiers of atomic-scale-defect assessment (STM, AFM, SNOM, ballistic electron energy microscopy, TEM, etc.); new approaches for multi-physic-parameter characterization with Nano-scale space resolution. Within these subjects, there were 58 talks, of which 18 invited, and 50 posters.

  12. Veritable electronic characteristics in ZnO nanowire circuits uncovered by the four-terminal method at a low temperature

    NASA Astrophysics Data System (ADS)

    Li, Xin; Zhang, Qi

    2017-04-01

    Understanding the natural electrical properties in semiconductor channels and the carrier transport across the metal-semiconductor contact is essential to improve the performance of nanowire devices. This work presents the true electronic characteristics of ZnO nanowire devices measured by a four-electrode method at a low-temperature environment. The temperature rise leads to the decrease in near-band-gap emission, which is attributed to two non-radiative recombination processes. For ZnO circuits, thermionic emission carrier transport mechanism plays a dominant role at Ti-Au/ZnO interface and the transport mechanism in ZnO nanowires is governed by two competitive thermal activation conduction processes: optical or acoustic phonons assisting hopping.

  13. SEM evaluation of metallization on semiconductors. [Scanning Electron Microscope

    NASA Technical Reports Server (NTRS)

    Fresh, D. L.; Adolphsen, J. W.

    1974-01-01

    A test method for the evaluation of metallization on semiconductors is presented and discussed. The method has been prepared in MIL-STD format for submittal as a proposed addition to MIL-STD-883. It is applicable to discrete devices and to integrated circuits and specifically addresses batch-process oriented defects. Quantitative accept/reject criteria are given for contact windows, other oxide steps, and general interconnecting metallization. Figures are provided that illustrate typical types of defects. Apparatus specifications, sampling plans, and specimen preparation and examination requirements are described. Procedures for glassivated devices and for multi-metal interconnection systems are included.

  14. Method and apparatus for use of III-nitride wide bandgap semiconductors in optical communications

    DOEpatents

    Hui, Rongqing [Lenexa, KS; Jiang, Hong-Xing [Manhattan, KS; Lin, Jing-Yu [Manhattan, KS

    2008-03-18

    The present disclosure relates to the use of III-nitride wide bandgap semiconductor materials for optical communications. In one embodiment, an optical device includes an optical waveguide device fabricated using a III-nitride semiconductor material. The III-nitride semiconductor material provides for an electrically controllable refractive index. The optical waveguide device provides for high speed optical communications in an infrared wavelength region. In one embodiment, an optical amplifier is provided using optical coatings at the facet ends of a waveguide formed of erbium-doped III-nitride semiconductor materials.

  15. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Curtin, D.P.

    The process analyzed involves non-production, laboratory environment use of trichloroethylene for the cleaning of semiconductor devices. The option selection centered on the replacement of the trichloroethylene with a non-hazardous material. This process waste assessment was performed as part of a pilot project.

  16. Reliability Prediction Models for Discrete Semiconductor Devices

    DTIC Science & Technology

    1988-07-01

    influence failure rate were device construction, semiconductor material, junction temperature, electrical stress, circuit application., a plication...found to influence failure rate were device construction, semiconductor material, junction temperature, electrical stress, circuit application...MFA Airbreathlng 14issile, Flight MFF Missile, Free Flight ML Missile, Launch MMIC Monolithic Microwave Integrated Circuits MOS Metal-Oxide

  17. Highly soluble [1]benzothieno[3,2-b]benzothiophene (BTBT) derivatives for high-performance, solution-processed organic field-effect transistors.

    PubMed

    Ebata, Hideaki; Izawa, Takafumi; Miyazaki, Eigo; Takimiya, Kazuo; Ikeda, Masaaki; Kuwabara, Hirokazu; Yui, Tatsuto

    2007-12-26

    2,7-Dialkyl[1]benzothieno[3,2-b]benzothiophenes were tested as solution-processible molecular semiconductors. Thin films of the organic semiconductors deposited on Si/SiO2 substrates by spin coating have well-ordered structures as confirmed by XRD analysis. Evaluations of the devices under ambient conditions showed typical p-channel FET responses with the field-effect mobility higher than 1.0 cm2 V-1 s-1 and Ion/Ioff of approximately 10(7).

  18. Luminescence in Conjugated Molecular Materials under Sub-bandgap Excitation

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    So, Franky

    2014-05-08

    Light emission in semiconductors occurs when they are under optical and electrical excitation with energy larger than the bandgap energy. In some low-dimensional semiconductor heterostructure systems, this thermodynamic limit can be violated due to radiative Auger recombination (AR), a process in which the sub-bandgap energy released from a recombined electron-hole pair is transferred to a third particle leading to radiative band-to-band recombination.1 Thus far, photoluminescence up-conversion phenomenon has been observed in some low dimensional semiconductor systems, and the effect is very weak and it can only be observed at low temperatures. Recently, we discovered that efficient electroluminescence in poly[2-methoxy-5-(2’-ethylhexyloxy)-1, phenylenevinylene]more » (MEH-PPV) polymer light-emitting devices (PLEDs) at drive voltages below its bandgap voltage could be observed when a ZnO nanoparticles (NPs) electron injection layer was inserted between the polymer and the aluminum electrode. Specifically, emitted photons with energy of 2.13 eV can be detected at operating voltages as low as 1.2 V at room temperature. Based on these data, we propose that the sub-bandgap turn-on in the MEH-PPV device is due to an Auger-assisted energy up-conversion process. The significance of this discovery is three-fold. First, radiative recombination occurs at operating voltages below the thermodynamic bandgap voltage. This process can significantly reduce the device operating voltage. For example, the current density of the device with the ZnO NC layer is almost two orders of magnitude higher than that of the device without the NC layer. Second, a reactive metal is no longer needed for the cathode. Third, this electroluminescence up-conversion process can be applied to inorganic semiconductors systems as well and their operation voltages of inorganic LEDs can be reduced to about half of the bandgap energy. Based on our initial data, we propose that the sub-bandgap turn-on in MEH-PPV devices is due to Auger-assisted energy up-conversion process. Specifically, we propose that the up-conversion process is due to charge accumulation at the polymer/NPs interface. This model requires that holes should be the dominant carriers in the polymer and the polymer/ZnO NCs heterojunction should be a type II alignment. In order to determine the mechanism of the up-conversion process, we will characterize devices fabricated using polymers with different carrier transporting properties to determine whether hole accumulation at the polymer/nanocrystals is required. Likewise, we will also use NPs with different electronic structures to fabricate devices to determine how electron accumulation affects the up-conversion process. Finally, we will measure quantitatively the interface charge accumulation by electroabsorption and correlate the results with the up-conversion photoluminescence efficiency measurements under an applied electric field.« less

  19. Emission factors of air toxics from semiconductor manufacturing in Korea.

    PubMed

    Eom, Yun-Sung; Hong, Ji-Hyung; Lee, Suk-Jo; Lee, Eun-Jung; Cha, Jun-Seok; Lee, Dae-Gyun; Bang, Sun-Ae

    2006-11-01

    The development of local, accurate emission factors is very important for the estimation of reliable national emissions and air quality management. For that, this study is performed for pollutants released to the atmosphere with source-specific emission tests from the semiconductor manufacturing industry. The semiconductor manufacturing industry is one of the major sources of air toxics or hazardous air pollutants (HAPs); thus, understanding the emission characteristics of the emission source is a very important factor in the development of a control strategy. However, in Korea, there is a general lack of information available on air emissions from the semiconductor industry. The major emission sources of air toxics examined from the semiconductor manufacturing industry were wet chemical stations, coating applications, gaseous operations, photolithography, and miscellaneous devices in the wafer fabrication and semiconductor packaging processes. In this study, analyses of emission characteristics, and the estimations of emission data and factors for air toxics, such as acids, bases, heavy metals, and volatile organic compounds from the semiconductor manufacturing process have been performed. The concentration of hydrogen chloride from the packaging process was the highest among all of the processes. In addition, the emission factor of total volatile organic compounds (TVOCs) for the packaging process was higher than that of the wafer fabrication process. Emission factors estimated in this study were compared with those of Taiwan for evaluation, and they were found to be of similar level in the case of TVOCs and fluorine compounds.

  20. High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

    PubMed

    Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

    2017-08-01

    Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

  1. High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

    PubMed Central

    Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

    2017-01-01

    Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

  2. Prospects for the application of GaN power devices in hybrid electric vehicle drive systems

    NASA Astrophysics Data System (ADS)

    Su, Ming; Chen, Chingchi; Rajan, Siddharth

    2013-07-01

    GaN, a wide bandgap semiconductor successfully implemented in optical and high-speed electronic devices, has gained momentum in recent years for power electronics applications. Along with rapid progress in material and device processing technologies, high-voltage transistors over 600 V have been reported by a number of teams worldwide. These advances make GaN highly attractive for the growing market of electrified vehicles, which currently employ bipolar silicon devices in the 600-1200 V class for the traction inverter. However, to capture this billion-dollar power market, GaN has to compete with existing IGBT products and deliver higher performance at comparable or lower cost. This paper reviews key achievements made by the GaN semiconductor industry, requirements of the automotive electric drive system and remaining challenges for GaN power devices to fit in the inverter application of hybrid vehicles.

  3. Methods of forming semiconductor devices and devices formed using such methods

    DOEpatents

    Fox, Robert V; Rodriguez, Rene G; Pak, Joshua

    2013-05-21

    Single source precursors are subjected to carbon dioxide to form particles of material. The carbon dioxide may be in a supercritical state. Single source precursors also may be subjected to supercritical fluids other than supercritical carbon dioxide to form particles of material. The methods may be used to form nanoparticles. In some embodiments, the methods are used to form chalcopyrite materials. Devices such as, for example, semiconductor devices may be fabricated that include such particles. Methods of forming semiconductor devices include subjecting single source precursors to carbon dioxide to form particles of semiconductor material, and establishing electrical contact between the particles and an electrode.

  4. Technology-design-manufacturing co-optimization for advanced mobile SoCs

    NASA Astrophysics Data System (ADS)

    Yang, Da; Gan, Chock; Chidambaram, P. R.; Nallapadi, Giri; Zhu, John; Song, S. C.; Xu, Jeff; Yeap, Geoffrey

    2014-03-01

    How to maintain the Moore's Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

  5. Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

    NASA Technical Reports Server (NTRS)

    Danchenko, V.

    1974-01-01

    Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

  6. Crystal growth of device quality GaAs in space

    NASA Technical Reports Server (NTRS)

    Gatos, H. C.; Lagowski, J.

    1984-01-01

    The crystal growth, device processing and device related properties and phenomena of GaAs are investigated. Our GaAs research evolves about these key thrust areas. The overall program combines: (1) studies of crystal growth on novel approaches to engineering of semiconductor materials (i.e., GaAs and related compounds); (2) investigation and correlation of materials properties and electronic characteristics on a macro- and microscale; (3) investigation of electronic properties and phenomena controlling device applications and device performance. The ground based program is developed which would insure successful experimentation with and eventually processing of GaAs in a near zero gravity environment.

  7. Nanoionics-Based Switches for Radio-Frequency Applications

    NASA Technical Reports Server (NTRS)

    Nessel, James; Lee, Richard

    2010-01-01

    Nanoionics-based devices have shown promise as alternatives to microelectromechanical systems (MEMS) and semiconductor diode devices for switching radio-frequency (RF) signals in diverse systems. Examples of systems that utilize RF switches include phase shifters for electronically steerable phased-array antennas, multiplexers, cellular telephones and other radio transceivers, and other portable electronic devices. Semiconductor diode switches can operate at low potentials (about 1 to 3 V) and high speeds (switching times of the order of nanoseconds) but are characterized by significant insertion loss, high DC power consumption, low isolation, and generation of third-order harmonics and intermodulation distortion (IMD). MEMS-based switches feature low insertion loss (of the order of 0.2 dB), low DC power consumption (picowatts), high isolation (>30 dB), and low IMD, but contain moving parts, are not highly reliable, and must be operated at high actuation potentials (20 to 60 V) generated and applied by use of complex circuitry. In addition, fabrication of MEMS is complex, involving many processing steps. Nanoionics-based switches offer the superior RF performance and low power consumption of MEMS switches, without need for the high potentials and complex circuitry necessary for operation of MEMS switches. At the same time, nanoionics-based switches offer the high switching speed of semiconductor devices. Also, like semiconductor devices, nanoionics-based switches can be fabricated relatively inexpensively by use of conventional integrated-circuit fabrication techniques. More over, nanoionics-based switches have simple planar structures that can easily be integrated into RF power-distribution circuits.

  8. 40 CFR 63.7195 - What definitions apply to this subpart?

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

  9. 40 CFR 63.7195 - What definitions apply to this subpart?

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

  10. 40 CFR 63.7195 - What definitions apply to this subpart?

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

  11. Recent Progress on Stretchable Electronic Devices with Intrinsically Stretchable Components.

    PubMed

    Trung, Tran Quang; Lee, Nae-Eung

    2017-01-01

    Stretchable electronic devices with intrinsically stretchable components have significant inherent advantages, including simple fabrication processes, a high integrity of the stacked layers, and low cost in comparison with stretchable electronic devices based on non-stretchable components. The research in this field has focused on developing new intrinsically stretchable components for conductors, semiconductors, and insulators. New methodologies and fabrication processes have been developed to fabricate stretchable devices with intrinsically stretchable components. The latest successful examples of stretchable conductors for applications in interconnections, electrodes, and piezoresistive devices are reviewed here. Stretchable conductors can be used for electrode or sensor applications depending on the electrical properties of the stretchable conductors under mechanical strain. A detailed overview of the recent progress in stretchable semiconductors, stretchable insulators, and other novel stretchable materials is also given, along with a discussion of the associated technological innovations and challenges. Stretchable electronic devices with intrinsically stretchable components such as field-effect transistors (FETs), photodetectors, light-emitting diodes (LEDs), electronic skins, and energy harvesters are also described and a new strategy for development of stretchable electronic devices is discussed. Conclusions and future prospects for the development of stretchable electronic devices with intrinsically stretchable components are discussed. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. Patterned arrays of lateral heterojunctions within monolayer two-dimensional semiconductors

    PubMed Central

    Mahjouri-Samani, Masoud; Lin, Ming-Wei; Wang, Kai; Lupini, Andrew R.; Lee, Jaekwang; Basile, Leonardo; Boulesbaa, Abdelaziz; Rouleau, Christopher M.; Puretzky, Alexander A.; Ivanov, Ilia N.; Xiao, Kai; Yoon, Mina; Geohegan, David B.

    2015-01-01

    The formation of semiconductor heterojunctions and their high-density integration are foundations of modern electronics and optoelectronics. To enable two-dimensional crystalline semiconductors as building blocks in next-generation electronics, developing methods to deterministically form lateral heterojunctions is crucial. Here we demonstrate an approach for the formation of lithographically patterned arrays of lateral semiconducting heterojunctions within a single two-dimensional crystal. Electron beam lithography is used to pattern MoSe2 monolayer crystals with SiO2, and the exposed locations are selectively and totally converted to MoS2 using pulsed laser vaporization of sulfur to form MoSe2/MoS2 heterojunctions in predefined patterns. The junctions and conversion process are studied by Raman and photoluminescence spectroscopy, atomically resolved scanning transmission electron microscopy and device characterization. This demonstration of lateral heterojunction arrays within a monolayer crystal is an essential step for the integration of two-dimensional semiconductor building blocks with different electronic and optoelectronic properties for high-density, ultrathin devices. PMID:26198727

  13. Chemical Vapor Deposition Of Silicon Carbide

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony; Larkin, David J.; Matus, Lawrence G.; Petit, Jeremy B.

    1993-01-01

    Large single-crystal SiC boules from which wafers of large area cut now being produced commerically. Availability of wafers opens door for development of SiC semiconductor devices. Recently developed chemical vapor deposition (CVD) process produces thin single-crystal SiC films on SiC wafers. Essential step in sequence of steps used to fabricate semiconductor devices. Further development required for specific devices. Some potential high-temperature applications include sensors and control electronics for advanced turbine engines and automobile engines, power electronics for electromechanical actuators for advanced aircraft and for space power systems, and equipment used in drilling of deep wells. High-frequency applications include communication systems, high-speed computers, and microwave power transistors. High-radiation applications include sensors and controls for nuclear reactors.

  14. Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

    2006-01-01

    An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

  15. Electrically driven plasmon-exciton coupled random lasing in ZnO metal-semiconductor-metal devices

    NASA Astrophysics Data System (ADS)

    Suja, Mohammad; Debnath, Bishwajit; Bashar, Sunayna B.; Su, Longxing; Lake, Roger; Liu, Jianlin

    2018-05-01

    Electrically driven plasmon-exciton coupled random lasing is demonstrated by incorporating Ag nanoparticles on Cu-doped ZnO metal-semiconductor-metal (MSM) devices. Both photoluminescence and electroluminescence studies show that emission efficiencies have been enhanced significantly due to coupling between ZnO excitons and Ag surface plasmons. With the incorporation of Ag nanoparticles on ZnO MSM structures, internal quantum efficiency up to 6 times is demonstrated. Threshold current for lasing is decreased by as much as 30% while the output power is increased up to 350% at an injection current of 40 mA. A numerical simulation study reveals that hole carriers are generated in the ZnO MSM devices from impact ionization processes for subsequent plasmon-exciton coupled lasing.

  16. Hardware-based image processing for high-speed inspection of grains

    USDA-ARS?s Scientific Manuscript database

    A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with slight color differences and small defects on grains The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) which...

  17. Photoemission-based microelectronic devices

    PubMed Central

    Forati, Ebrahim; Dill, Tyler J.; Tao, Andrea R.; Sievenpiper, Dan

    2016-01-01

    The vast majority of modern microelectronic devices rely on carriers within semiconductors due to their integrability. Therefore, the performance of these devices is limited due to natural semiconductor properties such as band gap and electron velocity. Replacing the semiconductor channel in conventional microelectronic devices with a gas or vacuum channel may scale their speed, wavelength and power beyond what is available today. However, liberating electrons into gas/vacuum in a practical microelectronic device is quite challenging. It often requires heating, applying high voltages, or using lasers with short wavelengths or high powers. Here, we show that the interaction between an engineered resonant surface and a low-power infrared laser can cause enough photoemission via electron tunnelling to implement feasible microelectronic devices such as transistors, switches and modulators. The proposed photoemission-based devices benefit from the advantages of gas-plasma/vacuum electronic devices while preserving the integrability of semiconductor-based devices. PMID:27811946

  18. Rapid Selective Annealing of Cu Thin Films on Si Using Microwaves

    NASA Technical Reports Server (NTRS)

    Brain, R. A.; Atwater, H. A.; Watson, T. J.; Barmatz, M.

    1994-01-01

    A major goal of the semiconductor indurstry is to lower the processing temperatures needed for interconnects in silicon integrated circuits. Typical rapid thermal annealing processes heat the film as well as the substrate, creating device problems.

  19. Overview of Characterization Techniques for High Speed Crystal Growth

    NASA Technical Reports Server (NTRS)

    Ravi, K. V.

    1984-01-01

    Features of characterization requirements for crystals, devices and completed products are discussed. Key parameters of interest in semiconductor processing are presented. Characterization as it applies to process control, diagnostics and research needs is discussed with appropriate examples.

  20. Analysis of fluctuations in semiconductor devices

    NASA Astrophysics Data System (ADS)

    Andrei, Petru

    The random nature of ion implantation and diffusion processes as well as inevitable tolerances in fabrication result in random fluctuations of doping concentrations and oxide thickness in semiconductor devices. These fluctuations are especially pronounced in ultrasmall (nanoscale) semiconductor devices when the spatial scale of doping and oxide thickness variations become comparable with the geometric dimensions of devices. In the dissertation, the effects of these fluctuations on device characteristics are analyzed by using a new technique for the analysis of random doping and oxide thickness induced fluctuations. This technique is universal in nature in the sense that it is applicable to any transport model (drift-diffusion, semiclassical transport, quantum transport etc.) and it can be naturally extended to take into account random fluctuations of the oxide (trapped) charges and channel length. The technique is based on linearization of the transport equations with respect to the fluctuating quantities. It is computationally much (a few orders of magnitude) more efficient than the traditional Monte-Carlo approach and it yields information on the sensitivity of fluctuations of parameters of interest (e.g. threshold voltage, small-signal parameters, cut-off frequencies, etc.) to the locations of doping and oxide thickness fluctuations. For this reason, it can be very instrumental in the design of fluctuation-resistant structures of semiconductor devices. Quantum mechanical effects are taken into account by using the density-gradient model as well as through self-consistent Poisson-Schrodinger computations. Special attention is paid to the presenting of the technique in a form that is suitable for implementation on commercial device simulators. The numerical implementation of the technique is discussed in detail and numerous computational results are presented and compared with those previously published in literature.

  1. Oxide semiconductor thin-film transistors: a review of recent advances.

    PubMed

    Fortunato, E; Barquinha, P; Martins, R

    2012-06-12

    Transparent electronics is today one of the most advanced topics for a wide range of device applications. The key components are wide bandgap semiconductors, where oxides of different origins play an important role, not only as passive component but also as active component, similar to what is observed in conventional semiconductors like silicon. Transparent electronics has gained special attention during the last few years and is today established as one of the most promising technologies for leading the next generation of flat panel display due to its excellent electronic performance. In this paper the recent progress in n- and p-type oxide based thin-film transistors (TFT) is reviewed, with special emphasis on solution-processed and p-type, and the major milestones already achieved with this emerging and very promising technology are summarizeed. After a short introduction where the main advantages of these semiconductors are presented, as well as the industry expectations, the beautiful history of TFTs is revisited, including the main landmarks in the last 80 years, finishing by referring to some papers that have played an important role in shaping transparent electronics. Then, an overview is presented of state of the art n-type TFTs processed by physical vapour deposition methods, and finally one of the most exciting, promising, and low cost but powerful technologies is discussed: solution-processed oxide TFTs. Moreover, a more detailed focus analysis will be given concerning p-type oxide TFTs, mainly centred on two of the most promising semiconductor candidates: copper oxide and tin oxide. The most recent data related to the production of complementary metal oxide semiconductor (CMOS) devices based on n- and p-type oxide TFT is also be presented. The last topic of this review is devoted to some emerging applications, finalizing with the main conclusions. Related work that originated at CENIMAT|I3N during the last six years is included in more detail, which has led to the fabrication of high performance n- and p-type oxide transistors as well as the fabrication of CMOS devices with and on paper. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  2. Molecular detection via hybrid peptide-semiconductor photonic devices

    NASA Astrophysics Data System (ADS)

    Estephan, E.; Saab, M.-b.; Martin, M.; Cloitre, T.; Larroque, C.; Cuisinier, F. J. G.; Malvezzi, A. M.; Gergely, C.

    2011-03-01

    The aim of this work was to investigate the possibilities to support device functionality that includes strongly confined and localized light emission and detection processes within nano/micro-structured semiconductors for biosensing applications. The interface between biological molecules and semiconductor surfaces, yet still under-explored is a key issue for improving biomolecular recognition in devices. We report on the use of adhesion peptides, elaborated via combinatorial phage-display libraries for controlled placement of biomolecules, leading to user-tailored hybrid photonic systems for molecular detection. An M13 bacteriophage library has been used to screen 1010 different peptides against various semiconductors to finally isolate specific peptides presenting a high binding capacity for the target surfaces. When used to functionalize porous silicon microcavities (PSiM) and GaAs/AlGaAs photonic crystals, we observe the formation of extremely thin (<1nm) peptide layers, hereby preserving the nanostructuration of the crystals. This is important to assure the photonic response of these tiny structures when they are functionalized by a biotinylated peptide layer and then used to capture streptavidin. Molecular detection was monitored via both linear and nonlinear optical measurements. Our linear reflectance spectra demonstrate an enhanced detection resolution via PSiM devices, when functionalized with the Si-specific peptide. Molecular capture at even lower concentrations (femtomols) is possible via the second harmonic generation of GaAs/AlGaAs photonic crystals when functionalized with GaAs-specific peptides. Our work demonstrates the outstanding value of adhesion peptides as interface linkers between semiconductors and biological molecules. They assure an enhanced molecular detection via both linear and nonlinear answers of photonic crystals.

  3. Extracting Silicon From Sodium-Process Products

    NASA Technical Reports Server (NTRS)

    Kapur, V.; Sanjurjo, A.; Sancier, K. M.; Nanis, L.

    1982-01-01

    New acid leaching process purifies silicon produced in reaction between silicon fluoride and sodium. Concentration of sodium fluoride and other impurities and byproducts remaining in silicon are within acceptable ranges for semi-conductor devices. Leaching process makes sodium reduction process more attractive for making large quantities of silicon for solar cells.

  4. Near-infrared light emitting device using semiconductor nanocrystals

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Supran, Geoffrey J.S.; Song, Katherine W.; Hwang, Gyuweon

    A near-infrared light emitting device can include semiconductor nanocrystals that emit at wavelengths beyond 1 .mu.m. The semiconductor nanocrystals can include a core and an overcoating on a surface of the core.

  5. Introduction to Semiconductor Devices

    NASA Astrophysics Data System (ADS)

    Brennan, Kevin F.

    2005-03-01

    This volume offers a solid foundation for understanding the most important devices used in the hottest areas of electronic engineering today, from semiconductor fundamentals to state-of-the-art semiconductor devices in the telecommunications and computing industries. Kevin Brennan describes future approaches to computing hardware and RF power amplifiers, and explains how emerging trends and system demands of computing and telecommunications systems influence the choice, design and operation of semiconductor devices. In addition, he covers MODFETs and MOSFETs, short channel effects, and the challenges faced by continuing miniaturization. His book is both an excellent senior/graduate text and a valuable reference for practicing engineers and researchers.

  6. Ambipolar Small-Molecule:Polymer Blend Semiconductors for Solution-Processable Organic Field-Effect Transistors.

    PubMed

    Kang, Minji; Hwang, Hansu; Park, Won-Tae; Khim, Dongyoon; Yeo, Jun-Seok; Kim, Yunseul; Kim, Yeon-Ju; Noh, Yong-Young; Kim, Dong-Yu

    2017-01-25

    We report on the fabrication of an organic thin-film semiconductor formed using a blend solution of soluble ambipolar small molecules and an insulating polymer binder that exhibits vertical phase separation and uniform film formation. The semiconductor thin films are produced in a single step from a mixture containing a small molecular semiconductor, namely, quinoidal biselenophene (QBS), and a binder polymer, namely, poly(2-vinylnaphthalene) (PVN). Organic field-effect transistors (OFETs) based on QBS/PVN blend semiconductor are then assembled using top-gate/bottom-contact device configuration, which achieve almost four times higher mobility than the neat QBS semiconductor. Depth profile via secondary ion mass spectrometry and atomic force microscopy images indicate that the QBS domains in the films made from the blend are evenly distributed with a smooth morphology at the bottom of the PVN layer. Bias stress test and variable-temperature measurements on QBS-based OFETs reveal that the QBS/PVN blend semiconductor remarkably reduces the number of trap sites at the gate dielectric/semiconductor interface and the activation energy in the transistor channel. This work provides a one-step solution processing technique, which makes use of soluble ambipolar small molecules to form a thin-film semiconductor for application in high-performance OFETs.

  7. Chemical vapor deposition and characterization of polysilanes polymer based thin films and their applications in compound semiconductors and silicon devices

    NASA Astrophysics Data System (ADS)

    Oulachgar, El Hassane

    As the semiconductors industry is moving toward nanodevices, there is growing need to develop new materials and thin films deposition processes which could enable strict control of the atomic composition and structure of thin film materials in order to achieve precise control on their electrical and optical properties. The accurate control of thin film characteristics will become increasingly important as the miniaturization of semiconductor devices continue. There is no doubt that chemical synthesis of new materials and their self assembly will play a major role in the design and fabrication of next generation semiconductor devices. The objective of this work is to investigate the chemical vapor deposition (CVD) process of thin film using a polymeric precursor as a source material. This process offers many advantages including low deposition cost, hazard free working environment, and most importantly the ability to customize the polymer source material through polymer synthesis and polymer functionalization. The combination between polymer synthesis and CVD process will enable the design of new generation of complex thin film materials with a wide range of improved chemical, mechanical, electrical and optical properties which cannot be easily achieved through conventional CVD processes based on gases and small molecule precursors. In this thesis we mainly focused on polysilanes polymers and more specifically poly(dimethylsilanes). The interest in these polymers is motivated by their distinctive electronic and photonic properties which are attributed to the delocalization of the sigma-electron along the Si-Si backbone chain. These characteristics make polysilane polymers very promising in a broad range of applications as a dielectric, a semiconductor and a conductor. The polymer-based CVD process could be eventually extended to other polymer source materials such as polygermanes, as well as and a variety of other inorganic and hybrid organic-inorganic polymers. This work has demonstrated that a polysilane polymeric source can be used to deposit a wide range of thin film materials exhibiting similar properties with conventional ceramic materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC) silicon dioxide (SiO2) and silicon nitride (Si3N4). The strict control of the deposition process allows precise control of the electrical, optical and chemical properties of polymer-based thin films within a broad range. This work has also demonstrated for the first time that poly(dimethylsilmaes) polymers deposited by CVD can be used to effectively passivate both silicon and gallium arsenide MOS devices. This finding makes polymer-based thin films obtained by CVD very promising for the development of high-kappa dielectric materials for next generation high-mobility CMOS technology. Keywords. Thin films, Polymers, Vapor Phase Deposition, CVD, Nanodielectrics, Organosilanes, Polysilanes, GaAs Passivation, MOSFET, Silicon Oxynitride, Integrated Waveguide, Silicon Carbide, Compound Semiconductors.

  8. Energy storage device with large charge separation

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Holme, Timothy P.; Prinz, Friedrich B.; Iancu, Andrei T.

    High density energy storage in semiconductor devices is provided. There are two main aspects of the present approach. The first aspect is to provide high density energy storage in semiconductor devices based on formation of a plasma in the semiconductor. The second aspect is to provide high density energy storage based on charge separation in a p-n junction.

  9. Energy storage device with large charge separation

    DOEpatents

    Holme, Timothy P.; Prinz, Friedrich B.; Iancu, Andrei

    2016-04-12

    High density energy storage in semiconductor devices is provided. There are two main aspects of the present approach. The first aspect is to provide high density energy storage in semiconductor devices based on formation of a plasma in the semiconductor. The second aspect is to provide high density energy storage based on charge separation in a p-n junction.

  10. Ge/IIIV fin field-effect transistor common gate process and numerical simulations

    NASA Astrophysics Data System (ADS)

    Chen, Bo-Yuan; Chen, Jiann-Lin; Chu, Chun-Lin; Luo, Guang-Li; Lee, Shyong; Chang, Edward Yi

    2017-04-01

    This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high- and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations.

  11. Rapid Thermal Processing (RTP) of semiconductors in space

    NASA Technical Reports Server (NTRS)

    Anderson, T. J.; Jones, K. S.

    1993-01-01

    The progress achieved on the project entitled 'Rapid Thermal Processing of Semiconductors in Space' for a 12 month period of activity ending March 31, 1993 is summarized. The activity of this group is being performed under the direct auspices of the ROMPS program. The main objective of this program is to develop and demonstrate the use of advanced robotics in space with rapid thermal process (RTP) of semiconductors providing the test technology. Rapid thermal processing is an ideal processing step for demonstration purposes since it encompasses many of the characteristics of other processes used in solid state device manufacturing. Furthermore, a low thermal budget is becoming more important in existing manufacturing practice, while a low thermal budget is critical to successful processing in space. A secondary objective of this project is to determine the influence of microgravity on the rapid thermal process for a variety of operating modes. In many instances, this involves one or more fluid phases. The advancement of microgravity processing science is an important ancillary objective.

  12. Diode having trenches in a semiconductor region

    DOEpatents

    Palacios, Tomas Apostol; Lu, Bin; Matioli, Elison de Nazareth

    2016-03-22

    An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

  13. Process Control in Production-Worthy Plasma Doping Technology

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Winder, Edmund J.; Fang Ziwei; Arevalo, Edwin

    2006-11-13

    As the semiconductor industry continues to scale devices of smaller dimensions and improved performance, many ion implantation processes require lower energy and higher doses. Achieving these high doses (in some cases {approx}1x1016 ions/cm2) at low energies (<3 keV) while maintaining throughput is increasingly challenging for traditional beamline implant tools because of space-charge effects that limit achievable beam density at low energies. Plasma doping is recognized as a technology which can overcome this problem. In this paper, we highlight the technology available to achieve process control for all implant parameters associated with modem semiconductor manufacturing.

  14. Monolayer-Mediated Growth of Organic Semiconductor Films with Improved Device Performance.

    PubMed

    Huang, Lizhen; Hu, Xiaorong; Chi, Lifeng

    2015-09-15

    Increased interest in wearable and smart electronics is driving numerous research works on organic electronics. The control of film growth and patterning is of great importance when targeting high-performance organic semiconductor devices. In this Feature Article, we summarize our recent work focusing on the growth, crystallization, and device operation of organic semiconductors intermediated by ultrathin organic films (in most cases, only a monolayer). The site-selective growth, modified crystallization and morphology, and improved device performance of organic semiconductor films are demonstrated with the help of the inducing layers, including patterned and uniform Langmuir-Blodgett monolayers, crystalline ultrathin organic films, and self-assembled polymer brush films. The introduction of the inducing layers could dramatically change the diffusion of the organic semiconductors on the surface and the interactions between the active layer with the inducing layer, leading to improved aggregation/crystallization behavior and device performance.

  15. Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

    DOEpatents

    Welch, James D.

    2000-01-01

    Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  16. Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

    PubMed

    Wang, Zhenwei; Al-Jawhari, Hala A; Nayak, Pradipta K; Caraveo-Frescas, J A; Wei, Nini; Hedhili, M N; Alshareef, H N

    2015-04-20

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

  17. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    PubMed Central

    Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, M. N.; Alshareef, H. N.

    2015-01-01

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field. PMID:25892711

  18. Methods of manipulating stressed epistructures

    DOEpatents

    Wanlass, Mark W

    2014-04-08

    A method of processing an epistructure or processing a semiconductor device including associating a conformal and flexible handle with the epistructure and removing the epistructure and handle as a unit from the parent substrate. The method further includes causing the epistructure and handle unit to conform to a shape that differs from the shape the epistructure otherwise inherently assumes upon removal from the parent substrate. A device prepared according to the disclosed methods.

  19. Chemical and Morphological Control of Interfacial Self-Doping for Efficient Organic Electronics.

    PubMed

    Liu, Yao; Cole, Marcus D; Jiang, Yufeng; Kim, Paul Y; Nordlund, Dennis; Emrick, Todd; Russell, Thomas P

    2018-04-01

    Solution-based processing of materials for electrical doping of organic semiconductor interfaces is attractive for boosting the efficiency of organic electronic devices with multilayer structures. To simplify this process, self-doping perylene diimide (PDI)-based ionene polymers are synthesized, in which the semiconductor PDI components are embedded together with electrolyte dopants in the polymer backbone. Functionality contained within the PDI monomers suppresses their aggregation, affording self-doping interlayers with controllable thickness when processed from solution into organic photovoltaic devices (OPVs). Optimal results for interfacial self-doping lead to increased power conversion efficiencies (PCEs) of the fullerene-based OPVs, from 2.62% to 10.64%, and of the nonfullerene-based OPVs, from 3.34% to 10.59%. These PDI-ionene interlayers enable chemical and morphological control of interfacial doping and conductivity, demonstrating that the conductive channels are crucial for charge transport in doped organic semiconductor films. Using these novel interlayers with efficient doping and high conductivity, both fullerene- and nonfullerene-based OPVs are achieved with PCEs exceeding 9% over interlayer thicknesses ranging from ≈3 to 40 nm. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Room-temperature preparation of trisilver-copper-sulfide/polymer based heterojunction thin film for solar cell application

    NASA Astrophysics Data System (ADS)

    Lei, Yan; Yang, Xiaogang; Gu, Longyan; Jia, Huimin; Ge, Suxiang; Xiao, Pin; Fan, Xiaoli; Zheng, Zhi

    2015-04-01

    Solar cells devices based on inorganic/polymer heterojunction can be a possible solution to harvest solar energy and convert to electric energy with high efficiency through a cost-effective fabrication. The solution-process method can be easily used to produce large area devices. Moreover, due to the intrinsic different charge separation, diffusion or recombination in various semiconductors, the interfaces between each component may strongly influence the inorganic/polymer heterojunction performance. Here we prepared a n-type Ag3CuS2 (Eg = 1.25 eV) nanostructured film through a room-temperature element reaction process, which was confirmed as direct bandgap semiconductor through density function theory simulation. This Ag3CuS2 film was spin-coated with an organic semiconducting poly(3-hexythiophene) (P3HT) or polythieno[3,4-b]-thiophene-co-benzodithiophene (PTB7) film, which formed an inorganic/polymer heterojunction. After constructing it to a solar cell device, the power conversion efficiencies of 0.79% and 0.31% were achieved with simulated solar illumination on Ag3CuS2/P3HT and Ag3CuS2/PTB7, respectively. A possible mechanism was discussed and we showed the charge separation at interface of inorganic and polymer semiconductors played an important role.

  1. Wide-band-gap, alkaline-earth-oxide semiconductor and devices utilizing same

    DOEpatents

    Abraham, Marvin M.; Chen, Yok; Kernohan, Robert H.

    1981-01-01

    This invention relates to novel and comparatively inexpensive semiconductor devices utilizing semiconducting alkaline-earth-oxide crystals doped with alkali metal. The semiconducting crystals are produced by a simple and relatively inexpensive process. As a specific example, a high-purity lithium-doped MgO crystal is grown by conventional techniques. The crystal then is heated in an oxygen-containing atmosphere to form many [Li].degree. defects therein, and the resulting defect-rich hot crystal is promptly quenched to render the defects stable at room temperature and temperatures well above the same. Quenching can be effected conveniently by contacting the hot crystal with room-temperature air.

  2. Photoelectrochemical cell including Ga(Sb.sub.x)N.sub.1-x semiconductor electrode

    DOEpatents

    Menon, Madhu; Sheetz, Michael; Sunkara, Mahendra Kumar; Pendyala, Chandrashekhar; Sunkara, Swathi; Jasinski, Jacek B.

    2017-09-05

    The composition of matter comprising Ga(Sb.sub.x)N.sub.1-x where x=0.01 to 0.06 is characterized by a band gap between 2.4 and 1.7 eV. A semiconductor device includes a semiconductor layer of that composition. A photoelectric cell includes that semiconductor device.

  3. Mesoscopic Elastic Distortions in GaAs Quantum Dot Heterostructures.

    PubMed

    Pateras, Anastasios; Park, Joonkyu; Ahn, Youngjun; Tilka, Jack A; Holt, Martin V; Reichl, Christian; Wegscheider, Werner; Baart, Timothy A; Dehollain, Juan Pablo; Mukhopadhyay, Uditendu; Vandersypen, Lieven M K; Evans, Paul G

    2018-05-09

    Quantum devices formed in high-electron-mobility semiconductor heterostructures provide a route through which quantum mechanical effects can be exploited on length scales accessible to lithography and integrated electronics. The electrostatic definition of quantum dots in semiconductor heterostructure devices intrinsically involves the lithographic fabrication of intricate patterns of metallic electrodes. The formation of metal/semiconductor interfaces, growth processes associated with polycrystalline metallic layers, and differential thermal expansion produce elastic distortion in the active areas of quantum devices. Understanding and controlling these distortions present a significant challenge in quantum device development. We report synchrotron X-ray nanodiffraction measurements combined with dynamical X-ray diffraction modeling that reveal lattice tilts with a depth-averaged value up to 0.04° and strain on the order of 10 -4 in the two-dimensional electron gas (2DEG) in a GaAs/AlGaAs heterostructure. Elastic distortions in GaAs/AlGaAs heterostructures modify the potential energy landscape in the 2DEG due to the generation of a deformation potential and an electric field through the piezoelectric effect. The stress induced by metal electrodes directly impacts the ability to control the positions of the potential minima where quantum dots form and the coupling between neighboring quantum dots.

  4. Visualization of TlBr ionic transport mechanism by the Accelerated Device Degradation technique

    NASA Astrophysics Data System (ADS)

    Datta, Amlan; Becla, Piotr; Motakef, Shariar

    2015-06-01

    Thallium Bromide (TlBr) is a promising gamma radiation semiconductor detector material. However, it is an ionic semiconductor and suffers from polarization. As a result, TlBr devices degrade rapidly at room temperature. Polarization is associated with the flow of ionic current in the crystal under electrical bias, leading to the accumulation of charged ions at the device's electrical contacts. We report a fast and reliable direct characterization technique to identify the effects of various growth and post-growth process modifications on the polarization process. The Accelerated Device Degradation (ADD) characterization technique allows direct observation of nucleation and propagation of ionic transport channels within the TlBr crystals under applied bias. These channels are observed to be initiated both directly under the electrode as well as away from it. The propagation direction is always towards the anode indicating that Br- is the mobile diffusing species within the defect channels. The effective migration energy of the Br- ions was calculated to be 0.33±0.03 eV, which is consistent with other theoretical and experimental results.

  5. Self-cleaning and surface chemical reactions during hafnium dioxide atomic layer deposition on indium arsenide.

    PubMed

    Timm, Rainer; Head, Ashley R; Yngman, Sofie; Knutsson, Johan V; Hjort, Martin; McKibbin, Sarah R; Troian, Andrea; Persson, Olof; Urpelainen, Samuli; Knudsen, Jan; Schnadt, Joachim; Mikkelsen, Anders

    2018-04-12

    Atomic layer deposition (ALD) enables the ultrathin high-quality oxide layers that are central to all modern metal-oxide-semiconductor circuits. Crucial to achieving superior device performance are the chemical reactions during the first deposition cycle, which could ultimately result in atomic-scale perfection of the semiconductor-oxide interface. Here, we directly observe the chemical reactions at the surface during the first cycle of hafnium dioxide deposition on indium arsenide under realistic synthesis conditions using photoelectron spectroscopy. We find that the widely used ligand exchange model of the ALD process for the removal of native oxide on the semiconductor and the simultaneous formation of the first hafnium dioxide layer must be significantly revised. Our study provides substantial evidence that the efficiency of the self-cleaning process and the quality of the resulting semiconductor-oxide interface can be controlled by the molecular adsorption process of the ALD precursors, rather than the subsequent oxide formation.

  6. Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors

    NASA Astrophysics Data System (ADS)

    Marrs, Michael

    A low temperature amorphous oxide thin film transistor (TFT) and amorphous silicon PIN diode backplane technology for large area flexible digital x-ray detectors has been developed to create 7.9-in. diagonal backplanes. The critical steps in the evolution of the backplane process include the qualification and optimization of the low temperature (200 °C) metal oxide TFT and a-Si PIN photodiode process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication and assembly of the flexible detectors. Mixed oxide semiconductor TFTs on flexible plastic substrates suffer from performance and stability issues related to the maximum processing temperature limitation of the polymer. A novel device architecture based upon a dual active layer improves both the performance and stability. Devices are directly fabricated below 200 ºC on a polyethylene naphthalate (PEN) substrate using mixed metal oxides of either zinc indium oxide (ZIO) or indium gallium zinc oxide (IGZO) as the active semiconductor. The dual active layer architecture allows for adjustment to the saturation mobility and threshold voltage stability without the requirement of high temperature annealing, which is not compatible with flexible plastic substrates like PEN. The device performance and stability is strongly dependent upon the composition of the mixed metal oxide; this dependency provides a simple route to improving the threshold voltage stability and drive performance. By switching from a single to a dual active layer, the saturation mobility increases from 1.2 cm2/V-s to 18.0 cm2/V-s, while the rate of the threshold voltage shift decreases by an order of magnitude. This approach could assist in enabling the production of devices on flexible substrates using amorphous oxide semiconductors. Low temperature (200°C) processed amorphous silicon photodiodes were developed successfully by balancing the tradeoffs between low temperature and low stress (less than -70 MPa compressive) and device performance. Devices with a dark current of less than 1.0 pA/mm2 and a quantum efficiency of 68% have been demonstrated. Alternative processing techniques, such as pixelating the PIN diode and using organic photodiodes have also been explored for applications where extreme flexibility is desired.

  7. Development of Room Temperature Excitonic Lasing From ZnO and MgZnO Thin Film Based Metal-Semiconductor-Metal Devices

    NASA Astrophysics Data System (ADS)

    Suja, Mohammad Zahir Uddin

    Room temperature excitonic lasing is demonstrated and developed by utilizing metal-semiconductor-metal devices based on ZnO and MgZnO materials. At first, Cu-doped p-type ZnO films are grown on c-sapphire substrates by plasma-assisted molecular beam epitaxy. Photoluminescence (PL) experiments reveal a shallow acceptor state at 0.15 eV above the valence band edge. Hall effect results indicate that a growth condition window is found for the formation of p-type ZnO thin films and the best conductivity is achieved with a high hole concentration of 1.54x1018 cm-3, a low resistivity of 0.6 O cm and a moderate mobility of 6.65 cm2 V -1 s-1 at room temperature. Metal oxide semiconductor (MOS) capacitor devices have been fabricated on the Cu-doped ZnO films and the characteristics of capacitance-voltage measurements demonstrate that the Cu-doped ZnO thin films under proper growth conditions are p-type. Seebeck measurements on these Cu-doped ZnO samples lead to positive Seebeck coefficients and further confirm the p-type conductivity. Other measurements such as XRD, XPS, Raman and absorption are also performed to elucidate the structural and optical characteristics of the Cu-doped p-type ZnO films. The p-type conductivity is explained to originate from Cu substitution of Zn with a valency of +1 state. However, all p-type samples are converted to n-type over time, which is mostly due to the carrier compensation from extrinsic defects of ZnO. To overcome the stability issue of p-type ZnO film, alternate devices other than p-n junction has been developed. Electrically driven plasmon-exciton coupled random lasing is demonstrated by incorporating Ag nanoparticles on Cu-doped ZnO metal-semiconductor-metal (MSM) devices. Both photoluminescence and electroluminescence studies show that emission efficiencies have been enhanced significantly due to coupling between ZnO excitons and Ag surface plasmons. With the incorporation of Ag nanoparticles on ZnO MSM structures, internal quantum efficiency up to 6 times is demonstrated. Threshold current for lasing is decreased by as much as 30% while the output power is increased up to 350% at an injection current of 40 mA. A numerical simulation study reveals that hole carriers are generated in the ZnO MSM devices from impact ionization processes for subsequent plasmon-exciton coupled lasing. Our results suggest that plasmon-enhanced ZnO MSM random lasers can become a competitive candidate of efficient ultraviolet light sources. Semiconductor lasers in the deep ultraviolet (UV) range have numerous potential applications ranging from water purification and medical diagnosis to high-density data storage and flexible displays. Nevertheless, very little success was achieved in the realization of electrically driven deep UV semiconductor lasers to date. In this thesis, we report the fabrication and characterization of deep UV MgZnO semiconductor lasers. These lasers are operated with continuous current mode at room temperature and the shortest wavelength reaches 284 nm. The wide bandgap MgZnO thin films with various Mg mole fractions were grown on c-sapphire substrate using radio-frequency plasma assisted molecular beam epitaxy. Metal-semiconductor-metal (MSM) random laser devices were fabricated using lithography and metallization processes. Besides the demonstration of scalable emission wavelength, very low threshold current densities of 29 33 A/cm2 are achieved. Numerical modeling reveals that impact ionization process is responsible for the generation of hole carriers in the MgZnO MSM devices. The interaction of electrons and holes leads to radiative excitonic recombination and subsequent coherent random lasing.

  8. Monolithic integrated high-T.sub.c superconductor-semiconductor structure

    NASA Technical Reports Server (NTRS)

    Barfknecht, Andrew T. (Inventor); Garcia, Graham A. (Inventor); Russell, Stephen D. (Inventor); Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Clayton, Stanley R. (Inventor)

    2000-01-01

    A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

  9. Metal Contacts in Semiconductors.

    DTIC Science & Technology

    1983-11-01

    greater understanding of the role that imperfec- tions, defects etc. play in the formation of Schottk~y barriers and related devices. In section 1 of...these effects. In Section 2 of this report we consider the role of surface defects in the pinning of the Fermi level at free semiconductor surfaces and...in the adsorption and oxidation processes involved when these surfaces interact with gases and metals. The role of imperfections at metal

  10. Conservation of quantum efficiency in quantum well intermixing by stress engineering with dielectric bilayers

    NASA Astrophysics Data System (ADS)

    Arslan, Seval; Demir, Abdullah; Şahin, Seval; Aydınlı, Atilla

    2018-02-01

    In semiconductor lasers, quantum well intermixing (QWI) with high selectivity using dielectrics often results in lower quantum efficiency. In this paper, we report on an investigation regarding the effect of thermally induced dielectric stress on the quantum efficiency of quantum well structures in impurity-free vacancy disordering (IFVD) process using photoluminescence and device characterization in conjunction with microscopy. SiO2 and Si x O2/SrF2 (versus SrF2) films were employed for the enhancement and suppression of QWI, respectively. Large intermixing selectivity of 75 nm (125 meV), consistent with the theoretical modeling results, with negligible effect on the suppression region characteristics, was obtained. Si x O2 layer compensates for the large thermal expansion coefficient mismatch of SrF2 with the semiconductor and mitigates the detrimental effects of SrF2 without sacrificing its QWI benefits. The bilayer dielectric approach dramatically improved the dielectric-semiconductor interface quality. Fabricated high power semiconductor lasers demonstrated high quantum efficiency in the lasing region using the bilayer dielectric film during the intermixing process. Our results reveal that stress engineering in IFVD is essential and the thermal stress can be controlled by engineering the dielectric strain opening new perspectives for QWI of photonic devices.

  11. Interface Energetics and Chemical Doping of Organic Electronic Materials

    NASA Astrophysics Data System (ADS)

    Kahn, Antoine

    2014-03-01

    The energetics of organic semiconductors and their interfaces are central to the performance of organic thin film devices. The relative positions of charge transport states across the many interfaces of multi-layer OLEDs, OPV cells and OFETs determine in great part the efficiency and lifetime of these devices. New experiments are presented here, that look in detail at the position of these transport states and associated gap states and electronic traps that tail into the energy gap of organic molecular (e.g. pentacene) or polymer (P3HT, PBDTTT-C) semiconductors, and which directly affect carrier mobility in these materials. Disorder, sometime caused by simple exposure to an inert gas, impurities and defects are at the origin of these electronic gap states. Recent efforts in chemical doping in organic semiconductors aimed at mitigating the impact of electronic gap states are described. An overview of the reducing or oxidizing power of several n- and p-type dopants for vacuum- or solution-processed films, and their effect on the electronic structure and conductivity of both vacuum- and solution-processed organic semiconductor films is given. Finally, the filling (compensation) of active gap states via doping is investigated on the electron-transport materials C60 and P(NDI2OD-T2) , and the hole-transport polymer PBDTTT-C.

  12. A new approximation of Fermi-Dirac integrals of order 1/2 for degenerate semiconductor devices

    NASA Astrophysics Data System (ADS)

    AlQurashi, Ahmed; Selvakumar, C. R.

    2018-06-01

    There had been tremendous growth in the field of Integrated circuits (ICs) in the past fifty years. Scaling laws mandated both lateral and vertical dimensions to be reduced and a steady increase in doping densities. Most of the modern semiconductor devices have invariably heavily doped regions where Fermi-Dirac Integrals are required. Several attempts have been devoted to developing analytical approximations for Fermi-Dirac Integrals since numerical computations of Fermi-Dirac Integrals are difficult to use in semiconductor devices, although there are several highly accurate tabulated functions available. Most of these analytical expressions are not sufficiently suitable to be employed in semiconductor device applications due to their poor accuracy, the requirement of complicated calculations, and difficulties in differentiating and integrating. A new approximation has been developed for the Fermi-Dirac integrals of the order 1/2 by using Prony's method and discussed in this paper. The approximation is accurate enough (Mean Absolute Error (MAE) = 0.38%) and easy enough to be used in semiconductor device equations. The new approximation of Fermi-Dirac Integrals is applied to a more generalized Einstein Relation which is an important relation in semiconductor devices.

  13. Semiconductor technology program. Progress briefs

    NASA Technical Reports Server (NTRS)

    Bullis, W. M. (Editor)

    1979-01-01

    The current status of NBS work on measurement technology for semiconductor materials, process control, and devices is reported. Results of both in-house and contract research are covered. Highlighted activities include modeling of diffusion processes, analysis of model spreading resistance data, and studies of resonance ionization spectroscopy, resistivity-dopant density relationships in p-type silicon, deep level measurements, photoresist sensitometry, random fault measurements, power MOSFET thermal characteristics, power transistor switching characteristics, and gross leak testing. New and selected on-going projects are described. Compilations of recent publications and publications in press are included.

  14. Total-dose radiation effects data for semiconductor devices, volume 1. [radiation resistance of components for the Galileo Project

    NASA Technical Reports Server (NTRS)

    Price, W. E.; Martin, K. E.; Nichols, D. K.; Gauthier, M. K.; Brown, S. F.

    1981-01-01

    Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. Data are presented by JPL for various NASA space programs on diodes, bipolar transistors, field effect transistors, silicon-controlled rectifiers, and optical devices. A vendor identification code list is included along with semiconductor device electrical parameter symbols and abbreviations.

  15. Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Hu, Gangyi; Wijesinghe, Udumbara; Naquin, Clint; Maggio, Ken; Edwards, H. L.; Lee, Mark

    2017-10-01

    Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

  16. Semiconductor-based, large-area, flexible, electronic devices

    DOEpatents

    Goyal, Amit [Knoxville, TN

    2011-03-15

    Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  17. Semiconductor-based, large-area, flexible, electronic devices on {110}<100> oriented substrates

    DOEpatents

    Goyal, Amit

    2014-08-05

    Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  18. [100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices

    DOEpatents

    Goyal, Amit

    2015-03-24

    Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  19. Excitonic Materials for Hybrid Solar Cells and Energy Efficient Lighting

    NASA Astrophysics Data System (ADS)

    Kabra, Dinesh; Lu, Li Ping; Vaynzof, Yana; Song, Myounghoon; Snaith, Henry J.; Friend, Richard H.

    2011-07-01

    Conventional photovoltaic technology will certainly contribute this century, but to generate a significant fraction of our global power from solar energy, a radically new disruptive technology is required. Research primarily focused on developing the physics and technologies being low cost photovoltaic concepts are required. The materials with carbon-based solution processible organic semiconductors with power conversion efficiency as high as ˜8.2%, which have emerged over the last decade as promising alternatives to expensive silicon based technologies. We aim at exploring the morphological and optoelectronic properties of blends of newly synthesized polymer semiconductors as a route to enhance the performance of organic semiconductor based optoelectronic devices, like photovoltaic diodes (PV) and Light Emitting Diodes (LED). OLED efficiency has reached upto 150 lm/W and going to be next generation cheap and eco friendly solid state lighting solution. Hybrid electronics represent a valuable alternative for the production of easy processible, flexible and reliable optoelectronic thin film devices. I will be presenting recent advancement of my work in the area of hybrid photovoltaics, PLED and research path towards realization electrically injectable organic laser diodes.

  20. Doped polymer semiconductors with ultrahigh and ultralow work functions for ohmic contacts.

    PubMed

    Tang, Cindy G; Ang, Mervin C Y; Choo, Kim-Kian; Keerthi, Venu; Tan, Jun-Kai; Syafiqah, Mazlan Nur; Kugler, Thomas; Burroughes, Jeremy H; Png, Rui-Qi; Chua, Lay-Lay; Ho, Peter K H

    2016-11-24

    To make high-performance semiconductor devices, a good ohmic contact between the electrode and the semiconductor layer is required to inject the maximum current density across the contact. Achieving ohmic contacts requires electrodes with high and low work functions to inject holes and electrons respectively, where the work function is the minimum energy required to remove an electron from the Fermi level of the electrode to the vacuum level. However, it is challenging to produce electrically conducting films with sufficiently high or low work functions, especially for solution-processed semiconductor devices. Hole-doped polymer organic semiconductors are available in a limited work-function range, but hole-doped materials with ultrahigh work functions and, especially, electron-doped materials with low to ultralow work functions are not yet available. The key challenges are stabilizing the thin films against de-doping and suppressing dopant migration. Here we report a general strategy to overcome these limitations and achieve solution-processed doped films over a wide range of work functions (3.0-5.8 electronvolts), by charge-doping of conjugated polyelectrolytes and then internal ion-exchange to give self-compensated heavily doped polymers. Mobile carriers on the polymer backbone in these materials are compensated by covalently bonded counter-ions. Although our self-compensated doped polymers superficially resemble self-doped polymers, they are generated by separate charge-carrier doping and compensation steps, which enables the use of strong dopants to access extreme work functions. We demonstrate solution-processed ohmic contacts for high-performance organic light-emitting diodes, solar cells, photodiodes and transistors, including ohmic injection of both carrier types into polyfluorene-the benchmark wide-bandgap blue-light-emitting polymer organic semiconductor. We also show that metal electrodes can be transformed into highly efficient hole- and electron-injection contacts via the self-assembly of these doped polyelectrolytes. This consequently allows ambipolar field-effect transistors to be transformed into high-performance p- and n-channel transistors. Our strategy provides a method for producing ohmic contacts not only for organic semiconductors, but potentially for other advanced semiconductors as well, including perovskites, quantum dots, nanotubes and two-dimensional materials.

  1. Cycling excitation process: An ultra efficient and quiet signal amplification mechanism in semiconductor

    NASA Astrophysics Data System (ADS)

    Liu, Yu-Hsin; Yan, Lujiang; Zhang, Alex Ce; Hall, David; Niaz, Iftikhar Ahmad; Zhou, Yuchun; Sham, L. J.; Lo, Yu-Hwa

    2015-08-01

    Signal amplification, performed by transistor amplifiers with its merit rated by the efficiency and noise characteristics, is ubiquitous in all electronic systems. Because of transistor thermal noise, an intrinsic signal amplification mechanism, impact ionization was sought after to complement the limits of transistor amplifiers. However, due to the high operation voltage (30-200 V typically), low power efficiency, limited scalability, and, above all, rapidly increasing excess noise with amplification factor, impact ionization has been out of favor for most electronic systems except for a few applications such as avalanche photodetectors and single-photon Geiger detectors. Here, we report an internal signal amplification mechanism based on the principle of the phonon-assisted cycling excitation process (CEP). Si devices using this concept show ultrahigh gain, low operation voltage, CMOS compatibility, and, above all, quantum limit noise performance that is 30 times lower than devices using impact ionization. Established on a unique physical effect of attractive properties, CEP-based devices can potentially revolutionize the fields of semiconductor electronics.

  2. Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

    NASA Astrophysics Data System (ADS)

    Almuslem, A. S.; Hanna, A. N.; Yapici, T.; Wehbe, N.; Diallo, E. M.; Kutbee, A. T.; Bahabry, R. R.; Hussain, M. M.

    2017-02-01

    In the recent past, with the advent of transient electronics for mostly implantable and secured electronic applications, the whole field effect transistor structure has been dissolved in a variety of chemicals. Here, we show simple water soluble nano-scale (sub-10 nm) germanium oxide (GeO2) as the dissolvable component to remove the functional structures of metal oxide semiconductor devices and then reuse the expensive germanium substrate again for functional device fabrication. This way, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured and billions are disposed, which extend the harmful impact to our environment. Therefore, this is a key study to show a pragmatic approach for water soluble high performance electronics for environmentally friendly manufacturing and bioresorbable electronic applications.

  3. Nanoscale doping of compound semiconductors by solid phase dopant diffusion

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Ahn, Jaehyun, E-mail: jaehyun.ahn@utexas.edu; Koh, Donghyi; Roy, Anupam

    2016-03-21

    Achieving damage-free, uniform, abrupt, ultra-shallow junctions while simultaneously controlling the doping concentration on the nanoscale is an ongoing challenge to the scaling down of electronic device dimensions. Here, we demonstrate a simple method of effectively doping ΙΙΙ-V compound semiconductors, specifically InGaAs, by a solid phase doping source. This method is based on the in-diffusion of oxygen and/or silicon from a deposited non-stoichiometric silicon dioxide (SiO{sub x}) film on InGaAs, which then acts as donors upon activation by annealing. The dopant profile and concentration can be controlled by the deposited film thickness and thermal annealing parameters, giving active carrier concentration ofmore » 1.4 × 10{sup 18 }cm{sup −3}. Our results also indicate that conventional silicon based processes must be carefully reviewed for compound semiconductor device fabrication to prevent unintended doping.« less

  4. Conductors and semiconductors for advanced organic electronics

    NASA Astrophysics Data System (ADS)

    Meyer-Friedrichsen, Timo; Elschner, Andreas; Keohan, Frank; Lövenich, Wilfried; Ponomarenko, Sergei A.

    2009-08-01

    The development of suitable materials for organic electronics is still one of the key points to access new application areas with this promising technology. Semiconductors based on thiophene chemistry show very high charge carrier mobilities. The functionalization with linker groups provided materials that built monomolecular layers of the semiconductors on the hydrolyzed oxide surface of a silicon-wafer. This approach lead to self-assembled mono-layer field-effect transistors (SAM-FETs) with mobilities of up to 0.04 cm2/Vs, which is comparable to the values of the respective bulk thin film. Transparent inorganic conductors like ITO are highly conductive but the costly processing and the brittleness hamper their use in cost-sensitive and/or flexible devices. Highly conductive PEDOT-grades have been developed with conductivities of up to 1000 S/cm which are easily applicable by printing techniques and can be used as ITO replacement in devices such as touch panels or organic photovoltaics.

  5. Multi-material optoelectronic fiber devices

    NASA Astrophysics Data System (ADS)

    Sorin, F.; Yan, Wei; Volpi, Marco; Page, Alexis G.; Nguyen Dang, Tung; Qu, Y.

    2017-05-01

    The recent ability to integrate materials with different optical and optoelectronic properties in prescribed architectures within flexible fibers is enabling novel opportunities for advanced optical probes, functional surfaces and smart textiles. In particular, the thermal drawing process has known a series of breakthroughs in recent years that have expanded the range of materials and architectures that can be engineered within uniform fibers. Of particular interest in this presentation will be optoelectronic fibers that integrate semiconductors electrically addressed by conducting materials. These long, thin and flexible fibers can intercept optical radiation, localize and inform on a beam direction, detect its wavelength and even harness its energy. They hence constitute ideal candidates for applications such as remote and distributed sensing, large-area optical-detection arrays, energy harvesting and storage, innovative health care solutions, and functional fabrics. To improve performance and device complexity, tremendous progresses have been made in terms of the integrated semiconductor architectures, evolving from large fiber solid-core, to sub-hundred nanometer thin-films, nano-filaments and even nanospheres. To bridge the gap between the optoelectronic fiber concept and practical applications however, we still need to improve device performance and integration. In this presentation we will describe the materials and processing approaches to realize optoelectronic fibers, as well as give a few examples of demonstrated systems for imaging as well as light and chemical sensing. We will then discuss paths towards practical applications focusing on two main points: fiber connectivity, and improving the semiconductor microstructure by developing scalable approaches to make fiber-integrated single-crystal nanowire based devices.

  6. Lithography for enabling advances in integrated circuits and devices.

    PubMed

    Garner, C Michael

    2012-08-28

    Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

  7. Colloidal core-seeded semiconductor nanorods as fluorescent labels for in-vitro diagnostics (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Chan, YinThai

    2016-03-01

    Colloidal semiconductor nanocrystals are ideal fluorophores for clinical diagnostics, therapeutics, and highly sensitive biochip applications due to their high photostability, size-tunable color of emission and flexible surface chemistry. The relatively recent development of core-seeded semiconductor nanorods showed that the presence of a rod-like shell can confer even more advantageous physicochemical properties than their spherical counterparts, such as large multi-photon absorption cross-sections and facet-specific chemistry that can be exploited to deposit secondary nanoparticles. It may be envisaged that these highly fluorescent nanorods can be integrated with large scale integrated (LSI) microfluidic systems that allow miniaturization and integration of multiple biochemical processes in a single device at the nanoliter scale, resulting in a highly sensitive and automated detection platform. In this talk, I will describe a LSI microfluidic device that integrates RNA extraction, reverse transcription to cDNA, amplification and target pull-down to detect histidine decarboxylase (HDC) gene directly from human white blood cells samples. When anisotropic colloidal semiconductor nanorods (NRs) were used as the fluorescent readout, the detection limit was found to be 0.4 ng of total RNA, which was much lower than that obtained using spherical quantum dots (QDs) or organic dyes. This was attributed to the large action cross-section of NRs and their high probability of target capture in a pull-down detection scheme. The combination of large scale integrated microfluidics with highly fluorescent semiconductor NRs may find widespread utility in point-of-care devices and multi-target diagnostics.

  8. Micro-Raman spectroscopy as a tool for the characterization of silicon carbide in power semiconductor material processing

    NASA Astrophysics Data System (ADS)

    De Biasio, M.; Kraft, M.; Schultz, M.; Goller, B.; Sternig, D.; Esteve, R.; Roesner, M.

    2017-05-01

    Silicon carbide (SiC) is a wide band-gap semi-conductor material that is used increasingly for high voltage power devices, since it has a higher breakdown field strength and better thermal conductivity than silicon. However, in particular its hardness makes wafer processing difficult and many standard semi-conductor processes have to be specially adapted. We measure the effects of (i) mechanical processing (i.e. grinding of the backside) and (ii) chemical and thermal processing (i.e. doping and annealing), using confocal microscopy to measure the surface roughness of ground wafers and micro-Raman spectroscopy to measure the stresses induced in the wafers by grinding. 4H-SiC wafers with different dopings were studied before and after annealing, using depth-resolved micro-Raman spectroscopy to observe how doping and annealing affect: i.) the damage and stresses induced on the crystalline structure of the samples and ii.) the concentration of free electrical carriers. Our results show that mechanical, chemical and thermal processing techniques have effects on this semiconductor material that can be observed and characterized using confocal microscopy and high resolution micro Raman spectroscopy.

  9. Photovoltaic healing of non-uniformities in semiconductor devices

    DOEpatents

    Karpov, Victor G.; Roussillon, Yann; Shvydka, Diana; Compaan, Alvin D.; Giolando, Dean M.

    2006-08-29

    A method of making a photovoltaic device using light energy and a solution to normalize electric potential variations in the device. A semiconductor layer having nonuniformities comprising areas of aberrant electric potential deviating from the electric potential of the top surface of the semiconductor is deposited onto a substrate layer. A solution containing an electrolyte, at least one bonding material, and positive and negative ions is applied over the top surface of the semiconductor. Light energy is applied to generate photovoltage in the semiconductor, causing a redistribution of the ions and the bonding material to the areas of aberrant electric potential. The bonding material selectively bonds to the nonuniformities in a manner such that the electric potential of the nonuniformities is normalized relative to the electric potential of the top surface of the semiconductor layer. A conductive electrode layer is then deposited over the top surface of the semiconductor layer.

  10. Highly Crystalline C8-BTBT Thin-Film Transistors by Lateral Homo-Epitaxial Growth on Printed Templates.

    PubMed

    Janneck, Robby; Pilet, Nicolas; Bommanaboyena, Satya Prakash; Watts, Benjamin; Heremans, Paul; Genoe, Jan; Rolin, Cedric

    2017-11-01

    Highly crystalline thin films of organic semiconductors offer great potential for fundamental material studies as well as for realizing high-performance, low-cost flexible electronics. The fabrication of these films directly on inert substrates is typically done by meniscus-guided coating techniques. The resulting layers show morphological defects that hinder charge transport and induce large device-to-device variability. Here, a double-step method for organic semiconductor layers combining a solution-processed templating layer and a lateral homo-epitaxial growth by a thermal evaporation step is reported. The epitaxial regrowth repairs most of the morphological defects inherent to meniscus-guided coatings. The resulting film is highly crystalline and features a mobility increased by a factor of three and a relative spread in device characteristics improved by almost half an order of magnitude. This method is easily adaptable to other coating techniques and offers a route toward the fabrication of high-performance, large-area electronics based on highly crystalline thin films of organic semiconductors. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  11. Small molecule organic semiconductors on the move: promises for future solar energy technology.

    PubMed

    Mishra, Amaresh; Bäuerle, Peter

    2012-02-27

    This article is written from an organic chemist's point of view and provides an up-to-date review about organic solar cells based on small molecules or oligomers as absorbers and in detail deals with devices that incorporate planar-heterojunctions (PHJ) and bulk heterojunctions (BHJ) between a donor (p-type semiconductor) and an acceptor (n-type semiconductor) material. The article pays particular attention to the design and development of molecular materials and their performance in corresponding devices. In recent years, a substantial amount of both, academic and industrial research, has been directed towards organic solar cells, in an effort to develop new materials and to improve their tunability, processability, power conversion efficiency, and stability. On the eve of commercialization of organic solar cells, this review provides an overview over efficiencies attained with small molecules/oligomers in OSCs and reflects materials and device concepts developed over the last decade. Approaches to enhancing the efficiency of organic solar cells are analyzed. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. Process for fabricating a charge coupled device

    DOEpatents

    Conder, Alan D.; Young, Bruce K. F.

    2002-01-01

    A monolithic three dimensional charged coupled device (3D-CCD) which utilizes the entire bulk of the semiconductor for charge generation, storage, and transfer. The 3D-CCD provides a vast improvement of current CCD architectures that use only the surface of the semiconductor substrate. The 3D-CCD is capable of developing a strong E-field throughout the depth of the semiconductor by using deep (buried) parallel (bulk) electrodes in the substrate material. Using backside illumination, the 3D-CCD architecture enables a single device to image photon energies from the visible, to the ultra-violet and soft x-ray, and out to higher energy x-rays of 30 keV and beyond. The buried or bulk electrodes are electrically connected to the surface electrodes, and an E-field parallel to the surface is established with the pixel in which the bulk electrodes are located. This E-field attracts charge to the bulk electrodes independent of depth and confines it within the pixel in which it is generated. Charge diffusion is greatly reduced because the E-field is strong due to the proximity of the bulk electrodes.

  13. {100}<100> or 45.degree.-rotated {100}<100>, semiconductor-based, large-area, flexible, electronic devices

    DOEpatents

    Goyal, Amit [Knoxville, TN

    2012-05-15

    Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45.degree.-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  14. Photoelectrochemical devices for solar water splitting - materials and challenges.

    PubMed

    Jiang, Chaoran; Moniz, Savio J A; Wang, Aiqin; Zhang, Tao; Tang, Junwang

    2017-07-31

    It is widely accepted within the community that to achieve a sustainable society with an energy mix primarily based on solar energy we need an efficient strategy to convert and store sunlight into chemical fuels. A photoelectrochemical (PEC) device would therefore play a key role in offering the possibility of carbon-neutral solar fuel production through artificial photosynthesis. The past five years have seen a surge in the development of promising semiconductor materials. In addition, low-cost earth-abundant co-catalysts are ubiquitous in their employment in water splitting cells due to the sluggish kinetics of the oxygen evolution reaction (OER). This review commences with a fundamental understanding of semiconductor properties and charge transfer processes in a PEC device. We then describe various configurations of PEC devices, including single light-absorber cells and multi light-absorber devices (PEC, PV-PEC and PV/electrolyser tandem cell). Recent progress on both photoelectrode materials (light absorbers) and electrocatalysts is summarized, and important factors which dominate photoelectrode performance, including light absorption, charge separation and transport, surface chemical reaction rate and the stability of the photoanode, are discussed. Controlling semiconductor properties is the primary concern in developing materials for solar water splitting. Accordingly, strategies to address the challenges for materials development in this area, such as the adoption of smart architectures, innovative device configuration design, co-catalyst loading, and surface protection layer deposition, are outlined throughout the text, to deliver a highly efficient and stable PEC device for water splitting.

  15. Dynamic carrier transport modulation for constructing advanced devices with improved performance by piezotronic and piezo-phototronic effects: a brief review

    NASA Astrophysics Data System (ADS)

    Guo, Zhen; Pan, Haixi; Li, Chuanyu; Zhang, Lili; Yan, Shuai; Zhang, Wei; Yao, Jia; Tang, Yuguo; Yang, Hongbo; Wu, Yihui; Feng, Liping; Zhou, Lianqun

    2017-08-01

    Carrier generation, transport, separation, and recombination behaviors can be modulated for improving the performance of semiconductor devices by using piezotronic and piezo-phototronic effects with creating piezopotential in crystals based on non-centrosymmetric semiconductor materials such as group II-VI and III-V semiconductors and transition metal dichalcogenides (TMDCs), which have emerged as attractive materials for electronic/photonic applications because of their novel properties. Until now, much effort has been devoted to improving the performance of devices based on the aforementioned materials through modulation of the carrier behavior. However, due to existing drawbacks, it has been difficult to further enhance the device performance for a built structure. However, effective exploration of the piezotronic and piezo-phototronic effects in these semiconducting materials could pave the way to the realization of high-performance devices. In general, the effective modulation of carrier behavior dynamically in devices such as light-emitting diodes, photodetectors, solar cells, nanogenerators, and so on, remains a key challenge. Due to the polarization of ions in semiconductor materials with noncentral symmetry under external strain, a piezopotential is created considering piezotronic and piezo-photoronic effects, which could dynamically modulate charge carrier transport behaviors across p-n junctions or metal-semiconductor interfaces. Through a combination of these effects and semiconductor properties, the performance of the related devices could be improved and new types of devices such as piezoelectric field-effect transistors and sensors have emerged, with potential applications in self-driven devices for effective energy harvesting and biosensing with high sensitivity, which are different from those traditionally designed and may have potential applications in strained triggered devices. The objective of this review is to briefly introduce the corresponding mechanisms for modulating carrier behavior on the basis of piezotronic and piezo-phototronic effects in materials such as group II-VI and group III-V semiconductors and TMDCs, as well as to discuss possible solutions to effectively enhance the performance of the devices via carrier modulation.

  16. Solid state photosensitive devices which employ isolated photosynthetic complexes

    DOEpatents

    Peumans, Peter; Forrest, Stephen R.

    2009-09-22

    Solid state photosensitive devices including photovoltaic devices are provided which comprise a first electrode and a second electrode in superposed relation; and at least one isolated Light Harvesting Complex (LHC) between the electrodes. Preferred photosensitive devices comprise an electron transport layer formed of a first photoconductive organic semiconductor material, adjacent to the LHC, disposed between the first electrode and the LHC; and a hole transport layer formed of a second photoconductive organic semiconductor material, adjacent to the LHC, disposed between the second electrode and the LHC. Solid state photosensitive devices of the present invention may comprise at least one additional layer of photoconductive organic semiconductor material disposed between the first electrode and the electron transport layer; and at least one additional layer of photoconductive organic semiconductor material, disposed between the second electrode and the hole transport layer. Methods of generating photocurrent are provided which comprise exposing a photovoltaic device of the present invention to light. Electronic devices are provided which comprise a solid state photosensitive device of the present invention.

  17. Looking into the crystal ball: future device learning using hybrid e-beam and optical lithography (Keynote Paper)

    NASA Astrophysics Data System (ADS)

    Steen, S. E.; McNab, S. J.; Sekaric, L.; Babich, I.; Patel, J.; Bucchignano, J.; Rooks, M.; Fried, D. M.; Topol, A. W.; Brancaccio, J. R.; Yu, R.; Hergenrother, J. M.; Doyle, J. P.; Nunes, R.; Viswanathan, R. G.; Purushothaman, S.; Rothwell, M. B.

    2005-05-01

    Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node. To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond. In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the world's smallest working SRAM cell.

  18. Method for making a monolithic integrated high-T.sub.c superconductor-semiconductor structure

    NASA Technical Reports Server (NTRS)

    Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Russell, Stephen D. (Inventor); Garcia, Graham A. (Inventor); Barfknecht, Andrew T. (Inventor); Clayton, Stanley R. (Inventor)

    2000-01-01

    A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

  19. Tapered rib fiber coupler for semiconductor optical devices

    DOEpatents

    Vawter, Gregory A.; Smith, Robert Edward

    2001-01-01

    A monolithic tapered rib waveguide for transformation of the spot size of light between a semiconductor optical device and an optical fiber or from the fiber into the optical device. The tapered rib waveguide is integrated into the guiding rib atop a cutoff mesa type semiconductor device such as an expanded mode optical modulator or and expanded mode laser. The tapered rib acts to force the guided light down into the mesa structure of the semiconductor optical device instead of being bound to the interface between the bottom of the guiding rib and the top of the cutoff mesa. The single mode light leaving or entering the output face of the mesa structure then can couple to the optical fiber at coupling losses of 1.0 dB or less.

  20. Silicon superlattices: Theory and application to semiconductor devices

    NASA Technical Reports Server (NTRS)

    Moriarty, J. A.

    1981-01-01

    Silicon superlattices and their applicability to improved semiconductor devices were studied. The device application potential of the atomic like dimension of III-V semiconductor superlattices fabricated in the form of ultrathin periodically layered heterostructures was examined. Whether this leads to quantum size effects and creates the possibility to alter familiar transport and optical properties over broad physical ranges was studied. Applications to improved semiconductor lasers and electrondevices were achieved. Possible application of silicon sperlattices to faster high speed computing devices was examined. It was found that the silicon lattices show features of smaller fundamental energyband gaps and reduced effective masses. The effects correlate strongly with both the chemical and geometrical nature of the superlattice.

  1. Process tool monitoring and matching using interferometry technique

    NASA Astrophysics Data System (ADS)

    Anberg, Doug; Owen, David M.; Mileham, Jeffrey; Lee, Byoung-Ho; Bouche, Eric

    2016-03-01

    The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today's manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield. In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.

  2. Role of Polymorphism and Thin-Film Morphology in Organic Semiconductors Processed by Solution Shearing

    PubMed Central

    2018-01-01

    Organic semiconductors (OSCs) are promising materials for cost-effective production of electronic devices because they can be processed from solution employing high-throughput techniques. However, small-molecule OSCs are prone to structural modifications because of the presence of weak van der Waals intermolecular interactions. Hence, controlling the crystallization in these materials is pivotal to achieve high device reproducibility. In this perspective article, we focus on controlling polymorphism and morphology in small-molecule organic semiconducting thin films deposited by solution-shearing techniques compatible with roll-to-roll systems. Special attention is paid to the influence that the different experimental deposition parameters can have on thin films. Further, the main characterization techniques for thin-film structures are reviewed, highlighting the in situ characterization tools that can provide crucial insights into the crystallization mechanisms. PMID:29503976

  3. Solution-processed, Self-organized Organic Single Crystal Arrays with Controlled Crystal Orientation

    PubMed Central

    Kumatani, Akichika; Liu, Chuan; Li, Yun; Darmawan, Peter; Takimiya, Kazuo; Minari, Takeo; Tsukagoshi, Kazuhito

    2012-01-01

    A facile solution process for the fabrication of organic single crystal semiconductor devices which meets the demand for low-cost and large-area fabrication of high performance electronic devices is demonstrated. In this paper, we develop a bottom-up method which enables direct formation of organic semiconductor single crystals at selected locations with desired orientations. Here oriented growth of one-dimensional organic crystals is achieved by using self-assembly of organic molecules as the driving force to align these crystals in patterned regions. Based upon the self-organized organic single crystals, we fabricate organic field effect transistor arrays which exhibit an average field-effect mobility of 1.1 cm2V−1s−1. This method can be carried out under ambient atmosphere at room temperature, thus particularly promising for production of future plastic electronics. PMID:22563523

  4. Progress in Piezo-Phototronic-Effect-Enhanced Light-Emitting Diodes and Pressure Imaging.

    PubMed

    Pan, Caofeng; Chen, Mengxiao; Yu, Ruomeng; Yang, Qing; Hu, Youfan; Zhang, Yan; Wang, Zhong Lin

    2016-02-24

    Wurtzite materials exhibit both semiconductor and piezoelectric properties under strains due to the non-central symmetric crystal structures. The three-way coupling of semiconductor properties, piezoelectric polarization and optical excitation in ZnO, GaN, CdS and other piezoelectric semiconductors leads to the emerging field of piezo-phototronics. This effect can efficiently manipulate the emission intensity of light-emitting diodes (LEDs) by utilizing the piezo-polarization charges created at the junction upon straining to modulate the energy band diagrams and the optoelectronic processes, such as generation, separation, recombination and/or transport of charge carriers. Starting from fundamental physics principles, recent progress in piezo-phototronic-effect-enhanced LEDs is reviewed; following their development from single-nanowire pressure-sensitive devices to high-resolution array matrices for pressure-distribution mapping applications. The piezo-phototronic effect provides a promising method to enhance the light emission of LEDs based on piezoelectric semiconductors through applying static strains, and may find perspective applications in various optoelectronic devices and integrated systems. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. Evolution of corundum-structured III-oxide semiconductors: Growth, properties, and devices

    NASA Astrophysics Data System (ADS)

    Fujita, Shizuo; Oda, Masaya; Kaneko, Kentaro; Hitora, Toshimi

    2016-12-01

    The recent progress and development of corundum-structured III-oxide semiconductors are reviewed. They allow bandgap engineering from 3.7 to ∼9 eV and function engineering, leading to highly durable electronic devices and deep ultraviolet optical devices as well as multifunctional devices. Mist chemical vapor deposition can be a simple and safe growth technology and is advantageous for reducing energy and cost for the growth. This is favorable for the wide commercial use of devices at low cost. The III-oxide semiconductors are promising candidates for new devices contributing to sustainable social, economic, and technological development for the future.

  6. Economic analysis of crystal growth in space

    NASA Technical Reports Server (NTRS)

    Ulrich, D. R.; Chung, A. M.; Yan, C. S.; Mccreight, L. R.

    1972-01-01

    Many advanced electronic technologies and devices for the 1980's are based on sophisticated compound single crystals, i.e. ceramic oxides and compound semiconductors. Space processing of these electronic crystals with maximum perfection, purity, and size is suggested. No ecomonic or technical justification was found for the growth of silicon single crystals for solid state electronic devices in space.

  7. Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal

    NASA Technical Reports Server (NTRS)

    Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor)

    2011-01-01

    Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.

  8. Excitonic processes at organic heterojunctions

    NASA Astrophysics Data System (ADS)

    He, ShouJie; Lu, ZhengHong

    2018-02-01

    Understanding excitonic processes at organic heterojunctions is crucial for development of organic semiconductor devices. This article reviews recent research on excitonic physics that involve intermolecular charge transfer (CT) excitons, and progress on understanding relationships between various interface energy levels and key parameters governing various competing interface excitonic processes. These interface excitonic processes include radiative exciplex emission, nonradiative recombination, Auger electron emission, and CT exciton dissociation. This article also reviews various device applications involving interface CT excitons, such as organic light-emitting diodes (OLEDs), organic photovoltaic cells, organic rectifying diodes, and ultralow-voltage Auger OLEDs.

  9. Body of Knowledge (BOK) for Copper Wire Bonds

    NASA Technical Reports Server (NTRS)

    Rutkowski, E.; Sampson, M. J.

    2015-01-01

    Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate - approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling. Despite the difficult problems associated with the changeover to copper bonding wire, there are billions of copper wire bonded devices delivered annually to customers. It is noteworthy that Texas Instruments announced in October of 2014 that they are shipping microcircuits containing copper wire bonds for safety critical automotive applications. An evaluation of copper wire bond technology for applicability to spaceflight hardware may be warranted along with concurrently compiling a comprehensive understanding of the failure mechanisms involved with copper wire bonded semiconductor devices.

  10. Semiconductor materials for high frequency solid state sources

    NASA Astrophysics Data System (ADS)

    Grubin, H. L.

    1983-03-01

    The broad goal of the subject contract is to suggest candidate materials for high frequency device operation. During the initial phase of the study, attention has been focused on defining the general role of the band structure and associated scattering processes in determining the response of semiconductors to transient high-speed electrical signals. Moments of the Boltzmann transport equation form the basis of the study, and the scattering rates define the semiconductor under study. The selection of semiconductor materials proceeds from a set of simple, yet significant, set of scaling principles. During the first quarter scaling was associated with what can formally be identified as velocity invariants, but which in more practical terms identifies the relative speed advantages of e.g., InP over GaAs.

  11. Interconnected semiconductor devices

    DOEpatents

    Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

    1990-10-23

    Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

  12. Spin Coherence at the Nanoscale: Polymer Surfaces and Interfaces

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Epstein, Arthur J.

    2013-09-10

    Breakthrough results were achieved during the reporting period in the areas of organic spintronics. (A) For the first time the giant magnetic resistance (GMR) was observed in spin valve with an organic spacer. Thus we demonstrated the ability of organic semiconductors to transport spin in GMR devices using rubrene as a prototype for organic semiconductors. (B) We discovered the electrical bistability and spin valve effect in a ferromagnet /organic semiconductor/ ferromagnet heterojunction. The mechanism of switching between conducting phases and its potential applications were suggested. (C) The ability of V(TCNE)x to inject spin into organic semiconductors such as rubrene wasmore » demonstrated for the first time. The mechanisms of spin injection and transport from and into organic magnets as well through organic semiconductors were elucidated. (D) In collaboration with the group of OSU Prof. Johnston-Halperin we reported the successful extraction of spin polarized current from a thin film of the organic-based room temperature ferrimagnetic semiconductor V[TCNE]x and its subsequent injection into a GaAs/AlGaAs light-emitting diode (LED). Thus all basic steps for fabrication of room temperature, light weight, flexible all organic spintronic devices were successfully performed. (E) A new synthesis/processing route for preparation of V(TCNE)x enabling control of interface and film thicknesses at the nanoscale was developed at OSU. Preliminary results show these films are higher quality and what is extremely important they are substantially more air stable than earlier prepared V(TCNE)x. In sum the breakthrough results we achieved in the past two years form the basis of a promising new technology, Multifunctional Flexible Organic-based Spintronics (MFOBS). MFOBS technology enables us fabrication of full function flexible spintronic devices that operate at room temperature.« less

  13. Surface chemistry relevant to material processing for semiconductor devices

    NASA Astrophysics Data System (ADS)

    Okada, Lynne Aiko

    Metal-oxide-semiconductor (MOS) structures are the core of many modern integrated circuit (IC) devices. Each material utilized in the different regions of the device has its own unique chemistry. Silicon is the base semiconductor material used in the majority of these devices. With IC device complexity increasing and device dimensions decreasing, understanding material interactions and processing becomes increasingly critical. Hsb2 desorption is the rate-limiting step in silicon growth using silane under low temperature conditions. Activation energies for Hsb2 desorption measured during Si chemical vapor deposition (CVD) versus single-crystal studies are found to be significantly lower. It has been proposed that defect sites on the silicon surface could explain the observed differences. Isothermal Hsb2 desorption studies using laser induced thermal desorption (LITD) techniques have addressed this issue. The growth of low temperature oxides is another relevant issue for fabrication of IC devices. Recent studies using 1,4-disilabutane (DSB) (SiHsb3CHsb2CHsb2SiHsb3) at 100sp°C in ambient Osb2 displayed the successful low temperature growth of silicon dioxide (SiOsb2). However, these studies provided no information about the deposition mechanism. We performed LITD and Fourier transform infrared (FTIR) studies on single-crystal and porous silicon surfaces to examine the adsorption, decomposition, and desorption processes to determine the deposition mechanism. Titanium nitride (TiN) diffusion barriers are necessary in modern metallization structures. Controlled deposition using titanium tetrachloride (TiClsb4) and ammonia (NHsb3) has been demonstrated using atomic layered processing (ALP) techniques. We intended to study the sequential deposition method by monitoring the surface intermediates using LITD techniques. However, formation of a Cl impurity source, ammonium chloride (NHsb4sp+Clsp-), was observed, thereby, limiting our ability for effective studies. Tetrakis(dimethylamino)titanium (Tilbrack N\\{CHsb3\\}sb2rbracksb4) (TDMAT) is another precursor used in the CVD deposition of TiN films in IC devices. Thermal decomposition studies have demonstrated deviations from conformal deposition. Successful conformal deposition may be affected by readsorption of the reaction product, dimethylamine (HNlbrack CHsb3rbracksb2). Detailed studies were performed using LITD techniques in order to understand the adsorption and desorption kinetics of TDMAT and dimethylamine to gain insights about the conformal deposition of TiN.

  14. “Playing around” with Field-Effect Sensors on the Basis of EIS Structures, LAPS and ISFETs

    PubMed Central

    Schöning, Michael J.

    2005-01-01

    Microfabricated semiconductor devices are becoming increasingly relevant, also for the detection of biological and chemical quantities. Especially, the “marriage” of biomolecules and silicon technology often yields successful new sensor concepts. The fabrication techniques of such silicon-based chemical sensors and biosensors, respectively, will have a distinct impact in different fields of application such as medicine, food technology, environment, chemistry and biotechnology as well as information processing. Moreover, scientists and engineers are interested in the analytical benefits of miniaturised and microfabricated sensor devices. This paper gives a survey on different types of semiconductor-based field-effect structures that have been recently developed in our laboratory.

  15. Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems

    DOEpatents

    Welch, James D.

    2003-09-23

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.

  16. A Thermal and Electrical Analysis of Power Semiconductor Devices

    NASA Technical Reports Server (NTRS)

    Vafai, Kambiz

    1997-01-01

    The state-of-art power semiconductor devices require a thorough understanding of the thermal behavior for these devices. Traditional thermal analysis have (1) failed to account for the thermo-electrical interaction which is significant for power semiconductor devices operating at high temperature, and (2) failed to account for the thermal interactions among all the levels involved in, from the entire device to the gate micro-structure. Furthermore there is a lack of quantitative studies of the thermal breakdown phenomenon which is one of the major failure mechanisms for power electronics. This research work is directed towards addressing. Using a coupled thermal and electrical simulation, in which the drift-diffusion equations for the semiconductor and the energy equation for temperature are solved simultaneously, the thermo-electrical interactions at the micron scale of various junction structures are thoroughly investigated. The optimization of gate structure designs and doping designs is then addressed. An iterative numerical procedure which incorporates the thermal analysis at the device, chip and junction levels of the power device is proposed for the first time and utilized in a BJT power semiconductor device. In this procedure, interactions of different levels are fully considered. The thermal stability issue is studied both analytically and numerically in this research work in order to understand the mechanism for thermal breakdown.

  17. P and n-type microcrystalline semiconductor alloy material including band gap widening elements, devices utilizing same

    DOEpatents

    Guha, Subhendu; Ovshinsky, Stanford R.

    1988-10-04

    An n-type microcrystalline semiconductor alloy material including a band gap widening element; a method of fabricating p-type microcrystalline semiconductor alloy material including a band gap widening element; and electronic and photovoltaic devices incorporating said n-type and p-type materials.

  18. neutron-Induced Failures in semiconductor Devices

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Wender, Stephen Arthur

    2017-03-13

    Single Event Effects are a very significant failure mode in modern semiconductor devices that may limit their reliability. Accelerated testing is important for semiconductor industry. Considerable more work is needed in this field to mitigate the problem. Mitigation of this problem will probably come from Physicists and Electrical Engineers working together

  19. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-01

    ... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... No. 6,847,904 (``the '904 patent''). The complaint further alleges that an industry in the United...

  20. Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

    2003-01-01

    An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

  1. Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

    2000-01-01

    An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

  2. Semiconductor Quantum Electron Wave Transport, Diffraction, and Interference: Analysis, Device, and Measurement.

    NASA Astrophysics Data System (ADS)

    Henderson, Gregory Newell

    Semiconductor device dimensions are rapidly approaching a fundamental limit where drift-diffusion equations and the depletion approximation are no longer valid. In this regime, quantum effects can dominate device response. To increase further device density and speed, new devices must be designed that use these phenomena to positive advantage. In addition, quantum effects provide opportunities for a new class of devices which can perform functions previously unattainable with "conventional" semiconductor devices. This thesis has described research in the analysis of electron wave effects in semiconductors and the development of methods for the design, fabrication, and characterization of quantum devices based on these effects. First, an exact set of quantitative analogies are presented which allow the use of well understood optical design and analysis tools for the development of electron wave semiconductor devices. Motivated by these analogies, methods are presented for modeling electron wave grating diffraction using both an exact rigorous coupled-wave analysis and approximate analyses which are useful for grating design. Example electron wave grating switch and multiplexer designs are presented. In analogy to thin-film optics, the design and analysis of electron wave Fabry-Perot interference filters are also discussed. An innovative technique has been developed for testing these (and other) electron wave structures using Ballistic Electron Emission Microscopy (BEEM). This technique uses a liquid-helium temperature scanning tunneling microscope (STM) to perform spectroscopy of the electron transmittance as a function of electron energy. Experimental results show that BEEM can resolve even weak quantum effects, such as the reflectivity of a single interface between materials. Finally, methods are discussed for incorporating asymmetric electron wave Fabry-Perot filters into optoelectronic devices. Theoretical and experimental results show that such structures could be the basis for a new type of electrically pumped mid - to far-infrared semiconductor laser.

  3. Electric field induced spin-polarized current

    DOEpatents

    Murakami, Shuichi; Nagaosa, Naoto; Zhang, Shoucheng

    2006-05-02

    A device and a method for generating an electric-field-induced spin current are disclosed. A highly spin-polarized electric current is generated using a semiconductor structure and an applied electric field across the semiconductor structure. The semiconductor structure can be a hole-doped semiconductor having finite or zero bandgap or an undoped semiconductor of zero bandgap. In one embodiment, a device for injecting spin-polarized current into a current output terminal includes a semiconductor structure including first and second electrodes, along a first axis, receiving an applied electric field and a third electrode, along a direction perpendicular to the first axis, providing the spin-polarized current. The semiconductor structure includes a semiconductor material whose spin orbit coupling energy is greater than room temperature (300 Kelvin) times the Boltzmann constant. In one embodiment, the semiconductor structure is a hole-doped semiconductor structure, such as a p-type GaAs semiconductor layer.

  4. Liquid crystal cells with built-in CdSe nanotubes for chromogenic smart emission devices.

    PubMed

    Lin, Tsung Ju; Chen, Chin-Chang; Cheng, Soofin; Chen, Yang Fang

    2008-01-21

    A simple and general approach for controlling optical anisotropy of nanostructured semiconductors is reported. Our design involves the fabrication of liquid crystal devices with built-in semiconductor nanotubes. Quite interestingly, it is found that semiconductor nanotubes can be well aligned along the orientation of liquid crystals molecules automatically, resulting in a very large emission anisotropy with the degree of polarization up to 72%. This intriguing result manifests a way to obtain well aligned semiconductor nanotubes and the emission anisotropy can be easily manipulated by an external bias. The ability to well control the emission anisotropy should open up new opportunities for nanostructured semiconductors, including optical filters, polarized light emitting diodes, flat panel displays, and many other chromogenic smart devices.

  5. Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates

    DOEpatents

    Norman, Andrew G; Ptak, Aaron J

    2013-08-13

    Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

  6. Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Swain, Basudev, E-mail: Swain@iae.re.kr; Mishra, Chinmayee; Lee, Chan Gi

    2015-07-15

    Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga{sub 0.97}N{sub 0.9}O{sub 0.09} is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga{sub 0.97}N{sub 0.9}O{sub 0.09} of the MOCVD dust is leached at the optimum condition. Subsequently, the leachmore » residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4 M HCl, 100 °C and pulp density of 100 kg/m{sup 3,} respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. - Highlights: • Waste MOCVD dust is treated through mechanochemical leaching. • GaN is hardly leached, and converted to NaGaO{sub 2} through ball milling and annealing. • Process for gallium recovery from waste MOCVD dust has been developed. • Thermal analysis and phase properties of GaN to Ga{sub 2}O{sub 3} and GaN to NaGaO{sub 2} is revealed. • Solid-state chemistry involved in this process is reported.« less

  7. Design and fabrication of 6.1-.ANG. family semiconductor devices using semi-insulating A1Sb substrate

    DOEpatents

    Sherohman, John W [Livermore, CA; Coombs, III, Arthur W.; Yee, Jick Hong [Livermore, CA; Wu, Kuang Jen J [Cupertino, CA

    2007-05-29

    For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-.ANG. family heterostructure devices.

  8. Contributive research in compound semiconductor material and related devices

    NASA Astrophysics Data System (ADS)

    Twist, James R.

    1988-05-01

    The objective of this program was to provide the Electronic Device Branch (AFWAL/AADR) with the support needed to perform state of the art electronic device research. In the process of managing and performing on the project, UES has provided a wide variety of scientific and engineering talent who worked in-house for the Avionics Laboratory. These personnel worked on many different types of research programs from gas phase microwave driven lasers, CVD and MOCVD of electronic materials to Electronic Device Technology for new devices. The fields of research included MBE and theoretical research in this novel growth technique. Much of the work was slanted towards the rapidly developing technology of GaAs and the general thrust of the research that these tasks started has remained constant. This work was started because the Avionics Laboratory saw a chance to advance the knowledge and level of the current device technology by working in the compounds semiconductor field. UES is pleased to have had the opportunity to perform on this program and is looking forward to future efforts with the Avionics Laboratory.

  9. The application of charge-coupled device processors in automatic-control systems

    NASA Technical Reports Server (NTRS)

    Mcvey, E. S.; Parrish, E. A., Jr.

    1977-01-01

    The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.

  10. Progress in piezo-phototronic effect modulated photovoltaics.

    PubMed

    Que, Miaoling; Zhou, Ranran; Wang, Xiandi; Yuan, Zuqing; Hu, Guofeng; Pan, Caofeng

    2016-11-02

    Wurtzite structured materials, like ZnO, GaN, CdS, and InN, simultaneously possess semiconductor and piezoelectric properties. The inner-crystal piezopotential induced by external strain can effectively tune/control the carrier generation, transport and separation/combination processes at the metal-semiconductor contact or p-n junction, which is called the piezo-phototronic effect. This effect can efficiently enhance the performance of photovoltaic devices based on piezoelectric semiconductor materials by utilizing the piezo-polarization charges at the junction induced by straining, which can modulate the energy band of the piezoelectric material and then accelerate or prevent the separation process of the photon-generated electrons and vacancies. This paper introduces the fundamental physics principles of the piezo-phototronic effect, and reviews recent progress in piezo-phototronic effect enhanced solar cells, including solar cells based on semiconductor nanowire, organic/inorganic materials, quantum dots, and perovskite. The piezo-phototronic effect is suggested as a suitable basis for the development of an innovative method to enhance the performance of solar cells based on piezoelectric semiconductors by applied extrinsic strains, which might be appropriate for fundamental research and potential applications in various areas of optoelectronics.

  11. Progress in piezo-phototronic effect modulated photovoltaics

    NASA Astrophysics Data System (ADS)

    Que, Miaoling; Zhou, Ranran; Wang, Xiandi; Yuan, Zuqing; Hu, Guofeng; Pan, Caofeng

    2016-11-01

    Wurtzite structured materials, like ZnO, GaN, CdS, and InN, simultaneously possess semiconductor and piezoelectric properties. The inner-crystal piezopotential induced by external strain can effectively tune/control the carrier generation, transport and separation/combination processes at the metal-semiconductor contact or p-n junction, which is called the piezo-phototronic effect. This effect can efficiently enhance the performance of photovoltaic devices based on piezoelectric semiconductor materials by utilizing the piezo-polarization charges at the junction induced by straining, which can modulate the energy band of the piezoelectric material and then accelerate or prevent the separation process of the photon-generated electrons and vacancies. This paper introduces the fundamental physics principles of the piezo-phototronic effect, and reviews recent progress in piezo-phototronic effect enhanced solar cells, including solar cells based on semiconductor nanowire, organic/inorganic materials, quantum dots, and perovskite. The piezo-phototronic effect is suggested as a suitable basis for the development of an innovative method to enhance the performance of solar cells based on piezoelectric semiconductors by applied extrinsic strains, which might be appropriate for fundamental research and potential applications in various areas of optoelectronics.

  12. Size-tunable Lateral Confinement in Monolayer Semiconductors

    DOE PAGES

    Wei, Guohua; Czaplewski, David A.; Lenferink, Erik J.; ...

    2017-06-12

    Three-dimensional confinement allows semiconductor quantum dots to exhibit size-tunable electronic and optical properties that enable a wide range of opto-electronic applications from displays, solar cells and bio-medical imaging to single-electron devices. Additional modalities such as spin and valley properties in monolayer transition metal dichalcogenides provide further degrees of freedom requisite for information processing and spintronics. In nanostructures, however, spatial confinement can cause hybridization that inhibits the robustness of these emergent properties. Here in this paper, we show that laterally-confined excitons in monolayer MoS 2 nanodots can be created through top-down nanopatterning with controlled size tunability. Unlike chemically-exfoliated monolayer nanoparticles, themore » lithographically patterned monolayer semiconductor nanodots down to a radius of 15 nm exhibit the same valley polarization as in a continuous monolayer sheet. The inherited bulk spin and valley properties, the size dependence of excitonic energies, and the ability to fabricate MoS 2 nanostructures using semiconductor-compatible processing suggest that monolayer semiconductor nanodots have potential to be multimodal building blocks of integrated optoelectronics and spintronics systems« less

  13. Sealed symmetric multilayered microelectronic device package with integral windows

    DOEpatents

    Peterson, Kenneth A.; Watson, Robert D.

    2002-01-01

    A sealed symmetric multilayered package with integral windows for housing one or more microelectronic devices. The devices can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the windows being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic devices can be flip-chip bonded and oriented so that the light-sensitive sides are optically accessible through the windows. The result is a compact, low-profile, sealed symmetric package, having integral windows that can be hermetically-sealed.

  14. Molecular Electrical Doping of Organic Semiconductors: Fundamental Mechanisms and Emerging Dopant Design Rules.

    PubMed

    Salzmann, Ingo; Heimel, Georg; Oehzelt, Martin; Winkler, Stefanie; Koch, Norbert

    2016-03-15

    Today's information society depends on our ability to controllably dope inorganic semiconductors, such as silicon, thereby tuning their electrical properties to application-specific demands. For optoelectronic devices, organic semiconductors, that is, conjugated polymers and molecules, have emerged as superior alternative owing to the ease of tuning their optical gap through chemical variability and their potential for low-cost, large-area processing on flexible substrates. There, the potential of molecular electrical doping for improving the performance of, for example, organic light-emitting devices or organic solar cells has only recently been established. The doping efficiency, however, remains conspicuously low, highlighting the fact that the underlying mechanisms of molecular doping in organic semiconductors are only little understood compared with their inorganic counterparts. Here, we review the broad range of phenomena observed upon molecularly doping organic semiconductors and identify two distinctly different scenarios: the pairwise formation of both organic semiconductor and dopant ions on one hand and the emergence of ground state charge transfer complexes between organic semiconductor and dopant through supramolecular hybridization of their respective frontier molecular orbitals on the other hand. Evidence for the occurrence of these two scenarios is subsequently discussed on the basis of the characteristic and strikingly different signatures of the individual species involved in the respective doping processes in a variety of spectroscopic techniques. The critical importance of a statistical view of doping, rather than a bimolecular picture, is then highlighted by employing numerical simulations, which reveal one of the main differences between inorganic and organic semiconductors to be their respective density of electronic states and the doping induced changes thereof. Engineering the density of states of doped organic semiconductors, the Fermi-Dirac occupation of which ultimately determines the doping efficiency, thus emerges as key challenge. As a first step, the formation of charge transfer complexes is identified as being detrimental to the doping efficiency, which suggests sterically shielding the functional core of dopant molecules as an additional design rule to complement the requirement of low ionization energies or high electron affinities in efficient n-type or p-type dopants, respectively. In an extended outlook, we finally argue that, to fully meet this challenge, an improved understanding is required of just how the admixture of dopant molecules to organic semiconductors does affect the density of states: compared with their inorganic counterparts, traps for charge carriers are omnipresent in organic semiconductors due to structural and chemical imperfections, and Coulomb attraction between ionized dopants and free charge carriers is typically stronger in organic semiconductors owing to their lower dielectric constant. Nevertheless, encouraging progress is being made toward developing a unifying picture that captures the entire range of doping induced phenomena, from ion-pair to complex formation, in both conjugated polymers and molecules. Once completed, such a picture will provide viable guidelines for synthetic and supramolecular chemistry that will enable further technological advances in organic and hybrid organic/inorganic devices.

  15. Hot carrier-enhanced interlayer electron-hole pair multiplication in 2D semiconductor heterostructure photocells

    NASA Astrophysics Data System (ADS)

    Barati, Fatemeh; Grossnickle, Max; Su, Shanshan; Lake, Roger K.; Aji, Vivek; Gabor, Nathaniel M.

    2017-12-01

    Strong electronic interactions can result in novel particle-antiparticle (electron-hole, e-h) pair generation effects, which may be exploited to enhance the photoresponse of nanoscale optoelectronic devices. Highly efficient e-h pair multiplication has been demonstrated in several important nanoscale systems, including nanocrystal quantum dots, carbon nanotubes and graphene. The small Fermi velocity and nonlocal nature of the effective dielectric screening in ultrathin layers of transition-metal dichalcogenides (TMDs) indicates that e-h interactions are very strong, so high-efficiency generation of e-h pairs from hot electrons is expected. However, such e-h pair multiplication has not been observed in 2D TMD devices. Here, we report the highly efficient multiplication of interlayer e-h pairs in 2D semiconductor heterostructure photocells. Electronic transport measurements of the interlayer I-VSD characteristics indicate that layer-indirect e-h pairs are generated by hot-electron impact excitation at temperatures near T = 300 K. By exploiting this highly efficient interlayer e-h pair multiplication process, we demonstrate near-infrared optoelectronic devices that exhibit 350% enhancement of the optoelectronic responsivity at microwatt power levels. Our findings, which demonstrate efficient carrier multiplication in TMD-based optoelectronic devices, make 2D semiconductor heterostructures viable for a new class of ultra-efficient photodetectors based on layer-indirect e-h excitations.

  16. Nanocrystalline ZnON; High mobility and low band gap semiconductor material for high performance switch transistor and image sensor application

    PubMed Central

    Lee, Eunha; Benayad, Anass; Shin, Taeho; Lee, HyungIk; Ko, Dong-Su; Kim, Tae Sang; Son, Kyoung Seok; Ryu, Myungkwan; Jeon, Sanghun; Park, Gyeong-Su

    2014-01-01

    Interest in oxide semiconductors stems from benefits, primarily their ease of process, relatively high mobility (0.3–10 cm2/vs), and wide-bandgap. However, for practical future electronic devices, the channel mobility should be further increased over 50 cm2/vs and wide-bandgap is not suitable for photo/image sensor applications. The incorporation of nitrogen into ZnO semiconductor can be tailored to increase channel mobility, enhance the optical absorption for whole visible light and form uniform micro-structure, satisfying the desirable attributes essential for high performance transistor and visible light photo-sensors on large area platform. Here, we present electronic, optical and microstructural properties of ZnON, a composite of Zn3N2 and ZnO. Well-optimized ZnON material presents high mobility exceeding 100 cm2V−1s−1, the band-gap of 1.3 eV and nanocrystalline structure with multiphase. We found that mobility, microstructure, electronic structure, band-gap and trap properties of ZnON are varied with nitrogen concentration in ZnO. Accordingly, the performance of ZnON-based device can be adjustable to meet the requisite of both switch device and image-sensor potentials. These results demonstrate how device and material attributes of ZnON can be optimized for new device strategies in display technology and we expect the ZnON will be applicable to a wide range of imaging/display devices. PMID:24824778

  17. Metal organic chemical vapor deposition of 111-v compounds on silicon

    DOEpatents

    Vernon, Stanley M.

    1986-01-01

    Expitaxial composite comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) on single crystal silicon substrates are disclosed. Also disclosed is a process for manufacturing, by chemical deposition from the vapor phase, epitaxial composites as above described, and to semiconductor devices based on such epitaxial composites. The composites have particular utility for use in making light sensitive solid state solar cells.

  18. Voltage-controlled quantum light from an atomically thin semiconductor

    NASA Astrophysics Data System (ADS)

    Chakraborty, Chitraleema; Kinnischtzke, Laura; Goodfellow, Kenneth M.; Beams, Ryan; Vamivakas, A. Nick

    2015-06-01

    Although semiconductor defects can often be detrimental to device performance, they are also responsible for the breadth of functionality exhibited by modern optoelectronic devices. Artificially engineered defects (so-called quantum dots) or naturally occurring defects in solids are currently being investigated for applications ranging from quantum information science and optoelectronics to high-resolution metrology. In parallel, the quantum confinement exhibited by atomically thin materials (semi-metals, semiconductors and insulators) has ushered in an era of flatland optoelectronics whose full potential is still being articulated. In this Letter we demonstrate the possibility of leveraging the atomically thin semiconductor tungsten diselenide (WSe2) as a host for quantum dot-like defects. We report that this previously unexplored solid-state quantum emitter in WSe2 generates single photons with emission properties that can be controlled via the application of external d.c. electric and magnetic fields. These new optically active quantum dots exhibit excited-state lifetimes on the order of 1 ns and remarkably large excitonic g-factors of 10. It is anticipated that WSe2 quantum dots will provide a novel platform for integrated solid-state quantum photonics and quantum information processing, as well as a rich condensed-matter physics playground with which to explore the coupling of quantum dots and atomically thin semiconductors.

  19. Micromechanical Structures Fabrication

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Rajic, S

    2001-05-08

    Work in materials other than silicon for MEMS applications has typically been restricted to metals and metal oxides instead of more ''exotic'' semiconductors. However, group III-V and II-VI semiconductors form a very important and versatile collection of material and electronic parameters available to the MEMS and MOEMS designer. With these materials, not only are the traditional mechanical material variables (thermal conductivity, thermal expansion, Young's modulus, etc.) available, but also chemical constituents can be varied in ternary and quaternary materials. This flexibility can be extremely important for both friction and chemical compatibility issues for MEMS. In addition, the ability to continuallymore » vary the bandgap energy can be particularly useful for many electronics and infrared detection applications. However, there are two major obstacles associated with alternate semiconductor material MEMS. The first issue is the actual fabrication of non-silicon micro-devices and the second impediment is communicating with these novel devices. We have implemented an essentially material independent fabrication method that is amenable to most group III-V and II-VI semiconductors. This technique uses a combination of non-traditional direct write precision fabrication processes such as diamond turning, ion milling, laser ablation, etc. This type of deterministic fabrication approach lends itself to an almost trivial assembly process. We also implemented a mechanical, electrical, and optical self-aligning hybridization technique for these alternate-material MEMS substrates.« less

  20. Novel Fabrication and Simple Hybridization of Exotic Material MEMS

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Datskos, P.G.; Rajic, S.

    1999-11-13

    Work in materials other than silicon for MEMS applications has typically been restricted to metals and metal oxides instead of more ''exotic'' semiconductors. However, group III-V and II-VI semiconductors form a very important and versatile collection of material and electronic parameters available to the MEMS and MOEMS designer. With these materials, not only are the traditional mechanical material variables (thermal conductivity, thermal expansion, Young's modulus, etc.) available, but also chemical constituents can be varied in ternary and quaternary materials. This flexibility can be extremely important for both friction and chemical compatibility issues for MEMS. In addition, the ability to continuallymore » vary the bandgap energy can be particularly useful for many electronics and infrared detection applications. However, there are two major obstacles associated with alternate semiconductor material MEMS. The first issue is the actual fabrication of non-silicon devices and the second impediment is communicating with these novel devices. We will describe an essentially material independent fabrication method that is amenable to most group III-V and II-VI semiconductors. This technique uses a combination of non-traditional direct write precision fabrication processes such as diamond turning, ion milling, laser ablation, etc. This type of deterministic fabrication approach lends itself to an almost trivial assembly process. We will also describe in detail the mechanical, electrical, and optical self-aligning hybridization technique used for these alternate-material MEMS.« less

  1. CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Switching Characteristics of Phase Change Memory Cell Integrated with Metal-Oxide Semiconductor Field Effect Transistor

    NASA Astrophysics Data System (ADS)

    Xu, Cheng; Liu, Bo; Chen, Yi-Feng; Liang, Shuang; Song, Zhi-Tang; Feng, Song-Lin; Wan, Xu-Dong; Yang, Zuo-Ya; Xie, Joseph; Chen, Bomy

    2008-05-01

    A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor (MOSFET) is fabricated using standard 0. 18 μm complementary metal-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50 ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.

  2. Memory effects in a Al/Ti:HfO2/CuPc metal-oxide-semiconductor device

    NASA Astrophysics Data System (ADS)

    Tripathi, Udbhav; Kaur, Ramneek

    2016-05-01

    Metal oxide semiconductor structured organic memory device has been successfully fabricated. Ti doped hafnium oxide (Ti:HfO2) nanoparticles has been fabricated by precipitation method and further calcinated at 800 °C. Copper phthalocyanine, a hole transporting material has been utilized as an organic semiconductor. The electrical properties of the fabricated device have been studied by measuring the current-voltage and capacitance-voltage characteristics. The amount of charge stored in the nanoparticles has been calculated by using flat band condition. This simple approach for fabricating MOS memory device has opens up opportunities for the development of next generation memory devices.

  3. Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications - SiC, GaN, Ga2O3, and Diamond.

    PubMed

    Wellmann, Peter J

    2017-11-17

    Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies.

  4. Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications – SiC, GaN, Ga2O3, and Diamond

    PubMed Central

    2017-01-01

    Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies. PMID:29200530

  5. A Self-Aligned InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated through a Lift-Off-Free Front-End Process

    NASA Astrophysics Data System (ADS)

    Lin, Jianqiang; Kim, Tae-Woo; Antoniadis, Dimitri A.; del Alamo, Jesús A.

    2012-06-01

    We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm2 V-1 s-1.

  6. Stretchable and foldable electronic devices

    DOEpatents

    Rogers, John A; Huang, Yonggang; Ko, Heung Cho; Stoykovich, Mark; Choi, Won Mook; Song, Jizhou; Ahn, Jong Hyun; Kim, Dae Hyeong

    2013-10-08

    Disclosed herein are stretchable, foldable and optionally printable, processes for making devices and devices such as semiconductors, electronic circuits and components thereof that are capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Strain isolation layers provide good strain isolation to functional device layers. Multilayer devices are constructed to position a neutral mechanical surface coincident or proximate to a functional layer having a material that is susceptible to strain-induced failure. Neutral mechanical surfaces are positioned by one or more layers having a property that is spatially inhomogeneous, such as by patterning any of the layers of the multilayer device.

  7. Stretchable and foldable electronic devices

    DOEpatents

    Rogers, John A; Huang, Yonggang; Ko, Heung Cho; Stoykovich, Mark; Choi, Won Mook; Song, Jizhou; Ahn, Jong Hyun; Kim, Dae Hyeong

    2014-12-09

    Disclosed herein are stretchable, foldable and optionally printable, processes for making devices and devices such as semiconductors, electronic circuits and components thereof that are capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Strain isolation layers provide good strain isolation to functional device layers. Multilayer devices are constructed to position a neutral mechanical surface coincident or proximate to a functional layer having a material that is susceptible to strain-induced failure. Neutral mechanical surfaces are positioned by one or more layers having a property that is spatially inhomogeneous, such as by patterning any of the layers of the multilayer device.

  8. Hot Charge Carrier Transmission from Plasmonic Nanostructures

    NASA Astrophysics Data System (ADS)

    Christopher, Phillip; Moskovits, Martin

    2017-05-01

    Surface plasmons have recently been harnessed to carry out processes such as photovoltaic current generation, redox photochemistry, photocatalysis, and photodetection, all of which are enabled by separating energetic (hot) electrons and holes—processes that, previously, were the domain of semiconductor junctions. Currently, the power conversion efficiencies of systems using plasmon excitation are low. However, the very large electron/hole per photon quantum efficiencies observed for plasmonic devices fan the hope of future improvements through a deeper understanding of the processes involved and through better device engineering, especially of critical interfaces such as those between metallic and semiconducting nanophases (or adsorbed molecules). In this review, we focus on the physics and dynamics governing plasmon-derived hot charge carrier transfer across, and the electronic structure at, metal-semiconductor (molecule) interfaces, where we feel the barriers contributing to low efficiencies reside. We suggest some areas of opportunity that deserve early attention in the still-evolving field of hot carrier transmission from plasmonic nanostructures to neighboring phases.

  9. Over-voltage protection system and method

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Chi, Song; Dong, Dong; Lai, Rixin

    An over-voltage protection system includes an electronic valve connected across two terminals of a circuit and an over-voltage detection circuit connected across one of the plurality of semiconductor devices for detecting an over-voltage across the circuit. The electronic valve includes a plurality of semiconductor devices connected in series. The over-voltage detection circuit includes a voltage divider circuit connected to a break-over diode in a way to provide a representative low voltage to the break-over diode and an optocoupler configured to receive a current from the break-over diode when the representative low voltage exceeds a threshold voltage of the break-over diodemore » indicating an over-voltage condition. The representative low voltage provided to the break-over diode represents a voltage across the one semiconductor device. A plurality of self-powered gate drive circuits are connected to the plurality of semiconductor devices, wherein the plurality of self-powered gate drive circuits receive over-voltage triggering pulses from the optocoupler during the over-voltage condition and switch on the plurality of semiconductor devices to bypass the circuit.« less

  10. The preparation method of terahertz monolithic integrated device

    NASA Astrophysics Data System (ADS)

    Zhang, Cong; Su, Bo; He, Jingsuo; Zhang, Hongfei; Wu, Yaxiong; Zhang, Shengbo; Zhang, Cunlin

    2018-01-01

    The terahertz monolithic integrated device is to integrate the pumping area of the terahertz generation, the detection area of the terahertz receiving and the metal waveguide of terahertz transmission on the same substrate. The terahertz generation and detection device use a photoconductive antenna structure the metal waveguide use a microstrip line structure. The evanescent terahertz-bandwidth electric field extending above the terahertz transmission line interacts with, and is modified by, overlaid dielectric samples, thus enabling the characteristic vibrational absorption resonances in the sample to be probed. In this device structure, since the semiconductor substrate of the photoconductive antenna is located between the strip conductor and the dielectric layer of the microstrip line, and the semiconductor substrate cannot grow on the dielectric layer directly. So how to prepare the semiconductor substrate of the photoconductive antenna and how to bond the semiconductor substrate to the dielectric layer of the microstrip line is a key step in the terahertz monolithic integrated device. In order to solve this critical problem, the epitaxial wafer structure of the two semiconductor substrates is given and transferred to the desired substrate by two methods, respectively.

  11. Interconnect assembly for an electronic assembly and assembly method therefor

    DOEpatents

    Gerbsch, Erich William

    2003-06-10

    An interconnect assembly and method for a semiconductor device, in which the interconnect assembly can be used in lieu of wirebond connections to form an electronic assembly. The interconnect assembly includes first and second interconnect members. The first interconnect member has a first surface with a first contact and a second surface with a second contact electrically connected to the first contact, while the second interconnect member has a flexible finger contacting the second contact of the first interconnect member. The first interconnect member is adapted to be aligned and registered with a semiconductor device having a contact on a first surface thereof, so that the first contact of the first interconnect member electrically contacts the contact of the semiconductor device. Consequently, the assembly method does not require any wirebonds, but instead merely entails aligning and registering the first interconnect member with the semiconductor device so that the contacts of the first interconnect member and the semiconductor device make electrically contact, and then contacting the second contact of the first interconnect member with the flexible finger of the second interconnect member.

  12. Metal-organic semiconductor interfacial barrier height determination from internal photoemission signal in spectral response measurements

    NASA Astrophysics Data System (ADS)

    Kumar, Sandeep; Iyer, S. Sundar Kumar

    2017-04-01

    Accurate and convenient evaluation methods of the interfacial barrier ϕb for charge carriers in metal semiconductor (MS) junctions are important for designing and building better opto-electronic devices. This becomes more critical for organic semiconductor devices where a plethora of molecules are in use and standardised models applicable to myriads of material combinations for the different devices may have limited applicability. In this paper, internal photoemission (IPE) from spectral response (SR) in the ultra-violet to near infra-red range of different MS junctions of metal-organic semiconductor-metal (MSM) test structures is used to determine more realistic MS ϕb values. The representative organic semiconductor considered is [6, 6]-phenyl C61 butyric acid methyl ester, and the metals considered are Al and Au. The IPE signals in the SR measurement of the MSM device are identified and separated before it is analysed to estimate ϕb for the MS junction. The analysis of IPE signals under different bias conditions allows the evaluation of ϕb for both the front and back junctions, as well as for symmetric MSM devices.

  13. Computer-aided engineering of semiconductor integrated circuits

    NASA Astrophysics Data System (ADS)

    Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

    1980-07-01

    Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

  14. Comprehensive capacitance-voltage analysis including quantum effects for high-k interfaces on germanium and other alternative channel materials

    NASA Astrophysics Data System (ADS)

    Anwar, Sarkar R. M.

    High mobility alternative channel materials to silicon are critical to the continued scaling of metal oxide semiconductor (MOS) devices. However, before they can be incorporated into advanced devices, some major issues need to be solved. The high mobility materials suffer from lower allowable thermal budgets compared to Si (before desorption and defect formation becomes an issue) and the absence of a good quality native oxide has further increased the interest in the use of high-k dielectrics. However, the high interface state density and high electric fields at these semiconductor/high-k interfaces can significantly impact the capacitance-voltage (C-V) profile, and current C-V modeling software cannot account for these effects. This in turn affects the parameters extracted from the C-V data of the high mobility semiconductor/high-k interface, which are crucial to fully understand the interface properties and expedite process development. To address this issue, we developed a model which takes into account quantum corrections which can be applied to a number of these alternative channel materials including SixGe1-x, Ge, InGaAs, and GaAs. The C-V simulation using this QM correction model is orders of magnitude faster compared to a full band Schrodinger-Poisson solver. The simulated C-V is directly benchmarked to a self consistent Schrodinger-Poisson solution for each bulk semiconductor material, and from the benchmarking process the QM correction parameters are extracted. The full program, C-V Alternative Channel Extraction (CV ACE), incorporates a quantum mechanical correction model, along with the interface state density model, and can extract device parameters such as equivalent oxide thickness (EOT), doping density and flat band voltage (Vfb) as well as the interface state density profile using multiple measurements performed at different frequencies and temperatures, simultaneously. The program was used to analyze experimentally measured C-V profiles and the extracted device parameters show excellent agreement with the known device structure and previously published results. CV ACE has been applied in the development of a process flow for germanium interface passivation in Ge based MOS devices using a GeOx interlayer. A post atomic layer deposition (ALD) plasma oxidation (PPO) process was developed using radio frequency (RF) plasma in a plasma enhanced chemical vapor deposition (PECVD) chamber and demonstrated significant surface passivation. Various gases were investigated and 1% O2/Ar was found to reduce the growth rate and provide excellent control over the degradation of EOT. A 100 W plasma with 1% O2/Ar was found to provide the best combination of EOT and low Dit and is concluded to be the optimum process for PPO of germanium surfaces. CV ACE and PPO were also utilized to investigate other process development challenges. A study of the impact of low temperature anneals on Ge-based MOS devices was found to result in a degradation of the electrical thickness and a change in fixed charge, indicating that the process window is very narrow and at much lower temperatures than for Si.

  15. Method for fabricating an interconnected array of semiconductor devices

    DOEpatents

    Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

    1989-10-10

    Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

  16. Electrical Properties of Reactive Liquid Crystal Semiconductors

    NASA Astrophysics Data System (ADS)

    McCulloch, Iain; Coelle, Michael; Genevicius, Kristijonas; Hamilton, Rick; Heckmeier, Michael; Heeney, Martin; Kreouzis, Theo; Shkunov, Maxim; Zhang, Weimin

    2008-01-01

    Fabrication of display products by low cost printing technologies such as ink jet, gravure offset lithography and flexography requires solution processable semiconductors for the backplane electronics. The products will typically be of lower performance than polysilicon transistors, but comparable to amorphous silicon. A range of prototypes are under development, including rollable electrophoretic displays, active matrix liquid crystal displays (AMLCD's), and flexible organic light-emitting diode (OLED) displays. Organic semiconductors that offer both electrical performance and stability with respect to storage and operation under ambient conditions are required. This work describes the initial evaluation of reactive mesogen semiconductors, which can polymerise within mesophase temperatures, “freezing in” the order in crosslinked domains. These crosslinked domains offer mechanical stability and are inert to solvent exposure in further processing steps. Reactive mesogens containing conjugated aromatic cores, designed to facilitate charge transport and provide good oxidative stability, were prepared and their liquid crystalline properties evaluated. Both time-of-flight and field effect transistor devices were prepared and their electrical characterisation reported.

  17. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Wei, Guohua; Czaplewski, David A.; Lenferink, Erik J.

    Three-dimensional confinement allows semiconductor quantum dots to exhibit size-tunable electronic and optical properties that enable a wide range of opto-electronic applications from displays, solar cells and bio-medical imaging to single-electron devices. Additional modalities such as spin and valley properties in monolayer transition metal dichalcogenides provide further degrees of freedom requisite for information processing and spintronics. In nanostructures, however, spatial confinement can cause hybridization that inhibits the robustness of these emergent properties. Here in this paper, we show that laterally-confined excitons in monolayer MoS 2 nanodots can be created through top-down nanopatterning with controlled size tunability. Unlike chemically-exfoliated monolayer nanoparticles, themore » lithographically patterned monolayer semiconductor nanodots down to a radius of 15 nm exhibit the same valley polarization as in a continuous monolayer sheet. The inherited bulk spin and valley properties, the size dependence of excitonic energies, and the ability to fabricate MoS 2 nanostructures using semiconductor-compatible processing suggest that monolayer semiconductor nanodots have potential to be multimodal building blocks of integrated optoelectronics and spintronics systems« less

  18. All-inkjet-printed flexible ZnO micro photodetector for a wearable UV monitoring device.

    PubMed

    Tran, Van-Thai; Wei, Yuefan; Yang, Hongyi; Zhan, Zhaoyao; Du, Hejun

    2017-03-03

    Fabrication of small-sized patterns of inorganic semiconductor onto flexible substrates is a major concern when manufacturing wearable devices for measuring either biometric or environmental parameters. In this study, micro-sized flexible ZnO UV photodetectors have been thoroughly prepared by a facile inkjet printing technology and followed with heat treatments. A simple ink recipe of zinc acetate precursor solution was investigated. It is found that the substrate temperature during zinc precursor ink depositing has significant effects on ZnO pattern shape, film morphology, and crystallization. The device fabricated from the additive manufacturing approach has good bendability, Ohmic contact, short response time as low as 0.3 s, and high on/off ratio of 3525. We observed the sensor's dependence of response/decay time by the illuminating UV light intensity. The whole process is based on additive manufacturing which has many benefits such as rapid prototyping, saving material, being environmentally friendly, and being capable of creating high-resolution patterns. In addition, this method can be applied to flexible substrates, which makes the device more applicable for applications requiring flexibility such as wearable devices. The proposed all-inkjet-printing approach for a micro-sized ZnO UV photodetector would significantly simplify the fabrication process of micro-sized inorganic semiconductor-based devices. A potential application is real-time monitoring of UV light exposure to warn users about unsafe direct sunlight to implement suitable avoidance solutions.

  19. New developments in power semiconductors

    NASA Technical Reports Server (NTRS)

    Sundberg, G. R.

    1983-01-01

    This paper represents an overview of some recent power semiconductor developments and spotlights new technologies that may have significant impact for aircraft electric secondary power. Primary emphasis will be on NASA-Lewis-supported developments in transistors, diodes, a new family of semiconductors, and solid-state remote power controllers. Several semiconductor companies that are moving into the power arena with devices rated at 400 V and 50 A and above are listed, with a brief look at a few devices.

  20. Annealing of Solar Cells and Other Thin Film Devices

    NASA Technical Reports Server (NTRS)

    Escobar, Hector; Kuhlman, Franz; Dils, D. W.; Lush, G. B.; Mackey, Willie R. (Technical Monitor)

    2001-01-01

    Annealing is a key step in most semiconductor fabrication processes, especially for thin films where annealing enhances performance by healing defects and increasing grain sizes. We have employed a new annealing oven for the annealing of CdTe-based solar cells and have been using this system in an attempt to grow US on top of CdTe by annealing in the presence of H2S gas. Preliminary results of this process on CdTe solar cells and other thin-film devices will be presented.

  1. Gas-phase synthesis of semiconductor nanocrystals and its applications

    NASA Astrophysics Data System (ADS)

    Mandal, Rajib

    Luminescent nanomaterials is a newly emerging field that provides challenges not only to fundamental research but also to innovative technology in several areas such as electronics, photonics, nanotechnology, display, lighting, biomedical engineering and environmental control. These nanomaterials come in various forms, shapes and comprises of semiconductors, metals, oxides, and inorganic and organic polymers. Most importantly, these luminescent nanomaterials can have different properties owing to their size as compared to their bulk counterparts. Here we describe the use of plasmas in synthesis, modification, and deposition of semiconductor nanomaterials for luminescence applications. Nanocrystalline silicon is widely known as an efficient and tunable optical emitter and is attracting great interest for applications in several areas. To date, however, luminescent silicon nanocrystals (NCs) have been used exclusively in traditional rigid devices. For the field to advance towards new and versatile applications for nanocrystal-based devices, there is a need to investigate whether these NCs can be used in flexible and stretchable devices. We show how the optical and structural/morphological properties of plasma-synthesized silicon nanocrystals (Si NCs) change when they are deposited on stretchable substrates made of polydimethylsiloxane (PDMS). Synthesis of these NCs was performed in a nonthermal, low-pressure gas phase plasma reactor. To our knowledge, this is the first demonstration of direct deposition of NCs onto stretchable substrates. Additionally, in order to prevent oxidation and enhance the luminescence properties, a silicon nitride shell was grown around Si NCs. We have demonstrated surface nitridation of Si NCs in a single step process using non?thermal plasma in several schemes including a novel dual-plasma synthesis/shell growth process. These coated NCs exhibit SiNx shells with composition depending on process parameters. While measurements including photoluminescence (PL), surface analysis, and defect identification indicate the shell is protective against oxidation compared to Si NCs without any shell growth. Gallium Nitride (GaN) is one of the most well-known semiconductor material and the industry standard for fabricating LEDs. The problem is that epitaxial growth of high-quality GaN requires costly substrates (e.g. sapphire), high temperatures, and long processing times. Synthesizing freestanding NCs of GaN, on the other hand, could enable these novel device morphologies, as the NCs could be incorporated into devices without the requirements imposed by epitaxial GaN growth. Synthesis of GaN NCs was performed using a fully gas-phase process. Different sizes of crystalline GaN nanoparticles were produced indicating versatility of this gas-phase process. Elemental analysis using X-ray photoelectron spectroscopy (XPS) indicated a possible nitrogen deficiency in the NCs; addition of secondary plasma for surface treatment indicates improving stoichiometric ratio and points towards a unique method for creating high-quality GaN NCs with ultimate alloying and doping for full-spectrum luminescence.

  2. Cycling excitation process: An ultra efficient and quiet signal amplification mechanism in semiconductor

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Liu, Yu-Hsin; Yan, Lujiang; Zhang, Alex Ce

    2015-08-03

    Signal amplification, performed by transistor amplifiers with its merit rated by the efficiency and noise characteristics, is ubiquitous in all electronic systems. Because of transistor thermal noise, an intrinsic signal amplification mechanism, impact ionization was sought after to complement the limits of transistor amplifiers. However, due to the high operation voltage (30-200 V typically), low power efficiency, limited scalability, and, above all, rapidly increasing excess noise with amplification factor, impact ionization has been out of favor for most electronic systems except for a few applications such as avalanche photodetectors and single-photon Geiger detectors. Here, we report an internal signal amplification mechanismmore » based on the principle of the phonon-assisted cycling excitation process (CEP). Si devices using this concept show ultrahigh gain, low operation voltage, CMOS compatibility, and, above all, quantum limit noise performance that is 30 times lower than devices using impact ionization. Established on a unique physical effect of attractive properties, CEP-based devices can potentially revolutionize the fields of semiconductor electronics.« less

  3. Semiconductor devices incorporating multilayer interference regions

    DOEpatents

    Biefeld, Robert M.; Drummond, Timothy J.; Gourley, Paul L.; Zipperian, Thomas E.

    1990-01-01

    A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration.

  4. Thin film photovoltaic device with multilayer substrate

    DOEpatents

    Catalano, Anthony W.; Bhushan, Manjul

    1984-01-01

    A thin film photovoltaic device which utilizes at least one compound semiconductor layer chosen from Groups IIB and VA of the Periodic Table is formed on a multilayer substrate The substrate includes a lowermost support layer on which all of the other layers of the device are formed. Additionally, an uppermost carbide or silicon layer is adjacent to the semiconductor layer. Below the carbide or silicon layer is a metal layer of high conductivity and expansion coefficient equal to or slightly greater than that of the semiconductor layer.

  5. Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

    NASA Astrophysics Data System (ADS)

    Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Yamada, Hisashi; Takahashi, Tokio; Shimizu, Mitsuaki; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2018-01-01

    A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm-2 eV-1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

  6. Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

    2005-01-01

    An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

  7. Damage free Ar ion plasma surface treatment on In{sub 0.53}Ga{sub 0.47}As-on-silicon metal-oxide-semiconductor device

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Koh, Donghyi; Shin, Seung Heon; Ahn, Jaehyun

    2015-11-02

    In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}),more » which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.« less

  8. Multi-harmonic quantum dot optomechanics in fused LiNbO3-(Al)GaAs hybrids

    NASA Astrophysics Data System (ADS)

    Nysten, Emeline D. S.; Huo, Yong Heng; Yu, Hailong; Song, Guo Feng; Rastelli, Armando; Krenner, Hubert J.

    2017-11-01

    We fabricated an acousto-optic semiconductor hybrid device for strong optomechanical coupling of individual quantum emitters and a surface acoustic wave. Our device comprises of a surface acoustic wave chip made from highly piezoelectric LiNbO3 and a GaAs-based semiconductor membrane with an embedded layer of quantum dots. Employing multi-harmonic transducers, we generated sound waves on LiNbO3 over a wide range of radio frequencies. We monitored their coupling to and propagation across the semiconductor membrane, both in the electrical and optical domain. We demonstrate the enhanced optomechanical tuning of the embedded quantum dots with increasing frequencies. This effect was verified by finite element modelling of our device geometry and attributed to an increased localization of the acoustic field within the semiconductor membrane. For moderately high acoustic frequencies, our simulations predict strong optomechanical coupling, making our hybrid device ideally suited for applications in semiconductor based quantum acoustics.

  9. MM&T Program to Establish Production Techniques for the Automatic Detection and Qualification of Trace Elements Present in the Production of Microwave Semiconductors.

    DTIC Science & Technology

    1981-03-01

    lots. A single store of partially processed devices may serve as a source for several different product lines. Because the manufacture of microwave...matrix, or react chem- ically with some of the semiconductor materials. In some cases these element impurities may migrate to an interface inducing... different viscosity, the background intensity varied independently of the signal, a significant error could be introduced. A more effec- tive method

  10. Fabrication of Superconducting Detectors for Studying the Universe

    NASA Technical Reports Server (NTRS)

    Brown, Ari-David

    2012-01-01

    Superconducting detectors offer unparalleled means of making astronomical/cosmological observations. Fabrication of these detectors is somewhat unconventional; however, a lot of novel condensed matter physics/materials scientific discoveries and semiconductor fabrication processes can be generated in making these devices.

  11. Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

    NASA Astrophysics Data System (ADS)

    Alivov, Yahya; Funke, Hans; Nagpal, Prashant

    2015-07-01

    Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

  12. The measurement of alpha particle emissions from semiconductor memory materials

    NASA Astrophysics Data System (ADS)

    Bouldin, D. P.

    1981-07-01

    With the increasing concern for the affects of alpha particles on the reliability of semiconductor memories, an interest has arisen in characterizing semiconductor manufacturing materials for extremely low-level alpha-emitting contaminants. It is shown that four elements are of primary concern: uranium, thorium, radium, and polonium. Measurement of contamination levels are given relevance by first correlating them with alpha flux emission levels and then corre1ating these flux values with device soft error rates. Measurement techniques involve either measurements of elemental concentrations-applicable to only uranium and thorium - or direct measurements of alpha emission fluxes. Alpha fluxes are most usefully measured by means of ZnS scintillation counting, practical details of which are discussed. Materials measurements are reported for ceramics, solder, silicon, quartz, and various metals and organic materials. Ceramics and most metals have contamination levels of concern, but the high temperature processing normally used in semiconductor manufacturing and low total amounts reduce problems, at least for metals. Silicon, silicon compounds, and organic materials have been found to have no detectable alpha emitters. Finally, a brief discussion of the calibration of alpha sources for accelerated device testing is given, including practical details on the affects of source/chip separation and alignment variations.

  13. The influence of interfacial defects on fast charge trapping in nanocrystalline oxide-semiconductor thin film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

    2016-05-01

    Defects in oxide semiconductors not only influence the initial device performance but also affect device reliability. The front channel is the major carrier transport region during the transistor turn-on stage, therefore an understanding of defects located in the vicinity of the interface is very important. In this study, we investigated the dynamics of charge transport in a nanocrystalline hafnium-indium-zinc-oxide thin-film transistor (TFT) by short pulse I-V, transient current and 1/f noise measurement methods. We found that the fast charging behavior of the tested device stems from defects located in both the front channel and the interface, following a multi-trapping mechanism. We found that a silicon-nitride stacked hafnium-indium-zinc-oxide TFT is vulnerable to interfacial charge trapping compared with silicon-oxide counterpart, causing significant mobility degradation and threshold voltage instability. The 1/f noise measurement data indicate that the carrier transport in a silicon-nitride stacked TFT device is governed by trapping/de-trapping processes via defects in the interface, while the silicon-oxide device follows the mobility fluctuation model.

  14. Conjugated polymers and their use in optoelectronic devices

    DOEpatents

    Marks, Tobin J.; Guo, Xugang; Zhou, Nanjia; Chang, Robert P. H.; Drees, Martin; Facchetti, Antonio

    2016-10-18

    The present invention relates to certain polymeric compounds and their use as organic semiconductors in organic and hybrid optical, optoelectronic, and/or electronic devices such as photovoltaic cells, light emitting diodes, light emitting transistors, and field effect transistors. The present compounds can provide improved device performance, for example, as measured by power conversion efficiency, fill factor, open circuit voltage, field-effect mobility, on/off current ratios, and/or air stability when used in photovoltaic cells or transistors. The present compounds can have good solubility in common solvents enabling device fabrication via solution processes.

  15. Semiconductor devices incorporating multilayer interference regions

    DOEpatents

    Biefeld, R.M.; Drummond, T.J.; Gourley, P.L.; Zipperian, T.E.

    1987-08-31

    A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration. 8 figs.

  16. Lattice matched semiconductor growth on crystalline metallic substrates

    DOEpatents

    Norman, Andrew G; Ptak, Aaron J; McMahon, William E

    2013-11-05

    Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.

  17. Temperature measuring device

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Lauf, R.J.; Bible, D.W.; Sohns, C.W.

    1999-10-19

    Systems and methods are described for a wireless instrumented silicon wafer that can measure temperatures at various points and transmit those temperature readings to an external receiver. The device has particular utility in the processing of semiconductor wafers, where it can be used to map thermal uniformity on hot plates, cold plates, spin bowl chucks, etc. without the inconvenience of wires or the inevitable thermal perturbations attendant with them.

  18. Temperature measuring device

    DOEpatents

    Lauf, Robert J.; Bible, Don W.; Sohns, Carl W.

    1999-01-01

    Systems and methods are described for a wireless instrumented silicon wafer that can measure temperatures at various points and transmit those temperature readings to an external receiver. The device has particular utility in the processing of semiconductor wafers, where it can be used to map thermal uniformity on hot plates, cold plates, spin bowl chucks, etc. without the inconvenience of wires or the inevitable thermal perturbations attendant with them.

  19. Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

    NASA Astrophysics Data System (ADS)

    Sheng, Jiazhen; Han, Ki-Lim; Hong, TaeHyun; Choi, Wan-Ho; Park, Jin-Seong

    2018-01-01

    The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors (TFTs), fabricating with atomic layer deposition (ALD) processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types (directions). The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields. Project supported by the National Research Foundation of Korea (NRF) (No. NRF-2017R1D1A1B03034035), the Ministry of Trade, Industry & Energy (No. #10051403), and the Korea Semiconductor Research Consortium.

  20. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-10-04

    ... Circuit Devices and Products Containing Same; Notice of Commission Determination Not To Review an Initial... public record for this investigation may be viewed on the Commission's electronic docket (EDIS) at http... certain semiconductor integrated circuit devices and products containing same by reason of infringement of...

  1. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-03-29

    ... INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and... Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is soliciting comments on... Commission's electronic docket (EDIS) at http://edis.usitc.gov , and will be available for inspection during...

  2. Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

    NASA Astrophysics Data System (ADS)

    Hussain, Muhammad M.; Rojas, Jhonathan P.; Torres Sevilla, Galo A.

    2013-05-01

    Today's information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor - heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon - industry's darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

  3. Integration of Indium Phosphide Based Devices with Flexible Substrates

    NASA Astrophysics Data System (ADS)

    Chen, Wayne Huai

    2011-12-01

    Flexible substrates have many advantages in applications where bendability, space, or weight play important roles or where rigid circuits are undesirable. However, conventional flexible thin film transistors are typically characterized as having low carrier mobility as compared to devices used in the electronics industry. This is in part due to the limited temperature tolerance of plastic flexible substrates, which commonly reduces the highest processing temperature to below 200°C. Common approaches of implementation include low temperature deposition of organic, amorphous, or polycrystalline semiconductors, all of which result in carrier mobility well below 100 cm2V -1s-1. High quality, single crystalline III-V semiconductors such as indium phosphide (InP), on the other hand, have carrier mobility well over 1000 cm 2V-1s-1 at room temperature, depending on carrier concentration. Recently, the ion-cut process has been used in conjunction with wafer bonding to integrate thin layers of III-V material onto silicon for optoelectronic applications. This approach has the advantage of high scalability, reusability of the initial III-V substrate, and the ability to tailor the location (depth) of the layer splitting. However, the transferred substrate usually suffers from hydrogen implantation damage. This dissertation demonstrates a new approach to enable integration of InP with various substrates, called the double-flip transfer process. The process combines ion-cutting with adhesive bonding. The problem of hydrogen implantation was overcome by patterned ion-cut transfer. In this type of transfer, areas of interest are shielded from implantation but still transferred by surrounding implanted regions. We found that patterned ion-cut transfer is strongly dependent upon crystal orientation and that using cleavage-plane oriented donors can be beneficial in transferring large areas of high quality semiconductor material. InP-based devices were fabricated to demonstrate the transfer process and test functionality following transfer. Passive devices (photodetectors) as well as active transistors were transferred and fabricated on various substrates. The transferred device layers were either implanted through with a blanket implant or protected with an ion-mask during implantation. Results demonstrate the viability of the double-flip ion-cut process in achieving very high electron mobility (˜2800 cm2V-1s-1) transistors on plastic flexible substrates.

  4. The photoirradiation induced p-n junction in naphthylamine-based organic photovoltaic cells

    NASA Astrophysics Data System (ADS)

    Bai, Linyi; Gao, Qiang; Xia, Youyi; Ang, Chung Yen; Bose, Purnandhu; Tan, Si Yu; Zhao, Yanli

    2015-08-01

    The bulk heterojunction (BHJ) plays an indispensable role in organic photovoltaics, and thus has been investigated extensively in recent years. While a p-n heterojunction is usually fabricated using two different donor and acceptor materials such as poly(3-hexylthiophene-2,5-diyl) (P3HT) and phenyl-C61-butyric acid methyl ester (PCBM), it is really rare that such a BHJ is constructed by a single entity. Here, we presented a photoirradiation-induced p-n heterojunction in naphthylamine-based organic photovoltaic cells, where naphthylamine as a typical p-type semiconductor could be oxidized under photoirradiation and transformed into a new semiconductor with the n-type character. The p-n heterojunction was realized using both the remaining naphthylamine and its oxidative product, giving rise to the performance improvement in organic photovoltaic devices. The experimental results show that the power conversion efficiency (PCE) of the devices could be achieved up to 1.79% and 0.43% in solution and thin film processes, respectively. Importantly, this technology using naphthylamine does not require classic P3HT and PCBM to realize the p-n heterojunction, thereby simplifying the device fabrication process. The present approach opens up a promising route for the development of novel materials applicable to the p-n heterojunction.The bulk heterojunction (BHJ) plays an indispensable role in organic photovoltaics, and thus has been investigated extensively in recent years. While a p-n heterojunction is usually fabricated using two different donor and acceptor materials such as poly(3-hexylthiophene-2,5-diyl) (P3HT) and phenyl-C61-butyric acid methyl ester (PCBM), it is really rare that such a BHJ is constructed by a single entity. Here, we presented a photoirradiation-induced p-n heterojunction in naphthylamine-based organic photovoltaic cells, where naphthylamine as a typical p-type semiconductor could be oxidized under photoirradiation and transformed into a new semiconductor with the n-type character. The p-n heterojunction was realized using both the remaining naphthylamine and its oxidative product, giving rise to the performance improvement in organic photovoltaic devices. The experimental results show that the power conversion efficiency (PCE) of the devices could be achieved up to 1.79% and 0.43% in solution and thin film processes, respectively. Importantly, this technology using naphthylamine does not require classic P3HT and PCBM to realize the p-n heterojunction, thereby simplifying the device fabrication process. The present approach opens up a promising route for the development of novel materials applicable to the p-n heterojunction. Electronic supplementary information (ESI) available: Additional synthesis and characterization details. See DOI: 10.1039/c5nr04471e

  5. Insulator Charging in RF MEMS Capacitive Switches

    DTIC Science & Technology

    2005-06-01

    and Simulations,” Journal of Microelectromechanical Systems, 8: 208-217 (June 1999). 5. Neaman , Donald. Semiconductor Physics & Devices. Boston...227-230 (2001). 5. Sze, S.M. Semiconductor Devices: Physics and Technology. New York: Wiley, 1985. 6. Neaman , Donald A. Semiconductor Physics...Radiation Response of Hafnium-Silicate Capacitors,” IEEE Transactions on Nuclear Science, 49: 3191-3196 (December 2002). 3. Neaman , D.A

  6. Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Nam, Chang-Yong; Stein, Aaron

    Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

  7. Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

    DOE PAGES

    Nam, Chang-Yong; Stein, Aaron

    2017-11-15

    Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

  8. High-performance all-printed amorphous oxide FETs and logics with electronically compatible electrode/ channel interface.

    PubMed

    Sharma, Bhupendra Kumar; Stoesser, Anna; Mondal, Sandeep Kumar; Garlapati, Suresh K; Fawey, Mohammed H; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

    2018-06-12

    Oxide semiconductors typically show superior device performance compared to amorphous silicon or organic counterparts, especially, when they are physical vapor deposited. However, it is not easy to reproduce identical device characteristics when the oxide field-effect transistors (FETs) are solution-processed/ printed; the level of complexity further intensifies with the need to print the passive elements as well. Here, we developed a protocol for designing the most electronically compatible electrode/ channel interface based on the judicious material selection. Exploiting this newly developed fabrication schemes, we are now able to demonstrate high-performance all-printed FETs and logic circuits using amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor, indium tin oxide (ITO) as electrodes and composite solid polymer electrolyte as the gate insulator. Interestingly, all-printed FETs demonstrate an optimal electrical performance in terms of threshold voltages and device mobility and may very well be compared with devices fabricated using sputtered ITO electrodes. This observation originates from the selection of electrode/ channel materials from the same transparent semiconductor oxide family, resulting in the formation of In-Sn-Zn-O (ITZO) based diffused a-IGZO/ ITO interface that controls doping density while ensuring high electrical performance. Compressive spectroscopic studies reveal that Sn doping mediated excellent band alignment of IGZO with ITO electrodes is responsible for the excellent device performance observed. All-printed n-MOS based logic circuits have also been demonstrated towards new-generation portable electronics.

  9. Charge dissipative dielectric for cryogenic devices

    NASA Technical Reports Server (NTRS)

    Cantor, Robin Harold (Inventor); Hall, John Addison (Inventor)

    2007-01-01

    A Superconducting Quantum Interference Device (SQUID) is disclosed comprising a pair of resistively shunted Josephson junctions connected in parallel within a superconducting loop and biased by an external direct current (dc) source. The SQUID comprises a semiconductor substrate and at least one superconducting layer. The metal layer(s) are separated by or covered with a semiconductor material layer having the properties of a conductor at room temperature and the properties of an insulator at operating temperatures (generally less than 100 Kelvins). The properties of the semiconductor material layer greatly reduces the risk of electrostatic discharge that can damage the device during normal handling of the device at room temperature, while still providing the insulating properties desired to allow normal functioning of the device at its operating temperature. A method of manufacturing the SQUID device is also disclosed.

  10. Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

    PubMed

    Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

    2011-06-01

    The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

  11. Anisotropy-based crystalline oxide-on-semiconductor material

    DOEpatents

    McKee, Rodney Allen; Walker, Frederick Joseph

    2000-01-01

    A semiconductor structure and device for use in a semiconductor application utilizes a substrate of semiconductor-based material, such as silicon, and a thin film of a crystalline oxide whose unit cells are capable of exhibiting anisotropic behavior overlying the substrate surface. Within the structure, the unit cells of the crystalline oxide are exposed to an in-plane stain which influences the geometric shape of the unit cells and thereby arranges a directional-dependent quality of the unit cells in a predisposed orientation relative to the substrate. This predisposition of the directional-dependent quality of the unit cells enables the device to take beneficial advantage of characteristics of the structure during operation. For example, in the instance in which the crystalline oxide of the structure is a perovskite, a spinel or an oxide of similarly-related cubic structure, the structure can, within an appropriate semiconductor device, exhibit ferroelectric, piezoelectric, pyroelectric, electro-optic, ferromagnetic, antiferromagnetic, magneto-optic or large dielectric properties that synergistically couple to the underlying semiconductor substrate.

  12. EDITORIAL The 23rd Nordic Semiconductor Meeting The 23rd Nordic Semiconductor Meeting

    NASA Astrophysics Data System (ADS)

    Ólafsson, Sveinn; Sveinbjörnsson, Einar

    2010-12-01

    A Nordic Semiconductor Meeting is held every other year with the venue rotating amongst the Nordic countries of Denmark, Finland, Iceland, Norway and Sweden. The focus of these meetings remains 'original research and science being carried out on semiconductor materials, devices and systems'. Reports on industrial activity have usually featured. The topics have ranged from fundamental research on point defects in a semiconductor to system architecture of semiconductor electronic devices. Proceedings from these events are regularly published as a topical issue of Physica Scripta. All of the papers in this topical issue have undergone critical peer review and we wish to thank the reviewers and the authors for their cooperation, which has been instrumental in meeting the high scientific standards and quality of the series. This meeting of the 23rd Nordic Semiconductor community, NSM 2009, was held at Háskólatorg at the campus of the University of Iceland, Reykjavik, Iceland, 14-17 June 2009. Support was provided by the University of Iceland. Almost 50 participants presented a broad range of topics covering semiconductor materials and devices as well as related material science interests. The conference provided a forum for Nordic and international scientists to present and discuss new results and ideas concerning the fundamentals and applications of semiconductor materials. The meeting aim was to advance the progress of Nordic science and thus aid in future worldwide technological advances concerning technology, education, energy and the environment. Topics Theory and fundamental physics of semiconductors Emerging semiconductor technologies (for example III-V integration on Si, novel Si devices, graphene) Energy and semiconductors Optical phenomena and optical devices MEMS and sensors Program 14 June Registration 13:00-17:00 15 June Meeting program 09:30-17:00 and Poster Session I 16 June Meeting program 09:30-17:00 and Poster Session II 17 June Excursion and dinner on Icelandic National Day In connection with the conference, a summer school for 40 research students was organized by the Nordic LENS network. The summer school took place in Reykjavik on 11-14 June. For more information on the school please visit the website. The next Nordic Semiconductor meeting, NSM 2011, is scheduled to take place in Aarhus, Denmark, 19-22 June 2011. A full participant list is available in the PDF of this article.

  13. Self bleaching photoelectrochemical-electrochromic device

    DOEpatents

    Bechinger, Clemens S.; Gregg, Brian A.

    2002-04-09

    A photoelectrochemical-electrochromic device comprising a first transparent electrode and a second transparent electrode in parallel, spaced relation to each other. The first transparent electrode is electrically connected to the second transparent electrode. An electrochromic material is applied to the first transparent electrode and a nanoporous semiconductor film having a dye adsorbed therein is applied to the second transparent electrode. An electrolyte layer contacts the electrochromic material and the nanoporous semiconductor film. The electrolyte layer has a redox couple whereby upon application of light, the nanoporous semiconductor layer dye absorbs the light and the redox couple oxidizes producing an electric field across the device modulating the effective light transmittance through the device.

  14. Electron transport through magnetic quantum point contacts

    NASA Astrophysics Data System (ADS)

    Day, Timothy Ellis

    Spin-based electronics, or spintronics, has generated a great deal of interest as a possible next-generation integrated circuit technology. Recent experimental and theoretical work has shown that these devices could exhibit increased processing speed, decreased power consumption, and increased integration densities as compared with conventional semiconductor devices. The spintronic device that was designed, fabricated, and tested throughout the course of this work aimed to study the generation of spin-polarized currents in semiconductors using magnetic fringe fields. The device scheme relied on the Zeeman effect in combination with a quantum mechanical barrier to generate spin-polarized currents. The Zeeman effect was used to break the degeneracy of spin-up and spin-down electrons and the quantum mechanical potential to transmit one while rejecting the other. The design was dictated by the drive to maximize the strength of the magnetic fringe field and in turn maximize the energy separation of the two spin species. The device was fabricated using advanced techniques in semiconductor processing including electron beam lithography and DC magnetron sputtering. Measurements were performed in a 3He cryostat equipped with a superconducting magnet at temperatures below 300 mK. Preliminary characterization of the device revealed magnetoconductance oscillations produced by the effect of the transverse confining potential on the density of states and the mobility. Evidence of the effect of the magnetic fringe fields on the transport properties of electrons in the device were observed in multiple device measurements. An abrupt washout of the quantized conductance steps was observed over a minute range of the applied magnetic field. The washout was again observed as electrons were shifted closer to the magnetic gates. In addition, bias spectroscopy demonstrated that the washout occurred despite stronger electron confinement, as compared to a non-magnetic split-gate. Thus, the measurements indicated that conductance quantization breaks down in a non-uniform magnetic field, possibly due to changes to the stationary Landau states. It was also demonstrated that non-integer conductance plateaus at high source-drain bias are not caused by a macroscopic asymmetry in the potential drop.

  15. Semiconductor/dielectric interface engineering and characterization

    NASA Astrophysics Data System (ADS)

    Lucero, Antonio T.

    The focus of this dissertation is the application and characterization of several, novel interface passivation techniques for III-V semiconductors, and the development of an in-situ electrical characterization. Two different interface passivation techniques were evaluated. The first is interface nitridation using a nitrogen radical plasma source. The nitrogen radical plasma generator is a unique system which is capable of producing a large flux of N-radicals free of energetic ions. This was applied to Si and the surface was studied using x-ray photoelectron spectroscopy (XPS). Ultra-thin nitride layers could be formed from 200-400° C. Metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated using this passivation technique. Interface nitridation was able to reduce leakage current and improve the equivalent oxide thickness of the devices. The second passivation technique studied is the atomic layer deposition (ALD) diethylzinc (DEZ)/water treatment of sulfur treated InGaAs and GaSb. On InGaAs this passivation technique is able to chemically reduce higher oxidation states on the surface, and the process results in the deposition of a ZnS/ZnO interface passivation layer, as determined by XPS. Capacitance-voltage (C-V) measurements of MOSCAPs made on p-InGaAs reveal a large reduction in accumulation dispersion and a reduction in the density of interfacial traps. The same technique was applied to GaSb and the process was studied in an in-situ half-cycle XPS experiment. DEZ/H2O is able to remove all Sb-S from the surface, forming a stable ZnS passivation layer. This passivation layer is resistant to further reoxidation during dielectric deposition. The final part of this dissertation is the design and construction of an ultra-high vacuum cluster tool for in-situ electrical characterization. The system consists of three deposition chambers coupled to an electrical probe station. With this setup, devices can be processed and subsequently electrically characterized without exposing the sample to air. This is the first time that such a system has been reported. A special air-gap C-V probe will allow top gated measurements to be made, allowing semiconductor-dielectric interfaces to be studied during device processing.

  16. Single InAs/GaSb nanowire low-power CMOS inverter.

    PubMed

    Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

    2012-11-14

    III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

  17. Defect-Rich Dopant-Free ZrO2 Nanostructures with Superior Dilute Ferromagnetic Semiconductor Properties.

    PubMed

    Rahman, Md Anisur; Rout, S; Thomas, Joseph P; McGillivray, Donald; Leung, Kam Tong

    2016-09-14

    Control of the spin degree of freedom of an electron has brought about a new era in spin-based applications, particularly spin-based electronics, with the potential to outperform the traditional charge-based semiconductor technology for data storage and information processing. However, the realization of functional spin-based devices for information processing remains elusive due to several fundamental challenges such as the low Curie temperature of group III-V and II-VI semiconductors (<200 K), and the low spin-injection efficiencies of existing III-V, II-VI, and transparent conductive oxide semiconductors in a multilayer device structure, which are caused by precipitation and migration of dopants from the host layer to the adjacent layers. Here, we use catalyst-assisted pulsed laser deposition to grow, for the first time, oxygen vacancy defect-rich, dopant-free ZrO2 nanostructures with high TC (700 K) and high magnetization (5.9 emu/g). The observed magnetization is significantly greater than both doped and defect-rich transparent conductive oxide nanomaterials reported to date. We also provide the first experimental evidence that it is the amounts and types of oxygen vacancy defects in, and not the phase of ZrO2 that control the ferromagnetic order in undoped ZrO2 nanostructures. To explain the origin of ferromagnetism in these ZrO2 nanostructures, we hypothesize a new defect-induced bound polaron model, which is generally applicable to other defect-rich, dopant-free transparent conductive oxide nanostructures. These results provide new insights into magnetic ordering in undoped dilute ferromagnetic semiconductor oxides and contribute to the design of exotic magnetic and novel multifunctional materials.

  18. Optoelectronic Devices and Materials

    NASA Astrophysics Data System (ADS)

    Sweeney, Stephen; Adams, Alfred

    Unlike the majority of electronic devices, which are silicon based, optoelectronic devices are predominantly made using III-V semiconductor compounds such as GaAs, InP, GaN and GaSb and their alloys due to their direct band gap. Understanding the properties of these materials has been of vital importance in the development of optoelectronic devices. Since the first demonstration of a semiconductor laser in the early 1960s, optoelectronic devices have been produced in their millions, pervading our everyday lives in communications, computing, entertainment, lighting and medicine. It is perhaps their use in optical-fibre communications that has had the greatest impact on humankind, enabling high-quality and inexpensive voice and data transmission across the globe. Optical communications spawned a number of developments in optoelectronics, leading to devices such as vertical-cavity surface-emitting lasers, semiconductor optical amplifiers, optical modulators and avalanche photodiodes. In this chapter we discuss the underlying theory of operation of the most important optoelectronic devices. The influence of carrier-photon interactions is discussed in the context of producing efficient emitters and detectors. Finally we discuss how the semiconductor band structure can be manipulated to enhance device properties using quantum confinement and strain effects, and how the addition of dilute amounts of elements such as nitrogen is having a profound effect on the next generation of optoelectronic devices.

  19. Efficient Suppression of Defects and Charge Trapping in High Density In-Sn-Zn-O Thin Film Transistor Prepared using Microwave-Assisted Sputter.

    PubMed

    Goh, Youngin; Ahn, Jaehan; Lee, Jeong Rak; Park, Wan Woo; Ko Park, Sang-Hee; Jeon, Sanghun

    2017-10-25

    Amorphous oxide semiconductor-based thin film transistors (TFTs) have been considered as excellent switching elements for driving active-matrix organic light-emitting diodes (AMOLED) owing to their high mobility and process compatibility. However, oxide semiconductors have inherent defects, causing fast transient charge trapping and device instability. For the next-generation displays such as flexible, wearable, or transparent displays, an active semiconductor layer with ultrahigh mobility and high reliability at low deposition temperature is required. Therefore, we introduced high density plasma microwave-assisted (MWA) sputtering method as a promising deposition tool for the formation of high density and high-performance oxide semiconductor films. In this paper, we present the effect of the MWA sputtering method on the defects and fast charge trapping in In-Sn-Zn-O (ITZO) TFTs using various AC device characterization methodologies including fast I-V, pulsed I-V, transient current, low frequency noise, and discharge current analysis. Using these methods, we were able to analyze the charge trapping mechanism and intrinsic electrical characteristics, and extract the subgap density of the states of oxide TFTs quantitatively. In comparison to conventional sputtered ITZO, high density plasma MWA-sputtered ITZO exhibits outstanding electrical performance, negligible charge trapping characteristics and low subgap density of states. High-density plasma MWA sputtering method has high deposition rate even at low working pressure and control the ion bombardment energy, resulting in forming low defect generation in ITZO and presenting high performance ITZO TFT. We expect the proposed high density plasma sputtering method to be applicable to a wide range of oxide semiconductor device applications.

  20. Release strategies for making transferable semiconductor structures, devices and device components

    DOEpatents

    Rogers, John A; Nuzzo, Ralph G; Meitl, Matthew; Ko, Heung Cho; Yoon, Jongseung; Menard, Etienne; Baca, Alfred J

    2014-11-25

    Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

  1. Release strategies for making transferable semiconductor structures, devices and device components

    DOEpatents

    Rogers, John A [Champaign, IL; Nuzzo, Ralph G [Champaign, IL; Meitl, Matthew [Raleigh, NC; Ko, Heung Cho [Urbana, IL; Yoon, Jongseung [Urbana, IL; Menard, Etienne [Durham, NC; Baca, Alfred J [Urbana, IL

    2011-04-26

    Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

  2. Release strategies for making transferable semiconductor structures, devices and device components

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Rogers, John A.; Nuzzo, Ralph G.; Meitl, Matthew

    2016-05-24

    Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

  3. Bulk semiconducting scintillator device for radiation detection

    DOEpatents

    Stowe, Ashley C.; Burger, Arnold; Groza, Michael

    2016-08-30

    A bulk semiconducting scintillator device, including: a Li-containing semiconductor compound of general composition Li-III-VI.sub.2, wherein III is a Group III element and VI is a Group VI element; wherein the Li-containing semiconductor compound is used in one or more of a first mode and a second mode, wherein: in the first mode, the Li-containing semiconductor compound is coupled to an electrical circuit under bias operable for measuring electron-hole pairs in the Li-containing semiconductor compound in the presence of neutrons and the Li-containing semiconductor compound is also coupled to current detection electronics operable for detecting a corresponding current in the Li-containing semiconductor compound; and, in the second mode, the Li-containing semiconductor compound is coupled to a photodetector operable for detecting photons generated in the Li-containing semiconductor compound in the presence of the neutrons.

  4. Spectroscopic Studies of the Electronic Structure of Metal-Semiconductor and Vacuum-Semiconductor Interfaces.

    DTIC Science & Technology

    1982-12-31

    interfaces which are of importance in such semi- conductor devices as MOSFETS, CCD devices, photovoltaic devices, DD I jAN 73 1473 EDITION OF INOV 66 if...interfaces is interesting for the study of electrolytic cells . Our photoemission study reveals for the first time how the electronic structure of water

  5. Semiconductor quantum wells: old technology or new device functionalities

    NASA Astrophysics Data System (ADS)

    Kolbas, R. M.; Lo, Y. C.; Hsieh, K. Y.; Lee, J. H.; Reed, F. E.; Zhang, D.; Zhang, T.

    2009-08-01

    The introduction of semiconductor quantum wells in the 1970s created a revolution in optoelectronic devices. A large fraction of today's lasers and light emitting diodes are based on quantum wells. It has been more than 30 years but novel ideas and new device functions have recently been demonstrated using quantum well heterostructures. This paper provides a brief overview of the subject and then focuses on the physics of quantum wells that the lead author believes holds the key to new device functionalities. The data and figures contained within are not new. They have been assembled from 30 years of work. They are presented to convey the story of why quantum wells continue to fuel the engine that drives the semiconductor optoelectronic business. My apologies in advance to my students and co-workers that contributed so much that could not be covered in such a short manuscript. The explanations provided are based on the simplest models possible rather than the very sophisticated mathematical models that have evolved over many years. The intended readers are those involved with semiconductor optoelectronic devices and are interested in new device possibilities.

  6. A Silicon Nanocrystal Schottky Junction Solar Cell produced from Colloidal Silicon Nanocrystals

    PubMed Central

    2010-01-01

    Solution-processed semiconductors are seen as a promising route to reducing the cost of the photovoltaic device manufacture. We are reporting a single-layer Schottky photovoltaic device that was fabricated by spin-coating intrinsic silicon nanocrystals (Si NCs) from colloidal suspension. The thin-film formation process was based on Si NCs without any ligand attachment, exchange, or removal reactions. The Schottky junction device showed a photovoltaic response with a power conversion efficiency of 0.02%, a fill factor of 0.26, short circuit-current density of 0.148 mA/cm2, and open-circuit voltage of 0.51 V. PMID:20676200

  7. Surface breakdown igniter for mercury arc devices

    DOEpatents

    Bayless, John R.

    1977-01-01

    Surface breakdown igniter comprises a semiconductor of medium resistivity which has the arc device cathode as one electrode and has an igniter anode electrode so that when voltage is applied between the electrodes a spark is generated when electrical breakdown occurs over the surface of the semiconductor. The geometry of the igniter anode and cathode electrodes causes the igniter discharge to be forced away from the semiconductor surface.

  8. Photovoltaic devices comprising zinc stannate buffer layer and method for making

    DOEpatents

    Wu, Xuanzhi; Sheldon, Peter; Coutts, Timothy J.

    2001-01-01

    A photovoltaic device has a buffer layer zinc stannate Zn.sub.2 SnO.sub.4 disposed between the semiconductor junction structure and the transparent conducting oxide (TCO) layer to prevent formation of localized junctions with the TCO through a thin window semiconductor layer, to prevent shunting through etched grain boundaries of semiconductors, and to relieve stresses and improve adhesion between these layers.

  9. Semiconductor Materials for High Frequency Solid State Sources.

    DTIC Science & Technology

    1985-01-18

    saturation on near and submicron-scale device performance. The motivation for this is as follows: Presently, individual semiconductors are accepted or...basis of all FET scaling procedures; and is a major motivating factor for going to submicron structures. This scaling was tested with the 4 following...performance. The motivation for this is as follows: Presently, individual semiconductors are accepted or rejected as candidate device materials based, in

  10. One-Dimensional Nanostructures and Devices of II–V Group Semiconductors

    PubMed Central

    2009-01-01

    The II–V group semiconductors, with narrow band gaps, are important materials with many applications in infrared detectors, lasers, solar cells, ultrasonic multipliers, and Hall generators. Since the first report on trumpet-like Zn3P2nanowires, one-dimensional (1-D) nanostructures of II–V group semiconductors have attracted great research attention recently because these special 1-D nanostructures may find applications in fabricating new electronic and optoelectronic nanoscale devices. This article covers the 1-D II–V semiconducting nanostructures that have been synthesized till now, focusing on nanotubes, nanowires, nanobelts, and special nanostructures like heterostructured nanowires. Novel electronic and optoelectronic devices built on 1-D II–V semiconducting nanostructures will also be discussed, which include metal–insulator-semiconductor field-effect transistors, metal-semiconductor field-effect transistors, andp–nheterojunction photodiode. We intent to provide the readers a brief account of these exciting research activities. PMID:20596452

  11. Main principles of developing exploitation models of semiconductor devices

    NASA Astrophysics Data System (ADS)

    Gradoboev, A. V.; Simonova, A. V.

    2018-05-01

    The paper represents primary tasks, solutions of which allow to develop the exploitation modes of semiconductor devices taking into account complex and combined influence of ionizing irradiation and operation factors. The structure of the exploitation model of the semiconductor device is presented, which is based on radiation and reliability models. Furthermore, it was shown that the exploitation model should take into account complex and combine influence of various ionizing irradiation types and operation factors. The algorithm of developing the exploitation model of the semiconductor devices is proposed. The possibility of creating the radiation model of Schottky barrier diode, Schottky field-effect transistor and Gunn diode is shown based on the available experimental data. The basic exploitation model of IR-LEDs based upon double AlGaAs heterostructures is represented. The practical application of the exploitation models will allow to output the electronic products with guaranteed operational properties.

  12. Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

    DOEpatents

    Wu, Xuanzhi; Coutts, Timothy J.; Sheldon, Peter; Rose, Douglas H.

    1999-01-01

    A photovoltaic device having a substrate, a layer of Cd.sub.2 SnO.sub.4 disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd.sub.2 SnO.sub.4, and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd.sub.2 SnO.sub.4 layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd.sub.2 SnO.sub.4, and depositing an electrically conductive film onto the thin film of semiconductor materials.

  13. Numerical simulation and characterization of trapping noise in InGaP-GaAs heterojunctions devices at high injection

    NASA Astrophysics Data System (ADS)

    Nallatamby, Jean-Christophe; Abdelhadi, Khaled; Jacquet, Jean-Claude; Prigent, Michel; Floriot, Didier; Delage, Sylvain; Obregon, Juan

    2013-03-01

    Commercially available simulators present considerable advantages in performing accurate DC, AC and transient simulations of semiconductor devices, including many fundamental and parasitic effects which are not generally taken into account in house-made simulators. Nevertheless, while the TCAD simulators of the public domain we have tested give accurate results for the simulation of diffusion noise, none of the tested simulators perform trap-assisted GR noise accurately. In order to overcome the aforementioned problem we propose a robust solution to accurately simulate GR noise due to traps. It is based on numerical processing of the output data of one of the simulators available in the public-domain, namely SENTAURUS (from Synopsys). We have linked together, through a dedicated Data Access Component (DAC), the deterministic output data available from SENTAURUS and a powerful, customizable post-processing tool developed on the mathematical SCILAB software package. Thus, robust simulations of GR noise in semiconductor devices can be performed by using GR Langevin sources associated to the scalar Green functions responses of the device. Our method takes advantage of the accuracy of the deterministic simulations of electronic devices obtained with SENTAURUS. A Comparison between 2-D simulations and measurements of low frequency noise on InGaP-GaAs heterojunctions, at low as well as high injection levels, demonstrates the validity of the proposed simulation tool.

  14. Detection of X-ray photons by solution-processed organic-inorganic perovskites

    PubMed Central

    Yakunin, Sergii; Sytnyk, Mykhailo; Kriegner, Dominik; Shrestha, Shreetu; Richter, Moses; Matt, Gebhard J.; Azimi, Hamed; Brabec, Christoph J.; Stangl, Julian; Kovalenko, Maksym V.; Heiss, Wolfgang

    2017-01-01

    The evolution of real-time medical diagnostic tools such as angiography and computer tomography from radiography based on photographic plates was enabled by the development of integrated solid-state X-ray photon detectors, based on conventional solid-state semiconductors. Recently, for optoelectronic devices operating in the visible and near infrared spectral regions, solution-processed organic and inorganic semiconductors have also attracted immense attention. Here we demonstrate a possibility to use such inexpensive semiconductors for sensitive detection of X-ray photons by direct photon-to-current conversion. In particular, methylammonium lead iodide perovskite (CH3NH3PbI3) offers a compelling combination of fast photoresponse and a high absorption cross-section for X-rays, owing to the heavy Pb and I atoms. Solution processed photodiodes as well as photoconductors are presented, exhibiting high values of X-ray sensitivity (up to 25 µC mGyair-1 cm-3) and responsivity (1.9×104 carriers/photon), which are commensurate with those obtained by the current solid-state technology. PMID:28553368

  15. Materials and Molecular Research Division annual report 1983

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Searcy, A.W.; Muller, R.H.; Peterson, C.V.

    1984-07-01

    Progress is reported in the following fields: materials sciences (metallurgy and ceramics, solid-state physics, materials chemistry), chemical sciences (fundamental interactions, processes and techniques), actinide chemistry, fossil energy, electrochemical energy storage systems, superconducting magnets, semiconductor materials and devices, and work for others. (DLC)

  16. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Shi, Zhemin; Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552; Taguchi, Dai

    The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial chargingmore » in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.« less

  17. Quantifying resistances across nanoscale low- and high-angle interspherulite boundaries in solution-processed organic semiconductor thin films.

    PubMed

    Lee, Stephanie S; Mativetsky, Jeffrey M; Loth, Marsha A; Anthony, John E; Loo, Yueh-Lin

    2012-11-27

    The nanoscale boundaries formed when neighboring spherulites impinge in polycrystalline, solution-processed organic semiconductor thin films act as bottlenecks to charge transport, significantly reducing organic thin-film transistor mobility in devices comprising spherulitic thin films as the active layers. These interspherulite boundaries (ISBs) are structurally complex, with varying angles of molecular orientation mismatch along their lengths. We have successfully engineered exclusively low- and exclusively high-angle ISBs to elucidate how the angle of molecular orientation mismatch at ISBs affects their resistivities in triethylsilylethynyl anthradithiophene thin films. Conductive AFM and four-probe measurements reveal that current flow is unaffected by the presence of low-angle ISBs, whereas current flow is significantly disrupted across high-angle ISBs. In the latter case, we estimate the resistivity to be 22 MΩμm(2)/width of the ISB, only less than a quarter of the resistivity measured across low-angle grain boundaries in thermally evaporated sexithiophene thin films. This discrepancy in resistivities across ISBs in solution-processed organic semiconductor thin films and grain boundaries in thermally evaporated organic semiconductor thin films likely arises from inherent differences in the nature of film formation in the respective systems.

  18. Nanocrystals for electronics.

    PubMed

    Panthani, Matthew G; Korgel, Brian A

    2012-01-01

    Semiconductor nanocrystals are promising materials for low-cost large-area electronic device fabrication. They can be synthesized with a wide variety of chemical compositions and size-tunable optical and electronic properties as well as dispersed in solvents for room-temperature deposition using various types of printing processes. This review addresses research progress in large-area electronic device applications using nanocrystal-based electrically active thin films, including thin-film transistors, light-emitting diodes, photovoltaics, and thermoelectrics.

  19. Doped Aluminum Gallium Arsenide (AlGaAs)/Gallium Arsenide (GaAs) Photoconductive Semiconductor Switch (PCSS) Fabrication

    DTIC Science & Technology

    2016-09-27

    contact regions and epitaxial capping layer are fabricated to investigate the advantages of both approaches. Devices were fabricated with various... Contacts 7 2.5 Packaging 11 3. Conclusions 12 4. References 13 Appendix. Detailed Fabrication Process 15 List of Symbols, Abbreviations, and...regions in violet (overlaying previous patterns) .......7 Fig. 6 Mask 4: intrinsic device contact window regions in orange (overlaying previous

  20. A full time-domain approach to spatio-temporal dynamics of semiconductor lasers. II. Spatio-temporal dynamics

    NASA Astrophysics Data System (ADS)

    Böhringer, Klaus; Hess, Ortwin

    The spatio-temporal dynamics of novel semiconductor lasers is discussed on the basis of a space- and momentum-dependent full time-domain approach. To this means the space-, time-, and momentum-dependent Full-Time Domain Maxwell Semiconductor Bloch equations, derived and discussed in our preceding paper I [K. Böhringer, O. Hess, A full time-domain approach to spatio-temporal dynamics of semiconductor lasers. I. Theoretical formulation], are solved by direct numerical integration. Focussing on the device physics of novel semiconductor lasers that profit, in particular, from recent advances in nanoscience and nanotechnology, we discuss the examples of photonic band edge surface emitting lasers (PBE-SEL) and semiconductor disc lasers (SDLs). It is demonstrated that photonic crystal effects can be obtained for finite crystal structures, and leading to a significant improvement in laser performance such as reduced lasing thresholds. In SDLs, a modern device concept designed to increase the power output of surface-emitters in combination with near-diffraction-limited beam quality, we explore the complex interplay between the intracavity optical fields and the quantum well gain material in SDL structures. Our simulations reveal the dynamical balance between carrier generation due to pumping into high energy states, momentum relaxation of carriers, and stimulated recombination from states near the band edge. Our full time-domain approach is shown to also be an excellent framework for the modelling of the interaction of high-intensity femtosecond and picosecond pulses with semiconductor nanostructures. It is demonstrated that group velocity dispersion, dynamical gain saturation and fast self-phase modulation (SPM) are the main causes for the induced changes and asymmetries in the amplified pulse shape and spectrum of an ultrashort high-intensity pulse. We attest that the time constants of the intraband scattering processes are critical to gain recovery. Moreover, we present new insight into the physics of nonlinear coherent pulse propagation phenomena in active (semiconductor) gain media. Our numerical full time-domain simulations are shown to generally agree well with analytical predictions, while in the case of optical pulses with large pulse areas or few-cycle pulses they reveal the limits of analytic approaches. Finally, it is demonstrated that coherent ultrafast nonlinear propagation effects become less distinctive if we apply a realistic model of the quantum well semiconductor gain material, consider characteristic loss channels and take into account de-phasing processes and homogeneous broadening.

  1. Light-Emitting GaAs Nanowires on a Flexible Substrate.

    PubMed

    Valente, João; Godde, Tillmann; Zhang, Yunyan; Mowbray, David J; Liu, Huiyun

    2018-06-18

    Semiconductor nanowire-based devices are among the most promising structures used to meet the current challenges of electronics, optics and photonics. Due to their high surface-to-volume ratio and excellent optical and electrical properties, devices with low power, high efficiency and high density can be created. This is of major importance for environmental issues and economic impact. Semiconductor nanowires have been used to fabricate high performance devices, including detectors, solar cells and transistors. Here, we demonstrate a technique for transferring large-area nanowire arrays to flexible substrates while retaining their excellent quantum efficiency in emission. Starting with a defect-free self-catalyzed molecular beam epitaxy (MBE) sample grown on a Si substrate, GaAs core-shell nanowires are embedded in a dielectric, removed by reactive ion etching and transferred to a plastic substrate. The original structural and optical properties, including the vertical orientation, of the nanowires are retained in the final plastic substrate structure. Nanowire emission is observed for all stages of the fabrication process, with a higher emission intensity observed for the final transferred structure, consistent with a reduction in nonradiative recombination via the modification of surface states. This transfer process could form the first critical step in the development of flexible nanowire-based light-emitting devices.

  2. Rapid, all dry microfabrication of three-dimensional Co3O4/Pt nanonetworks for high-performance microsupercapacitors.

    PubMed

    Ma, Xinyu; Feng, Shuxuan; He, Liang; Yan, Mengyu; Tian, Xiaocong; Li, Yanxi; Tang, Chunjuan; Hong, Xufeng; Mai, Liqiang

    2017-08-17

    On-chip electrochemical energy storage devices have attracted growing attention due to the decreasing size of electronic devices. Various approaches have been applied for constructing the microsupercapacitors. However, the microfabrication of high-performance microsupercapacitors by conventional and fully compatible semiconductor microfabrication technologies is still a critical challenge. Herein, unique three-dimensional (3D) Co 3 O 4 nanonetwork microelectrodes formed by the interconnection of Co 3 O 4 nanosheets are constructed by controllable physical vapor deposition combined with rapid thermal annealing. This construction process is an all dry and rapid (≤5 minutes) procedure. Afterward, by sputtering highly electrically conductive Pt nanoparticles on the microelectrodes, the 3D Co 3 O 4 /Pt nanonetworks based microsupercapacitor is fabricated, showing a high volume capacitance (35.7 F cm -3 ) at a scan rate of 20 mV s -1 due to the unique interconnected structures, high electrical conductivity and high surface area of the microelectrodes. This microfabrication process is also used to construct high-performance flexible microsupercapacitors, and it can be applied in the construction of wearable devices. The proposed strategy is completely compatible with the current semiconductor microfabrication and shows great potential in the applications of the large-scale integration of micro/nano and wearable devices.

  3. Performance improvement of GaN-based metal-semiconductor-metal photodiodes grown on Si(111) substrate by thermal cycle annealing process

    NASA Astrophysics Data System (ADS)

    Lin, Jyun-Hao; Huang, Shyh-Jer; Su, Yan-Kuin

    2014-01-01

    A simple thermal cycle annealing (TCA) process was used to improve the quality of GaN grown on a Si substrate. The X-ray diffraction (XRD) and etch pit density (EPD) results revealed that using more process cycles, the defect density cannot be further reduced. However, the performance of GaN-based metal-semiconductor-metal (MSM) photodiodes (PDs) prepared on Si substrates showed significant improvement. With a two-cycle TCA process, it is found that the dark current of the device was only 1.46 × 10-11 A, and the photo-to-dark-current contrast ratio was about 1.33 × 105 at 5 V. Also, the UV/visible rejection ratios can reach as high as 1077.

  4. Methods for growth of relatively large step-free SiC crystal surfaces

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G. (Inventor); Powell, J. Anthony (Inventor)

    2002-01-01

    A method for growing arrays of large-area device-size films of step-free (i.e., atomically flat) SiC surfaces for semiconductor electronic device applications is disclosed. This method utilizes a lateral growth process that better overcomes the effect of extended defects in the seed crystal substrate that limited the obtainable step-free area achievable by prior art processes. The step-free SiC surface is particularly suited for the heteroepitaxial growth of 3C (cubic) SiC, AlN, and GaN films used for the fabrication of both surface-sensitive devices (i.e., surface channel field effect transistors such as HEMT's and MOSFET's) as well as high-electric field devices (pn diodes and other solid-state power switching devices) that are sensitive to extended crystal defects.

  5. High voltage semiconductor devices and methods of making the devices

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Matocha, Kevin; Chatty, Kiran; Banerjee, Sujit

    A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias.more » The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.« less

  6. High voltage semiconductor devices and methods of making the devices

    DOEpatents

    Matocha, Kevin; Chatty, Kiran; Banerjee, Sujit

    2017-02-28

    A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

  7. High gain photoconductive semiconductor switch having tailored doping profile zones

    DOEpatents

    Baca, Albert G.; Loubriel, Guillermo M.; Mar, Alan; Zutavern, Fred J; Hjalmarson, Harold P.; Allerman, Andrew A.; Zipperian, Thomas E.; O'Malley, Martin W.; Helgeson, Wesley D.; Denison, Gary J.; Brown, Darwin J.; Sullivan, Charles T.; Hou, Hong Q.

    2001-01-01

    A photoconductive semiconductor switch with tailored doping profile zones beneath and extending laterally from the electrical contacts to the device. The zones are of sufficient depth and lateral extent to isolate the contacts from damage caused by the high current filaments that are created in the device when it is turned on. The zones may be formed by etching depressions into the substrate, then conducting epitaxial regrowth in the depressions with material of the desired doping profile. They may be formed by surface epitaxy. They may also be formed by deep diffusion processes. The zones act to reduce the energy density at the contacts by suppressing collective impact ionization and formation of filaments near the contact and by reducing current intensity at the contact through enhanced current spreading within the zones.

  8. Electrical characterization of organic thin film transistors and alternative device architectures

    NASA Astrophysics Data System (ADS)

    Newman, Christopher R.

    In the last 10--15 years, organic semiconductors have evolved from experimental curiosities into viable alternatives for practical applications involving large-area and low-cost electronics such as display backplanes, electronic paper, radio frequency identification (RFID) tags, and solar cells. Many of the initially-stated goals in this field have been achieved; organic semconductors have demonstrated performance comparable to or greater than amorphous silicon (a-Si), the entrenched technology for most of the applications listed above. At present, the major obstacles remaining to commercialization of devices based on organic semiconductors involve material stability, processing considerations and optimization of the other device components (e.g. metal contacts and dielectric materials). Despite these technical achievements, significant gaps remain in our understanding of the underlying transport physics in these devices. This thesis summarizes experiments performed on organic field-effect transistors (OFETs) in an attempt to address some of these knowledge gaps. The FET, in addition to being a very useful device for practical applications (such as the driving elements in pixel backplanes), is also a very flexible architecture from an experimental standpoint. The presence of a capacitively-coupled gate electrode allows the investigation of transport physics as a function of carrier concentration. For devices in which non-idealities (i.e. carrier traps) largely dictate the observed characteristics, this is a very useful feature. Although practical OFETs are fabricated as conventional single-gate structures on an organic thin film (OTFTs), more exotic structures can often provide insights that standard OTFTs cannot. Specifically, single-crystal OFETs allow the investigation of carrier transport in the absence of grain boundaries, and double-gated OTFTs facilitate the investigation and comparison of properties across two discrete interfaces. One of the remaining challenges in terms of achieving stability inorganic semiconductors involves understanding, and hopefully minimizing, the bias stress effect of operating OTFTs. Largely ignored during the years in which research groups sought to optimize the standard device metrics of field-effect mobility, current on/off ratio, and threshold voltage, operational stability is emerging as a dominant consideration in these materials. Experiments performed with the goal of quantifying and understanding the bias-stress effect in organic semiconductors are described at the end of this thesis.

  9. Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

    PubMed

    Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

    2011-01-01

    The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

  10. All-inkjet-printed flexible ZnO micro photodetector for a wearable UV monitoring device

    NASA Astrophysics Data System (ADS)

    Tran, Van-Thai; Wei, Yuefan; Yang, Hongyi; Zhan, Zhaoyao; Du, Hejun

    2017-03-01

    Fabrication of small-sized patterns of inorganic semiconductor onto flexible substrates is a major concern when manufacturing wearable devices for measuring either biometric or environmental parameters. In this study, micro-sized flexible ZnO UV photodetectors have been thoroughly prepared by a facile inkjet printing technology and followed with heat treatments. A simple ink recipe of zinc acetate precursor solution was investigated. It is found that the substrate temperature during zinc precursor ink depositing has significant effects on ZnO pattern shape, film morphology, and crystallization. The device fabricated from the additive manufacturing approach has good bendability, Ohmic contact, short response time as low as 0.3 s, and high on/off ratio of 3525. We observed the sensor’s dependence of response/decay time by the illuminating UV light intensity. The whole process is based on additive manufacturing which has many benefits such as rapid prototyping, saving material, being environmentally friendly, and being capable of creating high-resolution patterns. In addition, this method can be applied to flexible substrates, which makes the device more applicable for applications requiring flexibility such as wearable devices. The proposed all-inkjet-printing approach for a micro-sized ZnO UV photodetector would significantly simplify the fabrication process of micro-sized inorganic semiconductor-based devices. A potential application is real-time monitoring of UV light exposure to warn users about unsafe direct sunlight to implement suitable avoidance solutions.

  11. Inverted organic electronic and optoelectronic devices

    NASA Astrophysics Data System (ADS)

    Small, Cephas E.

    The research and development of organic electronics for commercial application has received much attention due to the unique properties of organic semiconductors and the potential for low-cost high-throughput manufacturing. For improved large-scale processing compatibility and enhanced device stability, an inverted geometry has been employed for devices such as organic light emitting diodes and organic photovoltaic cells. These improvements are attributed to the added flexibility to incorporate more air-stable materials into the inverted device geometry. However, early work on organic electronic devices with an inverted geometry typically showed reduced device performance compared to devices with a conventional structure. In the case of organic light emitting diodes, inverted devices typically show high operating voltages due to insufficient carrier injection. Here, a method for enhancing hole injection in inverted organic electronic devices is presented. By incorporating an electron accepting interlayer into the inverted device, a substantial enhancement in hole injection efficiency was observed as compared to conventional devices. Through a detailed carrier injection study, it is determined that the injection efficiency enhancements in the inverted devices are due to enhanced charge transfer at the electron acceptor/organic semiconductor interface. A similar situation is observed for organic photovoltaic cells, in which devices with an inverted geometry show limited carrier extraction in early studies. In this work, enhanced carrier extraction is demonstrated for inverted polymer solar cells using a surface-modified ZnO-polymer composite electron-transporting layer. The insulating polymer in the composite layer inhibited aggregation of the ZnO nanoparticles, while the surface-modification of the composite interlayer improved the electronic coupling with the photoactive layer. As a result, inverted polymer solar cells with power conversion efficiencies of over 8% were obtained. To further study carrier extraction in inverted polymer solar cells, the active layer thickness dependence of the efficiency was investigated. For devices with active layer thickness < 200 nm, power conversion efficiencies over 8% was obtained. This result is important for demonstrating improved large-scale processing compatibility. Above 200 nm, significant reduction in cell efficiency were observed. A detailed study of the loss processes that contributed to the reduction in efficiency for thick-film devices are presented.

  12. Organic Donor-Acceptor Complexes as Novel Organic Semiconductors.

    PubMed

    Zhang, Jing; Xu, Wei; Sheng, Peng; Zhao, Guangyao; Zhu, Daoben

    2017-07-18

    Organic donor-acceptor (DA) complexes have attracted wide attention in recent decades, resulting in the rapid development of organic binary system electronics. The design and synthesis of organic DA complexes with a variety of component structures have mainly focused on metallicity (or even superconductivity), emission, or ferroelectricity studies. Further efforts have been made in high-performance electronic investigations. The chemical versatility of organic semiconductors provides DA complexes with a great number of possibilities for semiconducting applications. Organic DA complexes extend the semiconductor family and promote charge separation and transport in organic field-effect transistors (OFETs) and organic photovoltaics (OPVs). In OFETs, the organic complex serves as an active layer across extraordinary charge pathways, ensuring the efficient transport of induced charges. Although an increasing number of organic semiconductors have been reported to exhibit good p- or n-type properties (mobilities higher than 1 or even 10 cm 2 V -1 s -1 ), critical scientific challenges remain in utilizing the advantages of existing semiconductor materials for more and wider applications while maintaining less complicated synthetic or device fabrication processes. DA complex materials have revealed new insight: their unique molecular packing and structure-property relationships. The combination of donors and acceptors could offer practical advantages compared with their unimolecular materials. First, growing crystals of DA complexes with densely packed structures will reduce impurities and traps from the self-assembly process. Second, complexes based on the original structural components could form superior mixture stacking, which can facilitate charge transport depending on the driving force in the coassembly process. Third, the effective use of organic semiconductors can lead to tunable band structures, allowing the operation mode (p- or n-type) of the transistor to be systematically controlled by changing the components. Finally, theoretical calculations based on cocrystals with unique stacking could widen our understanding of structure-property relationships and in turn help us design high-performance semiconductors based on DA complexes. In this Account, we focus on discussing organic DA complexes as a new class of semiconducting materials, including their design, growth methods, packing modes, charge-transport properties, and structure-property relationships. We have also fabricated and investigated devices based on these binary crystals. This interdisciplinary work combines techniques from the fields of self-assembly, crystallography, condensed-matter physics, and theoretical chemistry. Researchers have designed new complex systems, including donor and acceptor compounds that self-assemble in feasible ways into highly ordered cocrystals. We demonstrate that using this crystallization method can easily realize ambipolar or unipolar transport. To further improve device performance, we propose several design strategies, such as using new kinds of donors and acceptors, modulating the energy alignment of the donor (ionization potential, IP) and acceptor (electron affinity, EA) components, and extending the π-conjugated backbones. In addition, we have found that when we use molecular "doping" (2:1 cocrystallization), the charge-transport nature of organic semiconductors can be switched from hole-transport-dominated to electron-transport-dominated. We expect that the formation of cocrystals through the complexation of organic donor and acceptor species will serve as a new strategy to develop semiconductors for organic electronics with superior performances over their corresponding individual components.

  13. Wide Bandgap Extrinsic Photoconductive Switches

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sullivan, James S.

    2012-01-20

    Photoconductive semiconductor switches (PCSS) have been investigated since the late 1970s. Some devices have been developed that withstand tens of kilovolts and others that switch hundreds of amperes. However, no single device has been developed that can reliably withstand both high voltage and switch high current. Yet, photoconductive switches still hold the promise of reliable high voltage and high current operation with subnanosecond risetimes. Particularly since good quality, bulk, single crystal, wide bandgap semiconductor materials have recently become available. In this chapter we will review the basic operation of PCSS devices, status of PCSS devices and properties of the widemore » bandgap semiconductors 4H-SiC, 6H-SiC and 2H-GaN.« less

  14. NREL Finds Nanotube Semiconductors Well-suited for PV Systems | News | NREL

    Science.gov Websites

    photoinduced electron transfer for emerging organic semiconductors such as single-walled carbon nanotubes (SWCNT) that can be used in organic PV devices. In organic PV devices, after a photon is absorbed Larson, and Steven Strauss from Colorado State University. Organic PV devices involve an interface

  15. Hybrid method of making an amorphous silicon P-I-N semiconductor device

    DOEpatents

    Moustakas, Theodore D.; Morel, Don L.; Abeles, Benjamin

    1983-10-04

    The invention is directed to a hydrogenated amorphous silicon PIN semiconductor device of hybrid glow discharge/reactive sputtering fabrication. The hybrid fabrication method is of advantage in providing an ability to control the optical band gap of the P and N layers, resulting in increased photogeneration of charge carriers and device output.

  16. Development of p-type oxide semiconductors based on tin oxide and its alloys: application to thin film transistors

    NASA Astrophysics Data System (ADS)

    Barros, Ana Raquel Xarouco de

    In spite of the recent p-type oxide TFTs developments based on SnOx and CuxO, the results achieved so far refer to devices processed at high temperatures and are limited by a low hole mobility and a low On-Off ratio and still there is no report on p-type oxide TFTs with performance similar to n-type, especially when comparing their field-effect mobility values, which are at least one order of magnitude higher on n-type oxide TFTs. Achieving high performance p-type oxide TFTs will definitely promote a new era for electronics in rigid and flexible substrates, away from silicon. None of the few reported p-channel oxide TFTs is suitable for practical applications, which demand significant improvements in the device engineering to meet the real-world electronic requirements, where low processing temperatures together with high mobility and high On-Off ratio are required for TFT and CMOS applications. The present thesis focuses on the study and optimization of p-type thin film transistors based on oxide semiconductors deposited by r.f. magnetron sputtering without intentional substrate heating. In this work several p-type oxide semiconductors were studied and optimized based on undoped tin oxide, Cu-doped SnOx and In-doped SnO2.

  17. Lorentz factor determination for local electric fields in semiconductor devices utilizing hyper-thin dielectrics

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    McPherson, J. W., E-mail: mcpherson.reliability@yahoo.com

    The local electric field (the field that distorts, polarizes, and weakens polar molecular bonds in dielectrics) has been investigated for hyper-thin dielectrics. Hyper-thin dielectrics are currently required for advanced semiconductor devices. In the work presented, it is shown that the common practice of using a Lorentz factor of L = 1/3, to describe the local electric field in a dielectric layer, remains valid for hyper-thin dielectrics. However, at the very edge of device structures, a rise in the macroscopic/Maxwell electric field E{sub diel} occurs and this causes a sharp rise in the effective Lorentz factor L{sub eff}. At capacitor and transistor edges,more » L{sub eff} is found to increase to a value 2/3 < L{sub eff} < 1. The increase in L{sub eff} results in a local electric field, at device edge, that is 50%–100% greater than in the bulk of the dielectric. This increase in local electric field serves to weaken polar bonds thus making them more susceptible to breakage by standard Boltzmann and/or current-driven processes. This has important time-dependent dielectric breakdown (TDDB) implications for all electronic devices utilizing polar materials, including GaN devices that suffer from device-edge TDDB.« less

  18. Processing approach towards the formation of thin-film Cu(In,Ga)Se2

    DOEpatents

    Beck, Markus E.; Noufi, Rommel

    2003-01-01

    A two-stage method of producing thin-films of group IB-IIIA-VIA on a substrate for semiconductor device applications includes a first stage of depositing an amorphous group IB-IIIA-VIA precursor onto an unheated substrate, wherein the precursor contains all of the group IB and group IIIA constituents of the semiconductor thin-film to be produced in the stoichiometric amounts desired for the final product, and a second stage which involves subjecting the precursor to a short thermal treatment at 420.degree. C.-550.degree. C. in a vacuum or under an inert atmosphere to produce a single-phase, group IB-III-VIA film. Preferably the precursor also comprises the group VIA element in the stoichiometric amount desired for the final semiconductor thin-film. The group IB-IIIA-VIA semiconductor films may be, for example, Cu(In,Ga)(Se,S).sub.2 mixed-metal chalcogenides. The resultant supported group IB-IIIA-VIA semiconductor film is suitable for use in photovoltaic applications.

  19. Dual ohmic contact to N- and P-type silicon carbide

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2013-01-01

    Simultaneous formation of electrical ohmic contacts to silicon carbide (SiC) semiconductor having donor and acceptor impurities (n- and p-type doping, respectively) is disclosed. The innovation provides for ohmic contacts formed on SiC layers having n- and p-doping at one process step during the fabrication of the semiconductor device. Further, the innovation provides a non-discriminatory, universal ohmic contact to both n- and p-type SiC, enhancing reliability of the specific contact resistivity when operated at temperatures in excess of 600.degree. C.

  20. Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

    NASA Technical Reports Server (NTRS)

    Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

    2016-01-01

    Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

  1. Metal oxide semiconductor thin-film transistors for flexible electronics

    NASA Astrophysics Data System (ADS)

    Petti, Luisa; Münzenrieder, Niko; Vogt, Christian; Faber, Hendrik; Büthe, Lars; Cantarella, Giuseppe; Bottacchi, Francesca; Anthopoulos, Thomas D.; Tröster, Gerhard

    2016-06-01

    The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This review reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.

  2. Metal oxide semiconductor thin-film transistors for flexible electronics

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Petti, Luisa; Vogt, Christian; Büthe, Lars

    The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This reviewmore » reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.« less

  3. Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

    NASA Astrophysics Data System (ADS)

    Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

    2015-08-01

    Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

  4. Fused thiophene-based conjugated polymers and their use in optoelectronic devices

    DOEpatents

    Facchetti, Antonio; Marks, Tobin J; Takai, Atsuro; Seger, Mark; Chen, Zhihua

    2015-11-03

    The present teachings relate to certain polymeric compounds and their use as organic semiconductors in organic and hybrid optical, optoelectronic, and/or electronic devices such as photovoltaic cells, light emitting diodes, light emitting transistors, and field effect transistors. The disclosed compounds can provide improved device performance, for example, as measured by power conversion efficiency, fill factor, open circuit voltage, field-effect mobility, on/off current ratios, and/or air stability when used in photovoltaic cells or transistors. The disclosed compounds can have good solubility in common solvents enabling device fabrication via solution processes.

  5. Testing methodologies and systems for semiconductor optical amplifiers

    NASA Astrophysics Data System (ADS)

    Wieckowski, Michael

    Semiconductor optical amplifiers (SOA's) are gaining increased prominence in both optical communication systems and high-speed optical processing systems, due primarily to their unique nonlinear characteristics. This in turn, has raised questions regarding their lifetime performance reliability and has generated a demand for effective testing techniques. This is especially critical for industries utilizing SOA's as components for system-in-package products. It is important to note that very little research to date has been conducted in this area, even though production volume and market demand has continued to increase. In this thesis, the reliability of dilute-mode InP semiconductor optical amplifiers is studied experimentally and theoretically. The aging characteristics of the production level devices are demonstrated and the necessary techniques to accurately characterize them are presented. In addition, this work proposes a new methodology for characterizing the optical performance of these devices using measurements in the electrical domain. It is shown that optical performance degradation, specifically with respect to gain, can be directly qualified through measurements of electrical subthreshold differential resistance. This metric exhibits a linear proportionality to the defect concentration in the active region, and as such, can be used for prescreening devices before employing traditional optical testing methods. A complete theoretical analysis is developed in this work to explain this relationship based upon the device's current-voltage curve and its associated leakage and recombination currents. These results are then extended to realize new techniques for testing semiconductor optical amplifiers and other similarly structured devices. These techniques can be employed after fabrication and during packaged operation through the use of a proposed stand-alone testing system, or using a proposed integrated CMOS self-testing circuit. Both methods are capable of ascertaining SOA performance based solely on the subthreshold differential resistance signature, and are a first step toward the inevitable integration of self-testing circuits into complex optoelectronic systems.

  6. Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

    NASA Astrophysics Data System (ADS)

    Tu, Hongen

    This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

  7. IEEE WMED 2016 Homepage

    Science.gov Websites

    characterization, design, and new device technologies. This workshop will consist of invited talks, contributed and Reliability Semiconductor package reliability, Design for Manufacturability, Stacked die packaging and Novel assembly processes Microelectronic Circuit Design New product design, high-speed and/or low

  8. Tuning polymorphism and orientation in organic semiconductor thin films via post-deposition processing.

    PubMed

    Hiszpanski, Anna M; Baur, Robin M; Kim, Bumjung; Tremblay, Noah J; Nuckolls, Colin; Woll, Arthur R; Loo, Yueh-Lin

    2014-11-05

    Though both the crystal structure and molecular orientation of organic semiconductors are known to impact charge transport in thin-film devices, separately accessing different polymorphs and varying the out-of-plane molecular orientation is challenging, typically requiring stringent control over film deposition conditions, film thickness, and substrate chemistry. Here we demonstrate independent tuning of the crystalline polymorph and molecular orientation in thin films of contorted hexabenzocoronene, c-HBC, during post-deposition processing without the need to adjust deposition conditions. Three polymorphs are observed, two of which have not been previously reported. Using our ability to independently tune the crystal structure and out-of-plane molecular orientation in thin films of c-HBC, we have decoupled and evaluated the effects that molecular packing and orientation have on device performance in thin-film transistors (TFTs). In the case of TFTs comprising c-HBC, polymorphism and molecular orientation are equally important; independently changing either one affects the field-effect mobility by an order of magnitude.

  9. Measuring the complete cross-cell carrier mobility distributions in bulk heterojunction solar cells

    NASA Astrophysics Data System (ADS)

    Seifter, Jason; Sun, Yanming; Choi, Hyosung; Lee, Byoung Hoon; Heeger, Alan

    2015-03-01

    Carbon nanotube-enabled, vertical, organic field effect transistors (CN-VFETs) based on the small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) have demonstrated high current, low-power operation suitable for driving active matix organic light emitting diode (AMOLED) displays. This performance is achieved without the need for costly high-resolution patterning, despite the low mobility of the organic semiconductor, by employing sub-micron channel widths, defined in the vertical devices by the thickness of the semiconducting layer. Replacing the thermally evaporated small molecule semiconductor with a solution-processed polymer would possibly further simplify the fabrication process and reduce manufacturing cost. Here we investigate several polymer systems as wide bandgap semiconducting channel layers for potentially air stable and transparent CN-VFETs. The field effect mobility and optical transparency of the polymer layers are determined, and the performance and air stability of CN-VFET devices are measured. A. S. gratefully acknowledges support from the National Science Foundation under DMR-1156737.

  10. Thermovoltaic semiconductor device including a plasma filter

    DOEpatents

    Baldasaro, Paul F.

    1999-01-01

    A thermovoltaic energy conversion device and related method for converting thermal energy into an electrical potential. An interference filter is provided on a semiconductor thermovoltaic cell to pre-filter black body radiation. The semiconductor thermovoltaic cell includes a P/N junction supported on a substrate which converts incident thermal energy below the semiconductor junction band gap into electrical potential. The semiconductor substrate is doped to provide a plasma filter which reflects back energy having a wavelength which is above the band gap and which is ineffectively filtered by the interference filter, through the P/N junction to the source of radiation thereby avoiding parasitic absorption of the unusable portion of the thermal radiation energy.

  11. Semiconductor cooling by thin-film thermocouples

    NASA Technical Reports Server (NTRS)

    Tick, P. A.; Vilcans, J.

    1970-01-01

    Thin-film, metal alloy thermocouple junctions do not rectify, change circuit impedance only slightly, and require very little increase in space. Although they are less efficient cooling devices than semiconductor junctions, they may be applied to assist conventional cooling techniques for electronic devices.

  12. Multiple gap photovoltaic device

    DOEpatents

    Dalal, Vikram L.

    1981-01-01

    A multiple gap photovoltaic device having a transparent electrical contact adjacent a first cell which in turn is adjacent a second cell on an opaque electrical contact, includes utilizing an amorphous semiconductor as the first cell and a crystalline semiconductor as the second cell.

  13. Exploration of Gas Discharges with GaAs, GaP and ZnSe Electrodes Under Atmospheric Pressure

    NASA Astrophysics Data System (ADS)

    Kurt, H. Hilal

    2018-03-01

    This work reports on the electrical and optical characterization of the atmospheric pressure glow discharge regimes for different semiconductor electrodes made of GaAs, GaP and ZnSe. The discharge cell is driven by DC feeding voltages at a wide pressure range of 0.66-120 kPa in argon and air media for different interelectrode gaps. The discharge phenomena including different stages of discharges such as glow and Townsend breakdown have been examined. In addition, the infrared sensitivities of the semiconducting materials are evaluated in the micro-discharge cell and discharge light emission measurements have been performed. The qualities of the semiconducting electrode samples can be determined by seeking the homogeneity of the discharge light emission for the optoelectronic device applications. Operation of optical devices under atmospheric pressures gives certain advantages for manufacturing of the devices including the material processing and surface treatment procedures. Besides, finite element analyses of the overall experimental system have been performed for the abovementioned semiconductors. The electron densities and potential patterns have been determined on the discharge cell plane between the electrodes. The findings have proven that the electron densities along the plasma cell depend on both the semiconductor type and plasma parameters.

  14. High efficiency photovoltaic device

    DOEpatents

    Guha, Subhendu; Yang, Chi C.; Xu, Xi Xiang

    1999-11-02

    An N-I-P type photovoltaic device includes a multi-layered body of N-doped semiconductor material which has an amorphous, N doped layer in contact with the amorphous body of intrinsic semiconductor material, and a microcrystalline, N doped layer overlying the amorphous, N doped material. A tandem device comprising stacked N-I-P cells may further include a second amorphous, N doped layer interposed between the microcrystalline, N doped layer and a microcrystalline P doped layer. Photovoltaic devices thus configured manifest improved performance, particularly when configured as tandem devices.

  15. New Concentric Electrode Metal-Semiconductor-Metal Photodetectors

    NASA Technical Reports Server (NTRS)

    Towe, Elias

    1996-01-01

    A new metal-semiconductor-metal (MSM) photodetector geometry is proposed. The new device has concentric metal electrodes which exhibit a high degree of symmetry and a design flexibility absent in the conventional MSM device. The concentric electrodes are biased to alternating potentials as in the conventional interdigitated device. Because of the high symmetry configuration, however, the new device also has a lower effective capacitance. This device and the conventional MSM structure are analyzed within a common theoretical framework which allows for the comparison of the important performance characteristics.

  16. High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

    NASA Astrophysics Data System (ADS)

    Houin, G.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

    2016-09-01

    The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance with hysteresis-free characteristics. A number of approaches were applied to simplify the process, improve device performance and decrease the operating voltage: they include an oxide interfacial layer to decrease contact resistance; a polymer passivation layer to optimize semiconductor/dielectric interface and an anodized high-k oxide as dielectric layer for low voltage operation. The devices fabricated on plastic substrate yielded excellent electrical characteristics, showing mobility of 1.6 cm2/Vs, lack of hysteresis, operation below 5 V and on/off current ratio above 105. An OFET model based on variable ranging hopping theory was used to extract the relevant parameters from the transfer and output characteristics, which enabled us to simulate our devices achieving reasonable agreement with the measurements

  17. Methods of producing strain in a semiconductor waveguide and related devices

    DOEpatents

    Cox, Johathan Albert; Rakich, Peter Thomas

    2016-02-16

    Quasi-phase matched (QPM), semiconductor photonic waveguides include periodically-poled alternating first and second sections. The first sections exhibit a high degree of optical coupling (abbreviated "X.sup.2"), while the second sections have a low X.sup.2. The alternating first and second sections may comprise high-strain and low-strain sections made of different material states (such as crystalline and amorphous material states) that exhibit high and low X.sup.2 properties when formed on a particular substrate, and/or strained corrugated sections of different widths. The QPM semiconductor waveguides may be implemented as silicon-on-insulator (SOI), or germanium-on-silicon structures compatible with standard CMOS processes, or as silicon-on-sapphire (SOS) structures.

  18. Nonequilibrium carrier dynamics in transition metal dichalcogenide semiconductors

    NASA Astrophysics Data System (ADS)

    Steinhoff, A.; Florian, M.; Rösner, M.; Lorke, M.; Wehling, T. O.; Gies, C.; Jahnke, F.

    2016-09-01

    When exploring new materials for their potential in (opto)electronic device applications, it is important to understand the role of various carrier interaction and scattering processes. In atomically thin transition metal dichalcogenide semiconductors, the Coulomb interaction is known to be much stronger than in quantum wells of conventional semiconductors like GaAs, as witnessed by the 50 times larger exciton binding energy. The question arises, whether this directly translates into equivalently faster carrier-carrier Coulomb scattering of excited carriers. Here we show that a combination of ab initio band-structure and many-body theory predicts Coulomb-mediated carrier relaxation on a sub-100 fs time scale for a wide range of excitation densities, which is less than an order of magnitude faster than in quantum wells.

  19. Frequency-doubled vertical-external-cavity surface-emitting laser

    DOEpatents

    Raymond, Thomas D.; Alford, William J.; Crawford, Mary H.; Allerman, Andrew A.

    2002-01-01

    A frequency-doubled semiconductor vertical-external-cavity surface-emitting laser (VECSEL) is disclosed for generating light at a wavelength in the range of 300-550 nanometers. The VECSEL includes a semiconductor multi-quantum-well active region that is electrically or optically pumped to generate lasing at a fundamental wavelength in the range of 600-1100 nanometers. An intracavity nonlinear frequency-doubling crystal then converts the fundamental lasing into a second-harmonic output beam. With optical pumping with 330 milliWatts from a semiconductor diode pump laser, about 5 milliWatts or more of blue light can be generated at 490 nm. The device has applications for high-density optical data storage and retrieval, laser printing, optical image projection, chemical-sensing, materials processing and optical metrology.

  20. Organic photosensitive cells grown on rough electrode with nano-scale morphology control

    DOEpatents

    Yang, Fan [Piscataway, NJ; Forrest, Stephen R [Ann Arbor, MI

    2011-06-07

    An optoelectronic device and a method for fabricating the optoelectronic device includes a first electrode disposed on a substrate, an exposed surface of the first electrode having a root mean square roughness of at least 30 nm and a height variation of at least 200 nm, the first electrode being transparent. A conformal layer of a first organic semiconductor material is deposited onto the first electrode by organic vapor phase deposition, the first organic semiconductor material being a small molecule material. A layer of a second organic semiconductor material is deposited over the conformal layer. At least some of the layer of the second organic semiconductor material directly contacts the conformal layer. A second electrode is deposited over the layer of the second organic semiconductor material. The first organic semiconductor material is of a donor-type or an acceptor-type relative to the second organic semiconductor material, which is of the other material type.

  1. Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

    DOEpatents

    Wu, X.; Coutts, T.J.; Sheldon, P.; Rose, D.H.

    1999-07-13

    A photovoltaic device is disclosed having a substrate, a layer of Cd[sub 2]SnO[sub 4] disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd[sub 2]SnO[sub 4], and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd[sub 2]SnO[sub 4] layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd[sub 2]SnO[sub 4], and depositing an electrically conductive film onto the thin film of semiconductor materials. 10 figs.

  2. Enhanced photoconductivity by melt quenching method for amorphous organic photorefractive materials

    NASA Astrophysics Data System (ADS)

    Tsujimura, S.; Fujihara, T.; Sassa, T.; Kinashi, K.; Sakai, W.; Ishibashi, K.; Tsutsumi, N.

    2014-10-01

    For many optical semiconductor fields of study, the high photoconductivity of amorphous organic semiconductors has strongly been desired, because they make the manufacture of high-performance devices easy when controlling charge carrier transport and trapping is otherwise difficult. This study focuses on the correlation between photoconductivity and bulk state in amorphous organic photorefractive materials to probe the nature of the performance of photoconductivity and to enhance the response time and diffraction efficiency of photorefractivity. The general cooling processes of the quenching method achieved enhanced photoconductivity and a decreased filling rate for shallow traps. Therefore, sample processing, which was quenching in the present case, for photorefractive composites significantly relates to enhanced photorefractivity.

  3. Radiation tolerant 1 micron CMOS technology

    NASA Astrophysics Data System (ADS)

    Crevel, P.; Rodde, K.

    1991-03-01

    Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

  4. A Novel SPM Probe with MOS Transistor and Nano Tip for Surface Electric Properties

    NASA Astrophysics Data System (ADS)

    Lee, Sang H.; Lim, Geunbae; Moon, Wonkyu

    2007-03-01

    In this paper, the novel SPM (Scanning Probe Microscope) probe with the planar MOS (Metal-Oxide-Semiconductor) transistor and the FIB (Focused Ion Beam) nano tip is fabricated for the surface electric properties. Since the MOS transistor has high working frequency, the device can overcome the speed limitation of EFM (Electrostatic Force Microscope) system. The sensitivity is also high, and no bulky device such as lock-in-amplifier is required. Moreover, the nano tip with nanometer scale tip radius is fabricated with FIB system, and the resolution can be improved. Therefore, the probe can rapidly detect small localized electric properties with high sensitivity and high resolution. The MOS transistor is fabricated with the common semiconductor process, and the nano tip is grown by the FIB system. The planar structure of the MOS transistor makes the fabrication process easier, which is the advantage on the commercial production. Various electric signals are applied using the function generator, and the measured data represent the well-established electric properties of the device. It shows the promising aspect of the local surface electric property detection with high sensitivity and high resolution.

  5. Prospects and fundamental limitations of room temperature, non-avalanche, semiconductor photon-counting sensors (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Ma, Jiaju; Zhang, Yang; Wang, Xiaoxin; Ying, Lei; Masoodian, Saleh; Wang, Zhiyuan; Starkey, Dakota A.; Deng, Wei; Kumar, Rahul; Wu, Yang; Ghetmiri, Seyed Amir; Yu, Zongfu; Yu, Shui-Qing; Salamo, Gregory J.; Fossum, Eric R.; Liu, Jifeng

    2017-05-01

    This research investigates the fundamental limits and trade-space of quantum semiconductor photodetectors using the Schrödinger equation and the laws of thermodynamics.We envision that, to optimize the metrics of single photon detection, it is critical to maximize the optical absorption in the minimal volume and minimize the carrier transit process simultaneously. Integration of photon management with quantum charge transport/redistribution upon optical excitation can be engineered to maximize the quantum efficiency (QE) and data rate and minimize timing jitter at the same time. Due to the ultra-low capacitance of these quantum devices, even a single photoelectron transfer can induce a notable change in the voltage, enabling non-avalanche single photon detection at room temperature as has been recently demonstrated in Si quanta image sensors (QIS). In this research, uniform III-V quantum dots (QDs) and Si QIS are used as model systems to test the theory experimentally. Based on the fundamental understanding, we also propose proof-of-concept, photon-managed quantum capacitance photodetectors. Built upon the concepts of QIS and single electron transistor (SET), this novel device structure provides a model system to synergistically test the fundamental limits and tradespace predicted by the theory for semiconductor detectors. This project is sponsored under DARPA/ARO's DETECT Program: Fundamental Limits of Quantum Semiconductor Photodetectors.

  6. Semiconductor-Based Photoelectrochemical Conversion of Carbon Dioxide: Stepping Towards Artificial Photosynthesis.

    PubMed

    Pang, Hong; Masuda, Takuya; Ye, Jinhua

    2018-01-18

    The photoelectrochemical (PEC) carbon dioxide reduction process stands out as a promising avenue for the conversion of solar energy into chemical feedstocks, among various methods available for carbon dioxide mitigation. Semiconductors derived from cheap and abundant elements are interesting candidates for catalysis. Whether employed as intrinsic semiconductors or hybridized with metallic cocatalysts, biocatalysts, and metal molecular complexes, semiconductor photocathodes exhibit good performance and low overpotential during carbon dioxide reduction. Apart from focusing on carbon dioxide reduction materials and chemistry, PEC cells towards standalone devices that use photohybrid electrodes or solar cells have also been a hot topic in recent research. An overview of the state-of-the-art progress in PEC carbon dioxide reduction is presented and a deep understanding of the catalysts of carbon dioxide reduction is also given. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. Nanocrystal doped matrixes

    DOEpatents

    Parce, J. Wallace; Bernatis, Paul; Dubrow, Robert; Freeman, William P.; Gamoras, Joel; Kan, Shihai; Meisel, Andreas; Qian, Baixin; Whiteford, Jeffery A.; Ziebarth, Jonathan

    2010-01-12

    Matrixes doped with semiconductor nanocrystals are provided. In certain embodiments, the semiconductor nanocrystals have a size and composition such that they absorb or emit light at particular wavelengths. The nanocrystals can comprise ligands that allow for mixing with various matrix materials, including polymers, such that a minimal portion of light is scattered by the matrixes. The matrixes of the present invention can also be utilized in refractive index matching applications. In other embodiments, semiconductor nanocrystals are embedded within matrixes to form a nanocrystal density gradient, thereby creating an effective refractive index gradient. The matrixes of the present invention can also be used as filters and antireflective coatings on optical devices and as down-converting layers. Processes for producing matrixes comprising semiconductor nanocrystals are also provided. Nanostructures having high quantum efficiency, small size, and/or a narrow size distribution are also described, as are methods of producing indium phosphide nanostructures and core-shell nanostructures with Group II-VI shells.

  8. Effect of interface roughness on Auger recombination in semiconductor quantum wells

    NASA Astrophysics Data System (ADS)

    Tan, Chee-Keong; Sun, Wei; Wierer, Jonathan J.; Tansu, Nelson

    2017-03-01

    Auger recombination in a semiconductor is a three-carrier process, wherein the energy from the recombination of an electron and hole pair promotes a third carrier to a higher energy state. In semiconductor quantum wells with increased carrier densities, the Auger recombination becomes an appreciable fraction of the total recombination rate and degrades luminescence efficiency. Gaining insight into the variables that influence Auger recombination in semiconductor quantum wells could lead to further advances in optoelectronic and electronic devices. Here we demonstrate the important role that interface roughness has on Auger recombination within quantum wells. Our computational studies find that as the ratio of interface roughness to quantum well thickness is increased, Auger recombination is significantly enhanced. Specifically, when considering a realistic interface roughness for an InGaN quantum well, the enhancement in Auger recombination rate over a quantum well with perfect heterointerfaces can be approximately four orders of magnitude.

  9. In-situ integrated processing and characterization of thin films of high temperature superconductors, dielectrics and semiconductors by MOCVD

    NASA Technical Reports Server (NTRS)

    Singh, R.; Sinha, S.; Hsu, N. J.; Thakur, R. P. S.; Chou, P.; Kumar, A.; Narayan, J.

    1990-01-01

    In this strategy of depositing the basic building blocks of superconductors, semiconductors, and dielectric having common elements, researchers deposited superconducting films of Y-Ba-Cu-O, semiconductor films of Cu2O, and dielectric films of BaF2 and Y2O3 by metal oxide chemical vapor deposition (MOCVD). By switching source materials entering the chamber, and by using direct writting capability, complex device structures like three-terminal hybrid semiconductors/superconductors transistors can be fabricated. The Y-Ba-Cu-O superconducting thin films on BaF2/YSZ substrates show a T(sub c) of 80 K and are textured with most of the grains having their c-axis or a-axis perpendicular to the substrate. Electrical characteristics as well as structural characteristics of superconductors and related materials obtained by x-ray defraction, electron microscopy, and energy dispersive x-ray analysis are discussed.

  10. In-situ integrated processing and characterization of thin films of high temperature superconductors, dielectrics and semiconductors by MOCVD

    NASA Technical Reports Server (NTRS)

    Singh, R.; Sinha, S.; Hsu, N. J.; Thakur, R. P. S.; Chou, P.; Kumar, A.; Narayan, J.

    1991-01-01

    In this strategy of depositing the basic building blocks of superconductors, semiconductors, and dielectrics having common elements, researchers deposited superconducting films of Y-Ba-Cu-O, semiconductor films of Cu2O, and dielectric films of BaF2 and Y2O3 by metal oxide chemical vapor deposition (MOCVD). By switching source materials entering the chamber, and by using direct writing capability, complex device structures like three terminal hybrid semiconductor/superconductor transistors can be fabricated. The Y-Ba-Cu-O superconducting thin films on BaF2/YSZ substrates show a T(sub c) of 80 K and are textured with most of the grains having their c-axis or a-axis perpendicular to the substrate. Electrical characteristics as well as structural characteristics of superconductors and related materials obtained by x-ray deffraction, electron microscopy, and energy dispersive x-ray analysis are discussed.

  11. Two dimensional thermal and charge mapping of power thyristors

    NASA Technical Reports Server (NTRS)

    Hu, S. P.; Rabinovici, B. M.

    1975-01-01

    The two dimensional static and dynamic current density distributions within the junction of semiconductor power switching devices and in particular the thyristors were obtained. A method for mapping the thermal profile of the device junctions with fine resolution using an infrared beam and measuring the attenuation through the device as a function of temperature were developed. The results obtained are useful in the design and quality control of high power semiconductor switching devices.

  12. In Situ Chemical Modification of Schottky Barrier in Solution-Processed Zinc Tin Oxide Diode.

    PubMed

    Son, Youngbae; Li, Jiabo; Peterson, Rebecca L

    2016-09-14

    Here we present a novel in situ chemical modification process to form vertical Schottky diodes using palladium (Pd) rectifying bottom contacts, amorphous zinc tin oxide (Zn-Sn-O) semiconductor made via acetate-based solution process, and molybdenum top ohmic contacts. Using X-ray photoelectron spectroscopy depth profiling, we show that oxygen plasma treatment of Pd creates a PdOx interface layer, which is then reduced back to metallic Pd by in situ reactions during Zn-Sn-O film annealing. The plasma treatment ensures an oxygen-rich environment in the semiconductor near the Schottky barrier, reducing the level of oxygen-deficiency-related defects and improving the rectifying contact. Using this process, we achieve diodes with high forward current density exceeding 10(3)A cm(-2) at 1 V, rectification ratios of >10(2), and ideality factors of around 1.9. The measured diode current-voltage characteristics are compared to numerical simulations of thermionic field emission with sub-bandgap states in the semiconductor, which we attribute to spatial variations in metal stoichiometry of amorphous Zn-Sn-O. To the best of our knowledge, this is the first demonstration of vertical Schottky diodes using solution-processed amorphous metal oxide semiconductor. Furthermore, the in situ chemical modification method developed here can be adapted to tune interface properties in many other oxide devices.

  13. Multi-junction, monolithic solar cell using low-band-gap materials lattice matched to GaAs or Ge

    DOEpatents

    Olson, Jerry M.; Kurtz, Sarah R.; Friedman, Daniel J.

    2001-01-01

    A multi-junction, monolithic, photovoltaic solar cell device is provided for converting solar radiation to photocurrent and photovoltage with improved efficiency. The solar cell device comprises a plurality of semiconductor cells, i.e., active p/n junctions, connected in tandem and deposited on a substrate fabricated from GaAs or Ge. To increase efficiency, each semiconductor cell is fabricated from a crystalline material with a lattice constant substantially equivalent to the lattice constant of the substrate material. Additionally, the semiconductor cells are selected with appropriate band gaps to efficiently create photovoltage from a larger portion of the solar spectrum. In this regard, one semiconductor cell in each embodiment of the solar cell device has a band gap between that of Ge and GaAs. To achieve desired band gaps and lattice constants, the semiconductor cells may be fabricated from a number of materials including Ge, GaInP, GaAs, GaInAsP, GaInAsN, GaAsGe, BGaInAs, (GaAs)Ge, CuInSSe, CuAsSSe, and GaInAsNP. To further increase efficiency, the thickness of each semiconductor cell is controlled to match the photocurrent generated in each cell. To facilitate photocurrent flow, a plurality of tunnel junctions of low-resistivity material are included between each adjacent semiconductor cell. The conductivity or direction of photocurrent in the solar cell device may be selected by controlling the specific p-type or n-type characteristics for each active junction.

  14. Recent progress in tungsten oxides based memristors and their neuromorphological applications

    NASA Astrophysics Data System (ADS)

    Qu, Bo; Younis, Adnan; Chu, Dewei

    2016-09-01

    The advance in conventional silicon based semiconductor industry is now becoming indeterminacy as it still along the road of Moore's Law and concomitant problems associated with it are the emergence of a number of practical issues such as short channel effect. In terms of memory applications, it is generally believed that transistors based memory devices will approach to their scaling limits up to 2018. Therefore, one of the most prominent challenges today in semiconductor industry is the need of a new memory technology which is able to combine the best characterises of current devices. The resistive switching memories which are regarded as "memristors" thus gain great attentions thanks to their specific nonlinear electrical properties. More importantly, their behaviour resembles with the transmission characteristic of synapse in biology. Therefore, the research of synapses biomimetic devices based on memristor will certainly bring a great research prospect in studying synapse emulation as well as building artificial neural networks. Tungsten oxides (WO x ) exhibits many essential characteristics as a great candidate for memristive devices including: accredited endurance (over 105 cycles), stoichiometric flexibility, complimentary metal-oxide-semiconductor (CMOS) process compatibility and configurable properties including non-volatile rectification, memorization and learning functions. Herein, recent progress on Tungsten oxide based materials and its associating memory devices had been reviewed. The possible implementation of this material as a bio-inspired artificial synapse is also highlighted. The penultimate section summaries the current research progress for tungsten oxide based biological synapses and end up with several proposals that have been suggested for possible future developments.

  15. Active pixel sensor array with multiresolution readout

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Kemeny, Sabrina E. (Inventor); Pain, Bedabrata (Inventor)

    1999-01-01

    An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. The imaging device can also include an electronic shutter formed on the substrate adjacent the photogate, and/or a storage section to allow for simultaneous integration. In addition, the imaging device can include a multiresolution imaging circuit to provide images of varying resolution. The multiresolution circuit could also be employed in an array where the photosensitive portion of each pixel cell is a photodiode. This latter embodiment could further be modified to facilitate low light imaging.

  16. Enhancement of ZnO-based flexible nano generators via a sol-gel technique for sensing and energy harvesting applications

    NASA Astrophysics Data System (ADS)

    Rajagopalan, P.; Singh, Vipul; Palani, I. A.

    2018-03-01

    Zinc oxide (ZnO) is a remarkable inorganic semiconductor with exceptional piezoelectric properties compared to other semiconductors. However, in comparison to lead-based hazardous piezoelectric materials, its properties have undesired limitations. Here we report a 5˜6 fold enhancement in piezoelectric features via chemical doping of copper matched to intrinsic ZnO. A flexible piezoelectric nanogenerator (F-PENG) device was fabricated using an unpretentious solution process of spin coating, with other advantages such as robustness, low-weight, improved adhesion, and low cost. The device was used to demonstrate energy harvesting from a standard weight as low as 4 gm and can work as a self-powered mass sensor in a broad range of 4 to 100 gm. The device exhibited a novel energy harvesting technique from a wind source due to its inherent flexibility. At three different velocities (10˜30 m s-1) and five different angles of attack (0˜180 degrees), the device validated the ability to discern different velocities and directions of flow. The device will be useful for mapping the flow of air apart from harvesting the energy. The simulation was done to verify the underlining mechanism of aerodynamics involved.

  17. Enhancement of ZnO-based flexible nano generators via a sol-gel technique for sensing and energy harvesting applications.

    PubMed

    Rajagopalan, P; Singh, Vipul; Palani, I A

    2018-02-01

    Zinc oxide (ZnO) is a remarkable inorganic semiconductor with exceptional piezoelectric properties compared to other semiconductors. However, in comparison to lead-based hazardous piezoelectric materials, its properties have undesired limitations. Here we report a 5∼6 fold enhancement in piezoelectric features via chemical doping of copper matched to intrinsic ZnO. A flexible piezoelectric nanogenerator (F-PENG) device was fabricated using an unpretentious solution process of spin coating, with other advantages such as robustness, low-weight, improved adhesion, and low cost. The device was used to demonstrate energy harvesting from a standard weight as low as 4 gm and can work as a self-powered mass sensor in a broad range of 4 to 100 gm. The device exhibited a novel energy harvesting technique from a wind source due to its inherent flexibility. At three different velocities (10∼30 m s -1 ) and five different angles of attack (0∼180 degrees), the device validated the ability to discern different velocities and directions of flow. The device will be useful for mapping the flow of air apart from harvesting the energy. The simulation was done to verify the underlining mechanism of aerodynamics involved.

  18. Optical devices integrated with semiconductor optical amplifier

    NASA Astrophysics Data System (ADS)

    Oh, Kwang R.; Park, Moon S.; Jeong, Jong S.; Baek, Yongsoon; Oh, Dae-Kon

    2000-07-01

    Semiconductor optical amplifiers (SOA's) have been used as a key optical component for the high capacity communication systems. The monolithic integration is necessary for the stable operation of these devices and the wider applications. In this paper, the coupling technique between different waveguides and the integration of SSC's are discussed and the research results of optical devices integrated with SOA's are presented.

  19. Sputtered pin amorphous silicon semi-conductor device and method therefor

    DOEpatents

    Moustakas, Theodore D.; Friedman, Robert A.

    1983-11-22

    A high efficiency amorphous silicon PIN semi-conductor device is constructed by the sequential sputtering of N, I and P layers of amorphous silicon and at least one semi-transparent ohmic electrode. A method of construction produces a PIN device, exhibiting enhanced physical integrity and facilitates ease of construction in a singular vacuum system and vacuum pump down procedure.

  20. Modeling of Quantum Transport in Semiconductor Devices (The Physics and Operation of Ultra-Submicron Length Semiconductor Devices).

    DTIC Science & Technology

    1994-05-01

    Open Systems and Contacts ...................... 16 A Ballistic Transport .......................... 17 B Role of the Boundaries and Contacts...15 Other Devices ................................ 90 V Modeling with the Green’s Functions 91 16 Homogeneous, Low-Field Systems .................. 93 A...The Retarded Function ..................... 95 B The "Less-Than" Function ................... 99 17 Homogeneous, High-Field Systems

  1. Semiconductor crystal high resolution imager

    NASA Technical Reports Server (NTRS)

    Matteson, James (Inventor); Levin, Craig S. (Inventor)

    2011-01-01

    A radiation imaging device (10). The radiation image device (10) comprises a subject radiation station (12) producing photon emissions (14), and at least one semiconductor crystal detector (16) arranged in an edge-on orientation with respect to the emitted photons (14) to directly receive the emitted photons (14) and produce a signal. The semiconductor crystal detector (16) comprises at least one anode and at least one cathode that produces the signal in response to the emitted photons (14).

  2. Semiconductor/High-Tc-Superconductor Hybrid ICs

    NASA Technical Reports Server (NTRS)

    Burns, Michael J.

    1995-01-01

    Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

  3. Optical devices featuring nonpolar textured semiconductor layers

    DOEpatents

    Moustakas, Theodore D; Moldawer, Adam; Bhattacharyya, Anirban; Abell, Joshua

    2013-11-26

    A semiconductor emitter, or precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of nonpolar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the invention can be 70-80% or higher. The invention provides highly efficient light emitting diodes suitable for solid state lighting.

  4. Semiconductor devices for entangled photon pair generation: a review

    NASA Astrophysics Data System (ADS)

    Orieux, Adeline; Versteegh, Marijn A. M.; Jöns, Klaus D.; Ducci, Sara

    2017-07-01

    Entanglement is one of the most fascinating properties of quantum mechanical systems; when two particles are entangled the measurement of the properties of one of the two allows the properties of the other to be instantaneously known, whatever the distance separating them. In parallel with fundamental research on the foundations of quantum mechanics performed on complex experimental set-ups, we assist today with bourgeoning of quantum information technologies bound to exploit entanglement for a large variety of applications such as secure communications, metrology and computation. Among the different physical systems under investigation, those involving photonic components are likely to play a central role and in this context semiconductor materials exhibit a huge potential in terms of integration of several quantum components in miniature chips. In this article we review the recent progress in the development of semiconductor devices emitting entangled photons. We will present the physical processes allowing the generation of entanglement and the tools to characterize it; we will give an overview of major recent results of the last few years and highlight perspectives for future developments.

  5. In-situ thermal annealing of on-membrane silicon-on-insulator semiconductor-based devices after high gamma dose irradiation.

    PubMed

    Amor, S; André, N; Kilchytska, V; Tounsi, F; Mezghani, B; Gérard, P; Ali, Z; Udrea, F; Flandre, D; Francis, L A

    2017-05-05

    In this paper, we investigate the recovery of some semiconductor-based components, such as N/P-type field-effect transistors (FETs) and a complementary metal-oxide-semiconductor (CMOS) inverter, after being exposed to a high total dose of gamma ray radiation. The employed method consists mainly of a rapid, low power and in situ annealing mitigation technique by silicon-on-insulator micro-hotplates. Due to the ionizing effect of the gamma irradiation, the threshold voltages showed an average shift of -580 mV for N-channel transistors, and -360 mV for P-MOSFETs. A 4 min double-cycle annealing of components with a heater temperature up to 465 °C, corresponding to a maximum power of 38 mW, ensured partial recovery but was not sufficient for full recovery. The degradation was completely recovered after the use of a built-in high temperature annealing process, up to 975 °C for 8 min corresponding to a maximum power of 112 mW, which restored the normal operating characteristics for all devices after their irradiation.

  6. In-situ thermal annealing of on-membrane silicon-on-insulator semiconductor-based devices after high gamma dose irradiation

    NASA Astrophysics Data System (ADS)

    Amor, S.; André, N.; Kilchytska, V.; Tounsi, F.; Mezghani, B.; Gérard, P.; Ali, Z.; Udrea, F.; Flandre, D.; Francis, L. A.

    2017-05-01

    In this paper, we investigate the recovery of some semiconductor-based components, such as N/P-type field-effect transistors (FETs) and a complementary metal-oxide-semiconductor (CMOS) inverter, after being exposed to a high total dose of gamma ray radiation. The employed method consists mainly of a rapid, low power and in situ annealing mitigation technique by silicon-on-insulator micro-hotplates. Due to the ionizing effect of the gamma irradiation, the threshold voltages showed an average shift of -580 mV for N-channel transistors, and -360 mV for P-MOSFETs. A 4 min double-cycle annealing of components with a heater temperature up to 465 °C, corresponding to a maximum power of 38 mW, ensured partial recovery but was not sufficient for full recovery. The degradation was completely recovered after the use of a built-in high temperature annealing process, up to 975 °C for 8 min corresponding to a maximum power of 112 mW, which restored the normal operating characteristics for all devices after their irradiation.

  7. Directional interlayer spin-valley transfer in two-dimensional heterostructures

    DOE PAGES

    Schaibley, John R.; Rivera, Pasqual; Yu, Hongyi; ...

    2016-12-14

    Van der Waals heterostructures formed by two different monolayer semiconductors have emerged as a promising platform for new optoelectronic and spin/valleytronic applications. In addition to its atomically thin nature, a two-dimensional semiconductor heterostructure is distinct from its three-dimensional counterparts due to the unique coupled spin-valley physics of its constituent monolayers. In this paper, we report the direct observation that an optically generated spin-valley polarization in one monolayer can be transferred between layers of a two-dimensional MoSe 2–WSe 2 heterostructure. Using non-degenerate optical circular dichroism spectroscopy, we show that charge transfer between two monolayers conserves spin-valley polarization and is only weaklymore » dependent on the twist angle between layers. Finally, our work points to a new spin-valley pumping scheme in nanoscale devices, provides a fundamental understanding of spin-valley transfer across the two-dimensional interface, and shows the potential use of two-dimensional semiconductors as a spin-valley generator in two-dimensional spin/valleytronic devices for storing and processing information.« less

  8. Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

    DOEpatents

    Rogers, John A; Meitl, Matthew; Sun, Yugang; Ko, Heung Cho; Carlson, Andrew; Choi, Won Mook; Stoykovich, Mark; Jiang, Hanqing; Huang, Yonggang; Nuzzo, Ralph G; Zhu, Zhengtao; Menard, Etienne; Khang, Dahl-Young

    2014-05-20

    In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

  9. Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

    DOEpatents

    Rogers, John A [Champaign, IL; Meitl, Matthew [Raleigh, NC; Sun, Yugang [Naperville, IL; Ko, Heung Cho [Urbana, IL; Carlson, Andrew [Urbana, IL; Choi, Won Mook [Champaign, IL; Stoykovich, Mark [Dover, NH; Jiang, Hanqing [Urbana, IL; Huang, Yonggang [Glencoe, IL; Nuzzo, Ralph G [Champaign, IL; Lee, Keon Jae [Tokyo, JP; Zhu, Zhengtao [Rapid City, SD; Menard, Etienne [Durham, NC; Khang, Dahl-Young [Seoul, KR; Kan, Seong Jun [Daejeon, KR; Ahn, Jong Hyun [Suwon, KR; Kim, Hoon-sik [Champaign, IL

    2012-07-10

    In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

  10. Fabrication of eco-friendly PNP transistor using RF magnetron sputtering

    NASA Astrophysics Data System (ADS)

    Kumar, B. Santhosh; Harinee, N.; Purvaja, K.; Shanker, N. Praveen; Manikandan, M.; Aparnadevi, N.; Mukilraj, T.; Venkateswaran, C.

    2018-05-01

    An effort has been made to fabricate a thin film transistor using eco-friendly oxide semiconductor materials. Oxide semiconductor materials are cost - effective, thermally and chemically stable with high electron/hole mobility. Copper (II) oxide is a p-type semiconductor and zinc oxide is an n-type semiconductor. A pnp thin film transistor was fabricated using RF magnetron sputtering. The films deposited have been subjected to structural characterization using AFM. I-V characterization of the fabricated device, Ag/CuO/ZnO/CuO/Ag, confirms transistor behaviour. The mechanism of electron/hole transport of the device is discussed below.

  11. Near-Unity Absorption in van der Waals Semiconductors for Ultrathin Optoelectronics.

    PubMed

    Jariwala, Deep; Davoyan, Artur R; Tagliabue, Giulia; Sherrott, Michelle C; Wong, Joeson; Atwater, Harry A

    2016-09-14

    We demonstrate near-unity, broadband absorbing optoelectronic devices using sub-15 nm thick transition metal dichalcogenides (TMDCs) of molybdenum and tungsten as van der Waals semiconductor active layers. Specifically, we report that near-unity light absorption is possible in extremely thin (<15 nm) van der Waals semiconductor structures by coupling to strongly damped optical modes of semiconductor/metal heterostructures. We further fabricate Schottky junction devices using these highly absorbing heterostructures and characterize their optoelectronic performance. Our work addresses one of the key criteria to enable TMDCs as potential candidates to achieve high optoelectronic efficiency.

  12. Noise And Charge Transport In Carbon Nanotube Devices

    NASA Astrophysics Data System (ADS)

    Reza, Shahed; Huynh, Quyen T.; Bosman, Gijs; Sippel, Jennifer; Rinzler, Andrew G.

    2005-11-01

    The charge transport and noise properties of three terminal, gated devices containing multiple, single wall, metallic and semiconductor carbon nanotubes have been measured as a function of gate and drain bias at 300K. Using pulsed bias the metallic tubes could be burned sequentially enabling the separation of measured conductance and low frequency excess noise into metallic and semiconductor contributions. The relative low frequency excess noise of the metallic tubes was about a factor 100 lower than that of the semiconductor tubes, whereas the conductance of the metallic tubes was significantly higher (10 to 50 times) than that of the semiconductor tubes.

  13. Gate bias stress in pentacene field-effect-transistors: Charge trapping in the dielectric or semiconductor

    NASA Astrophysics Data System (ADS)

    Häusermann, R.; Batlogg, B.

    2011-08-01

    Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO2 and Cytop). We show that it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone or in the dielectric.

  14. Monolayer borophene electrode for effective elimination of both the Schottky barrier and strong electric field effect

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Liu, L. Z., E-mail: lzliu@nju.edu.cn, E-mail: hkxlwu@nju.edu.cn; Xiong, S. J.; Wu, X. L., E-mail: lzliu@nju.edu.cn, E-mail: hkxlwu@nju.edu.cn

    2016-08-08

    The formation of Schottky barriers between 2D semiconductors and traditional metallic electrodes has greatly limited the application of 2D semiconductors in nanoelectronic and optoelectronic devices. In this study, metallic borophene was used as a substitute for the traditional noble metal electrode to contact with the 2D semiconductor. Theoretical calculations demonstrated that no Schottky barrier exists in the borophene/2D semiconductor heterostructure. The contact remains ohmic even with a strong electric field applied. This finding provides a way to construct 2D electronic devices and sensors with greatly enhanced performance.

  15. Functional carbon nitride materials — design strategies for electrochemical devices

    NASA Astrophysics Data System (ADS)

    Kessler, Fabian K.; Zheng, Yun; Schwarz, Dana; Merschjann, Christoph; Schnick, Wolfgang; Wang, Xinchen; Bojdys, Michael J.

    2017-06-01

    In the past decade, research in the field of artificial photosynthesis has shifted from simple, inorganic semiconductors to more abundant, polymeric materials. For example, polymeric carbon nitrides have emerged as promising materials for metal-free semiconductors and metal-free photocatalysts. Polymeric carbon nitride (melon) and related carbon nitride materials are desirable alternatives to industrially used catalysts because they are easily synthesized from abundant and inexpensive starting materials. Furthermore, these materials are chemically benign because they do not contain heavy metal ions, thereby facilitating handling and disposal. In this Review, we discuss the building blocks of carbon nitride materials and examine how strategies in synthesis, templating and post-processing translate from the molecular level to macroscopic properties, such as optical and electronic bandgap. Applications of carbon nitride materials in bulk heterojunctions, laser-patterned memory devices and energy storage devices indicate that photocatalytic overall water splitting on an industrial scale may be realized in the near future and reveal a new avenue of 'post-silicon electronics'.

  16. High-temperature electronics

    NASA Technical Reports Server (NTRS)

    Seng, Gary T.

    1987-01-01

    In recent years, there was a growing need for electronics capable of sustained high-temperature operation for aerospace propulsion system instrumentation, control and condition monitoring, and integrated sensors. The desired operating temperature in some applications exceeds 600 C, which is well beyond the capability of currently available semiconductor devices. Silicon carbide displays a number of properties which make it very attractive as a semiconductor material, one of which is the ability to retain its electronic integrity at temperatures well above 600 C. An IR-100 award was presented to NASA Lewis in 1983 for developing a chemical vapor deposition process to grow single crystals of this material on standard silicon wafers. Silicon carbide devices were demonstrated above 400 C, but much work remains in the areas of crystal growth, characterization, and device fabrication before the full potential of silicon carbide can be realized. The presentation will conclude with current and future high-temperature electronics program plans. Although the development of silicon carbide falls into the category of high-risk research, the future looks promising, and the potential payoffs are tremendous.

  17. Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

    PubMed

    Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

    2017-06-28

    β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

  18. A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

    PubMed Central

    Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

    2012-01-01

    This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

  19. Low-Temperature UV-Assisted Fabrication of Metal Oxide Thin Film Transistor

    NASA Astrophysics Data System (ADS)

    Zhu, Shuanglin

    Solution processed metal oxide semiconductors have attracted intensive attention in the last several decades and have emerged as a promising candidate for the application of thin film transistor (TFT) due to their nature of transparency, flexibility, high mobility, simple processing technique and potential low manufacturing cost. However, metal oxide thin film fabricated by solution process usually requires a high temperature (over 300 °C), which is above the glass transition temperature of some conventional polymer substrates. In order to fabricate the flexible electronic device on polymer substrates, it is necessary to find a facile approach to lower the fabrication temperature and minimize defects in metal oxide thin film. In this thesis, the electrical properties dependency on temperature is discussed and an UV-assisted annealing method incorporating Deep ultraviolet (DUV)-decomposable additives is demonstrated, which can effectively improve electrical properties solution processed metal oxide semiconductors processed at temperature as low as 220 °C. By studying a widely used indium oxide (In2O3) TFT as a model system, it is worth noted that compared with the sample without UV treatment, the linear mobility and saturation mobility of UV-annealing sample are improved by 56% and 40% respectively. Meanwhile, the subthreshold swing is decreased by 32%, indicating UV-treated device could turn on and off more efficiently. In addition to pure In2O3 film, the similar phenomena have also been observed in indium oxide based Indium-Gallium-Zinc Oxide (IGZO) system. These finding presented in this thesis suggest that the UV assisted annealing process open a new route to fabricate high performance metal oxide semiconductors under low temperatures.

  20. George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

    NASA Astrophysics Data System (ADS)

    Doering, Robert

    In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

  1. Perspectives on integrated modeling of transport processes in semiconductor crystal growth

    NASA Technical Reports Server (NTRS)

    Brown, Robert A.

    1992-01-01

    The wide range of length and time scales involved in industrial scale solidification processes is demonstrated here by considering the Czochralski process for the growth of large diameter silicon crystals that become the substrate material for modern microelectronic devices. The scales range in time from microseconds to thousands of seconds and in space from microns to meters. The physics and chemistry needed to model processes on these different length scales are reviewed.

  2. Outline and comparison of the possible effects present in a metal-thin-film-insulator-semiconductor solar cell

    NASA Technical Reports Server (NTRS)

    Fonash, S. J.

    1976-01-01

    The advantages possible with the insertion of a thin-film insulating or semi-insulating layer between a metal and a semiconductor to form the MIS photovoltaic device have been presented previously in the literature. This MIS configuration may be considered as a specific example of a more general class of photovoltaic devices: electrode-thin-film-insulator-semiconductor devices. Since the advantages of the configuration were pointed out, there has been considerable experimental interest in these photovoltaic devices. Because the previous analysis showed that the introduction of the insulator layer could produce several different but advantageous effects, this paper presents a further outline giving a comparison of these effects together with their ramifications.

  3. New method of contour-based mask-shape compiler

    NASA Astrophysics Data System (ADS)

    Matsuoka, Ryoichi; Sugiyama, Akiyuki; Onizawa, Akira; Sato, Hidetoshi; Toyoda, Yasutaka

    2007-10-01

    We have developed a new method of accurately profiling a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, it is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method for a DFM solution in which two dimensional data are extracted for an error free practical simulation by precise reproduction of a real mask shape in addition to the mask data simulation. The flow centering around the design data is fully automated and provides an environment where optimization and verification for fully automated model calibration with much less error is available. It also allows complete consolidation of input and output functions with an EDA system by constructing a design data oriented system structure. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

  4. Multifunctional Self-Assembled Monolayers for Organic Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Cernetic, Nathan

    Organic field effect transistors (OFETs) have the potential to reach commercialization for a wide variety of applications such as active matrix display circuitry, chemical and biological sensing, radio-frequency identification devices and flexible electronics. In order to be commercially competitive with already at-market amorphous silicon devices, OFETs need to approach similar performance levels. Significant progress has been made in developing high performance organic semiconductors and dielectric materials. Additionally, a common route to improve the performance metric of OFETs is via interface modification at the critical dielectric/semiconductor and electrode/semiconductor interface which often play a significant role in charge transport properties. These metal oxide interfaces are typically modified with rationally designed multifunctional self-assembled monolayers. As means toward improving the performance metrics of OFETs, rationally designed multifunctional self-assembled monolayers are used to explore the relationship between surface energy, SAM order, and SAM dipole on OFET performance. The studies presented within are (1) development of a multifunctional SAM capable of simultaneously modifying dielectric and metal surface while maintaining compatibility with solution processed techniques (2) exploration of the relationship between SAM dipole and anchor group on graphene transistors, and (3) development of self-assembled monolayer field-effect transistor in which the traditional thick organic semiconductor is replaced by a rationally designed self-assembled monolayer semiconductor. The findings presented within represent advancement in the understanding of the influence of self-assembled monolayers on OFETs as well as progress towards rationally designed monolayer transistors.

  5. Nanoimprint lithography for nanodevice fabrication

    NASA Astrophysics Data System (ADS)

    Barcelo, Steven; Li, Zhiyong

    2016-09-01

    Nanoimprint lithography (NIL) is a compelling technique for low cost nanoscale device fabrication. The precise and repeatable replication of nanoscale patterns from a single high resolution patterning step makes the NIL technique much more versatile than other expensive techniques such as e-beam or even helium ion beam lithography. Furthermore, the use of mechanical deformation during the NIL process enables grayscale lithography with only a single patterning step, not achievable with any other conventional lithography techniques. These strengths enable the fabrication of unique nanoscale devices by NIL for a variety of applications including optics, plasmonics and even biotechnology. Recent advances in throughput and yield in NIL processes demonstrate the potential of being adopted for mainstream semiconductor device fabrication as well.

  6. Process for forming pure silver ohmic contacts to N- and P-type gallium arsenide materials

    DOEpatents

    Hogan, S.J.

    1983-03-13

    Disclosed is an improved process for manufacturing gallium arsenide semiconductor devices having as its components a n-type gallium arsenide substrate layer and a p-type gallium arsenide diffused layer. The improved process comprises forming a pure silver ohmic contact to both the diffuse layer and the substrate layer wherein the n-type layer comprises a substantially low doping carrier concentration.

  7. A comprehensive study of charge trapping in organic field-effect devices with promising semiconductors and different contact metals by displacement current measurements

    NASA Astrophysics Data System (ADS)

    Bisoyi, Sibani; Rödel, Reinhold; Zschieschang, Ute; Kang, Myeong Jin; Takimiya, Kazuo; Klauk, Hagen; Tiwari, Shree Prakash

    2016-02-01

    A systematic and comprehensive study on the charge-carrier injection and trapping behavior was performed using displacement current measurements in long-channel capacitors based on four promising small-molecule organic semiconductors (pentacene, DNTT, C10-DNTT and DPh-DNTT). In thin-film transistors, these semiconductors showed charge-carrier mobilities ranging from 1.0 to 7.8 cm2 V-1 s-1. The number of charges injected into and extracted from the semiconductor and the density of charges trapped in the device during each measurement were calculated from the displacement current characteristics and it was found that the density of trapped charges is very similar in all devices and of the order 1012 cm-2, despite the fact that the four semiconductors show significantly different charge-carrier mobilities. The choice of the contact metal (Au, Ag, Cu, Pd) was also found to have no significant effect on the trapping behavior.

  8. An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

    PubMed

    Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

    2017-10-11

    The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

  9. Researchers Validate UV Light's Use in Improving Semiconductors | News |

    Science.gov Websites

    device. The ability to use different classes of semiconductors could create additional possibilities for integrating a variety of different semiconductors in the future," Park said. The researchers explored

  10. Research and Development Strategies in the Semiconductor Industry

    NASA Astrophysics Data System (ADS)

    Bowling, Allen

    2003-03-01

    In the 21st Century semiconductor industry, there is a critical balance between internally funded semiconductor research and development (R) and externally funded R. External R may include jointly-funded research collaborations/partnerships with other device manufacturers, jointly-funded consortia-based R, and individually-funded research programs at universities and other contract research locations. Each of these approaches has merits and each has costs. There is a critical balance between keeping the internal research and development pipeline filled and keeping it from being overspent. To meet both competitive schedule and cost goals, a semiconductor device manufacturer must decide on a model for selection of internal versus external R. Today, one of the most critical decisions is whether or not to do semiconductor research and development on 300 mm silicon wafers. Equipment suppliers are doing first development on 300 mm equipment. So, for the device manufacturer, there is a balance between the cost of doing development on 300 mm wafers and the development time schedule driven by equipment availability. In the face of these cost and schedule elements, device manufacturers are looking to consortia such as SEMATECH, SRC, and SRC MARCO for early development and screening of new materials and device structure approaches. This also causes much more close development collaboration between device manufacturer and equipment supplier. Many device manufacturers are also making use of direct contract research with universities and other contract-research organizations, such as IMEC, LETI, and other government-funded research organizations around the world. To get the most out of these external research interactions, the company must develop a strategy for management and technology integration of external R.

  11. 78 FR 40427 - Foreign-Trade Zone (FTZ) 183-Austin, Texas; Notification of Proposed Production Activity; Samsung...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-07-05

    ..., Texas; Notification of Proposed Production Activity; Samsung Austin Semiconductor, LLC (Semiconductors); Austin, Texas Samsung Austin Semiconductor, LLC (Samsung), operator of Subzone 183B, submitted a... June 26, 2013. Samsung currently has authority to produce semiconductor memory devices for export...

  12. Semiconductor Laser Low Frequency Noise Characterization

    NASA Technical Reports Server (NTRS)

    Maleki, Lute; Logan, Ronald T.

    1996-01-01

    This work summarizes the efforts in identifying the fundamental noise limit in semiconductor optical sources (lasers) to determine the source of 1/F noise and it's associated behavior. In addition, the study also addresses the effects of this 1/F noise on RF phased arrays. The study showed that the 1/F noise in semiconductor lasers has an ultimate physical limit based upon similar factors to fundamental noise generated in other semiconductor and solid state devices. The study also showed that both additive and multiplicative noise can be a significant detriment to the performance of RF phased arrays especially in regard to very low sidelobe performance and ultimate beam steering accuracy. The final result is that a noise power related term must be included in a complete analysis of the noise spectrum of any semiconductor device including semiconductor lasers.

  13. Building devices from colloidal quantum dots.

    PubMed

    Kagan, Cherie R; Lifshitz, Efrat; Sargent, Edward H; Talapin, Dmitri V

    2016-08-26

    The continued growth of mobile and interactive computing requires devices manufactured with low-cost processes, compatible with large-area and flexible form factors, and with additional functionality. We review recent advances in the design of electronic and optoelectronic devices that use colloidal semiconductor quantum dots (QDs). The properties of materials assembled of QDs may be tailored not only by the atomic composition but also by the size, shape, and surface functionalization of the individual QDs and by the communication among these QDs. The chemical and physical properties of QD surfaces and the interfaces in QD devices are of particular importance, and these enable the solution-based fabrication of low-cost, large-area, flexible, and functional devices. We discuss challenges that must be addressed in the move to solution-processed functional optoelectronic nanomaterials. Copyright © 2016, American Association for the Advancement of Science.

  14. Method for altering the luminescence of a semiconductor

    DOEpatents

    Barbour, J. Charles; Dimos, Duane B.

    1999-01-01

    A method is described for altering the luminescence of a light emitting semiconductor (LES) device. In particular, a method is described whereby a silicon LES device can be selectively irradiated with a radiation source effective for altering the intensity of luminescence of the irradiated region.

  15. Power semiconductor device with negative thermal feedback

    NASA Technical Reports Server (NTRS)

    Borky, J. M.; Thornton, R. D.

    1970-01-01

    Composite power semiconductor avoids second breakdown and provides stable operation. It consists of an array of parallel-connected integrated circuits fabricated in a single chip. The output power device and associated low-level amplifier are closely coupled thermally, so that they have a predetermined temperature relationship.

  16. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

    The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

  17. Bi-level multilayered microelectronic device package with an integral window

    DOEpatents

    Peterson, Kenneth A.; Watson, Robert D.

    2002-01-01

    A bi-level, multilayered package with an integral window for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that the light-sensitive side is optically accessible through the window. A second chip can be bonded to the backside of the first chip, with the second chip being wirebonded to the second level of the bi-level package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed.

  18. Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-12-09

    Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.

  19. GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

    NASA Astrophysics Data System (ADS)

    Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

    2015-04-01

    GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

  20. Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Lu, Anh Khoa Augustin; IMEC, 75 Kapeldreef, B-3001 Leuven; Pourtois, Geoffrey

    2016-01-25

    The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10 nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, andmore » sets the limit of the scaling in future transistor designs.« less

  1. Semiconductor millimeter wavelength electronics

    NASA Astrophysics Data System (ADS)

    Rosenbaum, F. J.

    1985-12-01

    This final report summarizes the results of research carried out on topics in millimeter wavelength semiconductor electronics under an ONR Selected Research Opportunity program. Study areas included III-V compound semiconductor growth and characterization, microwave and millimeter wave device modeling, fabrication and testing, and the development of new device concepts. A new millimeter wave mixer and detector, the Gap diode was invented. Topics reported on include ballistic transport, Zener oscillations, impurities in GaAs, electron velocity-electric field calculation and measurements, etc., calculations.

  2. Implications of Analytical Investigations about the Semiconductor Equations on Device Modeling Programs.

    DTIC Science & Technology

    1983-04-01

    34.. .. . ...- "- -,-. SIGNIFICANCE AND EXPLANATION Many different codes for the simulation of semiconductor devices such as transitors , diodes, thyristors are already circulated...partially take into account the consequences introduced by degenerate semiconductors (e.g. invalidity of Boltzmann’s statistics , bandgap narrowing). These...ft - ni p nep /Ut(2.10) Sni *e p nie 2.11) .7. (2.10) can be physically interpreted as the application of Boltzmann statistics . However (2.10) a.,zo

  3. Investigation of semiconductor clad optical waveguides

    NASA Technical Reports Server (NTRS)

    Batchman, T. E.; Carson, R. F.

    1985-01-01

    A variety of techniques have been proposed for fabricating integrated optical devices using semiconductors, lithium niobate, and glasses as waveguides and substrates. The use of glass waveguides and their interaction with thin semiconductor cladding layers was studied. Though the interactions of these multilayer waveguide structures have been analyzed here using glass, they may be applicable to other types of materials as well. The primary reason for using glass is that it provides a simple, inexpensive way to construct waveguides and devices.

  4. Rocksalt nitride metal/semiconductor superlattices: A new class of artificially structured materials

    NASA Astrophysics Data System (ADS)

    Saha, Bivas; Shakouri, Ali; Sands, Timothy D.

    2018-06-01

    Artificially structured materials in the form of superlattice heterostructures enable the search for exotic new physics and novel device functionalities, and serve as tools to push the fundamentals of scientific and engineering knowledge. Semiconductor heterostructures are the most celebrated and widely studied artificially structured materials, having led to the development of quantum well lasers, quantum cascade lasers, measurements of the fractional quantum Hall effect, and numerous other scientific concepts and practical device technologies. However, combining metals with semiconductors at the atomic scale to develop metal/semiconductor superlattices and heterostructures has remained a profoundly difficult scientific and engineering challenge. Though the potential applications of metal/semiconductor heterostructures could range from energy conversion to photonic computing to high-temperature electronics, materials challenges primarily had severely limited progress in this pursuit until very recently. In this article, we detail the progress that has taken place over the last decade to overcome the materials engineering challenges to grow high quality epitaxial, nominally single crystalline metal/semiconductor superlattices based on transition metal nitrides (TMN). The epitaxial rocksalt TiN/(Al,Sc)N metamaterials are the first pseudomorphic metal/semiconductor superlattices to the best of our knowledge, and their physical properties promise a new era in superlattice physics and device engineering.

  5. Methods for forming particles from single source precursors

    DOEpatents

    Fox, Robert V [Idaho Falls, ID; Rodriguez, Rene G [Pocatello, ID; Pak, Joshua [Pocatello, ID

    2011-08-23

    Single source precursors are subjected to carbon dioxide to form particles of material. The carbon dioxide may be in a supercritical state. Single source precursors also may be subjected to supercritical fluids other than supercritical carbon dioxide to form particles of material. The methods may be used to form nanoparticles. In some embodiments, the methods are used to form chalcopyrite materials. Devices such as, for example, semiconductor devices may be fabricated that include such particles. Methods of forming semiconductor devices include subjecting single source precursors to carbon dioxide to form particles of semiconductor material, and establishing electrical contact between the particles and an electrode.

  6. Integrated semiconductor optical sensors for chronic, minimally-invasive imaging of brain function.

    PubMed

    Lee, Thomas T; Levi, Ofer; Cang, Jianhua; Kaneko, Megumi; Stryker, Michael P; Smith, Stephen J; Shenoy, Krishna V; Harris, James S

    2006-01-01

    Intrinsic optical signal (IOS) imaging is a widely accepted technique for imaging brain activity. We propose an integrated device consisting of interleaved arrays of gallium arsenide (GaAs) based semiconductor light sources and detectors operating at telecommunications wavelengths in the near-infrared. Such a device will allow for long-term, minimally invasive monitoring of neural activity in freely behaving subjects, and will enable the use of structured illumination patterns to improve system performance. In this work we describe the proposed system and show that near-infrared IOS imaging at wavelengths compatible with semiconductor devices can produce physiologically significant images in mice, even through skull.

  7. Pump-probe spectroscopy in organic semiconductors: monitoring fundamental processes of relevance in optoelectronics.

    PubMed

    Cabanillas-Gonzalez, Juan; Grancini, Giulia; Lanzani, Guglielmo

    2011-12-08

    In this review we highlight the contribution of pump-probe spectroscopy to understand elementary processes taking place in organic based optoelectronic devices. The techniques described in this article span from conventional pump-probe spectroscopy to electromodulated pump-probe and the state-of-the-art confocal pump-probe microscopy. The article is structured according to three fundamental processes (optical gain, charge photogeneration and charge transport) and the contribution of these techniques on them. The combination of these tools opens up new perspectives for assessing the role of short-lived excited states on processes lying underneath organic device operation. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  8. In-Line Detection and Measurement of Molecular Contamination in Semiconductor Process Solutions

    NASA Astrophysics Data System (ADS)

    Wang, Jason; West, Michael; Han, Ye; McDonald, Robert C.; Yang, Wenjing; Ormond, Bob; Saini, Harmesh

    2005-09-01

    This paper discusses a fully automated metrology tool for detection and quantitative measurement of contamination, including cationic, anionic, metallic, organic, and molecular species present in semiconductor process solutions. The instrument is based on an electrospray ionization time-of-flight mass spectrometer (ESI-TOF/MS) platform. The tool can be used in diagnostic or analytical modes to understand process problems in addition to enabling routine metrology functions. Metrology functions include in-line contamination measurement with near real-time trend analysis. This paper discusses representative organic and molecular contamination measurement results in production process problem solving efforts. The examples include the analysis and identification of organic compounds in SC-1 pre-gate clean solution; urea, NMP (N-Methyl-2-pyrrolidone) and phosphoric acid contamination in UPW; and plasticizer and an organic sulfur-containing compound found in isopropyl alcohol (IPA). It is expected that these unique analytical and metrology capabilities will improve the understanding of the effect of organic and molecular contamination on device performance and yield. This will permit the development of quantitative correlations between contamination levels and process degradation. It is also expected that the ability to perform routine process chemistry metrology will lead to corresponding improvements in manufacturing process control and yield, the ability to avoid excursions and will improve the overall cost effectiveness of the semiconductor manufacturing process.

  9. Method for altering the luminescence of a semiconductor

    DOEpatents

    Barbour, J.C.; Dimos, D.B.

    1999-01-12

    A method is described for altering the luminescence of a light emitting semiconductor (LES) device. In particular, a method is described whereby a silicon LES device can be selectively irradiated with a radiation source effective for altering the intensity of luminescence of the irradiated region. 4 figs.

  10. General Electronics Technician: Semiconductor Devices and Circuits.

    ERIC Educational Resources Information Center

    Hilley, Robert

    These instructional materials include a teacher's guide designed to assist instructors in organizing and presenting an introductory course in general electronics focusing on semiconductor devices and circuits and a student guide. The materials are based on the curriculum-alignment concept of first stating the objectives, developing instructional…

  11. 40 CFR Table 1 to Subpart Bbbbb of... - Requirements for Performance Tests

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... CATEGORIES (CONTINUED) National Emission Standards for Hazardous Air Pollutants for Semiconductor... necessary. 2. Process vent stream a. Measure organic and inorganic HAP concentration (two method option) i... simultaneous sampling at inlet and outlet of control device and analyze for same organic and inorganic HAP at...

  12. 40 CFR Table 1 to Subpart Bbbbb of... - Requirements for Performance Tests

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... CATEGORIES (CONTINUED) National Emission Standards for Hazardous Air Pollutants for Semiconductor... necessary. 2. Process vent stream a. Measure organic and inorganic HAP concentration (two method option) i... simultaneous sampling at inlet and outlet of control device and analyze for same organic and inorganic HAP at...

  13. Current challenges in organic photovoltaic solar energy conversion.

    PubMed

    Schlenker, Cody W; Thompson, Mark E

    2012-01-01

    Over the last 10 years, significant interest in utilizing conjugated organic molecules for solid-state solar to electric conversion has produced rapid improvement in device efficiencies. Organic photovoltaic (OPV) devices are attractive for their compatibility with low-cost processing techniques and thin-film applicability to flexible and conformal applications. However, many of the processes that lead to power losses in these systems still remain poorly understood, posing a significant challenge for the future efficiency improvements required to make these devices an attractive solar technology. While semiconductor band models have been employed to describe OPV operation, a more appropriate molecular picture of the pertinent processes is beginning to emerge. This chapter presents mechanisms of OPV device operation, based on the bound molecular nature of the involved transient species. With the intention to underscore the importance of considering both thermodynamic and kinetic factors, recent progress in elucidating molecular characteristics that dictate photovoltage losses in heterojunction organic photovoltaics is also discussed.

  14. Development of a Photoelectrochemical Etch Process to Enable Heterogeneous Substrate Integration of Epitaxial III-Nitride Semiconductors

    DTIC Science & Technology

    2017-12-01

    Chung, Stephen Kelley, Kimberley Olver, Blair C. Connelly, Anand V. Sampath, and Meredith L. Reed Sensors and Electron Devices Directorate, ARL...nitride [GaN], indium nitride, and corresponding ternary alloys) provide a basis for a variety of electronic and photonic devices across several...and driven by an electron beam irradiation, which leads to high carrier densities. This necessitates the transfer/removal of the GaN substrate (or GaN

  15. Active layers of high-performance lead zirconate titanate at temperatures compatible with silicon nano- and microelecronic devices

    PubMed Central

    Bretos, Iñigo; Jiménez, Ricardo; Tomczyk, Monika; Rodríguez-Castellón, Enrique; Vilarinho, Paula M.; Calzada, M. Lourdes

    2016-01-01

    Applications of ferroelectric materials in modern microelectronics will be greatly encouraged if the thermal incompatibility between inorganic ferroelectrics and semiconductor devices is overcome. Here, solution-processable layers of the most commercial ferroelectric compound ─ morphotrophic phase boundary lead zirconate titanate, namely Pb(Zr0.52Ti0.48)O3 (PZT) ─ are grown on silicon substrates at temperatures well below the standard CMOS process of semiconductor technology. The method, potentially transferable to a broader range of Zr:Ti ratios, is based on the addition of crystalline nanoseeds to photosensitive solutions of PZT resulting in perovskite crystallization from only 350 °C after the enhanced decomposition of metal precursors in the films by UV irradiation. A remanent polarization of 10.0 μC cm−2 is obtained for these films that is in the order of the switching charge densities demanded for FeRAM devices. Also, a dielectric constant of ~90 is measured at zero voltage which exceeds that of current single-oxide candidates for capacitance applications. The multifunctionality of the films is additionally demonstrated by their pyroelectric and piezoelectric performance. The potential integration of PZT layers at such low fabrication temperatures may redefine the concept design of classical microelectronic devices, besides allowing inorganic ferroelectrics to enter the scene of the emerging large-area, flexible electronics. PMID:26837240

  16. Active layers of high-performance lead zirconate titanate at temperatures compatible with silicon nano- and microeletronic [corrected] devices.

    PubMed

    Bretos, Iñigo; Jiménez, Ricardo; Tomczyk, Monika; Rodríguez-Castellón, Enrique; Vilarinho, Paula M; Calzada, M Lourdes

    2016-02-03

    Applications of ferroelectric materials in modern microelectronics will be greatly encouraged if the thermal incompatibility between inorganic ferroelectrics and semiconductor devices is overcome. Here, solution-processable layers of the most commercial ferroelectric compound--morphotrophic phase boundary lead zirconate titanate, namely Pb(Zr0.52Ti0.48)O3 (PZT)--are grown on silicon substrates at temperatures well below the standard CMOS process of semiconductor technology. The method, potentially transferable to a broader range of Zr:Ti ratios, is based on the addition of crystalline nanoseeds to photosensitive solutions of PZT resulting in perovskite crystallization from only 350 °C after the enhanced decomposition of metal precursors in the films by UV irradiation. A remanent polarization of 10.0 μC cm(-2) is obtained for these films that is in the order of the switching charge densities demanded for FeRAM devices. Also, a dielectric constant of ~90 is measured at zero voltage which exceeds that of current single-oxide candidates for capacitance applications. The multifunctionality of the films is additionally demonstrated by their pyroelectric and piezoelectric performance. The potential integration of PZT layers at such low fabrication temperatures may redefine the concept design of classical microelectronic devices, besides allowing inorganic ferroelectrics to enter the scene of the emerging large-area, flexible electronics.

  17. A study of selenium nanoparticles as charge storage element for flexible semi-transparent memory devices

    NASA Astrophysics Data System (ADS)

    Alotaibi, Sattam; Nama Manjunatha, Krishna; Paul, Shashi

    2017-12-01

    Flexible Semi-Transparent electronic memory would be useful in coming years for integrated flexible transparent electronic devices. However, attaining such flexibility and semi-transparency leads to the boundaries in material composition. Thus, impeding processing speed and device performance. In this work, we present the use of inorganic stable selenium nanoparticles (Se-NPs) as a storage element and hydrogenated amorphous carbon (a-C:H) as an insulating layer in two terminal non-volatile physically flexible and semi-transparent capacitive memory devices (2T-NMDs). Furthermore, a-C:H films can be deposited at very low temperature (<40° C) on a variety of substrates (including many kinds of plastic substrates) by an industrial technique called Plasma Enhanced Chemical Vapour Deposition (PECVD) which is available in many existing fabrication labs. Self-assembled Se-NPs has several unique features including deposition at room temperature by simple vacuum thermal evaporation process without the need for further optimisation. This facilitates the fabrication of memory on a flexible substrate. Moreover, the memory behaviour of the Se-NPs was found to be more distinct than those of the semiconductor and metal nanostructures due to higher work function compared to the commonly used semiconductor and metal species. The memory behaviour was observed from the hysteresis of current-voltage (I-V) measurements while the two distinguishable electrical conductivity states (;0; and "1") were studied by current-time (I-t) measurements.

  18. Precise, Self-Limited Epitaxy of Ultrathin Organic Semiconductors and Heterojunctions Tailored by van der Waals Interactions.

    PubMed

    Wu, Bing; Zhao, Yinghe; Nan, Haiyan; Yang, Ziyi; Zhang, Yuhan; Zhao, Huijuan; He, Daowei; Jiang, Zonglin; Liu, Xiaolong; Li, Yun; Shi, Yi; Ni, Zhenhua; Wang, Jinlan; Xu, Jian-Bin; Wang, Xinran

    2016-06-08

    Precise assembly of semiconductor heterojunctions is the key to realize many optoelectronic devices. By exploiting the strong and tunable van der Waals (vdW) forces between graphene and organic small molecules, we demonstrate layer-by-layer epitaxy of ultrathin organic semiconductors and heterostructures with unprecedented precision with well-defined number of layers and self-limited characteristics. We further demonstrate organic p-n heterojunctions with molecularly flat interface, which exhibit excellent rectifying behavior and photovoltaic responses. The self-limited organic molecular beam epitaxy (SLOMBE) is generically applicable for many layered small-molecule semiconductors and may lead to advanced organic optoelectronic devices beyond bulk heterojunctions.

  19. Microsensors based on GaN semiconductors covalently functionalized with luminescent Ru(II) complexes.

    PubMed

    López-Gejo, Juan; Arranz, Antonio; Navarro, Alvaro; Palacio, Carlos; Muñoz, Elías; Orellana, Guillermo

    2010-02-17

    Covalent tethering of a Ru(II) dye to gallium nitride surfaces has been accomplished as a key step in the development of innovative sensing devices in which the indicator support (semiconductor) plays the role of both support and excitation source. Luminescence emission decays and time-resolved emission spectra confirm the presence of the dye on the semiconductor surfaces, while X-ray photoelectron spectroscopy proves its covalent bonding. The O(2) sensitivity of the new device is comparable to those of other ruthenium-based sensor systems. This achievement paves the way to a new generation of integrable ultracompact microsensors that combine semiconductor emitter-probe assemblies.

  20. Editorial

    NASA Astrophysics Data System (ADS)

    Bruzzi, Mara; Cartiglia, Nicolo; Pace, Emanuele; Talamonti, Cinzia

    2015-10-01

    The 10th edition of the International Conference on Radiation Effects on Semiconductor Materials, Detectors and Devices (RESMDD) was held in Florence, at Dipartimento di Fisica ed Astronomia on October 8-10, 2014. It has been aimed at discussing frontier research activities in several application fields as nuclear and particle physics, astrophysics, medical and solid-state physics. Main topics discussed in this conference concern performance of heavily irradiated silicon detectors, developments required for the luminosity upgrade of the Large Hadron Collider (HL-LHC), ultra-fast silicon detectors design and manufacturing, high-band gap semiconductor detectors, novel semiconductor-based devices for medical applications, radiation damage issues in semiconductors and related radiation-hardening technologies.

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