Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

1995-01-01

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

Method for making a monolithic integrated high-T.sub.c superconductor-semiconductor structure

NASA Technical Reports Server (NTRS)

Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Russell, Stephen D. (Inventor); Garcia, Graham A. (Inventor); Barfknecht, Andrew T. (Inventor); Clayton, Stanley R. (Inventor)

2000-01-01

A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Discrete Semiconductor Device Reliability

DTIC Science & Technology

1988-03-25

array or alphanumeric display. "--" indicates unknown diode count. Voc Open circuit voltage for photovoltaic modules . indicates unknown. Isc Short... circuit current for photovoltaic modules . "--" indicates unknown. Number Tested Quantity of parts under the described test or field conditions for that...information pertaining to electronic systems and parts used therein. The present scope includes integrated circuits , hybrids, discrete semiconductors

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system

NASA Astrophysics Data System (ADS)

Liu, Yang; Wang, Sheng; Liu, Huaping; Peng, Lian-Mao

2017-06-01

Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

An X-Band SOS Resistive Gate-Insulator-Semiconductor /RIS/ switch

NASA Astrophysics Data System (ADS)

Kwok, S. P.

1980-02-01

The new X-Band Resistive Gate-Insulator-Semiconductor (RIS) switch has been fabricated on silicon-on-sapphire, and its equivalent circuit model characterized. An RIS SPST switch with 20-dB on/off isolation, 1.2-dB insertion loss, and power handling capacity in excess of 20-W peak has been achieved at X band. The device switching time is on the order of 600 ns, and it requires negligible control holding current in both on and off states. The device is compatible with monolithic integrated-circuit technology and thus is suitable for integration into low-cost monolithic phase shifters or other microwave integrated circuits.

Self-contained sub-millimeter wave rectifying antenna integrated circuit

NASA Technical Reports Server (NTRS)

Siegel, Peter H. (Inventor)

2004-01-01

The invention is embodied in a monolithic semiconductor integrated circuit in which is formed an antenna, such as a slot dipole antenna, connected across a rectifying diode. In the preferred embodiment, the antenna is tuned to received an electromagnetic wave of about 2500 GHz so that the device is on the order of a wavelength in size, or about 200 microns across and 30 microns thick. This size is ideal for mounting on a microdevice such as a microrobot for example. The antenna is endowed with high gain in the direction of the incident radiation by providing a quarter-wavelength (30 microns) thick resonant cavity below the antenna, the cavity being formed as part of the monolithic integrated circuit. Preferably, the integrated circuit consists of a thin gallium arsenide membrane overlying the resonant cavity and supporting an epitaxial Gallium Arsenide semiconductor layer. The rectifying diode is a Schottky diode formed in the GaAs semiconductor layer and having an area that is a very small fraction of the wavelength of the 2500 GHz incident radiation. The cavity provides high forward gain in the antenna and isolation from surrounding structure.

Photo-Spectrometer Realized In A Standard Cmos Ic Process

DOEpatents

Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

1999-10-12

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

PubMed

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.

GaAs Optoelectronic Integrated-Circuit Neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

1992-01-01

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

VLSI (Very Large Scale Integrated Circuits) Device Reliability Models.

DTIC Science & Technology

1984-12-01

CIRCUIT COMPLEXITY FAILURE RATES FOR... A- 40 MOS SSI/MSI DEVICES IN FAILURE PER 106 HOURS TABLE 5.1.2.5-19: C1 AND C2 CIRCUIT COMPLEXITY FAILURE RATES FOR...A- 40 MOS SSI/MSI DEVICES IN FAILURE PER 106 HOURS TABLE 5.1.2.5-19: Cl AND C2 CIRCUIT COMPLEXITY FAILURE RATES FOR... A-41 LINEAR DEVICES IN...19 National Semiconductor 20 Nitron 21 Raytheon 22 Sprague 23 Synertek 24 Teledyne Crystalonics 25 TRW Semiconductor 26 Zilog The following companies

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Semiconductor Cubing

NASA Technical Reports Server (NTRS)

1996-01-01

Through Goddard Space Flight Center and Jet Propulsion Laboratory Small Business Innovation Research contracts, Irvine Sensors developed a three-dimensional memory system for a spaceborne data recorder and other applications for NASA. From these contracts, the company created the Memory Short Stack product, a patented technology for stacking integrated circuits that offers higher processing speeds and levels of integration, and lower power requirements. The product is a three-dimensional semiconductor package in which dozens of integrated circuits are stacked upon each other to form a cube. The technology is being used in various computer and telecommunications applications.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

PubMed

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Multilevel metallization method for fabricating a metal oxide semiconductor device

NASA Technical Reports Server (NTRS)

Hollis, B. R., Jr.; Feltner, W. R.; Bouldin, D. L.; Routh, D. E. (Inventor)

1978-01-01

An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield.

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

A Program in Semiconductor Processing.

ERIC Educational Resources Information Center

McConica, Carol M.

1984-01-01

A graduate program at Colorado State University which focuses on integrated circuit processing is described. The program utilizes courses from several departments while allowing students to apply chemical engineering techniques to an integrated circuit fabrication research topic. Information on employment of chemical engineers by electronics…

Lithography for enabling advances in integrated circuits and devices.

PubMed

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

1995-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2004-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Industrial Electronics II for ICT. Student's Manual.

ERIC Educational Resources Information Center

Snider, Bob

This student manual contains the following six units for classroom and laboratory experiences in high school industrial electronics: (1) introduction and review of DC and AC circuits; (2) semiconductors; (3) integrated circuits; (4) digital basics; (5) complex digital circuits; and (6) computer circuits. The units include unit objectives, specific…

Apparatus for millimeter-wave signal generation

DOEpatents

Vawter, G. Allen; Hietala, Vincent M.; Zolper, John C.; Mar, Alan; Hohimer, John P.

1999-01-01

An opto-electronic integrated circuit (OEIC) apparatus is disclosed for generating an electrical signal at a frequency .gtoreq.10 GHz. The apparatus, formed on a single substrate, includes a semiconductor ring laser for generating a continuous train of mode-locked lasing pulses and a high-speed photodetector for detecting the train of lasing pulses and generating the electrical signal therefrom. Embodiments of the invention are disclosed with an active waveguide amplifier coupling the semiconductor ring laser and the high-speed photodetector. The invention has applications for use in OEICs and millimeter-wave monolithic integrated circuits (MMICs).

Monolithic in-based III-V compound semiconductor focal plane array cell with single stage CCD output

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Cunningham, Thomas J. (Inventor); Krabach, Timothy N. (Inventor); Staller, Craig O. (Inventor)

1994-01-01

A monolithic semiconductor imager includes an indium-based III-V compound semiconductor monolithic active layer of a first conductivity type, an array of plural focal plane cells on the active layer, each of the focal plane cells including a photogate over a top surface of the active layer, a readout circuit dedicated to the focal plane cell including plural transistors formed monolithically with the monolithic active layer and a single-stage charge coupled device formed monolithically with the active layer between the photogate and the readout circuit for transferring photo-generated charge accumulated beneath the photogate during an integration period to the readout circuit. The photogate includes thin epitaxial semiconductor layer of a second conductivity type overlying the active layer and an aperture electrode overlying a peripheral portion of the thin epitaxial semiconductor layer, the aperture electrode being connectable to a photogate bias voltage.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Integrated three-dimensional module heat exchanger for power electronics cooling

DOEpatents

Bennion, Kevin; Lustbader, Jason

2013-09-24

Embodiments discussed herein are directed to a power semiconductor packaging that removes heat from a semiconductor package through one or more cooling zones that are located in a laterally oriented position with respect to the semiconductor package. Additional embodiments are directed to circuit elements that are constructed from one or more modular power semiconductor packages.

Computer-aided engineering of semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Standardization of Schwarz-Christoffel transformation for engineering design of semiconductor and hybrid integrated-circuit elements

NASA Astrophysics Data System (ADS)

Yashin, A. A.

1985-04-01

A semiconductor or hybrid structure into a calculable two-dimensional region mapped by the Schwarz-Christoffel transformation and a universal algorithm can be constructed on the basis of Maxwell's electro-magnetic-thermal similarity principle for engineering design of integrated-circuit elements. The design procedure involves conformal mapping of the original region into a polygon and then the latter into a rectangle with uniform field distribution, where conductances and capacitances are calculated, using tabulated standard mapping functions. Subsequent synthesis of a device requires inverse conformal mapping. Devices adaptable as integrated-circuit elements are high-resistance film resistors with periodic serration, distributed-resistance film attenuators with high transformation ratio, coplanar microstrip lines, bipolar transistors, directional couplers with distributed coupling to microstrip lines for microwave bulk devices, and quasirregular smooth matching transitions from asymmetric to coplanar microstrip lines.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Wavelength-division multiplexed optical integrated circuit with vertical diffraction grating

NASA Technical Reports Server (NTRS)

Lang, Robert J. (Inventor); Forouhar, Siamak (Inventor)

1994-01-01

A semiconductor optical integrated circuit for wave division multiplexing has a semiconductor waveguide layer, a succession of diffraction grating points in the waveguide layer along a predetermined diffraction grating contour, a semiconductor diode array in the waveguide layer having plural optical ports facing the succession of diffraction grating points along a first direction, respective semiconductor diodes in the array corresponding to respective ones of a predetermined succession of wavelengths, an optical fiber having one end thereof terminated at the waveguide layer, the one end of the optical fiber facing the succession of diffraction grating points along a second direction, wherein the diffraction grating points are spatially distributed along the predetermined contour in such a manner that the succession of diffraction grating points diffracts light of respective ones of the succession of wavelengths between the one end of the optical fiber and corresponding ones of the optical ports.

Advanced 3-V semiconductor technology assessment

NASA Technical Reports Server (NTRS)

Nowogrodzki, M.

1983-01-01

Components required for extensions of currently planned space communications systems are discussed for large antennas, crosslink systems, single sideband systems, Aerostat systems, and digital signal processing. Systems using advanced modulation concepts and new concepts in communications satellites are included. The current status and trends in materials technology are examined with emphasis on bulk growth of semi-insulating GaAs and InP, epitaxial growth, and ion implantation. Microwave solid state discrete active devices, multigigabit rate GaAs digital integrated circuits, microwave integrated circuits, and the exploratory development of GaInAs devices, heterojunction devices, and quasi-ballistic devices is considered. Competing technologies such as RF power generation, filter structures, and microwave circuit fabrication are discussed. The fundamental limits of semiconductor devices and problems in implementation are explored.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Parallel stitching of 2D materials

DOE PAGES

Ling, Xi; Wu, Lijun; Lin, Yuxuan; ...

2016-01-27

Diverse parallel stitched 2D heterostructures, including metal–semiconductor, semiconductor–semiconductor, and insulator–semiconductor, are synthesized directly through selective “sowing” of aromatic molecules as the seeds in the chemical vapor deposition (CVD) method. Lastly, the methodology enables the large-scale fabrication of lateral heterostructures, which offers tremendous potential for its application in integrated circuits.

Monolithic 3D CMOS Using Layered Semiconductors.

PubMed

Sachid, Angada B; Tosun, Mahmut; Desai, Sujay B; Hsu, Ching-Yi; Lien, Der-Hsien; Madhvapathy, Surabhi R; Chen, Yu-Ze; Hettick, Mark; Kang, Jeong Seuk; Zeng, Yuping; He, Jr-Hau; Chang, Edward Yi; Chueh, Yu-Lun; Javey, Ali; Hu, Chenming

2016-04-06

Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Making A D-Latch Sensitive To Alpha Particles

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Nixon, Robert H.

1994-01-01

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

The Design and Assessment of a Hypermedia Course on Semiconductor Manufacturing.

ERIC Educational Resources Information Center

Schank, Patrick K.; Rowe, Lawrence A.

1993-01-01

Describes the design and evaluation of a multimedia course on integrated circuit manufacturing that was developed at the University of California at Berkeley using IC-HIP (Integrated Circuit-Hypermedia in PICASSO), a hypermedia-based instructional system. Learning effects based on prior knowledge, methods of navigation, and other factors are…

A Subthreshold Digital Library Using a Dynamic-Threshold Metal-Oxide Semiconductor (DTMOS) and Transmission Gate Logic

DTIC Science & Technology

2014-09-01

electrocardiography (ECG), electromyography (EMG), and electroencephalography (EEG) applications that operate using thermoelectrically generated energy...semiconductor ECG electrocardiography EEG electroencephalography EMG electromyography FY15 fiscal year 2015 IC integrated circuit MOSFETs

75 FR 65654 - In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-10-26

...'') granting a motion filed by complainant Freescale Semiconductor, Inc. (``Freescale'') for leave to amend its... April 2, 2010, based on a complaint filed by Freescale Semiconductor of Austin, Texas (``Freescale...

75 FR 49524 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-08-13

...'') granting a motion filed by complainant Freescale Semiconductor, Inc. (``Freescale'') for leave to amend its..., 2010, based on a complaint filed by Freescale Semiconductor of Austin, Texas (``Freescale''). 75 FR...

Graphene radio frequency receiver integrated circuit.

PubMed

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Graphene radio frequency receiver integrated circuit

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A.; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Development of analog watch with minute repeater

NASA Astrophysics Data System (ADS)

Okigami, Tomio; Aoyama, Shigeru; Osa, Takashi; Igarashi, Kiyotaka; Ikegami, Tomomi

A complementary metal oxide semiconductor with large scale integration was developed for an electronic minute repeater. It is equipped with the synthetic struck sound circuit to generate natural struck sound necessary for the minute repeater. This circuit consists of an envelope curve drawing circuit, frequency mixer, polyphonic mixer, and booster circuit made by using analog circuit technology. This large scale integration is a single chip microcomputer with motor drivers and input ports in addition to the synthetic struck sound circuit, and it is possible to make an electronic system of minute repeater at a very low cost in comparison with the conventional type.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

An integrated semiconductor device enabling non-optical genome sequencing.

PubMed

Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

2011-07-20

The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

Integrated-circuit balanced parametric amplifier

NASA Technical Reports Server (NTRS)

Dickens, L. E.

1975-01-01

Amplifier, fabricated on single dielectric substrate, has pair of Schottky barrier varactor diodes mounted on single semiconductor chip. Circuit includes microstrip transmission line and slot line section to conduct signals. Main features of amplifier are reduced noise output and low production cost.

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.;

The Integration of Bacteriorhodopsin Proteins with Semiconductor Heterostructure Devices

NASA Astrophysics Data System (ADS)

Xu, Jian

2008-03-01

Bioelectronics has emerged as one of the most rapidly developing fields among the active frontiers of interdisciplinary research. A major thrust in this field is aimed at the coupling of the technologically-unmatched performance of biological systems, such as neural and sensing functions, with the well developed technology of microelectronics and optoelectronics. To this end we have studied the integration of a suitably engineered protein, bacteriorhodopsin (BR), with semiconductor optoelectronic devices and circuits. Successful integration will potentially lead to ultrasensitive sensors with polarization selectivity and built-in preprocessing capabilities that will be useful for high speed tracking, motion and edge detection, biological detection, and artificial vision systems. In this presentation we will summarize our progresses in this area, which include fundamental studies on the transient dynamics of photo-induced charge shift in BR and the coupling mechanism at protein-semiconductor interface for effective immobilizing and selectively integrating light sensitive proteins with microelectronic devices and circuits, and the device engineering of BR-transistor-integrated optical sensors as well as their applications in phototransceiver circuits. Work done in collaboration with Pallab Bhattacharya, Jonghyun Shin, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI; Robert R. Birge, Department of Chemistry, University of Connecticut, Storrs, CT 06269; and György V'ar'o, Institute of Biophysics, Biological Research Center of the Hungarian Academy of Science, H-6701 Szeged, Hungary.

Active pixel sensor array with multiresolution readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Kemeny, Sabrina E. (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. The imaging device can also include an electronic shutter formed on the substrate adjacent the photogate, and/or a storage section to allow for simultaneous integration. In addition, the imaging device can include a multiresolution imaging circuit to provide images of varying resolution. The multiresolution circuit could also be employed in an array where the photosensitive portion of each pixel cell is a photodiode. This latter embodiment could further be modified to facilitate low light imaging.

Power semiconductor device with negative thermal feedback

NASA Technical Reports Server (NTRS)

Borky, J. M.; Thornton, R. D.

1970-01-01

Composite power semiconductor avoids second breakdown and provides stable operation. It consists of an array of parallel-connected integrated circuits fabricated in a single chip. The output power device and associated low-level amplifier are closely coupled thermally, so that they have a predetermined temperature relationship.

SPICE Modeling of Body Bias Effect in 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Smart Power: New power integrated circuit technologies and their applications

NASA Astrophysics Data System (ADS)

Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

1992-05-01

Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum

ERIC Educational Resources Information Center

Smith, S. C.; Al-Assadi, W. K.; Di, J.

2010-01-01

As demand increases for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used in the semiconductor industry, as evidenced by the International Technology Roadmap for Semiconductors' (ITRS) prediction of a likely shift from synchronous to asynchronous design…

Microwave GaAs Integrated Circuits On Quartz Substrates

NASA Technical Reports Server (NTRS)

Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

1994-01-01

Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Interfacing spin qubits in quantum dots and donors—hot, dense, and coherent

NASA Astrophysics Data System (ADS)

Vandersypen, L. M. K.; Bluhm, H.; Clarke, J. S.; Dzurak, A. S.; Ishihara, R.; Morello, A.; Reilly, D. J.; Schreiber, L. R.; Veldhorst, M.

2017-09-01

Semiconductor spins are one of the few qubit realizations that remain a serious candidate for the implementation of large-scale quantum circuits. Excellent scalability is often argued for spin qubits defined by lithography and controlled via electrical signals, based on the success of conventional semiconductor integrated circuits. However, the wiring and interconnect requirements for quantum circuits are completely different from those for classical circuits, as individual direct current, pulsed and in some cases microwave control signals need to be routed from external sources to every qubit. This is further complicated by the requirement that these spin qubits currently operate at temperatures below 100 mK. Here, we review several strategies that are considered to address this crucial challenge in scaling quantum circuits based on electron spin qubits. Key assets of spin qubits include the potential to operate at 1 to 4 K, the high density of quantum dots or donors combined with possibilities to space them apart as needed, the extremely long-spin coherence times, and the rich options for integration with classical electronics based on the same technology.

Inclusion of Body Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 degrees Celsius durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Inclusion of Body-Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Metal oxide semiconductor thin-film transistors for flexible electronics

NASA Astrophysics Data System (ADS)

Petti, Luisa; Münzenrieder, Niko; Vogt, Christian; Faber, Hendrik; Büthe, Lars; Cantarella, Giuseppe; Bottacchi, Francesca; Anthopoulos, Thomas D.; Tröster, Gerhard

2016-06-01

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This review reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.

Metal oxide semiconductor thin-film transistors for flexible electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petti, Luisa; Vogt, Christian; Büthe, Lars

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This reviewmore » reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.« less

A new approximation of Fermi-Dirac integrals of order 1/2 for degenerate semiconductor devices

NASA Astrophysics Data System (ADS)

AlQurashi, Ahmed; Selvakumar, C. R.

2018-06-01

There had been tremendous growth in the field of Integrated circuits (ICs) in the past fifty years. Scaling laws mandated both lateral and vertical dimensions to be reduced and a steady increase in doping densities. Most of the modern semiconductor devices have invariably heavily doped regions where Fermi-Dirac Integrals are required. Several attempts have been devoted to developing analytical approximations for Fermi-Dirac Integrals since numerical computations of Fermi-Dirac Integrals are difficult to use in semiconductor devices, although there are several highly accurate tabulated functions available. Most of these analytical expressions are not sufficiently suitable to be employed in semiconductor device applications due to their poor accuracy, the requirement of complicated calculations, and difficulties in differentiating and integrating. A new approximation has been developed for the Fermi-Dirac integrals of the order 1/2 by using Prony's method and discussed in this paper. The approximation is accurate enough (Mean Absolute Error (MAE) = 0.38%) and easy enough to be used in semiconductor device equations. The new approximation of Fermi-Dirac Integrals is applied to a more generalized Einstein Relation which is an important relation in semiconductor devices.

Slow-wave propagation on monolithic microwave integrated circuits with layered and non-layered structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tzuang, C.K.C.

1986-01-01

Various MMIC (monolithic microwave integrated circuit) planar waveguides have shown possible existence of a slow-wave propagation. In many practical applications of these slow-wave circuits, the semiconductor devices have nonuniform material properties that may affect the slow-wave propagation. In the first part of the dissertation, the effects of the nonuniform material properties are studied by a finite-element method. In addition, the transient pulse excitations of these slow-wave circuits also have great theoretical and practical interests. In the second part, the time-domain analysis of a slow-wave coplanar waveguide is presented.

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

2005-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Roadmap evolution: from NTRS to ITRS, from ITRS 2.0 to IRDS

NASA Astrophysics Data System (ADS)

Gargini, Paolo A.

2017-10-01

The semiconductor industry benefitted from roadmap guidance since the mid-60s. The roadmap anticipated and outlined the main needs of the semiconductor industry for years to come and identified future challenges and possible solutions. Making transistor smaller by means of advanced lithographic technologies enabled both increased integration levels and improved IC performance. The roadmap methodology allowed the removal of multiple "red brick walls". The NTRS and the ITRS constituted primarily a "bottom up" approach as standard microprocessors and memories where introduced at a blistering pace barely allowing time for system houses to integrate them in their products. The 1998 ITRS provided the vision that triggered research, development and manufacturing communities to develop a completely new transistor structure in addition to replacing aluminum interconnects with a more advanced technology. The advent of Foundries and Fabless companies transformed the electronics industry into a "top down" driven industry in the past 15 years. The ITRS adjusted to this new ecosystem and morphed into the International Roadmap for Devices and Systems (IRDS) sponsored by IEEE. The IRDS is addressing the requirements and needs of the renewed electronics industry. Furthermore, by the middle of the next decade the ability to layout integrated circuits in a 2D geometry grid will reach fundamental physical limits and the aggressive conversion to 3D architecture for integrated circuit must be pursued across the board as an avenue to continuously increasing transistor count and improving performance. EUV technology is finally approaching the manufacturing stage but with the advent of 3D monolithically integrated heterogeneous circuits approaching in the not-toodistant future should the semiconductor industry concentrate its resources on the next lithographic technology generation in order to enhance resolution or on providing a smooth transition to the new revolutionary 3D architecture of integrated circuits? It is essential for the whole semiconductor industry to come together and make fundamental choices leading to a cooperative and synchronized allocation of adequate resources to produce viable solutions that once introduced in a timely manner into manufacturing will enable the continuation of the growth of the electronic industry at a pace comparable or exceeding historical trends.

Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

NASA Astrophysics Data System (ADS)

Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

2017-02-01

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

PubMed

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

NASA Astrophysics Data System (ADS)

Ostrowsky, D. B.; Sriram, S.

Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

From Bell Labs to Silicon Valley: A Saga of Technology Transfer, 1954-1961

NASA Astrophysics Data System (ADS)

Riordan, Michael

2009-03-01

Although Bell Telephone Laboratories invented the transistor and developed most of the associated semiconductor technology, the integrated circuit or microchip emerged elsewhere--at Texas Instruments and Fairchild Semiconductor Company. I recount how the silicon technology required to make microchips possible was first developed at Bell Labs in the mid-1950s. Much of it reached the San Francisco Bay Area when transistor pioneer William Shockley left Bell Labs in 1955 to establish the Shockley Semiconductor Laboratory in Mountain View, hiring a team of engineers and scientists to develop and manufacture transistors and related semiconductor devices. But eight of them--including Gordon Moore and Robert Noyce, eventually the co-founders of Intel--resigned en masse in September 1957 to start Fairchild, bringing with them the scientific and technological expertise they had acquired and further developed at Shockley's firm. This event marked the birth of Silicon Valley, both technologically and culturally. By March 1961 the company was marketing its Micrologic integrated circuits, the first commercial silicon microchips, based on the planar processing technique developed at Fairchild by Jean Hoerni.

The future of automation for high-volume wafer fabrication and ASIC manufacturing

NASA Astrophysics Data System (ADS)

Hughes, Randall A.; Shott, John D.

1986-12-01

A framework is given to analyze the future trends in semiconductor manufacturing automation systems, focusing specifically on the needs of ASIC (application-specific integrated circuit) or custom integrated circuit manufacturing. Advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating nonstandard functions on silicon. ASICs are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. Previously, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment.

VLSI (Very Large Scale Integrated) Design of a 16 Bit Very Fast Pipelined Carry Look Ahead Adder.

DTIC Science & Technology

1983-09-01

the ability for systems engineers to custom design digital integrated circuits. Until recently, the design of integrated circuits has been...traditionally carried out by a select group of logic designers working in semiconductor laboratories. Systems engineers had to "make do" or "fit in" the...products of these labs to realize their designs. The systems engineers had little participation in the actual design of the chip. The MED and CONWAY design

Silica Integrated Optical Circuits Based on Glass Photosensitivity

NASA Technical Reports Server (NTRS)

Abushagur, Mustafa A. G.

1999-01-01

Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

Very high speed integrated circuits - Into the second generation. V - The issues of standardization and technology insertion

NASA Astrophysics Data System (ADS)

Martin, J.

1982-04-01

It is shown that the fulfillment of very high speed integrated circuit (VHSIC) device development goals entails the restructuring of military electronics acquisition policy, standardization which produces the maximum number of systems and subsystems by means of the minimum number of flexible, broad-purpose, high-power semiconductors, and especially the standardization of bus structures incorporating a priorization system. It is expected that the Design Specification Handbook currently under preparation by the VHSIC program office of the DOD will make the design of such systems a task whose complexity is comparable to that of present integrated circuit electronics.

Laboratory experiments in integrated circuit fabrication

NASA Technical Reports Server (NTRS)

Jenkins, Thomas J.; Kolesar, Edward S.

1993-01-01

The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

Bridging the Hardware-Software Gap: A Proof Carrying Approach for Computer Systems Trust Evaluation (5.3.5)

DTIC Science & Technology

2017-08-22

has significantly lowered the design cost and shortened the time-to- market (TTM) of Integrated Circuits (ICs) in the electronic industry. Over the...semiconductor companies have focused on high-profit phases such as design, marketing , and sales and have outsourced chip manufacturing, wafer fabrication...supply chain has significantly lowered the design cost and shortened the time- to- market (TTM) of integrated circuits (ICs) in the electronic

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

PubMed

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Reconfigurable exciton-plasmon interconversion for nanophotonic circuits

PubMed Central

Lee, Hyun Seok; Luong, Dinh Hoa; Kim, Min Su; Jin, Youngjo; Kim, Hyun; Yun, Seokjoon; Lee, Young Hee

2016-01-01

The recent challenges for improving the operation speed of nanoelectronics have motivated research on manipulating light in on-chip integrated circuits. Hybrid plasmonic waveguides with low-dimensional semiconductors, including quantum dots and quantum wells, are a promising platform for realizing sub-diffraction limited optical components. Meanwhile, two-dimensional transition metal dichalcogenides (TMDs) have received broad interest in optoelectronics owing to tightly bound excitons at room temperature, strong light-matter and exciton-plasmon interactions, available top-down wafer-scale integration, and band-gap tunability. Here, we demonstrate principal functionalities for on-chip optical communications via reconfigurable exciton-plasmon interconversions in ∼200-nm-diameter Ag-nanowires overlapping onto TMD transistors. By varying device configurations for each operation purpose, three active components for optical communications are realized: field-effect exciton transistors with a channel length of ∼32 μm, field-effect exciton multiplexers transmitting multiple signals through a single NW and electrical detectors of propagating plasmons with a high On/Off ratio of∼190. Our results illustrate the unique merits of two-dimensional semiconductors for constructing reconfigurable device architectures in integrated nanophotonic circuits. PMID:27892463

The present situation and forecasts of semiconductor elements performance within the microwave range, 1970-1985

NASA Technical Reports Server (NTRS)

Peterson, B.

1978-01-01

The present situation and possible developments over the period 1970-1985 for active semiconductor elements in the microwave range are outlined. After a short historical survey of FT techniques, the following are discussed: Generation, power amplification, amplification of small signals, frequency conversion, detection, electronic signal control and integrated microwave circuits.

Department of Defense statement on the X-ray Lithography Program to the Research and Development Subcommittee of the House Armed Services Committee of 100th Congress, second session

NASA Astrophysics Data System (ADS)

Maynard, E. D., Jr.

1988-03-01

The Department has a broad and necessarily diverse program in semiconductor science and technology. The three principal goals of that effort are: Reduce the gap between commercial integrated circuit usage and its deployment in military systems, assure a healthy on-shore industrial base to support our defense needs, enhance the producibility of specialized military semiconductor products. The major effort to achieve the first of these objectives is the Very High Speed Integrated Circuits (VHSIC) Program which is nearing completion. The Microwave/millimeter wave Monolithic Integrated Circuit (MIMIC) program has just completed a study program to define the product mix needed to meet military system requirements for radar, electronic warfare, smart weapons and telecommunications. We are bringing together the system requirements of all DoD with the device fabrication and product delivery capabilities of industry in an Infrared Focal Plane Array (IRFPA) program. The goal of the Software Initiative is to enhance our warfighting capability through development of efficient software generation technology and products plus the creation of a technology infusion infrastructure to couple the technology and products to system applications. The X-Ray Lithography Program will begin to establish the industrial base which will be required to sustain U.S. leadership in the semiconductor industry for the late 1990s.

Transparent megahertz circuits from solution-processed composite thin films.

PubMed

Liu, Xingqiang; Wan, Da; Wu, Yun; Xiao, Xiangheng; Guo, Shishang; Jiang, Changzhong; Li, Jinchai; Chen, Tangsheng; Duan, Xiangfeng; Fan, Zhiyong; Liao, Lei

2016-04-21

Solution-processed amorphous oxide semiconductors have attracted considerable interest in large-area transparent electronics. However, due to its relative low carrier mobility (∼10 cm(2) V(-1) s(-1)), the demonstrated circuit performance has been limited to 800 kHz or less. Herein, we report solution-processed high-speed thin-film transistors (TFTs) and integrated circuits with an operation frequency beyond the megahertz region on 4 inch glass. The TFTs can be fabricated from an amorphous indium gallium zinc oxide/single-walled carbon nanotube (a-IGZO/SWNT) composite thin film with high yield and high carrier mobility of >70 cm(2) V(-1) s(-1). On-chip microwave measurements demonstrate that these TFTs can deliver an unprecedented operation frequency in solution-processed semiconductors, including an extrinsic cut-off frequency (f(T) = 102 MHz) and a maximum oscillation frequency (f(max) = 122 MHz). Ring oscillators further demonstrated an oscillation frequency of 4.13 MHz, for the first time, realizing megahertz circuit operation from solution-processed semiconductors. Our studies represent an important step toward high-speed solution-processed thin film electronics.

Total-dose radiation effects data for semiconductor devices. 1985 Supplement. Volume 2, part B

NASA Technical Reports Server (NTRS)

Martin, K. E.; Gauthier, M. K.; Coss, J. R.; Dantas, A. R. V.; Price, W. E.

1986-01-01

Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 (Parts A and B) provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done steady-state 2.5-MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose. All data were generated in support of NASA space programs by the JPL Radiation Effects and Testing Group (514).

FIBER AND INTEGRATED OPTICS: Photodetector waveguide structures made of epitaxial InGaAs films and intended for integrated circuits manufactured from III-V semiconductor compounds

NASA Astrophysics Data System (ADS)

Shmal'ko, A. V.; Lamekin, V. F.; Smirnov, V. L.; Polyantsev, A. S.; Kogan, Yu I.; Babushkina, T. S.; Kuntsevich, T. S.; Peshkovskaya, O. G.

1990-08-01

Photodetector waveguide structures made of epitaxial InxGa1 - xAs solid-solution films were developed and investigated. These structures were intended for optical integrated circuits manufactured from III-V semiconductor compounds for operation in the wavelength range 1.0-1.5 μm. Two types of photodetector waveguide p-i-n structures were developed. They consisted of a composite waveguide and tunnel-coupled waveguides, respectively. A study was made of structural parameters, responsivity, spectral and time characteristics, and dark currents in photodetectors made of the waveguide structures. This investigation was carried out in the wavelength range 1.0-1.3 μm. The maximum spectral responsivity of one of the types of the waveguide photodetector was ~ 0.5 ± 0.1 A/W and the dark current did not exceed 10 - 7-10 - 8 A.

Total-dose radiation effects data for semiconductor devices. 1985 supplement. Volume 2, part A

NASA Technical Reports Server (NTRS)

Martin, K. E.; Gauthier, M. K.; Coss, J. R.; Dantas, A. R. V.; Price, W. E.

1986-01-01

Steady-state, total-dose radiation test data, are provided in graphic format for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. This volume provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done using the JPL or Boeing electron accelerator (Dynamitron) which provides a steady-state 2.5 MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Semiconductor diode with external field modulation

DOEpatents

Nasby, Robert D.

2000-01-01

A non-destructive-readout nonvolatile semiconductor diode switching device that may be used as a memory element is disclosed. The diode switching device is formed with a ferroelectric material disposed above a rectifying junction to control the conduction characteristics therein by means of a remanent polarization. The invention may be used for the formation of integrated circuit memories for the storage of information.

WOCSDICE󈧇 The 27th Workshop on Compound Semiconductor Devices and Integrated Circuits Held in Europe May 26 - 28, 2003 Forigen, Switzerland

DTIC Science & Technology

2003-05-28

Rodrigues-Girones, M. Saglam, A. Megej, H.L. Hartnagel vi Recent Advances, Remaining Challenges in Wide Bandgap Semiconductors Colin ...R. H. Friend, and H. Sirringhaus, Science, 299, pp. 1881-1884, 2003. 19. C. J. Drury , C. M. J. Mutsaers, C. M. Hart, M. Matters, and D. M. de Leeuw

Functional Laser Trimming Of Thin Film Resistors On Silicon ICs

NASA Astrophysics Data System (ADS)

Mueller, Michael J.; Mickanin, Wes

1986-07-01

Modern Laser Wafer Trimming (LWT) technology achieves exceptional analog circuit performance and precision while maintain-ing the advantages of high production throughput and yield. Microprocessor-driven instrumentation has both emphasized the role of data conversion circuits and demanded sophisticated signal conditioning functions. Advanced analog semiconductor circuits with bandwidths over 1 GHz, and high precision, trimmable, thin-film resistors meet many of todays emerging circuit requirements. Critical to meeting these requirements are optimum choices of laser characteristics, proper materials, trimming process control, accurate modeling of trimmed resistor performance, and appropriate circuit design. Once limited exclusively to hand-crafted, custom integrated circuits, designs are now available in semi-custom circuit configurations. These are similar to those provided for digital designs and supported by computer-aided design (CAD) tools. Integrated with fully automated measurement and trimming systems, these quality circuits can now be produced in quantity to meet the requirements of communications, instrumentation, and signal processing markets.

454th Brookhaven Lecture

ScienceCinema

Charles Black

2017-12-09

Black discusses examples of integrating self-assembly into semiconductor microelectronics, where advances in the ability to define circuit elements at ever-higher resolution have largely fueled more than 40 years of consistent performance improvements

SEMICONDUCTOR INTEGRATED CIRCUITS: A quasi-3-dimensional simulation method for a high-voltage level-shifting circuit structure

NASA Astrophysics Data System (ADS)

Jizhi, Liu; Xingbi, Chen

2009-12-01

A new quasi-three-dimensional (quasi-3D) numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.

Packet Controller For Wireless Headset

NASA Technical Reports Server (NTRS)

Christensen, Kurt K.; Swanson, Richard J.

1993-01-01

Packet-message controller implements communications protocol of network of wireless headsets. Designed for headset application, readily adapted to other uses; slight modification enables controller to implement Integrated Services Digital Network (ISDN) X.25 protocol, giving far-reaching applications in telecommunications. Circuit converts continuous voice signals into digital packets of data and vice versa. Operates in master or slave mode. Controller reduced to single complementary metal oxide/semiconductor integrated-circuit chip. Occupies minimal space in headset and consumes little power, extending life of headset battery.

Study of SEM induced current and voltage contrast modes to assess semiconductor reliability

NASA Technical Reports Server (NTRS)

Beall, J. R.

1976-01-01

The purpose of the scanning electron microscopy study was to review the failure history of existing integrated circuit technologies to identify predominant failure mechanisms, and to evaluate the feasibility of their detection using SEM application techniques. The study investigated the effects of E-beam irradiation damage and contamination deposition rates; developed the necessary methods for applying the techniques to the detection of latent defects and weaknesses in integrated circuits; and made recommendations for applying the techniques.

A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

PubMed

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-03-15

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Four-terminal circuit element with photonic core

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sampayan, Stephen

A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated basedmore » on electrical bias or control designs. The photonic core aspect of the four-terminal circuit element provides unique features that enable versatile circuit applications to either replace the semiconductor transistor-based circuit elements or semiconductor diode-based circuit elements.« less

A Way to End the IC Designer Shortage.

ERIC Educational Resources Information Center

Robinson, Arthur L.

1980-01-01

Discusses the problem of the shortage of engineers capable of designing advanced integrated circuits (IC) and presents some suggestions for increasing the number of IC designers in universities and semiconductor companies. (HM)

Speed-Up Techniques for Complementary Metal Oxide Semiconductor Very Large Scale Integration.

DTIC Science & Technology

1984-12-14

The input voltage at which the two transistors are in the constant current region at the same time marks the active operating region of the inverter...decoder precharge configurations. One circuit displayed a marked enhancement in operation while the other precharged circuit displyed degraded operation due...34 IEEE Journal of Solid State Circuits, SC-18: 457-462 (October 1983). 19. Cobbold , R. Theory and Applications of Field Effect Transistors, New York: John

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Spin-Based Devices for Magneto-Optoelectronic Integrated Circuits

DTIC Science & Technology

2009-04-29

bulk material and matches that in quantum wells. While these simple linear relationships hold for spin-polarized light-emitting diodes (spin-LEDs...temperature. The quantum efficiency and hence r| increases with decreasing temperature. The individual circuit elements, 33 therefore, exhibit the...Injection, Threshold Reduction and Output Circular Polarization Modulation in Quantum Well and Quantum Dot Semiconductor Spin Polarized Lasers working

Extremely high frequency RF effects on electronics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Loubriel, Guillermo Manuel; Vigliano, David; Coleman, Phillip Dale

The objective of this work was to understand the fundamental physics of extremely high frequency RF effects on electronics. To accomplish this objective, we produced models, conducted simulations, and performed measurements to identify the mechanisms of effects as frequency increases into the millimeter-wave regime. Our purpose was to answer the questions, 'What are the tradeoffs between coupling, transmission losses, and device responses as frequency increases?', and, 'How high in frequency do effects on electronic systems continue to occur?' Using full wave electromagnetics codes and a transmission-line/circuit code, we investigated how extremely high-frequency RF propagates on wires and printed circuit boardmore » traces. We investigated both field-to-wire coupling and direct illumination of printed circuit boards to determine the significant mechanisms for inducing currents at device terminals. We measured coupling to wires and attenuation along wires for comparison to the simulations, looking at plane-wave coupling as it launches modes onto single and multiconductor structures. We simulated the response of discrete and integrated circuit semiconductor devices to those high-frequency currents and voltages, using SGFramework, the open-source General-purpose Semiconductor Simulator (gss), and Sandia's Charon semiconductor device physics codes. This report documents our findings.« less

Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

NASA Technical Reports Server (NTRS)

Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

Calculating Second-Order Effects in MOSFET's

NASA Technical Reports Server (NTRS)

Benumof, Reuben; Zoutendyk, John A.; Coss, James R.

1990-01-01

Collection of mathematical models includes second-order effects in n-channel, enhancement-mode, metal-oxide-semiconductor field-effect transistors (MOSFET's). When dimensions of circuit elements relatively large, effects neglected safely. However, as very-large-scale integration of microelectronic circuits leads to MOSFET's shorter or narrower than 2 micrometer, effects become significant in design and operation. Such computer programs as widely-used "Simulation Program With Integrated Circuit Emphasis, Version 2" (SPICE 2) include many of these effects. In second-order models of n-channel, enhancement-mode MOSFET, first-order gate-depletion region diminished by triangular-cross-section deletions on end and augmented by circular-wedge-cross-section bulges on sides.

Experimental demonstration of distributed feedback semiconductor lasers based on reconstruction-equivalent-chirp technology.

PubMed

Li, Jingsi; Wang, Huan; Chen, Xiangfei; Yin, Zuowei; Shi, Yuechun; Lu, Yanqing; Dai, Yitang; Zhu, Hongliang

2009-03-30

In this paper we report, to the best of our knowledge, the first experimental realization of distributed feedback (DFB) semiconductor lasers based on reconstruction-equivalent-chirp (REC) technology. Lasers with different lasing wavelengths are achieved simultaneously on one chip, which shows a potential for the REC technology in combination with the photonic integrated circuits (PIC) technology to be a possible method for monolithic integration, in that its fabrication is as powerful as electron beam technology and the cost and time-consuming are almost the same as standard holographic technology.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Quantum dash based single section mode locked lasers for photonic integrated circuits.

PubMed

Joshi, Siddharth; Calò, Cosimo; Chimot, Nicolas; Radziunas, Mindaugas; Arkhipov, Rostislav; Barbet, Sophie; Accard, Alain; Ramdane, Abderrahim; Lelarge, Francois

2014-05-05

We present the first demonstration of an InAs/InP Quantum Dash based single-section frequency comb generator designed for use in photonic integrated circuits (PICs). The laser cavity is closed using a specifically designed Bragg reflector without compromising the mode-locking performance of the self pulsating laser. This enables the integration of single-section mode-locked laser in photonic integrated circuits as on-chip frequency comb generators. We also investigate the relations between cavity modes in such a device and demonstrate how the dispersion of the complex mode frequencies induced by the Bragg grating implies a violation of the equi-distance between the adjacent mode frequencies and, therefore, forbids the locking of the modes in a classical Bragg Device. Finally we integrate such a Bragg Mirror based laser with Semiconductor Optical Amplifier (SOA) to demonstrate the monolithic integration of QDash based low phase noise sources in PICs.

Hybrid integrated biological-solid-state system powered with adenosine triphosphate.

PubMed

Roseman, Jared M; Lin, Jianxun; Ramakrishnan, Siddharth; Rosenstein, Jacob K; Shepard, Kenneth L

2015-12-07

There is enormous potential in combining the capabilities of the biological and the solid state to create hybrid engineered systems. While there have been recent efforts to harness power from naturally occurring potentials in living systems in plants and animals to power complementary metal-oxide-semiconductor integrated circuits, here we report the first successful effort to isolate the energetics of an electrogenic ion pump in an engineered in vitro environment to power such an artificial system. An integrated circuit is powered by adenosine triphosphate through the action of Na(+)/K(+) adenosine triphosphatases in an integrated in vitro lipid bilayer membrane. The ion pumps (active in the membrane at numbers exceeding 2 × 10(6) mm(-2)) are able to sustain a short-circuit current of 32.6 pA mm(-2) and an open-circuit voltage of 78 mV, providing for a maximum power transfer of 1.27 pW mm(-2) from a single bilayer. Two series-stacked bilayers provide a voltage sufficient to operate an integrated circuit with a conversion efficiency of chemical to electrical energy of 14.9%.

Spatially controlled doping of two-dimensional SnS 2 through intercalation for electronics

DOE PAGES

Gong, Yongji; Yuan, Hongtao; Wu, Chun-Lan; ...

2018-02-26

Doped semiconductors are the most important building elements for modern electronic devices. In silicon-based integrated circuits, facile and controllable fabrication and integration of these materials can be realized without introducing a high-resistance interface. Besides, the emergence of two-dimensional (2D) materials enables the realization of atomically thin integrated circuits. However, the 2D nature of these materials precludes the use of traditional ion implantation techniques for carrier doping and further hinders device development10. Here, we demonstrate a solvent-based intercalation method to achieve p-type, n-type and degenerately doped semiconductors in the same parent material at the atomically thin limit. In contrast to naturallymore » grown n-type S-vacancy SnS 2, Cu intercalated bilayer SnS 2 obtained by this technique displays a hole field-effect mobility of ~40 cm 2 V -1 s -1, and the obtained Co-SnS 2 exhibits a metal-like behaviour with sheet resistance comparable to that of few-layer graphene. Combining this intercalation technique with lithography, an atomically seamless p–n–metal junction could be further realized with precise size and spatial control, which makes in-plane heterostructures practically applicable for integrated devices and other 2D materials. Therefore, the presented intercalation method can open a new avenue connecting the previously disparate worlds of integrated circuits and atomically thin materials.« less

Spatially controlled doping of two-dimensional SnS 2 through intercalation for electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gong, Yongji; Yuan, Hongtao; Wu, Chun-Lan

Doped semiconductors are the most important building elements for modern electronic devices. In silicon-based integrated circuits, facile and controllable fabrication and integration of these materials can be realized without introducing a high-resistance interface. Besides, the emergence of two-dimensional (2D) materials enables the realization of atomically thin integrated circuits. However, the 2D nature of these materials precludes the use of traditional ion implantation techniques for carrier doping and further hinders device development10. Here, we demonstrate a solvent-based intercalation method to achieve p-type, n-type and degenerately doped semiconductors in the same parent material at the atomically thin limit. In contrast to naturallymore » grown n-type S-vacancy SnS 2, Cu intercalated bilayer SnS 2 obtained by this technique displays a hole field-effect mobility of ~40 cm 2 V -1 s -1, and the obtained Co-SnS 2 exhibits a metal-like behaviour with sheet resistance comparable to that of few-layer graphene. Combining this intercalation technique with lithography, an atomically seamless p–n–metal junction could be further realized with precise size and spatial control, which makes in-plane heterostructures practically applicable for integrated devices and other 2D materials. Therefore, the presented intercalation method can open a new avenue connecting the previously disparate worlds of integrated circuits and atomically thin materials.« less

Spatially controlled doping of two-dimensional SnS2 through intercalation for electronics

NASA Astrophysics Data System (ADS)

Gong, Yongji; Yuan, Hongtao; Wu, Chun-Lan; Tang, Peizhe; Yang, Shi-Ze; Yang, Ankun; Li, Guodong; Liu, Bofei; van de Groep, Jorik; Brongersma, Mark L.; Chisholm, Matthew F.; Zhang, Shou-Cheng; Zhou, Wu; Cui, Yi

2018-04-01

Doped semiconductors are the most important building elements for modern electronic devices1. In silicon-based integrated circuits, facile and controllable fabrication and integration of these materials can be realized without introducing a high-resistance interface2,3. Besides, the emergence of two-dimensional (2D) materials enables the realization of atomically thin integrated circuits4-9. However, the 2D nature of these materials precludes the use of traditional ion implantation techniques for carrier doping and further hinders device development10. Here, we demonstrate a solvent-based intercalation method to achieve p-type, n-type and degenerately doped semiconductors in the same parent material at the atomically thin limit. In contrast to naturally grown n-type S-vacancy SnS2, Cu intercalated bilayer SnS2 obtained by this technique displays a hole field-effect mobility of 40 cm2 V-1 s-1, and the obtained Co-SnS2 exhibits a metal-like behaviour with sheet resistance comparable to that of few-layer graphene5. Combining this intercalation technique with lithography, an atomically seamless p-n-metal junction could be further realized with precise size and spatial control, which makes in-plane heterostructures practically applicable for integrated devices and other 2D materials. Therefore, the presented intercalation method can open a new avenue connecting the previously disparate worlds of integrated circuits and atomically thin materials.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors.

PubMed

Prezioso, M; Merrikh-Bayat, F; Hoskins, B D; Adam, G C; Likharev, K K; Strukov, D B

2015-05-07

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Proceedings of the Workshop on Compound Semiconductor Devices and Integrated Circuits (13th) Held in Cabourg, France on 10-12 May 1989

DTIC Science & Technology

1989-05-12

USA Resonant tunneling transistors and New III-V memory devices for new circuit architectures with reduced complexity F. Capasso, Bell. Murray Hill...the evaporation, or by selective oxidation of As, leaving metallic Ga clusters and b) the interdiffusive deterioration of metal contacts on GaAs...VEB (My) Resonant Tunneling Transistors and New III-V Memory Devices for New Circuit Architectures with Reduced Complexity . Invited: F. Capasso

Active quench and reset integrated circuit with novel hold-off time control logic for Geiger-mode avalanche photodiodes.

PubMed

Deng, Shijie; Morrison, Alan P

2012-09-15

This Letter presents an active quench-and-reset circuit for Geiger-mode avalanche photodiodes (GM-APDs). The integrated circuit was fabricated using a conventional 0.35 μm complementary metal oxide semiconductor process. Experimental results show that the circuit is capable of linearly setting the hold-off time from several nanoseconds to microseconds with a resolution of 6.5 ns. This allows the selection of the optimal afterpulse-free hold-off time for the GM-APD via external digital inputs or additional signal processing circuitry. Moreover, this circuit resets the APD automatically following the end of the hold-off period, thus simplifying the control for the end user. Results also show that a minimum dead time of 28.4 ns is achieved, demonstrating a saturated photon-counting rate of 35.2 Mcounts/s.

Microwave integrated circuits for space applications

NASA Technical Reports Server (NTRS)

Leonard, Regis F.; Romanofsky, Robert R.

1991-01-01

Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

Design and Fabrication of an Implantable Cortical Semiconductor Integrated Circuit Electrode Array

DTIC Science & Technology

1990-12-01

25 Array Pads....................25 Polyimide ....................26 III. METHODOLOGY.........................27 Brain Chip Electronics...38 Ionic Permeation. .................. 38 Polyimide . ................... 38 Implantation. .................... 39 Wire Bonding...53 Pad Sensitivity ................. 53 Ionic Permeat:.on. .................. 54 Polyimide . ................... 54 Implantation

Improved insulator layer for MIS devices

NASA Technical Reports Server (NTRS)

Miller, W. E.

1980-01-01

Insulating layer of supersonic conductor such as LaF sub 3 has been shown able to impart improved electrical properties to photoconductive detectors and promises to improve other metal/insulator/semiconductor (MIS) devices, e.g., MOSFET and integrated circuits.

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

NASA Technical Reports Server (NTRS)

Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

1996-01-01

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

Micro-fabricated integrated coil and magnetic circuit and method of manufacturing thereof

DOEpatents

Mihailovich, Robert E.; Papavasiliou, Alex P.; Mehrotra, Vivek; Stupar, Philip A.; Borwick, III, Robert L.; Ganguli, Rahul; DeNatale, Jeffrey F.

2017-03-28

A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material.

Uncertain behaviours of integrated circuits improve computational performance.

PubMed

Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

2015-11-20

Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

Quantum cascade lasers grown on silicon.

PubMed

Nguyen-Van, Hoang; Baranov, Alexei N; Loghmari, Zeineb; Cerutti, Laurent; Rodriguez, Jean-Baptiste; Tournet, Julie; Narcy, Gregoire; Boissier, Guilhem; Patriarche, Gilles; Bahriz, Michael; Tournié, Eric; Teissier, Roland

2018-05-08

Technological platforms offering efficient integration of III-V semiconductor lasers with silicon electronics are eagerly awaited by industry. The availability of optoelectronic circuits combining III-V light sources with Si-based photonic and electronic components in a single chip will enable, in particular, the development of ultra-compact spectroscopic systems for mass scale applications. The first circuits of such type were fabricated using heterogeneous integration of semiconductor lasers by bonding the III-V chips onto silicon substrates. Direct epitaxial growth of interband III-V laser diodes on silicon substrates has also been reported, whereas intersubband emitters grown on Si have not yet been demonstrated. We report the first quantum cascade lasers (QCLs) directly grown on a silicon substrate. These InAs/AlSb QCLs grown on Si exhibit high performances, comparable with those of the devices fabricated on their native InAs substrate. The lasers emit near 11 µm, the longest emission wavelength of any laser integrated on Si. Given the wavelength range reachable with InAs/AlSb QCLs, these results open the way to the development of a wide variety of integrated sensors.

High-Speed Binary-Output Image Sensor

NASA Technical Reports Server (NTRS)

Fossum, Eric; Panicacci, Roger A.; Kemeny, Sabrina E.; Jones, Peter D.

1996-01-01

Photodetector outputs digitized by circuitry on same integrated-circuit chip. Developmental special-purpose binary-output image sensor designed to capture up to 1,000 images per second, with resolution greater than 10 to the 6th power pixels per image. Lower-resolution but higher-frame-rate prototype of sensor contains 128 x 128 array of photodiodes on complementary metal oxide/semiconductor (CMOS) integrated-circuit chip. In application for which it is being developed, sensor used to examine helicopter oil to determine whether amount of metal and sand in oil sufficient to warrant replacement.

Foundry fabricated photonic integrated circuit optical phase lock loop.

PubMed

Bałakier, Katarzyna; Fice, Martyn J; Ponnampalam, Lalitha; Graham, Chris S; Wonfor, Adrian; Seeds, Alwyn J; Renaud, Cyril C

2017-07-24

This paper describes the first foundry-based InP photonic integrated circuit (PIC) designed to work within a heterodyne optical phase locked loop (OPLL). The PIC and an external electronic circuit were used to phase-lock a single-line semiconductor laser diode to an incoming reference laser, with tuneable frequency offset from 4 GHz to 12 GHz. The PIC contains 33 active and passive components monolithically integrated on a single chip, fully demonstrating the capability of a generic foundry PIC fabrication model. The electronic part of the OPLL consists of commercially available RF components. This semi-packaged system stabilizes the phase and frequency of the integrated laser so that an absolute frequency, high-purity heterodyne signal can be generated when the OPLL is in operation, with phase noise lower than -100 dBc/Hz at 10 kHz offset from the carrier. This is the lowest phase noise level ever demonstrated by monolithically integrated OPLLs.

Gallium Arsenide Monolithic Optoelectronic Circuits

NASA Astrophysics Data System (ADS)

Bar-Chaim, N.; Katz, J.; Margalit, S.; Ury, I.; Wilt, D.; Yariv, A.

1981-07-01

The optical properties of GaAs make it a very useful material for the fabrication of optical emitters and detectors. GaAs also possesses electronic properties which allow the fabrication of high speed electronic devices which are superior to conventional silicon devices. Monolithic optoelectronic circuits are formed by the integration of optical and electronic devices on a single GaAs substrate. Integration of many devices is most easily accomplished on a semi-insulating (SI) sub-strate. Several laser structures have been fabricated on SI GaAs substrates. Some of these lasers have been integrated with Gunn diodes and with metal semiconductor field effect transistors (MESFETs). An integrated optical repeater has been demonstrated in which MESFETs are used for optical detection and electronic amplification, and a laser is used to regenerate the optical signal. Monolithic optoelectronic circuits have also been constructed on conducting substrates. A heterojunction bipolar transistor driver has been integrated with a laser on an n-type GaAs substrate.

Solar cell circuit and method for manufacturing solar cells

NASA Technical Reports Server (NTRS)

Mardesich, Nick (Inventor)

2010-01-01

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Hybrid integration of III-V semiconductor lasers on silicon waveguides using optofluidic microbubble manipulation

PubMed Central

Jung, Youngho; Shim, Jaeho; Kwon, Kyungmook; You, Jong-Bum; Choi, Kyunghan; Yu, Kyoungsik

2016-01-01

Optofluidic manipulation mechanisms have been successfully applied to micro/nano-scale assembly and handling applications in biophysics, electronics, and photonics. Here, we extend the laser-based optofluidic microbubble manipulation technique to achieve hybrid integration of compound semiconductor microdisk lasers on the silicon photonic circuit platform. The microscale compound semiconductor block trapped on the microbubble surface can be precisely assembled on a desired position using photothermocapillary convective flows induced by focused laser beam illumination. Strong light absorption within the micro-scale compound semiconductor object allows real-time and on-demand microbubble generation. After the assembly process, we verify that electromagnetic radiation from the optically-pumped InGaAsP microdisk laser can be efficiently coupled to the single-mode silicon waveguide through vertical evanescent coupling. Our simple and accurate microbubble-based manipulation technique may provide a new pathway for realizing high precision fluidic assembly schemes for heterogeneously integrated photonic/electronic platforms as well as microelectromechanical systems. PMID:27431769

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

NASA Technical Reports Server (NTRS)

Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

2015-01-01

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

Chip-integrated optical power limiter based on an all-passive micro-ring resonator

NASA Astrophysics Data System (ADS)

Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

2014-10-01

Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

PubMed Central

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

Rapid Selective Annealing of Cu Thin Films on Si Using Microwaves

NASA Technical Reports Server (NTRS)

Brain, R. A.; Atwater, H. A.; Watson, T. J.; Barmatz, M.

1994-01-01

A major goal of the semiconductor indurstry is to lower the processing temperatures needed for interconnects in silicon integrated circuits. Typical rapid thermal annealing processes heat the film as well as the substrate, creating device problems.

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Goals, achievements of microelectronics program

NASA Astrophysics Data System (ADS)

Schronk, L.

1985-05-01

Besides reviewing the objectives of the government's microelectronics program, the Microelectronics Enterprise, the production of metal oxide semiconductors and bipolar integrated-circuit chips, specific research and development results to date, and the plans for future activity are discussed. Marketing and domestic demand are discussed.

Over-voltage protection system and method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chi, Song; Dong, Dong; Lai, Rixin

An over-voltage protection system includes an electronic valve connected across two terminals of a circuit and an over-voltage detection circuit connected across one of the plurality of semiconductor devices for detecting an over-voltage across the circuit. The electronic valve includes a plurality of semiconductor devices connected in series. The over-voltage detection circuit includes a voltage divider circuit connected to a break-over diode in a way to provide a representative low voltage to the break-over diode and an optocoupler configured to receive a current from the break-over diode when the representative low voltage exceeds a threshold voltage of the break-over diodemore » indicating an over-voltage condition. The representative low voltage provided to the break-over diode represents a voltage across the one semiconductor device. A plurality of self-powered gate drive circuits are connected to the plurality of semiconductor devices, wherein the plurality of self-powered gate drive circuits receive over-voltage triggering pulses from the optocoupler during the over-voltage condition and switch on the plurality of semiconductor devices to bypass the circuit.« less

Plasmonic integrated circuits comprising metal waveguides, multiplexer/demultiplexer, detectors, and logic circuits on a silicon substrate

NASA Astrophysics Data System (ADS)

Fukuda, M.; Ota, M.; Sumimura, A.; Okahisa, S.; Ito, M.; Ishii, Y.; Ishiyama, T.

2017-05-01

A plasmonic integrated circuit configuration comprising plasmonic and electronic components is presented and the feasibility for high-speed signal processing applications is discussed. In integrated circuits, plasmonic signals transmit data at high transfer rates with light velocity. Plasmonic and electronic components such as wavelength-divisionmultiplexing (WDM) networks comprising metal wires, plasmonic multiplexers/demultiplexers, and crossing metal wires are connected via plasmonic waveguides on the nanometer or micrometer scales. To merge plasmonic and electronic components, several types of plasmonic components were developed. To ensure that the plasmonic components could be easily fabricated and monolithically integrated onto a silicon substrate using silicon complementary metal-oxide-semiconductor (CMOS)-compatible processes, the components were fabricated on a Si substrate and made from silicon, silicon oxides, and metal; no other materials were used in the fabrication. The plasmonic components operated in the 1300- and 1550-nm-wavelength bands, which are typically employed in optical fiber communication systems. The plasmonic logic circuits were formed by patterning a silicon oxide film on a metal film, and the operation as a half adder was confirmed. The computed plasmonic signals can propagate through the plasmonic WDM networks and be connected to electronic integrated circuits at high data-transfer rates.

Late Quaternary to Holocene Geology, Geomorphology and Glacial History of Dawson Creek and Surrounding area, Northeast British Columbia, Canada

NASA Astrophysics Data System (ADS)

Henry, Edward Trowbridge

Semiconductor quantum dots in silicon demonstrate exceptionally long spin lifetimes as qubits and are therefore promising candidates for quantum information processing. However, control and readout techniques for these devices have thus far employed low frequency electrons, in contrast to high speed temperature readout techniques used in other qubit architectures, and coupling between multiple quantum dot qubits has not been satisfactorily addressed. This dissertation presents the design and characterization of a semiconductor charge qubit based on double quantum dot in silicon with an integrated microwave resonator for control and readout. The 6 GHz resonator is designed to achieve strong coupling with the quantum dot qubit, allowing the use of circuit QED control and readout techniques which have not previously been applicable to semiconductor qubits. To achieve this coupling, this document demonstrates successful operation of a novel silicon double quantum dot design with a single active metallic layer and a coplanar stripline resonator with a bias tee for dc excitation. Experiments presented here demonstrate quantum localization and measurement of both electrons on the quantum dot and photons in the resonator. Further, it is shown that the resonator-qubit coupling in these devices is sufficient to reach the strong coupling regime of circuit QED. The details of a measurement setup capable of performing simultaneous low noise measurements of the resonator and quantum dot structure are also presented here. The ultimate aim of this research is to integrate the long coherence times observed in electron spins in silicon with the sophisticated readout architectures available in circuit QED based quantum information systems. This would allow superconducting qubits to be coupled directly to semiconductor qubits to create hybrid quantum systems with separate quantum memory and processing components.

Improved Photon-Emission-Microscope System

NASA Technical Reports Server (NTRS)

Vu, Duc

2006-01-01

An improved photon-emission-microscope (PEM) instrumentation system has been developed for use in diagnosing failure conditions in semiconductor devices, including complex integrated circuits. This system is designed primarily to image areas that emit photons, at wavelengths from 400 to 1,100 nm, associated with device failures caused by leakage of electric current through SiO2 and other dielectric materials used in multilayer semiconductor structures. In addition, the system is sensitive enough to image areas that emit photons during normal operation.

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

NASA Technical Reports Server (NTRS)

Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

2009-01-01

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

Method for deposition of a conductor in integrated circuits

DOEpatents

Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

1997-01-01

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

Walk-through survey report: Control technology for integrated circuit fabrication, Xerox Corporation, El Segundo, California

NASA Astrophysics Data System (ADS)

Mihlan, G. J.; Ungers, L. J.; Smith, R. K.; Mitchell, R. I.; Jones, J. H.

1983-05-01

A preliminary control technology assessment survey was conducted at the facility which manufactures N-channel metal oxide semiconductor (NMOS) integrated circuits. The facility has industrial hygiene review procedures for evaluating all new and existing process equipment. Employees are trained in safety, use of personal protective equipment, and emergency response. Workers potentially exposed to arsenic are monitored for urinary arsenic levels. The facility should be considered a candidate for detailed study based on the diversity of process operations encountered and the use of state-of-the-art technology and process equipment.

Optical-Interferometry-Based CMOS-MEMS Sensor Transduced by Stress-Induced Nanomechanical Deflection

PubMed Central

Maruyama, Satoshi; Hizawa, Takeshi; Takahashi, Kazuhiro; Sawada, Kazuaki

2018-01-01

We developed a Fabry–Perot interferometer sensor with a metal-oxide-semiconductor field-effect transistor (MOSFET) circuit for chemical sensing. The novel signal transducing technique was performed in three steps: mechanical deflection, transmittance change, and photocurrent change. A small readout photocurrent was processed by an integrated source follower circuit. The movable film of the sensor was a 350-nm-thick polychloro-para-xylylene membrane with a diameter of 100 µm and an air gap of 300 nm. The linearity of the integrated source follower circuit was obtained. We demonstrated a gas response using 80-ppm ethanol detected by small membrane deformation of 50 nm, which resulted in an output-voltage change with the proposed high-efficiency transduction. PMID:29304011

Optical-Interferometry-Based CMOS-MEMS Sensor Transduced by Stress-Induced Nanomechanical Deflection.

PubMed

Maruyama, Satoshi; Hizawa, Takeshi; Takahashi, Kazuhiro; Sawada, Kazuaki

2018-01-05

We developed a Fabry-Perot interferometer sensor with a metal-oxide-semiconductor field-effect transistor (MOSFET) circuit for chemical sensing. The novel signal transducing technique was performed in three steps: mechanical deflection, transmittance change, and photocurrent change. A small readout photocurrent was processed by an integrated source follower circuit. The movable film of the sensor was a 350-nm-thick polychloro-para-xylylene membrane with a diameter of 100 µm and an air gap of 300 nm. The linearity of the integrated source follower circuit was obtained. We demonstrated a gas response using 80-ppm ethanol detected by small membrane deformation of 50 nm, which resulted in an output-voltage change with the proposed high-efficiency transduction.

CMOS-micromachined, two-dimenisional transistor arrays for neural recording and stimulation.

PubMed

Lin, J S; Chang, S R; Chang, C H; Lu, S C; Chen, H

2007-01-01

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die-level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

77 FR 64826 - Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-10-23

...: Realtek Semiconductor Corporation 2 Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan. (b) The... notice to the respondent, to find the facts to be as alleged in the complaint and this notice and to...

SRC: A Model of Industry-University Cooperation.

ERIC Educational Resources Information Center

Cavin, Ralph K., III; Phillips, D. Howard

1988-01-01

Describes the Semiconductor Research Corporation (SRC), a non-profit research cooperative designed to conduct research in the field of integrated circuits, principally in U.S. universities, with membership restricted to U.S.-owned companies. Analyzes SRC's impact on the U.S. educational system. (TW)

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

PubMed

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-12-02

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

PubMed

Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

2010-01-01

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e(-) for the simple integration CMS and 75 dB and 2.2 e(-) for the folding integration CMS, respectively, are obtained.

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.

PubMed

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries.

Semiconductor Metal-Organic Frameworks: Future Low-Bandgap Materials.

PubMed

Usman, Muhammad; Mendiratta, Shruti; Lu, Kuang-Lieh

2017-02-01

Metal-organic frameworks (MOFs) with low density, high porosity, and easy tunability of functionality and structural properties, represent potential candidates for use as semiconductor materials. The rapid development of the semiconductor industry and the continuous miniaturization of feature sizes of integrated circuits toward the nanometer (nm) scale require novel semiconductor materials instead of traditional materials like silicon, germanium, and gallium arsenide etc. MOFs with advantageous properties of both the inorganic and the organic components promise to serve as the next generation of semiconductor materials for the microelectronics industry with the potential to be extremely stable, cheap, and mechanically flexible. Here, a perspective of recent research is provided, regarding the semiconducting properties of MOFs, bandgap studies, and their potential in microelectronic devices. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

PubMed

McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

2017-03-28

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Topics investigated include: measurements of transistor delay time; application of the infrared response technique to the study of radiation-damaged, lithium-drifted silicon detectors; and identification of a condition that minimizes wire flexure and reduces the failure rate of wire bonds in transistors and integrated circuits under slow thermal cycling conditions. Supplementary data concerning staff, standards committee activities, technical services, and publications are included as appendixes.

Development of standardized specifications for screening space level integrated circuits and semiconductors

NASA Technical Reports Server (NTRS)

1984-01-01

Standardized methods are established for screening of JAN B microcircuits and JANTXV semiconductor components for space mission or other critical applications when JAN S devices are not available. General specifications are provided which outline the DPA (destructive physical analysis), environmental, electrical, and data requirements for screening of various component technologies. This standard was developed for Air Force Space Division, and is available for use by other DOD agencies, NASA, and space systems contractors for establishing common screening methods for electronic components.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

PubMed Central

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-01-01

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

PubMed

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-10-25

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures.

PubMed

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng; Zhou, Peng

2018-04-01

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS 2 /GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

PubMed

Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

2016-01-21

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

PubMed Central

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng

2018-01-01

Abstract 2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field‐effect transistors. However, 2DLM‐based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS2/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM‐based integrated circuits based on amplifier circuits. PMID:29721428

Triple inverter pierce oscillator circuit suitable for CMOS

DOEpatents

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

PubMed Central

Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

2017-01-01

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors. PMID:28368355

Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-10-28

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems.

PubMed

Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

2017-04-03

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

All-optical differential equation solver with constant-coefficient tunable based on a single microring resonator.

PubMed

Yang, Ting; Dong, Jianji; Lu, Liangjun; Zhou, Linjie; Zheng, Aoling; Zhang, Xinliang; Chen, Jianping

2014-07-04

Photonic integrated circuits for photonic computing open up the possibility for the realization of ultrahigh-speed and ultra wide-band signal processing with compact size and low power consumption. Differential equations model and govern fundamental physical phenomena and engineering systems in virtually any field of science and engineering, such as temperature diffusion processes, physical problems of motion subject to acceleration inputs and frictional forces, and the response of different resistor-capacitor circuits, etc. In this study, we experimentally demonstrate a feasible integrated scheme to solve first-order linear ordinary differential equation with constant-coefficient tunable based on a single silicon microring resonator. Besides, we analyze the impact of the chirp and pulse-width of input signals on the computing deviation. This device can be compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may motivate the development of integrated photonic circuits for optical computing.

All-optical differential equation solver with constant-coefficient tunable based on a single microring resonator

PubMed Central

Yang, Ting; Dong, Jianji; Lu, Liangjun; Zhou, Linjie; Zheng, Aoling; Zhang, Xinliang; Chen, Jianping

2014-01-01

Photonic integrated circuits for photonic computing open up the possibility for the realization of ultrahigh-speed and ultra wide-band signal processing with compact size and low power consumption. Differential equations model and govern fundamental physical phenomena and engineering systems in virtually any field of science and engineering, such as temperature diffusion processes, physical problems of motion subject to acceleration inputs and frictional forces, and the response of different resistor-capacitor circuits, etc. In this study, we experimentally demonstrate a feasible integrated scheme to solve first-order linear ordinary differential equation with constant-coefficient tunable based on a single silicon microring resonator. Besides, we analyze the impact of the chirp and pulse-width of input signals on the computing deviation. This device can be compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may motivate the development of integrated photonic circuits for optical computing. PMID:24993440

Soviet Cybernetics Review, Volume 3, Number 11.

ERIC Educational Resources Information Center

Holland, Wade B.

Soviet efforts in designing third-generation computers are discussed in two featured articles which describe (1) the development and production of integrated circuits, and their role in computers; and (2) the use of amorphous chalcogenide glass in lasers, infrared devices, and semiconductors. Other articles discuss production-oriented branch…

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Monolithically integrated solid state laser and waveguide using spin-on glass

DOEpatents

Ashby, C.I.H.; Hohimer, J.P.; Neal, D.R.; Vawter, G.A.

1995-10-31

A monolithically integrated photonic circuit is disclosed combining a semiconductor source of excitation light with an optically active waveguide formed on the substrate. The optically active waveguide is preferably formed of a spin-on glass to which are added optically active materials which can enable lasing action, optical amplification, optical loss, or frequency conversion in the waveguide, depending upon the added material. 4 figs.

A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2011-01-01

A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

NASA Astrophysics Data System (ADS)

Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

Using NCAP to predict RFI effects in linear bipolar integrated circuits

NASA Astrophysics Data System (ADS)

Fang, T.-F.; Whalen, J. J.; Chen, G. K. C.

1980-11-01

Applications of the Nonlinear Circuit Analysis Program (NCAP) to calculate RFI effects in electronic circuits containing discrete semiconductor devices have been reported upon previously. The objective of this paper is to demonstrate that the computer program NCAP also can be used to calcuate RFI effects in linear bipolar integrated circuits (IC's). The IC's reported upon are the microA741 operational amplifier (op amp) which is one of the most widely used IC's, and a differential pair which is a basic building block in many linear IC's. The microA741 op amp was used as the active component in a unity-gain buffer amplifier. The differential pair was used in a broad-band cascode amplifier circuit. The computer program NCAP was used to predict how amplitude-modulated RF signals are demodulated in the IC's to cause undesired low-frequency responses. The predicted and measured results for radio frequencies in the 0.050-60-MHz range are in good agreement.

Silicon Satellites: Picosats, Nanosats, and Microsats

NASA Technical Reports Server (NTRS)

Janson, Siegfried W.

1995-01-01

Silicon, the most abundant solid element in the Earth's lithosphere, is a useful material for spacecraft construction. Silicon is stronger than stainless steel, has a thermal conductivity about half that of aluminum, is transparent to much of the infrared radiation spectrum, and can form a stable oxide. These unique properties enable silicon to become most of the mass of a satellite, it can simultaneously function as structure, heat transfer system, radiation shield, optics, and semiconductor substrate. Semiconductor batch-fabrication techniques can produce low-power digital circuits, low-power analog circuits, silicon-based radio frequency circuits, and micro-electromechanical systems (MEMS) such as thrusters and acceleration sensors on silicon substrates. By exploiting these fabrication techniques, it is possible to produce highly-integrated satellites for a number of applications. This paper analyzes the limitations of silicon satellites due to size. Picosatellites (approximately 1 gram mass), nanosatellites (about 1 kg mass), and highly capable microsatellites (about 10 kg mass) can perform various missions with lifetimes of a few days to greater than a decade.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Method for deposition of a conductor in integrated circuits

DOEpatents

Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

1997-09-02

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

NASA Astrophysics Data System (ADS)

Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

2017-07-01

Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

Nanoionics-Based Switches for Radio-Frequency Applications

NASA Technical Reports Server (NTRS)

Nessel, James; Lee, Richard

2010-01-01

Nanoionics-based devices have shown promise as alternatives to microelectromechanical systems (MEMS) and semiconductor diode devices for switching radio-frequency (RF) signals in diverse systems. Examples of systems that utilize RF switches include phase shifters for electronically steerable phased-array antennas, multiplexers, cellular telephones and other radio transceivers, and other portable electronic devices. Semiconductor diode switches can operate at low potentials (about 1 to 3 V) and high speeds (switching times of the order of nanoseconds) but are characterized by significant insertion loss, high DC power consumption, low isolation, and generation of third-order harmonics and intermodulation distortion (IMD). MEMS-based switches feature low insertion loss (of the order of 0.2 dB), low DC power consumption (picowatts), high isolation (>30 dB), and low IMD, but contain moving parts, are not highly reliable, and must be operated at high actuation potentials (20 to 60 V) generated and applied by use of complex circuitry. In addition, fabrication of MEMS is complex, involving many processing steps. Nanoionics-based switches offer the superior RF performance and low power consumption of MEMS switches, without need for the high potentials and complex circuitry necessary for operation of MEMS switches. At the same time, nanoionics-based switches offer the high switching speed of semiconductor devices. Also, like semiconductor devices, nanoionics-based switches can be fabricated relatively inexpensively by use of conventional integrated-circuit fabrication techniques. More over, nanoionics-based switches have simple planar structures that can easily be integrated into RF power-distribution circuits.

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Materials-Process Interactions in Ternary Alloy Semiconductors.

DTIC Science & Technology

1984-08-01

high, the surface potential can be * modulated . PECVD SiO. appears to be a viable candidate as a gate dielectric for * Irf ,fO-4A)s MISFETs...it is desirable to integrate the detectors with circuits capable of performing signal processing functions. These circuits can either be fabricated in...to be a major problem in In0. 5 3Ga 0.* 47 s. 25 S. . . . . 13821 -1 R I (a) CROSS SECTION KEYBOARD 210M ANNEALING CHAMBER GATE TRIGG TRIAC

Plasma chemistry and its applications

NASA Technical Reports Server (NTRS)

Hozumi, K.

1980-01-01

The relationship between discharge phenomena and plasma chemistry, as well as the equipment and mechanisms of plasma chemical reactions are described. Various areas in which plasma chemistry is applied are surveyed, such as: manufacturing of semiconductor integrated circuits; synthetic fibers; high polymer materials for medical uses; optical lenses; and membrane filters (reverse penetration films).

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

Interface design for CMOS-integrated Electrochemical Impedance Spectroscopy (EIS) biosensors.

PubMed

Manickam, Arun; Johnson, Christopher Andrew; Kavusi, Sam; Hassibi, Arjang

2012-10-29

Electrochemical Impedance Spectroscopy (EIS) is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs) that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

NASA Astrophysics Data System (ADS)

Doering, Robert

In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

Synchronized conductivity modulation to realize broadband lossless magnetic-free non-reciprocity.

PubMed

Dinc, Tolga; Tymchenko, Mykhailo; Nagulu, Aravind; Sounas, Dimitrios; Alu, Andrea; Krishnaswamy, Harish

2017-10-06

Recent research has explored the spatiotemporal modulation of permittivity to break Lorentz reciprocity in a manner compatible with integrated-circuit fabrication. However, permittivity modulation is inherently weak and accompanied by loss due to carrier injection, particularly at higher frequencies, resulting in large insertion loss, size, and/or narrow operation bandwidths. Here, we show that the presence of absorption in an integrated electronic circuit may be counter-intuitively used to our advantage to realize a new generation of magnet-free non-reciprocal components. We exploit the fact that conductivity in semiconductors provides a modulation index several orders of magnitude larger than permittivity. While directly associated with loss in static systems, we show that properly synchronized conductivity modulation enables loss-free, compact and extremely broadband non-reciprocity. We apply these concepts to obtain a wide range of responses, from isolation to gyration and circulation, and verify our findings by realizing a millimeter-wave (25 GHz) circulator fully integrated in complementary metal-oxide-semiconductor technology.Optical non-reciprocity achieved through refractive index modulation can have its challenges and limitations. Here, Dinc et al. introduce the concept of non-reciprocity based on synchronized spatio-temporal modulation of conductivity to achieve different types of non-reciprocal functionality.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations

PubMed Central

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

2008-01-01

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ≈1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ≈140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

IIIV/Si Nanoscale Lasers and Their Integration with Silicon Photonics

NASA Astrophysics Data System (ADS)

Bondarenko, Olesya

The rapidly evolving global information infrastructure requires ever faster data transfer within computer networks and stations. Integrated chip scale photonics can pave the way to accelerated signal manipulation and boost bandwidth capacity of optical interconnects in a compact and ergonomic arrangement. A key building block for integrated photonic circuits is an on-chip laser. In this dissertation we explore ways to reduce the physical footprint of semiconductor lasers and make them suitable for high density integration on silicon, a standard material platform for today's integrated circuits. We demonstrated the first room temperature metalo-dielectric nanolaser, sub-wavelength in all three dimensions. Next, we demonstrated a nanolaser on silicon, showing the feasibility of its integration with this platform. We also designed and realized an ultracompact feedback laser with edge-emitting structure, amenable for in-plane coupling with a standard silicon waveguide. Finally, we discuss the challenges and propose solutions for improvement of the device performance and practicality.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

Subwavelength InSb-based Slot wavguides for THz transport: concept and practical implementations.

PubMed

Ma, Youqiao; Zhou, Jun; Pištora, Jaromír; Eldlio, Mohamed; Nguyen-Huu, Nghia; Maeda, Hiroshi; Wu, Qiang; Cada, Michael

2016-12-07

Seeking better surface plasmon polariton (SPP) waveguides is of critical importance to construct the frequency-agile terahertz (THz) front-end circuits. We propose and investigate here a new class of semiconductor-based slot plasmonic waveguides for subwavelength THz transport. Optimizations of the key geometrical parameters demonstrate its better guiding properties for simultaneous realization of long propagation lengths (up to several millimeters) and ultra-tight mode confinement (~λ 2 /530) in the THz spectral range. The feasibility of the waveguide for compact THz components is also studied to lay the foundations for its practical implementations. Importantly, the waveguide is compatible with the current complementary metal-oxide-semiconductor (CMOS) fabrication technique. We believe the proposed waveguide configuration could offer a potential for developing a CMOS plasmonic platform and can be designed into various components for future integrated THz circuits (ITCs).

Optical XOR gate

DOEpatents

Vawter, G. Allen

2013-11-12

An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Total-dose radiation effects data for semiconductor devices: 1985 supplement, volume 1

NASA Technical Reports Server (NTRS)

Martin, K. E.; Gauthier, M. K.; Coss, J. R.; Dantas, A. R. V.; Price, W. E.

1985-01-01

Steady-state, total-dose radiation test data are provided, in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 provides total-dose radiation test data on integrated circuits. Volume 1 of this 1985 Supplement contains new total-dose radiation test data generated since the August 1, 1981 release date of the original Volume 1. Publication of Volume 2 of the 1985 Supplement will follow that of Volume 1 by approximately three months.

Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

DOEpatents

Rogers, John A; Meitl, Matthew; Sun, Yugang; Ko, Heung Cho; Carlson, Andrew; Choi, Won Mook; Stoykovich, Mark; Jiang, Hanqing; Huang, Yonggang; Nuzzo, Ralph G; Zhu, Zhengtao; Menard, Etienne; Khang, Dahl-Young

2014-05-20

In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

DOEpatents

Rogers, John A [Champaign, IL; Meitl, Matthew [Raleigh, NC; Sun, Yugang [Naperville, IL; Ko, Heung Cho [Urbana, IL; Carlson, Andrew [Urbana, IL; Choi, Won Mook [Champaign, IL; Stoykovich, Mark [Dover, NH; Jiang, Hanqing [Urbana, IL; Huang, Yonggang [Glencoe, IL; Nuzzo, Ralph G [Champaign, IL; Lee, Keon Jae [Tokyo, JP; Zhu, Zhengtao [Rapid City, SD; Menard, Etienne [Durham, NC; Khang, Dahl-Young [Seoul, KR; Kan, Seong Jun [Daejeon, KR; Ahn, Jong Hyun [Suwon, KR; Kim, Hoon-sik [Champaign, IL

2012-07-10

In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

Implementation of an integrated op-amp based chaotic neuron model and observation of its chaotic dynamics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jung, Jinwoo; Lee, Jewon; Song, Hanjung

2011-03-15

This paper presents a fully integrated circuit implementation of an operational amplifier (op-amp) based chaotic neuron model with a bipolar output function, experimental measurements, and analyses of its chaotic behavior. The proposed chaotic neuron model integrated circuit consists of several op-amps, sample and hold circuits, a nonlinear function block for chaotic signal generation, a clock generator, a nonlinear output function, etc. Based on the HSPICE (circuit program) simulation results, approximated empirical equations for analyses were formulated. Then, the chaotic dynamical responses such as bifurcation diagrams, time series, and Lyapunov exponent were calculated using these empirical equations. In addition, we performedmore » simulations about two chaotic neuron systems with four synapses to confirm neural network connections and got normal behavior of the chaotic neuron such as internal state bifurcation diagram according to the synaptic weight variation. The proposed circuit was fabricated using a 0.8-{mu}m single poly complementary metal-oxide semiconductor technology. Measurements of the fabricated single chaotic neuron with {+-}2.5 V power supplies and a 10 kHz sampling clock frequency were carried out and compared with the simulated results.« less

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

Modelling of optoelectronic circuits based on resonant tunneling diodes

NASA Astrophysics Data System (ADS)

Rei, João. F. M.; Foot, James A.; Rodrigues, Gil C.; Figueiredo, José M. L.

2017-08-01

Resonant tunneling diodes (RTDs) are the fastest pure electronic semiconductor devices at room temperature. When integrated with optoelectronic devices they can give rise to new devices with novel functionalities due to their highly nonlinear properties and electrical gain, with potential applications in future ultra-wide-band communication systems (see e.g. EU H2020 iBROW Project). The recent coverage on these devices led to the need to have appropriated simulation tools. In this work, we present RTD based optoelectronic circuits simulation packages to provide circuit signal level analysis such as transient and frequency responses. We will present and discuss the models, and evaluate the simulation packages.

Associative Pattern Recognition In Analog VLSI Circuits

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1995-01-01

Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.;

Programmable resistive-switch nanowire transistor logic circuits.

PubMed

Shim, Wooyoung; Yao, Jun; Lieber, Charles M

2014-09-10

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

Technological and organizational diversity and technical advance in the early history of the American semiconductor industry

NASA Astrophysics Data System (ADS)

Cohen, W.; Holbrook, D.; Klepper, S.

1994-06-01

This study examines the early years of the semiconductor industry and focuses on the roles played by different size firms in technologically innovative processes. A large and diverse pool of firms participated in the growth of the industry. Three related technological areas were chosen for in-depth analysis: integrated circuits, materials technology, and device packaging. Large business producing vacuum tubes dominated the early production of semiconductor devices. As the market for new devices grew during the 1950's, new firms were founded and existing firms from other industries, e.g. aircraft builders and instrument makers, began to pursue semiconductor electronics. Small firms began to cater to the emerging industry by supplying materials and equipment. These firms contributed to the development of certain aspects of one thousand firms that were playing some part in the semiconductor industry.

Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

DOEpatents

Welch, James D.

2000-01-01

Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

High-resolution inkjet printing of all-polymer transistor circuits.

PubMed

Sirringhaus, H; Kawase, T; Friend, R H; Shimoda, T; Inbasekaran, M; Wu, W; Woo, E P

2000-12-15

Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and self-organizing semiconductors. We show that the use of substrate surface energy patterning to direct the flow of water-based conducting polymer inkjet droplets enables high-resolution definition of practical channel lengths of 5 micrometers. High mobilities of 0.02 square centimeters per volt second and on-off current switching ratios of 10(5) were achieved.

A Solder Based Self Assembly Project in an Introductory IC Fabrication Course

ERIC Educational Resources Information Center

Rao, Madhav; Lusth, John C.; Burkett, Susan L.

2015-01-01

Integrated circuit (IC) fabrication principles is an elective course in a senior undergraduate and early graduate student's curriculum. Over the years, the semiconductor industry relies heavily on students with developed expertise in the area of fabrication techniques, learned in an IC fabrication theory and laboratory course. The theory course…

77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-07-03

..., 500 E Street SW., Washington, DC 20436, telephone (202) 708-2301. Copies of non- confidential... Commission, 500 E Street SW., Washington, DC 20436, telephone (202) 205-2000. General information concerning... Rules of Practice and Procedure (19 CFR 210.42). By order of the Commission. Issued: June 27, 2012. Lisa...

Heterogeneous integration of low-temperature metal-oxide TFTs

NASA Astrophysics Data System (ADS)

Schuette, Michael L.; Green, Andrew J.; Leedy, Kevin D.; McCandless, Jonathan P.; Jessen, Gregg H.

2017-02-01

The breadth of circuit fabrication opportunities enabled by metal-oxide thin-film transistors (MO-TFTs) is unprecedented. Large-area deposition techniques and high electron mobility are behind their adoption in the display industry, and substrate agnosticism and low process temperatures enabled the present wave of flexible electronics research. Reports of circuits involving complementaryMO-TFTs, oxide-organic hybrid combinations, and even MO-TFTs integrated onto Si LSI back end of line interconnects demonstrate this technology's utility in 2D and 3D monolithic heterogeneous integration (HI). In addition to a brief literature review focused on functional HI between MO-TFTs and a variety of dissimilar active devices, we share progress toward integrating MO-TFTs with compound semiconductor devices, namely GaN HEMTs. A monolithically integrated cascode topology was used to couple a HEMT's >200 V breakdown characteristic with the gate driving characteristic of an IGZO TFT, effectively shifting the HEMT threshold voltage from -3 V to +1 V.

A fast low-power optical memory based on coupled micro-ring lasers

NASA Astrophysics Data System (ADS)

Hill, Martin T.; Dorren, Harmen J. S.; de Vries, Tjibbe; Leijtens, Xaveer J. M.; den Besten, Jan Hendrik; Smalbrugge, Barry; Oei, Yok-Siang; Binsma, Hans; Khoe, Giok-Djan; Smit, Meint K.

2004-11-01

The increasing speed of fibre-optic-based telecommunications has focused attention on high-speed optical processing of digital information. Complex optical processing requires a high-density, high-speed, low-power optical memory that can be integrated with planar semiconductor technology for buffering of decisions and telecommunication data. Recently, ring lasers with extremely small size and low operating power have been made, and we demonstrate here a memory element constructed by interconnecting these microscopic lasers. Our device occupies an area of 18 × 40µm2 on an InP/InGaAsP photonic integrated circuit, and switches within 20ps with 5.5fJ optical switching energy. Simulations show that the element has the potential for much smaller dimensions and switching times. Large numbers of such memory elements can be densely integrated and interconnected on a photonic integrated circuit: fast digital optical information processing systems employing large-scale integration should now be viable.

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Beheim, Glenn M.; Okojie, Robert S.; Chang, Carl W.; Meredith, Roger D.; Ferrier, Terry L.; Evans, Laura J.; Krasowski, Michael J.;

Photonic integrated circuits unveil crisis-induced intermittency.

PubMed

Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

2016-09-19

We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

SEM analysis of ionizing radiation effects in linear integrated circuits. [Scanning Electron Microscope

NASA Technical Reports Server (NTRS)

Stanley, A. G.; Gauthier, M. K.

1977-01-01

A successful diagnostic technique was developed using a scanning electron microscope (SEM) as a precision tool to determine ionization effects in integrated circuits. Previous SEM methods radiated the entire semiconductor chip or major areas. The large area exposure methods do not reveal the exact components which are sensitive to radiation. To locate these sensitive components a new method was developed, which consisted in successively irradiating selected components on the device chip with equal doses of electrons /10 to the 6th rad (Si)/, while the whole device was subjected to representative bias conditions. A suitable device parameter was measured in situ after each successive irradiation with the beam off.

A molybdenum disulfide/carbon nanotube heterogeneous complementary inverter.

PubMed

Huang, Jun; Somu, Sivasubramanian; Busnaina, Ahmed

2012-08-24

We report a simple, bottom-up/top-down approach for integrating drastically different nanoscale building blocks to form a heterogeneous complementary inverter circuit based on layered molybdenum disulfide and carbon nanotube (CNT) bundles. The fabricated CNT/MoS(2) inverter is composed of n-type molybdenum disulfide (MOS(2)) and p-type CNT transistors, with a high voltage gain of 1.3. The CNT channels are fabricated using directed assembly while the layered molybdenum disulfide channels are fabricated by mechanical exfoliation. This bottom-up fabrication approach for integrating various nanoscale elements with unique characteristics provides an alternative cost-effective methodology to complementary metal-oxide-semiconductors, laying the foundation for the realization of high performance logic circuits.

Prototype AEGIS: A Pixel-Array Readout Circuit for Gamma-Ray Imaging.

PubMed

Barber, H Bradford; Augustine, F L; Furenlid, L; Ingram, C M; Grim, G P

2005-07-31

Semiconductor detector arrays made of CdTe/CdZnTe are expected to be the main components of future high-performance, clinical nuclear medicine imaging systems. Such systems will require small pixel-pitch and much larger numbers of pixels than are available in current semiconductor-detector cameras. We describe the motivation for developing a new readout integrated circuit, AEGIS, for use in hybrid semiconductor detector arrays, that may help spur the development of future cameras. A basic design for AEGIS is presented together with results of an HSPICE ™ simulation of the performance of its unit cell. AEGIS will have a shaper-amplifier unit cell and neighbor pixel readout. Other features include the use of a single input power line with other biases generated on-board, a control register that allows digital control of all thresholds and chip configurations and an output approach that is compatible with list-mode data acquisition. An 8×8 prototype version of AEGIS is currently under development; the full AEGIS will be a 64×64 array with 300 μm pitch.

Investigation of Radiation Effects on Semiconductor Devices and Integrated Circuits

DTIC Science & Technology

1988-09-16

qualitativelysimilar to, and consistent with, findings at the two higher energies .) Results for irradiation of eightwhere q is the electronic charge, ni is the...COMMUNICATIONS R&D COMMAND ATTN: R BROWN ASSISTANT TO THE SECRETARY OF DEFENSE ATOMIC ENERGY U S ARMY ELECTRONIC TECH DEV LAB ATTN: EXECUTIVE ASSISTANT...Continue on reverse if necessary and identify by block number) Results of a study of radiation effects on electronic materials, devices, and integrated

Porous Diblock Copolymer Thin Films in High-Performance Semiconductor Microelectronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, C.T.

2011-02-01

The engine fueling more than 40 years of performance improvements in semiconductor integrated circuits (ICs) has been industry's ability to pattern circuit elements at ever-higher resolution and with ever-greater precision. Steady advances in photolithography - the process wherein ultraviolet light chemically changes a photosensitive polymer resist material in order to create a latent image - have resulted in scaling of minimum printed feature sizes from tens of microns during the 1980s to sub-50 nanometer transistor gate lengths in today's state-of-the-art ICs. The history of semiconductor technology scaling as well as future technology requirements is documented in the International Technology Roadmapmore » for Semiconductors (ITRS). The progression of the semiconductor industry to the realm of nanometer-scale sizes has brought enormous challenges to device and circuit fabrication, rendering performance improvements by conventional scaling alone increasingly difficult. Most often this discussion is couched in terms of field effect transistor (FET) feature sizes such as the gate length or gate oxide thickness, however these challenges extend to many other aspects of the IC, including interconnect dimensions and pitch, device packing density, power consumption, and heat dissipation. The ITRS Technology Roadmap forecasts a difficult set of scientific and engineering challenges with no presently-known solutions. The primary focus of this chapter is the research performed at IBM on diblock copolymer films composed of polystyrene (PS) and poly(methyl-methacrylate) (PMMA) (PS-b-PMMA) with total molecular weights M{sub n} in the range of {approx}60K (g/mol) and polydispersities (PD) of {approx}1.1. These materials self assemble to form patterns having feature sizes in the range of 15-20nm. PS-b-PMMA was selected as a self-assembling patterning material due to its compatibility with the semiconductor microelectronics manufacturing infrastructure, as well as the significant body of existing research on understanding its material properties.« less

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip

PubMed Central

Schuck, C.; Guo, X.; Fan, L.; Ma, X.; Poot, M.; Tang, H. X.

2016-01-01

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips. PMID:26792424

Development of a unit cell for a Ge:Ga detector array

NASA Technical Reports Server (NTRS)

1988-01-01

Two modules of gallium-doped germanium (Ge:Ga) infrared detectors with integrated multiplexing readouts and supporting drive electronics were designed and tested. This development investigated the feasibility of producing two-dimensional Ge:Ga arrays by stacking linear modules in a housing capable of providing uniaxial stress for enhanced long-wavelength response. Each module includes 8 detectors (1x1x2 mm) mounted to a sapphire board. The element spacing is 12 microns. The back faces of the detector elements are beveled with an 18 deg angle, which was proved to significantly enhance optical absorption. Each module includes a different silicon metal-oxide semiconductor field effect transistor (MOSFET) readout. The first circuit was built from discrete MOSFET components; the second incorporated devices taken from low-temperature integrated circuit multiplexers. The latter circuit exhibited much lower stray capacitance and improved stability. Using these switched-FET circuits, it was demonstrated that burst readout, with multiplexer active only during the readout period, could successfully be implemented at approximately 3.5 K.

An ultra low-power CMOS automatic action potential detector.

PubMed

Gosselin, Benoit; Sawan, Mohamad

2009-08-01

We present a low-power complementary metal-oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- microm chip dissipates 780 nW, and it features a size of 0.07 mm(2). So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.

Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-01-01

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90 %RH. PMID:25353984

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Noise and linearity optimization methods for a 1.9GHz low noise amplifier.

PubMed

Guo, Wei; Huang, Da-Quan

2003-01-01

Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

All-semiconductor metamaterial-based optical circuit board at the microscale

DOE Office of Scientific and Technical Information (OSTI.GOV)

Min, Li; Huang, Lirong, E-mail: lrhuang@hust.edu.cn

2015-07-07

The newly introduced metamaterial-based optical circuit, an analogue of electronic circuit, is becoming a forefront topic in the fields of electronics, optics, plasmonics, and metamaterials. However, metals, as the commonly used plasmonic elements in an optical circuit, suffer from large losses at the visible and infrared wavelengths. We propose here a low-loss, all-semiconductor metamaterial-based optical circuit board at the microscale by using interleaved intrinsic GaAs and doped GaAs, and present the detailed design process for various lumped optical circuit elements, including lumped optical inductors, optical capacitors, optical conductors, and optical insulators. By properly combining these optical circuit elements and arrangingmore » anisotropic optical connectors, we obtain a subwavelength optical filter, which can always hold band-stop filtering function for various polarization states of the incident electromagnetic wave. All-semiconductor optical circuits may provide a new opportunity in developing low-power and ultrafast components and devices for optical information processing.« less

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education

ERIC Educational Resources Information Center

Hu, J.; Haffner, M.; Yoder, S.; Scott, M.; Reehal, G.; Ismail, M.

2010-01-01

The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test education at the collegiate level is cited as one of the main sources for this problem. In response to this situation, the Department of Electrical and Computer Engineering at…

77 FR 1505 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-01-10

... Freescale Semiconductor, Inc. of Austin, Texas. The complaint alleges violations of section 337 based upon... `455 patent''). The complaint further alleges that an industry in the United States exists as required... televisions that infringe one or more of claims 9 and 10, and whether an industry in the United States exists...

SEM evaluation of metallization on semiconductors. [Scanning Electron Microscope

NASA Technical Reports Server (NTRS)

Fresh, D. L.; Adolphsen, J. W.

1974-01-01

A test method for the evaluation of metallization on semiconductors is presented and discussed. The method has been prepared in MIL-STD format for submittal as a proposed addition to MIL-STD-883. It is applicable to discrete devices and to integrated circuits and specifically addresses batch-process oriented defects. Quantitative accept/reject criteria are given for contact windows, other oxide steps, and general interconnecting metallization. Figures are provided that illustrate typical types of defects. Apparatus specifications, sampling plans, and specimen preparation and examination requirements are described. Procedures for glassivated devices and for multi-metal interconnection systems are included.

Imaging detectors and electronics—a view of the future

NASA Astrophysics Data System (ADS)

Spieler, Helmuth

2004-09-01

Imaging sensors and readout electronics have made tremendous strides in the past two decades. The application of modern semiconductor fabrication techniques and the introduction of customized monolithic integrated circuits have made large-scale imaging systems routine in high-energy physics. This technology is now finding its way into other areas, such as space missions, synchrotron light sources, and medical imaging. I review current developments and discuss the promise and limits of new technologies. Several detector systems are described as examples of future trends. The discussion emphasizes semiconductor detector systems, but I also include recent developments for large-scale superconducting detector arrays.

A Microcomputer-Based Program for Printing Check Plots of Integrated Circuits Specified in Caltech Intermediate Form.

DTIC Science & Technology

1984-12-01

only four transistors[5]. Each year since that time, the semiconductor industry has con- sistently improved the quality of the fabrication tech- niques...rarely took place at universities and was almost exclusively confined to industry . IC design techniques were developed, tested, and taught only in the...community, it is not uncommon for industry to borrow ideas and even particular programs from these university designed tools. The Very Large Scale Integration

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

University of Illinois

2009-04-21

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

Rogers, John A [Champaign, IL; Khang, Dahl-Young [Seoul, KR; Sun, Yugang [Naperville, IL; Menard, Etienne [Durham, NC

2012-06-12

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

Rogers, John A.; Khang, Dahl-Young; Sun, Yugang; Menard, Etienne

2014-06-17

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

Rogers, John A.; Khang, Dahl-Young; Sun, Yugang; Menard, Etienne

2016-12-06

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

Rogers, John A.; Khang, Dahl -Young; Sun, Yugang; Menard, Etienne

2015-08-11

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Results on 3D interconnection from AIDA WP3

NASA Astrophysics Data System (ADS)

Moser, Hans-Günther; AIDA-WP3

2016-09-01

From 2010 to 2014 the EU funded AIDA project established in one of its work packages (WP3) a network of groups working collaboratively on advanced 3D integration of electronic circuits and semiconductor sensors for applications in particle physics. The main motivation came from the severe requirements on pixel detectors for tracking and vertexing at future Particle Physics experiments at LHC, super-B factories and linear colliders. To go beyond the state-of-the-art, the main issues were studying low mass, high bandwidth applications, with radiation hardness capabilities, with low power consumption, offering complex functionality, with small pixel size and without dead regions. The interfaces and interconnects of sensors to electronic readout integrated circuits are a key challenge for new detector applications.

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement

NASA Astrophysics Data System (ADS)

Muyskens, Mark

1997-07-01

Our application of an integrated-circuit (IC) temperature sensor which is easy-to-use, inexpensive, rugged, easily computer-interfacable and has good precision is described. The design, based on the National Semiconductor LM35 IC chip, avoids some of the difficulties associated with conventional sensors (thermocouples, thermistors, and platinum resistance thermometers) and a previously described IC sensor. The sensor can be used with a variety of data-acquisition systems. Applications range from general chemistry to physical chemistry, particularly where computer interfaced, digital temperature measurement is desired. Included is a detailed description of our current design with suggestions for improvement and a performance evaluation of the precision in differential measurement and the time constant for responding to temperature change.

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Effect of top-down nanomachining on electrical conduction properties of TiO2 nanostructure-based chemical sensors.

PubMed

Francioso, L; De Pascali, C; Capone, S; Siciliano, P

2012-03-09

The present research was motivated by the growing interest of the scientific community towards the understanding of basic gas-surface interaction mechanisms in 1D nanostructured metal oxide semiconductors, whose significantly enhanced chemical detection sensitivity is known. In this work, impedance spectroscopy (IS) was used to evaluate how a top-down patterning of the sensitive layer can modulate the electrical properties of a gas sensor based on a fully integrated nanometric array of TiO(2) polycrystalline strips. The aim of the study was supported by comparative experimental activity carried out on different thin film gas sensors based on identical TiO(2) polycrystalline sensitive thin films. The impedance responses of the investigated devices under dry air (as the reference environment) and ethanol vapors (as the target gas) were fitted by a complex nonlinear least-squares method using LEVM software, in order to find an appropriate equivalent circuit describing the main conduction processes involved in the gas/semiconductor interactions. Two different equivalent circuit models were identified as completely representative of the TiO(2) thin film and the TiO(2) nanostructure-based gas sensors, respectively. All the circuit parameters were quantified and the related standard deviations were evaluated. The simulated results well approximated the experimental data as indicated by the small mean errors of the fits (in the range of 10(-4)) and the small standard deviations of the circuit parameters. In addition to the substrate capacitance, three different contributions to the overall conduction mechanism were identified for both equivalent circuits: bulk conductivity, intergrain contact and semiconductor-electrode contact, electrically represented by an ideal resistor R(g), a parallel R(gb)C(gb) block and a parallel R(c)-CPE(c) combination, respectively. In terms of equivalent circuit modeling, the sensitive layer patterning introduced an additional parameter in parallel connection with the whole circuit block. Such a circuit element (an ideal inductor, L) has an average value of about 125 μH and exhibits no direct dependence on the analyte gas concentration. Its presence could be due to complex mutual inductance effects occurring both between all the adjacent nanostrips (10 µm spaced) and between the nanostrips and the n-type-doped silicon substrate underneath the thermal oxide (wire/plate effect), where a two order of magnitude higher magnetic permeability of silicon can give L values comparable with those estimated by the fitting procedure. Slightly modified experimental models confirmed that the theoretical background, regulating thin film devices based on metal oxide semiconductors, is also valid for nanopatterned devices.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

PubMed Central

Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

2016-01-01

The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

Enhacement of intrafield overlay using a design based metrology system

NASA Astrophysics Data System (ADS)

Jo, Gyoyeon; Ji, Sunkeun; Kim, Shinyoung; Kang, Hyunwoo; Park, Minwoo; Kim, Sangwoo; Kim, Jungchan; Park, Chanha; Yang, Hyunjo; Maruyama, Kotaro; Park, Byungjun

2016-03-01

As the scales of the semiconductor devices continue to shrink, accurate measurement and control of the overlay have been emphasized for securing more overlay margin. Conventional overlay analysis methods are based on the optical measurement of the overlay mark. However, the overlay data obtained from these optical methods cannot represent the exact misregistration between two layers at the circuit level. The overlay mismatch may arise from the size or pitch difference between the overlay mark and the real pattern. Pattern distortion, caused by CMP or etching, could be a source of the overlay mismatch as well. Another issue is the overlay variation in the real circuit pattern which varies depending on its location. The optical overlay measurement methods, such as IBO and DBO that use overlay mark on the scribeline, are not capable of defining the exact overlay values of the real circuit. Therefore, the overlay values of the real circuit need to be extracted to integrate the semiconductor device properly. The circuit level overlay measurement using CDSEM is time-consuming in extracting enough data to indicate overall trend of the chip. However DBM tool is able to derive sufficient data to display overlay tendency of the real circuit region with high repeatability. An E-beam based DBM(Design Based Metrology) tool can be an alternative overlay measurement method. In this paper, we are going to certify that the overlay values extracted from optical measurement cannot represent the circuit level overlay values. We will also demonstrate the possibility to correct misregistration between two layers using the overlay data obtained from the DBM system.

Procedures for Instructional Systems Development

DTIC Science & Technology

1981-09-18

single faults to the circuit and components level. (JTI Task No. TCB-01). Figure III-ll.--Example of a Module Page of a Curriculum Outline. 3 - 80...semiconductor trapezoidal wave generator circuit , multimeter, and oscilloscope measure the output amplitude, rise time, and jump voltage within +/- 10...accuracy. Given a trainer having a semiconductor trapezoidal wave generator circuit , multimeter, and oscilloscope - CONDITION (C) . measure the output

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Rare earth doped III-nitride semiconductors for spintronic and optoelectronic applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Palai, Ratnakar

2016-10-01

Since last four decades the information and communication technologies are relying on the semiconductor materials. Currently a great deal of attention is being focused on adding spin degree-of-freedom into semiconductor to create a new area of solid-state electronics, called spintronics. In spintronics not only the current but also its spin state is controlled. Such materials need to be good semiconductors for easy integration in typical integrated circuits with high sensitivity to the spin orientation, especially room temperature ferromagnetism being an important desirable property. GaN is considered to be the most important semiconductor after silicon. It is widely used for the production of green, blue, UV, and white LEDs in full color displays, traffic lights, automotive lightings, and general room lighting using white LEDs. GaN-based systems also show promise for microwave and high power electronics intended for radar, satellite, wireless base stations and spintronic applications. Rare earth (Yb, Eu, Er, and Tm) doped GaN shows many interesting optoelectronic and magnetoptic properties e. g. sharp emission from UV through visible to IR, radiation hardness, and ferromagnetism. The talk will be focused on fabrication, optoelectronic (photoluminescence, cathodeluminescence, magnetic, and x-ray photoelectron spectroscopy) properties of some rare earth doped GaN and InGaN semiconductor nanostructures grown by plasma assisted molecular beam epitaxy (MBE) and future applications.

Advances in MMIC technology for communications satellites

NASA Technical Reports Server (NTRS)

Leonard, Regis F.

1992-01-01

This paper discusses NASA Lewis Research Center's program for development of monolithic microwave integrated circuits (MMIC) for application in space communications. Emphasis will be on the improved performance in power amplifiers and low noise receivers which has been made possible by the development of new semiconductor materials and devices. Possible applications of high temperature superconductivity for space communications will also be presented.

77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-13

... U.S.C. 1337, on behalf of Peregrine Semiconductor Corporation of San Diego, California. Supplements... alleges that an industry in the United States exists as required by subsection (a)(2) of section 337. The...; and claims 1, 3, 5, and 6 of the `499 patent, and whether an industry in the United States exists as...

Towards a DNA Nanoprocessor: Reusable Tile-Integrated DNA Circuits.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2016-08-22

Modern electronic microprocessors use semiconductor logic gates organized on a silicon chip to enable efficient inter-gate communication. Here, arrays of communicating DNA logic gates integrated on a single DNA tile were designed and used to process nucleic acid inputs in a reusable format. Our results lay the foundation for the development of a DNA nanoprocessor, a small and biocompatible device capable of performing complex analyses of DNA and RNA inputs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

Astronaut Peggy Whitson Installs SUBSA Experiment

NASA Technical Reports Server (NTRS)

2002-01-01

Expedition Five flight engineer Peggy Whitson is shown installing the Solidification Using a Baffle in Sealed Ampoules (SUBSA) experiment in the Microgravity Science Glovebox (MSG) in the Destiny laboratory aboard the International Space Station (ISS). SUBSA examines the solidification of semiconductor crystals from a melted material. Semiconductor crystals are used for many products that touch our everyday lives. They are found in computer chips, integrated circuits, and a multitude of other electronic devices, such as sensors for medical imaging equipment and detectors of nuclear radiation. Materials scientists want to make better semiconductor crystals to be able to further reduce the size of high-tech devices. In the microgravity environment, convection and sedimentation are reduced, so fluids do not remove and deform. Thus, space laboratories provide an ideal environment of studying solidification from the melt. This investigation is expected to determine the mechanism causing fluid motion during production of semiconductors in space. It will provide insight into the role of the melt motion in production of semiconductor crystals, advancing our knowledge of the crystal growth process. This could lead to a reduction of defects in semiconductor crystals produced in space and on Earth.

International Space Station (ISS)

NASA Image and Video Library

2002-07-05

Expedition Five flight engineer Peggy Whitson is shown installing the Solidification Using a Baffle in Sealed Ampoules (SUBSA) experiment in the Microgravity Science Glovebox (MSG) in the Destiny laboratory aboard the International Space Station (ISS). SUBSA examines the solidification of semiconductor crystals from a melted material. Semiconductor crystals are used for many products that touch our everyday lives. They are found in computer chips, integrated circuits, and a multitude of other electronic devices, such as sensors for medical imaging equipment and detectors of nuclear radiation. Materials scientists want to make better semiconductor crystals to be able to further reduce the size of high-tech devices. In the microgravity environment, convection and sedimentation are reduced, so fluids do not remove and deform. Thus, space laboratories provide an ideal environment of studying solidification from the melt. This investigation is expected to determine the mechanism causing fluid motion during production of semiconductors in space. It will provide insight into the role of the melt motion in production of semiconductor crystals, advancing our knowledge of the crystal growth process. This could lead to a reduction of defects in semiconductor crystals produced in space and on Earth.

Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

PubMed

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-08-21

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Use of vacuum tubes in test instrumentation for measuring characteristics of fast high-voltage semiconductor devices

NASA Technical Reports Server (NTRS)

Berning, D.

1981-01-01

Circuits are described that permit measurement of fast events occurring in power semiconductors. These circuits were developed for the dynamic characterization of transistors used in inductive-load switching applications. Fast voltage clamping using vacuum diodes is discussed, and reference is made to a unique circuit that was built for performing nondestructive, reverse-bias, second-breakdown tests on transistors.

Alternative Packaging for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Development of optical packet and circuit integrated ring network testbed.

PubMed

Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

2011-12-12

We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated. © 2011 Optical Society of America

Nanogap Electrodes towards Solid State Single-Molecule Transistors.

PubMed

Cui, Ajuan; Dong, Huanli; Hu, Wenping

2015-12-01

With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Erbium-doped zinc-oxide waveguide amplifiers for hybrid photonic integrated circuits

NASA Astrophysics Data System (ADS)

O'Neal, Lawrence; Anthony, Deion; Bonner, Carl; Geddis, Demetris

2016-02-01

CMOS logic circuits have entered the sub-100nm regime, and research is on-going to investigate the quantum effects that are apparent at this dimension. To avoid some of the constraints imposed by fabrication, entropy, energy, and interference considerations for nano-scale devices, many have begun designing hybrid and/or photonic integrated circuits. These circuits consist of transistors, light emitters, photodetectors, and electrical and optical waveguides. As attenuation is a limiting factor in any communications system, it is advantageous to integrate a signal amplifier. There are numerous examples of electrical amplifiers, but in order to take advantage of the benefits provided by optically integrated systems, optical amplifiers are necessary. The erbium doped fiber amplifier is an example of an optical amplifier which is commercially available now, but the distance between the amplifier and the device benefitting from amplification can be decreased and provide greater functionality by providing local, on-chip amplification. Zinc oxide is an attractive material due to its electrical and optical properties. Its wide bandgap (≍3.4 eV) and high refractive index (≍2) make it an excellent choice for integrated optics systems. Moreover, erbium doped zinc oxide (Er:ZnO) is a suitable candidate for optical waveguide amplifiers because of its compatibility with semiconductor processing technology, 1.54 μm luminescence, transparency, low resistivity, and amplification characteristics. This research presents the characterization of radio frequency magnetron sputtered Er:ZnO, the design and fabrication of integrated waveguide amplifiers, and device analysis.

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa. PMID:22303167

Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

PubMed

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

50 Years of ``Scaling'' Jack Kilby's Invention

NASA Astrophysics Data System (ADS)

Doering, Robert

2008-03-01

This year is the 50th anniversary of Jack Kilby's 1958 invention of the integrated circuit (IC), for which he won the 2000 Nobel Prize in Physics. Since that invention in a laboratory at Texas Instruments, IC components have been continuously miniaturized, which has resulted in exponential improvement trends in their performance, energy efficiency, and cost per function. These improvements have created a semiconductor industry that has grown to over 250B in annual sales. The process of reducing integrated-circuit component size and associated parameters in a coordinated fashion is traditionally called ``feature-size scaling.'' Kilby's original circuit had active (transistor) and passive (resistor, capacitor) components with dimensions of a few millimeters. Today, the minimum feature sizes on integrated circuits are less than 30 nanometers for patterned line widths and down to about one nanometer for film thicknesses. Thus, we have achieved about five orders of magnitude in linear-dimension scaling over the past fifty years, which has resulted in about ten orders of magnitude increase in the density of IC components, a representation of ``Moore's Law.'' As IC features are approaching atomic dimensions, increasing emphasis is now being given to the parallel effort of further diversifying the types of components in integrated circuits. This is called ``functional scaling'' and ``more then Moore.'' Of course, the enablers for both types of scaling have been developed at many laboratories around the world. This talk will review a few of the highlights in scaling and its applications from R&D projects at Texas Instruments.

Nanotubes May Break Through "Chip Wall"

NASA Technical Reports Server (NTRS)

Laufenberg, Larry

2003-01-01

In 1965, just four years after the first planar integrated circuit (IC) was discovered, Cordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law" For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that may soon block the continued scaling predicted by by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known manufacturable solution exists. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.

CMOS compatible IR sensors by cytochrome c protein

NASA Astrophysics Data System (ADS)

Liao, Chien-Jen; Su, Guo-Dung

2013-09-01

In recent years, due to the progression of the semiconductor industrial, the uncooled Infrared sensor - microbolometer has opened the opportunity for achieving low cost infrared imaging systems for both military and commercial applications. Therefore, various fabrication processes and different materials based microbolometer have been developed sequentially. The cytochrome c (protein) thin film has be reported high temperature coefficient of resistance (TCR), which is related to the performance of microbolometer directly. Hence the superior TCR value will increase the performance of microbolometer. In this paper, we introduced a novel fabrication process using aluminum which is compatible with the Taiwan Semiconductor Manufacture Company (TSMC) D35 2P4M process as the main structure material, which benefits the device to integrate with readout integrated circuit (ROIC).The aluminum split structure is suspended by sacrificial layer utilizing the standard photolithography technology and chemical etching. The height and thickness of the structure are already considered. Besides, cytochrome c solutions were ink-jetted onto the aluminum structure by using the inkjet printer, applying precise control of the Infrared absorbing layer. In measurement, incident Infrared radiation can be detected and later the heat can be transmitted to adjacent pads to readout the signal. This approach applies an inexpensive and simple fabrication process and makes the device suitable for integration. In addition, the performance can be further improved with low noise readout circuits.

Integrating Magnetics for On-Chip Power: A Perspective

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sullivan, CR; Harburg, DV; Qiu, JZ

Integration of efficient power converters requires technology for efficient, high-power on-chip inductors and transformers. Increases in switching frequency, facilitated by advances in circuit designs and silicon or wide-bandgap semiconductors, can enable miniaturization, but only if the magnetics technology works well at the higher frequencies. Technologies, geometries, and scaling of air-core and magnetic-core inductors and transformers are examined, and their potential for integration is discussed. Air-core inductors can use simpler fabrication, and increasing frequency can always be used to decrease their size, but magnetic cores can decrease the required thickness without requiring as high a frequency.

Photonic generation of ultra-wideband signals by direct current modulation on SOA section of an SOA-integrated SGDBR laser.

PubMed

Lv, Hui; Yu, Yonglin; Shu, Tan; Huang, Dexiu; Jiang, Shan; Barry, Liam P

2010-03-29

Photonic ultra-wideband (UWB) pulses are generated by direct current modulation of a semiconductor optical amplifier (SOA) section of an SOA-integrated sampled grating distributed Bragg reflector (SGDBR) laser. Modulation responses of the SOA section of the laser are first simulated with a microwave equivalent circuit model. Simulated results show a resonance behavior indicating the possibility to generate UWB signals with complex shapes in the time domain. The UWB pulse generation is then experimentally demonstrated for different selected wavelength channels with an SOA-integrated SGDBR laser.

Electron Beam "Writes" Silicon On Sapphire

NASA Technical Reports Server (NTRS)

Heinemann, Klaus

1988-01-01

Method of growing silicon on sapphire substrate uses beam of electrons to aid growth of semiconductor material. Silicon forms as epitaxial film in precisely localized areas in micron-wide lines. Promising fabrication method for fast, densely-packed integrated circuits. Silicon deposited preferentially in contaminated substrate zones and in clean zone irradiated by electron beam. Electron beam, like surface contamination, appears to stimulate decomposition of silane atmosphere.

75 FR 16837 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-04-02

.... 1337, on behalf of Freescale Semiconductor, Inc. of Austin, Texas. A letter supplementing the complaint...,715,014; and 7,199,306. The complaint further alleges that an industry in the United States exists as...,715,014; and claims 1, 6, 11, and 13-16 of U.S. Patent No. 7,199,306, and whether an industry in the...

General Electronics Technician: Semiconductor Devices and Circuits.

ERIC Educational Resources Information Center

Hilley, Robert

These instructional materials include a teacher's guide designed to assist instructors in organizing and presenting an introductory course in general electronics focusing on semiconductor devices and circuits and a student guide. The materials are based on the curriculum-alignment concept of first stating the objectives, developing instructional…

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

PubMed Central

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature. PMID:22399944

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique.

PubMed

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature.

UHF front-end feeding RFID-based body sensor networks by exploiting the reader signal

NASA Astrophysics Data System (ADS)

Pasca, M.; Colella, R.; Catarinucci, L.; Tarricone, L.; D'Amico, S.; Baschirotto, A.

2016-05-01

This paper presents an integrated, high-sensitivity UHF radio frequency identification (RFID) power management circuit for body sensor network applications. The circuit consists of a two-stage RF-DC Dickson's rectifier followed by an integrated five-stage DC-DC Pelliconi's charge pump driven by an ultralow start-up voltage LC oscillator. The DC-DC charge pump interposed between the RF-DC rectifier and the output load provides the RF to load isolation avoiding losses due to the diodes reverse saturation current. The RF-DC rectifier has been realized on FR4 substrate, while the charge pump and the oscillator have been realized in 180 nm complementary metal oxide semiconductor (CMOS) technology. Outdoor measurements demonstrate the ability of the power management circuit to provide 400 mV output voltage at 14 m distance from the UHF reader, in correspondence of -25 dBm input signal power. As demonstrated in the literature, such output voltage level is suitable to supply body sensor network nodes.

Business dynamics of lithography at very low k1 factors

NASA Astrophysics Data System (ADS)

Harrell, Sam; Preil, Moshe E.

1999-07-01

Lithography is the largest capital investment and the largest operating cost component of leading edge semiconductor fabs. In addition, it is the dominant factor in determining the performance of a semiconductor device and is important in determining the yield and thus the economics of a semiconductor circuit. To increase competitiveness and broaden adoption of circuits and the end products in which they are used, there has been and continues to be a dramatic acceleration in the industry roadmap. A critical factor in the acceleration is driving the lithographic images to smaller feature size. There has always been economic tension between the pace of change and the resultant circuit cost. The genius of the semiconductor industry has been in its ability to balance its technology with economic factors and deliver outstanding value to those using the circuits to add value to their end products. The critical question today is whether optical lithography can be successfully and economically extended to maintain and improve the economic benefits of higher complexity circuits. In this paper we will discuss some of these significant tradeoffs required to maintain optically based lithographic progress on the roadmap at acceptable cost.

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

PubMed

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

2016-12-31

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

PubMed Central

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

2016-01-01

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

NASA Space Engineering Research Center for VLSI systems design

NASA Technical Reports Server (NTRS)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

A 5GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO with a Novel Varactors Pair Circuit

NASA Astrophysics Data System (ADS)

Ta, Tuan Thanh; Kameda, Suguru; Takagi, Tadashi; Tsubouchi, Kazuo

In this paper, a fully integrated 5GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1GHz to 6.1GHz (relative value of 17.9%) and phase noise of lower than -110.8dBc/Hz at 1MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182dBc/Hz.

Computational Modeling of Ultrafast Pulse Propagation in Nonlinear Optical Materials

NASA Technical Reports Server (NTRS)

Goorjian, Peter M.; Agrawal, Govind P.; Kwak, Dochan (Technical Monitor)

1996-01-01

There is an emerging technology of photonic (or optoelectronic) integrated circuits (PICs or OEICs). In PICs, optical and electronic components are grown together on the same chip. rib build such devices and subsystems, one needs to model the entire chip. Accurate computer modeling of electromagnetic wave propagation in semiconductors is necessary for the successful development of PICs. More specifically, these computer codes would enable the modeling of such devices, including their subsystems, such as semiconductor lasers and semiconductor amplifiers in which there is femtosecond pulse propagation. Here, the computer simulations are made by solving the full vector, nonlinear, Maxwell's equations, coupled with the semiconductor Bloch equations, without any approximations. The carrier is retained in the description of the optical pulse, (i.e. the envelope approximation is not made in the Maxwell's equations), and the rotating wave approximation is not made in the Bloch equations. These coupled equations are solved to simulate the propagation of femtosecond optical pulses in semiconductor materials. The simulations describe the dynamics of the optical pulses, as well as the interband and intraband.

On-Chip Waveguide Coupling of a Layered Semiconductor Single-Photon Source.

PubMed

Tonndorf, Philipp; Del Pozo-Zamudio, Osvaldo; Gruhler, Nico; Kern, Johannes; Schmidt, Robert; Dmitriev, Alexander I; Bakhtinov, Anatoly P; Tartakovskii, Alexander I; Pernice, Wolfram; Michaelis de Vasconcellos, Steffen; Bratschitsch, Rudolf

2017-09-13

Fully integrated quantum technology based on photons is in the focus of current research, because of its immense potential concerning performance and scalability. Ideally, the single-photon sources, the processing units, and the photon detectors are all combined on a single chip. Impressive progress has been made for on-chip quantum circuits and on-chip single-photon detection. In contrast, nonclassical light is commonly coupled onto the photonic chip from the outside, because presently only few integrated single-photon sources exist. Here, we present waveguide-coupled single-photon emitters in the layered semiconductor gallium selenide as promising on-chip sources. GaSe crystals with a thickness below 100 nm are placed on Si 3 N 4 rib or slot waveguides, resulting in a modified mode structure efficient for light coupling. Using optical excitation from within the Si 3 N 4 waveguide, we find nonclassicality of generated photons routed on the photonic chip. Thus, our work provides an easy-to-implement and robust light source for integrated quantum technology.

Feasibility study of silicon nitride protection of plastic encapsulated semiconductors

NASA Technical Reports Server (NTRS)

Peters, J. W.; Hall, T. C.; Erickson, J. J.; Gebhart, F. L.

1979-01-01

The application of low temperature silicon nitride protective layers on wire bonded integrated circuits mounted on lead frame assemblies is reported. An evaluation of the mechanical and electrical compatibility of both plasma nitride and photochemical silicon nitride (photonitride) passivations (parallel evaluations) of integrated circuits which were then encapsulated in plastic is described. Photonitride passivation is compatible with all wire bonded lead frame assemblies, with or without initial chip passivation. Plasma nitride passivation of lead frame assemblies is possible only if the chip is passivated before lead frame assembly. The survival rate after the environmental test sequence of devices with a coating of plasma nitride on the chip and a coating of either plasma nitride or photonitride over the assembled device is significantly greater than that of devices assembled with no nitride protective coating over either chip or lead frame.

CMOS array design automation techniques. [metal oxide semiconductors

NASA Technical Reports Server (NTRS)

Ramondetta, P.; Feller, A.; Noto, R.; Lombardi, T.

1975-01-01

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.

Circuit For Current-vs.-Voltage Tests Of Semiconductors

NASA Technical Reports Server (NTRS)

Huston, Steven W.

1991-01-01

Circuit designed for measurement of dc current-versus-voltage characteristics of semiconductor devices. Operates in conjunction with x-y pen plotter or digital storage oscilloscope, which records data. Includes large feedback resistors to prevent high currents damaging device under test. Principal virtues: low cost, simplicity, and compactness. Also used to evaluate diodes and transistors.

22 W coherent GaAlAs amplifier array with 400 emitters

NASA Technical Reports Server (NTRS)

Krebs, D.; Herrick, R.; No, K.; Harting, W.; Struemph, F.

1991-01-01

Greater than 22 W of optical power has been demonstrated from a multiple-emitter, traveling-wave semiconductor amplifier, with approximately 87 percent of the output at the frequency of the injection source. The device integrates, in AlGaAs graded-index separate-confinement heterostructure single quantum well (GRINSCH-SQW) epitaxy, 400 ridge waveguide amplifiers with a coherent optical signal distribution circuit on a 12 x 6 mm chip.

338-GHz Semiconductor Amplifier Module

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Gaier, Todd C.; Soria, Mary M.; Fung, King Man; Rasisic, Vesna; Deal, William; Leong, Kevin; Mei, Xiao Bing; Yoshida, Wayne; Liu, Po-Hsin;

Total-dose radiation effects data for semiconductor devices, volume 2

NASA Technical Reports Server (NTRS)

Price, W. E.; Martin, K. E.; Nichols, D. K.; Gauthier, M. K.; Brown, S. F.

1981-01-01

Total ionizing dose radiation test data on integrated circuits are analyzed. Tests were performed with the electron accelerator (Dynamitron) that provides a steady state 2.5 MeV electron beam. Some radiation exposures were made with a Cobalt-60 gamma ray source. The results obtained with the Cobalt-60 source are considered an approximate measure of the radiation damage that would be incurred by an equivalent dose of electrons.

Toward high performance nanoscale optoelectronic devices: super solar energy harvesting in single standing core-shell nanowire.

PubMed

Zhou, Jian; Wu, Yonggang; Xia, Zihuan; Qin, Xuefei; Zhang, Zongyi

2017-11-27

Single nanowire solar cells show great promise for next-generation photovoltaics and for powering nanoscale devices. Here, we present a detailed study of light absorption in a single standing semiconductor-dielectric core-shell nanowire (CSNW). We find that the CSNW structure can not only concentrate the incident light into the structure, but also confine most of the concentrated light to the semiconductor core region, which boosts remarkably the light absorption cross-section of the semiconductor core. The CSNW can support multiple higher-order HE modes, as well as Fabry-Pérot (F-P) resonance, compared to the bare nanowire (BNW). Overlapping of the adjacent higher-order HE modes results in broadband light absorption enhancement in the solar radiation spectrum. Results based on detailed balance analysis demonstrate that the super light concentration of the single CSNW gives rise to higher short-circuit current and open-circuit voltage, and thus higher apparent power conversion efficiency (3644.2%), which goes far beyond that of the BNW and the Shockley-Queisser limit that restricts the performance of a planar counterparts. Our study shows that the single CSNW can be a promising platform for construction of high performance nanoscale photodetectors, nanoelectronic power sources, super miniature cells, and diverse integrated nanosystems.

Visible light laser voltage probing on thinned substrates

DOEpatents

Beutler, Joshua; Clement, John Joseph; Miller, Mary A.; Stevens, Jeffrey; Cole, Jr., Edward I.

2017-03-21

The various technologies presented herein relate to utilizing visible light in conjunction with a thinned structure to enable characterization of operation of one or more features included in an integrated circuit (IC). Short wavelength illumination (e.g., visible light) is applied to thinned samples (e.g., ultra-thinned samples) to achieve a spatial resolution for laser voltage probing (LVP) analysis to be performed on smaller technology node silicon-on-insulator (SOI) and bulk devices. Thinning of a semiconductor material included in the IC (e.g., backside material) can be controlled such that the thinned semiconductor material has sufficient thickness to enable operation of one or more features comprising the IC during LVP investigation.

Thermally grown oxide and diffusions for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1979-01-01

A totally automated facility for semiconductor oxidation and diffusion was developed using a state-of-the-art diffusion furnace and high temperature grown oxides. Major innovations include: (1) a process controller specifically for semiconductor processing; (2) an automatic loading system to accept wafers from an air track, insert them into a quartz carrier and then place the carrier on a paddle for insertion into the furnace; (3) automatic unloading of the wafers back onto the air track, and (4) boron diffusion using diborane with plus or minus 5 percent uniformity. Processes demonstrated include Wet and dry oxidation for general use and for gate oxide, boron diffusion, phosphorous diffusion, and sintering.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits.

PubMed

Baeg, Kang-Jun; Kim, Juhwan; Khim, Dongyoon; Caironi, Mario; Kim, Dong-Yu; You, In-Kyu; Quinn, Jordan R; Facchetti, Antonio; Noh, Yong-Young

2011-08-01

Ambipolar π-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (∼4.1 eV) compared to that of a pristine Au electrode (∼4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ∼0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ∼0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) < 70 nA when I(on) > 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ∼12 kHz) based on a solution-processed ambipolar polymer are demonstrated.

On-chip passive three-port circuit of all-optical ordered-route transmission.

PubMed

Liu, Li; Dong, Jianji; Gao, Dingshan; Zheng, Aoling; Zhang, Xinliang

2015-05-13

On-chip photonic circuits of different specific functions are highly desirable and becoming significant demands in all-optical communication network. Especially, the function to control the transmission directions of the optical signals in integrated circuits is a fundamental research. Previous schemes, such as on-chip optical circulators, are mostly realized by Faraday effect which suffers from material incompatibilities between semiconductors and magneto-optical materials. Achieving highly functional circuits in which light circulates in a particular direction with satisfied performances are still difficult in pure silicon photonics platform. Here, we propose and experimentally demonstrate a three-port passive device supporting optical ordered-route transmission based on silicon thermo-optic effect for the first time. By injecting strong power from only one port, the light could transmit through the three ports in a strict order (1→2, 2→3, 3→1) while be blocked in the opposite order (1→3, 3→2, 2→1). The blocking extinction ratios and operation bandwidths have been investigated in this paper. Moreover, with compact size, economic fabrication process and great extensibility, this proposed photonic integrated circuit is competitive to be applied in on-chip all-optical information processing systems, such as path priority selector.

Development of Integrated Preamplifier for High-Frequency Ultrasonic Transducers and Low-Power Handheld Receiver

PubMed Central

Choi, Hojong; Li, Xiang; Lau, Sien-Ting; Hu, ChangHong; Zhou, Qifa; Shung, K. Kirk

2012-01-01

This paper describes the design of a front-end circuit consisting of an integrated preamplifier with a Sallen-Key Butterworth filter for very-high-frequency ultrasonic transducers and a low-power handheld receiver. This preamplifier was fabricated using a 0.18-μm 7WL SiGe bi-polar complementary metal oxide semiconductor (BiCMOS) process. The Sallen-Key filter is used to increase the voltage gain of the front-end circuit for high-frequency transducers which are generally low in sensitivity. The measured peak voltage gain of the frontend circuits for the BiCMOS preamplifier with the Sallen-Key filter was 41.28 dB at 100 MHz with a −6-dB bandwidth of 91%, and the dc power consumption of the BiCMOS preamplifier was 49.53 mW. The peak voltage gain of the front-end circuits for the CMOS preamplifier with the Sallen-Key filter was 39.52 dB at 100 MHz with a −6-dB bandwidth of 108%, and the dc power consumption of the CMOS preamplifier was 43.57 mW. Pulse-echo responses and wire phantom images with a single-element ultrasonic transducer have been acquired to demonstrate the performance of the front-end circuit. PMID:23443700

On-chip passive three-port circuit of all-optical ordered-route transmission

PubMed Central

Liu, Li; Dong, Jianji; Gao, Dingshan; Zheng, Aoling; Zhang, Xinliang

2015-01-01

On-chip photonic circuits of different specific functions are highly desirable and becoming significant demands in all-optical communication network. Especially, the function to control the transmission directions of the optical signals in integrated circuits is a fundamental research. Previous schemes, such as on-chip optical circulators, are mostly realized by Faraday effect which suffers from material incompatibilities between semiconductors and magneto-optical materials. Achieving highly functional circuits in which light circulates in a particular direction with satisfied performances are still difficult in pure silicon photonics platform. Here, we propose and experimentally demonstrate a three-port passive device supporting optical ordered-route transmission based on silicon thermo-optic effect for the first time. By injecting strong power from only one port, the light could transmit through the three ports in a strict order (1→2, 2→3, 3→1) while be blocked in the opposite order (1→3, 3→2, 2→1). The blocking extinction ratios and operation bandwidths have been investigated in this paper. Moreover, with compact size, economic fabrication process and great extensibility, this proposed photonic integrated circuit is competitive to be applied in on-chip all-optical information processing systems, such as path priority selector. PMID:25970855

Multi-spectral imaging with infrared sensitive organic light emitting diode

PubMed Central

Kim, Do Young; Lai, Tzung-Han; Lee, Jae Woong; Manders, Jesse R.; So, Franky

2014-01-01

Commercially available near-infrared (IR) imagers are fabricated by integrating expensive epitaxial grown III-V compound semiconductor sensors with Si-based readout integrated circuits (ROIC) by indium bump bonding which significantly increases the fabrication costs of these image sensors. Furthermore, these typical III-V compound semiconductors are not sensitive to the visible region and thus cannot be used for multi-spectral (visible to near-IR) sensing. Here, a low cost infrared (IR) imaging camera is demonstrated with a commercially available digital single-lens reflex (DSLR) camera and an IR sensitive organic light emitting diode (IR-OLED). With an IR-OLED, IR images at a wavelength of 1.2 µm are directly converted to visible images which are then recorded in a Si-CMOS DSLR camera. This multi-spectral imaging system is capable of capturing images at wavelengths in the near-infrared as well as visible regions. PMID:25091589

Multi-spectral imaging with infrared sensitive organic light emitting diode

NASA Astrophysics Data System (ADS)

Kim, Do Young; Lai, Tzung-Han; Lee, Jae Woong; Manders, Jesse R.; So, Franky

2014-08-01

Commercially available near-infrared (IR) imagers are fabricated by integrating expensive epitaxial grown III-V compound semiconductor sensors with Si-based readout integrated circuits (ROIC) by indium bump bonding which significantly increases the fabrication costs of these image sensors. Furthermore, these typical III-V compound semiconductors are not sensitive to the visible region and thus cannot be used for multi-spectral (visible to near-IR) sensing. Here, a low cost infrared (IR) imaging camera is demonstrated with a commercially available digital single-lens reflex (DSLR) camera and an IR sensitive organic light emitting diode (IR-OLED). With an IR-OLED, IR images at a wavelength of 1.2 µm are directly converted to visible images which are then recorded in a Si-CMOS DSLR camera. This multi-spectral imaging system is capable of capturing images at wavelengths in the near-infrared as well as visible regions.

Spatially selective hydrogen irradiation of dilute nitride semiconductors: a brief review

NASA Astrophysics Data System (ADS)

Felici, Marco; Pettinari, Giorgio; Biccari, Francesco; Capizzi, Mario; Polimeni, Antonio

2018-05-01

We provide a brief survey of the most recent results obtained by performing spatially selective hydrogen irradiation of dilute nitride semiconductors. The striking effects of the formation of stable N–H complexes in these compounds—coupled to the ultrasharp diffusion profile of H therein—can be exploited to tailor the structural (lattice constant) and optoelectronic (energy gap, refractive index, electron effective mass) properties of the material in the growth plane, with a spatial resolution of a few nm. This can be applied to the fabrication of site-controlled quantum dots (QDs) and wires, but also to the realization of the optical elements required for the on-chip manipulation and routing of qubits in fully integrated photonic circuits. The fabricated QDs—which have shown the ability to emit single photons—can also be deterministically coupled with photonic crystal microcavities, proving their inherent suitability to act as integrated light sources in complex nanophotonic devices.

3D hybrid integrated lasers for silicon photonics

NASA Astrophysics Data System (ADS)

Song, B.; Pinna, S.; Liu, Y.; Megalini, L.; Klamkin, J.

2018-02-01

A novel 3D hybrid integration platform combines group III-V materials and silicon photonics to yield high-performance lasers is presented. This platform is based on flip-chip bonding and vertical optical coupling integration. In this work, indium phosphide (InP) devices with monolithic vertical total internal reflection turning mirrors were bonded to active silicon photonic circuits containing vertical grating couplers. Greater than 2 mW of optical power was coupled into a silicon waveguide from an InP laser. The InP devices can also be bonded directly to the silicon substrate, providing an efficient path for heat dissipation owing to the higher thermal conductance of silicon compared to InP. Lasers realized with this technique demonstrated a thermal impedance as low as 6.2°C/W, allowing for high efficiency and operation at high temperature. InP reflective semiconductor optical amplifiers were also integrated with 3D hybrid integration to form integrated external cavity lasers. These lasers demonstrated a wavelength tuning range of 30 nm, relative intensity noise lower than -135 dB/Hz and laser linewidth of 1.5 MHz. This platform is promising for integration of InP lasers and photonic integrated circuits on silicon photonics.

Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

NASA Astrophysics Data System (ADS)

Naquin, Clint Alan

Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.

Fundamentals handbook of electrical and computer engineering. Volume 1 Circuits fields and electronics

NASA Astrophysics Data System (ADS)

Chang, S. S. L.

State of the art technology in circuits, fields, and electronics is discussed. The principles and applications of these technologies to industry, digital processing, microwave semiconductors, and computer-aided design are explained. Important concepts and methodologies in mathematics and physics are reviewed, and basic engineering sciences and associated design methods are dealt with, including: circuit theory and the design of magnetic circuits and active filter synthesis; digital signal processing, including FIR and IIR digital filter design; transmission lines, electromagnetic wave propagation and surface acoustic wave devices. Also considered are: electronics technologies, including power electronics, microwave semiconductors, GaAs devices, and magnetic bubble memories; digital circuits and logic design.

Electrically driven monolithic subwavelength plasmonic interconnect circuits

PubMed Central

Liu, Yang; Zhang, Jiasen; Liu, Huaping; Wang, Sheng; Peng, Lian-Mao

2017-01-01

In the post-Moore era, an electrically driven monolithic optoelectronic integrated circuit (OEIC) fabricated from a single material is pursued globally to enable the construction of wafer-scale compact computing systems with powerful processing capabilities and low-power consumption. We report a monolithic plasmonic interconnect circuit (PIC) consisting of a photovoltaic (PV) cascading detector, Au-strip waveguides, and electrically driven surface plasmon polariton (SPP) sources. These components are fabricated from carbon nanotubes (CNTs) via a CMOS (complementary metal-oxide semiconductor)–compatible doping-free technique in the same feature size, which can be reduced to deep-subwavelength scale (~λ/7 to λ/95, λ = 1340 nm) compared with the 14-nm technique node. An OEIC could potentially be configured as a repeater for data transport because of its “photovoltaic” operation mode to transform SPP energy directly into electricity to drive subsequent electronic circuits. Moreover, chip-scale throughput capability has also been demonstrated by fabricating a 20 × 20 PIC array on a 10 mm × 10 mm wafer. Tailoring photonics for monolithic integration with electronics beyond the diffraction limit opens a new era of chip-level nanoscale electronic-photonic systems, introducing a new path to innovate toward much faster, smaller, and cheaper computing frameworks. PMID:29062890

Artificial Neuron Based on Integrated Semiconductor Quantum Dot Mode-Locked Lasers

NASA Astrophysics Data System (ADS)

Mesaritakis, Charis; Kapsalis, Alexandros; Bogris, Adonis; Syvridis, Dimitris

2016-12-01

Neuro-inspired implementations have attracted strong interest as a power efficient and robust alternative to the digital model of computation with a broad range of applications. Especially, neuro-mimetic systems able to produce and process spike-encoding schemes can offer merits like high noise-resiliency and increased computational efficiency. Towards this direction, integrated photonics can be an auspicious platform due to its multi-GHz bandwidth, its high wall-plug efficiency and the strong similarity of its dynamics under excitation with biological spiking neurons. Here, we propose an integrated all-optical neuron based on an InAs/InGaAs semiconductor quantum-dot passively mode-locked laser. The multi-band emission capabilities of these lasers allows, through waveband switching, the emulation of the excitation and inhibition modes of operation. Frequency-response effects, similar to biological neural circuits, are observed just as in a typical two-section excitable laser. The demonstrated optical building block can pave the way for high-speed photonic integrated systems able to address tasks ranging from pattern recognition to cognitive spectrum management and multi-sensory data processing.

Artificial Neuron Based on Integrated Semiconductor Quantum Dot Mode-Locked Lasers

PubMed Central

Mesaritakis, Charis; Kapsalis, Alexandros; Bogris, Adonis; Syvridis, Dimitris

2016-01-01

Neuro-inspired implementations have attracted strong interest as a power efficient and robust alternative to the digital model of computation with a broad range of applications. Especially, neuro-mimetic systems able to produce and process spike-encoding schemes can offer merits like high noise-resiliency and increased computational efficiency. Towards this direction, integrated photonics can be an auspicious platform due to its multi-GHz bandwidth, its high wall-plug efficiency and the strong similarity of its dynamics under excitation with biological spiking neurons. Here, we propose an integrated all-optical neuron based on an InAs/InGaAs semiconductor quantum-dot passively mode-locked laser. The multi-band emission capabilities of these lasers allows, through waveband switching, the emulation of the excitation and inhibition modes of operation. Frequency-response effects, similar to biological neural circuits, are observed just as in a typical two-section excitable laser. The demonstrated optical building block can pave the way for high-speed photonic integrated systems able to address tasks ranging from pattern recognition to cognitive spectrum management and multi-sensory data processing. PMID:27991574

Mechanically Flexible and High-Performance CMOS Logic Circuits.

PubMed

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-10-13

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth

NASA Astrophysics Data System (ADS)

Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

2010-05-01

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

Mechanically Flexible and High-Performance CMOS Logic Circuits

PubMed Central

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-01-01

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

Growth and high rate reactive ion etching of epitaxially grown barium hexaferrite films on single crystal silicon carbide substrates

NASA Astrophysics Data System (ADS)

Chen, Zhaohui

Ferrites are an invaluable group of insulating magnetic materials used for high frequency microwave applications in such passive electronic devices as isolators, phase shifters, and circulators. Because of their high permeability, non-reciprocal electromagnetic properties, and low eddy current losses, there are no other materials that serve such a broad range of applications. Until recently, they have been widely employed in bulk form, with little success in thin film-based applications in commercial or military microwave technologies. In today's technology, emerging electronic systems, such as high frequency, high power wireless and satellite communications (GPS, Bluetooth, WLAN, commercial radar, etc) thin film materials are in high demand. It is widely recognized that as high frequency devices shift to microwave frequencies the integration of passive devices with semiconductor electronics holds significant advantages in the realization of miniaturization, broader bandwidths, higher performance, speed, power and lower production costs. Thus, the primary objective of this thesis is to explore the integration of ferrite films with wide band gap semiconductor substrates for the realization of monolithic integrated circuits (MICs). This thesis focuses on two key steps for the integration of barium hexaferrite (Ba M-type or BaM) devices on semiconductor substrates. First, the development of high crystal quality ferrite film growth via pulsed laser deposition on wide band gap silicon carbide semiconductor substrates, and second, the effective patterning of BaM films using dry etching techniques. To address part one, BaM films were deposited on 6H silicon carbide (0001) substrates by Pulsed Laser Deposition. X-ray diffraction showed strong crystallographic alignment while pole figures exhibited reflections consistent with epitaxial growth. After optimized annealing, BaM films have a perpendicular magnetic anisotropy field of 16,900 Oe, magnetization (4piMs) of 4.4 kG, and ferromagnetic resonance peak-to-peak derivative linewidth at 53 GHz of 96 Oe. This combination of properties qualifies these films for microwave device applications. This marks the first growth of a microwave ferrite on SiC substrates and offers a new approach in the design and development of mu-wave and mm-wave monolithic integrated circuits. In part two, high-rate reactive ion etching using CHF3/SF6 gas mixtures was successfully demonstrated on BaM films, resulting in high aspect profile features of less than 50 nm in lateral dimension. These demonstrations enable the future integration of ferrites into MIC devices and technologies.

On-chip single photon filtering and multiplexing in hybrid quantum photonic circuits.

PubMed

Elshaari, Ali W; Zadeh, Iman Esmaeil; Fognini, Andreas; Reimer, Michael E; Dalacu, Dan; Poole, Philip J; Zwiller, Val; Jöns, Klaus D

2017-08-30

Quantum light plays a pivotal role in modern science and future photonic applications. Since the advent of integrated quantum nanophotonics different material platforms based on III-V nanostructures-, colour centers-, and nonlinear waveguides as on-chip light sources have been investigated. Each platform has unique advantages and limitations; however, all implementations face major challenges with filtering of individual quantum states, scalable integration, deterministic multiplexing of selected quantum emitters, and on-chip excitation suppression. Here we overcome all of these challenges with a hybrid and scalable approach, where single III-V quantum emitters are positioned and deterministically integrated in a complementary metal-oxide-semiconductor-compatible photonic circuit. We demonstrate reconfigurable on-chip single-photon filtering and wavelength division multiplexing with a foot print one million times smaller than similar table-top approaches, while offering excitation suppression of more than 95 dB and efficient routing of single photons over a bandwidth of 40 nm. Our work marks an important step to harvest quantum optical technologies' full potential.Combining different integration platforms on the same chip is currently one of the main challenges for quantum technologies. Here, Elshaari et al. show III-V Quantum Dots embedded in nanowires operating in a CMOS compatible circuit, with controlled on-chip filtering and tunable routing.

Wireless Low-Power Integrated Basal-Body-Temperature Detection Systems Using Teeth Antennas in the MedRadio Band.

PubMed

Yang, Chin-Lung; Zheng, Gou-Tsun

2015-11-20

This study proposes using wireless low power thermal sensors for basal-body-temperature detection using frequency modulated telemetry devices. A long-term monitoring sensor requires low-power circuits including a sampling circuit and oscillator. Moreover, temperature compensated technologies are necessary because the modulated frequency might have additional frequency deviations caused by the varying temperature. The temperature compensated oscillator is composed of a ring oscillator and a controlled-steering current source with temperature compensation, so the output frequency of the oscillator does not drift with temperature variations. The chip is fabricated in a standard Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm complementary metal oxide semiconductor (CMOS) process, and the chip area is 0.9 mm². The power consumption of the sampling amplifier is 128 µW. The power consumption of the voltage controlled oscillator (VCO) core is less than 40 µW, and the output is -3.04 dBm with a buffer stage. The output voltage of the bandgap reference circuit is 1 V. For temperature measurements, the maximum error is 0.18 °C with a standard deviation of ±0.061 °C, which is superior to the required specification of 0.1 °C.

Semiconductor electrolyte photovoltaic energy converter

NASA Technical Reports Server (NTRS)

Anderson, W. W.; Anderson, L. B.

1975-01-01

Feasibility and practicality of a solar cell consisting of a semiconductor surface in contact with an electrolyte are evaluated. Basic components and processes are detailed for photovoltaic energy conversion at the surface of an n-type semiconductor in contact with an electrolyte which is oxidizing to conduction band electrons. Characteristics of single crystal CdS, GaAs, CdSe, CdTe and thin film CdS in contact with aqueous and methanol based electrolytes are studied and open circuit voltages are measured from Mott-Schottky plots and open circuit photo voltages. Quantum efficiencies for short circuit photo currents of a CdS crystal and a 20 micrometer film are shown together with electrical and photovoltaic properties. Highest photon irradiances are observed with the GaAs cell.

European roadmap on superconductive electronics - status and perspectives

NASA Astrophysics Data System (ADS)

Anders, S.; Blamire, M. G.; Buchholz, F.-Im.; Crété, D.-G.; Cristiano, R.; Febvre, P.; Fritzsch, L.; Herr, A.; Il'ichev, E.; Kohlmann, J.; Kunert, J.; Meyer, H.-G.; Niemeyer, J.; Ortlepp, T.; Rogalla, H.; Schurig, T.; Siegel, M.; Stolz, R.; Tarte, E.; ter Brake, H. J. M.; Toepfer, H.; Villegier, J.-C.; Zagoskin, A. M.; Zorin, A. B.

2010-12-01

Executive SummaryFor four decades semiconductor electronics has followed Moore’s law: with each generation of integration the circuit features became smaller, more complex and faster. This development is now reaching a wall so that smaller is no longer any faster. The clock rate has saturated at about 3-5 GHz and the parallel processor approach will soon reach its limit. The prime reason for the limitation the semiconductor electronics experiences is not the switching speed of the individual transistor, but its power dissipation and thus heat. Digital superconductive electronics is a circuit- and device-technology that is inherently faster at much less power dissipation than semiconductor electronics. It makes use of superconductors and Josephson junctions as circuit elements, which can provide extremely fast digital devices in a frequency range - dependent on the material - of hundreds of GHz: for example a flip-flop has been demonstrated that operated at 750 GHz. This digital technique is scalable and follows similar design rules as semiconductor devices. Its very low power dissipation of only 0.1 μW per gate at 100 GHz opens the possibility of three-dimensional integration. Circuits like microprocessors and analogue-to-digital converters for commercial and military applications have been demonstrated. In contrast to semiconductor circuits, the operation of superconducting circuits is based on naturally standardized digital pulses the area of which is exactly the flux quantum Φ0. The flux quantum is also the natural quantization unit for digital-to-analogue and analogue-to-digital converters. The latter application is so precise, that it is being used as voltage standard and that the physical unit ‘Volt’ is defined by means of this standard. Apart from its outstanding features for digital electronics, superconductive electronics provides also the most sensitive sensor for magnetic fields: the Superconducting Quantum Interference Device (SQUID). Amongst many other applications SQUIDs are used as sensors for magnetic heart and brain signals in medical applications, as sensor for geological surveying and food-processing and for non-destructive testing. As amplifiers of electrical signals, SQUIDs can nearly reach the theoretical limit given by Quantum Mechanics. A further important field of application is the detection of very weak signals by ‘transition-edge’ bolometers, superconducting nanowire single-photon detectors, and superconductive tunnel junctions. Their application as radiation detectors in a wide frequency range, from microwaves to X-rays is now standard. The very low losses of superconductors have led to commercial microwave filter designs that are now widely used in the USA in base stations for cellular phones and in military communication applications. The number of demonstrated applications is continuously increasing and there is no area in professional electronics, in which superconductive electronics cannot be applied and surpasses the performance of classical devices. Superconductive electronics has to be cooled to very low temperatures. Whereas this was a bottleneck in the past, cooling techniques have made a huge step forward in recent years: very compact systems with high reliability and a wide range of cooling power are available commercially, from microcoolers of match-box size with milli-Watt cooling power to high-reliability coolers of many Watts of cooling power for satellite applications. Superconductive electronics will not replace semiconductor electronics and similar room-temperature techniques in standard applications, but for those applications which require very high speed, low-power consumption, extreme sensitivity or extremely high precision, superconductive electronics is superior to all other available techniques. To strengthen the European competitiveness in superconductor electronics research projects have to be set-up in the following field: Ultra-sensitive sensing and imaging. Quantum measurement instrumentation. Advanced analogue-to-digital converters. Superconductive electronics technology.

Testing methodologies and systems for semiconductor optical amplifiers

NASA Astrophysics Data System (ADS)

Wieckowski, Michael

Semiconductor optical amplifiers (SOA's) are gaining increased prominence in both optical communication systems and high-speed optical processing systems, due primarily to their unique nonlinear characteristics. This in turn, has raised questions regarding their lifetime performance reliability and has generated a demand for effective testing techniques. This is especially critical for industries utilizing SOA's as components for system-in-package products. It is important to note that very little research to date has been conducted in this area, even though production volume and market demand has continued to increase. In this thesis, the reliability of dilute-mode InP semiconductor optical amplifiers is studied experimentally and theoretically. The aging characteristics of the production level devices are demonstrated and the necessary techniques to accurately characterize them are presented. In addition, this work proposes a new methodology for characterizing the optical performance of these devices using measurements in the electrical domain. It is shown that optical performance degradation, specifically with respect to gain, can be directly qualified through measurements of electrical subthreshold differential resistance. This metric exhibits a linear proportionality to the defect concentration in the active region, and as such, can be used for prescreening devices before employing traditional optical testing methods. A complete theoretical analysis is developed in this work to explain this relationship based upon the device's current-voltage curve and its associated leakage and recombination currents. These results are then extended to realize new techniques for testing semiconductor optical amplifiers and other similarly structured devices. These techniques can be employed after fabrication and during packaged operation through the use of a proposed stand-alone testing system, or using a proposed integrated CMOS self-testing circuit. Both methods are capable of ascertaining SOA performance based solely on the subthreshold differential resistance signature, and are a first step toward the inevitable integration of self-testing circuits into complex optoelectronic systems.

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

PubMed

Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

2012-07-01

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Magnetic-free non-reciprocity based on staggered commutation

PubMed Central

Reiskarimian, Negar; Krishnaswamy, Harish

2016-01-01

Lorentz reciprocity is a fundamental characteristic of the vast majority of electronic and photonic structures. However, non-reciprocal components such as isolators, circulators and gyrators enable new applications ranging from radio frequencies to optical frequencies, including full-duplex wireless communication and on-chip all-optical information processing. Such components today dominantly rely on the phenomenon of Faraday rotation in magneto-optic materials. However, they are typically bulky, expensive and not suitable for insertion in a conventional integrated circuit. Here we demonstrate magnetic-free linear passive non-reciprocity based on the concept of staggered commutation. Commutation is a form of parametric modulation with very high modulation ratio. We observe that staggered commutation enables time-reversal symmetry breaking within very small dimensions (λ/1,250 × λ/1,250 in our device), resulting in a miniature radio-frequency circulator that exhibits reduced implementation complexity, very low loss, strong non-reciprocity, significantly enhanced linearity and real-time reconfigurability, and is integrated in a conventional complementary metal–oxide–semiconductor integrated circuit for the first time. PMID:27079524

Computer-Aided Engineering of Semiconductor Integrated Circuits

DTIC Science & Technology

1979-07-01

equation using a five point finite difference approximation. Section 4.3.6 describes the numerical techniques and iterative algorithms which are used...neighbor points. This is generally referred to as a five point finite difference scheme on a rectangular grid, as described below. The finite difference ...problems in steady state have been analyzed by the finite difference method [4. 16 ] [4.17 3 or finite element method [4. 18 3, [4. 19 3 as reported last

Computer Aided Engineering of Semiconductor Integrated Circuits

DTIC Science & Technology

1976-04-01

from that of the ideal charge-contrpl model. Application of the test developed here to a practical MOS NAND gate demonstrates marked violations of...defining properties: [31] J. E. Meyer, RCA Review, 321, 42 (1971). [32] R.S.C. Cobbold , Theory and Applications of Field-Effect Transistors...decrease of thxs dxs- I ’ [!] H.K.J. Ihantola and J. L. Moll, Solid State Electronics, 7, 423 (1964). [2] R.S.C. Cobbold , Theory and

Government-Imposed Barriers to the Use of Commercial Integrated Circuits in Military Systems.

DTIC Science & Technology

1996-02-01

Advanced Planning Briefing for Industry (undated). The FY94/FY95 research agenda of the Microprocessor Technology Utiliza- tion Program includes... planning and re- sults. As a model of how a private institute might operate, we suggest (without implying partiality) the Semiconductor Research...or incorporate lessons learned). Those IC suppliers passing the audit are listed on the QML. Products from QML-listed suppliers can be used with

III-V Semiconductor Optical Micro-Ring Resonators

NASA Astrophysics Data System (ADS)

Grover, Rohit; Absil, Philippe P.; Ibrahim, Tarek A.; Ho, Ping-Tong

2004-05-01

We describe the theory of optical ring resonators, and our work on GaAs-AlGaAs and GaInAsP-InP optical micro-ring resonators. These devices are promising building blocks for future all-optical signal processing and photonic logic circuits. Their versatility allows the fabrication of ultra-compact multiplexers/demultiplexers, optical channel dropping filters, lasers, amplifiers, and logic gates (to name a few), which will enable large-scale monolithic integration for optics.

Chip-scale sensor system integration for portable health monitoring.

PubMed

Jokerst, Nan M; Brooke, Martin A; Cho, Sang-Yeon; Shang, Allan B

2007-12-01

The revolution in integrated circuits over the past 50 yr has produced inexpensive computing and communications systems that are powerful and portable. The technologies for these integrated chip-scale sensing systems, which will be miniature, lightweight, and portable, are emerging with the integration of sensors with electronics, optical systems, micromachines, microfluidics, and the integration of chemical and biological materials (soft/wet material integration with traditional dry/hard semiconductor materials). Hence, we stand at a threshold for health monitoring technology that promises to provide wearable biochemical sensing systems that are comfortable, inauspicious, wireless, and battery-operated, yet that continuously monitor health status, and can transmit compressed data signals at regular intervals, or alarm conditions immediately. In this paper, we explore recent results in chip-scale sensor integration technology for health monitoring. The development of inexpensive chip-scale biochemical optical sensors, such as microresonators, that are customizable for high sensitivity coupled with rapid prototyping will be discussed. Ground-breaking work in the integration of chip-scale optical systems to support these optical sensors will be highlighted, and the development of inexpensive Si complementary metal-oxide semiconductor circuitry (which makes up the vast majority of computational systems today) for signal processing and wireless communication with local receivers that lie directly on the chip-scale sensor head itself will be examined.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Excitability and optical pulse generation in semiconductor lasers driven by resonant tunneling diode photo-detectors.

PubMed

Romeira, Bruno; Javaloyes, Julien; Ironside, Charles N; Figueiredo, José M L; Balle, Salvador; Piro, Oreste

2013-09-09

We demonstrate, experimentally and theoretically, excitable nanosecond optical pulses in optoelectronic integrated circuits operating at telecommunication wavelengths (1550 nm) comprising a nanoscale double barrier quantum well resonant tunneling diode (RTD) photo-detector driving a laser diode (LD). When perturbed either electrically or optically by an input signal above a certain threshold, the optoelectronic circuit generates short electrical and optical excitable pulses mimicking the spiking behavior of biological neurons. Interestingly, the asymmetric nonlinear characteristic of the RTD-LD allows for two different regimes where one obtain either single pulses or a burst of multiple pulses. The high-speed excitable response capabilities are promising for neurally inspired information applications in photonics.

Characteristics of High-Resolution Hemoglobin Measurement Microchip Integrated with Signal Processing Circuit

NASA Astrophysics Data System (ADS)

Noda, Toshihiko; Takao, Hidekuni; Ashiki, Mitsuaki; Ebi, Hiroyuki; Sawada, Kazuaki; Ishida, Makoto

2004-04-01

In this study, a microchip for measurement of hemoglobin in human blood has been proposed, fabricated and evaluated. The measurement principle of hemoglobin is based on the “cyanmethemoglobin method” that calculates the cyanmethemoglobin concentration by absorption photometry. A glass/silicon/silicon structure was used for the microchip. The middle silicon layer includes flow channels, and 45° mirrors formed at each end of the flow channels. Photodiodes and metal oxide semiconductor (MOS) integrated circuits were fabricated on the bottom silicon layer. The performance of the microchip for hemoglobin measurement was evaluated using a solution of red food color instead of a real blood sample. The fabricated microchip exhibited a similar performance to a nonminiaturized absorption cell which has the same optical path length. Signal processing output varied with solution concentration from 5.32 V to 5.55 V with very high stability due to differential signal processing.

Micro and nano devices in passive millimetre wave imaging systems

NASA Astrophysics Data System (ADS)

Appleby, R.

2013-06-01

The impact of micro and nano technology on millimetre wave imaging from the post war years to the present day is reviewed. In the 1950s whisker contacted diodes in mixers and vacuum tubes were used to realise both radiometers and radars but required considerable skill to realise the performance needed. Development of planar semiconductor devices such as Gunn and Schottky diodes revolutionised mixer performance and provided considerable improvement. The next major breakthrough was high frequency transistors based on gallium arsenide which were initially used at intermediate frequencies but later after further development at millimeter wave frequencies. More recently Monolithic Microwave Integrated circuits(MMICs) offer exceptional performance and the opportunity for innovative design in passive imaging systems. In the future the use of micro and nano technology will continue to drive system performance and we can expect to see integration of antennae, millimetre wave and sub millimetre wave circuits and signal processing.

Recent progress in GeSn growth and GeSn-based photonic devices

NASA Astrophysics Data System (ADS)

Zheng, Jun; Liu, Zhi; Xue, Chunlai; Li, Chuanbo; Zuo, Yuhua; Cheng, Buwen; Wang, Qiming

2018-06-01

The GeSn binary alloy is a new group IV material that exhibits a direct bandgap when the Sn content exceeds 6%. It shows great potential for laser use in optoelectronic integration circuits (OEIC) on account of its low light emission efficiency arising from the indirect bandgap characteristics of Si and Ge. The bandgap of GeSn can be tuned from 0.6 to 0 eV by varying the Sn content, thus making this alloy suitable for use in near-infrared and mid-infrared detectors. In this paper, the growth of the GeSn alloy is first reviewed. Subsequently, GeSn photodetectors, light emitting diodes, and lasers are discussed. The GeSn alloy presents a promising pathway for the monolithic integration of Si photonic circuits by the complementary metal–oxide–semiconductor (CMOS) technology. Project supported by the Beijing Natural Science Foundation (No. 4162063) and the Youth Innovation Promotion Association of CAS (No. 2015091).

Fabrication of Circuit QED Quantum Processors, Part 2: Advanced Semiconductor Manufacturing Perspectives

NASA Astrophysics Data System (ADS)

Michalak, D. J.; Bruno, A.; Caudillo, R.; Elsherbini, A. A.; Falcon, J. A.; Nam, Y. S.; Poletto, S.; Roberts, J.; Thomas, N. K.; Yoscovits, Z. R.; Dicarlo, L.; Clarke, J. S.

Experimental quantum computing is rapidly approaching the integration of sufficient numbers of quantum bits for interesting applications, but many challenges still remain. These challenges include: realization of an extensible design for large array scale up, sufficient material process control, and discovery of integration schemes compatible with industrial 300 mm fabrication. We present recent developments in extensible circuits with vertical delivery. Toward the goal of developing a high-volume manufacturing process, we will present recent results on a new Josephson junction process that is compatible with current tooling. We will then present the improvements in NbTiN material uniformity that typical 300 mm fabrication tooling can provide. While initial results on few-qubit systems are encouraging, advanced processing control is expected to deliver the improvements in qubit uniformity, coherence time, and control required for larger systems. Research funded by Intel Corporation.

A 0.2 V Micro-Electromechanical Switch Enabled by a Phase Transition.

PubMed

Dong, Kaichen; Choe, Hwan Sung; Wang, Xi; Liu, Huili; Saha, Bivas; Ko, Changhyun; Deng, Yang; Tom, Kyle B; Lou, Shuai; Wang, Letian; Grigoropoulos, Costas P; You, Zheng; Yao, Jie; Wu, Junqiao

2018-04-01

Micro-electromechanical (MEM) switches, with advantages such as quasi-zero leakage current, emerge as attractive candidates for overcoming the physical limits of complementary metal-oxide semiconductor (CMOS) devices. To practically integrate MEM switches into CMOS circuits, two major challenges must be addressed: sub 1 V operating voltage to match the voltage levels in current circuit systems and being able to deliver at least millions of operating cycles. However, existing sub 1 V mechanical switches are mostly subject to significant body bias and/or limited lifetimes, thus failing to meet both limitations simultaneously. Here 0.2 V MEM switching devices with ≳10 6 safe operating cycles in ambient air are reported, which achieve the lowest operating voltage in mechanical switches without body bias reported to date. The ultralow operating voltage is mainly enabled by the abrupt phase transition of nanolayered vanadium dioxide (VO 2 ) slightly above room temperature. The phase-transition MEM switches open possibilities for sub 1 V hybrid integrated devices/circuits/systems, as well as ultralow power consumption sensors for Internet of Things applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

PubMed Central

Dai, Ching-Liang; Chen, Yen-Chi; Wu, Chyan-Chyi; Kuo, Chin-Fu

2010-01-01

The study presents a micro carbon monoxide (CO) sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT) film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively. PMID:22294897

Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

Cobalt oxide nanosheet and CNT micro carbon monoxide sensor integrated with readout circuit on chip.

PubMed

Dai, Ching-Liang; Chen, Yen-Chi; Wu, Chyan-Chyi; Kuo, Chin-Fu

2010-01-01

The study presents a micro carbon monoxide (CO) sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT) film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

A memristor-based nonvolatile latch circuit

NASA Astrophysics Data System (ADS)

Robinett, Warren; Pickett, Matthew; Borghetti, Julien; Xia, Qiangfei; Snider, Gregory S.; Medeiros-Ribeiro, Gilberto; Williams, R. Stanley

2010-06-01

Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

Advanced testing of the DEPFET minimatrix particle detector

NASA Astrophysics Data System (ADS)

Andricek, L.; Kodyš, P.; Koffmane, C.; Ninkovic, J.; Oswald, C.; Richter, R.; Ritter, A.; Rummel, S.; Scheirich, J.; Wassatsch, A.

2012-01-01

The DEPFET (DEPleted Field Effect Transistor) is an active pixel particle detector with a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is gained this way. The DEPFET sensor will be used as a vertex detector in the Belle II experiment at SuperKEKB, electron-positron collider in Japan. The vertex detector will be composed of two layers of pixel detectors (DEPFET) and four layers of strip detectors. The DEPFET sensor requires switching and current readout circuits for its operation. These circuits have been designed as ASICs (Application Specific Integrated Circuits) in several different versions, but they provide insufficient flexibility for precise detector testing. Therefore, a test system with a flexible control cycle range and minimal noise has been designed for testing and characterizing of small detector prototypes (Minimatrices). Sensors with different design layouts and thicknesses are produced in order to evaluate and select the one with the best performance for the Belle II application. Description of the test system as well as measurement results are presented.

Flexible ambipolar organic field-effect transistors with reverse-offset-printed silver electrodes for a complementary inverter.

PubMed

Park, Junsu; Kim, Minseok; Yeom, Seung-Won; Ha, Hyeon Jun; Song, Hyenggun; Min Jhon, Young; Kim, Yun-Hi; Ju, Byeong-Kwon

2016-06-03

We report ambipolar organic field-effect transistors and complementary inverter circuits with reverse-offset-printed (ROP) Ag electrodes fabricated on a flexible substrate. A diketopyrrolopyrrole-based co-polymer (PDPP-TAT) was used as the semiconductor and poly(methyl methacrylate) was used as the gate insulator. Considerable improvement is observed in the n-channel electrical characteristics by inserting a cesium carbonate (Cs2CO3) as the electron-injection/hole-blocking layer at the interface between the semiconductors and the electrodes. The saturation mobility values are 0.35 cm(2) V(-1) s(-1) for the p-channel and 0.027 cm(2) V(-1) s(-1) for the n-channel. A complementary inverter is demonstrated based on the ROP process, and it is selectively controlled by the insertion of Cs2CO3 onto the n-channel region via thermal evaporation. Moreover, the devices show stable operation during the mechanical bending test using tensile strains ranging from 0.05% to 0.5%. The results confirm that these devices have great potential for use in flexible and inexpensive integrated circuits over a large area.

Self-similar and fractal design for stretchable electronics

DOEpatents

Rogers, John A.; Fan, Jonathan; Yeo, Woon-Hong; Su, Yewang; Huang, Yonggang; Zhang, Yihui

2017-04-04

The present invention provides electronic circuits, devices and device components including one or more stretchable components, such as stretchable electrical interconnects, electrodes and/or semiconductor components. Stretchability of some of the present systems is achieved via a materials level integration of stretchable metallic or semiconducting structures with soft, elastomeric materials in a configuration allowing for elastic deformations to occur in a repeatable and well-defined way. The stretchable device geometries and hard-soft materials integration approaches of the invention provide a combination of advance electronic function and compliant mechanics supporting a broad range of device applications including sensing, actuation, power storage and communications.

High-performance, mechanically flexible, and vertically integrated 3D carbon nanotube and InGaZnO complementary circuits with a temperature sensor.

PubMed

Honda, Wataru; Harada, Shingo; Ishida, Shohei; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-08-26

A vertically integrated inorganic-based flexible complementary metal-oxide-semiconductor (CMOS) inverter with a temperature sensor with a high inverter gain of ≈50 and a low power consumption of <7 nW mm(-1) is demonstrated using a layer-by-layer assembly process. In addition, the negligible influence of the mechanical flexibility on the performance of the CMOS inverter and the temperature dependence of the CMOS inverter characteristics are discussed. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Architectures for Improved Organic Semiconductor Devices

NASA Astrophysics Data System (ADS)

Beck, Jonathan H.

Advancements in the microelectronics industry have brought increasing performance and decreasing prices to a wide range of users. Conventional silicon-based electronics have followed Moore's law to provide an ever-increasing integrated circuit transistor density, which drives processing power, solid-state memory density, and sensor technologies. As shrinking conventional integrated circuits became more challenging, researchers began exploring electronics with the potential to penetrate new applications with a low price of entry: "Electronics everywhere." The new generation of electronics is thin, light, flexible, and inexpensive. Organic electronics are part of the new generation of thin-film electronics, relying on the synthetic flexibility of carbon molecules to create organic semiconductors, absorbers, and emitters which perform useful tasks. Organic electronics can be fabricated with low energy input on a variety of novel substrates, including inexpensive plastic sheets. The potential ease of synthesis and fabrication of organic-based devices means that organic electronics can be made at very low cost. Successfully demonstrated organic semiconductor devices include photovoltaics, photodetectors, transistors, and light emitting diodes. Several challenges that face organic semiconductor devices are low performance relative to conventional devices, long-term device stability, and development of new organic-compatible processes and materials. While the absorption and emission performance of organic materials in photovoltaics and light emitting diodes is extraordinarily high for thin films, the charge conduction mobilities are generally low. Building highly efficient devices with low-mobility materials is one challenge. Many organic semiconductor films are unstable during fabrication, storage, and operation due to reactions with water, oxygen and hydroxide. A final challenge facing organic electronics is the need for new processes and materials for electrodes, semiconductors and substrates compatible with low-temperature, flexible, and oxygenated and aromatic solvent-free fabrication. Materials and processes must be capable of future high volume production in order to enable low costs. In this thesis we explore several techniques to improve organic semiconductor device performance and enable new fabrication processes. In Chapter 2, I describe the integration of sub-optical-wavelength nanostructured electrodes that improve fill factor and power conversion efficiency in organic photovoltaic devices. Photovoltaic fill factor performance is one of the primary challenges facing organic photovoltaics because most organic semiconductors have poor charge mobility. Our electrical and optical measurements and simulations indicate that nanostructured electrodes improve charge extraction in organic photovoltaics. In Chapter 3, I describe a general method for maximizing the efficiency of organic photovoltaic devices by simultaneously optimizing light absorption and charge carrier collection. We analyze the potential benefits of light trapping strategies for maximizing the overall power conversion efficiency of organic photovoltaic devices. This technique may be used to improve organic photovoltaic materials with low absorption, or short exciton diffusion and carrier-recombination lengths, opening up the device design space. In Chapter 4, I describe a process for high-quality graphene transfer onto chemically sensitive, weakly interacting organic semiconductor thin-films. Graphene is a promising flexible and highly transparent electrode for organic electronics; however, transferring graphene films onto organic semiconductor devices was previously impossible. We demonstrate a new transfer technique based on an elastomeric stamp coated with an fluorinated polymer release layer. We fabricate three classes of organic semiconductor devices: field effect transistors without high temperature annealing, transparent organic light-emitting diodes, and transparent small-molecule organic photovoltaic devices.

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

PubMed

Nakazato, Kazuo

2014-03-28

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

NASA Astrophysics Data System (ADS)

Heck, Martijn J. R.

2017-01-01

Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

Resistivity analysis

DOEpatents

Bruce, Michael R [Austin, TX; Bruce, Victoria J [Austin, TX; Ring, Rosalinda M [Austin, TX; Cole, Edward Jr I [Albuquerque, NM; Hawkins, Charles F [Albuquerque, NM; Tangyungong, Paiboon [Albuquerque, NM

2006-06-13

According to an example embodiment of the present invention a semiconductor die having a resistive electrical connection is analyzed. Heat is directed to the die as the die is undergoing a state-changing operation to cause a failure due to suspect circuitry. The die is monitored, and a circuit path that electrically changes in response to the heat is detected and used to detect that a particular portion therein of the circuit is resistive. In this manner, the detection and localization of a semiconductor die defect that includes a resistive portion of a circuit path is enhanced.

Measurement science and manufacturing science research

NASA Technical Reports Server (NTRS)

Phillips, D. Howard

1987-01-01

The research program of Semiconductor Research Corp. is managed as three overlapping areas: Manufacturing Sciences, Design Sciences and Microstructure Sciences. A total of 40 universities are participating in the performance of over 200 research tasks. The goals and direction of Manufacturing Sciences research became more clearly focused through the efforts of the Manufacturing Sciences Committee of the SRC Technical Advisory Board (TAB). The mission of the SRC Manufacturing Research is the quantification, control, and understanding of semiconductor manufacturing process necessary to achieve a predictable and profitable product output in the competitive environment of the next decade. The 1994 integrated circuit factory must demonstrate a three level hierarchy of control: (1) operation control, (2) process control, and (3) process design. These levels of control are briefly discussed.

Future reticle demand and next-generation lithography technologies

NASA Astrophysics Data System (ADS)

Behringer, Uwe F. W.; Ehrlich, Christian; Fortange, Olaf

1999-04-01

Mask technology has often been considered an enabling for semiconductor fabrication. But today photomasks have evolved to a bottle neck in the every increasing integration process of semiconductor circuits. Regarding to the 1997 SIA roadmap there are very stringent requirements for mask making. Even with the momentary weak Asian market the worldwide demand for reticles will continue to grow. The anticipation of larger reticles has been discussed over years. What ever the reason for the need of larger reticles, the move to the 230 mm X 230 mm reticle size will provide size will provide unique challenges to both the mask equipment manufacturers and mask fabricator. Next Generation Lithography together with their mask techniques are in development and try to come into the market.

Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling.

PubMed

Koswatta, Siyuranga O; Lundstrom, Mark S; Nikonov, Dmitri E

2007-05-01

Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the nonequilibrium Green's function formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (J. Am. Chem. Soc. 2006, 128, 3518-3519), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by optical phonon assisted inelastic transport, which can have important implications on the transistor characteristics. It is shown that, under large biasing conditions, two-phonon scattering may also become important.

Bacteria inside semiconductors as potential sensor elements: biochip progress.

PubMed

Sah, Vasu R; Baier, Robert E

2014-06-24

It was discovered at the beginning of this Century that living bacteria-and specifically the extremophile Pseudomonas syzgii-could be captured inside growing crystals of pure water-corroding semiconductors-specifically germanium-and thereby initiated pursuit of truly functional "biochip-based" biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips.

Aerosol-jet-printed, 1 volt H-bridge drive circuit on plastic with integrated electrochromic pixel.

PubMed

Ha, Mingjing; Zhang, Wei; Braga, Daniele; Renn, Michael J; Kim, Chris H; Frisbie, C Daniel

2013-12-26

In this report, we demonstrate a printed, flexible, and low-voltage circuit that successfully drives a polymer electrochromic (EC) pixel as large as 4 mm(2) that is printed on the same substrate. All of the key components of the drive circuitry, namely, resistors, capacitors, and transistors, were aerosol-jet-printed onto a plastic foil; metallic electrodes and interconnects were the only components prepatterned on the plastic by conventional photolithography. The large milliampere drive currents necessary to switch a 4 mm(2) EC pixel were controlled by printed electrolyte-gated transistors (EGTs) that incorporate printable ion gels for the gate insulator layers and poly(3-hexylthiophene) for the semiconductor channels. Upon application of a 1 V input pulse, the circuit switches the printed EC pixel ON (red) and OFF (blue) two times in approximately 4 s. The performance of the circuit and the behavior of the individual resistors, capacitors, EGTs, and the EC pixel are analyzed as functions of the printing parameters and operating conditions.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

CMOL: A New Concept for Nanoelectronics

NASA Astrophysics Data System (ADS)

Likharev, Konstantin

2005-03-01

I will review the recent work on devices and architectures for future hybrid semiconductor/molecular integrated circuits, in particular those of ``CMOL'' variety [1]. Such circuits would combine an advanced CMOS subsystem fabricated by the usual lithographic patterning, two layers of parallel metallic nanowires formed, e.g., by nanoimprint, and two-terminal molecular devices self-assembled on the nanowire crosspoints. Estimates show that this powerful combination may allow CMOL circuits to reach an unparalleled density (up to 10^12 functions per cm^2) and ultrahigh rate of information processing (up to 10^20 operations per second on a single chip), at acceptable power dissipation. The main challenges on the way toward practical CMOL technology are: (i) reliable chemically-directed self-assembly of mid-size organic molecules, and (ii) the development of efficient defect-tolerant architectures for CMOL circuits. Our recent work has shown that such architectures may be developed not only for terabit-scale memories and naturally defect-tolerant mixed-signal neuromorphic networks, but (rather unexpectedly) also for FPGA-style digital Boolean circuits. [1] For details, see http://rsfq1.physics.sunysb.edu/˜likharev/nano/Springer04.pdf

Influence of Asymmetric Contact Form on Contact Resistance and Schottky Barrier, and Corresponding Applications of Diode.

PubMed

Zhao, Yudan; Xiao, Xiaoyang; Huo, Yujia; Wang, Yingcheng; Zhang, Tianfu; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan; Li, Qunqing

2017-06-07

We have fabricated carbon nanotube and MoS 2 field-effect transistors with asymmetric contact forms of source-drain electrodes, from which we found the current directionality of the devices and different contact resistances under the two current directions. By designing various structures, we can conclude that the asymmetric electrical performance was caused by the difference in the effective Schottky barrier height (Φ SB ) caused by the different contact forms. A detailed temperature-dependent study was used to extract and compare the Φ SB for both contact forms of CNT and MoS 2 devices; we found that the Φ SB for the metal-on-semiconductor form was much lower than that of the semiconductor-on-metal form and is suitable for all p-type, n-type, or ambipolar semiconductors. This conclusion is meaningful with respect to the design and application of nanomaterial electronic devices. Additionally, using the difference in barrier height caused by the contact forms, we have also proposed and fabricated Schottky barrier diodes with a current ratio up to 10 4 ; rectifying circuits consisting of these diodes were able to work in a wide frequency range. This design avoided the use of complex chemical doping or heterojunction methods to achieve fundamental diodes that are relatively simple and use only a single material; these may be suitable for future application in nanoelectronic radio frequency or integrated circuits.

Epitaxial growth of 100-μm thick M-type hexaferrite crystals on wide bandgap semiconductor GaN/Al{sub 2}O{sub 3} substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Bolin; Su, Zhijuan; Bennett, Steve

2014-05-07

Thick barium hexaferrite BaFe{sub 12}O{sub 19} (BaM) films having thicknesses of ∼100 μm were epitaxially grown on GaN/Al{sub 2}O{sub 3} substrates from a molten-salt solution by vaporizing the solvent. X-ray diffraction measurement verified the growth of BaM (001) textured growth of thick films. Saturation magnetization, 4πM{sub s}, was measured for as-grown films to be 4.6 ± 0.2 kG and ferromagnetic resonance measurements revealed a microwave linewidth of ∼100 Oe at X-band. Scanning electron microscopy indicated clear hexagonal crystals distributed on the semiconductor substrate. These results demonstrate feasibility of growing M-type hexaferrite crystal films on wide bandgap semiconductor substrates by using a simplemore » powder melting method. It also presents a potential pathway for the integration of ferrite microwave passive devices with active semiconductor circuit elements creating system-on-a-wafer architectures.« less

Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates

DOEpatents

Rogers, John A; Cao, Qing; Alam, Muhammad; Pimparkar, Ninad

2015-02-03

The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Digital Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors.

PubMed

Tremblay, Noah J; Jung, Byung Jun; Breysse, Patrick; Katz, Howard E

2011-11-22

Chemiresistors and sensitive OFETs have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Here we report higher order logic circuits utilizing OFETs sensitive to amine vapors. The circuits depend on the synergistic responses of paired p- and n-channel organic semiconductors, including an unprecedented analyte-induced current increase by the n-channel semiconductor. This represents the first step towards 'intelligent sensors' that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations.

Digital Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors

PubMed Central

Tremblay, Noah J.; Jung, Byung Jun; Breysse, Patrick; Katz, Howard E.

2013-01-01

Chemiresistors and sensitive OFETs have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Here we report higher order logic circuits utilizing OFETs sensitive to amine vapors. The circuits depend on the synergistic responses of paired p- and n-channel organic semiconductors, including an unprecedented analyte-induced current increase by the n-channel semiconductor. This represents the first step towards ‘intelligent sensors’ that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations. PMID:23754969

Extraction of carrier mobility and interface trap density in InGaAs metal oxide semiconductor structures using gated Hall method

NASA Astrophysics Data System (ADS)

Chidambaram, Thenappan

III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for D it and mobility. Here we employ gated Hall method to quantify the D it spectrum at the high-K oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values.

Inverter circuits on freestanding flexible substrate using ZnO nanoparticles for cost-efficient electronics

NASA Astrophysics Data System (ADS)

Vidor, Fábio F.; Meyers, Thorsten; Müller, Kathrin; Wirth, Gilson I.; Hilleringmann, Ulrich

2017-11-01

Driven by the Internet of Things (IoT), flexible and transparent smart systems have been intensively researched by the scientific community and by several companies. This technology is already available for consumers in a wide range of innovative products, e.g., flexible displays, radio-frequency identification tags and wearable electronic skins which, for instance, collect and analyze data for medical applications. For these systems, thin-film transistors (TFTs) are the key elements responsible for the driving currents. Solution-based materials such as nanoparticle dispersions avail the fabrication on large-area substrates with high throughput processes. In this study, we discuss the integration of ZnO nanoparticle thin-film transistors and inverter circuits on freestanding polymeric substrates enclosing the main issues concerning the transfer of the integration process from a rigid substrate to a flexible one. The TFTs depict VON between -0.2 and 1 V, ION/IOFF > 104 and field-effect mobility >0.5 cm2 V-1 s-1. Additionally, in order to enhance the transistors and inverters performance, an adaptation on the device configuration, from an inverted coplanar to an inverted staggered setup, was conducted and analyzed. By employing the inverted staggered setup a considerable increase in the contact quality between the semiconductor and the drain and source electrodes was observed. As the integrated devices depict electrical characteristics which enable the fabrication of electronic circuits for the low-cost sector, inverters were fabricated and characterized, evaluating the circuit's gain as function of the applied supply voltage and circuit's geometric ratio.

Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

NASA Astrophysics Data System (ADS)

Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

2018-01-01

We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1-200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

Ethanol Microsensors with a Readout Circuit Manufactured Using the CMOS-MEMS Technique

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang

2015-01-01

The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS)-microelectro-mechanical system (MEMS) technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm. PMID:25594598

Ethanol microsensors with a readout circuit manufactured using the CMOS-MEMS technique.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang

2015-01-14

The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS)-microelectro -mechanical system (MEMS) technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm.

Reset Tree-Based Optical Fault Detection

PubMed Central

Lee, Dong-Geon; Choi, Dooho; Seo, Jungtaek; Kim, Howon

2013-01-01

In this paper, we present a new reset tree-based scheme to protect cryptographic hardware against optical fault injection attacks. As one of the most powerful invasive attacks on cryptographic hardware, optical fault attacks cause semiconductors to misbehave by injecting high-energy light into a decapped integrated circuit. The contaminated result from the affected chip is then used to reveal secret information, such as a key, from the cryptographic hardware. Since the advent of such attacks, various countermeasures have been proposed. Although most of these countermeasures are strong, there is still the possibility of attack. In this paper, we present a novel optical fault detection scheme that utilizes the buffers on a circuit's reset signal tree as a fault detection sensor. To evaluate our proposal, we model radiation-induced currents into circuit components and perform a SPICE simulation. The proposed scheme is expected to be used as a supplemental security tool. PMID:23698267

An improved low-voltage ride-through performance of DFIG based wind plant using stator dynamic composite fault current limiter.

PubMed

Gayen, P K; Chatterjee, D; Goswami, S K

2016-05-01

In this paper, an enhanced low-voltage ride-through (LVRT) performance of a grid connected doubly fed induction generator (DFIG) has been presented with the usage of stator dynamic composite fault current limiter (SDCFCL). This protection circuit comprises of a suitable series resistor-inductor combination and parallel bidirectional semiconductor switch. The SDCFCL facilitates double benefits such as reduction of rotor induced open circuit voltage due to increased value of stator total inductance and concurrent increase of rotor impedance. Both effects will limit rotor circuit over current and over voltage situation more secured way in comparison to the conventional scheme like the dynamic rotor current limiter (RCL) during any type of fault situation. The proposed concept is validated through the simulation study of the grid integrated 2.0MW DFIG. Copyright © 2016 ISA. Published by Elsevier Ltd. All rights reserved.

Electrically-driven GHz range ultrafast graphene light emitter (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kim, Youngduck; Gao, Yuanda; Shiue, Ren-Jye; Wang, Lei; Aslan, Ozgur Burak; Kim, Hyungsik; Nemilentsau, Andrei M.; Low, Tony; Taniguchi, Takashi; Watanabe, Kenji; Bae, Myung-Ho; Heinz, Tony F.; Englund, Dirk R.; Hone, James

2017-02-01

Ultrafast electrically driven light emitter is a critical component in the development of the high bandwidth free-space and on-chip optical communications. Traditional semiconductor based light sources for integration to photonic platform have therefore been heavily studied over the past decades. However, there are still challenges such as absence of monolithic on-chip light sources with high bandwidth density, large-scale integration, low-cost, small foot print, and complementary metal-oxide-semiconductor (CMOS) technology compatibility. Here, we demonstrate the first electrically driven ultrafast graphene light emitter that operate up to 10 GHz bandwidth and broadband range (400 1600 nm), which are possible due to the strong coupling of charge carriers in graphene and surface optical phonons in hBN allow the ultrafast energy and heat transfer. In addition, incorporation of atomically thin hexagonal boron nitride (hBN) encapsulation layers enable the stable and practical high performance even under the ambient condition. Therefore, electrically driven ultrafast graphene light emitters paves the way towards the realization of ultrahigh bandwidth density photonic integrated circuits and efficient optical communications networks.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

PubMed

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Adaptive neuro fuzzy inference system-based power estimation method for CMOS VLSI circuits

NASA Astrophysics Data System (ADS)

Vellingiri, Govindaraj; Jayabalan, Ramesh

2018-03-01

Recent advancements in very large scale integration (VLSI) technologies have made it feasible to integrate millions of transistors on a single chip. This greatly increases the circuit complexity and hence there is a growing need for less-tedious and low-cost power estimation techniques. The proposed work employs Back-Propagation Neural Network (BPNN) and Adaptive Neuro Fuzzy Inference System (ANFIS), which are capable of estimating the power precisely for the complementary metal oxide semiconductor (CMOS) VLSI circuits, without requiring any knowledge on circuit structure and interconnections. The ANFIS to power estimation application is relatively new. Power estimation using ANFIS is carried out by creating initial FIS modes using hybrid optimisation and back-propagation (BP) techniques employing constant and linear methods. It is inferred that ANFIS with the hybrid optimisation technique employing the linear method produces better results in terms of testing error that varies from 0% to 0.86% when compared to BPNN as it takes the initial fuzzy model and tunes it by means of a hybrid technique combining gradient descent BP and mean least-squares optimisation algorithms. ANFIS is the best suited for power estimation application with a low RMSE of 0.0002075 and a high coefficient of determination (R) of 0.99961.

Microwave processed NiMg ferrite: Studies on structural and magnetic properties

NASA Astrophysics Data System (ADS)

Chandra Babu Naidu, K.; Madhuri, W.

2016-12-01

Ferrites are magnetic semiconductors realizing an important role in electrical and electronic circuits where electrical and magnetic property coupling is required. Though ferrite materials are known for a long time, there is a large scope in the improvement of their properties (vice sintering and frequency dependence of electrical and magnetic properties) with the current technological trends. Forth coming technology is aimed at miniaturization and smart gadgets, electrical components like inductors and transformers cannot be included in integrated circuits. These components are incorporated into the circuit as surface mount devices whose fabrication involves low temperature co-firing of ceramics and microwave monolithic integrated circuits technologies. These technologies demand low temperature sinter-ability of ferrites. This article presents low temperature microwave sintered Ni-Mg ferrites of general chemical formula Ni1-xMgxFe2O4 (x=0, 0.2, 0.4, 0.5, 0.6, 0.8, 1) for potential applications as transformer core materials. The series of ferrites are characterized using X-ray diffractometer, scanning electron microscopy, Fourier transform infrared and vibrating sample magnetometer for investigating structural, morphological and magnetic properties respectively. The initial permeability is studied with magnesium content, temperature and frequency in the temperature range of 308 K-873 K and 42 Hz-5 MHz.

A fully integrated oven controlled microelectromechanical oscillator -- Part I. Design and fabrication

DOE PAGES

Wojciechowski, Kenneth E.; Baker, Michael S.; Clews, Peggy J.; ...

2015-06-24

Our paper reports the design and fabrication of a fully integrated oven controlled microelectromechanical oscillator (OCMO). This paper begins by describing the limits on oscillator frequency stability imposed by the thermal drift and electronic properties (Q, resistance) of both the resonant tank circuit and feedback electronics required to form an electronic oscillator. An OCMO is presented that takes advantage of high thermal isolation and monolithic integration of both micromechanical resonators and electronic circuitry to thermally stabilize or ovenize all the components that comprise an oscillator. This was achieved by developing a processing technique where both silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) circuitrymore » and piezoelectric aluminum nitride, AlN, micromechanical resonators are placed on a suspended platform within a standard CMOS integrated circuit. Operation at microscale sizes achieves high thermal resistances (~10 °C/mW), and hence thermal stabilization of the oscillators at very low-power levels when compared with the state-of-the-art ovenized crystal oscillators, OCXO. This constant resistance feedback circuit is presented that incorporates on platform resistive heaters and temperature sensors to both measure and stabilize the platform temperature. Moreover, the limits on temperature stability of the OCMO platform and oscillator frequency imposed by the gain of the constant resistance feedback loop, placement of the heater and temperature sensing resistors, as well as platform radiative and convective heat losses are investigated.« less

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, Michael L.; Rose, Benny H.; Craft, David C.; Enquist, Paul M.; Slater, Jr., David B.

1997-01-01

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

NASA Technical Reports Server (NTRS)

Vasile, Stefan; Lipson, Jerold

2012-01-01

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, M.L.; Rose, B.H.; Craft, D.C.; Enquist, P.M.; Slater, D.B. Jr.

1997-11-04

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1,000 Mb/s or more. 4 figs.

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

NASA Technical Reports Server (NTRS)

Olson, E. M.

1986-01-01

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

The record of electrical and communication engineering conversazione Tohoku University Volume 63, No. 3

NASA Astrophysics Data System (ADS)

1995-05-01

English abstracts contained are from papers authored by the research staff of the Research Institute of Electrical Communication and the departments of Electrical Engineering, Electrical Communications, Electronic Engineering, and Information Engineering, Tohoku University, which originally appeared in scientific journals in 1994. The abstracts are organized under the following disciplines: electromagnetic theory; physics; fundamental theory of information; communication theory and systems; signal and image processing; systems control; computers; artificial intelligence; recording; acoustics and speech; ultrasonic electronics; antenna, propagation, and transmission; optoelectronics and optical communications; quantum electronics; superconducting materials and applications; magnetic materials and magnetics; semiconductors; electronic materials and parts; electronic devices and integrated circuits; electronic circuits; medical electronics and bionics; measurements and applied electronics; electric power; and miscellaneous.

Active-Pixel Image Sensor With Analog-To-Digital Converters

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

1995-01-01

Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formedmore » with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.« less

Direct oriented growth of armchair graphene nanoribbons on germanium

PubMed Central

Jacobberger, Robert M.; Kiraly, Brian; Fortin-Deschenes, Matthieu; Levesque, Pierre L.; McElhinny, Kyle M.; Brady, Gerald J.; Rojas Delgado, Richard; Singha Roy, Susmit; Mannix, Andrew; Lagally, Max G.; Evans, Paul G.; Desjardins, Patrick; Martel, Richard; Hersam, Mark C.; Guisinger, Nathan P.; Arnold, Michael S.

2015-01-01

Graphene can be transformed from a semimetal into a semiconductor if it is confined into nanoribbons narrower than 10 nm with controlled crystallographic orientation and well-defined armchair edges. However, the scalable synthesis of nanoribbons with this precision directly on insulating or semiconducting substrates has not been possible. Here we demonstrate the synthesis of graphene nanoribbons on Ge(001) via chemical vapour deposition. The nanoribbons are self-aligning 3° from the Ge〈110〉 directions, are self-defining with predominantly smooth armchair edges, and have tunable width to <10 nm and aspect ratio to >70. In order to realize highly anisotropic ribbons, it is critical to operate in a regime in which the growth rate in the width direction is especially slow, <5 nm h−1. This directional and anisotropic growth enables nanoribbon fabrication directly on conventional semiconductor wafer platforms and, therefore, promises to allow the integration of nanoribbons into future hybrid integrated circuits. PMID:26258594

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

PubMed

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High density circuit technology, part 3

NASA Technical Reports Server (NTRS)

Wade, T. E.

1982-01-01

Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.

Silicon Technologies Adjust to RF Applications

NASA Technical Reports Server (NTRS)

Reinecke Taub, Susan; Alterovitz, Samuel A.

1994-01-01

Silicon (Si), although not traditionally the material of choice for RF and microwave applications, has become a serious challenger to other semiconductor technologies for high-frequency applications. Fine-line electron- beam and photolithographic techniques are now capable of fabricating silicon gate sizes as small as 0.1 micron while commonly-available high-resistivity silicon wafers support low-loss microwave transmission lines. These advances, coupled with the recent development of silicon-germanium (SiGe), arm silicon integrated circuits (ICs) with the speed required for increasingly higher-frequency applications.

The 1.06 micrometer avalanche photodiode detectors with integrated circuit preamplifiers

NASA Technical Reports Server (NTRS)

Eden, R. C.

1975-01-01

The development of a complete solid state 1.06 micron optical receiver which can be used in optical communications at data rates approaching 1.5 Gb/s, or in other applications requiring sensitive, short-pulse detection, is reported. This work entailed both the development of a new type of heterojunction 3-5 semiconductor alloy avalanche photodiode and an extremely charge-sensitive wideband low-noise preamp design making use of GaAs Schottky barrier-gate field effect transistors.

Optics education for machine operators in the semiconductor industry: moving beyond button pushing

NASA Astrophysics Data System (ADS)

Karakekes, Meg; Currier, Deborah

1995-10-01

In the competitive semiconductor manufacturing industry, employees who operate equipment are able to make greater contributions if they understand how the equipment works. By understanding the 'why' behind the 'what', the equipment operators can better partner with other technical staff to produce quality integrated circuits efficiently and effectively. This additional knowledge also opens equipment operators to job enrichment and enlargement opportunities. Advanced Micro Devices (AMD) is in the process of upgrading the skills of its equipment operators. This paper is an overview of a pilot program that employs optics education to upgrade stepper operators' skills. The paper starts with stepper tasks that require optics knowledge, examines teaching methods, reports both end-of-course and three months post-training knowledge retention, and summarizes how the training has impacted the production floor.

Patterning and templating for nanoelectronics.

PubMed

Galatsis, Kosmas; Wang, Kang L; Ozkan, Mihri; Ozkan, Cengiz S; Huang, Yu; Chang, Jane P; Monbouquette, Harold G; Chen, Yong; Nealey, Paul; Botros, Youssry

2010-02-09

The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top-down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top-down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next-generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.

Development of UItra-Low Temperature Motor Controllers: Ultra Low Temperatures Evaluation and Characterization of Semiconductor Technologies For The Next Generation Space Telescope

NASA Technical Reports Server (NTRS)

Elbuluk, Malik E.

2003-01-01

Electronics designed for low temperature operation will result in more efficient systems than room temperature. This improvement is a result of better electronic, electrical, and thermal properties of materials at low temperatures. In particular, the performance of certain semiconductor devices improves with decreasing temperature down to ultra-low temperature (-273 'C). The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components and systems suitable for applications in deep space missions. Research is being conducted on devices and systems for use down to liquid helium temperatures (-273 'C). Some of the components that are being characterized include semiconductor switching devices, resistors, magnetics, and capacitors. The work performed this summer has focused on the evaluation of silicon-, silicon-germanium- and gallium-Arsenide-based (GaAs) bipolar, MOS and CMOS discrete components and integrated circuits (ICs), from room temperature (23 'C) down to ultra low temperatures (-263 'C).

Product manufacturing, quality, and reliability initiatives to maintain a competitive advantage and meet customer expectations in the semiconductor industry

NASA Astrophysics Data System (ADS)

Capps, Gregory

Semiconductor products are manufactured and consumed across the world. The semiconductor industry is constantly striving to manufacture products with greater performance, improved efficiency, less energy consumption, smaller feature sizes, thinner gate oxides, and faster speeds. Customers have pushed towards zero defects and require a more reliable, higher quality product than ever before. Manufacturers are required to improve yields, reduce operating costs, and increase revenue to maintain a competitive advantage. Opportunities exist for integrated circuit (IC) customers and manufacturers to work together and independently to reduce costs, eliminate waste, reduce defects, reduce warranty returns, and improve quality. This project focuses on electrical over-stress (EOS) and re-test okay (RTOK), two top failure return mechanisms, which both make great defect reduction opportunities in customer-manufacturer relationship. Proactive continuous improvement initiatives and methodologies are addressed with emphasis on product life cycle, manufacturing processes, test, statistical process control (SPC), industry best practices, customer education, and customer-manufacturer interaction.

Fabrication of semiconductor-polymer compound nonlinear photonic crystal slab with highly uniform infiltration based on nano-imprint lithography technique.

PubMed

Qin, Fei; Meng, Zi-Ming; Zhong, Xiao-Lan; Liu, Ye; Li, Zhi-Yuan

2012-06-04

We present a versatile technique based on nano-imprint lithography to fabricate high-quality semiconductor-polymer compound nonlinear photonic crystal (NPC) slabs. The approach allows one to infiltrate uniformly polystyrene materials that possess large Kerr nonlinearity and ultrafast nonlinear response into the cylindrical air holes with diameter of hundred nanometers that are perforated in silicon membranes. Both the structural characterization via the cross-sectional scanning electron microscopy images and the optical characterization via the transmission spectrum measurement undoubtedly show that the fabricated compound NPC samples have uniform and dense polymer infiltration and are of high quality in optical properties. The compound NPC samples exhibit sharp transmission band edges and nondegraded high quality factor of microcavities compared with those in the bare silicon PC. The versatile method can be expanded to make general semiconductor-polymer hybrid optical nanostructures, and thus it may pave the way for reliable and efficient fabrication of ultrafast and ultralow power all-optical tunable integrated photonic devices and circuits.

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

NASA Technical Reports Server (NTRS)

Taylor, B.

1990-01-01

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Two-Dimensional Metal-Free Organic Multiferroic Material for Design of Multifunctional Integrated Circuits.

PubMed

Tu, Zhengyuan; Wu, Menghao; Zeng, Xiao Cheng

2017-05-04

Coexistence of ferromagnetism and ferroelectricity in a single 2D material is highly desirable for integration of multifunctional units in 2D material-based circuits. We report theoretical evidence of C 6 N 8 H organic network as being the first 2D organic multiferroic material with coexisting ferromagnetic and ferroelectric properties. The ferroelectricity stems from multimode proton-transfer within the 2D C 6 N 8 H network, in which a long-range proton-transfer mode is enabled by the facilitation of oxygen molecule when the network is exposed to the air. Such oxygen-assisted ferroelectricity also leads to a high Curie temperature and coupling between ferroelectricity and ferromagnetism. We also find that hydrogenation and carbon doping can transform the 2D g-C 3 N 4 network from an insulator to an n-type/p-type magnetic semiconductor with modest bandgap. Akin to the dopant induced n/p channels in silicon wafer, a variety of dopant created functional units can be integrated into the g-C 3 N 4 wafer by design for nanoelectronic applications.

A miniaturized neuroprosthesis suitable for implantation into the brain

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Binkley, David; Blalock, Benjamin; Andersen, Richard; Ulshoefer, Norbert; Johnson, Travis; Del Castillo, Linda

2003-01-01

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400-microm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1 degree C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

NASA Astrophysics Data System (ADS)

Ellinger, Frank; Fritsche, David; Tretter, Gregor; Leufker, Jan Dirk; Yodprasit, Uroschanit; Carta, C.

2017-01-01

In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

Communications technology

NASA Astrophysics Data System (ADS)

Sokoloski, Martin M.

1988-09-01

The objective of the Communications Technology Program is to enable data transmission to and from low Earth orbit, geostationary orbit, and solar and deep space missions. This can be achieved by maintaining an effective, balances effort in basic, applied, and demonstration prototype communications technology through work in theory, experimentation, and components. The program consists of three major research and development discipline areas which are: microwave and millimeter wave tube components; solid state monolithic integrated circuit; and free space laser communications components and devices. The research ranges from basic research in surface physics (to study the mechanisms of surface degradation from under high temperature and voltage operating conditions which impacts cathode tube reliability and lifetime) to generic research on the dynamics of electron beams and circuits (for exploitation in various micro- and millimeter wave tube devices). Work is also performed on advanced III-V semiconductor materials and devices for use in monolithic integrated analog circuits (used in adaptive, programmable phased arrays for microwave antenna feeds and receivers) - on the use of electromagnetic theory in antennas and on technology necessary for eventual employment of lasers for free space communications for future low earth, geostationary, and deep space missions requiring high data rates with corresponding directivity and reliability.

Communications technology

NASA Technical Reports Server (NTRS)

Sokoloski, Martin M.

1988-01-01

The objective of the Communications Technology Program is to enable data transmission to and from low Earth orbit, geostationary orbit, and solar and deep space missions. This can be achieved by maintaining an effective, balances effort in basic, applied, and demonstration prototype communications technology through work in theory, experimentation, and components. The program consists of three major research and development discipline areas which are: microwave and millimeter wave tube components; solid state monolithic integrated circuit; and free space laser communications components and devices. The research ranges from basic research in surface physics (to study the mechanisms of surface degradation from under high temperature and voltage operating conditions which impacts cathode tube reliability and lifetime) to generic research on the dynamics of electron beams and circuits (for exploitation in various micro- and millimeter wave tube devices). Work is also performed on advanced III-V semiconductor materials and devices for use in monolithic integrated analog circuits (used in adaptive, programmable phased arrays for microwave antenna feeds and receivers) - on the use of electromagnetic theory in antennas and on technology necessary for eventual employment of lasers for free space communications for future low earth, geostationary, and deep space missions requiring high data rates with corresponding directivity and reliability.

Sensors for process control Focus Team report

NASA Astrophysics Data System (ADS)

At the Semiconductor Technology Workshop, held in November 1992, the Semiconductor Industry Association (SIA) convened 179 semiconductor technology experts to assess the 15-year outlook for the semiconductor manufacturing industry. The output of the Workshop, a document entitled 'Semiconductor Technology: Workshop Working Group Reports,' contained an overall roadmap for the technology characteristics envisioned in integrated circuits (IC's) for the period 1992-2007. In addition, the document contained individual roadmaps for numerous key areas in IC manufacturing, such as film deposition, thermal processing, manufacturing systems, exposure technology, etc. The SIA Report did not contain a separate roadmap for contamination free manufacturing (CFM). A key component of CFM for the next 15 years is the use of sensors for (1) defect reduction, (2) improved product quality, (3) improved yield, (4) improved tool utilization through contamination reduction, and (5) real time process control in semiconductor fabrication. The objective of this Focus Team is to generate a Sensors for Process Control Roadmap. Implicit in this objective is the identification of gaps in current sensor technology so that research and development activity in the sensor industry can be stimulated to develop sensor systems capable of meeting the projected roadmap needs. Sensor performance features of interest include detection limit, specificity, sensitivity, ease of installation and maintenance, range, response time, accuracy, precision, ease and frequency of calibration, degree of automation, and adaptability to in-line process control applications.

Tunneling effect on double potential barriers GaAs and PbS

NASA Astrophysics Data System (ADS)

Prastowo, S. H. B.; Supriadi, B.; Ridlo, Z. R.; Prihandono, T.

2018-04-01

A simple model of transport phenomenon tunnelling effect through double barrier structure was developed. In this research we concentrate on the variation of electron energy which entering double potential barriers to transmission coefficient. The barriers using semiconductor materials GaAs (Galium Arsenide) with band-gap energy 1.424 eV, distance of lattice 0.565 nm, and PbS (Lead Sulphide) with band gap energy 0.41 eV distance of lattice is 18 nm. The Analysisof tunnelling effect on double potentials GaAs and PbS using Schrodinger’s equation, continuity, and matrix propagation to get transmission coefficient. The maximum energy of electron that we use is 1.0 eV, and observable from 0.0025 eV- 1.0 eV. The shows the highest transmission coefficient is0.9982 from electron energy 0.5123eV means electron can pass the barriers with probability 99.82%. Semiconductor from materials GaAs and PbS is one of selected material to design semiconductor device because of transmission coefficient directly proportional to bias the voltage of semiconductor device. Application of the theoretical analysis of resonant tunnelling effect on double barriers was used to design and develop new structure and combination of materials for semiconductor device (diode, transistor, and integrated circuit).

Entanglement distribution schemes employing coherent photon-to-spin conversion in semiconductor quantum dot circuits

NASA Astrophysics Data System (ADS)

Gaudreau, Louis; Bogan, Alex; Korkusinski, Marek; Studenikin, Sergei; Austing, D. Guy; Sachrajda, Andrew S.

2017-09-01

Long distance entanglement distribution is an important problem for quantum information technologies to solve. Current optical schemes are known to have fundamental limitations. A coherent photon-to-spin interface built with quantum dots (QDs) in a direct bandgap semiconductor can provide a solution for efficient entanglement distribution. QD circuits offer integrated spin processing for full Bell state measurement (BSM) analysis and spin quantum memory. Crucially the photo-generated spins can be heralded by non-destructive charge detection techniques. We review current schemes to transfer a polarization-encoded state or a time-bin-encoded state of a photon to the state of a spin in a QD. The spin may be that of an electron or that of a hole. We describe adaptations of the original schemes to employ heavy holes which have a number of attractive properties including a g-factor that is tunable to zero for QDs in an appropriately oriented external magnetic field. We also introduce simple throughput scaling models to demonstrate the potential performance advantage of full BSM capability in a QD scheme, even when the quantum memory is imperfect, over optical schemes relying on linear optical elements and ensemble quantum memories.

Research progress of Ge on insulator grown by rapid melting growth

NASA Astrophysics Data System (ADS)

Liu, Zhi; Wen, Juanjuan; Li, Chuanbo; Xue, Chunlai; Cheng, Buwen

2018-06-01

Ge is an attractive material for Si-based microelectronics and photonics due to its high carries mobility, pseudo direct bandgap structure, and the compatibility with complementary metal oxide semiconductor (CMOS) processes. Based on Ge, Ge on insulator (GOI) not only has these advantages, but also provides strong electronic and optical confinement. Recently, a novel technique to fabricate GOI by rapid melting growth (RMG) has been described. Here, we introduce the RMG technique and review recent efforts and progress in RMG. Firstly, we will introduce process steps of RMG. We will then review the researches which focus on characterizations of the GOI including growth dimension, growth mechanism, growth orientation, concentration distribution, and strain status. Finally, GOI based applications including high performance metal–oxide–semiconductor field effect transistors (MOSFETs) and photodetectors will be discussed. These results show that RMG is a promising technique for growth of high quality GOIs with different characterizations. The GOI grown by RMG is a potential material for the next-generation of integrated circuits and optoelectronic circuits. Project supported in part by the National Key Research and Development Program of China (No. 2017YFA0206404) and the National Natural Science Foundation of China (Nos. 61435013, 61534005, 61534004, 61604146).

Career Opportunities for Physicists in the Micro Electronics Industry

NASA Astrophysics Data System (ADS)

Bourianoff, George

1997-10-01

The US micro electronics industry anticipates growth of 20 to 30 percent per year for the next five years. The need for engineers and scientists poses a critical problem for the industry but conversely presents great opportunities for those in closely related fields such as physics where career opportunities may be more limited. There is no shortage of important and challenging problems on the Semiconductor Institute of America (SIA) roadmap which will require solution in the next 10 years and which require expertise in the physical sciences. However, significant cultural differences exist between the physics community and the engineering oriented semiconductor community which must be understood and addressed in order for a physicist to successfully contribute in this environment. This talk will identify some of those cultural differences and describe some of the critical physics related problems which must be solved. Critical roadblocks include lithographic patterning below 0.18m. and design of Very Large Scale Integrated (VLSI) circuits in the deep submicron regime. The former will require developing radiation sources and optical elements for the EUV or XRAY part of the spectrum. The latter will require incorporating electromagnetic field equations with traditional lumped element circuit design methods. The cultural barriers alluded to earlier involve the manner in which engineering detail is approached. A physicist's basic instinct is to strip off the detail in order to make a problem mathematically tractable. This enables understanding of the underlying physical relationships but does not yield the quantitative detail necessary in semiconductor production.

InP-based photonic integrated circuit platform on SiC wafer.

PubMed

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Directed self-assembly of block copolymers for nanolithography: fabrication of isolated features and essential integrated circuit geometries.

PubMed

Stoykovich, Mark P; Kang, Huiman; Daoulas, Kostas Ch; Liu, Guoliang; Liu, Chi-Chun; de Pablo, Juan J; Müller, Marcus; Nealey, Paul F

2007-10-01

Self-assembling block copolymers are of interest for nanomanufacturing due to the ability to realize sub-100 nm dimensions, thermodynamic control over the size and uniformity and density of features, and inexpensive processing. The insertion point of these materials in the production of integrated circuits, however, is often conceptualized in the short term for niche applications using the dense periodic arrays of spots or lines that characterize bulk block copolymer morphologies, or in the long term for device layouts completely redesigned into periodic arrays. Here we show that the domain structure of block copolymers in thin films can be directed to assemble into nearly the complete set of essential dense and isolated patterns as currently defined by the semiconductor industry. These results suggest that block copolymer materials, with their intrinsically advantageous self-assembling properties, may be amenable for broad application in advanced lithography, including device layouts used in existing nanomanufacturing processes.

Antenna-coupled Superconducting Bolometers for Observations of the Cosmic Microwave Background Polarization

NASA Astrophysics Data System (ADS)

Myers, Michael James

We describe the development of a novel millimeter-wave cryogenic detector. The device integrates a planar antenna, superconducting transmission line, bandpass filter, and bolometer onto a single silicon wafer. The bolometer uses a superconducting Transition-Edge Sensor (TES) thermistor, which provides substantial advantages over conventional semiconductor bolometers. The detector chip is fabricated using standard micro-fabrication techniques. This highly-integrated detector architecture is particularly well-suited for use in the de- velopment of polarization-sensitive cryogenic receivers with thousands of pixels. Such receivers are needed to meet the sensitivity requirements of next-generation cosmic microwave background polarization experiments. The design, fabrication, and testing of prototype array pixels are described. Preliminary considerations for a full array design are also discussed. A set of on-chip millimeter-wave test structures were developed to help understand the performance of our millimeter-wave microstrip circuits. These test structures produce a calibrated transmission measurement for an arbitrary two-port circuit using optical techniques, rather than a network analyzer. Some results of fabricated test structures are presented.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment.

PubMed

Porrazzo, Rossella; Luzio, Alessandro; Bellani, Sebastiano; Bonacchini, Giorgio Ernesto; Noh, Yong-Young; Kim, Yun-Hi; Lanzani, Guglielmo; Antognazza, Maria Rosa; Caironi, Mario

2017-01-31

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm -2 in full accumulation and a mobility-capacitance product of 7 × 10 -3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation.

Electron-beam-evaporated thin films of hafnium dioxide for fabricating electronic devices

DOE PAGES

Xiao, Zhigang; Kisslinger, Kim

2015-06-17

Thin films of hafnium dioxide (HfO 2) are widely used as the gate oxide in fabricating integrated circuits because of their high dielectric constants. In this paper, the authors report the growth of thin films of HfO 2 using e-beam evaporation, and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using this HfO 2 thin film as the gate oxide. The authors analyzed the thin films using high-resolution transmission electron microscopy and electron diffraction, thereby demonstrating that the e-beam-evaporation-grown HfO 2 film has a polycrystalline structure and forms an excellent interface with silicon. Accordingly, we fabricated 31-stage CMOS ringmore » oscillator to test the quality of the HfO 2 thin film as the gate oxide, and obtained excellent rail-to-rail oscillation waveforms from it, denoting that the HfO 2 thin film functioned very well as the gate oxide.« less

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment

PubMed Central

2017-01-01

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm–2 in full accumulation and a mobility–capacitance product of 7 × 10–3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation. PMID:28180187

MOSFET analog memory circuit achieves long duration signal storage

NASA Technical Reports Server (NTRS)

1966-01-01

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

PubMed

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-05-09

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

PubMed Central

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-01-01

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

MOS Circuitry Would Detect Low-Energy Charged Particles

NASA Technical Reports Server (NTRS)

Sinha, Mahadeva; Wadsworth, Mark

2003-01-01

Metal oxide semiconductor (MOS) circuits for measuring spatially varying intensities of beams of low-energy charged particles have been developed. These circuits are intended especially for use in measuring fluxes of ions with spatial resolution along the focal planes of mass spectrometers. Unlike prior mass spectrometer focal-plane detectors, these MOS circuits would not be based on ion-induced generation of electrons, and photons; instead, they would be based on direct detection of the electric charges of the ions. Hence, there would be no need for microchannel plates (for ion-to-electron conversion), phosphors (for electron-to-photon conversion), and photodetectors (for final detection) -- components that degrade spatial resolution and contribute to complexity and size. The developmental circuits are based on linear arrays of charge-coupled devices (CCDs) with associated readout circuitry (see figure). They resemble linear CCD photodetector arrays, except that instead of a photodetector, each pixel contains a capacitive charge sensor. The capacitor in each sensor comprises two electrodes (typically made of aluminum) separated by a layer of insulating material. The exposed electrode captures ions and accumulates their electric charges during signal-integration periods.

Recent Progress in the Development of Printed Thin-Film Transistors and Circuits with High-Resolution Printing Technology.

PubMed

Fukuda, Kenjiro; Someya, Takao

2017-07-01

Printed electronics enable the fabrication of large-scale, low-cost electronic devices and systems, and thus offer significant possibilities in terms of developing new electronics/optics applications in various fields. Almost all electronic applications require information processing using logic circuits. Hence, realizing the high-speed operation of logic circuits is also important for printed devices. This report summarizes recent progress in the development of printed thin-film transistors (TFTs) and integrated circuits in terms of materials, printing technologies, and applications. The first part of this report gives an overview of the development of functional inks such as semiconductors, electrodes, and dielectrics. The second part discusses high-resolution printing technologies and strategies to enable high-resolution patterning. The main focus of this report is on obtaining printed electrodes with high-resolution patterning and the electrical performance of printed TFTs using such printed electrodes. In the final part, some applications of printed electronics are introduced to exemplify their potential. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Deep-Sea Video Cameras Without Pressure Housings

NASA Technical Reports Server (NTRS)

Cunningham, Thomas

2004-01-01

Underwater video cameras of a proposed type (and, optionally, their light sources) would not be housed in pressure vessels. Conventional underwater cameras and their light sources are housed in pods that keep the contents dry and maintain interior pressures of about 1 atmosphere (.0.1 MPa). Pods strong enough to withstand the pressures at great ocean depths are bulky, heavy, and expensive. Elimination of the pods would make it possible to build camera/light-source units that would be significantly smaller, lighter, and less expensive. The depth ratings of the proposed camera/light source units would be essentially unlimited because the strengths of their housings would no longer be an issue. A camera according to the proposal would contain an active-pixel image sensor and readout circuits, all in the form of a single silicon-based complementary metal oxide/semiconductor (CMOS) integrated- circuit chip. As long as none of the circuitry and none of the electrical leads were exposed to seawater, which is electrically conductive, silicon integrated- circuit chips could withstand the hydrostatic pressure of even the deepest ocean. The pressure would change the semiconductor band gap by only a slight amount . not enough to degrade imaging performance significantly. Electrical contact with seawater would be prevented by potting the integrated-circuit chip in a transparent plastic case. The electrical leads for supplying power to the chip and extracting the video signal would also be potted, though not necessarily in the same transparent plastic. The hydrostatic pressure would tend to compress the plastic case and the chip equally on all sides; there would be no need for great strength because there would be no need to hold back high pressure on one side against low pressure on the other side. A light source suitable for use with the camera could consist of light-emitting diodes (LEDs). Like integrated- circuit chips, LEDs can withstand very large hydrostatic pressures. If power-supply regulators or filter capacitors were needed, these could be attached in chip form directly onto the back of, and potted with, the imager chip. Because CMOS imagers dissipate little power, the potting would not result in overheating. To minimize the cost of the camera, a fixed lens could be fabricated as part of the plastic case. For improved optical performance at greater cost, an adjustable glass achromatic lens would be mounted in a reservoir that would be filled with transparent oil and subject to the full hydrostatic pressure, and the reservoir would be mounted on the case to position the lens in front of the image sensor. The lens would by adjusted for focus by use of a motor inside the reservoir (oil-filled motors already exist).

High-Temperature Electronics: A Role for Wide Bandgap Semiconductors?

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Okojie, Robert S.; Chen, Liang-Yu

2002-01-01

It is increasingly recognized that semiconductor based electronics that can function at ambient temperatures higher than 150 C without external cooling could greatly benefit a variety of important applications, especially-in the automotive, aerospace, and energy production industries. The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300 C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog very large scale integrated circuits in this temperature range. However, practical operation of silicon power devices at ambient temperatures above 200 C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once the technology for realizing these devices become sufficiently developed that they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Schwank, James R.; Fleetwood, Daniel M.; Shaneyfelt, Marty R.; Winokur, Peter S.; Devine, Roderick A. B.

1998-01-01

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

Bacteria Inside Semiconductors as Potential Sensor Elements: Biochip Progress

PubMed Central

Sah, Vasu R.; Baier, Robert E.

2014-01-01

It was discovered at the beginning of this Century that living bacteria—and specifically the extremophile Pseudomonas syzgii—could be captured inside growing crystals of pure water-corroding semiconductors—specifically germanium—and thereby initiated pursuit of truly functional “biochip-based” biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips. PMID:24961215

Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation.

PubMed

Kim, Jongpal; Kim, Jihoon; Ko, Hyoungho

2015-12-31

To overcome light interference, including a large DC offset and ambient light variation, a robust photoplethysmogram (PPG) readout chip is fabricated using a 0.13-μm complementary metal-oxide-semiconductor (CMOS) process. Against the large DC offset, a saturation detection and current feedback circuit is proposed to compensate for an offset current of up to 30 μA. For robustness against optical path variation, an automatic emitted light compensation method is adopted. To prevent ambient light interference, an alternating sampling and charge redistribution technique is also proposed. In the proposed technique, no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26.4 μW and has an input referred current noise of 260 pArms.

Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation

PubMed Central

Kim, Jongpal; Kim, Jihoon; Ko, Hyoungho

2015-01-01

To overcome light interference, including a large DC offset and ambient light variation, a robust photoplethysmogram (PPG) readout chip is fabricated using a 0.13-μm complementary metal–oxide–semiconductor (CMOS) process. Against the large DC offset, a saturation detection and current feedback circuit is proposed to compensate for an offset current of up to 30 μA. For robustness against optical path variation, an automatic emitted light compensation method is adopted. To prevent ambient light interference, an alternating sampling and charge redistribution technique is also proposed. In the proposed technique, no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26.4 μW and has an input referred current noise of 260 pArms. PMID:26729122

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

Integration and manufacture of multifunctional planar lightwave circuits

NASA Astrophysics Data System (ADS)

Lipscomb, George F.; Ticknor, Anthony J.; Stiller, Marc A.; Chen, Wenjie; Schroeter, Paul

2001-11-01

The demands of exponentially growing Internet traffic, coupled with the advent of Dense Wavelength Division Multiplexing (DWDM) fiber optic systems to meet those demands, have triggered a revolution in the telecommunications industry. This dramatic change has been built upon, and has driven, improvements in fiber optic component technology. The next generation of systems for the all optical network will require higher performance components coupled with dramatically lower costs. One approach to achieve significantly lower costs per function is to employ Planar Lightwave Circuits (PLC) to integrate multiple optical functions in a single package. PLCs are optical circuits laid out on a silicon wafer, and are made using tools and techniques developed to extremely high levels by the semi-conductor industry. In this way multiple components can be fabricated and interconnected at once, significantly reducing both the manufacturing and the packaging/assembly costs. Currently, the predominant commercial application of PLC technology is arrayed-waveguide gratings (AWG's) for multiplexing and demultiplexing multiple wavelength channels in a DWDM system. Although this is generally perceived as a single-function device, it can be performing the function of more than 100 discrete fiber-optic components and already represents a considerable degree of integration. Furthermore, programmable functions such as variable-optical attenuators (VOAs) and switches made with compatible PLC technology are now moving into commercial production. In this paper, we present results on the integration of active and passive functions together using PLC technology, e.g. a 40 channel AWG multiplexer with 40 individually controllable VOAs.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

CIRCUS--A digital computer program for transient analysis of electronic circuits

NASA Technical Reports Server (NTRS)

Moore, W. T.; Steinbert, L. L.

1968-01-01

Computer program simulates the time domain response of an electronic circuit to an arbitrary forcing function. CIRCUS uses a charge-control parameter model to represent each semiconductor device. Given the primary photocurrent, the transient behavior of a circuit in a radiation environment is determined.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Perspective: The future of quantum dot photonic integrated circuits

NASA Astrophysics Data System (ADS)

Norman, Justin C.; Jung, Daehwan; Wan, Yating; Bowers, John E.

2018-03-01

Direct epitaxial integration of III-V materials on Si offers substantial manufacturing cost and scalability advantages over heterogeneous integration. The challenge is that epitaxial growth introduces high densities of crystalline defects that limit device performance and lifetime. Quantum dot lasers, amplifiers, modulators, and photodetectors epitaxially grown on Si are showing promise for achieving low-cost, scalable integration with silicon photonics. The unique electrical confinement properties of quantum dots provide reduced sensitivity to the crystalline defects that result from III-V/Si growth, while their unique gain dynamics show promise for improved performance and new functionalities relative to their quantum well counterparts in many devices. Clear advantages for using quantum dot active layers for lasers and amplifiers on and off Si have already been demonstrated, and results for quantum dot based photodetectors and modulators look promising. Laser performance on Si is improving rapidly with continuous-wave threshold currents below 1 mA, injection efficiencies of 87%, and output powers of 175 mW at 20 °C. 1500-h reliability tests at 35 °C showed an extrapolated mean-time-to-failure of more than ten million hours. This represents a significant stride toward efficient, scalable, and reliable III-V lasers on on-axis Si substrates for photonic integrate circuits that are fully compatible with complementary metal-oxide-semiconductor (CMOS) foundries.

Non- contacting capacitive diagnostic device

DOEpatents

Ellison, Timothy

2005-07-12

A non-contacting capacitive diagnostic device includes a pulsed light source for producing an electric field in a semiconductor or photovoltaic device or material to be evaluated and a circuit responsive to the electric field. The circuit is not in physical contact with the device or material being evaluated and produces an electrical signal characteristic of the electric field produced in the device or material. The diagnostic device permits quality control and evaluation of semiconductor or photovoltaic device properties in continuous manufacturing processes.

Ratiometric, filter-free optical sensor based on a complementary metal oxide semiconductor buried double junction photodiode.

PubMed

Yung, Ka Yi; Zhan, Zhiyong; Titus, Albert H; Baker, Gary A; Bright, Frank V

2015-07-16

We report a complementary metal oxide semiconductor integrated circuit (CMOS IC) with a buried double junction (BDJ) photodiode that (i) provides a real-time output signal that is related to the intensity ratio at two emission wavelengths and (ii) simultaneously eliminates the need for an optical filter to block Rayleigh scatter. We demonstrate the BDJ platform performance for gaseous NH3 and aqueous pH detection. We also compare the BDJ performance to parallel results obtained by using a slew scanned fluorimeter (SSF). The BDJ results are functionally equivalent to the SSF results without the need for any wavelength filtering or monochromators and the BDJ platform is not prone to errors associated with source intensity fluctuations or sensor signal drift. Copyright © 2015 Elsevier B.V. All rights reserved.

Testbed Experiment for SPIDER: A Photonic Integrated Circuit-based Interferometric imaging system

NASA Astrophysics Data System (ADS)

Badham, K.; Duncan, A.; Kendrick, R. L.; Wuchenich, D.; Ogden, C.; Chriqui, G.; Thurman, S. T.; Su, T.; Lai, W.; Chun, J.; Li, S.; Liu, G.; Yoo, S. J. B.

The Lockheed Martin Advanced Technology Center (LM ATC) and the University of California at Davis (UC Davis) are developing an electro-optical (EO) imaging sensor called SPIDER (Segmented Planar Imaging Detector for Electro-optical Reconnaissance) that seeks to provide a 10x to 100x size, weight, and power (SWaP) reduction alternative to the traditional bulky optical telescope and focal-plane detector array. The substantial reductions in SWaP would reduce cost and/or provide higher resolution by enabling a larger-aperture imager in a constrained volume. Our SPIDER imager replaces the traditional optical telescope and digital focal plane detector array with a densely packed interferometer array based on emerging photonic integrated circuit (PIC) technologies that samples the object being imaged in the Fourier domain (i.e., spatial frequency domain), and then reconstructs an image. Our approach replaces the large optics and structures required by a conventional telescope with PICs that are accommodated by standard lithographic fabrication techniques (e.g., complementary metal-oxide-semiconductor (CMOS) fabrication). The standard EO payload integration and test process that involves precision alignment and test of optical components to form a diffraction limited telescope is, therefore, replaced by in-process integration and test as part of the PIC fabrication, which substantially reduces associated schedule and cost. In this paper we describe the photonic integrated circuit design and the testbed used to create the first images of extended scenes. We summarize the image reconstruction steps and present the final images. We also describe our next generation PIC design for a larger (16x area, 4x field of view) image.

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

NASA Astrophysics Data System (ADS)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Micro-opto-mechanical devices and systems using epitaxial lift off

NASA Technical Reports Server (NTRS)

Camperi-Ginestet, C.; Kim, Young W.; Wilkinson, S.; Allen, M.; Jokerst, N. M.

1993-01-01

The integration of high quality, single crystal thin film gallium arsenide (GaAs) and indium phosphide (InP) based photonic and electronic materials and devices with host microstructures fabricated from materials such as silicon (Si), glass, and polymers will enable the fabrication of the next generation of micro-opto-mechanical systems (MOMS) and optoelectronic integrated circuits. Thin film semiconductor devices deposited onto arbitrary host substrates and structures create hybrid (more than one material) near-monolithic integrated systems which can be interconnected electrically using standard inexpensive microfabrication techniques such as vacuum metallization and photolithography. These integrated systems take advantage of the optical and electronic properties of compound semiconductor devices while still using host substrate materials such as silicon, polysilicon, glass and polymers in the microstructures. This type of materials optimization for specific tasks creates higher performance systems than those systems which must use trade-offs in device performance to integrate all of the function in a single material system. The low weight of these thin film devices also makes them attractive for integration with micromechanical devices which may have difficulty supporting and translating the full weight of a standard device. These thin film devices and integrated systems will be attractive for applications, however, only when the development of low cost, high yield fabrication and integration techniques makes their use economically feasible. In this paper, we discuss methods for alignment, selective deposition, and interconnection of thin film epitaxial GaAs and InP based devices onto host substrates and host microstructures.

Survey Of High Speed Test Techniques

NASA Astrophysics Data System (ADS)

Gheewala, Tushar

1988-02-01

The emerging technologies for the characterization and production testing of high-speed devices and integrated circuits are reviewed. The continuing progress in the field of semiconductor technologies will, in the near future, demand test techniques to test 10ps to lOOps gate delays, 10 GHz to 100 GHz analog functions and 10,000 to 100,000 gates on a single chip. Clearly, no single test technique would provide a cost-effective answer to all the above demands. A divide-and-conquer approach based on a judicial selection of parametric, functional and high-speed tests will be required. In addition, design-for-test methods need to be pursued which will include on-chip test electronics as well as circuit techniques that minimize the circuit performance sensitivity to allowable process variations. The electron and laser beam based test technologies look very promising and may provide the much needed solutions to not only the high-speed test problem but also to the need for high levels of fault coverage during functional testing.

On-chip III-V monolithic integration of heralded single photon sources and beamsplitters

NASA Astrophysics Data System (ADS)

Belhassen, J.; Baboux, F.; Yao, Q.; Amanti, M.; Favero, I.; Lemaître, A.; Kolthammer, W. S.; Walmsley, I. A.; Ducci, S.

2018-02-01

We demonstrate a monolithic III-V photonic circuit combining a heralded single photon source with a beamsplitter, at room temperature and telecom wavelength. Pulsed parametric down-conversion in an AlGaAs waveguide generates counterpropagating photons, one of which is used to herald the injection of its twin into the beamsplitter. We use this configuration to implement an integrated Hanbury-Brown and Twiss experiment, yielding a heralded second-order correlation gher(2 )(0 )=0.10 ±0.02 that confirms single-photon operation. The demonstrated generation and manipulation of quantum states on a single III-V semiconductor chip opens promising avenues towards real-world applications in quantum information.

On-Chip Optical Nonreciprocity Using an Active Microcavity

PubMed Central

Jiang, Xiaoshun; Yang, Chao; Wu, Hongya; Hua, Shiyue; Chang, Long; Ding, Yang; Hua, Qian; Xiao, Min

2016-01-01

Optically nonreciprocal devices provide critical functionalities such as light isolation and circulation in integrated photonic circuits for optical communications and information processing, but have been difficult to achieve. By exploring gain-saturation nonlinearity, we demonstrate on-chip optical nonreciprocity with excellent isolation performance within telecommunication wavelengths using only one toroid microcavity. Compatible with current complementary metal-oxide-semiconductor process, our compact and simple scheme works for a very wide range of input power levels from ~10 microwatts down to ~10 nanowatts, and exhibits remarkable properties of one-way light transport with sufficiently low insertion loss. These superior features make our device become a promising critical building block indispensable for future integrated nanophotonic networks. PMID:27958356

Finite size effects in ferroelectric-semiconductor thin films under open-circuit electric boundary conditions

DOE PAGES

Eliseev, Eugene A.; Kalinin, Sergei V.; Morozovska, Anna N.

2015-01-21

General features of finite size effects in the ferroelectric-semiconductor film under open-circuit electric boundary conditions are analyzed using Landau-Ginzburg-Devonshire theory and continuum media electrostatics. The temperature dependence of the film critical thickness, spontaneous polarization and depolarization field profiles of the open-circuited films are found to be significantly different from the characteristics of short-circuited ones. In particular, we predict the re-entrant type transition boundary between the mono-domain and poly-domain ferroelectric states due to reduced internal screening efficiency and analyzed possible experimental scenarios created by this mechanism. Performed analysis is relevant for the quantitative description of free-standing ferroelectric films phase diagrams andmore » polar properties. Also our results can be useful for the explanation of the scanning-probe microscopy experiments on free ferroelectric surfaces.« less

SiC JFET Transistor Circuit Model for Extreme Temperature Range

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2008-01-01

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Electric Circuit Model Analogy for Equilibrium Lattice Relaxation in Semiconductor Heterostructures

NASA Astrophysics Data System (ADS)

Kujofsa, Tedi; Ayers, John E.

2018-01-01

The design and analysis of semiconductor strained-layer device structures require an understanding of the equilibrium profiles of strain and dislocations associated with mismatched epitaxy. Although it has been shown that the equilibrium configuration for a general semiconductor strained-layer structure may be found numerically by energy minimization using an appropriate partitioning of the structure into sublayers, such an approach is computationally intense and non-intuitive. We have therefore developed a simple electric circuit model approach for the equilibrium analysis of these structures. In it, each sublayer of an epitaxial stack may be represented by an analogous circuit configuration involving an independent current source, a resistor, an independent voltage source, and an ideal diode. A multilayered structure may be built up by the connection of the appropriate number of these building blocks, and the node voltages in the analogous electric circuit correspond to the equilibrium strains in the original epitaxial structure. This enables analysis using widely accessible circuit simulators, and an intuitive understanding of electric circuits can easily be extended to the relaxation of strained-layer structures. Furthermore, the electrical circuit model may be extended to continuously-graded epitaxial layers by considering the limit as the individual sublayer thicknesses are diminished to zero. In this paper, we describe the mathematical foundation of the electrical circuit model, demonstrate its application to several representative structures involving In x Ga1- x As strained layers on GaAs (001) substrates, and develop its extension to continuously-graded layers. This extension allows the development of analytical expressions for the strain, misfit dislocation density, critical layer thickness and widths of misfit dislocation free zones for a continuously-graded layer having an arbitrary compositional profile. It is similar to the transition from circuit theory, using lumped circuit elements, to electromagnetics, using distributed electrical quantities. We show this development using first principles, but, in a more general sense, Maxwell's equations of electromagnetics could be applied.

The AMOS cell - An improved metal-semiconductor solar cell. [Antireflection coated Metal Oxide Semiconductor

NASA Technical Reports Server (NTRS)

Stirn, R. J.; Yeh, Y.-C. M.

1975-01-01

A new fabrication process is being developed which significantly improves the efficiency of metal-semiconductor solar cells. The resultant effect, a marked increase in the open-circuit voltage, is produced by the addition of an interfacial layer oxide on the semiconductor. Cells using gold on n-type gallium arsenide have been made in small areas (0.17 sq cm) with conversion efficiencies of 15% in terrestrial sunlight.

High density circuit technology, part 1

NASA Technical Reports Server (NTRS)

Wade, T. E.

1982-01-01

The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

Transient Negative Optical Nonlinearity of Indium Oxide Nanorod Arrays in the Full-Visible Range

DOE PAGES

Guo, Peijun; Chang, Robert P. H.; Schaller, Richard D.

2017-06-09

Dynamic control of the optical response of materials at visible wavelengths is key to future metamaterials and photonic integrated circuits. Here we demonstrate large amplitude, negative optical nonlinearity (Δ n from -0.05 to -0.09) of indium oxide nanorod arrays in the full-visible range. We experimentally quantify and theoretically calculate the optical nonlinearity, which arises from the modifications of interband optical transitions. Furthermore, the approach towards negative optical nonlinearity can be generalized to other transparent semiconductors and opens door to reconfigurable, sub-wavelength optical components.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Cell Libraries

NASA Technical Reports Server (NTRS)

1994-01-01

A NASA contract led to the development of faster and more energy efficient semiconductor materials for digital integrated circuits. Gallium arsenide (GaAs) conducts electrons 4-6 times faster than silicon and uses less power at frequencies above 100-150 megahertz. However, the material is expensive, brittle, fragile and has lacked computer automated engineering tools to solve this problem. Systems & Processes Engineering Corporation (SPEC) developed a series of GaAs cell libraries for cell layout, design rule checking, logic synthesis, placement and routing, simulation and chip assembly. The system is marketed by Compare Design Automation.

Bi-level microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2004-01-06

A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The multilayered package can be formed of a LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded so that the light-sensitive side is optically accessible through the window. The package has at least two levels of circuits for making electrical interconnections to a pair of microelectronic devices. The result is a compact, low-profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device(s).

Electronic Components and Circuits for Extreme Temperature Environments

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad; Dickman, John E.; Gerber, Scott

2003-01-01

Planetary exploration missions and deep space probes require electrical power management and control systems that are capable of efficient and reliable operation in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures will not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures; thereby reducing system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior and tolerance in the electrical and thermal properties of semiconductor and dielectric materials at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial-off-the-shelf as well as developed components that are being characterized include switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, DC/DC converters, operational amplifiers, and oscillators are also being investigated for potential use in low temperature applications. An overview of the NASA Glenn Research Center Low Temperature Electronic Program will be presented in this paper. A description of the low temperature test facilities along with selected data obtained through in-house component and circuit testing will also be discussed. Ongoing research activities that are being performed in collaboration with various organizations will also be presented.

Monolithically integrated bacteriorhodopsin-GaAs/GaAlAs phototransceiver.

PubMed

Shin, Jonghyun; Bhattacharya, Pallab; Xu, Jian; Váró, György

2004-10-01

A monolithically integrated bacteriorhodopsin-semiconductor phototransceiver is demonstrated for the first time to the authors' knowledge. In this novel biophotonic optical interconnect, the input photoexcitation is detected by bacteriorhodopsin (bR) that has been selectively deposited onto the gate of a GaAs-based field-effect transistor. The photovoltage developed across the bR is converted by the transistor into an amplified photocurrent, which drives an integrated light-emitting diode with a Ga0.37Al0.63As active region. Advantage is taken of the high-input impedance of the field-effect transistor, which matches the high internal resistance of bR. The input and output wavelengths are 594 and 655 nm, respectively. The transient response of the optoelectronic circuit to modulated input light has also been studied.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gottwald, M.; Kan, J. J.; Lee, K.

Thermal budget, stack thickness, and dipolar offset field control are crucial for seamless integration of perpendicular magnetic junctions (pMTJ) into semiconductor integrated circuits to build scalable spin-transfer-torque magnetoresistive random access memory. This paper is concerned with materials and process tuning to deliver thermally robust (400 °C, 30 min) and thin (i.e., fewer layers and integration-friendly) pMTJ utilizing Co/Pt-based bottom pinned layers. Interlayer roughness control is identified as a key enabler to achieve high thermal budgets. The dipolar offset fields of the developed film stacks at scaled dimensions are evaluated by micromagnetic simulations. This paper shows a path towards achieving sub-15 nm-thick pMTJ withmore » tunneling magnetoresistance ratio higher than 150% after 30 min of thermal excursion at 400 °C.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, R.; Lu, R.; Gong, S.

We demonstrate a room-temperature semiconductor-based photodetector where readout is achieved using a resonant radio-frequency (RF) circuit consisting of a microstrip split-ring resonator coupled to a microstrip busline, fabricated on a semiconductor substrate. The RF resonant circuits are characterized at RF frequencies as function of resonator geometry, as well as for their response to incident IR radiation. The detectors are modeled analytically and using commercial simulation software, with good agreement to our experimental results. Though the detector sensitivity is weak, the detector architecture offers the potential for multiplexing arrays of detectors on a single read-out line, in addition to high speedmore » response for either direct coupling of optical signals to RF circuitry, or alternatively, carrier dynamics characterization of semiconductor, or other, material systems.« less

A Single Phase 7-Level Cascade Inverter Topology with Reduced Number of Switches on Resistive Load by Using PWM

NASA Astrophysics Data System (ADS)

Hamzah, H. H.; Ponniran, A.; Kasiran, A. N.; Harimon, M. A.; Gendum, D. A.; Yatim, M. H.

2018-04-01

This paper discussing design principles of inverter structure with reduced number of semiconductor devices of seven levels symmetric H-bridge multilevel inverter (MLI) topology. The aim of this paper is to design an inverter circuit with reduction of semiconductor losses, converter size and development cost. The H-bridge and auxiliary structures were considered in order to achieve seven levels output voltage. The performance of design circuit is compared with conventional seven levels structure in terms of voltage output. The circuit development consists of seven switches and three diode. A basic modulation technique is used to confirm the designed circuit. The results show that the designed circuit is able to convert seven level output voltage with low total harmonics distortion (THD) in voltage fundamental output. According to the results, fundamental output voltage is increased up to 8.314%, and the THD is decreased up to 0.81% compared to the conventional seven level inverter.

A Cost-Effective Energy-Recovering Sustain Driving Circuit for ac Plasma Display Panels

NASA Astrophysics Data System (ADS)

Lim, Jae Kwang; Tae, Heung-Sik; Choi, Byungcho; Kim, Seok Gi

A new sustain driving circuit, featuring an energy-recovering function with simple structure and minimal component count, is proposed as a cost-effective solution for driving plasma display panels during the sustaining period. Compared with existing solutions, the proposed circuit reduces the number of semiconductor switches and reactive circuit components without compromising the circuit performance and gas-discharging characteristics. In addition, the proposed circuit utilizes the harness wire as an inductive circuit component, thereby further simplifying the circuit structure. The performance of the proposed circuit is confirmed with a 42-inch plasma display panel.

Scalable Sub-micron Patterning of Organic Materials Toward High Density Soft Electronics.

PubMed

Kim, Jaekyun; Kim, Myung-Gil; Kim, Jaehyun; Jo, Sangho; Kang, Jingu; Jo, Jeong-Wan; Lee, Woobin; Hwang, Chahwan; Moon, Juhyuk; Yang, Lin; Kim, Yun-Hi; Noh, Yong-Young; Jaung, Jae Yun; Kim, Yong-Hoon; Park, Sung Kyu

2015-09-28

The success of silicon based high density integrated circuits ignited explosive expansion of microelectronics. Although the inorganic semiconductors have shown superior carrier mobilities for conventional high speed switching devices, the emergence of unconventional applications, such as flexible electronics, highly sensitive photosensors, large area sensor array, and tailored optoelectronics, brought intensive research on next generation electronic materials. The rationally designed multifunctional soft electronic materials, organic and carbon-based semiconductors, are demonstrated with low-cost solution process, exceptional mechanical stability, and on-demand optoelectronic properties. Unfortunately, the industrial implementation of the soft electronic materials has been hindered due to lack of scalable fine-patterning methods. In this report, we demonstrated facile general route for high throughput sub-micron patterning of soft materials, using spatially selective deep-ultraviolet irradiation. For organic and carbon-based materials, the highly energetic photons (e.g. deep-ultraviolet rays) enable direct photo-conversion from conducting/semiconducting to insulating state through molecular dissociation and disordering with spatial resolution down to a sub-μm-scale. The successful demonstration of organic semiconductor circuitry promise our result proliferate industrial adoption of soft materials for next generation electronics.

Scalable Sub-micron Patterning of Organic Materials Toward High Density Soft Electronics

NASA Astrophysics Data System (ADS)

Kim, Jaekyun; Kim, Myung-Gil; Kim, Jaehyun; Jo, Sangho; Kang, Jingu; Jo, Jeong-Wan; Lee, Woobin; Hwang, Chahwan; Moon, Juhyuk; Yang, Lin; Kim, Yun-Hi; Noh, Yong-Young; Yun Jaung, Jae; Kim, Yong-Hoon; Kyu Park, Sung

2015-09-01

The success of silicon based high density integrated circuits ignited explosive expansion of microelectronics. Although the inorganic semiconductors have shown superior carrier mobilities for conventional high speed switching devices, the emergence of unconventional applications, such as flexible electronics, highly sensitive photosensors, large area sensor array, and tailored optoelectronics, brought intensive research on next generation electronic materials. The rationally designed multifunctional soft electronic materials, organic and carbon-based semiconductors, are demonstrated with low-cost solution process, exceptional mechanical stability, and on-demand optoelectronic properties. Unfortunately, the industrial implementation of the soft electronic materials has been hindered due to lack of scalable fine-patterning methods. In this report, we demonstrated facile general route for high throughput sub-micron patterning of soft materials, using spatially selective deep-ultraviolet irradiation. For organic and carbon-based materials, the highly energetic photons (e.g. deep-ultraviolet rays) enable direct photo-conversion from conducting/semiconducting to insulating state through molecular dissociation and disordering with spatial resolution down to a sub-μm-scale. The successful demonstration of organic semiconductor circuitry promise our result proliferate industrial adoption of soft materials for next generation electronics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Jaekyun; Kim, Myung -Gil; Kim, Jaehyun

The success of silicon based high density integrated circuits ignited explosive expansion of microelectronics. Although the inorganic semiconductors have shown superior carrier mobilities for conventional high speed switching devices, the emergence of unconventional applications, such as flexible electronics, highly sensitive photosensors, large area sensor array, and tailored optoelectronics, brought intensive research on next generation electronic materials. The rationally designed multifunctional soft electronic materials, organic and carbon-based semiconductors, are demonstrated with low-cost solution process, exceptional mechanical stability, and on-demand optoelectronic properties. Unfortunately, the industrial implementation of the soft electronic materials has been hindered due to lack of scalable fine-patterning methods. Inmore » this report, we demonstrated facile general route for high throughput sub-micron patterning of soft materials, using spatially selective deep-ultraviolet irradiation. For organic and carbon-based materials, the highly energetic photons (e.g. deep-ultraviolet rays) enable direct photo-conversion from conducting/semiconducting to insulating state through molecular dissociation and disordering with spatial resolution down to a sub-μm-scale. As a result, the successful demonstration of organic semiconductor circuitry promise our result proliferate industrial adoption of soft materials for next generation electronics.« less

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

PubMed

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Editor)

1992-01-01

The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

Power management circuits for self-powered systems based on micro-scale solar energy harvesting

NASA Astrophysics Data System (ADS)

Yoon, Eun-Jung; Yu, Chong-Gun

2016-03-01

In this paper, two types of power management circuits for self-powered systems based on micro-scale solar energy harvesting are proposed. First, if a solar cell outputs a very low voltage, less than 0.5 V, as in miniature solar cells or monolithic integrated solar cells, such that it cannot directly power the load, a voltage booster is employed to step up the solar cell's output voltage, and then a power management unit (PMU) delivers the boosted voltage to the load. Second, if the output voltage of a solar cell is enough to drive the load, the PMU directly supplies the load with solar energy. The proposed power management systems are designed and fabricated in a 0.18-μm complementary metal-oxide-semiconductor process, and their performances are compared and analysed through measurements.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

PubMed

Asano, Sho; Muroyama, Masanori; Nakayama, Takahiro; Hata, Yoshiyuki; Nonomura, Yutaka; Tanaka, Shuji

2017-10-25

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer †

PubMed Central

Asano, Sho; Nakayama, Takahiro; Hata, Yoshiyuki; Tanaka, Shuji

2017-01-01

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively. PMID:29068429

Semiconductor cooling by thin-film thermocouples

NASA Technical Reports Server (NTRS)

Tick, P. A.; Vilcans, J.

1970-01-01

Thin-film, metal alloy thermocouple junctions do not rectify, change circuit impedance only slightly, and require very little increase in space. Although they are less efficient cooling devices than semiconductor junctions, they may be applied to assist conventional cooling techniques for electronic devices.

Wireless multichannel biopotential recording using an integrated FM telemetry circuit.

PubMed

Mohseni, Pedram; Najafi, Khalil; Eliades, Steven J; Wang, Xiaoqin

2005-09-01

This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of approximately 0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-microm double-poly double-metal n-well standard complementary metal-oxide semiconductor process, interfaced with only three off-chip components on a custom-designed printed-circuit board that measures 1.7 x 1.2 x 0.16 cm3, and weighs 1.1 g including two miniature 1.5-V batteries. We characterize the microsystem performance, operating in a truly wireless fashion in single-channel and multichannel operation modes, via extensive benchtop and in vitro tests in saline utilizing two different micromachined neural recording microelectrodes, while dissipating approximately 2.2 mW from a 3-V power supply. Moreover, we demonstrate successful wireless in vivo recording of spontaneous neural activity at 96.2 MHz from the auditory cortex of an awake marmoset monkey at several transmission distances ranging from 10 to 50 cm with signal-to-noise ratios in the range of 8.4-9.5 dB.

Triple voltage dc-to-dc converter and method

DOEpatents

Su, Gui-Jia

2008-08-05

A circuit and method of providing three dc voltage buses and transforming power between a low voltage dc converter and a high voltage dc converter, by coupling a primary dc power circuit and a secondary dc power circuit through an isolation transformer; providing the gating signals to power semiconductor switches in the primary and secondary circuits to control power flow between the primary and secondary circuits and by controlling a phase shift between the primary voltage and the secondary voltage. The primary dc power circuit and the secondary dc power circuit each further comprising at least two tank capacitances arranged in series as a tank leg, at least two resonant switching devices arranged in series with each other and arranged in parallel with the tank leg, and at least one voltage source arranged in parallel with the tank leg and the resonant switching devices, said resonant switching devices including power semiconductor switches that are operated by gating signals. Additional embodiments having a center-tapped battery on the low voltage side and a plurality of modules on both the low voltage side and the high voltage side are also disclosed for the purpose of reducing ripple current and for reducing the size of the components.

Energy saving in ac generators

NASA Technical Reports Server (NTRS)

Nola, F. J.

1980-01-01

Circuit cuts no-load losses, without sacrificing full-load power. Phase-contro circuit includes gate-controlled semiconductor switch that cuts off applied voltage for most of ac cycle if generator idling. Switch "on" time increases when generator is in operation.

Integrated Optoelectronic Position Sensor for Scanning Micromirrors.

PubMed

Cheng, Xiang; Sun, Xinglin; Liu, Yan; Zhu, Lijun; Zhang, Xiaoyang; Zhou, Liang; Xie, Huikai

2018-03-26

Scanning micromirrors have been used in a wide range of areas, but many of them do not have position sensing built in, which significantly limits their application space. This paper reports an integrated optoelectronic position sensor (iOE-PS) that can measure the linear displacement and tilting angle of electrothermal MEMS (Micro-electromechanical Systems) scanning mirrors. The iOE-PS integrates a laser diode and its driving circuits, a quadrant photo-detector (QPD) and its readout circuits, and a band-gap reference all on a single chip, and it has been fabricated in a standard 0.5 μm CMOS (Complementary Metal Oxide Semiconductor) process. The footprint of the iOE-PS chip is 5 mm × 5 mm. Each quadrant of the QPD has a photosensitive area of 500 µm × 500 µm and the spacing between adjacent quadrants is 500 μm. The iOE-PS chip is simply packaged underneath of an electrothermally-actuated MEMS mirror. Experimental results show that the iOE-PS has a linear response when the MEMS mirror plate moves vertically between 2.0 mm and 3.0 mm over the iOE-PS chip or scans from -5 to +5°. Such MEMS scanning mirrors integrated with the iOE-PS can greatly reduce the complexity and cost of the MEMS mirrors-enabled modules and systems.

SOI CMOS Imager with Suppression of Cross-Talk

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

2009-01-01

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Analysis of a Statistical Relationship Between Dose and Error Tallies in Semiconductor Digital Integrated Circuits for Application to Radiation Monitoring Over a Wireless Sensor Network

NASA Astrophysics Data System (ADS)

Colins, Karen; Li, Liqian; Liu, Yu

2017-05-01

Mass production of widely used semiconductor digital integrated circuits (ICs) has lowered unit costs to the level of ordinary daily consumables of a few dollars. It is therefore reasonable to contemplate the idea of an engineered system that consumes unshielded low-cost ICs for the purpose of measuring gamma radiation dose. Underlying the idea is the premise of a measurable correlation between an observable property of ICs and radiation dose. Accumulation of radiation-damage-induced state changes or error events is such a property. If correct, the premise could make possible low-cost wide-area radiation dose measurement systems, instantiated as wireless sensor networks (WSNs) with unshielded consumable ICs as nodes, communicating error events to a remote base station. The premise has been investigated quantitatively for the first time in laboratory experiments and related analyses performed at the Canadian Nuclear Laboratories. State changes or error events were recorded in real time during irradiation of samples of ICs of different types in a 60Co gamma cell. From the error-event sequences, empirical distribution functions of dose were generated. The distribution functions were inverted and probabilities scaled by total error events, to yield plots of the relationship between dose and error tallies. Positive correlation was observed, and discrete functional dependence of dose quantiles on error tallies was measured, demonstrating the correctness of the premise. The idea of an engineered system that consumes unshielded low-cost ICs in a WSN, for the purpose of measuring gamma radiation dose over wide areas, is therefore tenable.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Schwank, J.R.; Fleetwood, D.M.; Shaneyfelt, M.R.; Winokur, P.S.; Devine, R.A.B.

1998-07-28

A method is disclosed for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer. 5 figs.

Review on the dynamics of semiconductor nanowire lasers

NASA Astrophysics Data System (ADS)

Röder, Robert; Ronning, Carsten

2018-03-01

Semiconductor optoelectronic devices have contributed tremendously to the technological progress in the past 50-60 years. Today, they also play a key role in nanophotonics stimulated by the inherent limitations of electronic integrated circuits and the growing demand for faster communications on chip. In particular, the field of ‘nanowire photonics’ has emerged including the search for coherent light sources with a nano-scaled footprint. The past decade has been dedicated to find suitable semiconductor nanowire (NW) materials for such nanolasers. Nowadays, such NW lasers consistently work at room temperature covering a huge spectral range from the ultraviolet down to the mid-infrared depending on the band gap of the NW material. Furthermore, first approaches towards the modification and optimization of such NW laser devices have been demonstrated. The underlying dynamics of the electronic and photonic NW systems have also been studied very recently, as they need to be understood in order to push the technological relevance of nano-scaled coherent light sources. Therefore, this review will first present novel measurement approaches in order to study the ultrafast temporal and optical mode dynamics of individual NW laser devices. Furthermore, these fundamental new insights are reviewed and deeply discussed towards the efficient control and adjustment of the dynamics in semiconductor NW lasers.

New non-linear photovoltaic effect in uniform bipolar semiconductor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Volovichev, I.

2014-11-21

A linear theory of the new non-linear photovoltaic effect in the closed circuit consisting of a non-uniformly illuminated uniform bipolar semiconductor with neutral impurities is developed. The non-uniform photo-excitation of impurities results in the position-dependant current carrier mobility that breaks the semiconductor homogeneity and induces the photo-electromotive force (emf). As both the electron (or hole) mobility gradient and the current carrier generation rate depend on the light intensity, the photo-emf and the short-circuit current prove to be non-linear functions of the incident light intensity at an arbitrarily low illumination. The influence of the sample size on the photovoltaic effect magnitudemore » is studied. Physical relations and distinctions between the considered effect and the Dember and bulk photovoltaic effects are also discussed.« less

Transfer of InP epilayers by wafer bonding

NASA Astrophysics Data System (ADS)

Hjort, Klas

2004-08-01

Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

Integrated resonant micro-optical gyroscope and method of fabrication

DOEpatents

Vawter, G Allen [Albuquerque, NM; Zubrzycki, Walter J [Sandia Park, NM; Guo, Junpeng [Albuquerque, NM; Sullivan, Charles T [Albuquerque, NM

2006-09-12

An integrated optic gyroscope is disclosed which is based on a photonic integrated circuit (PIC) having a bidirectional laser source, a pair of optical waveguide phase modulators and a pair of waveguide photodetectors. The PIC can be connected to a passive ring resonator formed either as a coil of optical fiber or as a coiled optical waveguide. The lasing output from each end of the bidirectional laser source is phase modulated and directed around the passive ring resonator in two counterpropagating directions, with a portion of the lasing output then being detected to determine a rotation rate for the integrated optical gyroscope. The coiled optical waveguide can be formed on a silicon, glass or quartz substrate with a silicon nitride core and a silica cladding, while the PIC includes a plurality of III V compound semiconductor layers including one or more quantum well layers which are disordered in the phase modulators and to form passive optical waveguides.

Metal-Insulator-Semiconductor Nanowire Network Solar Cells.

PubMed

Oener, Sebastian Z; van de Groep, Jorik; Macco, Bart; Bronsveld, Paula C P; Kessels, W M M; Polman, Albert; Garnett, Erik C

2016-06-08

Metal-insulator-semiconductor (MIS) junctions provide the charge separating properties of Schottky junctions while circumventing the direct and detrimental contact of the metal with the semiconductor. A passivating and tunnel dielectric is used as a separation layer to reduce carrier recombination and remove Fermi level pinning. When applied to solar cells, these junctions result in two main advantages over traditional p-n-junction solar cells: a highly simplified fabrication process and excellent passivation properties and hence high open-circuit voltages. However, one major drawback of metal-insulator-semiconductor solar cells is that a continuous metal layer is needed to form a junction at the surface of the silicon, which decreases the optical transmittance and hence short-circuit current density. The decrease of transmittance with increasing metal coverage, however, can be overcome by nanoscale structures. Nanowire networks exhibit precisely the properties that are required for MIS solar cells: closely spaced and conductive metal wires to induce an inversion layer for homogeneous charge carrier extraction and simultaneously a high optical transparency. We experimentally demonstrate the nanowire MIS concept by using it to make silicon solar cells with a measured energy conversion efficiency of 7% (∼11% after correction), an effective open-circuit voltage (Voc) of 560 mV and estimated short-circuit current density (Jsc) of 33 mA/cm(2). Furthermore, we show that the metal nanowire network can serve additionally as an etch mask to pattern inverted nanopyramids, decreasing the reflectivity substantially from 36% to ∼4%. Our extensive analysis points out a path toward nanowire based MIS solar cells that exhibit both high Voc and Jsc values.

Quartz/fused silica chip carriers

NASA Technical Reports Server (NTRS)

1992-01-01

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

PubMed Central

Roever, Stefan

2012-01-01

A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

PubMed

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

2015-10-14

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-il Dan; Ko, Hyoungho

2015-01-01

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms. PMID:26473877

Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET

NASA Astrophysics Data System (ADS)

Maity, Subir Kr.; Pandit, Soumya

2017-11-01

InGaAs is an attractive choice as alternate channel material in n-channel metal oxide semiconductor transistor for high-performance applications. However, electrostatic integrity of such device is poor. In this paper, we present a comprehensive technology computer-aided design simulation-based study of the effect of scaling the thickness of the buried oxide (BOX) region and varying the dielectric constant of BOX material on the electrostatic integrity, analogue/radio frequency (RF) performance and circuit performance of InGaAs-on-Insulator device. Device with thin BOX layer gives better drain-induced barrier lowering performance which enhances output resistance. The carrier mobility remains almost constant with thinning of BOX layer up to certain value. By lowering the dielectric constant of the BOX material, it is further possible to improve the analogue and RF performance. Effect of BOX thickness scaling and role of BOX dielectric material on gain-frequency response of common source amplifier is also studied. It is observed that frequency response of the amplifier improves for thin BOX and with low dielectric constant-based material.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

18-THz-wide optical frequency comb emitted from monolithic passively mode-locked semiconductor quantum-well laser

NASA Astrophysics Data System (ADS)

Lo, Mu-Chieh; Guzmán, Robinson; Ali, Muhsin; Santos, Rui; Augustin, Luc; Carpintero, Guillermo

2017-10-01

We report on an optical frequency comb with 14nm (~1.8 THz) spectral bandwidth at -3 dB level that is generated using a passively mode-locked quantum-well (QW) laser in photonic integrated circuits (PICs) fabricated through an InP generic photonic integration technology platform. This 21.5-GHz colliding-pulse mode-locked laser cavity is defined by on-chip reflectors incorporating intracavity phase modulators followed by an extra-cavity SOA as booster amplifier. A 1.8-THz-wide optical comb spectrum is presented with ultrafast pulse that is 0.35-ps-wide. The radio frequency beat note has a 3-dB linewidth of 450 kHz and 35-dB SNR.

A physically transient form of silicon electronics.

PubMed

Hwang, Suk-Won; Tao, Hu; Kim, Dae-Hyeong; Cheng, Huanyu; Song, Jun-Kyul; Rill, Elliott; Brenckle, Mark A; Panilaitis, Bruce; Won, Sang Min; Kim, Yun-Soung; Song, Young Min; Yu, Ki Jun; Ameen, Abid; Li, Rui; Su, Yewang; Yang, Miaomiao; Kaplan, David L; Zakin, Mitchell R; Slepian, Marvin J; Huang, Yonggang; Omenetto, Fiorenzo G; Rogers, John A

2012-09-28

A remarkable feature of modern silicon electronics is its ability to remain physically invariant, almost indefinitely for practical purposes. Although this characteristic is a hallmark of applications of integrated circuits that exist today, there might be opportunities for systems that offer the opposite behavior, such as implantable devices that function for medically useful time frames but then completely disappear via resorption by the body. We report a set of materials, manufacturing schemes, device components, and theoretical design tools for a silicon-based complementary metal oxide semiconductor (CMOS) technology that has this type of transient behavior, together with integrated sensors, actuators, power supply systems, and wireless control strategies. An implantable transient device that acts as a programmable nonantibiotic bacteriocide provides a system-level example.

Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

PubMed Central

Chen, Szi-Wen; Chen, Yuan-Ho

2015-01-01

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

PubMed

Chen, Szi-Wen; Chen, Yuan-Ho

2015-10-16

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.