Thin-Film Solar Cell Fabricated on a Flexible Metallic Substrate

DOEpatents

Tuttle, J. R.; Noufi, R.; Hasoon, F. S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

DOEpatents

Wu, Xuanzhi; Coutts, Timothy J.; Sheldon, Peter; Rose, Douglas H.

1999-01-01

A photovoltaic device having a substrate, a layer of Cd.sub.2 SnO.sub.4 disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd.sub.2 SnO.sub.4, and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd.sub.2 SnO.sub.4 layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd.sub.2 SnO.sub.4, and depositing an electrically conductive film onto the thin film of semiconductor materials.

Method of producing strained-layer semiconductor devices via subsurface-patterning

DOEpatents

Dodson, Brian W.

1993-01-01

A method is described for patterning subsurface features in a semiconductor device, wherein the semiconductor device includes an internal strained layer. The method comprises creating a pattern of semiconductor material over the semiconductor device, the semiconductor material having a predetermined thickness which stabilizes areas of the strained semiconductor layer that lie beneath the pattern. Subsequently, a heating step is applied to the semiconductor device to cause a relaxation in areas of the strained layer which do not lie beneath the semiconductor material pattern, whereby dislocations result in the relaxed areas and impair electrical transport therethrough.

Cadmium-free junction fabrication process for CuInSe.sub.2 thin film solar cells

DOEpatents

Ramanathan, Kannan V.; Contreras, Miguel A.; Bhattacharya, Raghu N.; Keane, James; Noufi, Rommel

1999-01-01

The present invention provides an economical, simple, dry and controllable semiconductor layer junction forming process to make cadmium free high efficiency photovoltaic cells having a first layer comprised primarily of copper indium diselenide having a thin doped copper indium diselenide n-type region, generated by thermal diffusion with a group II(b) element such as zinc, and a halide, such as chlorine, and a second layer comprised of a conventional zinc oxide bilayer. A photovoltaic device according the present invention includes a first thin film layer of semiconductor material formed primarily from copper indium diselenide. Doping of the copper indium diselenide with zinc chloride is accomplished using either a zinc chloride solution or a solid zinc chloride material. Thermal diffusion of zinc chloride into the copper indium diselenide upper region creates the thin n-type copper indium diselenide surface. A second thin film layer of semiconductor material comprising zinc oxide is then applied in two layers. The first layer comprises a thin layer of high resistivity zinc oxide. The second relatively thick layer of zinc oxide is doped to exhibit low resistivity.

Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

DOEpatents

Wu, X.; Coutts, T.J.; Sheldon, P.; Rose, D.H.

1999-07-13

A photovoltaic device is disclosed having a substrate, a layer of Cd[sub 2]SnO[sub 4] disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd[sub 2]SnO[sub 4], and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd[sub 2]SnO[sub 4] layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd[sub 2]SnO[sub 4], and depositing an electrically conductive film onto the thin film of semiconductor materials. 10 figs.

Photovoltaic devices comprising zinc stannate buffer layer and method for making

DOEpatents

Wu, Xuanzhi; Sheldon, Peter; Coutts, Timothy J.

2001-01-01

A photovoltaic device has a buffer layer zinc stannate Zn.sub.2 SnO.sub.4 disposed between the semiconductor junction structure and the transparent conducting oxide (TCO) layer to prevent formation of localized junctions with the TCO through a thin window semiconductor layer, to prevent shunting through etched grain boundaries of semiconductors, and to relieve stresses and improve adhesion between these layers.

Group I-III-VI.sub.2 semiconductor films for solar cell application

DOEpatents

Basol, Bulent M.; Kapur, Vijay K.

1991-01-01

This invention relates to an improved thin film solar cell with excellent electrical and mechanical integrity. The device comprises a substrate, a Group I-III-VI.sub.2 semiconductor absorber layer and a transparent window layer. The mechanical bond between the substrate and the Group I-III-VI.sub.2 semiconductor layer is enhanced by an intermediate layer between the substrate and the Group I-III-VI.sub.2 semiconductor film being grown. The intermediate layer contains tellurium or substitutes therefor, such as Se, Sn, or Pb. The intermediate layer improves the morphology and electrical characteristics of the Group I-III-VI.sub.2 semiconductor layer.

Semiconductor laser having a non-absorbing passive region with beam guiding

NASA Technical Reports Server (NTRS)

Botez, Dan (Inventor)

1986-01-01

A laser comprises a semiconductor body having a pair of end faces and including an active region comprising adjacent active and guide layers which is spaced a distance from the end face and a passive region comprising adjacent non-absorbing guide and mode control layers which extends between the active region and the end face. The combination of the guide and mode control layers provides a weak positive index waveguide in the lateral direction thereby providing lateral mode control in the passive region between the active region and the end face.

Photodetector having high speed and sensitivity

DOEpatents

Morse, Jeffrey D.; Mariella, Jr., Raymond P.

1991-01-01

The present invention provides a photodetector having an advantageous combination of sensitivity and speed; it has a high sensitivity while retaining high speed. In a preferred embodiment, visible light is detected, but in some embodiments, x-rays can be detected, and in other embodiments infrared can be detected. The present invention comprises a photodetector having an active layer, and a recombination layer. The active layer has a surface exposed to light to be detected, and comprises a semiconductor, having a bandgap graded so that carriers formed due to interaction of the active layer with the incident radiation tend to be swept away from the exposed surface. The graded semiconductor material in the active layer preferably comprises Al.sub.1-x Ga.sub.x As. An additional sub-layer of graded In.sub.1-y Ga.sub.y As may be included between the Al.sub.1-x Ga.sub.x As layer and the recombination layer. The recombination layer comprises a semiconductor material having a short recombination time such as a defective GaAs layer grown in a low temperature process. The recombination layer is positioned adjacent to the active layer so that carriers from the active layer tend to be swept into the recombination layer. In an embodiment, the photodetector may comprise one or more additional layers stacked below the active and recombination layers. These additional layers may include another active layer and another recombination layer to absorb radiation not absorbed while passing through the first layers. A photodetector having a stacked configuration may have enhanced sensitivity and responsiveness at selected wavelengths such as infrared.

Semiconductor devices incorporating multilayer interference regions

DOEpatents

Biefeld, Robert M.; Drummond, Timothy J.; Gourley, Paul L.; Zipperian, Thomas E.

1990-01-01

A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration.

Transparent contacts for stacked compound photovoltaic cells

DOEpatents

Tauke-Pedretti, Anna; Cederberg, Jeffrey; Nielson, Gregory N.; Okandan, Murat; Cruz-Campa, Jose Luis

2016-11-29

A microsystems-enabled multi-junction photovoltaic (MEM-PV) cell includes a first photovoltaic cell having a first junction, the first photovoltaic cell including a first semiconductor material employed to form the first junction, the first semiconductor material having a first bandgap. The MEM-PV cell also includes a second photovoltaic cell comprising a second junction. The second photovoltaic cell comprises a second semiconductor material employed to form the second junction, the second semiconductor material having a second bandgap that is less than the first bandgap, the second photovoltaic cell further comprising a first contact layer disposed between the first junction of the first photovoltaic cell and the second junction of the second photovoltaic cell, the first contact layer composed of a third semiconductor material having a third bandgap, the third bandgap being greater than or equal to the first bandgap.

Semiconductor devices incorporating multilayer interference regions

DOEpatents

Biefeld, R.M.; Drummond, T.J.; Gourley, P.L.; Zipperian, T.E.

1987-08-31

A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration. 8 figs.

Amorphous semiconductor solar cell

DOEpatents

Dalal, Vikram L.

1981-01-01

A solar cell comprising a back electrical contact, amorphous silicon semiconductor base and junction layers and a top electrical contact includes in its manufacture the step of heat treating the physical junction between the base layer and junction layer to diffuse the dopant species at the physical junction into the base layer.

Alpha voltaic batteries and methods thereof

NASA Technical Reports Server (NTRS)

Jenkins, Phillip (Inventor); Scheiman, David (Inventor); Castro, Stephanie (Inventor); Raffaelle, Ryne P. (Inventor); Wilt, David (Inventor); Chubb, Donald (Inventor)

2011-01-01

An alpha voltaic battery includes at least one layer of a semiconductor material comprising at least one p/n junction, at least one absorption and conversion layer on the at least one layer of semiconductor layer, and at least one alpha particle emitter. The absorption and conversion layer prevents at least a portion of alpha particles from the alpha particle emitter from damaging the p/n junction in the layer of semiconductor material. The absorption and conversion layer also converts at least a portion of energy from the alpha particles into electron-hole pairs for collection by the one p/n junction in the layer of semiconductor material.

Narrow energy band gap gallium arsenide nitride semi-conductors and an ion-cut-synthesis method for producing the same

DOEpatents

Weng, Xiaojun; Goldman, Rachel S.

2006-06-06

A method for forming a semi-conductor material is provided that comprises forming a donor substrate constructed of GaAs, providing a receiver substrate, implanting nitrogen into the donor substrate to form an implanted layer comprising GaAs and nitrogen. The implanted layer is bonded to the receiver substrate and annealed to form GaAsN and nitrogen micro-blisters in the implanted layer. The micro-blisters allow the implanted layer to be cleaved from the donor substrate.

Charge dissipative dielectric for cryogenic devices

NASA Technical Reports Server (NTRS)

Cantor, Robin Harold (Inventor); Hall, John Addison (Inventor)

2007-01-01

A Superconducting Quantum Interference Device (SQUID) is disclosed comprising a pair of resistively shunted Josephson junctions connected in parallel within a superconducting loop and biased by an external direct current (dc) source. The SQUID comprises a semiconductor substrate and at least one superconducting layer. The metal layer(s) are separated by or covered with a semiconductor material layer having the properties of a conductor at room temperature and the properties of an insulator at operating temperatures (generally less than 100 Kelvins). The properties of the semiconductor material layer greatly reduces the risk of electrostatic discharge that can damage the device during normal handling of the device at room temperature, while still providing the insulating properties desired to allow normal functioning of the device at its operating temperature. A method of manufacturing the SQUID device is also disclosed.

Surface preparation of substances for continuous convective assembly of fine particles

DOEpatents

Rossi, Robert

2003-01-01

A method for producing periodic nanometer-scale arrays of metal or semiconductor junctions on a clean semiconductor substrate surface is provided comprising the steps of: etching the substrate surface to make it hydrophilic, forming, under an inert atmosphere, a crystalline colloid layer on the substrate surface, depositing a metal or semiconductor material through the colloid layer onto the surface of the substrate, and removing the colloid from the substrate surface. The colloid layer is grown on the clean semiconductor surface by withdrawing the semiconductor substrate from a sol of colloid particles.

Circular electrode geometry metal-semiconductor-metal photodetectors

NASA Technical Reports Server (NTRS)

Mcaddo, James A. (Inventor); Towe, Elias (Inventor); Bishop, William L. (Inventor); Wang, Liang-Guo (Inventor)

1994-01-01

The invention comprises a high speed, metal-semiconductor-metal photodetector which comprises a pair of generally circular, electrically conductive electrodes formed on an optically active semiconductor layer. Various embodiments of the invention include a spiral, intercoiled electrode geometry and an electrode geometry comprised of substantially circular, concentric electrodes which are interposed. These electrode geometries result in photodetectors with lower capacitances, dark currents and lower inductance which reduces the ringing seen in the optical pulse response.

Variable temperature semiconductor film deposition

DOEpatents

Li, X.; Sheldon, P.

1998-01-27

A method of depositing a semiconductor material on a substrate is disclosed. The method sequentially comprises (a) providing the semiconductor material in a depositable state such as a vapor for deposition on the substrate; (b) depositing the semiconductor material on the substrate while heating the substrate to a first temperature sufficient to cause the semiconductor material to form a first film layer having a first grain size; (c) continually depositing the semiconductor material on the substrate while cooling the substrate to a second temperature sufficient to cause the semiconductor material to form a second film layer deposited on the first film layer and having a second grain size smaller than the first grain size; and (d) raising the substrate temperature, while either continuing or not continuing to deposit semiconductor material to form a third film layer, to thereby anneal the film layers into a single layer having favorable efficiency characteristics in photovoltaic applications. A preferred semiconductor material is cadmium telluride deposited on a glass/tin oxide substrate already having thereon a film layer of cadmium sulfide.

Variable temperature semiconductor film deposition

DOEpatents

Li, Xiaonan; Sheldon, Peter

1998-01-01

A method of depositing a semiconductor material on a substrate. The method sequentially comprises (a) providing the semiconductor material in a depositable state such as a vapor for deposition on the substrate; (b) depositing the semiconductor material on the substrate while heating the substrate to a first temperature sufficient to cause the semiconductor material to form a first film layer having a first grain size; (c) continually depositing the semiconductor material on the substrate while cooling the substrate to a second temperature sufficient to cause the semiconductor material to form a second film layer deposited on the first film layer and having a second grain size smaller than the first grain size; and (d) raising the substrate temperature, while either continuing or not continuing to deposit semiconductor material to form a third film layer, to thereby anneal the film layers into a single layer having favorable efficiency characteristics in photovoltaic applications. A preferred semiconductor material is cadmium telluride deposited on a glass/tin oxide substrate already having thereon a film layer of cadmium sulfide.

Nanomembrane structures having mixed crystalline orientations and compositions

DOEpatents

Lagally, Max G.; Scott, Shelley A.; Savage, Donald E.

2014-08-12

The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but which differs from the nanomembrane semiconductor materials in composition, crystal orientation, or both.

Infrared nanoantenna apparatus and method for the manufacture thereof

DOEpatents

Peters, David W.; Davids, Paul; Leonhardt, Darin; Kim, Jin K.; Wendt, Joel R.; Klem, John F.

2014-06-10

An exemplary embodiment of the present invention is a photodetector comprising a semiconductor body, a periodically patterned metal nanoantenna disposed on a surface of the semiconductor body, and at least one electrode separate from the nanoantenna. The semiconductor body comprises an active layer in sufficient proximity to the nanoantenna for plasmonic coupling thereto. The nanoantenna is dimensioned to absorb electromagnetic radiation in at least some wavelengths not more than 12 .mu.m that are effective for plasmonic coupling into the active layer. The electrode is part of an electrode arrangement for obtaining a photovoltage or photocurrent in operation under appropriate stimulation.

All-vapor processing of p-type tellurium-containing II-VI semiconductor and ohmic contacts thereof

DOEpatents

McCandless, Brian E.

2001-06-26

An all dry method for producing solar cells is provided comprising first heat-annealing a II-VI semiconductor; enhancing the conductivity and grain size of the annealed layer; modifying the surface and depositing a tellurium layer onto the enhanced layer; and then depositing copper onto the tellurium layer so as to produce a copper tellurium compound on the layer.

Photovoltaic healing of non-uniformities in semiconductor devices

DOEpatents

Karpov, Victor G.; Roussillon, Yann; Shvydka, Diana; Compaan, Alvin D.; Giolando, Dean M.

2006-08-29

A method of making a photovoltaic device using light energy and a solution to normalize electric potential variations in the device. A semiconductor layer having nonuniformities comprising areas of aberrant electric potential deviating from the electric potential of the top surface of the semiconductor is deposited onto a substrate layer. A solution containing an electrolyte, at least one bonding material, and positive and negative ions is applied over the top surface of the semiconductor. Light energy is applied to generate photovoltage in the semiconductor, causing a redistribution of the ions and the bonding material to the areas of aberrant electric potential. The bonding material selectively bonds to the nonuniformities in a manner such that the electric potential of the nonuniformities is normalized relative to the electric potential of the top surface of the semiconductor layer. A conductive electrode layer is then deposited over the top surface of the semiconductor layer.

Semiconductor light source with electrically tunable emission wavelength

DOEpatents

Belenky, Gregory [Port Jefferson, NY; Bruno, John D [Bowie, MD; Kisin, Mikhail V [Centereach, NY; Luryi, Serge [Setauket, NY; Shterengas, Leon [Centereach, NY; Suchalkin, Sergey [Centereach, NY; Tober, Richard L [Elkridge, MD

2011-01-25

A semiconductor light source comprises a substrate, lower and upper claddings, a waveguide region with imbedded active area, and electrical contacts to provide voltage necessary for the wavelength tuning. The active region includes single or several heterojunction periods sandwiched between charge accumulation layers. Each of the active region periods comprises higher and lower affinity semiconductor layers with type-II band alignment. The charge carrier accumulation in the charge accumulation layers results in electric field build-up and leads to the formation of generally triangular electron and hole potential wells in the higher and lower affinity layers. Nonequillibrium carriers can be created in the active region by means of electrical injection or optical pumping. The ground state energy in the triangular wells and the radiation wavelength can be tuned by changing the voltage drop across the active region.

Method and structure for passivating semiconductor material

DOEpatents

Pankove, Jacques I.

1981-01-01

A structure for passivating semiconductor material comprises a substrate of crystalline semiconductor material, a relatively thin film of carbon disposed on a surface of the crystalline material, and a layer of hydrogenated amorphous silicon deposited on the carbon film.

Semiconductor laser devices having lateral refractive index tailoring

DOEpatents

Ashby, Carol I. H.; Hadley, G. Ronald; Hohimer, John P.; Owyoung, Adelbert

1990-01-01

A broad-area semiconductor laser diode includes an active lasing region interposed between an upper and a lower cladding layer, the laser diode further comprising structure for controllably varying a lateral refractive index profile of the diode to substantially compensate for an effect of junction heating during operation. In embodiments disclosed the controlling structure comprises resistive heating strips or non-radiative linear junctions disposed parallel to the active region. Another embodiment discloses a multi-layered upper cladding region selectively disordered by implanted or diffused dopant impurities. Still another embodiment discloses an upper cladding layer of variable thickness that is convex in shape and symmetrically disposed about a central axis of the active region. The teaching of the invention is also shown to be applicable to arrays of semiconductor laser diodes.

Selective epitaxy using the gild process

DOEpatents

Weiner, Kurt H.

1992-01-01

The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.1-x grown over silicon. Such a process may be used to manufacture small transistors that have a narrow base, heavy doping, and high gain. The narrowness allows a faster transistor, and the heavy doping reduces the resistance of the narrow layer. The process does not require high temperature annealing; therefore materials such as aluminum can be used. Furthermore, the process may be used to fabricate diodes that have a high reverse breakdown voltage and a low reverse leakage current.

Broadband light-emitting diode

DOEpatents

Fritz, Ian J.; Klem, John F.; Hafich, Michael J.

1998-01-01

A broadband light-emitting diode. The broadband light-emitting diode (LED) comprises a plurality of III-V compound semiconductor layers grown on a semiconductor substrate, with the semiconductor layers including a pair of cladding layers sandwiched about a strained-quantum-well active region having a plurality of different energy bandgaps for generating light in a wavelength range of about 1.3-2 .mu.m. In one embodiment of the present invention, the active region may comprise a first-grown quantum-well layer and a last-grown quantum-well layer that are oppositely strained; whereas in another embodiment of the invention, the active region is formed from a short-period superlattice structure (i.e. a pseudo alloy) comprising alternating thin layers of InGaAs and InGaAlAs. The use a short-period superlattice structure for the active region allows different layers within the active region to be simply and accurately grown by repetitively opening and closing one or more shutters in an MBE growth apparatus to repetitively switch between different growth states therein. The broadband LED may be formed as either a surface-emitting LED or as an edge-emitting LED for use in applications such as chemical sensing, fiber optic gyroscopes, wavelength-division-multiplexed (WDM) fiber-optic data links, and WDM fiber-optic sensor networks for automobiles and aircraft.

Broadband light-emitting diode

DOEpatents

Fritz, I.J.; Klem, J.F.; Hafich, M.J.

1998-07-14

A broadband light-emitting diode is disclosed. The broadband light-emitting diode (LED) comprises a plurality of III-V compound semiconductor layers grown on a semiconductor substrate, with the semiconductor layers including a pair of cladding layers sandwiched about a strained-quantum-well active region having a plurality of different energy bandgaps for generating light in a wavelength range of about 1.3--2 {micro}m. In one embodiment of the present invention, the active region may comprise a first-grown quantum-well layer and a last-grown quantum-well layer that are oppositely strained; whereas in another embodiment of the invention, the active region is formed from a short-period superlattice structure (i.e. a pseudo alloy) comprising alternating thin layers of InGaAs and InGaAlAs. The use a short-period superlattice structure for the active region allows different layers within the active region to be simply and accurately grown by repetitively opening and closing one or more shutters in an MBE growth apparatus to repetitively switch between different growth states therein. The broadband LED may be formed as either a surface-emitting LED or as an edge-emitting LED for use in applications such as chemical sensing, fiber optic gyroscopes, wavelength-divisionmultiplexed (WDM) fiber-optic data links, and WDM fiber-optic sensor networks for automobiles and aircraft. 10 figs.

Pure silver ohmic contacts to N- and P- type gallium arsenide materials

DOEpatents

Hogan, Stephen J.

1986-01-01

Disclosed is an improved process for manufacturing gallium arsenide semiconductor devices having as its components an n-type gallium arsenide substrate layer and a p-type gallium arsenide diffused layer. The improved process comprises forming a pure silver ohmic contact to both the diffused layer and the substrate layer, wherein the n-type layer comprises a substantially low doping carrier concentration.

High efficiency photovoltaic device

DOEpatents

Guha, Subhendu; Yang, Chi C.; Xu, Xi Xiang

1999-11-02

An N-I-P type photovoltaic device includes a multi-layered body of N-doped semiconductor material which has an amorphous, N doped layer in contact with the amorphous body of intrinsic semiconductor material, and a microcrystalline, N doped layer overlying the amorphous, N doped material. A tandem device comprising stacked N-I-P cells may further include a second amorphous, N doped layer interposed between the microcrystalline, N doped layer and a microcrystalline P doped layer. Photovoltaic devices thus configured manifest improved performance, particularly when configured as tandem devices.

Photoelectrochemical cells for conversion of solar energy to electricity and methods of their manufacture

DOEpatents

Skotheim, Terje

1984-04-10

A photoelectric device is disclosed which comprises first and second layers of semiconductive material, each of a different bandgap, with a layer of dry solid polymer electrolyte disposed between the two semiconductor layers. A layer of a polymer blend of a highly conductive polymer and a solid polymer electrolyte is further interposed between the dry solid polymer electrolyte and the first semiconductor layer. A method of manufacturing such devices is also disclosed.

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

1987-06-08

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space. The layer thicknesses of the quantum well layers are selected to provide a superlattice L/sub 2D/-valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley. 2 figs.

Multi-junction solar cell device

DOEpatents

Friedman, Daniel J.; Geisz, John F.

2007-12-18

A multi-junction solar cell device (10) is provided. The multi-junction solar cell device (10) comprises either two or three active solar cells connected in series in a monolithic structure. The multi-junction device (10) comprises a bottom active cell (20) having a single-crystal silicon substrate base and an emitter layer (23). The multi-junction device (10) further comprises one or two subsequent active cells each having a base layer (32) and an emitter layer (23) with interconnecting tunnel junctions between each active cell. At least one layer that forms each of the top and middle active cells is composed of a single-crystal III-V semiconductor alloy that is substantially lattice-matched to the silicon substrate (22). The polarity of the active p-n junction cells is either p-on-n or n-on-p. The present invention further includes a method for substantially lattice matching single-crystal III-V semiconductor layers with the silicon substrate (22) by including boron and/or nitrogen in the chemical structure of these layers.

Integration of planar transformer and/or planar inductor with power switches in power converter

DOEpatents

Chen, Kanghua; Ahmed, Sayeed; Zhu, Lizhi

2007-10-30

A power converter integrates at least one planar transformer comprising a multi-layer transformer substrate and/or at least one planar inductor comprising a multi-layer inductor substrate with a number of power semiconductor switches physically and thermally coupled to a heat sink via one or more multi-layer switch substrates.

Process for forming pure silver ohmic contacts to N- and P-type gallium arsenide materials

DOEpatents

Hogan, S.J.

1983-03-13

Disclosed is an improved process for manufacturing gallium arsenide semiconductor devices having as its components a n-type gallium arsenide substrate layer and a p-type gallium arsenide diffused layer. The improved process comprises forming a pure silver ohmic contact to both the diffuse layer and the substrate layer wherein the n-type layer comprises a substantially low doping carrier concentration.

Photoelectrochemical cell including Ga(Sb.sub.x)N.sub.1-x semiconductor electrode

DOEpatents

Menon, Madhu; Sheetz, Michael; Sunkara, Mahendra Kumar; Pendyala, Chandrashekhar; Sunkara, Swathi; Jasinski, Jacek B.

2017-09-05

The composition of matter comprising Ga(Sb.sub.x)N.sub.1-x where x=0.01 to 0.06 is characterized by a band gap between 2.4 and 1.7 eV. A semiconductor device includes a semiconductor layer of that composition. A photoelectric cell includes that semiconductor device.

Infrared emitting device and method

DOEpatents

Kurtz, S.R.; Biefeld, R.M.; Dawson, L.R.; Howard, A.J.; Baucom, K.C.

1997-04-29

The infrared emitting device comprises a III-V compound semiconductor substrate upon which are grown a quantum-well active region having a plurality of quantum-well layers formed of a ternary alloy comprising InAsSb sandwiched between barrier layers formed of a ternary alloy having a smaller lattice constant and a larger energy bandgap than the quantum-well layers. The quantum-well layers are preferably compressively strained to increase the threshold energy for Auger recombination; and a method is provided for determining the preferred thickness for the quantum-well layers. Embodiments of the present invention are described having at least one cladding layer to increase the optical and carrier confinement in the active region, and to provide for waveguiding of the light generated within the active region. Examples have been set forth showing embodiments of the present invention as surface- and edge-emitting light emitting diodes (LEDs), an optically-pumped semiconductor laser, and an electrically-injected semiconductor diode laser. The light emission from each of the infrared emitting devices of the present invention is in the midwave infrared region of the spectrum from about 2 to 6 microns. 8 figs.

Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

DOEpatents

Jansen, Kai W.; Maley, Nagi

2000-01-01

High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

DOEpatents

Jansen, Kai W.; Maley, Nagi

2001-01-01

High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

Photodetector with enhanced light absorption

DOEpatents

Kane, James

1985-01-01

A photodetector including a light transmissive electrically conducting layer having a textured surface with a semiconductor body thereon. This layer traps incident light thereby enhancing the absorption of light by the semiconductor body. A photodetector comprising a textured light transmissive electrically conducting layer of SnO.sub.2 and a body of hydrogenated amorphous silicon has a conversion efficiency about fifty percent greater than that of comparative cells. The invention also includes a method of fabricating the photodetector of the invention.

Infrared emitting device and method

DOEpatents

Kurtz, Steven R.; Biefeld, Robert M.; Dawson, L. Ralph; Howard, Arnold J.; Baucom, Kevin C.

1997-01-01

An infrared emitting device and method. The infrared emitting device comprises a III-V compound semiconductor substrate upon which are grown a quantum-well active region having a plurality of quantum-well layers formed of a ternary alloy comprising InAsSb sandwiched between barrier layers formed of a ternary alloy having a smaller lattice constant and a larger energy bandgap than the quantum-well layers. The quantum-well layers are preferably compressively strained to increase the threshold energy for Auger recombination; and a method is provided for determining the preferred thickness for the quantum-well layers. Embodiments of the present invention are described having at least one cladding layer to increase the optical and carrier confinement in the active region, and to provide for waveguiding of the light generated within the active region. Examples have been set forth showing embodiments of the present invention as surface- and edge-emitting light emitting diodes (LEDs), an optically-pumped semiconductor laser, and an electrically-injected semiconductor diode laser. The light emission from each of the infrared emitting devices of the present invention is in the midwave infrared region of the spectrum from about 2 to 6 microns.

Self bleaching photoelectrochemical-electrochromic device

DOEpatents

Bechinger, Clemens S.; Gregg, Brian A.

2002-04-09

A photoelectrochemical-electrochromic device comprising a first transparent electrode and a second transparent electrode in parallel, spaced relation to each other. The first transparent electrode is electrically connected to the second transparent electrode. An electrochromic material is applied to the first transparent electrode and a nanoporous semiconductor film having a dye adsorbed therein is applied to the second transparent electrode. An electrolyte layer contacts the electrochromic material and the nanoporous semiconductor film. The electrolyte layer has a redox couple whereby upon application of light, the nanoporous semiconductor layer dye absorbs the light and the redox couple oxidizes producing an electric field across the device modulating the effective light transmittance through the device.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y. Simon; Deb, Satyen K.

1990-01-01

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

Deposition method for producing silicon carbide high-temperature semiconductors

DOEpatents

Hsu, George C.; Rohatgi, Naresh K.

1987-01-01

An improved deposition method for producing silicon carbide high-temperature semiconductor material comprising placing a semiconductor substrate composed of silicon carbide in a fluidized bed silicon carbide deposition reactor, fluidizing the bed particles by hydrogen gas in a mildly bubbling mode through a gas distributor and heating the substrate at temperatures around 1200.degree.-1500.degree. C. thereby depositing a layer of silicon carbide on the semiconductor substrate.

Method for making a photodetector with enhanced light absorption

DOEpatents

Kane, James

1987-05-05

A photodetector including a light transmissive electrically conducting layer having a textured surface with a semiconductor body thereon. This layer traps incident light thereby enhancing the absorption of light by the semiconductor body. A photodetector comprising a textured light transmissive electrically conducting layer of SnO.sub.2 and a body of hydrogenated amorphous silicon has a conversion efficiency about fifty percent greater than that of comparative cells. The invention also includes a method of fabricating the photodetector of the invention.

Dry etching method for compound semiconductors

DOEpatents

Shul, Randy J.; Constantine, Christopher

1997-01-01

A dry etching method. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators.

Dry etching method for compound semiconductors

DOEpatents

Shul, R.J.; Constantine, C.

1997-04-29

A dry etching method is disclosed. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators. 1 fig.

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, deceased, Roger J.; Dawson, Ralph; Fritz, Ian J.; Osbourn, Gordon C.; Zipperian, Thomas E.

1989-01-01

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space which includes a lowest energy .GAMMA.-valley and a next lowest energy L-valley, each k-vector corresponding to one of the orthogonal directions defined by the planes of said layers and the directions perpendicular thereto. The layer thicknesses of the quantum well layers are selected to provide a superlattice L.sub.2D -valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley.

Substrate for thin silicon solar cells

DOEpatents

Ciszek, Theodore F.

1995-01-01

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1.times.10.sup.-3 ohm-cm.

SLS complementary logic devices with increase carrier mobility

DOEpatents

Chaffin, R.J.; Osbourn, G.C.; Zipperian, T.E.

1991-07-09

In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated. 5 figures.

SLS complementary logic devices with increase carrier mobility

DOEpatents

Chaffin, Roger J.; Osbourn, Gordon C.; Zipperian, Thomas E.

1991-01-01

In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.

Electrically pumped edge-emitting photonic bandgap semiconductor laser

DOEpatents

Lin, Shawn-Yu; Zubrzycki, Walter J.

2004-01-06

A highly efficient, electrically pumped edge-emitting semiconductor laser based on a one- or two-dimensional photonic bandgap (PBG) structure is described. The laser optical cavity is formed using a pair of PBG mirrors operating in the photonic band gap regime. Transverse confinement is achieved by surrounding an active semiconductor layer of high refractive index with lower-index cladding layers. The cladding layers can be electrically insulating in the passive PBG mirror and waveguide regions with a small conducting aperture for efficient channeling of the injection pump current into the active region. The active layer can comprise a quantum well structure. The quantum well structure can be relaxed in the passive regions to provide efficient extraction of laser light from the active region.

Back wall solar cell

NASA Technical Reports Server (NTRS)

Brandhorst, H. W., Jr. (Inventor)

1978-01-01

A solar cell is disclosed which comprises a first semiconductor material of one conductivity type with one face having the same conductivity type but more heavily doped to form a field region arranged to receive the radiant energy to be converted to electrical energy, and a layer of a second semiconductor material, preferably highly doped, of opposite conductivity type on the first semiconductor material adjacent the first semiconductor material at an interface remote from the heavily doped field region. Instead of the opposite conductivity layer, a metallic Schottky diode layer may be used, in which case no additional back contact is needed. A contact such as a gridded contact, previous to the radiant energy may be applied to the heavily doped field region of the more heavily doped, same conductivity material for its contact.

Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor)

2011-01-01

Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.

Substrate for thin silicon solar cells

DOEpatents

Ciszek, T.F.

1995-03-28

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1{times}10{sup {minus}3} ohm-cm. 4 figures.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y.S.; Deb, S.K.

1990-10-02

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

DOEpatents

Seager, C.H.; Evans, J.T. Jr.

1998-11-24

A method is described for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100 C and 300 C for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer. 1 fig.

Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

DOEpatents

Seager, Carleton H.; Evans, Jr., Joseph Tate

1998-01-01

A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.

Use of separate ZnTe interface layers to form ohmic contacts to p-CdTe films

DOEpatents

Gessert, T.A.

1999-06-01

A method of is disclosed improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising: depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurium-containing II-VI semiconductor, but thin enough to minimize affects of series resistance; depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; and depositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact. 11 figs.

Use of separate ZnTe interface layers to form OHMIC contacts to p-CdTe films

DOEpatents

Gessert, Timothy A.

1999-01-01

A method of improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising: depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurim-containing II-VI semiconductor, but thin enough to minimize affects of series resistance; depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; and depositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact.

Layered semiconductor neutron detectors

DOEpatents

Mao, Samuel S; Perry, Dale L

2013-12-10

Room temperature operating solid state hand held neutron detectors integrate one or more relatively thin layers of a high neutron interaction cross-section element or materials with semiconductor detectors. The high neutron interaction cross-section element (e.g., Gd, B or Li) or materials comprising at least one high neutron interaction cross-section element can be in the form of unstructured layers or micro- or nano-structured arrays. Such architecture provides high efficiency neutron detector devices by capturing substantially more carriers produced from high energy .alpha.-particles or .gamma.-photons generated by neutron interaction.

Miniaturized Metal (Metal Alloy)/PdO(x)/SiC Hydrogen and Hydrocarbon Gas Sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO(x)). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600 C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sided sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Static ferroelectric memory transistor having improved data retention

DOEpatents

Evans, Jr., Joseph T.; Warren, William L.; Tuttle, Bruce A.

1996-01-01

An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO.sub.3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentrations between 1% and 8%.

Photon and carrier management design for nonplanar thin-film copper indium gallium diselenide photovoltaics

DOEpatents

Atwater, Harry A.; Callahan, Dennis; Bukowsky, Colton

2017-11-21

Photovoltaic structures are disclosed. The structures can comprise randomly or periodically structured layers, a dielectric layer to reduce back diffusion of charge carriers, and a metallic layer to reflect photons back towards the absorbing semiconductor layers. This design can increase efficiency of photovoltaic structures. The structures can be fabricated by nanoimprint.

Visible-wavelength semiconductor lasers and arrays

DOEpatents

Schneider, Jr., Richard P.; Crawford, Mary H.

1996-01-01

A visible semiconductor laser. The visible semiconductor laser includes an InAlGaP active region surrounded by one or more AlGaAs layers on each side, with carbon as the sole p-type dopant. Embodiments of the invention are provided as vertical-cavity surface-emitting lasers (VCSELs) and as edge-emitting lasers (EELs). One or more transition layers comprised of a substantially indium-free semiconductor alloy such as AlAsP, AlGaAsP, or the like may be provided between the InAlGaP active region and the AlGaAS DBR mirrors or confinement layers to improve carrier injection and device efficiency by reducing any band offsets. Visible VCSEL devices fabricated according to the invention with a one-wavelength-thick (1.lambda.) optical cavity operate continuous-wave (cw) with lasing output powers up to 8 mW, and a peak power conversion efficiency of up to 11%.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Schwank, James R.; Fleetwood, Daniel M.; Shaneyfelt, Marty R.; Winokur, Peter S.; Devine, Roderick A. B.

1998-01-01

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2011-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x ). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Xu, Jennifer C. (Inventor); Hunter, Gary W. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Dye-sensitized solar cells

DOEpatents

Skotheim, T.A.

1980-03-04

A low-cost dye-sensitized Schottky barrier solar cell is comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent. 3 figs.

Dye-sensitized solar cells

DOEpatents

Skotheim, Terje A. [Berkeley, CA

1980-03-04

A low-cost dye-sensitized Schottky barrier solar cell comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent.

Dye-sensitized Schottky barrier solar cells

DOEpatents

Skotheim, Terje A.

1978-01-01

A low-cost dye-sensitized Schottky barrier solar cell comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent.

Megavoltage imaging with a photoconductor based sensor

DOEpatents

Partain, Larry Dean [Los Altos, CA; Zentai, George [Mountain View, CA

2011-02-08

A photodetector for detecting megavoltage (MV) radiation comprises a semiconductor conversion layer having a first surface and a second surface disposed opposite the first surface, a first electrode coupled to the first surface, a second electrode coupled to the second surface, and a low density substrate including a detector array coupled to the second electrode opposite the semiconductor conversion layer. The photodetector includes a sufficient thickness of a high density material to create a sufficient number of photoelectrons from incident MV radiation, so that the photoelectrons can be received by the conversion layer and converted to a sufficient of recharge carriers for detection by the detector array.

Fabrication of ionic liquid electrodeposited Cu--Sn--Zn--S--Se thin films and method of making

DOEpatents

Bhattacharya, Raghu Nath

2016-01-12

A semiconductor thin-film and method for producing a semiconductor thin-films comprising a metallic salt, an ionic compound in a non-aqueous solution mixed with a solvent and processing the stacked layer in chalcogen that results in a CZTS/CZTSS thin films that may be deposited on a substrate is disclosed.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Schwank, J.R.; Fleetwood, D.M.; Shaneyfelt, M.R.; Winokur, P.S.; Devine, R.A.B.

1998-07-28

A method is disclosed for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer. 5 figs.

Nanocrystal doped matrixes

DOEpatents

Parce, J. Wallace; Bernatis, Paul; Dubrow, Robert; Freeman, William P.; Gamoras, Joel; Kan, Shihai; Meisel, Andreas; Qian, Baixin; Whiteford, Jeffery A.; Ziebarth, Jonathan

2010-01-12

Matrixes doped with semiconductor nanocrystals are provided. In certain embodiments, the semiconductor nanocrystals have a size and composition such that they absorb or emit light at particular wavelengths. The nanocrystals can comprise ligands that allow for mixing with various matrix materials, including polymers, such that a minimal portion of light is scattered by the matrixes. The matrixes of the present invention can also be utilized in refractive index matching applications. In other embodiments, semiconductor nanocrystals are embedded within matrixes to form a nanocrystal density gradient, thereby creating an effective refractive index gradient. The matrixes of the present invention can also be used as filters and antireflective coatings on optical devices and as down-converting layers. Processes for producing matrixes comprising semiconductor nanocrystals are also provided. Nanostructures having high quantum efficiency, small size, and/or a narrow size distribution are also described, as are methods of producing indium phosphide nanostructures and core-shell nanostructures with Group II-VI shells.

Tandem junction amorphous semiconductor photovoltaic cell

DOEpatents

Dalal, V.L.

1983-06-07

A photovoltaic stack comprising at least two p[sup +]i n[sup +] cells in optical series, said cells separated by a transparent ohmic contact layer(s), provides a long optical path for the absorption of photons while preserving the advantageous field-enhanced minority carrier collection arrangement characteristic of p[sup +]i n[sup +] cells. 3 figs.

Tandem junction amorphous semiconductor photovoltaic cell

DOEpatents

Dalal, Vikram L.

1983-01-01

A photovoltaic stack comprising at least two p.sup.+ i n.sup.+ cells in optical series, said cells separated by a transparent ohmic contact layer(s), provides a long optical path for the absorption of photons while preserving the advantageous field-enhanced minority carrier collection arrangement characteristic of p.sup.+ i n.sup.+ cells.

Visible-wavelength semiconductor lasers and arrays

DOEpatents

Schneider, R.P. Jr.; Crawford, M.H.

1996-09-17

The visible semiconductor laser includes an InAlGaP active region surrounded by one or more AlGaAs layers on each side, with carbon as the sole p-type dopant. Embodiments of the invention are provided as vertical-cavity surface-emitting lasers (VCSELs) and as edge-emitting lasers (EELs). One or more transition layers comprised of a substantially indium-free semiconductor alloy such as AlAsP, AlGaAsP, or the like may be provided between the InAlGaP active region and the AlGaAS DBR mirrors or confinement layers to improve carrier injection and device efficiency by reducing any band offsets. Visible VCSEL devices fabricated according to the invention with a one-wavelength-thick (1{lambda}) optical cavity operate continuous-wave (cw) with lasing output powers up to 8 mW, and a peak power conversion efficiency of up to 11%. 5 figs.

Gas-driven microturbine

DOEpatents

Sniegowski, Jeffrey J.; Rodgers, Murray S.; McWhorter, Paul J.; Aeschliman, Daniel P.; Miller, William M.

2002-01-01

A microturbine fabricated by a three-level semiconductor batch-fabrication process based on polysilicon surface-micromachining. The microturbine comprises microelectromechanical elements formed from three polysilicon multi-layer surfaces applied to a silicon substrate. Interleaving sacrificial oxide layers provides electrical and physical isolation, and selective etching of both the sacrificial layers and the polysilicon layers allows formation of individual mechanical and electrical elements as well as the required space for necessary movement of rotating turbine parts and linear elements.

Photo-Spectrometer Realized In A Standard Cmos Ic Process

DOEpatents

Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

1999-10-12

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Strained layer Fabry-Perot device

DOEpatents

Brennan, Thomas M.; Fritz, Ian J.; Hammons, Burrell E.

1994-01-01

An asymmetric Fabry-Perot reflectance modulator (AFPM) consists of an active region between top and bottom mirrors, the bottom mirror being affixed to a substrate by a buffer layer. The active region comprises a strained-layer region having a bandgap and thickness chosen for resonance at the Fabry-Perot frequency. The mirrors are lattice matched to the active region, and the buffer layer is lattice matched to the mirror at the interface. The device operates at wavelengths of commercially available semiconductor lasers.

Solar cell with a gallium nitride electrode

DOEpatents

Pankove, Jacques I.

1979-01-01

A solar cell which comprises a body of silicon having a P-N junction therein with a transparent conducting N-type gallium nitride layer as an ohmic contact on the N-type side of the semiconductor exposed to solar radiation.

Minority carrier device comprising a passivating layer including a Group 13 element and a chalcogenide component

NASA Technical Reports Server (NTRS)

Barron, Andrew R. (Inventor); Hepp, Aloysius F. (Inventor); Jenkins, Phillip P. (Inventor); MacInnes, Andrew N. (Inventor)

1999-01-01

A minority carrier device includes at least one junction of at least two dissimilar materials, at least one of which is a semiconductor, and a passivating layer on at least one surface of the device. The passivating layer includes a Group 13 element and a chalcogenide component. Embodiments of the minority carrier device include, for example, laser diodes, light emitting diodes, heterojunction bipolar transistors, and solar cells.

Systems and methods for producing low work function electrodes

DOEpatents

Kippelen, Bernard; Fuentes-Hernandez, Canek; Zhou, Yinhua; Kahn, Antoine; Meyer, Jens; Shim, Jae Won; Marder, Seth R.

2015-07-07

According to an exemplary embodiment of the invention, systems and methods are provided for producing low work function electrodes. According to an exemplary embodiment, a method is provided for reducing a work function of an electrode. The method includes applying, to at least a portion of the electrode, a solution comprising a Lewis basic oligomer or polymer; and based at least in part on applying the solution, forming an ultra-thin layer on a surface of the electrode, wherein the ultra-thin layer reduces the work function associated with the electrode by greater than 0.5 eV. According to another exemplary embodiment of the invention, a device is provided. The device includes a semiconductor; at least one electrode disposed adjacent to the semiconductor and configured to transport electrons in or out of the semiconductor.

Near-chip compliant layer for reducing perimeter stress during assembly process

DOEpatents

Schultz, Mark D.; Takken, Todd E.; Tian, Shurong; Yao, Yuan

2018-03-20

A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.

Near-chip compliant layer for reducing perimeter stress during assembly process

DOEpatents

Schultz, Mark D.; Takken, Todd E.; Tian, Shurong; Yao, Yuan

2017-02-14

A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.

Coated semiconductor devices for neutron detection

DOEpatents

Klann, Raymond T.; McGregor, Douglas S.

2002-01-01

A device for detecting neutrons includes a semi-insulated bulk semiconductor substrate having opposed polished surfaces. A blocking Schottky contact comprised of a series of metals such as Ti, Pt, Au, Ge, Pd, and Ni is formed on a first polished surface of the semiconductor substrate, while a low resistivity ("ohmic") contact comprised of metals such as Au, Ge, and Ni is formed on a second, opposed polished surface of the substrate. In one embodiment, n-type low resistivity pinout contacts comprised of an Au/Ge based eutectic alloy or multi-layered Pd/Ge/Ti/Au are also formed on the opposed polished surfaces and in contact with the Schottky and ohmic contacts. Disposed on the Schottky contact is a neutron reactive film, or coating, for detecting neutrons. The coating is comprised of a hydrogen rich polymer, such as a polyolefin or paraffin; lithium or lithium fluoride; or a heavy metal fissionable material. By varying the coating thickness and electrical settings, neutrons at specific energies can be detected. The coated neutron detector is capable of performing real-time neutron radiography in high gamma fields, digital fast neutron radiography, fissile material identification, and basic neutron detection particularly in high radiation fields.

Integrated Broadband Quantum Cascade Laser

NASA Technical Reports Server (NTRS)

Mansour, Kamjou (Inventor); Soibel, Alexander (Inventor)

2016-01-01

A broadband, integrated quantum cascade laser is disclosed, comprising ridge waveguide quantum cascade lasers formed by applying standard semiconductor process techniques to a monolithic structure of alternating layers of claddings and active region layers. The resulting ridge waveguide quantum cascade lasers may be individually controlled by independent voltage potentials, resulting in control of the overall spectrum of the integrated quantum cascade laser source. Other embodiments are described and claimed.

Planar varactor frequency multiplier devices with blocking barrier

NASA Technical Reports Server (NTRS)

Lieneweg, Udo (Inventor); Frerking, Margaret A. (Inventor); Maserjian, Joseph (Inventor)

1994-01-01

The invention relates to planar varactor frequency multiplier devices with a heterojunction blocking barrier for near millimeter wave radiation of moderate power from a fundamental input wave. The space charge limitation of the submillimeter frequency multiplier devices of the BIN(sup +) type is overcome by a diode structure comprising an n(sup +) doped layer of semiconductor material functioning as a low resistance back contact, a layer of semiconductor material with n-type doping functioning as a drift region grown on the back contact layer, a delta doping sheet forming a positive charge at the interface of the drift region layer with a barrier layer, and a surface metal contact. The layers thus formed on an n(sup +) doped layer may be divided into two isolated back-to-back BNN(sup +) diodes by separately depositing two surface metal contacts. By repeating the sequence of the drift region layer and the barrier layer with the delta doping sheet at the interfaces between the drift and barrier layers, a plurality of stacked diodes is formed. The novelty of the invention resides in providing n-type semiconductor material for the drift region in a GaAs/AlGaAs structure, and in stacking a plurality of such BNN(sup +) diodes stacked for greater output power with and connected back-to-back with the n(sup +) GaAs layer as an internal back contact and separate metal contact over an AlGaAs barrier layer on top of each stack.

Method for making defect-free zone by laser-annealing of doped silicon

DOEpatents

Narayan, Jagdish; White, Clark W.; Young, Rosa T.

1980-01-01

This invention is a method for improving the electrical properties of silicon semiconductor material. The method comprises irradiating a selected surface layer of the semiconductor material with high-power laser pulses characterized by a special combination of wavelength, energy level, and duration. The combination effects melting of the layer without degrading electrical properties, such as minority-carrier diffusion length. The method is applicable to improving the electrical properties of n- and p-type silicon which is to be doped to form an electrical junction therein. Another important application of the method is the virtually complete removal of doping-induced defects from ion-implanted or diffusion-doped silicon substrates.

Phase-separated, epitaxial composite cap layers for electronic device applications and method of making the same

DOEpatents

Aytug, Tolga [Knoxville, TN; Paranthaman, Mariappan Parans [Knoxville, TN; Polat, Ozgur [Knoxville, TN

2012-07-17

An electronic component that includes a substrate and a phase-separated layer supported on the substrate and a method of forming the same are disclosed. The phase-separated layer includes a first phase comprising lanthanum manganate (LMO) and a second phase selected from a metal oxide (MO), metal nitride (MN), a metal (Me), and combinations thereof. The phase-separated material can be an epitaxial layer and an upper surface of the phase-separated layer can include interfaces between the first phase and the second phase. The phase-separated layer can be supported on a buffer layer comprising a composition selected from the group consisting of IBAD MgO, LMO/IBAD-MgO, homoepi-IBAD MgO and LMO/homoepi-MgO. The electronic component can also include an electronically active layer supported on the phase-separated layer. The electronically active layer can be a superconducting material, a ferroelectric material, a multiferroic material, a magnetic material, a photovoltaic material, an electrical storage material, and a semiconductor material.

Diode and method of making the same

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dickerson, Jeramy Ray; Wierer, Jr., Jonathan; Kaplar, Robert

2018-03-13

A diode includes a second semiconductor layer over a first semiconductor layer. The diode further includes a third semiconductor layer over the second semiconductor layer, where the third semiconductor layer includes a first semiconductor element over the second semiconductor layer. The third semiconductor layer additionally includes a second semiconductor element over the second semiconductor layer, wherein the second semiconductor element surrounds the first semiconductor element. Further, the third semiconductor layer includes a third semiconductor element over the second semiconductor element. Furthermore, a hole concentration of the second semiconductor element is less than a hole concentration of the first semiconductor element.

Thin film heterojunction photovoltaic cells and methods of making the same

DOEpatents

Basol, Bulent M.; Tseng, Eric S.; Rod, Robert L.

1983-06-14

A method of fabricating a thin film heterojunction photovoltaic cell which comprises depositing a film of a near intrinsic or n-type semiconductor compound formed of at least one of the metal elements of Class II B of the Periodic Table of Elements and at least tellurium and then heating said film at a temperature between about 250.degree. C. and 500.degree. C. for a time sufficient to convert said film to a suitably low resistivity p-type semiconductor compound. Such film may be deposited initially on the surface of an n-type semiconductor substrate. Alternatively, there may be deposited on the converted film a layer of n-type semiconductor compound different from the film semiconductor compound. The resulting photovoltaic cell exhibits a substantially increased power output over similar cells not subjected to the method of the present invention.

Method and making group IIB metal - telluride films and solar cells

DOEpatents

Basol, Bulent M.; Kapur, Vijay K.

1990-08-21

A technique is disclosed forming thin films (13) of group IIB metal-telluride, such as Cd.sub.x Zn.sub.1-x Te (0.ltoreq.x.ltoreq.1), on a substrate (10) which comprises depositing Te (18) and at least one of the elements (19) of Cd, Zn, and Hg onto a substrate and then heating the elements to form the telluride. A technique is also provided for doping this material by chemically forming a thin layer of a dopant on the surface of the unreacted elements and then heating the elements along with the layer of dopant. A method is disclosed of fabricating a thin film photovoltaic cell which comprises depositing Te and at least one of the elements of Cd, Zn, and Hg onto a substrate which contains on its surface a semiconductor film (12) and then heating the elements in the presence of a halide of the Group IIB metals, causing the formation of solar cell grade Group IIB metal-telluride film and also causing the formation of a rectifying junction, in situ, between the semiconductor film on the substrate and the Group IIB metal-telluride layer which has been formed.

Label-free detection of biomolecules with Ta2O5-based field effect devices

NASA Astrophysics Data System (ADS)

Branquinho, Rita Maria Mourao Salazar

Field-effect-based devices (FEDs) are becoming a basic structural element in a new generation of micro biosensors. Their numerous advantages such as small size, labelfree response and versatility, together with the possibility of on-chip integration of biosensor arrays with a future prospect of low-cost mass production, make their development highly desirable. The present thesis focuses on the study and optimization of tantalum pentoxide (Ta2O5) deposited by rf magnetron sputtering at room temperature, and their application as sensitive layer in biosensors based on field effect devices (BioFEDs). As such, the influence of several deposition parameters and post-processing annealing temperature and surface plasma treatment on the film¡¦s properties was investigated. Electrolyte-insulator-semiconductor (EIS) field-effect-based sensors comprising the optimized Ta2O5 sensitive layer were applied to the development of BioFEDs. Enzyme functionalized sensors (EnFEDs) were produced for penicillin detection. These sensors were also applied to the label free detection of DNA and the monitoring of its amplification via polymerase chain reaction (PCR), real time PCR (RT-PCR) and loop mediated isothermal amplification (LAMP). Ion sensitive field effect transistors (ISFETs) based on semiconductor oxides comprising the optimized Ta2O5 sensitive layer were also fabricated. EIS sensors comprising Ta2O5 films produced with optimized conditions demonstrated near Nernstian pH sensitivity, 58+/-0.3 mV/pH. These sensors were successfully applied to the label-free detection of penicillin and DNA. Penicillinase functionalized sensors showed a 29+/-7 mV/mM sensitivity towards penicillin detection up to 4 mM penicillin concentration. DNA detection was achieved with 30 mV/mugM sensitivity and DNA amplification monitoring with these sensors showed comparable results to those obtained with standard fluorescence based methods. Semiconductor oxides-based ISFETs with Ta2O5 sensitive layer were also produced. Finally, the high quality and sensitivity demonstrated by Ta2O5 thin films produced at low temperature by rf magnetron sputtering allows for their application as sensitive layer in field effect sensors.

Nonvolatile semiconductor memory having three dimension charge confinement

DOEpatents

Dawson, L. Ralph; Osbourn, Gordon C.; Peercy, Paul S.; Weaver, Harry T.; Zipperian, Thomas E.

1991-01-01

A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.

Buried superconducting layers comprised of magnesium diboride nanocrystals formed by ion implantation

NASA Astrophysics Data System (ADS)

Zhai, H. Y.; Christen, H. M.; White, C. W.; Budai, J. D.; Lowndes, D. H.; Meldrum, A.

2002-06-01

Superconducting layers of MgB2 were formed on Si substrates using techniques that are widely used and accepted in the semiconductor industry. Mg ions were implanted into boron films deposited on Si or Al2O3 substrates. After a thermal processing step, buried superconducting layers comprised of MgB2 nanocrystals were obtained which exhibit the highest Tc reported so far for MgB2 on silicon (Tconsetapproximately33.6 K, DeltaTc=0.5 K, as measured by current transport). These results show that our approach is clearly applicable to the fabrication of superconducting devices that can be operated at much higher temperatures (approximately20 K) than the current Nb technology (approximately6 K) while their integration with silicon structures remains straight-forward.

Long wavelength, high gain InAsSb strained-layer superlattice photoconductive detectors

DOEpatents

Biefeld, Robert M.; Dawson, L. Ralph; Fritz, Ian J.; Kurtz, Steven R.; Zipperian, Thomas E.

1991-01-01

A high gain photoconductive device for 8 to 12 .mu.m wavelength radiation including an active semiconductor region extending from a substrate to an exposed face, the region comprising a strained-layer superlattice of alternating layers of two different InAs.sub.1-x Sb.sub.x compounds having x>0.75. A pair of spaced electrodes are provided on the exposed face, and changes in 8 to 12 .mu.m radiation on the exposed face cause a large photoconductive gain between the spaced electrodes.

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Treesearch

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Highly efficient quantum dot-based photoconductive THz materials and devices

NASA Astrophysics Data System (ADS)

Rafailov, E. U.; Leyman, R.; Carnegie, D.; Bazieva, N.

2013-09-01

We demonstrate Terahertz (THz) signal sources based on photoconductive (PC) antenna devices comprising active layers of InAs semiconductor quantum dots (QDs) on GaAs. Antenna structures comprised of multiple active layers of InAs:GaAs PC materials are optically pumped using ultrashort pulses generated by a Ti:Sapphire laser and CW dualwavelength laser diodes. We also characterised THz output signals using a two-antenna coherent detection system. We discuss preliminary performance data from such InAs:GaAs THz devices which exhibit efficient emission of both pulsed and continuous wave (CW) THz signals and significant optical-to-THz conversion at both absorption wavelength ranges, <=850 nm and <=1300 nm.

Artificial semiconductor/insulator superlattice channel structure for high-performance oxide thin-film transistors

PubMed Central

Ahn, Cheol Hyoun; Senthil, Karuppanan; Cho, Hyung Koun; Lee, Sang Yeol

2013-01-01

High-performance thin-film transistors (TFTs) are the fundamental building blocks in realizing the potential applications of the next-generation displays. Atomically controlled superlattice structures are expected to induce advanced electric and optical performance due to two-dimensional electron gas system, resulting in high-electron mobility transistors. Here, we have utilized a semiconductor/insulator superlattice channel structure comprising of ZnO/Al2O3 layers to realize high-performance TFTs. The TFT with ZnO (5 nm)/Al2O3 (3.6 nm) superlattice channel structure exhibited high field effect mobility of 27.8 cm2/Vs, and threshold voltage shift of only < 0.5 V under positive/negative gate bias stress test during 2 hours. These properties showed extremely improved TFT performance, compared to ZnO TFTs. The enhanced field effect mobility and stability obtained for the superlattice TFT devices were explained on the basis of layer-by-layer growth mode, improved crystalline nature of the channel layers, and passivation effect of Al2O3 layers. PMID:24061388

Semiconductor structure and recess formation etch technique

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Bin; Sun, Min; Palacios, Tomas Apostol

2017-02-14

A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching processmore » stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.« less

Plastic Schottky barrier solar cells

DOEpatents

Waldrop, James R.; Cohen, Marshall J.

1984-01-24

A photovoltaic cell structure is fabricated from an active medium including an undoped, intrinsically p-type organic semiconductor comprising polyacetylene. When a film of such material is in rectifying contact with a magnesium electrode, a Schottky-barrier junction is obtained within the body of the cell structure. Also, a gold overlayer passivates the magnesium layer on the undoped polyacetylene film.

Infrared light sources with semimetal electron injection

DOEpatents

Kurtz, Steven R.; Biefeld, Robert M.; Allerman, Andrew A.

1999-01-01

An infrared light source is disclosed that comprises a layered semiconductor active region having a semimetal region and at least one quantum-well layer. The semimetal region, formed at an interface between a GaAsSb or GalnSb layer and an InAsSb layer, provides electrons and holes to the quantum-well layer to generate infrared light at a predetermined wavelength in the range of 2-6 .mu.m. Embodiments of the invention can be formed as electrically-activated light-emitting diodes (LEDs) or lasers, and as optically-pumped lasers. Since the active region is unipolar, multiple active regions can be stacked to form a broadband or multiple-wavelength infrared light source.

Method of making silicon on insalator material using oxygen implantation

DOEpatents

Hite, Larry R.; Houston, Ted; Matloubian, Mishel

1989-01-01

The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

Multi-harmonic quantum dot optomechanics in fused LiNbO3-(Al)GaAs hybrids

NASA Astrophysics Data System (ADS)

Nysten, Emeline D. S.; Huo, Yong Heng; Yu, Hailong; Song, Guo Feng; Rastelli, Armando; Krenner, Hubert J.

2017-11-01

We fabricated an acousto-optic semiconductor hybrid device for strong optomechanical coupling of individual quantum emitters and a surface acoustic wave. Our device comprises of a surface acoustic wave chip made from highly piezoelectric LiNbO3 and a GaAs-based semiconductor membrane with an embedded layer of quantum dots. Employing multi-harmonic transducers, we generated sound waves on LiNbO3 over a wide range of radio frequencies. We monitored their coupling to and propagation across the semiconductor membrane, both in the electrical and optical domain. We demonstrate the enhanced optomechanical tuning of the embedded quantum dots with increasing frequencies. This effect was verified by finite element modelling of our device geometry and attributed to an increased localization of the acoustic field within the semiconductor membrane. For moderately high acoustic frequencies, our simulations predict strong optomechanical coupling, making our hybrid device ideally suited for applications in semiconductor based quantum acoustics.

A new detector concept for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Sadigov, A.; Ahmadov, F.; Ahmadov, G.; Ariffin, A.; Khorev, S.; Sadygov, Z.; Suleymanov, S.; Zerrouk, F.; Madatov, R.

2016-07-01

A new design and principle of operation of silicon photomultipliers are presented. The new design comprises a semiconductor substrate and an array of independent micro-phototransistors formed on the substrate. Each micro-phototransistor comprises a photosensitive base operating in Geiger mode and an individual micro-emitter covering a small part of the base layer, thereby creating, together with this latter, a micro-transistor. Both micro-emitters and photosensitive base layers are connected with two respective independent metal grids via their individual micro-resistors. The total value of signal gain in the proposed silicon photomultiplier is a result of both the avalanche gain in the base layer and the corresponding gain in the micro-transistor. The main goals of the new design are: significantly lower both optical crosstalk and after-pulse effects at high signal amplification, improve speed of single photoelectron pulse formation, and significantly reduce the device capacitance.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dahal, Rajendra P.; Bhat, Ishwara B.; Chow, Tat-Sing

Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.

Photovoltaic driven multiple quantum well optical modulator

NASA Technical Reports Server (NTRS)

Maserjian, Joseph (Inventor)

1990-01-01

Multiple quantum well (MQW) structures (12) are utilized to provide real-time, reliable, high-performance, optically-addressed spatial-light modulators (SLM) (10). The optically-addressed SLM comprises a vertical stack of quantum well layers (12a) within the penetration depth of an optical write signal 18, a plurality of space charge barriers (12b) having predetermined tunneling times by control of doping and thickness. The material comprising the quantum well layers has a lower bandgap than that of the space charge barrier layers. The write signal modulates a read signal (20). The modulation sensitivity of the device is high and no external voltage source is required. In a preferred embodiment, the SLM having interleaved doped semiconductor layers for driving the MQW photovoltaically is characterized by the use of a shift analogous to the Moss-Burnstein shift caused by the filling of two-dimensional states in the multiple quantum wells, thus allowing high modulation sensitivity in very narrow wells. Arrays (30) may be formed with a plurality of the modulators.

Interface and gate bias dependence responses of sensing organic thin-film transistors.

PubMed

Tanese, Maria Cristina; Fine, Daniel; Dodabalapur, Ananth; Torsi, Luisa

2005-11-15

The effects of the exposure of organic thin-film transistors, comprising different organic semiconductors and gate dielectrics, to 1-pentanol are investigated. The transistor sensors exhibited an increase or a decrease of the transient source-drain current in the presence of the analyte, most likely as a result of a trapping or of a doping process of the organic active layer. The occurrence of these two effects, that can also coexist, depend on the gate-dielectric/organic semiconductor interface and on the applied gate field. Evidence of a systematic and sizable response enhancement for an OTFT sensor operated in the enhanced mode is also presented.

Preparation of dilute magnetic semiconductor films by metalorganic chemical vapor deposition

NASA Technical Reports Server (NTRS)

Nouhi, Akbar (Inventor); Stirn, Richard J. (Inventor)

1988-01-01

A method for preparation of a dilute magnetic semiconductor (DMS) film is provided, in which a Group II metal source, a Group VI metal source and a transition metal magnetic ion source are pyrolyzed in the reactor of a metalorganic chemical vapor deposition (MOCVD) system by contact with a heated substrate. As an example, the preparation of films of Cd(sub 1-x)Mn(sub x)Te, in which 0 is less than or equal to x less than or equal to 0.7, on suitable substrates (e.g., GaAs) is described. As a source of manganese, tricarbonyl (methylcyclopentadienyl) manganese (TCPMn) is employed. To prevent TCPMn condensation during its introduction into the reactor, the gas lines, valves and reactor tubes are heated. A thin-film solar cell of n-i-p structure, in which the i-type layer comprises a DMS, is also described; the i-type layer is suitably prepared by MOCVD.

Preparation of dilute magnetic semiconductor films by metalorganic chemical vapor deposition

NASA Technical Reports Server (NTRS)

Nouhi, Akbar (Inventor); Stirn, Richard J. (Inventor)

1990-01-01

A method for preparation of a dilute magnetic semiconductor (DMS) film is provided, wherein a Group II metal source, a Group VI metal source and a transition metal magnetic ion source are pyrolyzed in the reactor of a metalorganic chemical vapor deposition (MOCVD) system by contact with a heated substrate. As an example, the preparation of films of Cd.sub.1-x Mn.sub.x Te, wherein 0.ltoreq..times..ltoreq.0.7, on suitable substrates (e.g., GaAs) is described. As a source of manganese, tricarbonyl (methylcyclopentadienyl) maganese (TCPMn) is employed. To prevent TCPMn condensation during the introduction thereof int the reactor, the gas lines, valves and reactor tubes are heated. A thin-film solar cell of n-i-p structure, wherein the i-type layer comprises a DMS, is also described; the i-type layer is suitably prepared by MOCVD.

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al{sub 2}O{sub 3} gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aoki, Takeshi, E-mail: aokit@sc.sumitomo-chem.co.jp; Fukuhara, Noboru; Osada, Takenori

2015-08-15

This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al{sub 2}O{sub 3} gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al{sub 2}O{sub 3} in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al{sub 2}O{sub 3} layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resultingmore » MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (D{sub it}) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce D{sub it} to below 2 × 10{sup 12} cm{sup −2} eV{sup −1}. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.« less

Architectures and criteria for the design of high efficiency organic photovoltaic cells

DOEpatents

Rand, Barry; Forrest, Stephen R; Burk, Diana Pendergrast

2015-03-24

An organic photovoltaic cell includes an anode and a cathode, and a plurality of organic semiconductor layers between the anode and the cathode. At least one of the anode and the cathode is transparent. Each two adjacent layers of the plurality of organic semiconductor layers are in direct contact. The plurality of organic semiconductor layers includes an intermediate layer consisting essentially of a photoconductive material, and two sets of at least three layers. A first set of at least three layers is between the intermediate layer and the anode. Each layer of the first set consists essentially of a different organic semiconductor material having a higher LUMO and a higher HOMO, relative to the material of an adjacent layer of the plurality of organic semiconductor layers closer to the cathode. A second set of at least three layers is between the intermediate layer and the cathode. Each layer of the second set consists essentially of a different organic semiconductor material having a lower LUMO and a lower HOMO, relative to the material of an adjacent layer of the plurality of organic semiconductor layers closer to the anode.

Method of transferring a thin crystalline semiconductor layer

DOEpatents

Nastasi, Michael A [Sante Fe, NM; Shao, Lin [Los Alamos, NM; Theodore, N David [Mesa, AZ

2006-12-26

A method for transferring a thin semiconductor layer from one substrate to another substrate involves depositing a thin epitaxial monocrystalline semiconductor layer on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the thin semiconductor layer is bonded to a second substrate and the thin layer is separated away at the interface, which results in transferring the thin epitaxial semiconductor layer from one substrate to the other substrate.

High-efficiency photovoltaic cells

DOEpatents

Yang, H.T.; Zehr, S.W.

1982-06-21

High efficiency solar converters comprised of a two cell, non-lattice matched, monolithic stacked semiconductor configuration using optimum pairs of cells having bandgaps in the range 1.6 to 1.7 eV and 0.95 to 1.1 eV, and a method of fabrication thereof, are disclosed. The high band gap subcells are fabricated using metal organic chemical vapor deposition (MOCVD), liquid phase epitaxy (LPE) or molecular beam epitaxy (MBE) to produce the required AlGaAs layers of optimized composition, thickness and doping to produce high performance, heteroface homojunction devices. The low bandgap subcells are similarly fabricated from AlGa(As)Sb compositions by LPE, MBE or MOCVD. These subcells are then coupled to form a monolithic structure by an appropriate bonding technique which also forms the required transparent intercell ohmic contact (IOC) between the two subcells. Improved ohmic contacts to the high bandgap semiconductor structure can be formed by vacuum evaporating to suitable metal or semiconductor materials which react during laser annealing to form a low bandgap semiconductor which provides a low contact resistance structure.

Implantable biomedical devices on bioresorbable substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rogers, John A; Kim, Dae-Hyeong; Omenetto, Fiorenzo

Provided herein are implantable biomedical devices, methods of administering implantable biomedical devices, methods of making implantable biomedical devices, and methods of using implantable biomedical devices to actuate a target tissue or sense a parameter associated with the target tissue in a biological environment. Each implantable biomedical device comprises a bioresorbable substrate, an electronic device having a plurality of inorganic semiconductor components supported by the bioresorbable substrate, and a barrier layer encapsulating at least a portion of the inorganic semiconductor components. Upon contact with a biological environment the bioresorbable substrate is at least partially resorbed, thereby establishing conformal contact between themore » implantable biomedical device and the target tissue in the biological environment.« less

Continuous wave terahertz radiation from an InAs/GaAs quantum-dot photomixer device

NASA Astrophysics Data System (ADS)

Kruczek, T.; Leyman, R.; Carnegie, D.; Bazieva, N.; Erbert, G.; Schulz, S.; Reardon, C.; Reynolds, S.; Rafailov, E. U.

2012-08-01

Generation of continuous wave radiation at terahertz (THz) frequencies from a heterodyne source based on quantum-dot (QD) semiconductor materials is reported. The source comprises an active region characterised by multiple alternating photoconductive and QD carrier trapping layers and is pumped by two infrared optical signals with slightly offset wavelengths, allowing photoconductive device switching at the signals' difference frequency ˜1 THz.

Process for forming shaped group III-V semiconductor nanocrystals, and product formed using process

DOEpatents

Alivisatos, A. Paul; Peng, Xiaogang; Manna, Liberato

2001-01-01

A process for the formation of shaped Group III-V semiconductor nanocrystals comprises contacting the semiconductor nanocrystal precursors with a liquid media comprising a binary mixture of phosphorus-containing organic surfactants capable of promoting the growth of either spherical semiconductor nanocrystals or rod-like semiconductor nanocrystals, whereby the shape of the semiconductor nanocrystals formed in said binary mixture of surfactants is controlled by adjusting the ratio of the surfactants in the binary mixture.

Process for forming shaped group II-VI semiconductor nanocrystals, and product formed using process

DOEpatents

Alivisatos, A. Paul; Peng, Xiaogang; Manna, Liberato

2001-01-01

A process for the formation of shaped Group II-VI semiconductor nanocrystals comprises contacting the semiconductor nanocrystal precursors with a liquid media comprising a binary mixture of phosphorus-containing organic surfactants capable of promoting the growth of either spherical semiconductor nanocrystals or rod-like semiconductor nanocrystals, whereby the shape of the semiconductor nanocrystals formed in said binary mixture of surfactants is controlled by adjusting the ratio of the surfactants in the binary mixture.

Method of forming thermally stable high-resistivity regions in n-type indium phosphide by oxygen implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Thompson, P.E.; Dietrich, H.B.

1985-12-12

Objects of this invention are: to form high-temperature stable isolation regions in InP; to provide InP wafers that allow greater flexibility in the design and fabrication of discrete devices; to provide new and improved InP semiconductor devices in n-type InP; to provide high-resisitivity isolation regions in InP; to extend the usefulness of damage-induced isolation in n-type InP by making possible processes in which the isolation implantation precedes the alloying of ohmic contacts; and to provide n-type InP substrates without unwanted conductive layers. The above and other object are realized by an InP wafer comprising a S.I. InP substrate; a n-typemore » InP active layer disposed on the substrate; and oxygen ion implanted isolation regions disposed in the active layer. The S.I. InP dopant may comprise either Fe or Cr.« less

Semiconductor nanocrystal-based phagokinetic tracking

DOEpatents

Alivisatos, A Paul; Larabell, Carolyn A; Parak, Wolfgang J; Le Gros, Mark; Boudreau, Rosanne

2014-11-18

Methods for determining metabolic properties of living cells through the uptake of semiconductor nanocrystals by cells. Generally the methods require a layer of neutral or hydrophilic semiconductor nanocrystals and a layer of cells seeded onto a culture surface and changes in the layer of semiconductor nanocrystals are detected. The observed changes made to the layer of semiconductor nanocrystals can be correlated to such metabolic properties as metastatic potential, cell motility or migration.

Buried Porous Silicon-Germanium Layers in Monocrystalline Silicon Lattices

NASA Technical Reports Server (NTRS)

Fathauer, Robert W. (Inventor); George, Thomas (Inventor); Jones, Eric W. (Inventor)

1998-01-01

Monocrystalline semiconductor lattices with a buried porous semiconductor layer having different chemical composition is discussed and monocrystalline semiconductor superlattices with a buried porous semiconductor layers having different chemical composition than that of its monocrystalline semiconductor superlattice are discussed. Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si-Ge layers followed by patterning into mesa structures. The mesa structures are strain etched resulting in porosification of the Si-Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si-Ge layers produced in a similar manner emitted visible light at room temperature.

Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction

DOEpatents

Tauke-Pedretti, Anna; Nielson, Gregory N; Cederberg, Jeffrey G; Cruz-Campa, Jose Luis

2015-05-12

A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.

Conductive layer for biaxially oriented semiconductor film growth

DOEpatents

Findikoglu, Alp T.; Matias, Vladimir

2007-10-30

A conductive layer for biaxially oriented semiconductor film growth and a thin film semiconductor structure such as, for example, a photodetector, a photovoltaic cell, or a light emitting diode (LED) that includes a crystallographically oriented semiconducting film disposed on the conductive layer. The thin film semiconductor structure includes: a substrate; a first electrode deposited on the substrate; and a semiconducting layer epitaxially deposited on the first electrode. The first electrode includes a template layer deposited on the substrate and a buffer layer epitaxially deposited on the template layer. The template layer includes a first metal nitride that is electrically conductive and has a rock salt crystal structure, and the buffer layer includes a second metal nitride that is electrically conductive. The semiconducting layer is epitaxially deposited on the buffer layer. A method of making such a thin film semiconductor structure is also described.

Narrow band gap amorphous silicon semiconductors

DOEpatents

Madan, A.; Mahan, A.H.

1985-01-10

Disclosed is a narrow band gap amorphous silicon semiconductor comprising an alloy of amorphous silicon and a band gap narrowing element selected from the group consisting of Sn, Ge, and Pb, with an electron donor dopant selected from the group consisting of P, As, Sb, Bi and N. The process for producing the narrow band gap amorphous silicon semiconductor comprises the steps of forming an alloy comprising amorphous silicon and at least one of the aforesaid band gap narrowing elements in amount sufficient to narrow the band gap of the silicon semiconductor alloy below that of amorphous silicon, and also utilizing sufficient amounts of the aforesaid electron donor dopant to maintain the amorphous silicon alloy as an n-type semiconductor.

Field-effect P-N junction

DOEpatents

Regan, William; Zettl, Alexander

2015-05-05

This disclosure provides systems, methods, and apparatus related to field-effect p-n junctions. In one aspect, a device includes an ohmic contact, a semiconductor layer disposed on the ohmic contact, at least one rectifying contact disposed on the semiconductor layer, a gate including a layer disposed on the at least one rectifying contact and the semiconductor layer and a gate contact disposed on the layer. A lateral width of the rectifying contact is less than a semiconductor depletion width of the semiconductor layer. The gate contact is electrically connected to the ohmic contact to create a self-gating feedback loop that is configured to maintain a gate electric field of the gate.

Organic photosensitive cells grown on rough electrode with nano-scale morphology control

DOEpatents

Yang, Fan [Piscataway, NJ; Forrest, Stephen R [Ann Arbor, MI

2011-06-07

An optoelectronic device and a method for fabricating the optoelectronic device includes a first electrode disposed on a substrate, an exposed surface of the first electrode having a root mean square roughness of at least 30 nm and a height variation of at least 200 nm, the first electrode being transparent. A conformal layer of a first organic semiconductor material is deposited onto the first electrode by organic vapor phase deposition, the first organic semiconductor material being a small molecule material. A layer of a second organic semiconductor material is deposited over the conformal layer. At least some of the layer of the second organic semiconductor material directly contacts the conformal layer. A second electrode is deposited over the layer of the second organic semiconductor material. The first organic semiconductor material is of a donor-type or an acceptor-type relative to the second organic semiconductor material, which is of the other material type.

Bi-Se doped with Cu, p-type semiconductor

DOEpatents

Bhattacharya, Raghu Nath; Phok, Sovannary; Parilla, Philip Anthony

2013-08-20

A Bi--Se doped with Cu, p-type semiconductor, preferably used as an absorber material in a photovoltaic device. Preferably the semiconductor has at least 20 molar percent Cu. In a preferred embodiment, the semiconductor comprises at least 28 molar percent of Cu. In one embodiment, the semiconductor comprises a molar percentage of Cu and Bi whereby the molar percentage of Cu divided by the molar percentage of Bi is greater than 1.2. In a preferred embodiment, the semiconductor is manufactured as a thin film having a thickness less than 600 nm.

Visible light surface emitting semiconductor laser

DOEpatents

Olbright, Gregory R.; Jewell, Jack L.

1993-01-01

A vertical-cavity surface-emitting laser is disclosed comprising a laser cavity sandwiched between two distributed Bragg reflectors. The laser cavity comprises a pair of spacer layers surrounding one or more active, optically emitting quantum-well layers having a bandgap in the visible which serve as the active optically emitting material of the device. The thickness of the laser cavity is m .lambda./2n.sub.eff where m is an integer, .lambda. is the free-space wavelength of the laser radiation and n.sub.eff is the effective index of refraction of the cavity. Electrical pumping of the laser is achieved by heavily doping the bottom mirror and substrate to one conductivity-type and heavily doping regions of the upper mirror with the opposite conductivity type to form a diode structure and applying a suitable voltage to the diode structure. Specific embodiments of the invention for generating red, green, and blue radiation are described.

Graded core/shell semiconductor nanorods and nanorod barcodes

DOEpatents

Alivisatos, A Paul [Oakland, CA; Scher, Erik C [San Francisco, CA; Manna, Liberato [Palo Del Collie, IT

2009-05-19

Disclosed herein is a graded core/shell semiconductor nanorod having at least a first segment of a core of a Group II-VI, Group III-V or a Group IV semiconductor, a graded shell overlying the core, wherein the graded shell comprises at least two monolayers, wherein the at least two monolayers each independently comprise a Group II-VI, Group III-V or a Group IV semiconductor.

Methods for neutralizing anthrax or anthrax spores

DOEpatents

Sloan, Mark A; Vivekandanda, Jeevalatha; Holwitt, Eric A; Kiel, Johnathan L

2013-02-26

The present invention concerns methods, compositions and apparatus for neutralizing bioagents, wherein bioagents comprise biowarfare agents, biohazardous agents, biological agents and/or infectious agents. The methods comprise exposing the bioagent to an organic semiconductor and exposing the bioagent and organic semiconductor to a source of energy. Although any source of energy is contemplated, in some embodiments the energy comprises visible light, ultraviolet, infrared, radiofrequency, microwave, laser radiation, pulsed corona discharge or electron beam radiation. Exemplary organic semiconductors include DAT and DALM. In certain embodiments, the organic semiconductor may be attached to one or more binding moieties, such as an antibody, antibody fragment, or nucleic acid ligand. Preferably, the binding moiety has a binding affinity for one or more bioagents to be neutralized. Other embodiments concern an apparatus comprising an organic semiconductor and an energy source. In preferred embodiments, the methods, compositions and apparatus are used for neutralizing anthrax spores.

Numerical investigation of metal-semiconductor-insulator-semiconductor passivated hole contacts based on atomic layer deposited AlO x

NASA Astrophysics Data System (ADS)

Ke, Cangming; Xin, Zheng; Ling, Zhi Peng; Aberle, Armin G.; Stangl, Rolf

2017-08-01

Excellent c-Si tunnel layer surface passivation has been obtained recently in our lab, using atomic layer deposited aluminium oxide (ALD AlO x ) in the tunnel layer regime of 0.9 to 1.5 nm, investigated to be applied for contact passivation. Using the correspondingly measured interface properties, this paper compares the theoretical collection efficiency of a conventional metal-semiconductor (MS) contact on diffused p+ Si to a metal-semiconductor-insulator-semiconductor (MSIS) contact on diffused p+ Si or on undoped n-type c-Si. The influences of (1) the tunnel layer passivation quality at the tunnel oxide interface (Q f and D it), (2) the tunnel layer thickness and the electron and hole tunnelling mass, (3) the tunnel oxide material, and (4) the semiconductor capping layer material properties are investigated numerically by evaluation of solar cell efficiency, open-circuit voltage, and fill factor.

Method for removing semiconductor layers from salt substrates

DOEpatents

Shuskus, Alexander J.; Cowher, Melvyn E.

1985-08-27

A method is described for removing a CVD semiconductor layer from an alkali halide salt substrate following the deposition of the semiconductor layer. The semiconductor-substrate combination is supported on a material such as tungsten which is readily wet by the molten alkali halide. The temperature of the semiconductor-substrate combination is raised to a temperature greater than the melting temperature of the substrate but less than the temperature of the semiconductor and the substrate is melted and removed from the semiconductor by capillary action of the wettable support.

Controlled growth of larger heterojunction interface area for organic photosensitive devices

DOEpatents

Yang, Fan [Somerset, NJ; Forrest, Stephen R [Ann Arbor, MI

2009-12-29

An optoelectronic device and a method of fabricating a photosensitive optoelectronic device includes depositing a first organic semiconductor material on a first electrode to form a continuous first layer having protrusions, a side of the first layer opposite the first electrode having a surface area at least three times greater than an underlying lateral cross-sectional area; depositing a second organic semiconductor material directly on the first layer to form a discontinuous second layer, portions of the first layer remaining exposed; depositing a third organic semiconductor material directly on the second layer to form a discontinuous third layer, portions of at least the second layer remaining exposed; depositing a fourth organic semiconductor material on the third layer to form a continuous fourth layer, filling any exposed gaps and recesses in the first, second, and third layers; and depositing a second electrode on the fourth layer, wherein at least one of the first electrode and the second electrode is transparent, and the first and third organic semiconductor materials are both of a donor-type or an acceptor-type relative to second and fourth organic semiconductor materials, which are of the other material type.

High efficiency, low cost, thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

2001-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

1999-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

Semiconductor films on flexible iridium substrates

DOEpatents

Goyal, Amit

2005-03-29

A laminate semiconductor article includes a flexible substrate, an optional biaxially textured oxide buffer system on the flexible substrate, a biaxially textured Ir-based buffer layer on the substrate or the buffer system, and an epitaxial layer of a semiconductor. Ir can serve as a substrate with an epitaxial layer of a semiconductor thereon.

Light emitting diode with porous SiC substrate and method for fabricating

DOEpatents

Li, Ting; Ibbetson, James; Keller, Bernd

2005-12-06

A method and apparatus for forming a porous layer on the surface of a semiconductor material wherein an electrolyte is provided and is placed in contact with one or more surfaces of a layer of semiconductor material. The electrolyte is heated and a bias is introduced across said electrolyte and the semiconductor material causing a current to flow between the electrolyte and the semiconductor material. The current forms a porous layer on the one or more surfaces of the semiconductor material in contact with the electrolyte. The semiconductor material with its porous layer can serve as a substrate for a light emitter. A semiconductor emission region can be formed on the substrate. The emission region is capable of emitting light omnidirectionally in response to a bias, with the porous layer enhancing extraction of the emitting region light passing through the substrate.

Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates

DOEpatents

Norman, Andrew G; Ptak, Aaron J

2013-08-13

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

Intermediate-band photosensitive device with quantum dots embedded in energy fence barrier

DOEpatents

Forrest, Stephen R.; Wei, Guodan

2010-07-06

A plurality of layers of a first semiconductor material and a plurality of dots-in-a-fence barriers disposed in a stack between a first electrode and a second electrode. Each dots-in-a-fence barrier consists essentially of a plurality of quantum dots of a second semiconductor material embedded between and in direct contact with two layers of a third semiconductor material. Wave functions of the quantum dots overlap as at least one intermediate band. The layers of the third semiconductor material are arranged as tunneling barriers to require a first electron and/or a first hole in a layer of the first material to perform quantum mechanical tunneling to reach the second material within a respective quantum dot, and to require a second electron and/or a second hole in a layer of the first semiconductor material to perform quantum mechanical tunneling to reach another layer of the first semiconductor material.

Photovoltaic solar cell

DOEpatents

Nielson, Gregory N; Cruz-Campa, Jose Luis; Okandan, Murat; Resnick, Paul J

2014-05-20

A photovoltaic solar cell for generating electricity from sunlight is disclosed. The photovoltaic solar cell comprises a plurality of spaced-apart point contact junctions formed in a semiconductor body to receive the sunlight and generate the electricity therefrom, the plurality of spaced-apart point contact junctions having a first plurality of regions having a first doping type and a second plurality of regions having a second doping type. In addition, the photovoltaic solar cell comprises a first electrical contact electrically connected to each of the first plurality of regions and a second electrical contact electrically connected to each of the second plurality of regions, as well as a passivation layer covering major surfaces and sidewalls of the photovoltaic solar cell.

Photovoltaic solar cell

DOEpatents

Nielson, Gregory N; Okandan, Murat; Cruz-Campa, Jose Luis; Resnick, Paul J

2013-11-26

A photovoltaic solar cell for generating electricity from sunlight is disclosed. The photovoltaic solar cell comprises a plurality of spaced-apart point contact junctions formed in a semiconductor body to receive the sunlight and generate the electicity therefrom, the plurality of spaced-apart point contact junctions having a first plurality of regions having a first doping type and a second plurality of regions having a second doping type. In addition, the photovoltaic solar cell comprises a first electrical contact electrically connected to each of the first plurality of regions and a second electrical contact electrically connected to each of the second plurality of regions, as well as a passivation layer covering major surfaces and sidewalls of the photovoltaic solar cell.

Monolithic in-based III-V compound semiconductor focal plane array cell with single stage CCD output

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Cunningham, Thomas J. (Inventor); Krabach, Timothy N. (Inventor); Staller, Craig O. (Inventor)

1994-01-01

A monolithic semiconductor imager includes an indium-based III-V compound semiconductor monolithic active layer of a first conductivity type, an array of plural focal plane cells on the active layer, each of the focal plane cells including a photogate over a top surface of the active layer, a readout circuit dedicated to the focal plane cell including plural transistors formed monolithically with the monolithic active layer and a single-stage charge coupled device formed monolithically with the active layer between the photogate and the readout circuit for transferring photo-generated charge accumulated beneath the photogate during an integration period to the readout circuit. The photogate includes thin epitaxial semiconductor layer of a second conductivity type overlying the active layer and an aperture electrode overlying a peripheral portion of the thin epitaxial semiconductor layer, the aperture electrode being connectable to a photogate bias voltage.

Lattice matched semiconductor growth on crystalline metallic substrates

DOEpatents

Norman, Andrew G; Ptak, Aaron J; McMahon, William E

2013-11-05

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, B.L.

1999-04-27

A semiconductor device is described having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer. 9 figs.

Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji-Won

The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component comprising at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes duringmore » consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.« less

Thin film photovoltaic device with multilayer substrate

DOEpatents

Catalano, Anthony W.; Bhushan, Manjul

1984-01-01

A thin film photovoltaic device which utilizes at least one compound semiconductor layer chosen from Groups IIB and VA of the Periodic Table is formed on a multilayer substrate The substrate includes a lowermost support layer on which all of the other layers of the device are formed. Additionally, an uppermost carbide or silicon layer is adjacent to the semiconductor layer. Below the carbide or silicon layer is a metal layer of high conductivity and expansion coefficient equal to or slightly greater than that of the semiconductor layer.

Tunnel barrier schottky

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chu, Rongming; Cao, Yu; Li, Zijian

2018-02-20

A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.

A multifunctional biphasic water splitting catalyst tailored for integration with high-performance semiconductor photoanodes

NASA Astrophysics Data System (ADS)

Yang, Jinhui; Cooper, Jason K.; Toma, Francesca M.; Walczak, Karl A.; Favaro, Marco; Beeman, Jeffrey W.; Hess, Lucas H.; Wang, Cheng; Zhu, Chenhui; Gul, Sheraz; Yano, Junko; Kisielowski, Christian; Schwartzberg, Adam; Sharp, Ian D.

2017-03-01

Artificial photosystems are advanced by the development of conformal catalytic materials that promote desired chemical transformations, while also maintaining stability and minimizing parasitic light absorption for integration on surfaces of semiconductor light absorbers. Here, we demonstrate that multifunctional, nanoscale catalysts that enable high-performance photoelectrochemical energy conversion can be engineered by plasma-enhanced atomic layer deposition. The collective properties of tailored Co3O4/Co(OH)2 thin films simultaneously provide high activity for water splitting, permit efficient interfacial charge transport from semiconductor substrates, and enhance durability of chemically sensitive interfaces. These films comprise compact and continuous nanocrystalline Co3O4 spinel that is impervious to phase transformation and impermeable to ions, thereby providing effective protection of the underlying substrate. Moreover, a secondary phase of structurally disordered and chemically labile Co(OH)2 is introduced to ensure a high concentration of catalytically active sites. Application of this coating to photovoltaic p+n-Si junctions yields best reported performance characteristics for crystalline Si photoanodes.

Voltage-matched, monolithic, multi-band-gap devices

DOEpatents

Wanlass, Mark W.; Mascarenhas, Angelo

2006-08-22

Monolithic, tandem, photonic cells include at least a first semiconductor layer and a second semiconductor layer, wherein each semiconductor layer includes an n-type region, a p-type region, and a given band-gap energy. Formed within each semiconductor layer is a sting of electrically connected photonic sub-cells. By carefully selecting the numbers of photonic sub-cells in the first and second layer photonic sub-cell string(s), and by carefully selecting the manner in which the sub-cells in a first and second layer photonic sub-cell string(s) are electrically connected, each of the first and second layer sub-cell strings may be made to achieve one or more substantially identical electrical characteristics.

Voltage-Matched, Monolithic, Multi-Band-Gap Devices

DOEpatents

Wanlass, M. W.; Mascarenhas, A.

2006-08-22

Monolithic, tandem, photonic cells include at least a first semiconductor layer and a second semiconductor layer, wherein each semiconductor layer includes an n-type region, a p-type region, and a given band-gap energy. Formed within each semiconductor layer is a string of electrically connected photonic sub-cells. By carefully selecting the numbers of photonic sub-cells in the first and second layer photonic sub-cell string(s), and by carefully selecting the manner in which the sub-cells in a first and second layer photonic sub-cell string(s) are electrically connected, each of the first and second layer sub-cell strings may be made to achieve one or more substantially identical electrical characteristics.

Optoelectronic semiconductor device and method of fabrication

DOEpatents

Cui, Yi; Zhu, Jia; Hsu, Ching-Mei; Fan, Shanhui; Yu, Zongfu

2014-11-25

An optoelectronic device comprising an optically active layer that includes a plurality of domes is presented. The plurality of domes is arrayed in two dimensions having a periodicity in each dimension that is less than or comparable with the shortest wavelength in a spectral range of interest. By virtue of the plurality of domes, the optoelectronic device achieves high performance. A solar cell having high energy-conversion efficiency, improved absorption over the spectral range of interest, and an improved acceptance angle is presented as an exemplary device.

A miniature electronic nose system based on an MWNT-polymer microsensor array and a low-power signal-processing chip.

PubMed

Chiu, Shih-Wen; Wu, Hsiang-Chiu; Chou, Ting-I; Chen, Hsin; Tang, Kea-Tiong

2014-06-01

This article introduces a power-efficient, miniature electronic nose (e-nose) system. The e-nose system primarily comprises two self-developed chips, a multiple-walled carbon nanotube (MWNT)-polymer based microsensor array, and a low-power signal-processing chip. The microsensor array was fabricated on a silicon wafer by using standard photolithography technology. The microsensor array comprised eight interdigitated electrodes surrounded by SU-8 "walls," which restrained the material-solvent liquid in a defined area of 650 × 760 μm(2). To achieve a reliable sensor-manufacturing process, we used a two-layer deposition method, coating the MWNTs and polymer film as the first and second layers, respectively. The low-power signal-processing chip included array data acquisition circuits and a signal-processing core. The MWNT-polymer microsensor array can directly connect with array data acquisition circuits, which comprise sensor interface circuitry and an analog-to-digital converter; the signal-processing core consists of memory and a microprocessor. The core executes the program, classifying the odor data received from the array data acquisition circuits. The low-power signal-processing chip was designed and fabricated using the Taiwan Semiconductor Manufacturing Company 0.18-μm 1P6M standard complementary metal oxide semiconductor process. The chip consumes only 1.05 mW of power at supply voltages of 1 and 1.8 V for the array data acquisition circuits and the signal-processing core, respectively. The miniature e-nose system, which used a microsensor array, a low-power signal-processing chip, and an embedded k-nearest-neighbor-based pattern recognition algorithm, was developed as a prototype that successfully recognized the complex odors of tincture, sorghum wine, sake, whisky, and vodka.

Large-area, laterally-grown epitaxial semiconductor layers

DOEpatents

Han, Jung; Song, Jie; Chen, Danti

2017-07-18

Structures and methods for confined lateral-guided growth of a large-area semiconductor layer on an insulating layer are described. The semiconductor layer may be formed by heteroepitaxial growth from a selective growth area in a vertically-confined, lateral-growth guiding structure. Lateral-growth guiding structures may be formed in arrays over a region of a substrate, so as to cover a majority of the substrate region with laterally-grown epitaxial semiconductor tiles. Quality regions of low-defect, stress-free GaN may be grown on silicon.

340 Ghz Multipixel Transceiver

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam (Inventor); Cooper, Ken B. (Inventor); Decrossas, Emmanuel (Inventor); Gill, John J. (Inventor); Jung-Kubiak, Cecile (Inventor); Lee, Choonsup (Inventor); Lin, Robert (Inventor); Mehdi, Imran (Inventor); Peralta, Alejandro (Inventor); Reck, Theodore (Inventor)

2017-01-01

A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.

Photovoltaic Device Including A Boron Doping Profile In An I-Type Layer

DOEpatents

Yang, Liyou

1993-10-26

A photovoltaic cell for use in a single junction or multijunction photovoltaic device, which includes a p-type layer of a semiconductor compound including silicon, an i-type layer of an amorphous semiconductor compound including silicon, and an n-type layer of a semiconductor compound including silicon formed on the i-type layer. The i-type layer including an undoped first sublayer formed on the p-type layer, and a boron-doped second sublayer formed on the first sublayer.

Back contact buffer layer for thin-film solar cells

DOEpatents

Compaan, Alvin D.; Plotnikov, Victor V.

2014-09-09

A photovoltaic cell structure is disclosed that includes a buffer/passivation layer at a CdTe/Back contact interface. The buffer/passivation layer is formed from the same material that forms the n-type semiconductor active layer. In one embodiment, the buffer layer and the n-type semiconductor active layer are formed from cadmium sulfide (CdS). A method of forming a photovoltaic cell includes the step of forming the semiconductor active layers and the buffer/passivation layer within the same deposition chamber and using the same material source.

Methods of producing free-standing semiconductors using sacrificial buffer layers and recyclable substrates

DOEpatents

Ptak, Aaron Joseph; Lin, Yong; Norman, Andrew; Alberi, Kirstin

2015-05-26

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices. The low-defect density semiconductor materials produced using this method result in the enhanced performance of the semiconductor devices that incorporate the semiconductor materials.

Plasmon absorption modulator systems and methods

DOEpatents

Kekatpure, Rohan Deodatta; Davids, Paul

2014-07-15

Plasmon absorption modulator systems and methods are disclosed. A plasmon absorption modulator system includes a semiconductor substrate, a plurality of quantum well layers stacked on a top surface of the semiconductor substrate, and a metal layer formed on a top surface of the stack of quantum well layers. A method for modulating plasmonic current includes enabling propagation of the plasmonic current along a metal layer, and applying a voltage across the stack of quantum well layers to cause absorption of a portion of energy of the plasmonic current by the stack of quantum well layers. A metamaterial switching system includes a semiconductor substrate, a plurality of quantum well layers stacked on a top surface of the semiconductor substrate, and at least one metamaterial structure formed on a top surface of the stack of quantum well layers.

Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

DOEpatents

Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji Won; Rondinone, Adam J.; Love, Lonnie J.; Duty, Chad Edward; Madden, Andrew Stephen; Li, Yiliang; Ivanov, Ilia N.; Rawn, Claudia Jeanette

2014-06-24

The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component containing at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes during consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.

Quantifying resistances across nanoscale low- and high-angle interspherulite boundaries in solution-processed organic semiconductor thin films.

PubMed

Lee, Stephanie S; Mativetsky, Jeffrey M; Loth, Marsha A; Anthony, John E; Loo, Yueh-Lin

2012-11-27

The nanoscale boundaries formed when neighboring spherulites impinge in polycrystalline, solution-processed organic semiconductor thin films act as bottlenecks to charge transport, significantly reducing organic thin-film transistor mobility in devices comprising spherulitic thin films as the active layers. These interspherulite boundaries (ISBs) are structurally complex, with varying angles of molecular orientation mismatch along their lengths. We have successfully engineered exclusively low- and exclusively high-angle ISBs to elucidate how the angle of molecular orientation mismatch at ISBs affects their resistivities in triethylsilylethynyl anthradithiophene thin films. Conductive AFM and four-probe measurements reveal that current flow is unaffected by the presence of low-angle ISBs, whereas current flow is significantly disrupted across high-angle ISBs. In the latter case, we estimate the resistivity to be 22 MΩμm(2)/width of the ISB, only less than a quarter of the resistivity measured across low-angle grain boundaries in thermally evaporated sexithiophene thin films. This discrepancy in resistivities across ISBs in solution-processed organic semiconductor thin films and grain boundaries in thermally evaporated organic semiconductor thin films likely arises from inherent differences in the nature of film formation in the respective systems.

Interconnected semiconductor devices

DOEpatents

Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

1990-10-23

Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

Thermally robust semiconductor optical amplifiers and laser diodes

DOEpatents

Dijaili, Sol P.; Patterson, Frank G.; Walker, Jeffrey D.; Deri, Robert J.; Petersen, Holly; Goward, William

2002-01-01

A highly heat conductive layer is combined with or placed in the vicinity of the optical waveguide region of active semiconductor components. The thermally conductive layer enhances the conduction of heat away from the active region, which is where the heat is generated in active semiconductor components. This layer is placed so close to the optical region that it must also function as a waveguide and causes the active region to be nearly the same temperature as the ambient or heat sink. However, the semiconductor material itself should be as temperature insensitive as possible and therefore the invention combines a highly thermally conductive dielectric layer with improved semiconductor materials to achieve an overall package that offers improved thermal performance. The highly thermally conductive layer serves two basic functions. First, it provides a lower index material than the semiconductor device so that certain kinds of optical waveguides may be formed, e.g., a ridge waveguide. The second and most important function, as it relates to this invention, is that it provides a significantly higher thermal conductivity than the semiconductor material, which is the principal material in the fabrication of various optoelectronic devices.

Unitary lens semiconductor device

DOEpatents

Lear, Kevin L.

1997-01-01

A unitary lens semiconductor device and method. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors.

Method for depositing high-quality microcrystalline semiconductor materials

DOEpatents

Guha, Subhendu [Bloomfield Hills, MI; Yang, Chi C [Troy, MI; Yan, Baojie [Rochester Hills, MI

2011-03-08

A process for the plasma deposition of a layer of a microcrystalline semiconductor material is carried out by energizing a process gas which includes a precursor of the semiconductor material and a diluent with electromagnetic energy so as to create a plasma therefrom. The plasma deposits a layer of the microcrystalline semiconductor material onto the substrate. The concentration of the diluent in the process gas is varied as a function of the thickness of the layer of microcrystalline semiconductor material which has been deposited. Also disclosed is the use of the process for the preparation of an N-I-P type photovoltaic device.

Unitary lens semiconductor device

DOEpatents

Lear, K.L.

1997-05-27

A unitary lens semiconductor device and method are disclosed. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors. 9 figs.

Methods for forming particles

DOEpatents

Fox, Robert V.; Zhang, Fengyan; Rodriguez, Rene G.; Pak, Joshua J.; Sun, Chivin

2016-06-21

Single source precursors or pre-copolymers of single source precursors are subjected to microwave radiation to form particles of a I-III-VI.sub.2 material. Such particles may be formed in a wurtzite phase and may be converted to a chalcopyrite phase by, for example, exposure to heat. The particles in the wurtzite phase may have a substantially hexagonal shape that enables stacking into ordered layers. The particles in the wurtzite phase may be mixed with particles in the chalcopyrite phase (i.e., chalcopyrite nanoparticles) that may fill voids within the ordered layers of the particles in the wurtzite phase thus produce films with good coverage. In some embodiments, the methods are used to form layers of semiconductor materials comprising a I-III-VI.sub.2 material. Devices such as, for example, thin-film solar cells may be fabricated using such methods.

Low temperature production of large-grain polycrystalline semiconductors

DOEpatents

Naseem, Hameed A [Fayetteville, AR; Albarghouti, Marwan [Loudonville, NY

2007-04-10

An oxide or nitride layer is provided on an amorphous semiconductor layer prior to performing metal-induced crystallization of the semiconductor layer. The oxide or nitride layer facilitates conversion of the amorphous material into large grain polycrystalline material. Hence, a native silicon dioxide layer provided on hydrogenated amorphous silicon (a-Si:H), followed by deposited Al permits induced crystallization at temperatures far below the solid phase crystallization temperature of a-Si. Solar cells and thin film transistors can be prepared using this method.

Method for growing low defect, high purity crystalline layers utilizing lateral overgrowth of a patterned mask

NASA Technical Reports Server (NTRS)

Morrison, Andrew D. (Inventor); Daud, Taher (Inventor)

1986-01-01

A method for growing a high purity, low defect layer of semiconductor is described. This method involves depositing a patterned mask of a material impervious to impurities of the semiconductor on a surface of a blank. When a layer of semiconductor is grown on the mask, the semiconductor will first grow from the surface portions exposed by the openings in the mask and will bridge the connecting portions of the mask to form a continuous layer having improved purity, since only the portions overlying the openings are exposed to defects and impurities. The process can be iterated and the mask translated to further improve the quality of grown layers.

Laser pumping of thyristors for fast high current rise-times

DOEpatents

Glidden, Steven C.; Sanders, Howard D.

2013-06-11

An optically triggered semiconductor switch includes an anode metallization layer; a cathode metallization layer; a semiconductor between the anode metallization layer and the cathode metallization layer and a photon source. The semiconductor includes at least four layers of alternating doping in the form P-N-P-N, in which an outer layer adjacent to the anode metallization layer forms an anode and an outer layer adjacent the cathode metallization layer forms a cathode and in which the anode metallization layer has a window pattern of optically transparent material exposing the anode layer to light. The photon source emits light having a wavelength, with the light from the photon source being configured to match the window pattern of the anode metallization layer.

Whiskerless Schottky diode

NASA Technical Reports Server (NTRS)

Bishop, William L. (Inventor); Mcleod, Kathleen A. (Inventor); Mattauch, Robert J. (Inventor)

1991-01-01

A Schottky diode for millimeter and submillimeter wave applications is comprised of a multi-layered structure including active layers of gallium arsenide on a semi-insulating gallium arsenide substrate with first and second insulating layers of silicon dioxide on the active layers of gallium arsenide. An ohmic contact pad lays on the silicon dioxide layers. An anode is formed in a window which is in and through the silicon dioxide layers. An elongated contact finger extends from the pad to the anode and a trench, preferably a transverse channel or trench of predetermined width, is formed in the active layers of the diode structure under the contact finger. The channel extends through the active layers to or substantially to the interface of the semi-insulating gallium arsenide substrate and the adjacent gallium arsenide layer which constitutes a buffer layer. Such a structure minimizes the effect of the major source of shunt capacitance by interrupting the current path between the conductive layers beneath the anode contact pad and the ohmic contact. Other embodiments of the diode may substitute various insulating or semi-insulating materials for the silicon dioxide, various semi-conductors for the active layers of gallium arsenide, and other materials for the substrate, which may be insulating or semi-insulating.

Optical devices featuring textured semiconductor layers

DOEpatents

Moustakas, Theodore D [Dover, MA; Cabalu, Jasper S [Cary, NC

2011-10-11

A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor.

Optical devices featuring textured semiconductor layers

DOEpatents

Moustakas, Theodore D [Dover, MA; Cabalu, Jasper S [Cary, NC

2012-08-07

A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor.

Back-side readout semiconductor photomultiplier

DOEpatents

Choong, Woon-Seng; Holland, Stephen E

2014-05-20

This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region.

Sintered silver joints via controlled topography of electronic packaging subcomponents

DOEpatents

Wereszczak, Andrew A.

2014-09-02

Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.

Method for fabricating an interconnected array of semiconductor devices

DOEpatents

Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

1989-10-10

Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

Semiconductor crystal high resolution imager

NASA Technical Reports Server (NTRS)

Matteson, James (Inventor); Levin, Craig S. (Inventor)

2011-01-01

A radiation imaging device (10). The radiation image device (10) comprises a subject radiation station (12) producing photon emissions (14), and at least one semiconductor crystal detector (16) arranged in an edge-on orientation with respect to the emitted photons (14) to directly receive the emitted photons (14) and produce a signal. The semiconductor crystal detector (16) comprises at least one anode and at least one cathode that produces the signal in response to the emitted photons (14).

High-resolution parallel-detection sensor array using piezo-phototronics effect

DOEpatents

Wang, Zhong L.; Pan, Caofeng

2015-07-28

A pressure sensor element includes a substrate, a first type of semiconductor material layer and an array of elongated light-emitting piezoelectric nanostructures extending upwardly from the first type of semiconductor material layer. A p-n junction is formed between each nanostructure and the first type semiconductor layer. An insulative resilient medium layer is infused around each of the elongated light-emitting piezoelectric nanostructures. A transparent planar electrode, disposed on the resilient medium layer, is electrically coupled to the top of each nanostructure. A voltage source is coupled to the first type of semiconductor material layer and the transparent planar electrode and applies a biasing voltage across each of the nanostructures. Each nanostructure emits light in an intensity that is proportional to an amount of compressive strain applied thereto.

Solid state radiative heat pump

DOEpatents

Berdahl, P.H.

1984-09-28

A solid state radiative heat pump operable at room temperature (300 K) utilizes a semiconductor having a gap energy in the range of 0.03-0.25 eV and operated reversibly to produce an excess or deficit of change carriers as compared equilibrium. In one form of the invention an infrared semiconductor photodiode is used, with forward or reverse bias, to emit an excess or deficit of infrared radiation. In another form of the invention, a homogenous semiconductor is subjected to orthogonal magnetic and electric fields to emit an excess or deficit of infrared radiation. Three methods of enhancing transmission of radiation the active surface of the semiconductor are disclosed. In one method, an anti-refection layer is coated into the active surface of the semiconductor, the anti-reflection layer having an index of refraction equal to the square root of that of the semiconductor. In the second method, a passive layer is speaced trom the active surface of the semiconductor by a submicron vacuum gap, the passive layer having an index of refractive equal to that of the semiconductor. In the third method, a coupler with a paraboloid reflecting surface surface is in contact with the active surface of the semiconductor, the coupler having an index of refraction about the same as that of the semiconductor.

Organic conductive films for semiconductor electrodes

DOEpatents

Frank, Arthur J.

1984-01-01

According to the present invention, improved electrodes overcoated with conductive polymer films and preselected catalysts are provided. The electrodes typically comprise an inorganic semiconductor overcoated with a charge conductive polymer film comprising a charge conductive polymer in or on which is a catalyst or charge-relaying agent.

Solar Power Wires Based on Organic Photovoltaic Materials

NASA Astrophysics Data System (ADS)

Lee, Michael R.; Eckert, Robert D.; Forberich, Karen; Dennler, Gilles; Brabec, Christoph J.; Gaudiana, Russell A.

2009-04-01

Organic photovoltaics in a flexible wire format has potential advantages that are described in this paper. A wire format requires long-distance transport of current that can be achieved only with conventional metals, thus eliminating the use of transparent oxide semiconductors. A phase-separated, photovoltaic layer, comprising a conducting polymer and a fullerene derivative, is coated onto a thin metal wire. A second wire, coated with a silver film, serving as the counter electrode, is wrapped around the first wire. Both wires are encased in a transparent polymer cladding. Incident light is focused by the cladding onto to the photovoltaic layer even when it is completely shadowed by the counter electrode. Efficiency values of the wires range from 2.79% to 3.27%.

Microfabricated bragg waveguide

DOEpatents

Fleming, James G.; Lin, Shawn-Yu; Hadley, G. Ronald

2004-10-19

A microfabricated Bragg waveguide of semiconductor-compatible material having a hollow core and a multilayer dielectric cladding can be fabricated by integrated circuit technologies. The microfabricated Bragg waveguide can comprise a hollow channel waveguide or a hollow fiber. The Bragg fiber can be fabricated by coating a sacrificial mandrel or mold with alternating layers of high- and low-refractive-index dielectric materials and then removing the mandrel or mold to leave a hollow tube with a multilayer dielectric cladding. The Bragg channel waveguide can be fabricated by forming a trench embedded in a substrate and coating the inner wall of the trench with a multilayer dielectric cladding. The thicknesses of the alternating layers can be selected to satisfy the condition for minimum radiation loss of the guided wave.

Precise, Self-Limited Epitaxy of Ultrathin Organic Semiconductors and Heterojunctions Tailored by van der Waals Interactions.

PubMed

Wu, Bing; Zhao, Yinghe; Nan, Haiyan; Yang, Ziyi; Zhang, Yuhan; Zhao, Huijuan; He, Daowei; Jiang, Zonglin; Liu, Xiaolong; Li, Yun; Shi, Yi; Ni, Zhenhua; Wang, Jinlan; Xu, Jian-Bin; Wang, Xinran

2016-06-08

Precise assembly of semiconductor heterojunctions is the key to realize many optoelectronic devices. By exploiting the strong and tunable van der Waals (vdW) forces between graphene and organic small molecules, we demonstrate layer-by-layer epitaxy of ultrathin organic semiconductors and heterostructures with unprecedented precision with well-defined number of layers and self-limited characteristics. We further demonstrate organic p-n heterojunctions with molecularly flat interface, which exhibit excellent rectifying behavior and photovoltaic responses. The self-limited organic molecular beam epitaxy (SLOMBE) is generically applicable for many layered small-molecule semiconductors and may lead to advanced organic optoelectronic devices beyond bulk heterojunctions.

Organic conductive films for semiconductor electrodes

DOEpatents

Frank, A.J.

1984-01-01

According to the present invention, improved electrodes overcoated with conductive polymer films and preselected catalysts are provided. The electrodes typically comprise an inorganic semiconductor over-coated with a charge conductive polymer film comprising a charge conductive polymer in or on which is a catalyst or charge-relaying agent.

Porous silicon carbide (SiC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

A multifunctional biphasic water splitting catalyst tailored for integration with high-performance semiconductor photoanodes

DOE PAGES

Yang, Jinhui; Cooper, Jason K.; Toma, Francesca M.; ...

2016-11-07

Artificial photosystems are advanced by the development of conformal catalytic materials that promote desired chemical transformations, while also maintaining stability and minimizing parasitic light absorption for integration on surfaces of semiconductor light absorbers. We demonstrate that multifunctional, nanoscale catalysts that enable high-performance photoelectrochemical energy conversion can be engineered by plasma-enhanced atomic layer deposition. The collective properties of tailored Co 3 O 4 /Co(OH) 2 thin films simultaneously provide high activity for water splitting, permit efficient interfacial charge transport from semiconductor substrates, and enhance durability of chemically sensitive interfaces. Furthermore, these films comprise compact and continuous nanocrystalline Co 3 O 4more » spinel that is impervious to phase transformation and impermeable to ions, thereby providing effective protection of the underlying substrate. Moreover, a secondary phase of structurally disordered and chemically labile Co(OH) 2 is introduced to ensure a high concentration of catalytically active sites. Application of this coating to photovoltaic p + n-Si junctions yields best reported performance characteristics for crystalline Si photoanodes.« less

Thermal emitter comprising near-zero permittivity materials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Luk, Ting S.; Campione, Salvatore; Sinclair, Michael B.

A novel thermal source comprising a semiconductor hyperbolic metamaterial provides control of the emission spectrum and the angular emission pattern. These properties arise because of epsilon-near-zero conditions in the semiconductor hyperbolic metamaterial. In particular, the thermal emission is dominated by the epsilon-near-zero effect in the doped quantum wells composing the semiconductor hyperbolic metamaterial. Furthermore, different properties are observed for s and p polarizations, following the characteristics of the strong anisotropy of hyperbolic metamaterials.

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Dry texturing of solar cells

DOEpatents

Sopori, B.L.

1994-10-25

A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer. The result is a textured backside on an optically reflective, low resistivity alloy interface between the semiconductor substrate and the metal electrical contact layer. 9 figs.

Dry texturing of solar cells

DOEpatents

Sopori, Bhushan L.

1994-01-01

A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer. The result is a textured backside an optically reflective, low resistivity alloy interface between the semiconductor substrate and the metal electrical contact layer.

Die singulation method

DOEpatents

Swiler, Thomas P.; Garcia, Ernest J.; Francis, Kathryn M.

2013-06-11

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Die singulation method

DOEpatents

Swiler, Thomas P [Albuquerque, NM; Garcia, Ernest J [Albuquerque, NM; Francis, Kathryn M [Rio Rancho, NM

2014-01-07

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with a HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Method for depositing layers of high quality semiconductor material

DOEpatents

Guha, Subhendu; Yang, Chi C.

2001-08-14

Plasma deposition of substantially amorphous semiconductor materials is carried out under a set of deposition parameters which are selected so that the process operates near the amorphous/microcrystalline threshold. This threshold varies as a function of the thickness of the depositing semiconductor layer; and, deposition parameters, such as diluent gas concentrations, must be adjusted as a function of layer thickness. Also, this threshold varies as a function of the composition of the depositing layer, and in those instances where the layer composition is profiled throughout its thickness, deposition parameters must be adjusted accordingly so as to maintain the amorphous/microcrystalline threshold.

Charge Transport in Low-Temperature Processed Thin-Film Transistors Based on Indium Oxide/Zinc Oxide Heterostructures.

PubMed

Krausmann, Jan; Sanctis, Shawn; Engstler, Jörg; Luysberg, Martina; Bruns, Michael; Schneider, Jörg J

2018-06-20

The influence of the composition within multilayered heterostructure oxide semiconductors has a critical impact on the performance of thin-film transistor (TFT) devices. The heterostructures, comprising alternating polycrystalline indium oxide and zinc oxide layers, are fabricated by a facile atomic layer deposition (ALD) process, enabling the tuning of its electrical properties by precisely controlling the thickness of the individual layers. This subsequently results in enhanced TFT performance for the optimized stacked architecture after mild thermal annealing at temperatures as low as 200 °C. Superior transistor characteristics, resulting in an average field-effect mobility (μ sat. ) of 9.3 cm 2 V -1 s -1 ( W/ L = 500), an on/off ratio ( I on / I off ) of 5.3 × 10 9 , and a subthreshold swing of 162 mV dec -1 , combined with excellent long-term and bias stress stability are thus demonstrated. Moreover, the inherent semiconducting mechanism in such multilayered heterostructures can be conveniently tuned by controlling the thickness of the individual layers. Herein, devices comprising a higher In 2 O 3 /ZnO ratio, based on individual layer thicknesses, are predominantly governed by percolation conduction with temperature-independent charge carrier mobility. Careful adjustment of the individual oxide layer thicknesses in devices composed of stacked layers plays a vital role in the reduction of trap states, both interfacial and bulk, which consequently deteriorates the overall device performance. The findings enable an improved understanding of the correlation between TFT performance and the respective thin-film composition in ALD-based heterostructure oxides.

Lattice-mismatched GaInP LED devices and methods of fabricating same

DOEpatents

Mascarenhas, Angelo; Steiner, Myles A; Bhusal, Lekhnath; Zhang, Yong

2014-10-21

A method (100) of fabricating an LED or the active regions of an LED and an LED (200). The method includes growing, depositing or otherwise providing a bottom cladding layer (208) of a selected semiconductor alloy with an adjusted bandgap provided by intentionally disordering the structure of the cladding layer (208). A first active layer (202) may be grown above the bottom cladding layer (208) wherein the first active layer (202) is fabricated of the same semiconductor alloy, with however, a partially ordered structure. The first active layer (202) will also be fabricated to include a selected n or p type doping. The method further includes growing a second active layer (204) above the first active layer (202) where the second active layer (204) Is fabricated from the same semiconductor alloy.

Flexible single-layer ionic organic-inorganic frameworks towards precise nano-size separation

NASA Astrophysics Data System (ADS)

Yue, Liang; Wang, Shan; Zhou, Ding; Zhang, Hao; Li, Bao; Wu, Lixin

2016-02-01

Consecutive two-dimensional frameworks comprised of molecular or cluster building blocks in large area represent ideal candidates for membranes sieving molecules and nano-objects, but challenges still remain in methodology and practical preparation. Here we exploit a new strategy to build soft single-layer ionic organic-inorganic frameworks via electrostatic interaction without preferential binding direction in water. Upon consideration of steric effect and additional interaction, polyanionic clusters as connection nodes and cationic pseudorotaxanes acting as bridging monomers connect with each other to form a single-layer ionic self-assembled framework with 1.4 nm layer thickness. Such soft supramolecular polymer frameworks possess uniform and adjustable ortho-tetragonal nanoporous structure in pore size of 3.4-4.1 nm and exhibit greatly convenient solution processability. The stable membranes maintaining uniform porous structure demonstrate precisely size-selective separation of semiconductor quantum dots within 0.1 nm of accuracy and may hold promise for practical applications in selective transport, molecular separation and dialysis systems.

Monolayer-Mediated Growth of Organic Semiconductor Films with Improved Device Performance.

PubMed

Huang, Lizhen; Hu, Xiaorong; Chi, Lifeng

2015-09-15

Increased interest in wearable and smart electronics is driving numerous research works on organic electronics. The control of film growth and patterning is of great importance when targeting high-performance organic semiconductor devices. In this Feature Article, we summarize our recent work focusing on the growth, crystallization, and device operation of organic semiconductors intermediated by ultrathin organic films (in most cases, only a monolayer). The site-selective growth, modified crystallization and morphology, and improved device performance of organic semiconductor films are demonstrated with the help of the inducing layers, including patterned and uniform Langmuir-Blodgett monolayers, crystalline ultrathin organic films, and self-assembled polymer brush films. The introduction of the inducing layers could dramatically change the diffusion of the organic semiconductors on the surface and the interactions between the active layer with the inducing layer, leading to improved aggregation/crystallization behavior and device performance.

Nanocrystal structures

DOEpatents

Eisler, Hans J [Stoneham, MA; Sundar, Vikram C [Stoneham, MA; Walsh, Michael E [Everett, MA; Klimov, Victor I [Los Alamos, NM; Bawendi, Moungi G [Cambridge, MA; Smith, Henry I [Sudbury, MA

2008-12-30

A structure including a grating and a semiconductor nanocrystal layer on the grating, can be a laser. The semiconductor nanocrystal layer can include a plurality of semiconductor nanocrystals including a Group II-VI compound, the nanocrystals being distributed in a metal oxide matrix. The grating can have a periodicity from 200 nm to 500 nm.

Nanocrystal structures

DOEpatents

Eisler, Hans J.; Sundar, Vikram C.; Walsh, Michael E.; Klimov, Victor I.; Bawendi, Moungi G.; Smith, Henry I.

2006-12-19

A structure including a grating and a semiconductor nanocrystal layer on the grating, can be a laser. The semiconductor nanocrystal layer can include a plurality of semiconductor nanocrystals including a Group II–VI compound, the nanocrystals being distributed in a metal oxide matrix. The grating can have a periodicity from 200 nm to 500 nm.

Solid state radiative heat pump

DOEpatents

Berdahl, Paul H.

1986-01-01

A solid state radiative heat pump (10, 50, 70) operable at room temperature (300.degree. K.) utilizes a semiconductor having a gap energy in the range of 0.03-0.25 eV and operated reversibly to produce an excess or deficit of charge carriers as compared to thermal equilibrium. In one form of the invention (10, 70) an infrared semiconductor photodiode (21, 71) is used, with forward or reverse bias, to emit an excess or deficit of infrared radiation. In another form of the invention (50), a homogeneous semiconductor (51) is subjected to orthogonal magnetic and electric fields to emit an excess or deficit of infrared radiation. Three methods of enhancing transmission of radiation through the active surface of the semiconductor are disclosed. In one method, an anti-reflection layer (19) is coated into the active surface (13) of the semiconductor (11), the anti-reflection layer (19) having an index of refraction equal to the square root of that of the semiconductor (11). In the second method, a passive layer (75) is spaced from the active surface (73) of the semiconductor (71) by a submicron vacuum gap, the passive layer having an index of refractive equal to that of the semiconductor. In the third method, a coupler (91) with a paraboloid reflecting surface (92) is in contact with the active surface (13, 53) of the semiconductor (11, 51), the coupler having an index of refraction about the same as that of the semiconductor.

Optical devices featuring nonpolar textured semiconductor layers

DOEpatents

Moustakas, Theodore D; Moldawer, Adam; Bhattacharyya, Anirban; Abell, Joshua

2013-11-26

A semiconductor emitter, or precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of nonpolar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the invention can be 70-80% or higher. The invention provides highly efficient light emitting diodes suitable for solid state lighting.

SCB initiator

DOEpatents

Bickes Jr., Robert W.; Renlund, Anita M.; Stanton, Philip L.

1994-11-01

A detonator for high explosives initiated by mechanical impact includes a cylindrical barrel, a layer of flyer material mechanically covering the barrel at one end, and a semiconductor bridge ignitor including a pair of electrically conductive pads connected by a semiconductor bridge. The bridge is in operational contact with the layer, whereby ignition of said bridge forces a portion of the layer through the barrel to detonate the explosive. Input means are provided for igniting the semiconductor bridge ignitor.

SCB initiator

DOEpatents

Bickes, Jr., Robert W.; Renlund, Anita M.; Stanton, Philip L.

1994-01-01

A detonator for high explosives initiated by mechanical impact includes a cylindrical barrel, a layer of flyer material mechanically covering the barrel at one end, and a semiconductor bridge ignitor including a pair of electrically conductive pads connected by a semiconductor bridge. The bridge is in operational contact with the layer, whereby ignition of said bridge forces a portion of the layer through the barrel to detonate the explosive. Input means are provided for igniting the semiconductor bridge ignitor.

Electron gas grid semiconductor radiation detectors

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

An electron gas grid semiconductor radiation detector (EGGSRAD) useful for gamma-ray and x-ray spectrometers and imaging systems is described. The radiation detector employs doping of the semiconductor and variation of the semiconductor detector material to form a two-dimensional electron gas, and to allow transistor action within the detector. This radiation detector provides superior energy resolution and radiation detection sensitivity over the conventional semiconductor radiation detector and the "electron-only" semiconductor radiation detectors which utilize a grid electrode near the anode. In a first embodiment, the EGGSRAD incorporates delta-doped layers adjacent the anode which produce an internal free electron grid well to which an external grid electrode can be attached. In a second embodiment, a quantum well is formed between two of the delta-doped layers, and the quantum well forms the internal free electron gas grid to which an external grid electrode can be attached. Two other embodiments which are similar to the first and second embodiment involve a graded bandgap formed by changing the composition of the semiconductor material near the first and last of the delta-doped layers to increase or decrease the conduction band energy adjacent to the delta-doped layers.

Method of transferring strained semiconductor structure

DOEpatents

Nastasi, Michael A [Santa Fe, NM; Shao, Lin [College Station, TX

2009-12-29

The transfer of strained semiconductor layers from one substrate to another substrate involves depositing a multilayer structure on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the deposited multilayer structure is bonded to a second substrate and is separated away at the interface, which results in transferring a multilayer structure from one substrate to the other substrate. The multilayer structure includes at least one strained semiconductor layer and at least one strain-induced seed layer. The strain-induced seed layer can be optionally etched away after the layer transfer.

Semiconductor wire array structures, and solar cells and photodetectors based on such structures

DOEpatents

Kelzenberg, Michael D.; Atwater, Harry A.; Briggs, Ryan M.; Boettcher, Shannon W.; Lewis, Nathan S.; Petykiewicz, Jan A.

2014-08-19

A structure comprising an array of semiconductor structures, an infill material between the semiconductor materials, and one or more light-trapping elements is described. Photoconverters and photoelectrochemical devices based on such structure also described.

InP solar cell with window layer

NASA Technical Reports Server (NTRS)

Jain, Raj K. (Inventor); Landis, Geoffrey A. (Inventor)

1994-01-01

The invention features a thin light transmissive layer of the ternary semiconductor indium aluminum arsenide (InAlAs) as a front surface passivation or 'window' layer for p-on-n InP solar cells. The window layers of the invention effectively reduce front surface recombination of the object semiconductors thereby increasing the efficiency of the cells.

Solar cells using quantum funnels.

PubMed

Kramer, Illan J; Levina, Larissa; Debnath, Ratan; Zhitomirsky, David; Sargent, Edward H

2011-09-14

Colloidal quantum dots offer broad tuning of semiconductor bandstructure via the quantum size effect. Devices involving a sequence of layers comprised of quantum dots selected to have different diameters, and therefore bandgaps, offer the possibility of funneling energy toward an acceptor. Here we report a quantum funnel that efficiently conveys photoelectrons from their point of generation toward an intended electron acceptor. Using this concept we build a solar cell that benefits from enhanced fill factor as a result of this quantum funnel. This concept addresses limitations on transport in soft condensed matter systems and leverages their advantages in large-area optoelectronic devices and systems.

High band gap 2-6 and 3-5 tunneling junctions for silicon multijunction solar cells

NASA Technical Reports Server (NTRS)

Daud, Taher (Inventor); Kachare, Akaram H. (Inventor)

1986-01-01

A multijunction silicon solar cell of high efficiency is provided by providing a tunnel junction between the solar cell junctions to connect them in series. The tunnel junction is comprised of p+ and n+ layers of high band gap 3-5 or 2-6 semiconductor materials that match the lattice structure of silicon, such as GaP (band gap 2.24 eV) or ZnS (band gap 3.6 eV). Each of which has a perfect lattice match with silicon to avoid defects normally associated with lattice mismatch.

Systems and methods for solar cells with CIS and CIGS films made by reacting evaporated copper chlorides with selenium

DOEpatents

Albin, David S.; Noufi, Rommel

2015-06-09

Systems and methods for solar cells with CIS and CIGS films made by reacting evaporated copper chlorides with selenium are provided. In one embodiment, a method for fabricating a thin film device comprises: providing a semiconductor film comprising indium (In) and selenium (Se) upon a substrate; heating the substrate and the semiconductor film to a desired temperature; and performing a mass transport through vapor transport of a copper chloride vapor and se vapor to the semiconductor film within a reaction chamber.

Fabrication of optically reflecting ohmic contacts for semiconductor devices

DOEpatents

Sopori, Bhushan L.

1995-01-01

A method is provided to produce a low-resistivity ohmic contact having high optical reflectivity on one side of a semiconductor device. The contact is formed by coating the semiconductor substrate with a thin metal film on the back reflecting side and then optically processing the wafer by illuminating it with electromagnetic radiation of a predetermined wavelength and energy level through the front side of the wafer for a predetermined period of time. This method produces a thin epitaxial alloy layer between the semiconductor substrate and the metal layer when a crystalline substrate is used. The alloy layer provides both a low-resistivity ohmic contact and high optical reflectance.

Harvesting solar energy by means of charge-separating nanocrystals and their solids.

PubMed

Diederich, Geoffrey; O'Connor, Timothy; Moroz, Pavel; Kinder, Erich; Kohn, Elena; Perera, Dimuthu; Lorek, Ryan; Lambright, Scott; Imboden, Martene; Zamkov, Mikhail

2012-08-23

Conjoining different semiconductor materials in a single nano-composite provides synthetic means for the development of novel optoelectronic materials offering a superior control over the spatial distribution of charge carriers across material interfaces. As this study demonstrates, a combination of donor-acceptor nanocrystal (NC) domains in a single nanoparticle can lead to the realization of efficient photocatalytic materials, while a layered assembly of donor- and acceptor-like nanocrystals films gives rise to photovoltaic materials. Initially the paper focuses on the synthesis of composite inorganic nanocrystals, comprising linearly stacked ZnSe, CdS, and Pt domains, which jointly promote photoinduced charge separation. These structures are used in aqueous solutions for the photocatalysis of water under solar radiation, resulting in the production of H2 gas. To enhance the photoinduced separation of charges, a nanorod morphology with a linear gradient originating from an intrinsic electric field is used. The inter-domain energetics are then optimized to drive photogenerated electrons toward the Pt catalytic site while expelling the holes to the surface of ZnSe domains for sacrificial regeneration (via methanol). Here we show that the only efficient way to produce hydrogen is to use electron-donating ligands to passivate the surface states by tuning the energy level alignment at the semiconductor-ligand interface. Stable and efficient reduction of water is allowed by these ligands due to the fact that they fill vacancies in the valence band of the semiconductor domain, preventing energetic holes from degrading it. Specifically, we show that the energy of the hole is transferred to the ligand moiety, leaving the semiconductor domain functional. This enables us to return the entire nanocrystal-ligand system to a functional state, when the ligands are degraded, by simply adding fresh ligands to the system. To promote a photovoltaic charge separation, we use a composite two-layer solid of PbS and TiO2 films. In this configuration, photoinduced electrons are injected into TiO2 and are subsequently picked up by an FTO electrode, while holes are channeled to a Au electrode via PbS layer. To develop the latter we introduce a Semiconductor Matrix Encapsulated Nanocrystal Arrays (SMENA) strategy, which allows bonding PbS NCs into the surrounding matrix of CdS semiconductor. As a result, fabricated solids exhibit excellent thermal stability, attributed to the heteroepitaxial structure of nanocrystal-matrix interfaces, and show compelling light-harvesting performance in prototype solar cells.

Nanotube junctions

DOEpatents

Crespi, Vincent Henry; Cohen, Marvin Lou; Louie, Steven Gwon; Zettl, Alexander Karlwalte

2004-12-28

The present invention comprises a new nanoscale metal-semiconductor, semiconductor-semiconductor, or metal-metal junction, designed by introducing topological or chemical defects in the atomic structure of the nanotube. Nanotubes comprising adjacent sections having differing electrical properties are described. These nanotubes can be constructed from combinations of carbon, boron, nitrogen and other elements. The nanotube can be designed having different indices on either side of a junction point in a continuous tube so that the electrical properties on either side of the junction vary in a useful fashion. For example, the inventive nanotube may be electrically conducting on one side of a junction and semiconducting on the other side. An example of a semiconductor-metal junction is a Schottky barrier. Alternatively, the nanotube may exhibit different semiconductor properties on either side of the junction. Nanotubes containing heterojunctions, Schottky barriers, and metal-metal junctions are useful for microcircuitry.

Nanotube junctions

DOEpatents

Crespi, Vincent Henry; Cohen, Marvin Lou; Louie, Steven Gwon Sheng; Zettl, Alexander Karlwalter

2003-01-01

The present invention comprises a new nanoscale metal-semiconductor, semiconductor-semiconductor, or metal-metal junction, designed by introducing topological or chemical defects in the atomic structure of the nanotube. Nanotubes comprising adjacent sections having differing electrical properties are described. These nanotubes can be constructed from combinations of carbon, boron, nitrogen and other elements. The nanotube can be designed having different indices on either side of a junction point in a continuous tube so that the electrical properties on either side of the junction vary in a useful fashion. For example, the inventive nanotube may be electrically conducting on one side of a junction and semiconducting on the other side. An example of a semiconductor-metal junction is a Schottky barrier. Alternatively, the nanotube may exhibit different semiconductor properties on either side of the junction. Nanotubes containing heterojunctions, Schottky barriers, and metal-metal junctions are useful for microcircuitry.

p-Type semiconducting nickel oxide as an efficiency-enhancing anodal interfacial layer in bulk heterojunction solar cells

DOEpatents

Irwin, Michael D; Buchholz, Donald B; Marks, Tobin J; Chang, Robert P. H.

2014-11-25

The present invention, in one aspect, relates to a solar cell. In one embodiment, the solar cell includes an anode, a p-type semiconductor layer formed on the anode, and an active organic layer formed on the p-type semiconductor layer, where the active organic layer has an electron-donating organic material and an electron-accepting organic material.

Processes for multi-layer devices utilizing layer transfer

DOEpatents

Nielson, Gregory N; Sanchez, Carlos Anthony; Tauke-Pedretti, Anna; Kim, Bongsang; Cederberg, Jeffrey; Okandan, Murat; Cruz-Campa, Jose Luis; Resnick, Paul J

2015-02-03

A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, T.B.

1985-09-30

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron tunneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, Tomas B.

1987-01-01

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron funneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, T.B.

1987-06-23

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron funneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner. 2 figs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Usanov, D. A., E-mail: UsanovDA@info.sgu.ru; Nikitov, S. A.; Skripal, A. V.

A method is proposed for the measurement of the electrophysical characteristics of semiconductor structures: the electrical conductivity of the n layer, which plays the role of substrate for a semiconductor structure, and the thickness and electrical conductivity of the strongly doped epitaxial n{sup +} layer. The method is based on the use of a one-dimensional microwave photonic crystal with a violation of periodicity containing the semiconductor structure under investigation. The characteristics of epitaxial gallium-arsenide structures consisting of an epitaxial layer and the semi-insulating substrate measured by this method are presented.

Photoprecursor Approach Enables Preparation of Well-Performing Bulk-Heterojunction Layers Comprising a Highly Aggregating Molecular Semiconductor.

PubMed

Suzuki, Mitsuharu; Yamaguchi, Yuji; Takahashi, Kohei; Takahira, Katsuya; Koganezawa, Tomoyuki; Masuo, Sadahiro; Nakayama, Ken-ichi; Yamada, Hiroko

2016-04-06

Active-layer morphology critically affects the performance of organic photovoltaic cells, and thus its optimization is a key toward the achievement of high-efficiency devices. However, the optimization of active-layer morphology is sometimes challenging because of the intrinsic properties of materials such as strong self-aggregating nature or low miscibility. This study postulates that the "photoprecursor approach" can serve as an effective means to prepare well-performing bulk-heterojunction (BHJ) layers containing highly aggregating molecular semiconductors. In the photoprecursor approach, a photoreactive precursor compound is solution-deposited and then converted in situ to a semiconducting material. This study employs 2,6-di(2-thienyl)anthracene (DTA) and [6,6]-phenyl-C71-butyric acid methyl ester as p- and n-type materials, respectively, in which DTA is generated by the photoprecursor approach from the corresponding α-diketone-type derivative DTADK. When only chloroform is used as a cast solvent, the photovoltaic performance of the resulting BHJ films is severely limited because of unfavorable film morphology. The addition of a high-boiling-point cosolvent, o-dichlorobenzene (o-DCB), to the cast solution leads to significant improvement such that the resulting active layers afford up to approximately 5 times higher power conversion efficiencies. The film structure is investigated by two-dimensional grazing-incident wide-angle X-ray diffraction, atomic force microscopy, and fluorescence microspectroscopy to demonstrate that the use of o-DCB leads to improvement in film crystallinity and increase in charge-carrier generation efficiency. The change in film structure is assumed to originate from dynamic molecular motion enabled by the existence of solvent during the in situ photoreaction. The unique features of the photoprecursor approach will be beneficial in extending the material and processing scopes for the development of organic thin-film devices.

Coincident site lattice-matched growth of semiconductors on substrates using compliant buffer layers

DOEpatents

Norman, Andrew

2016-08-23

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.

Fabrication of optically reflecting ohmic contacts for semiconductor devices

DOEpatents

Sopori, B.L.

1995-07-04

A method is provided to produce a low-resistivity ohmic contact having high optical reflectivity on one side of a semiconductor device. The contact is formed by coating the semiconductor substrate with a thin metal film on the back reflecting side and then optically processing the wafer by illuminating it with electromagnetic radiation of a predetermined wavelength and energy level through the front side of the wafer for a predetermined period of time. This method produces a thin epitaxial alloy layer between the semiconductor substrate and the metal layer when a crystalline substrate is used. The alloy layer provides both a low-resistivity ohmic contact and high optical reflectance. 5 figs.

Scalable ferroelectric MOS capacitors comprised of single crystalline SrZrxTi1-xO3 on Ge.

NASA Astrophysics Data System (ADS)

Moghadam, Reza; Xiao, Z.-Y.; Ahmadi-Majlan, K.; Grimley, E.; Ong, P. V.; Lebeau, J. M.; Chambers, S. A.; Hong, X.; Sushko, P.; Ngai, J. H.

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to field-effect devices that require very little power to operate, or that possess both logic and memory functionalities. The development of metal-oxide-semiconductor (MOS) capacitors in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel is essential in order to realize such field-effect devices. Here we demonstrate that scalable, ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x = 0.7) that has been epitaxially grown on Ge. Single crystalline SrZrxTi1-xO3 exhibits characteristics that are ideal for a ferroelectric gate material, namely, a type-I band offset with respect to Ge, large coercive fields and polarization that can be enhanced with electric field. The latter characteristic stems from the relaxor nature of SrZrxTi1-xO3. These properties enable MOS capacitors with 5 nm thick SrZrxTi1-xO3 layers to exhibit a nearly 2 V wide hysteretic window in the capacitance-voltage characteristics. The realization of ferroelectric MOS capacitors with technologically relevant gate thicknesses opens the pathway to practical field effect devices. NSF DMR 1508530.

Context-based automated defect classification system using multiple morphological masks

DOEpatents

Gleason, Shaun S.; Hunt, Martin A.; Sari-Sarraf, Hamed

2002-01-01

Automatic detection of defects during the fabrication of semiconductor wafers is largely automated, but the classification of those defects is still performed manually by technicians. This invention includes novel digital image analysis techniques that generate unique feature vector descriptions of semiconductor defects as well as classifiers that use these descriptions to automatically categorize the defects into one of a set of pre-defined classes. Feature extraction techniques based on multiple-focus images, multiple-defect mask images, and segmented semiconductor wafer images are used to create unique feature-based descriptions of the semiconductor defects. These feature-based defect descriptions are subsequently classified by a defect classifier into categories that depend on defect characteristics and defect contextual information, that is, the semiconductor process layer(s) with which the defect comes in contact. At the heart of the system is a knowledge database that stores and distributes historical semiconductor wafer and defect data to guide the feature extraction and classification processes. In summary, this invention takes as its input a set of images containing semiconductor defect information, and generates as its output a classification for the defect that describes not only the defect itself, but also the location of that defect with respect to the semiconductor process layers.

Graded core/shell semiconductor nanorods and nanorod barcodes

DOEpatents

Alivisatos, A. Paul; Scher, Erik C.; Manna, Liberato

2010-12-14

Graded core/shell semiconductor nanorods and shaped nanorods are disclosed comprising Group II-VI, Group III-V and Group IV semiconductors and methods of making the same. Also disclosed are nanorod barcodes using core/shell nanorods where the core is a semiconductor or metal material, and with or without a shell. Methods of labeling analytes using the nanorod barcodes are also disclosed.

Graded core/shell semiconductor nanorods and nanorod barcodes

DOEpatents

Alivisatos, A. Paul; Scher, Erik C.; Manna, Liberato

2013-03-26

Graded core/shell semiconductor nanorods and shapped nanorods are disclosed comprising Group II-VI, Group III-V and Group IV semiconductors and methods of making the same. Also disclosed are nanorod barcodes using core/shell nanorods where the core is a semiconductor or metal material, and with or without a shell. Methods of labeling analytes using the nanorod barcodes are also disclosed.

Tunable Electron and Hole Injection Enabled by Atomically Thin Tunneling Layer for Improved Contact Resistance and Dual Channel Transport in MoS2/WSe2 van der Waals Heterostructure.

PubMed

Khan, Muhammad Atif; Rathi, Servin; Lee, Changhee; Lim, Dongsuk; Kim, Yunseob; Yun, Sun Jin; Youn, Doo Hyeb; Kim, Gil-Ho

2018-06-25

Two-dimensional (2D) materials based heterostructures provide a unique platform where interaction between stacked 2D layers can enhance the electrical and opto-electrical properties as well as give rise to interesting new phenomena. Here, operation of a van der Waals heterostructure device comprising of vertically stacked bi-layer MoS 2 and few layered WSe 2 has been demonstrated in which atomically thin MoS 2 layer has been employed as a tunneling layer to the underlying WSe 2 layer. In this way, simultaneous contacts to both MoS 2 and WSe 2 2D layers have been established by forming direct MS (metal semiconductor) to MoS 2 and tunneling based MIS (metal insulator semiconductor) contacts to WSe 2 , respectively. The use of MoS 2 as a dielectric tunneling layer results in improved contact resistance (80 kΩ-µm) for WSe 2 contact, which is attributed to reduction in effective Schottky barrier height and is also confirmed from the temperature dependent measurement. Further, this unique contact engineering and type II band alignment between MoS 2 and WSe 2 enables a selective and independent carrier transport across the respective layers. This contact engineered dual channel heterostructure exhibits an excellent gate control and both channel current and carrier types can be modulated by the vertical electric field of the gate electrode, which is also reflected in on/off ratio of 10 4 for both electrons (MoS 2 ) and holes (WSe 2 ) channels. Moreover, the charge transfer at the heterointerface is studied quantitatively from the shift in the threshold voltage of the pristine MoS 2 and heterostructure device, which agrees with the carrier recombination induced optical quenching as observed in the Raman spectra of the pristine and heterostructure layers. This observation of dual channel ambipolar transport enabled by the hybrid tunneling contacts and strong interlayer coupling can be utilized for high performance opto-electrical devices and applications.

Preparation of a semiconductor thin film

DOEpatents

Pehnt, Martin; Schulz, Douglas L.; Curtis, Calvin J.; Ginley, David S.

1998-01-01

A process for the preparation of a semiconductor film. The process comprises depositing nanoparticles of a semiconductor material onto a substrate whose surface temperature during nanoparticle deposition thereon is sufficient to cause substantially simultaneous fusion of the nanoparticles to thereby coalesce with each other and effectuate film growth.

Highly sensitive optically controlled tunable capacitor and photodetector based on a metal-insulator-semiconductor on silicon-on-insulator substrates

NASA Astrophysics Data System (ADS)

Mikhelashvili, V.; Cristea, D.; Meyler, B.; Yofis, S.; Shneider, Y.; Atiya, G.; Cohen-Hyams, T.; Kauffmann, Y.; Kaplan, W. D.; Eisenstein, G.

2015-01-01

We describe a new type of optically sensitive tunable capacitor with a wide band response ranging from the ultraviolet (245 nm) to the near infrared (880 nm). It is based on a planar Metal-Oxide-Semiconductor (MOS) structure fabricated on an insulator on silicon substrate where the insulator layer comprises a double layer dielectric stack of SiO2-HfO2. Two operating configurations have been examined, a single diode and a pair of back-to-back connected devices, where either one or both diodes are illuminated. The varactors exhibit, in all cases, very large sensitivities to illumination. Near zero bias, the capacitance dependence on illumination intensity is sub linear and otherwise it is nearly linear. In the back-to-back connected configuration, the reverse biased diode acts as a light tunable resistor whose value affects strongly the capacitance of the second, forward biased, diode and vice versa. The proposed device is superior to other optical varactors in its large sensitivity to illumination in a very broad wavelength range (245 nm-880 nm), the strong capacitance dependence on voltage and the superior current photo responsivity. Above and beyond that structure requires a very simple fabrication process which is CMOS compatible.

Synthesis, structural, thermal and optical studies of inorganic-organic hybrid semiconductors, R-PbI4

NASA Astrophysics Data System (ADS)

Pradeesh, K.; Nageswara Rao, K.; Vijaya Prakash, G.

2013-02-01

Wide varieties of naturally self-assembled two-dimensional inorganic-organic (IO) hybrid semiconductors, (4-ClC6H4NH3)2PbI4, (C6H9C2H4NH3)2PbI4, (CnH2n+1NH3)2PbI4 (where n = 12, 16, 18), (CnH2n-1NH3)2PbI4 (where n = 3, 4, 5), (C6H5C2H4NH3)2PbI4, NH3(CH2)12NH3PbI4, and (C4H3SC2H4NH3)2PbI4, were fabricated by intercalating structurally diverse organic guest moieties into lead iodide perovskite structure. The crystal packing of all these fabricated IO-hybrids comprises of well-ordered organic and inorganic layers, stacked-up alternately along c-axis. Almost all these hybrids are thermally stable upto 200 °C and show strong room-temperature exciton absorption and photoluminescence features. These strongly confined optical excitons are highly influenced by structural deformation of PbI matrix due to the conformation of organic moiety. A systematic correlation of optical exciton behavior of IO-hybrids with the organic/inorganic layer thicknesses, intercalating organic moieties, and various structural disorders were discussed. This systematic study clearly suggests that the PbI layer crumpling is directly responsible for the tunability of optical exciton energy.

Preparation of a semiconductor thin film

DOEpatents

Pehnt, M.; Schulz, D.L.; Curtis, C.J.; Ginley, D.S.

1998-01-27

A process is disclosed for the preparation of a semiconductor film. The process comprises depositing nanoparticles of a semiconductor material onto a substrate whose surface temperature during nanoparticle deposition thereon is sufficient to cause substantially simultaneous fusion of the nanoparticles to thereby coalesce with each other and effectuate film growth.

Effect of the waveguide layer thickness on output characteristics of semiconductor lasers with emission wavelength from 1500 to 1600 nm

NASA Astrophysics Data System (ADS)

Marmalyuk, A. A.; Ryaboshtan, Yu L.; Gorlachuk, P. V.; Ladugin, M. A.; Padalitsa, A. A.; Slipchenko, S. O.; Lyutetskiy, A. V.; Veselov, D. A.; Pikhtin, N. A.

2018-03-01

The effect of the waveguide layer thickness on output characteristics of AlGaInAs/InP quantum-well semiconductor lasers is analysed. The samples of semiconductor lasers with narrow and wide waveguides are experimentally fabricated. Their comparison is carried out and the advantages of particular constructions depending on the current pump are demonstrated.

Flat-lying semiconductor-insulator interfacial layer in DNTT thin films.

PubMed

Jung, Min-Cherl; Leyden, Matthew R; Nikiforov, Gueorgui O; Lee, Michael V; Lee, Han-Koo; Shin, Tae Joo; Takimiya, Kazuo; Qi, Yabing

2015-01-28

The molecular order of organic semiconductors at the gate dielectric is the most critical factor determining carrier mobility in thin film transistors since the conducting channel forms at the dielectric interface. Despite its fundamental importance, this semiconductor-insulator interface is not well understood, primarily because it is buried within the device. We fabricated dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) thin film transistors by thermal evaporation in vacuum onto substrates held at different temperatures and systematically correlated the extracted charge mobility to the crystal grain size and crystal orientation. As a result, we identify a molecular layer of flat-lying DNTT molecules at the semiconductor-insulator interface. It is likely that such a layer might form in other material systems as well, and could be one of the factors reducing charge transport. Controlling this interfacial flat-lying layer may raise the ultimate possible device performance for thin film devices.

Wavelength-division multiplexed optical integrated circuit with vertical diffraction grating

NASA Technical Reports Server (NTRS)

Lang, Robert J. (Inventor); Forouhar, Siamak (Inventor)

1994-01-01

A semiconductor optical integrated circuit for wave division multiplexing has a semiconductor waveguide layer, a succession of diffraction grating points in the waveguide layer along a predetermined diffraction grating contour, a semiconductor diode array in the waveguide layer having plural optical ports facing the succession of diffraction grating points along a first direction, respective semiconductor diodes in the array corresponding to respective ones of a predetermined succession of wavelengths, an optical fiber having one end thereof terminated at the waveguide layer, the one end of the optical fiber facing the succession of diffraction grating points along a second direction, wherein the diffraction grating points are spatially distributed along the predetermined contour in such a manner that the succession of diffraction grating points diffracts light of respective ones of the succession of wavelengths between the one end of the optical fiber and corresponding ones of the optical ports.

Contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication

DOEpatents

Sopori, Bhushan

2014-05-27

Methods for contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication are provided. In one embodiment, a method for fabricating an electrical semiconductor device comprises: a first step that includes gettering of impurities from a semiconductor wafer and forming a backsurface field; and a second step that includes forming a front contact for the semiconductor wafer, wherein the second step is performed after completion of the first step.

Multifunctional Organic-Semiconductor Interfacial Layers for Solution-Processed Oxide-Semiconductor Thin-Film Transistor.

PubMed

Kwon, Guhyun; Kim, Keetae; Choi, Byung Doo; Roh, Jeongkyun; Lee, Changhee; Noh, Yong-Young; Seo, SungYong; Kim, Myung-Gil; Kim, Choongik

2017-06-01

The stabilization and control of the electrical properties in solution-processed amorphous-oxide semiconductors (AOSs) is crucial for the realization of cost-effective, high-performance, large-area electronics. In particular, impurity diffusion, electrical instability, and the lack of a general substitutional doping strategy for the active layer hinder the industrial implementation of copper electrodes and the fine tuning of the electrical parameters of AOS-based thin-film transistors (TFTs). In this study, the authors employ a multifunctional organic-semiconductor (OSC) interlayer as a solution-processed thin-film passivation layer and a charge-transfer dopant. As an electrically active impurity blocking layer, the OSC interlayer enhances the electrical stability of AOS TFTs by suppressing the adsorption of environmental gas species and copper-ion diffusion. Moreover, charge transfer between the organic interlayer and the AOS allows the fine tuning of the electrical properties and the passivation of the electrical defects in the AOS TFTs. The development of a multifunctional solution-processed organic interlayer enables the production of low-cost, high-performance oxide semiconductor-based circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Mixed ternary heterojunction solar cell

DOEpatents

Chen, Wen S.; Stewart, John M.

1992-08-25

A thin film heterojunction solar cell and a method of making it has a p-type layer of mixed ternary I-III-VI.sub.2 semiconductor material in contact with an n-type layer of mixed binary II-VI semiconductor material. The p-type semiconductor material includes a low resistivity copper-rich region adjacent the back metal contact of the cell and a composition gradient providing a minority carrier mirror that improves the photovoltaic performance of the cell. The p-type semiconductor material preferably is CuInGaSe.sub.2 or CuIn(SSe).sub.2.

Near single-crystalline, high-carrier-mobility silicon thin film on a polycrystalline/amorphous substrate

DOEpatents

Findikoglu, Alp T [Los Alamos, NM; Jia, Quanxi [Los Alamos, NM; Arendt, Paul N [Los Alamos, NM; Matias, Vladimir [Santa Fe, NM; Choi, Woong [Los Alamos, NM

2009-10-27

A template article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material; is provided, together with a semiconductor article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material, and, a top-layer of semiconductor material upon the buffer material layer.

Method for sputtering a PIN microcrystalline/amorphous silicon semiconductor device with the P and N-layers sputtered from boron and phosphorous heavily doped targets

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-04-02

A silicon PIN microcrystalline/amorphous silicon semiconductor device is constructed by the sputtering of N, and P layers of silicon from silicon doped targets and the I layer from an undoped target, and at least one semi-transparent ohmic electrode.

Electrodynamic properties of a hypercrystal with ferrite and semiconductor layers in an external magnetic field

NASA Astrophysics Data System (ADS)

Fedorin, Illia V.

2018-01-01

Electrodynamic properties of a photonic hypercrystal formed by periodically alternating two types of anisotropic metamaterials are studied. The first metamaterial consists of ferrite and dielectric layers, while the second metamaterial consists of semiconductor and dielectric layers. The system is assumed to be placed in an external magnetic field, which applied parallel to the boundaries of the layers. An effective medium theory which is suitable for calculation of properties of long-wavelength electromagnetic modes is applied in order to derive averaged expressions for effective constitutive parameters. It has been shown that providing a conscious choice of the constitutive parameters and material fractions of magnetic, semiconductor, and dielectric layers, the system under study shows hypercrystal properties for both TE and TM waves in the different frequency ranges.

Process for fabricating polycrystalline semiconductor thin-film solar cells, and cells produced thereby

DOEpatents

Wu, Xuanzhi; Sheldon, Peter

2000-01-01

A novel, simplified method for fabricating a thin-film semiconductor heterojunction photovoltaic device includes initial steps of depositing a layer of cadmium stannate and a layer of zinc stannate on a transparent substrate, both by radio frequency sputtering at ambient temperature, followed by the depositing of dissimilar layers of semiconductors such as cadmium sulfide and cadmium telluride, and heat treatment to convert the cadmium stannate to a substantially single-phase material of a spinel crystal structure. Preferably, the cadmium sulfide layer is also deposited by radio frequency sputtering at ambient temperature, and the cadmium telluride layer is deposited by close space sublimation at an elevated temperature effective to convert the amorphous cadmium stannate to the polycrystalline cadmium stannate with single-phase spinel structure.

Architectures and criteria for the design of high efficiency organic photovoltaic cells

DOEpatents

Rand, Barry; Forrest, Stephen R; Pendergrast Burk, Diane

2015-03-31

A method for fabricating an organic photovoltaic cell includes providing a first electrode; depositing a series of at least seven layers onto the first electrode, each layer consisting essentially of a different organic semiconductor material, the organic semiconductor material of at least an intermediate layer of the sequence being a photoconductive material; and depositing a second electrode onto the sequence of at least seven layers. One of the first electrode and the second electrode is an anode and the other is a cathode. The organic semiconductor materials of the series of at least seven layers are arranged to provide a sequence of decreasing lowest unoccupied molecular orbitals (LUMOs) and a sequence of decreasing highest occupied molecular orbitals (HOMOs) across the series from the anode to the cathode.

Methods and devices for fabricating and assembling printable semiconductor elements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Methods and devices for fabricating and assembling printable semiconductor elements

DOEpatents

Nuzzo, Ralph G; Rogers, John A; Menard, Etienne; Lee, Keon Jae; Khang, Dahl-Young; Sun, Yugang; Meitl, Matthew; Zhu, Zhengtao

2014-03-04

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Organo Luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Jr., Marcel; Alivisatos, Paul

1999-01-01

A luminescent semiconductor nanocrystal compound is described which is capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation (luminescing) in a narrow wavelength band and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source (of narrow or broad bandwidth) or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule. The luminescent semiconductor nanocrystal compound is linked to an affinity molecule to form an organo luminescent semiconductor nanocrystal probe capable of bonding with a detectable substance in a material being analyzed, and capable of emitting electromagnetic radiation in a narrow wavelength band and/or absorbing, scattering, or diffracting energy when excited by an electromagnetic radiation source (of narrow or broad bandwidth) or a particle beam. The probe is stable to repeated exposure to light in the presence of oxygen and/or other radicals. Further described is a process for making the luminescent semiconductor nanocrystal compound and for making the organo luminescent semiconductor nanocrystal probe comprising the luminescent semiconductor nanocrystal compound linked to an affinity molecule capable of bonding to a detectable substance. A process is also described for using the probe to determine the presence of a detectable substance in a material.

Semiconductor-nanocrystal/conjugated polymer thin films

DOEpatents

Alivisatos, A. Paul; Dittmer, Janke J.; Huynh, Wendy U.; Milliron, Delia

2014-06-17

The invention described herein provides for thin films and methods of making comprising inorganic semiconductor-nanocrystals dispersed in semiconducting-polymers in high loading amounts. The invention also describes photovoltaic devices incorporating the thin films.

Semiconductor-nanocrystal/conjugated polymer thin films

DOEpatents

Alivisatos, A. Paul; Dittmer, Janke J.; Huynh, Wendy U.; Milliron, Delia

2010-08-17

The invention described herein provides for thin films and methods of making comprising inorganic semiconductor-nanocrystals dispersed in semiconducting-polymers in high loading amounts. The invention also describes photovoltaic devices incorporating the thin films.

A Designed Room Temperature Multilayered Magnetic Semiconductor

NASA Astrophysics Data System (ADS)

Bouma, Dinah Simone; Charilaou, Michalis; Bordel, Catherine; Duchin, Ryan; Barriga, Alexander; Farmer, Adam; Hellman, Frances; Materials Science Division, Lawrence Berkeley National Lab Team

2015-03-01

A room temperature magnetic semiconductor has been designed and fabricated by using an epitaxial antiferromagnet (NiO) grown in the (111) orientation, which gives surface uncompensated magnetism for an odd number of planes, layered with the lightly doped semiconductor Al-doped ZnO (AZO). Magnetization and Hall effect measurements of multilayers of NiO and AZO are presented for varying thickness of each. The magnetic properties vary as a function of the number of Ni planes in each NiO layer; an odd number of Ni planes yields on each NiO layer an uncompensated moment which is RKKY-coupled to the moments on adjacent NiO layers via the carriers in the AZO. This RKKY coupling oscillates with the AZO layer thickness, and it disappears entirely in samples where the AZO is replaced with undoped ZnO. The anomalous Hall effect data indicate that the carriers in the AZO are spin-polarized according to the direction of the applied field at both low temperature and room temperature. NiO/AZO multilayers are therefore a promising candidate for spintronic applications demanding a room-temperature semiconductor.

Abrupt Depletion Layer Approximation for the Metal Insulator Semiconductor Diode.

ERIC Educational Resources Information Center

Jones, Kenneth

1979-01-01

Determines the excess surface change carrier density, surface potential, and relative capacitance of a metal insulator semiconductor diode as a function of the gate voltage, using the precise questions and the equations derived with the abrupt depletion layer approximation. (Author/GA)

Membrane projection lithography

DOEpatents

Burckel, David Bruce; Davids, Paul S; Resnick, Paul J; Draper, Bruce L

2015-03-17

The various technologies presented herein relate to a three dimensional manufacturing technique for application with semiconductor technologies. A membrane layer can be formed over a cavity. An opening can be formed in the membrane such that the membrane can act as a mask layer to the underlying wall surfaces and bottom surface of the cavity. A beam to facilitate an operation comprising any of implantation, etching or deposition can be directed through the opening onto the underlying surface, with the opening acting as a mask to control the area of the underlying surfaces on which any of implantation occurs, material is removed, and/or material is deposited. The membrane can be removed, a new membrane placed over the cavity and a new opening formed to facilitate another implantation, etching, or deposition operation. By changing the direction of the beam different wall/bottom surfaces can be utilized to form a plurality of structures.

Energy-level alignment at organic heterointerfaces

PubMed Central

Oehzelt, Martin; Akaike, Kouki; Koch, Norbert; Heimel, Georg

2015-01-01

Today’s champion organic (opto-)electronic devices comprise an ever-increasing number of different organic-semiconductor layers. The functionality of these complex heterostructures largely derives from the relative alignment of the frontier molecular-orbital energies in each layer with respect to those in all others. Despite the technological relevance of the energy-level alignment at organic heterointerfaces, and despite continued scientific interest, a reliable model that can quantitatively predict the full range of phenomena observed at such interfaces is notably absent. We identify the limitations of previous attempts to formulate such a model and highlight inconsistencies in the interpretation of the experimental data they were based on. We then develop a theoretical framework, which we demonstrate to accurately reproduce experiment. Applying this theory, a comprehensive overview of all possible energy-level alignment scenarios that can be encountered at organic heterojunctions is finally given. These results will help focus future efforts on developing functional organic interfaces for superior device performance. PMID:26702447

Gain in three-dimensional metamaterials utilizing semiconductor quantum structures

NASA Astrophysics Data System (ADS)

Schwaiger, Stephan; Klingbeil, Matthias; Kerbst, Jochen; Rottler, Andreas; Costa, Ricardo; Koitmäe, Aune; Bröll, Markus; Heyn, Christian; Stark, Yuliya; Heitmann, Detlef; Mendach, Stefan

2011-10-01

We demonstrate gain in a three-dimensional metal/semiconductor metamaterial by the integration of optically active semiconductor quantum structures. The rolling-up of a metallic structure on top of strained semiconductor layers containing a quantum well allows us to achieve a tightly bent superlattice consisting of alternating layers of lossy metallic and amplifying gain material. We show that the transmission through the superlattice can be enhanced by exciting the quantum well optically under both pulsed or continuous wave excitation. This points out that our structures can be used as a starting point for arbitrary three-dimensional metamaterials including gain.

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubenko, E. B., E-mail: eugene.chubenko@gmail.com; Redko, S. V.; Sherstnyov, A. I.

2016-03-15

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materialsmore » on the basis of porous silicon and nanostructures with a high aspect ratio.« less

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

Traditional Semiconductors in the Two-Dimensional Limit.

PubMed

Lucking, Michael C; Xie, Weiyu; Choe, Duk-Hyun; West, Damien; Lu, Toh-Ming; Zhang, S B

2018-02-23

Interest in two-dimensional materials has exploded in recent years. Not only are they studied due to their novel electronic properties, such as the emergent Dirac fermion in graphene, but also as a new paradigm in which stacking layers of distinct two-dimensional materials may enable different functionality or devices. Here, through first-principles theory, we reveal a large new class of two-dimensional materials which are derived from traditional III-V, II-VI, and I-VII semiconductors. It is found that in the ultrathin limit the great majority of traditional binary semiconductors studied (a series of 28 semiconductors) are not only kinetically stable in a two-dimensional double layer honeycomb structure, but more energetically stable than the truncated wurtzite or zinc-blende structures associated with three dimensional bulk. These findings both greatly increase the landscape of two-dimensional materials and also demonstrate that in the double layer honeycomb form, even ordinary semiconductors, such as GaAs, can exhibit exotic topological properties.

Scalable quantum computer architecture with coupled donor-quantum dot qubits

DOEpatents

Schenkel, Thomas; Lo, Cheuk Chi; Weis, Christoph; Lyon, Stephen; Tyryshkin, Alexei; Bokor, Jeffrey

2014-08-26

A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, wherein a first voltage applied across at least one pair of the aligned quantum dot and donor atom controls a donor-quantum dot coupling. A method of performing quantum computing in a scalable architecture quantum computing apparatus includes arranging a pattern of single spin memory donor atoms in a semiconductor layer, forming a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, applying a first voltage across at least one aligned pair of a quantum dot and donor atom to control a donor-quantum dot coupling, and applying a second voltage between one or more quantum dots to control a Heisenberg exchange J coupling between quantum dots and to cause transport of a single spin polarized electron between quantum dots.

Self-cleaning and surface chemical reactions during hafnium dioxide atomic layer deposition on indium arsenide.

PubMed

Timm, Rainer; Head, Ashley R; Yngman, Sofie; Knutsson, Johan V; Hjort, Martin; McKibbin, Sarah R; Troian, Andrea; Persson, Olof; Urpelainen, Samuli; Knudsen, Jan; Schnadt, Joachim; Mikkelsen, Anders

2018-04-12

Atomic layer deposition (ALD) enables the ultrathin high-quality oxide layers that are central to all modern metal-oxide-semiconductor circuits. Crucial to achieving superior device performance are the chemical reactions during the first deposition cycle, which could ultimately result in atomic-scale perfection of the semiconductor-oxide interface. Here, we directly observe the chemical reactions at the surface during the first cycle of hafnium dioxide deposition on indium arsenide under realistic synthesis conditions using photoelectron spectroscopy. We find that the widely used ligand exchange model of the ALD process for the removal of native oxide on the semiconductor and the simultaneous formation of the first hafnium dioxide layer must be significantly revised. Our study provides substantial evidence that the efficiency of the self-cleaning process and the quality of the resulting semiconductor-oxide interface can be controlled by the molecular adsorption process of the ALD precursors, rather than the subsequent oxide formation.

Digital Alloy Absorber for Photodetectors

NASA Technical Reports Server (NTRS)

Hill, Cory J. (Inventor); Ting, David Z. (Inventor); Gunapala, Sarath D. (Inventor)

2016-01-01

In order to increase the spectral response range and improve the mobility of the photo-generated carriers (e.g. in an nBn photodetector), a digital alloy absorber may be employed by embedding one (or fraction thereof) to several monolayers of a semiconductor material (insert layers) periodically into a different host semiconductor material of the absorber layer. The semiconductor material of the insert layer and the host semiconductor materials may have lattice constants that are substantially mismatched. For example, this may performed by periodically embedding monolayers of InSb into an InAsSb host as the absorption region to extend the cutoff wavelength of InAsSb photodetectors, such as InAsSb based nBn devices. The described technique allows for simultaneous control of alloy composition and net strain, which are both key parameters for the photodetector operation.

GUARD RING SEMICONDUCTOR JUNCTION

DOEpatents

Goulding, F.S.; Hansen, W.L.

1963-12-01

A semiconductor diode having a very low noise characteristic when used under reverse bias is described. Surface leakage currents, which in conventional diodes greatly contribute to noise, are prevented from mixing with the desired signal currents. A p-n junction is formed with a thin layer of heavily doped semiconductor material disposed on a lightly doped, physically thick base material. An annular groove cuts through the thin layer and into the base for a short distance, dividing the thin layer into a peripheral guard ring that encircles the central region. Noise signal currents are shunted through the guard ring, leaving the central region free from such currents. (AEC)

Mechanisms of Current Transfer in Electrodeposited Layers of Submicron Semiconductor Particles

NASA Astrophysics Data System (ADS)

Zhukov, N. D.; Mosiyash, D. S.; Sinev, I. V.; Khazanov, A. A.; Smirnov, A. V.; Lapshin, I. V.

2017-12-01

Current-voltage ( I- V) characteristics of conductance in multigrain layers of submicron particles of silicon, gallium arsenide, indium arsenide, and indium antimonide have been studied. Nanoparticles of all semiconductors were obtained by processing initial single crystals in a ball mill and applied after sedimentation onto substrates by means of electrodeposition. Detailed analysis of the I- V curves of electrodeposited layers shows that their behavior is determined by the mechanism of intergranular tunneling emission from near-surface electron states of submicron particles. Parameters of this emission process have been determined. The proposed multigrain semiconductor structures can be used in gas sensors, optical detectors, IR imagers, etc.

Methods for enhancing P-type doping in III-V semiconductor films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Feng; Stringfellow, Gerald; Zhu, Junyi

2017-08-01

Methods of doping a semiconductor film are provided. The methods comprise epitaxially growing the III-V semiconductor film in the presence of a dopant, a surfactant capable of acting as an electron reservoir, and hydrogen, under conditions that promote the formation of a III-V semiconductor film doped with the p-type dopant. In some embodiments of the methods, the epitaxial growth of the doped III-V semiconductor film is initiated at a first hydrogen partial pressure which is increased to a second hydrogen partial pressure during the epitaxial growth process.

Semiconductor bridge (SCB) detonator

DOEpatents

Bickes, Jr., Robert W.; Grubelich, Mark C.

1999-01-01

The present invention is a low-energy detonator for high-density secondary-explosive materials initiated by a semiconductor bridge igniter that comprises a pair of electrically conductive lands connected by a semiconductor bridge. The semiconductor bridge is in operational or direct contact with the explosive material, whereby current flowing through the semiconductor bridge causes initiation of the explosive material. Header wires connected to the electrically-conductive lands and electrical feed-throughs of the header posts of explosive devices, are substantially coaxial to the direction of current flow through the SCB, i.e., substantially coaxial to the SCB length.

Two-dimensional layered semiconductor/graphene heterostructures for solar photovoltaic applications.

PubMed

Shanmugam, Mariyappan; Jacobs-Gedrim, Robin; Song, Eui Sang; Yu, Bin

2014-11-07

Schottky barriers formed by graphene (monolayer, bilayer, and multilayer) on 2D layered semiconductor tungsten disulfide (WS2) nanosheets are explored for solar energy harvesting. The characteristics of the graphene-WS2 Schottky junction vary significantly with the number of graphene layers on WS2, resulting in differences in solar cell performance. Compared with monolayer or stacked bilayer graphene, multilayer graphene helps in achieving improved solar cell performance due to superior electrical conductivity. The all-layered-material Schottky barrier solar cell employing WS2 as a photoactive semiconductor exhibits efficient photon absorption in the visible spectral range, yielding 3.3% photoelectric conversion efficiency with multilayer graphene as the Schottky contact. Carrier transport at the graphene/WS2 interface and the interfacial recombination process in the Schottky barrier solar cells are examined.

Proximity charge sensing for semiconductor detectors

DOEpatents

Luke, Paul N; Tindall, Craig S; Amman, Mark

2013-10-08

A non-contact charge sensor includes a semiconductor detector having a first surface and an opposing second surface. The detector includes a high resistivity electrode layer on the first surface and a low resistivity electrode on the high resistivity electrode layer. A portion of the low resistivity first surface electrode is deleted to expose the high resistivity electrode layer in a portion of the area. A low resistivity electrode layer is disposed on the second surface of the semiconductor detector. A voltage applied between the first surface low resistivity electrode and the second surface low resistivity electrode causes a free charge to drift toward the first or second surface according to a polarity of the free charge and the voltage. A charge sensitive preamplifier coupled to a non-contact electrode disposed at a distance from the exposed high resistivity electrode layer outputs a signal in response to movement of free charge within the detector.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Conversion of type of quantum well structure

NASA Technical Reports Server (NTRS)

Ning, Cun-Zheng (Inventor)

2007-01-01

A method for converting a Type 2 quantum well semiconductor material to a Type 1 material. A second layer of undoped material is placed between first and third layers of selectively doped material, which are separated from the second layer by undoped layers having small widths. Doping profiles are chosen so that a first electrical potential increment across a first layer-second layer interface is equal to a first selected value and/or a second electrical potential increment across a second layer-third layer interface is equal to a second selected value. The semiconductor structure thus produced is useful as a laser material and as an incident light detector material in various wavelength regions, such as a mid-infrared region.

Conversion of Type of Quantum Well Structure

NASA Technical Reports Server (NTRS)

Ning, Cun-Zheng (Inventor)

2007-01-01

A method for converting a Type 2 quantum well semiconductor material to a Type 1 material. A second layer of undoped material is placed between first and third layers of selectively doped material, which are separated from the second layer by undoped layers having small widths. Doping profiles are chosen so that a first electrical potential increment across a first layer-second layer interface is equal to a first selected value and/or a second electrical potential increment across a second layer-third layer interface is equal to a second selected value. The semiconductor structure thus produced is useful as a laser material and as an incident light detector material in various wavelength regions, such as a mid-infrared region.

Electrically tunable infrared metamaterial devices

DOEpatents

Brener, Igal; Jun, Young Chul

2015-07-21

A wavelength-tunable, depletion-type infrared metamaterial optical device is provided. The device includes a thin, highly doped epilayer whose electrical permittivity can become negative at some infrared wavelengths. This highly-doped buried layer optically couples with a metamaterial layer. Changes in the transmission spectrum of the device can be induced via the electrical control of this optical coupling. An embodiment includes a contact layer of semiconductor material that is sufficiently doped for operation as a contact layer and that is effectively transparent to an operating range of infrared wavelengths, a thin, highly doped buried layer of epitaxially grown semiconductor material that overlies the contact layer, and a metallized layer overlying the buried layer and patterned as a resonant metamaterial.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon [Pinole, CA; Bruchez, Jr., Marcel; Alivisatos, Paul [Oakland, CA

2008-01-01

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) an affinity molecule linked to the semiconductor nanocrystal. The semiconductor nanocrystal is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. Exposure of the semiconductor nanocrystal to excitation energy will excite the semiconductor nanocrystal causing the emission of electromagnetic radiation. Further described are processes for respectively: making the luminescent semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Thick layered semiconductor devices with water top-gates: High on-off ratio field-effect transistors and aqueous sensors.

PubMed

Huang, Yuan; Sutter, Eli; Wu, Liangmei; Xu, Hong; Bao, Lihong; Gao, Hong-Jun; Zhou, Xingjiang; Sutter, Peter

2018-06-21

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal sub-threshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels where such control is difficult to realize with conventional back-gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Method for producing a hybridization of detector array and integrated circuit for readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

1993-01-01

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Release strategies for making transferable semiconductor structures, devices and device components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rogers, John A.; Nuzzo, Ralph G.; Meitl, Matthew

2016-05-24

Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Controlled growth of semiconductor crystals

DOEpatents

Bourret-Courchesne, Edith D.

1992-01-01

A method for growth of III-V, II-VI and related semiconductor single crystals that suppresses random nucleation and sticking of the semiconductor melt at the crucible walls. Small pieces of an oxide of boron B.sub.x O.sub.y are dispersed throughout the comminuted solid semiconductor charge in the crucible, with the oxide of boron preferably having water content of at least 600 ppm. The crucible temperature is first raised to a temperature greater than the melt temperature T.sub.m1 of the oxide of boron (T.sub.m1 =723.degree. K. for boron oxide B.sub.2 O.sub.3), and the oxide of boron is allowed to melt and form a reasonably uniform liquid layer between the crucible walls and bottom surfaces and the still-solid semiconductor charge. The temperature is then raised to approximately the melt temperature T.sub.m2 of the semiconductor charge material, and crystal growth proceeds by a liquid encapsulated, vertical gradient freeze process. About half of the crystals grown have a dislocation density of less than 1000/cm.sup.2. If the oxide of boron has water content less than 600 ppm, the crucible material should include boron nitride, a layer of the inner surface of the crucible should be oxidized before the oxide of boron in the crucible charge is melted, and the sum of thicknesses of the solid boron oxide layer and liquid boron oxide layer should be at least 50 .mu.m.

Controlled growth of semiconductor crystals

DOEpatents

Bourret-Courchesne, E.D.

1992-07-21

A method is disclosed for growth of III-V, II-VI and related semiconductor single crystals that suppresses random nucleation and sticking of the semiconductor melt at the crucible walls. Small pieces of an oxide of boron B[sub x]O[sub y] are dispersed throughout the comminuted solid semiconductor charge in the crucible, with the oxide of boron preferably having water content of at least 600 ppm. The crucible temperature is first raised to a temperature greater than the melt temperature T[sub m1] of the oxide of boron (T[sub m1]=723 K for boron oxide B[sub 2]O[sub 3]), and the oxide of boron is allowed to melt and form a reasonably uniform liquid layer between the crucible walls and bottom surfaces and the still-solid semiconductor charge. The temperature is then raised to approximately the melt temperature T[sub m2] of the semiconductor charge material, and crystal growth proceeds by a liquid encapsulated, vertical gradient freeze process. About half of the crystals grown have a dislocation density of less than 1000/cm[sup 2]. If the oxide of boron has water content less than 600 ppm, the crucible material should include boron nitride, a layer of the inner surface of the crucible should be oxidized before the oxide of boron in the crucible charge is melted, and the sum of thicknesses of the solid boron oxide layer and liquid boron oxide layer should be at least 50 [mu]m. 7 figs.

Electroless silver plating of the surface of organic semiconductors.

PubMed

Campione, Marcello; Parravicini, Matteo; Moret, Massimo; Papagni, Antonio; Schröter, Bernd; Fritz, Torsten

2011-10-04

The integration of nanoscale processes and devices demands fabrication routes involving rapid, cost-effective steps, preferably carried out under ambient conditions. The realization of the metal/organic semiconductor interface is one of the most demanding steps of device fabrication, since it requires mechanical and/or thermal treatments which increment costs and are often harmful in respect to the active layer. Here, we provide a microscopic analysis of a room temperature, electroless process aimed at the deposition of a nanostructured metallic silver layer with controlled coverage atop the surface of single crystals and thin films of organic semiconductors. This process relies on the reaction of aqueous AgF solutions with the nonwettable crystalline surface of donor-type organic semiconductors. It is observed that the formation of a uniform layer of silver nanoparticles can be accomplished within 20 min contact time. The electrical characterization of two-terminal devices performed before and after the aforementioned treatment shows that the metal deposition process is associated with a redox reaction causing the p-doping of the semiconductor. © 2011 American Chemical Society

The preparation method of terahertz monolithic integrated device

NASA Astrophysics Data System (ADS)

Zhang, Cong; Su, Bo; He, Jingsuo; Zhang, Hongfei; Wu, Yaxiong; Zhang, Shengbo; Zhang, Cunlin

2018-01-01

The terahertz monolithic integrated device is to integrate the pumping area of the terahertz generation, the detection area of the terahertz receiving and the metal waveguide of terahertz transmission on the same substrate. The terahertz generation and detection device use a photoconductive antenna structure the metal waveguide use a microstrip line structure. The evanescent terahertz-bandwidth electric field extending above the terahertz transmission line interacts with, and is modified by, overlaid dielectric samples, thus enabling the characteristic vibrational absorption resonances in the sample to be probed. In this device structure, since the semiconductor substrate of the photoconductive antenna is located between the strip conductor and the dielectric layer of the microstrip line, and the semiconductor substrate cannot grow on the dielectric layer directly. So how to prepare the semiconductor substrate of the photoconductive antenna and how to bond the semiconductor substrate to the dielectric layer of the microstrip line is a key step in the terahertz monolithic integrated device. In order to solve this critical problem, the epitaxial wafer structure of the two semiconductor substrates is given and transferred to the desired substrate by two methods, respectively.

Casimir Pressure in Mds-Structures

NASA Astrophysics Data System (ADS)

Yurova, V. A.; Bukina, M. N.; Churkin, Yu. V.; Fedortsov, A. B.; Klimchitskaya, G. L.

2012-07-01

The Casimir pressure on the dielectric layer in metal-dielectric-semiconductor (MDS) structures is calculated in the framework of the Lifshitz theory at nonzero temperature. In this calculation the standard parameters of semiconductor devices with a thin dielectric layer are used. We consider the thickness of a layer decreasing from 40 to 1 nm. At the shortest thickness the Casimir pressure achieves 8 MPa. At small thicknesses the results are compared with the predictions of nonrelativistic theory.

Semiconductor bridge (SCB) detonator

DOEpatents

Bickes, R.W. Jr.; Grubelich, M.C.

1999-01-19

The present invention is a low-energy detonator for high-density secondary-explosive materials initiated by a semiconductor bridge (SCB) igniter that comprises a pair of electrically conductive lands connected by a semiconductor bridge. The semiconductor bridge is in operational or direct contact with the explosive material, whereby current flowing through the semiconductor bridge causes initiation of the explosive material. Header wires connected to the electrically-conductive lands and electrical feed-throughs of the header posts of explosive devices, are substantially coaxial to the direction of current flow through the SCB, i.e., substantially coaxial to the SCB length. 3 figs.

Centimetre-scale electron diffusion in photoactive organic heterostructures

NASA Astrophysics Data System (ADS)

Burlingame, Quinn; Coburn, Caleb; Che, Xiaozhou; Panda, Anurag; Qu, Yue; Forrest, Stephen R.

2018-02-01

The unique properties of organic semiconductors, such as flexibility and lightness, are increasingly important for information displays, lighting and energy generation. But organics suffer from both static and dynamic disorder, and this can lead to variable-range carrier hopping, which results in notoriously poor electrical properties, with low electron and hole mobilities and correspondingly short charge-diffusion lengths of less than a micrometre. Here we demonstrate a photoactive (light-responsive) organic heterostructure comprising a thin fullerene channel sandwiched between an electron-blocking layer and a blended donor:C70 fullerene heterojunction that generates charges by dissociating excitons. Centimetre-scale diffusion of electrons is observed in the fullerene channel, and this can be fitted with a simple electron diffusion model. Our experiments enable the direct measurement of charge diffusivity in organic semiconductors, which is as high as 0.83 ± 0.07 square centimetres per second in a C60 channel at room temperature. The high diffusivity of the fullerene combined with the extraordinarily long charge-recombination time yields diffusion lengths of more than 3.5 centimetres, orders of magnitude larger than expected for an organic system.

Graphene-on-semiconductor substrates for analog electronics

DOEpatents

Lagally, Max G.; Cavallo, Francesca; Rojas-Delgado, Richard

2016-04-26

Electrically conductive material structures, analog electronic devices incorporating the structures and methods for making the structures are provided. The structures include a layer of graphene on a semiconductor substrate. The graphene layer and the substrate are separated by an interfacial region that promotes transfer of charge carriers from the surface of the substrate to the graphene.

Low temperature junction growth using hot-wire chemical vapor deposition

DOEpatents

Wang, Qi; Page, Matthew; Iwaniczko, Eugene; Wang, Tihu; Yan, Yanfa

2014-02-04

A system and a process for forming a semi-conductor device, and solar cells (10) formed thereby. The process includes preparing a substrate (12) for deposition of a junction layer (14); forming the junction layer (14) on the substrate (12) using hot wire chemical vapor deposition; and, finishing the semi-conductor device.

Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

DOEpatents

Fitzgerald, Jr., Eugene A.; Ast, Dieter G.

1992-01-01

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10.times. critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers

DOEpatents

Fitzgerald, Jr., Eugene A.; Ast, Dieter G.

1991-01-01

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10x critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

DOEpatents

Fitzgerald, E.A. Jr.; Ast, D.G.

1992-10-20

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10[times] critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In[sub 0.05]Ga[sub 0.95]As/(001)GaAs interface was controlled by fabricating 2-[mu]m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500 [angstrom] of In[sub 0.05]Ga[sub 0.95]As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-[mu]m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 [mu]m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density. 7 figs.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Surface breakdown igniter for mercury arc devices

DOEpatents

Bayless, John R.

1977-01-01

Surface breakdown igniter comprises a semiconductor of medium resistivity which has the arc device cathode as one electrode and has an igniter anode electrode so that when voltage is applied between the electrodes a spark is generated when electrical breakdown occurs over the surface of the semiconductor. The geometry of the igniter anode and cathode electrodes causes the igniter discharge to be forced away from the semiconductor surface.

Wholly Aromatic Ether-Imides as n-Type Semiconductors

NASA Technical Reports Server (NTRS)

Weiser, Erik; St. Clair, Terry L.; Dingemans, Theo J.; Samulski, Edward T.; Irene, Gene

2006-01-01

Some wholly aromatic ether-imides consisting of rod-shaped, relatively-low-mass molecules that can form liquid crystals have been investigated for potential utility as electron-donor-type (ntype) organic semiconductors. It is envisioned that after further research to improve understanding of their physical and chemical properties, compounds of this type would be used to make thin film semiconductor devices (e.g., photovoltaic cells and field-effect transistors) on flexible electronic-circuit substrates. This investigation was inspired by several prior developments: Poly(ether-imides) [PEIs] are a class of engineering plastics that have been used extensively in the form of films in a variety of electronic applications, including insulating layers, circuit boards, and low-permittivity coatings. Wholly aromatic PEIs containing naphthalene and perylene moieties have been shown to be useful as electrochromic polymers. More recently, low-molecular-weight imides comprising naphthalene-based molecules with terminal fluorinated tails were shown to be useful as n-type organic semiconductors in such devices as field-effect transistors and Schottky diodes. Poly(etherimide)s as structural resins have been extensively investigated at NASA Langley Research Center for over 30 years. More recently, the need for multi-functional materials has become increasingly important. This n-type semiconductor illustrates the scope of current work towards new families of PEIs that not only can be used as structural resins for carbon-fiber reinforced composites, but also can function as sensors. Such a multi-functional material would permit so-called in-situ health monitoring of composite structures during service. The work presented here demonstrates that parts of the PEI backbone can be used as an n-type semiconductor with such materials being sensitive to damage, temperature, stress, and pressure. In the near future, multi-functional or "smart" composite structures are envisioned to be able to communicate such important parameters to the flight crew and provide vital information with respect to the operational status of their aircraft.

Low resistance barrier layer for isolating, adhering, and passivating copper metal in semiconductor fabrication

DOEpatents

Weihs, Timothy P.; Barbee, Jr., Troy W.

2002-01-01

Cubic or metastable cubic refractory metal carbides act as barrier layers to isolate, adhere, and passivate copper in semiconductor fabrication. One or more barrier layers of the metal carbide are deposited in conjunction with copper metallizations to form a multilayer characterized by a cubic crystal structure with a strong (100) texture. Suitable barrier layer materials include refractory transition metal carbides such as vanadium carbide (VC), niobium carbide (NbC), tantalum carbide (TaC), chromium carbide (Cr.sub.3 C.sub.2), tungsten carbide (WC), and molybdenum carbide (MoC).

Megahertz organic/polymer diodes

DOEpatents

Katz, Howard Edan; Sun, Jia; Pal, Nath Bhola

2012-12-11

Featured is an organic/polymer diode having a first layer composed essentially of one of an organic semiconductor material or a polymeric semiconductor material and a second layer formed on the first layer and being electrically coupled to the first layer such that current flows through the layers in one direction when a voltage is applied in one direction. The second layer is essentially composed of a material whose characteristics and properties are such that when formed on the first layer, the diode is capable of high frequency rectifications on the order of megahertz rectifications such as for example rectifications at one of above 100KHz, 500KhZ, IMHz, or 10 MHz. In further embodiments, the layers are arranged so as to be exposed to atmosphere.

Surface and Interface Engineering of Organometallic and Two Dimensional Semiconductor

NASA Astrophysics Data System (ADS)

Park, Jun Hong

For over half a century, inorganic Si and III-V materials have led the modern semiconductor industry, expanding to logic transistor and optoelectronic applications. However, these inorganic materials have faced two different fundamental limitations, flexibility for wearable applications and scaling limitation as logic transistors. As a result, the organic and two dimensional have been studied intentionally for various fields. In the present dissertation, three different studies will be presented with followed order; (1) the chemical response of organic semiconductor in NO2 exposure. (2) The surface and stability of WSe2 in ambient air. (3) Deposition of dielectric on two dimensional materials using organometallic seeding layer. The organic molecules rely on the van der Waals interaction during growth of thin films, contrast to covalent bond inorganic semiconductors. Therefore, the morphology and electronic property at surface of organic semiconductor in micro scale is more sensitive to change in gaseous conditions. In addition, metal phthalocyanine, which is one of organic semiconductor materials, change their electronic property as reaction with gaseous analytes, suggesting as potential chemical sensing platforms. In the present part, the growth behavior of metal phthalocyanine and surface response to gaseous condition will be elucidated using scanning tunneling microscopy (STM). In second part, the surface of layered transition metal dichalcogenides and their chemical response to exposure ambient air will be investigated, using STM. Layered transition metal dichalcogenides (TMDs) have attracted widespread attention in the scientific community for electronic device applications because improved electrostatic gate control and suppression of short channel leakage resulted from their atomic thin body. To fabricate the transistor based on TMDs, TMDs should be exposed to ambient conditions, while the effect of air exposure has not been understood fully. In this part, the effect of ambient air on TMDs will be investigated and partial oxidation of TMDs. In the last part, uniform deposition of dielectric layers on 2D materials will be presented, employing organic seedling layer. Although 2D materials have been expected as next generation semiconductor platform, direct deposition of dielectric is still challenging and induces leakage current commonly, because inertness of their surface resulted from absent of dangling bond. Here, metal phthalocyanine monolayer (ML) is employed as seedling layers and the growth of atomic layer deposition (ALD) dielectric is investigated in each step using STM.

Design and fabrication of 6.1-.ANG. family semiconductor devices using semi-insulating A1Sb substrate

DOEpatents

Sherohman, John W [Livermore, CA; Coombs, III, Arthur W.; Yee, Jick Hong [Livermore, CA; Wu, Kuang Jen J [Cupertino, CA

2007-05-29

For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-.ANG. family heterostructure devices.

Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-07-09

A high efficiency amorphous silicon PIN semiconductor device having partially crystallized (microcrystalline) P and N layers is constructed by the sequential sputtering of N, I and P layers and at least one semi-transparent ohmic electrode. The method of construction produces a PIN device, exhibiting enhanced electrical and optical properties, improved physical integrity, and facilitates the preparation in a singular vacuum system and vacuum pump down procedure.

Tuneable photonic device including an array of metamaterial resonators

DOEpatents

Brener, Igal; Wanke, Michael; Benz, Alexander

2017-03-14

A photonic apparatus includes a metamaterial resonator array overlying and electromagnetically coupled to a vertically stacked plurality of quantum wells defined in a semiconductor body. An arrangement of electrical contact layers is provided for facilitating the application of a bias voltage across the quantum well stack. Those portions of the semiconductor body that lie between the electrical contact layers are conformed to provide an electrically conductive path between the contact layers and through the quantum well stack.

Apparatus and method of manufacture for an imager equipped with a cross-talk barrier

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2012-01-01

An imager apparatus and associated starting material are provided. In one embodiment, an imager is provided including a silicon layer of a first conductivity type acting as a junction anode. Such silicon layer is adapted to convert light to photoelectrons. Also included is a semiconductor well of a second conductivity type formed in the silicon layer for acting as a junction cathode. Still yet, a barrier is formed adjacent to the semiconductor well. In another embodiment, a starting material is provided including a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Also included is a second silicon layer disposed adjacent to the oxide layer opposite the first silicon layer. Such second silicon layer is further equipped with an associated passivation layer and/or barrier.

High Performance High Temperature Thermoelectric Composites with Metallic Inclusions

NASA Technical Reports Server (NTRS)

Firdosy, Samad A. (Inventor); Kaner, Richard B. (Inventor); Ma, James M. (Inventor); Fleurial, Jean-Pierre (Inventor); Star, Kurt (Inventor); Bux, Sabah K. (Inventor); Ravi, Vilupanur A. (Inventor)

2017-01-01

The present invention provides a composite thermoelectric material. The composite thermoelectric material can include a semiconductor material comprising a rare earth metal. The atomic percent of the rare earth metal in the semiconductor material can be at least about 20%. The composite thermoelectric material can further include a metal forming metallic inclusions distributed throughout the semiconductor material. The present invention also provides a method of forming this composite thermoelectric material.

Observation of turnover of spontaneous polarization in ferroelectric layer of pentacene/poly-(vinylidene-trifluoroethylene) double-layer capacitor under photo illumination by optical second-harmonic generation measurement

NASA Astrophysics Data System (ADS)

Shi, Zhemin; Taguchi, Dai; Manaka, Takaaki; Iwamoto, Mitsumasa

2016-04-01

The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial charging in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.

van der Waals epitaxial two-dimensional CdSxSe(1-x) semiconductor alloys with tunable-composition and application to flexible optoelectronics.

PubMed

Xia, Jing; Zhao, Yun-Xuan; Wang, Lei; Li, Xuan-Ze; Gu, Yi-Yi; Cheng, Hua-Qiu; Meng, Xiang-Min

2017-09-21

Despite the substantial progress in the development of two-dimensional (2D) materials from conventional layered crystals, it still remains particularly challenging to produce high-quality 2D non-layered semiconductor alloys which may bring in some unique properties and new functions. In this work, the synthesis of well-oriented 2D non-layered CdS x Se (1-x) semiconductor alloy flakes with tunable compositions and optical properties is established. Structural analysis reveals that the 2D non-layered alloys follow an incommensurate van der Waals epitaxial growth pattern. Photoluminescence measurements show that the 2D alloys have composition-dependent direct bandgaps with the emission peak varying from 1.8 eV to 2.3 eV, coinciding well with the density functional theory calculations. Furthermore, photodetectors based on the CdS x Se (1-x) flakes exhibit a high photoresponsivity of 703 A W -1 with an external quantum efficiency of 1.94 × 10 3 and a response time of 39 ms. Flexible devices fabricated on a thin mica substrate display good mechanical stability upon repeated bending. This work suggests a facile and general method to produce high-quality 2D non-layered semiconductor alloys for next-generation optoelectronic devices.

Device and method for luminescence enhancement by resonant energy transfer from an absorptive thin film

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akselrod, Gleb M.; Bawendi, Moungi G.; Bulovic, Vladimir

Disclosed are a device and a method for the design and fabrication of the device for enhancing the brightness of luminescent molecules, nanostructures, and thin films. The device includes a mirror, a dielectric medium or spacer, an absorptive layer, and a luminescent layer. The absorptive layer is a continuous thin film of a strongly absorbing organic or inorganic material. The luminescent layer may be a continuous luminescent thin film or an arrangement of isolated luminescent species, e.g., organic or metal-organic dye molecules, semiconductor quantum dots, or other semiconductor nanostructures, supported on top of the absorptive layer.

Suppression of planar defects in the molecular beam epitaxy of GaAs/ErAs/GaAs heterostructures

NASA Astrophysics Data System (ADS)

Crook, Adam M.; Nair, Hari P.; Ferrer, Domingo A.; Bank, Seth R.

2011-08-01

We present a growth method that overcomes the mismatch in rotational symmetry of ErAs and conventional III-V semiconductors, allowing for epitaxially integrated semimetal/semiconductor heterostructures. Transmission electron microscopy and reflection high-energy electron diffraction reveal defect-free overgrowth of ErAs layers, consisting of >2× the total amount of ErAs that can be embedded with conventional layer-by-layer growth methods. We utilize epitaxial ErAs nanoparticles, overgrown with GaAs, as a seed to grow full films of ErAs. Growth proceeds by diffusion of erbium atoms through the GaAs spacer, which remains registered to the underlying substrate, preventing planar defect formation during subsequent GaAs growth. This growth method is promising for metal/semiconductor heterostructures that serve as embedded Ohmic contacts to epitaxial layers and epitaxially integrated active plasmonic devices.

Conduit for high temperature transfer of molten semiconductor crystalline material

NASA Technical Reports Server (NTRS)

Fiegl, George (Inventor); Torbet, Walter (Inventor)

1983-01-01

A conduit for high temperature transfer of molten semiconductor crystalline material consists of a composite structure incorporating a quartz transfer tube as the innermost member, with an outer thermally insulating layer designed to serve the dual purposes of minimizing heat losses from the quartz tube and maintaining mechanical strength and rigidity of the conduit at the elevated temperatures encountered. The composite structure ensures that the molten semiconductor material only comes in contact with a material (quartz) with which it is compatible, while the outer layer structure reinforces the quartz tube, which becomes somewhat soft at molten semiconductor temperatures. To further aid in preventing cooling of the molten semiconductor, a distributed, electric resistance heater is in contact with the surface of the quartz tube over most of its length. The quartz tube has short end portions which extend through the surface of the semiconductor melt and which are lef bare of the thermal insulation. The heater is designed to provide an increased heat input per unit area in the region adjacent these end portions.

Highly Efficient Multilayer Thermoelectric Devices

NASA Technical Reports Server (NTRS)

Boufelfel, Ali

2006-01-01

Multilayer thermoelectric devices now at the prototype stage of development exhibit a combination of desirable characteristics, including high figures of merit and high performance/cost ratios. These devices are capable of producing temperature differences of the order of 50 K in operation at or near room temperature. A solvent-free batch process for mass production of these state-of-the-art thermoelectric devices has also been developed. Like prior thermoelectric devices, the present ones have commercial potential mainly by virtue of their utility as means of controlled cooling (and/or, in some cases, heating) of sensors, integrated circuits, and temperature-critical components of scientific instruments. The advantages of thermoelectric devices for such uses include no need for circulating working fluids through or within the devices, generation of little if any noise, and high reliability. The disadvantages of prior thermoelectric devices include high power consumption and relatively low coefficients of performance. The present development program was undertaken in the hope of reducing the magnitudes of the aforementioned disadvantages and, especially, obtaining higher figures of merit for operation at and near room temperature. Accomplishments of the program thus far include development of an algorithm to estimate the heat extracted by, and the maximum temperature drop produced by, a thermoelectric device; solution of the problem of exchange of heat between a thermoelectric cooler and a water-cooled copper block; retrofitting of a vacuum chamber for depositing materials by sputtering; design of masks; and fabrication of multilayer thermoelectric devices of two different designs, denoted I and II. For both the I and II designs, the thicknesses of layers are of the order of nanometers. In devices of design I, nonconsecutive semiconductor layers are electrically connected in series. Devices of design II contain superlattices comprising alternating electron-acceptor (p)-doped and electron-donor (n)-doped, nanometer- thick semiconductor layers.

Estimation of carrier mobility and charge behaviors of organic semiconductor films in metal-insulator-semiconductor diodes consisting of high-k oxide/organic semiconductor double layers

NASA Astrophysics Data System (ADS)

Chosei, Naoya; Itoh, Eiji

2018-02-01

We have comparatively studied the charge behaviors of organic semiconductor films based on charge extraction by linearly increasing voltage in a metal-insulator-semiconductor (MIS) diode structure (MIS-CELIV) and by classical capacitance-voltage measurement. The MIS-CELIV technique allows the selective measurement of electron and hole mobilities of n- and p-type organic films with thicknesses representative of those of actual devices. We used an anodic oxidized sputtered Ta or Hf electrode as a high-k layer, and it effectively blocked holes at the insulator/semiconductor interface. We estimated the hole mobilities of the polythiophene derivatives regioregular poly(3-hexylthiophene) (P3HT) and poly(3,3‧‧‧-didodecylquarterthiophene) (PQT-12) before and after heat treatment in the ITO/high-k/(thin polymer insulator)/semiconductor/MoO3/Ag device structure. The hole mobility of PQT-12 was improved from 1.1 × 10-5 to 2.1 × 10-5 cm2 V-1 s-1 by the heat treatment of the device at 100 °C for 30 min. An almost two orders of magnitude higher mobility was obtained in MIS diodes with P3HT as the p-type layer. We also determined the capacitance from the displacement current in MIS diodes at a relatively low-voltage sweep, and it corresponded well to the classical capacitance-voltage and frequency measurement results.

Epitaxial growth of CoO films on semiconductor and metal substrates by constructing a complex heterostructure

NASA Astrophysics Data System (ADS)

Entani, S.; Kiguchi, M.; Saiki, K.; Koma, A.

2003-01-01

Epitaxial growth of CoO films was studied using reflection high-energy electron diffraction (RHEED), electron energy loss spectroscopy (EELS), ultraviolet photoelectron spectroscopy (UPS) and Auger electron spectroscopy (AES). The RHEED results indicated that an epitaxial CoO film grew on semiconductor and metal substrates (CoO (0 0 1)∥GaAs (0 0 1), Cu (0 0 1), Ag (0 0 1) and [1 0 0]CoO∥[1 0 0] substrates) by constructing a complex heterostructure with two alkali halide buffer layers. The AES, EELS and UPS results showed that the grown CoO film had almost the same electronic structure as bulk CoO. We could show that use of alkali halide buffer layers was a good way to grow metal oxide films on semiconductor and metal substrates in an O 2 atmosphere. The alkali halide layers not only works as glue to connect very dissimilar materials but also prevents oxidation of metal and semiconductor substrates.

Photoelectrical Stimulation of Neuronal Cells by an Organic Semiconductor-Electrolyte Interface.

PubMed

Abdullaeva, Oliya S; Schulz, Matthias; Balzer, Frank; Parisi, Jürgen; Lützen, Arne; Dedek, Karin; Schiek, Manuela

2016-08-23

As a step toward the realization of neuroprosthetics for vision restoration, we follow an electrophysiological patch-clamp approach to study the fundamental photoelectrical stimulation mechanism of neuronal model cells by an organic semiconductor-electrolyte interface. Our photoactive layer consisting of an anilino-squaraine donor blended with a fullerene acceptor is supporting the growth of the neuronal model cell line (N2A cells) without an adhesion layer on it and is not impairing cell viability. The transient photocurrent signal upon illumination from the semiconductor-electrolyte layer is able to trigger a passive response of the neuronal cells under physiological conditions via a capacitive coupling mechanism. We study the dynamics of the capacitive transmembrane currents by patch-clamp recordings and compare them to the dynamics of the photocurrent signal and its spectral responsivity. Furthermore, we characterize the morphology of the semiconductor-electrolyte interface by atomic force microscopy and study the stability of the interface in dark and under illuminated conditions.

Current-voltage characteristics of organic semiconductors: Interfacial control between organic layers and electrodes

NASA Astrophysics Data System (ADS)

Kondo, Takeshi

2007-12-01

Current-voltage (I-V) characteristics of organic molecular glasses and solution processable materials embedded between two electrodes were studied to find materials possessing high charge-carrier mobilities and to design organic memory devices. The comparison studies between TOF, FET and SCLC measurements confirm the validity of using analyses of I-V characteristics to determine the mobility of organic semiconductors. Hexaazatrinaphthylene derivatives tri-substituted by electron withdrawing groups were characterized as potential electron transporting molecular glasses. The presence of two isomers has important implications for film morphology and effective mobility. The statistical isomer mixture of hexaazatrinaphthylene derivatized with pentafluoro-phenylmethyl ester is able to form amorphous films, and electron mobilities with the range of 10--2 cm2/Vs are observed in their I-V characteristics. Single-layer organic memory devices consisting of a polymer layer embedded between an Al electrode and ITO modified with Ag nanodots (Ag-NDs) prepared by a solution-based surface assembly demonstrated a potential capability as nonvolatile organic memory device with high ON/OFF switching ratios of 10 4. This level of performance could be achieved by modifying the ITO electrodes with some Ag-NDs that act as trapping sites, reducing the current in the OFF state. Based upon the observed electrical characteristics, the currents of the low-resistance state can be attributed to a tunneling through low-resistance pathways of metal particles originating from the metal top electrode in the organic layer and that the high-resistance state is controlled by charge trapping by the metal particles including Ag-NDs. In an alternative approach, complex films of AgNO3: hexaazatrinaphthylene derivatives were studied as the active layers for all-solution processed and air-stable organic memory devices. Rewritable memory effects were observed in the devices comprised of a thin polymer dielectric layer deposited on the bottom electrode, the complex film, and a conducting polymer film as the top electrode. The electrical characteristics indicate that the accumulation of Ag+ ions at the interface of the complex film and the top electrode may contribute to the switching effect.

Microscopic properties of ionic liquid/organic semiconductor interfaces revealed by molecular dynamics simulations.

PubMed

Yokota, Yasuyuki; Miyamoto, Hiroo; Imanishi, Akihito; Takeya, Jun; Inagaki, Kouji; Morikawa, Yoshitada; Fukui, Ken-Ichi

2018-05-09

Electric double-layer transistors based on ionic liquid/organic semiconductor interfaces have been extensively studied during the past decade because of their high carrier densities at low operation voltages. Microscopic structures and the dynamics of ionic liquids likely determine the device performance; however, knowledge of these is limited by a lack of appropriate experimental tools. In this study, we investigated ionic liquid/organic semiconductor interfaces using molecular dynamics to reveal the microscopic properties of ionic liquids. The organic semiconductors include pentacene, rubrene, fullerene, and 7,7,8,8-tetracyanoquinodimethane (TCNQ). While ionic liquids close to the substrate always form the specific layered structures, the surface properties of organic semiconductors drastically alter the ionic dynamics. Ionic liquids at the fullerene interface behave as a two-dimensional ionic crystal because of the energy gain derived from the favorable electrostatic interaction on the corrugated periodic substrate.

The role of ultra-thin SiO2 layers in metal-insulator-semiconductor (MIS) photoelectrochemical devices (Presentation Recording)

NASA Astrophysics Data System (ADS)

Esposito, Daniel V.

2015-08-01

Solid-state junctions based on a metal-insulator-semiconductor (MIS) architecture are of great interest for a number of optoelectronic applications such as photovoltaics, photoelectrochemical cells, and photodetection. One major advantage of the MIS junction compared to the closely related metal-semiconductor junction, or Schottky junction, is that the thin insulating layer (1-3 nm thick) that separates the metal and semiconductor can significantly reduce the density of undesirable interfacial mid-gap states. The reduction in mid-gap states helps "un-pin" the junction, allowing for significantly higher built-in-voltages to be achieved. A second major advantage of the MIS junction is that the thin insulating layer can also protect the underlying semiconductor from corrosion in an electrochemical environment, making the MIS architecture well-suited for application in (photo)electrochemical applications. In this presentation, discontinuous Si-based MIS junctions immersed in electrolyte are explored for use as i.) photoelectrodes for solar-water splitting in photoelectrochemical cells (PECs) and ii.) position-sensitive photodetectors. The development and optimization of MIS photoelectrodes for both of these applications relies heavily on understanding how processing of the thin SiO2 layer impacts the properties of nano- and micro-scale MIS junctions, as well as the interactions of the insulating layer with the electrolyte. In this work, we systematically explore the effects of insulator thickness, synthesis method, and chemical treatment on the photoelectrochemical and electrochemical properties of these MIS devices. It is shown that electrolyte-induced inversion plays a critical role in determining the charge carrier dynamics within the MIS photoelectrodes for both applications.

Improved method of preparing p-i-n junctions in amorphous silicon semiconductors

DOEpatents

Madan, A.

1984-12-10

A method of preparing p/sup +/-i-n/sup +/ junctions for amorphous silicon semiconductors includes depositing amorphous silicon on a thin layer of trivalent material, such as aluminum, indium, or gallium at a temperature in the range of 200/sup 0/C to 250/sup 0/C. At this temperature, the layer of trivalent material diffuses into the amorphous silicon to form a graded p/sup +/-i junction. A layer of n-type doped material is then deposited onto the intrinsic amorphous silicon layer in a conventional manner to finish forming the p/sup +/-i-n/sup +/ junction.

Release strategies for making transferable semiconductor structures, devices and device components

DOEpatents

Rogers, John A; Nuzzo, Ralph G; Meitl, Matthew; Ko, Heung Cho; Yoon, Jongseung; Menard, Etienne; Baca, Alfred J

2014-11-25

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Release strategies for making transferable semiconductor structures, devices and device components

DOEpatents

Rogers, John A [Champaign, IL; Nuzzo, Ralph G [Champaign, IL; Meitl, Matthew [Raleigh, NC; Ko, Heung Cho [Urbana, IL; Yoon, Jongseung [Urbana, IL; Menard, Etienne [Durham, NC; Baca, Alfred J [Urbana, IL

2011-04-26

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Novel nano-semiconductor film layer supported nano-Pd Complex Nanostructured Catalyst Pd/Ⓕ-MeOx/AC for High Efficient Selective Hydrogenation of Phenol to Cyclohexanone.

PubMed

Si, Jiaqi; Ouyang, Wenbing; Zhang, Yanji; Xu, Wentao; Zhou, Jicheng

2017-04-28

Supported metal as a type of heterogeneous catalysts are the most widely used in industrial processes. High dispersion of the metal particles of supported catalyst is a key factor in determining the performance of such catalysts. Here we report a novel catalyst Pd/Ⓕ-MeO x /AC with complex nanostructured, Pd nanoparticles supported on the platelike nano-semiconductor film/activated carbon, prepared by the photocatalytic reduction method, which exhibited high efficient catalytic performance for selective hydrogenation of phenol to cyclohexanone. Conversion of phenol achieved up to more than 99% with a lower mole ratio (0.5%) of active components Pd and phenol within 2 h at 70 °C. The synergistic effect of metal nanoparticles and nano-semiconductors support layer and the greatly increasing of contact interface of nano-metal-semiconductors may be responsible for the high efficiency. This work provides a clear demonstration that complex nanostructured catalysts with nano-metal and nano-semiconductor film layer supported on high specific surface AC can yield enhanced catalytic activity and can afford promising approach for developing new supported catalyst.

Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth

DOEpatents

Fan, John C. C.; Tsaur, Bor-Yeu; Gale, Ronald P.; Davis, Frances M.

1992-02-25

Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth

DOEpatents

Fan, John C. C.; Tsaur, Bor-Yeu; Gale, Ronald P.; Davis, Frances M.

1986-12-30

Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps

PubMed Central

Mei, Yaochuan; Diemer, Peter J.; Niazi, Muhammad R.; Hallani, Rawad K.; Jarolimek, Karol; Day, Cynthia S.; Risko, Chad; Anthony, John E.; Amassian, Aram

2017-01-01

The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms. PMID:28739934

Probing dynamic behavior of electric fields and band diagrams in complex semiconductor heterostructures

NASA Astrophysics Data System (ADS)

Turkulets, Yury; Shalish, Ilan

2018-01-01

Modern bandgap engineered electronic devices are typically made of multi-semiconductor multi-layer heterostructures that pose a major challenge to silicon-era characterization methods. As a result, contemporary bandgap engineering relies mostly on simulated band structures that are hardly ever verified experimentally. Here, we present a method that experimentally evaluates bandgap, band offsets, and electric fields, in complex multi-semiconductor layered structures, and it does so simultaneously in all the layers. The method uses a modest optical photocurrent spectroscopy setup at ambient conditions. The results are analyzed using a simple model for electro-absorption. As an example, we apply the method to a typical GaN high electron mobility transistor structure. Measurements under various external electric fields allow us to experimentally construct band diagrams, not only at equilibrium but also under any other working conditions of the device. The electric fields are then used to obtain the charge carrier density and mobility in the quantum well as a function of the gate voltage over the entire range of operating conditions of the device. The principles exemplified here may serve as guidelines for the development of methods for simultaneous characterization of all the layers in complex, multi-semiconductor structures.

Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps.

PubMed

Mei, Yaochuan; Diemer, Peter J; Niazi, Muhammad R; Hallani, Rawad K; Jarolimek, Karol; Day, Cynthia S; Risko, Chad; Anthony, John E; Amassian, Aram; Jurchescu, Oana D

2017-08-15

The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures.

PubMed

Chen, Ruei-San; Tang, Chih-Che; Shen, Wei-Chu; Huang, Ying-Sheng

2015-12-05

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal-semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 Ω(-) (1) cm(-) (1), with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2.

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

PubMed Central

Chen, Ruei-San; Tang, Chih-Che; Shen, Wei-Chu; Huang, Ying-Sheng

2015-01-01

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal–semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 Ω−1 cm−1, with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2. PMID:26710105

Transparent Oxide Thin-Film Transistors: Production, Characterization and Integration

NASA Astrophysics Data System (ADS)

Barquinha, Pedro Miguel Candido

This dissertation is devoted to the study of the emerging area of transparent electronics, summarizing research work regarding the development of n-type thin-film transistors (TFTs) based on sputtered oxide semiconductors. All the materials are produced without intentional substrate heating, with annealing temperatures of only 150-200 °C being used to optimize transistor performance. The work is based on the study and optimization of active semiconductors from the gallium-indium-zinc oxide system, including both the binary compounds Ga2O3, In2O3 and ZnO, as well as ternary and quaternary oxides based on mixtures of those, such as IZO and GIZO with different atomic ratios. Several topics are explored, including the study and optimization of the oxide semiconductor thin films, their application as channel layers on TFTs and finally the implementation of the optimized processes to fabricate active matrix backplanes to be integrated in liquid crystal display (LCD) prototypes. Sputtered amorphous dielectrics with high dielectric constant (high-kappa) based on mixtures of tantalum-silicon or tantalum-aluminum oxides are also studied and used as the dielectric layers on fully transparent TFTs. These devices also include transparent and highly conducting IZO thin films as source, drain and gate electrodes. Given the flexibility of the sputtering technique, oxide semiconductors are analyzed regarding several deposition parameters, such as oxygen partial pressure and deposition pressure, as well as target composition. One of the most interesting features of multicomponent oxides such as IZO and GIZO is that, due to their unique electronic configuration and carrier transport mechanism, they allow to obtain amorphous structures with remarkable electrical properties, such as high hall-effect mobility that exceeds 60 cm2 V -1 s-1 for IZO. These properties can be easily tuned by changing the processing conditions and the atomic ratios of the multicomponent oxides, allowing to have amorphous oxides suitable to be used either as transparent semiconductors or as highly conducting electrodes. The amorphous structure, which is maintained even if the thin films are annealed at 500 °C, brings great advantages concerning interface quality and uniformity in large areas. A complete study comprising different deposition conditions of the semiconductor layer is also made regarding TFT electrical performance. Optimized devices present outstanding electrical performance, such as field-effect mobility (muFE) exceeding 20 cm2 V -1 s-1, turn-on voltage (Von) between -1 and 1 V, subthreshold slope (S) lower than 0.25 V dec-1 and On-Off ratio above 107 . Devices employing amorphous multicomponent oxides present largely improved properties when compared with the ones based on polycrystalline ZnO, mostly in terms of muFE. Within the compositional range where IZO and GIZO films are amorphous, TFT performance can be largely adjusted: for instance, high indium contents favor large mu FE but also highly negative Von, which can be compensated by proper amounts of zinc and gallium. Large oxygen concentrations during oxide semiconductor sputtering are found to be deleterious, decreasing muFE, shifting Von towards high values and turning the devices electrically unstable. It is also shown that semiconductor thickness (ds) has a very important role: for instance, by reducing ds to 10 nm it is possible to produce TFTs with Von≈0 V even using deposition conditions and/or target compositions that normally yield highly conducting films. Given the low ds of the films, this behavior is mostly related with surface states existent at the oxide semiconductor air-exposed back-surface, where depletion layers that can extend towards the dielectric/semiconductor interface are created due to the interaction with atmospheric oxygen. Different passivation layers on top of this air-exposed surface are studied, with SU-8 revealing to be to most effective one. Other important topics are source-drain contact resistance assessment and the effect of different annealing temperatures ( TA), being the properties of the TFTs dominated by TA rather than by the deposition conditions as TA increases. Fully transparent TFTs employing sputtered amorphous multicomponent dielectrics produced without intentional substrate heating present excellent electrical properties, that approach those exhibited by devices using PECVD SiO2 produced at 400 °C. Gate leakage current can be greatly reduced by using tantalum-silicon or tantalum-aluminum oxides rather than Ta2O5. A section of this dissertation is also devoted to the analysis of current stress stability and aging effects of the TFTs, being found that optimal devices exhibit recoverable threshold voltage shifts lower than 0.50 V after 24 h stress with constant drain current of 10 muA, as well as negligible aging effects during 18 months. The research work of this dissertation culminates in the fabrication of a backplane employing transparent TFTs and subsequent integration with a LCD frontplane by Hewlett-Packard. The successful operation of this initial 2.8h prototype with 128x128 pixels provides a solid demonstration that oxide semiconductor-based TFTs have the potential to largely contribute to a novel electronics era, where semiconductor materials away from conventional silicon are used to create fascinating applications, such as transparent electronic products.

Plasma Reflection in Multigrain Layers of Narrow-Bandgap Semiconductors

NASA Astrophysics Data System (ADS)

Zhukov, N. D.; Shishkin, M. I.; Rokakh, A. G.

2018-04-01

Qualitatively similar spectral characteristics of plasma-resonance reflection in the region of 15-25 μm were obtained for layers of electrodeposited submicron particles of InSb, InAs, and GaAs and plates of these semiconductors ground with M1-grade diamond powder. The most narrow-bandgap semiconductor InSb (intrinsic absorption edge ˜7 μm) is characterized by an absorption band at 2.1-2.3 μm, which is interpreted in terms of the model of optical excitation of electrons coupled by the Coulomb interaction. The spectra of a multigrain layer of chemically deposited PbS nanoparticles (50-70 nm) exhibited absorption maxima at 7, 10, and 17 μm, which can be explained by electron transitions obeying the energy-quantization rules for quantum dots.

Metal-Insulator-Semiconductor Diode Consisting of Two-Dimensional Nanomaterials.

PubMed

Jeong, Hyun; Oh, Hye Min; Bang, Seungho; Jeong, Hyeon Jun; An, Sung-Jin; Han, Gang Hee; Kim, Hyun; Yun, Seok Joon; Kim, Ki Kang; Park, Jin Cheol; Lee, Young Hee; Lerondel, Gilles; Jeong, Mun Seok

2016-03-09

We present a novel metal-insulator-semiconductor (MIS) diode consisting of graphene, hexagonal BN, and monolayer MoS2 for application in ultrathin nanoelectronics. The MIS heterojunction structure was fabricated by vertically stacking layered materials using a simple wet chemical transfer method. The stacking of each layer was confirmed by confocal scanning Raman spectroscopy and device performance was evaluated using current versus voltage (I-V) and photocurrent measurements. We clearly observed better current rectification and much higher current flow in the MIS diode than in the p-n junction and the metal-semiconductor diodes made of layered materials. The I-V characteristic curve of the MIS diode indicates that current flows mainly across interfaces as a result of carrier tunneling. Moreover, we observed considerably high photocurrent from the MIS diode under visible light illumination.

37 CFR 211.5 - Deposit of identifying material.

Code of Federal Regulations, 2011 CFR

2011-07-01

... fixed in the form of the semiconductor chip product in which it was first commercially exploited... photograph of each layer of the work fixed in a semiconductor chip product. The visually perceptible... complete form of the mask work as fixed in a semiconductor product. (ii) Where the mask work contribution...

Improved Stability and Performance of Visible Photoelectrochemical Water Splitting on Solution-Processed Organic Semiconductor Thin Films by Ultrathin Metal Oxide Passivation

DOE PAGES

Wang, Lei; Yan, Danhua; Shaffer, David W.; ...

2017-12-27

Solution-processable organic semiconductors have potentials as visible photoelectrochemical (PEC) water splitting photoelectrodes due to their tunable small band gap and electronic energy levels, but they are typically limited by poor stability and photocatalytic activity. In this study, we demonstrate the direct visible PEC water oxidation on solution-processed organic semiconductor thin films with improved stability and performance by ultrathin metal oxide passivation layers. N-type fullerene-derivative thin films passivated by sub-2 nm ZnO via atomic layer deposition enabled the visible PEC water oxidation at wavelengths longer than 600 nm in harsh alkaline electrolyte environments with up to 30 μA/cm 2 photocurrents atmore » the thermodynamic water-oxidation equilibrium potential and the photoanode half-lifetime extended to ~1000 s. The systematic investigation reveals the enhanced water oxidation catalytic activity afforded by ZnO passivation and the charge tunneling governing the hole transfer through passivation layers. Further enhanced PEC performances were realized by improving the bottom ohmic contact to the organic semiconductor, achieving ~60 μA/cm 2 water oxidation photocurrent at the equilibrium potential, the highest values reported for organic semiconductor thin films to our knowledge. The improved stability and performance of passivated organic photoelectrodes and discovered design rationales provide useful guidelines for realizing the stable visible solar PEC water splitting based on organic semiconductor thin films.« less

Improved Stability and Performance of Visible Photoelectrochemical Water Splitting on Solution-Processed Organic Semiconductor Thin Films by Ultrathin Metal Oxide Passivation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Lei; Yan, Danhua; Shaffer, David W.

Solution-processable organic semiconductors have potentials as visible photoelectrochemical (PEC) water splitting photoelectrodes due to their tunable small band gap and electronic energy levels, but they are typically limited by poor stability and photocatalytic activity. In this study, we demonstrate the direct visible PEC water oxidation on solution-processed organic semiconductor thin films with improved stability and performance by ultrathin metal oxide passivation layers. N-type fullerene-derivative thin films passivated by sub-2 nm ZnO via atomic layer deposition enabled the visible PEC water oxidation at wavelengths longer than 600 nm in harsh alkaline electrolyte environments with up to 30 μA/cm 2 photocurrents atmore » the thermodynamic water-oxidation equilibrium potential and the photoanode half-lifetime extended to ~1000 s. The systematic investigation reveals the enhanced water oxidation catalytic activity afforded by ZnO passivation and the charge tunneling governing the hole transfer through passivation layers. Further enhanced PEC performances were realized by improving the bottom ohmic contact to the organic semiconductor, achieving ~60 μA/cm 2 water oxidation photocurrent at the equilibrium potential, the highest values reported for organic semiconductor thin films to our knowledge. The improved stability and performance of passivated organic photoelectrodes and discovered design rationales provide useful guidelines for realizing the stable visible solar PEC water splitting based on organic semiconductor thin films.« less

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Jr., Marcel; Alivisatos, Paul

2006-09-05

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule. The compound is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. subsequent exposure to excitation energy will excite the semiconductor nanocrystal in the probe causing the emission of electromagnetic radiation. Further described are processes for respectively: making the luminescent semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon [Pinole, CA; Bruchez, Jr., Marcel; Alivisatos, Paul [Oakland, CA

2004-03-02

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule. The compound is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. Subsequent exposure to excitation energy will excite the semiconductor nanocrystal in the probe, causing the emission of electromagnetic radiation. Further described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Jr., Marcel; Alivisatos, Paul

2005-08-09

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule. The compound is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. Subsequent exposure to excitation energy will excite the semiconductor nanocrystal in the probe causing the emission of electromagnetic radiation. Further described are processes for respectively: making the luminescent semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Jr., Marcel; Alivisatos, Paul

2002-01-01

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affity molecule. The compound is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. Subsequent exposure to excitation energy will excite the semiconductor nanocrystal in he probe, causing the emission of electromagnetic radiation. Further described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Marcel; Alivisatos, Paul

2014-01-28

A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with one or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe.

Semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Weiss, Shimon; Bruchez, Marcel; Alivisatos, Paul A.

2016-12-27

A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with onemore » or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe.« less

Influence of the Compositional Grading on Concentration of Majority Charge Carriers in Near-Surface Layers of n(p)-HgCdTe Grown by Molecular Beam Epitaxy

NASA Astrophysics Data System (ADS)

Voitsekhovskii, A. V.; Nesmelov, S. N.; Dzyadukh, S. M.

2018-02-01

The capacitive characteristics of metal-insulator-semiconductor (MIS) structures based on the compositionally graded Hg1-xCdxTe created by molecular beam epitaxy have been experimentally investigated in a wide temperature range (8-77 K). A program has been developed for numerical simulation of ideal capacitance-voltage (C-V) characteristics in the low-frequency and high-frequency approximations. The concentrations of the majority carriers in the near-surface semiconductor layer are determined from the values of the capacitances in the minima of low-frequency C-V curves. For MIS structures based on p-Hg1-xCdxTe, the effect of the presence of the compositionally graded layer on the hole concentration in the near-surface semiconductor layer, determined from capacitive measurements, has not been established. Perhaps this is due to the fact that the concentration of holes in the near-surface layer largely depends on the type of dielectric coating and the regimes of its application. For MIS structures based on n-Hg1-x Cd x Te (x = 0.22-0.23) without a graded-gap layer, the electron concentration determined by the proposed method is close to the average concentration determined by the Hall measurements. The electron concentration in the near-surface semiconductor layer of the compositionally graded n-Hg1-x Cd x Te (x = 0.22-0.23) found from the minimum capacitance value is much higher than the average electron concentration determined by the Hall measurements. The results are qualitatively explained by the creation of additional intrinsic donor-type defects in the near-surface compositionally graded layer of n-Hg1-x Cd x Te.

Nanostructured materials for hydrogen storage

DOEpatents

Williamson, Andrew J.; Reboredo, Fernando A.

2007-12-04

A system for hydrogen storage comprising a porous nano-structured material with hydrogen absorbed on the surfaces of the porous nano-structured material. The system of hydrogen storage comprises absorbing hydrogen on the surfaces of a porous nano-structured semiconductor material.

Fast optical detecting media based on semiconductor nanostructures for recording images obtained using charges of free photocarriers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kasherininov, P. G., E-mail: peter.kasherininov@mail.ioffe.ru; Tomasov, A. A.; Beregulin, E. V.

2011-01-15

Available published data on the properties of optical recording media based on semiconductor structures are reviewed. The principles of operation, structure, parameters, and the range of application for optical recording media based on MIS structures formed of photorefractive crystals with a thick layer of insulator and MIS structures with a liquid crystal as the insulator (the MIS LC modulators), as well as the effect of optical bistability in semiconductor structures (semiconductor MIS structures with nanodimensionally thin insulator (TI) layer, M(TI)S nanostructures). Special attention is paid to recording media based on the M(TI)S nanostructures promising for fast processing of highly informativemore » images and to fabrication of optoelectronic correlators of images for noncoherent light.« less

Low temperature thin films formed from nanocrystal precursors

DOEpatents

Alivisatos, A. Paul; Goldstein, Avery N.

1993-01-01

Nanocrystals of semiconductor compounds are produced. When they are applied as a contiguous layer onto a substrate and heated they fuse into a continuous layer at temperatures as much as 250, 500, 750 or even 1000.degree. K below their bulk melting point. This allows continuous semiconductor films in the 0.25 to 25 nm thickness range to be formed with minimal thermal exposure.

Low temperature thin films formed from nanocrystal precursors

DOEpatents

Alivisatos, A.P.; Goldstein, A.N.

1993-11-16

Nanocrystals of semiconductor compounds are produced. When they are applied as a contiguous layer onto a substrate and heated they fuse into a continuous layer at temperatures as much as 250, 500, 750 or even 1000 K below their bulk melting point. This allows continuous semiconductor films in the 0.25 to 25 nm thickness range to be formed with minimal thermal exposure. 9 figures.

Doping-Induced Interband Gain in InAs/AlSb Quantum Wells

NASA Technical Reports Server (NTRS)

Kolokolov, K. I.; Ning, C. Z.

2005-01-01

A paper describes a computational study of effects of doping in a quantum well (QW) comprising a 10-nm-thick layer of InAs sandwiched between two 21-nm-thick AlSb layers. Heretofore, InAs/AlSb QWs have not been useful as interband gain devices because they have type-II energy-band-edge alignment, which causes spatial separation of electrons and holes, thereby leading to weak interband dipole matrix elements. In the doping schemes studied, an interior sublayer of each AlSb layer was doped at various total areal densities up to 5 X 10(exp 12) / square cm. It was found that (1) proper doping converts the InAs layer from a barrier to a well for holes, thereby converting the heterostructure from type II to type I; (2) the resultant dipole matrix elements and interband gains are comparable to those of typical type-I heterostructures; and (3) dipole moments and optical gain increase with the doping level. Optical gains in the transverse magnetic mode can be almost ten times those of other semiconductor material systems in devices used to generate medium-wavelength infrared (MWIR) radiation. Hence, doped InAs/AlSb QWs could be the basis of an alternative material system for devices to generate MWIR radiation.

Tuning the Performance of Organic Spintronic Devices Using X-Ray Generated Traps

DTIC Science & Technology

2012-08-16

observed in organic devices using the same organic semiconductor, namely tris(8-hydroxyquinoli- nato)aluminium ( Alq3 ) [5,15]. Here we will show that the...manufacturing steps were carried out in a deposition chamber located inside a nitrogen glovebox. Next, the organic layer Alq3 (70 to 100 nm) followed by the...As the organic semiconductor spacer layer, the Alq3 layer was fabricated by thermal evaporation in a vacuum of 10Ś mbar at a rate of 0:1 nm=s. The Fe

Photo-voltaic power generating means and methods

DOEpatents

Kroger, Ferdinand A.; Rod, Robert L.; Panicker, M. P. Ramachandra

1983-08-23

A photo-voltaic power cell based on a photoelectric semiconductor compound and the method of using and making the same. The semiconductor compound in the photo-voltaic power cell of the present invention can be electrolytically formed at a cathode in an electrolytic solution by causing discharge or decomposition of ions or molecules of a non-metallic component with deposition of the non-metallic component on the cathode and simultaneously providing ions of a metal component which discharge and combine with the non-metallic component at the cathode thereby forming the semiconductor compound film material thereon. By stoichiometrically adjusting the amounts of the components, or otherwise by introducing dopants into the desired amounts, an N-type layer can be formed and thereafter a P-type layer can be formed with a junction therebetween. The invention is effective in producing homojunction semiconductor materials and heterojunction semiconductor materials. The present invention also provides a method of using three electrodes in order to form the semiconductor compound material on one of these electrodes. Various examples are given for manufacturing different photo-voltaic cells in accordance with the present invention.

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Photo-voltaic power generating means and methods

DOEpatents

Kroger, Ferdinand A.; Rod, Robert L.; Panicker, Ramachandra M. P.; Knaster, Mark B.

1984-01-10

A photo-voltaic power cell based on a photoelectric semiconductor compound and the method of using and making the same. The semiconductor compound in the photo-voltaic power cell of the present invention can be electrolytically formed at a cathode in an electrolytic solution by causing discharge or decomposition of ions or molecules of a non-metallic component with deposition of the non-metallic component on the cathode and simultaneously providing ions of a metal component which discharge and combine with the non-metallic component at the cathode thereby forming the semiconductor compound film material thereon. By stoichiometrically adjusting the amounts of the components, or otherwise by introducing dopants into the desired amounts, an N-type layer can be formed and thereafter a P-type layer can be formed with a junction therebetween. The invention is effective in producing homojunction semiconductor materials and heterojunction semiconductor materials. The present invention also provides a method of using three electrodes in order to form the semiconductor compound material on one of these electrodes. Various examples are given for manufacturing different photo-voltaic cells in accordance with the present invention.

Time-Resolved Photoluminescence Microscopy for the Analysis of Semiconductor-Based Paint Layers

PubMed Central

Mosca, Sara; Gonzalez, Victor; Eveno, Myriam

2017-01-01

In conservation, science semiconductors occur as the constituent matter of the so-called semiconductor pigments, produced following the Industrial Revolution and extensively used by modern painters. With recent research highlighting the occurrence of various degradation phenomena in semiconductor paints, it is clear that their detection by conventional optical fluorescence imaging and microscopy is limited by the complexity of historical painting materials. Here, we illustrate and prove the capabilities of time-resolved photoluminescence (TRPL) microscopy, equipped with both spectral and lifetime sensitivity at timescales ranging from nanoseconds to hundreds of microseconds, for the analysis of cross-sections of paint layers made of luminescent semiconductor pigments. The method is sensitive to heterogeneities within micro-samples and provides valuable information for the interpretation of the nature of the emissions in samples. A case study is presented on micro samples from a painting by Henri Matisse and serves to demonstrate how TRPL can be used to identify the semiconductor pigments zinc white and cadmium yellow, and to inform future investigations of the degradation of a cadmium yellow paint. PMID:29160862

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chianelli, Russell R.; Castillo, Karina; Gupta, Vipin

Photovoltaic devices and methods of making the same, are disclosed herein. The cell comprises a photovoltaic device that comprises a first electrically conductive layer comprising a photo-sensitized electrode; at least one photoelectrochemical layer comprising metal-oxide particles, an electrolyte solution comprising at least one asphaltene fraction, wherein the metal-oxide particles are optionally dispersed in a surfactant; and a second electrically conductive layer comprising a counter-electrode, wherein the second electrically conductive layer comprises one or more conductive elements comprising carbon, graphite, soot, carbon allotropes or any combinations thereof.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Semiconductor cylinder fiber laser

NASA Astrophysics Data System (ADS)

Sandupatla, Abhinay; Flattery, James; Kornreich, Philipp

2015-12-01

We fabricated a fiber laser that uses a thin semiconductor layer surrounding the glass core as the gain medium. This is a completely new type of laser. The In2Te3 semiconductor layer is about 15-nm thick. The fiber laser has a core diameter of 14.2 μm, an outside diameter of 126 μm, and it is 25-mm long. The laser mirrors consist of a thick vacuum-deposited aluminum layer at one end and a thin semitransparent aluminum layer deposited at the other end of the fiber. The laser is pumped from the side with either light from a halogen tungsten incandescent lamp or a blue light emitting diode flash light. Both the In2Te3 gain medium and the aluminum mirrors have a wide bandwidth. Therefore, the output spectrum consists of a pedestal from a wavelength of about 454 to 623 nm with several peaks. There is a main peak at 545 nm. The main peak has an amplitude of 16.5 dB above the noise level of -73 dB.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

PubMed Central

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

Apparatus and methods for memory using in-plane polarization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Junwei; Chang, Kai; Ji, Shuai-Hua

A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process ismore » non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.« less

Metal-oxide-semiconductor devices using Ga2O3 dielectrics on n-type GaN

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Chen, Hong-Wei; Lee, Hsin-Ying

2003-06-01

Using a photoelectrochemical method involving a He-Cd laser, Ga2O3 oxide layers were directly grown on n-type GaN. We demonstrated the performance of the resultant metal-oxide-semiconductor devices based on the grown Ga2O3 layer. An extremely low reverse leakage current of 200 pA was achieved when devices operated at -20 V. Furthermore, high forward and reverse breakdown electric fields of 2.80 MV/cm and 5.70 MV/cm, respectively, were obtained. Using a photoassisted current-voltage method, a low interface state density of 2.53×1011 cm-2 eV-1 was estimated. The varactor devices permit formation of inversion layers, so that they may be applied for the fabrication of metal-oxide-semiconductor field-effect transistors.

Prediction of weak topological insulators in layered semiconductors.

PubMed

Yan, Binghai; Müchler, Lukas; Felser, Claudia

2012-09-14

We report the discovery of weak topological insulators by ab initio calculations in a honeycomb lattice. We propose a structure with an odd number of layers in the primitive unit cell as a prerequisite for forming weak topological insulators. Here, the single-layered KHgSb is the most suitable candidate for its large bulk energy gap of 0.24 eV. Its side surface hosts metallic surface states, forming two anisotropic Dirac cones. Although the stacking of even-layered structures leads to trivial insulators, the structures can host a quantum spin Hall layer with a large bulk gap, if an additional single layer exists as a stacking fault in the crystal. The reported honeycomb compounds can serve as prototypes to aid in the finding of new weak topological insulators in layered small-gap semiconductors.

Ultrafast and Ultrasensitive Gas Sensors Derived from a Large Fermi-Level Shift in the Schottky Junction with Sieve-Layer Modulation.

PubMed

Cheng, Ching-Cheng; Wu, Chia-Lin; Liao, Yu-Ming; Chen, Yang-Fang

2016-07-13

Gas sensors play an important role in numerous fields, covering a wide range of applications, including intelligent systems and detection of harmful and toxic gases. Even though they have attracted much attention, the response time on the order of seconds to minutes is still very slow. To circumvent the existing problems, here, we provide a seminal attempt with the integration of graphene, semiconductor, and an addition sieve layer forming a nanocomposite gas sensor with ultrahigh sensitivity and ultrafast response. The designed sieve layer has a suitable band structure that can serve as a blocking layer to prevent transfer of the charges induced by adsorbed gas molecules into the underlying semiconductor layer. We found that the sensitivity can be reduced to the parts per million level, and the ultrafast response of around 60 ms is unprecedented compared with published graphene-based gas sensors. The achieved high performance can be interpreted well by the large change of the Fermi level of graphene due to its inherent nature of the low density of states and blocking of the sieve layer to prevent charge transfer from graphene to the underlying semiconductor layer. Accordingly, our work is very useful and timely for the development of gas sensors with high performance for practical applications.

Giant Dirac point shift of graphene phototransistors by doped silicon substrate current

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shimatani, Masaaki; Ogawa, Shinpei, E-mail: Ogawa.Shimpei@eb.MitsubishiElectric.co.jp; Fujisawa, Daisuke

2016-03-15

Graphene is a promising new material for photodetectors due to its excellent optical properties and high-speed response. However, graphene-based phototransistors have low responsivity due to the weak light absorption of graphene. We have observed a giant Dirac point shift upon white light illumination in graphene-based phototransistors with n-doped Si substrates, but not those with p-doped substrates. The source-drain current and substrate current were investigated with and without illumination for both p-type and n-type Si substrates. The decay time of the drain-source current indicates that the Si substrate, SiO{sub 2} layer, and metal electrode comprise a metal-oxide-semiconductor (MOS) capacitor due tomore » the presence of defects at the interface between the Si substrate and SiO{sub 2} layer. The difference in the diffusion time of the intrinsic major carriers (electrons) and the photogenerated electron-hole pairs to the depletion layer delays the application of the gate voltage to the graphene channel. Therefore, the giant Dirac point shift is attributed to the n-type Si substrate current. This phenomenon can be exploited to realize high-performance graphene-based phototransistors.« less

Method and apparatus for increasing the durability and yield of thin film photovoltaic devices

DOEpatents

Phillips, J.E.; Lasswell, P.G.

1987-02-03

Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device. 10 figs.

Method and apparatus for increasing the durability and yield of thin film photovoltaic devices

DOEpatents

Phillips, James E.; Lasswell, Patrick G.

1987-01-01

Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device.

Investigations on Substrate Temperature-Induced Growth Modes of Organic Semiconductors at Dielectric/semiconductor Interface and Their Correlation with Threshold Voltage Stability in Organic Field-Effect Transistors.

PubMed

Padma, Narayanan; Maheshwari, Priya; Bhattacharya, Debarati; Tokas, Raj B; Sen, Shashwati; Honda, Yoshihide; Basu, Saibal; Pujari, Pradeep Kumar; Rao, T V Chandrasekhar

2016-02-10

Influence of substrate temperature on growth modes of copper phthalocyanine (CuPc) thin films at the dielectric/semiconductor interface in organic field effect transistors (OFETs) is investigated. Atomic force microscopy (AFM) imaging at the interface reveals a change from 'layer+island' to "island" growth mode with increasing substrate temperatures, further confirmed by probing the buried interfaces using X-ray reflectivity (XRR) and positron annihilation spectroscopic (PAS) techniques. PAS depth profiling provides insight into the details of molecular ordering while positron lifetime measurements reveal the difference in packing modes of CuPc molecules at the interface. XRR measurements show systematic increase in interface width and electron density correlating well with the change from layer + island to coalesced huge 3D islands at higher substrate temperatures. Study demonstrates the usefulness of XRR and PAS techniques to study growth modes at buried interfaces and reveals the influence of growth modes of semiconductor at the interface on hole and electron trap concentrations individually, thereby affecting hysteresis and threshold voltage stability. Minimum hole trapping is correlated to near layer by layer formation close to the interface at 100 °C and maximum to the island formation with large voids between the grains at 225 °C.

Pump-probe surface photovoltage spectroscopy measurements on semiconductor epitaxial layers.

PubMed

Jana, Dipankar; Porwal, S; Sharma, T K; Kumar, Shailendra; Oak, S M

2014-04-01

Pump-probe Surface Photovoltage Spectroscopy (SPS) measurements are performed on semiconductor epitaxial layers. Here, an additional sub-bandgap cw pump laser beam is used in a conventional chopped light geometry SPS setup under the pump-probe configuration. The main role of pump laser beam is to saturate the sub-bandgap localized states whose contribution otherwise swamp the information related to the bandgap of material. It also affects the magnitude of Dember voltage in case of semi-insulating (SI) semiconductor substrates. Pump-probe SPS technique enables an accurate determination of the bandgap of semiconductor epitaxial layers even under the strong influence of localized sub-bandgap states. The pump beam is found to be very effective in suppressing the effect of surface/interface and bulk trap states. The overall magnitude of SPV signal is decided by the dependence of charge separation mechanisms on the intensity of the pump beam. On the contrary, an above bandgap cw pump laser can be used to distinguish the signatures of sub-bandgap states by suppressing the band edge related feature. Usefulness of the pump-probe SPS technique is established by unambiguously determining the bandgap of p-GaAs epitaxial layers grown on SI-GaAs substrates, SI-InP wafers, and p-GaN epilayers grown on Sapphire substrates.

The AMOS cell - An improved metal-semiconductor solar cell. [Antireflection coated Metal Oxide Semiconductor

NASA Technical Reports Server (NTRS)

Stirn, R. J.; Yeh, Y.-C. M.

1975-01-01

A new fabrication process is being developed which significantly improves the efficiency of metal-semiconductor solar cells. The resultant effect, a marked increase in the open-circuit voltage, is produced by the addition of an interfacial layer oxide on the semiconductor. Cells using gold on n-type gallium arsenide have been made in small areas (0.17 sq cm) with conversion efficiencies of 15% in terrestrial sunlight.

Materials Science and Device Physics of 2-Dimensional Semiconductors

NASA Astrophysics Data System (ADS)

Fang, Hui

Materials and device innovations are the keys to future technology revolution. For MOSFET scaling in particular, semiconductors with ultra-thin thickness on insulator platform is currently of great interest, due to the potential of integrating excellent channel materials with the industrially mature Si processing. Meanwhile, ultra-thin thickness also induces strong quantum confinement which in turn affect most of the material properties of these 2-dimensional (2-D) semiconductors, providing unprecedented opportunities for emerging technologies. In this thesis, multiple novel 2-D material systems are explored. Chapter one introduces the present challenges faced by MOSFET scaling. Chapter two covers the integration of ultrathin III V membranes with Si. Free standing ultrathin III-V is studied to enable high performance III-V on Si MOSFETs with strain engineering and alloying. Chapter three studies the light absorption in 2-D membranes. Experimental results and theoretical analysis reveal that light absorption in the 2-D quantum membranes is quantized into a fundamental physical constant, where we call it the quantum unit of light absorption, irrelevant of most of the material dependent parameters. Chapter four starts to focus on another 2-D system, atomic thin layered chalcogenides. Single and few layered chalcogenides are first explored as channel materials, with focuses in engineering the contacts for high performance MOSFETs. Contact treatment by molecular doping methods reveals that many layered chalcogenides other than MoS2 exhibit good transport properties at single layer limit. Finally, Chapter five investigated 2-D van der Waals heterostructures built from different single layer chalcogenides. The investigation in a WSe2/MoS2 hetero-bilayer shows a large Stokes like shift between photoluminescence peak and lowest absorption peak, as well as strong photoluminescence intensity, consistent with spatially indirect transition in a type II band alignment in this van der Waals heterostructure. This result enables new family of semiconductor heterostructures having tunable optoelectronic properties with customized composite layers and highlights the ability to build van der Waals semiconductor heterostructure lasers/LEDs.

Method of making organic light emitting devices

DOEpatents

Shiang, Joseph John [Niskayuna, NY; Janora, Kevin Henry [Schenectady, NY; Parthasarathy, Gautam [Saratoga Springs, NY; Cella, James Anthony [Clifton Park, NY; Chichak, Kelly Scott [Clifton Park, NY

2011-03-22

The present invention provides a method for the preparation of organic light-emitting devices comprising a bilayer structure made by forming a first film layer comprising an electroactive material and an INP precursor material, and exposing the first film layer to a radiation source under an inert atmosphere to generate an interpenetrating network polymer composition comprising the electroactive material. At least one additional layer is disposed on the reacted first film layer to complete the bilayer structure. The bilayer structure is comprised within an organic light-emitting device comprising standard features such as electrodes and optionally one or more additional layers serving as a bipolar emission layer, a hole injection layer, an electron injection layer, an electron transport layer, a hole transport layer, exciton-hole transporting layer, exciton-electron transporting layer, a hole transporting emission layer, or an electron transporting emission layer.

Optical systems fabricated by printing-based assembly

DOEpatents

Rogers, John; Nuzzo, Ralph; Meitl, Matthew; Menard, Etienne; Baca, Alfred J; Motala, Michael; Ahn, Jong-Hyun; Park, Sang-Il; Yu, Chang-Jae; Ko, Heung Cho; Stoykovich, Mark; Yoon, Jongseung

2014-05-13

Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

Optical systems fabricated by printing-based assembly

DOEpatents

Rogers, John [Champaign, IL; Nuzzo, Ralph [Champaign, IL; Meitl, Matthew [Durham, NC; Menard, Etienne [Durham, NC; Baca, Alfred J [Urbana, IL; Motala, Michael [Champaign, IL; Ahn, Jong-Hyun [Suwon, KR; Park, Sang-II [Savoy, IL; Yu,; Chang-Jae, [Urbana, IL; Ko, Heung-Cho [Gwangju, KR; Stoykovich,; Mark, [Dover, NH; Yoon, Jongseung [Urbana, IL

2011-07-05

Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

Optical systems fabricated by printing-based assembly

DOEpatents

Rogers, John; Nuzzo, Ralph; Meitl, Matthew; Menard, Etienne; Baca, Alfred; Motala, Michael; Ahn, Jong -Hyun; Park, Sang -Il; Yu, Chang -Jae; Ko, Heung Cho; Stoykovich, Mark; Yoon, Jongseung

2015-08-25

Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

Optical systems fabricated by printing-based assembly

DOEpatents

Rogers, John; Nuzzo, Ralph; Meitl, Matthew; Menard, Etienne; Baca, Alfred; Motala, Michael; Ahn, Jong-Hyun; Park, Sang-Il; Yu, Chang-Jae; Ko, Heung Cho; Stoykovich, Mark; Yoon, Jongseung

2017-03-21

Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

Magnetism in Mn-nanowires and -clusters as δ-doped layers in group IV semiconductors (Si, Ge)

NASA Astrophysics Data System (ADS)

Simov, K. R.; Glans, P.-A.; Jenkins, C. A.; Liberati, M.; Reinke, P.

2018-01-01

Mn doping of group-IV semiconductors (Si/Ge) is achieved by embedding nanostructured Mn-layers in group-IV matrix. The Mn-nanostructures are monoatomic Mn-wires or Mn-clusters and capped with an amorphous Si or Ge layer. The precise fabrication of δ-doped Mn-layers is combined with element-specific detection of the magnetic signature with x-ray magnetic circular dichroism. The largest moment (2.5 μB/Mn) is measured for Mn-wires with ionic bonding character and a-Ge overlayer cap; a-Si capping reduces the moment due to variations of bonding in agreement with theoretical predictions. The moments in δ-doped layers dominated by clusters is quenched with an antiferromagnetic component from Mn-Mn bonding.

Ultra-thin ohmic contacts for p-type nitride light emitting devices

DOEpatents

Raffetto, Mark; Bharathan, Jayesh; Haberern, Kevin; Bergmann, Michael; Emerson, David; Ibbetson, James; Li, Ting

2014-06-24

A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 .ANG.. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

A lead-halide perovskite molecular ferroelectric semiconductor

PubMed Central

Liao, Wei-Qiang; Zhang, Yi; Hu, Chun-Li; Mao, Jiang-Gao; Ye, Heng-Yun; Li, Peng-Fei; Huang, Songping D.; Xiong, Ren-Gen

2015-01-01

Inorganic semiconductor ferroelectrics such as BiFeO3 have shown great potential in photovoltaic and other applications. Currently, semiconducting properties and the corresponding application in optoelectronic devices of hybrid organo-plumbate or stannate are a hot topic of academic research; more and more of such hybrids have been synthesized. Structurally, these hybrids are suitable for exploration of ferroelectricity. Therefore, the design of molecular ferroelectric semiconductors based on these hybrids provides a possibility to obtain new or high-performance semiconductor ferroelectrics. Here we investigated Pb-layered perovskites, and found the layer perovskite (benzylammonium)2PbCl4 is ferroelectric with semiconducting behaviours. It has a larger ferroelectric spontaneous polarization Ps=13 μC cm−2 and a higher Curie temperature Tc=438 K with a band gap of 3.65 eV. This finding throws light on the new properties of the hybrid organo-plumbate or stannate compounds and provides a new way to develop new semiconductor ferroelectrics. PMID:26021758

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2017-01-01

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2016-01-01

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Single-layer ZnMN2 (M = Si, Ge, Sn) zinc nitrides as promising photocatalysts.

PubMed

Bai, Yujie; Luo, Gaixia; Meng, Lijuan; Zhang, Qinfang; Xu, Ning; Zhang, Haiyang; Wu, Xiuqiang; Kong, Fanjie; Wang, Baolin

2018-05-30

Searching for two-dimensional semiconductor materials that are suitable for visible-light photocatalytic water splitting provides a sustainable solution to deal with the future energy crisis and environmental problems. Herein, based on first-principles calculations, single-layer ZnMN2 (M = Si, Ge, Sn) zinc nitrides are proposed as efficient photocatalysts for water splitting. Stability analyses show that the single-layer ZnMN2 zinc nitrides exhibit energetic and dynamical stability. The electronic properties reveal that all of the single-layer ZnMN2 zinc nitrides are semiconductors. Interestingly, single-layer ZnSnN2 is a direct band gap semiconductor with a desirable band gap (1.74 eV), and the optical adsorption spectrum confirms its optical absorption in the visible light region. The hydrogen evolution reaction (HER) calculations show that the catalytic activity for single-layer ZnMN2 (M = Ge, Sn) is better than that of single-layer ZnSiN2. Furthermore, the band gaps and band edge positions for the single-layer ZnMN2 zinc nitrides can be effectively tuned by biaxial strain. Especially, single-layer ZnGeN2 can be effectively tuned to match better with the redox potentials of water and enhance the light absorption in the visible light region at a tensile strain of 5%, which is confirmed by the corresponding optical absorption spectrum. Our results provide guidance for experimental synthesis efforts and future searches for single-layer materials suitable for photocatalytic water splitting.

Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

NASA Astrophysics Data System (ADS)

Biyikli, Necmi; Haider, Ali

2017-09-01

In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

Method of passivating semiconductor surfaces

DOEpatents

Wanlass, M.W.

1990-06-19

A method is described for passivating Group III-V or II-VI semiconductor compound surfaces. The method includes selecting a passivating material having a lattice constant substantially mismatched to the lattice constant of the semiconductor compound. The passivating material is then grown as an ultrathin layer of passivating material on the surface of the Group III-V or II-VI semiconductor compound. The passivating material is grown to a thickness sufficient to maintain a coherent interface between the ultrathin passivating material and the semiconductor compound. In addition, a device formed from such method is also disclosed.

High resolution three-dimensional doping profiler

DOEpatents

Thundat, Thomas G.; Warmack, Robert J.

1999-01-01

A semiconductor doping profiler provides a Schottky contact at one surface and an ohmic contact at the other. While the two contacts are coupled to a power source, thereby establishing an electrical bias in the semiconductor, a localized light source illuminates the semiconductor to induce a photocurrent. The photocurrent changes in accordance with the doping characteristics of the semiconductor in the illuminated region. By changing the voltage of the power source the depth of the depletion layer can be varied to provide a three dimensional view of the local properties of the semiconductor.

Method of passivating semiconductor surfaces

DOEpatents

Wanlass, Mark W.

1990-01-01

A method of passivating Group III-V or II-VI semiconductor compound surfaces. The method includes selecting a passivating material having a lattice constant substantially mismatched to the lattice constant of the semiconductor compound. The passivating material is then grown as an ultrathin layer of passivating material on the surface of the Group III-V or II-VI semiconductor compound. The passivating material is grown to a thickness sufficient to maintain a coherent interface between the ultrathin passivating material and the semiconductor compound. In addition, a device formed from such method is also disclosed.

Copolymer semiconductors comprising thiazolothiazole or benzobisthiazole, or benzobisoxazole electron acceptor subunits, and electron donor subunits, and their uses in transistors and solar cells

DOEpatents

Jenekhe, Samson A; Subramaniyan, Selvam; Ahmed, Eilaf; Xin, Hao; Kim, Felix Sunjoo

2014-10-28

The inventions disclosed, described, and/or claimed herein relate to copolymers comprising copolymers comprising electron accepting A subunits that comprise thiazolothiazole, benzobisthiazole, or benzobisoxazoles rings, and electron donating subunits that comprise certain heterocyclic groups. The copolymers are useful for manufacturing organic electronic devices, including transistors and solar cells. The invention also relates to certain synthetic precursors of the copolymers. Methods for making the copolymers and the derivative electronic devices are also described.

Efficient organic photovoltaic cells on a single layer graphene transparent conductive electrode using MoOx as an interfacial layer.

PubMed

Du, J H; Jin, H; Zhang, Z K; Zhang, D D; Jia, S; Ma, L P; Ren, W C; Cheng, H M; Burn, P L

2017-01-07

The large surface roughness, low work function and high cost of transparent electrodes using multilayer graphene films can limit their application in organic photovoltaic (OPV) cells. Here, we develop single layer graphene (SLG) films as transparent anodes for OPV cells that contain light-absorbing layers comprised of the evaporable molecular organic semiconductor materials, zinc phthalocyanine (ZnPc)/fullerene (C60), as well as a molybdenum oxide (MoO x ) interfacial layer. In addition to an increase in the optical transmittance, the SLG anodes had a significant decrease in surface roughness compared to two and four layer graphene (TLG and FLG) anodes fabricated by multiple transfer and stacking of SLGs. Importantly, the introduction of a MoO x interfacial layer not only reduced the energy barrier between the graphene anode and the active layer, but also decreased the resistance of the SLG by nearly ten times. The OPV cells with the structure of polyethylene terephthalate/SLG/MoO x /CuI/ZnPc/C60/bathocuproine/Al were flexible, and had a power conversion efficiency of up to 0.84%, which was only 17.6% lower than the devices with an equivalent structure but prepared on commercial indium tin oxide anodes. Furthermore, the devices with the SLG anode were 50% and 86.7% higher in efficiency than the cells with the TLG and FLG anodes. These results show the potential of SLG electrodes for flexible and wearable OPV cells as well as other organic optoelectronic devices.

Composition/bandgap selective dry photochemical etching of semiconductor materials

DOEpatents

Ashby, Carol I. H.; Dishman, James L.

1987-01-01

A method of selectively photochemically dry etching a first semiconductor material of a given composition and direct bandgap Eg.sub.1 in the presence of a second semiconductor material of a different composition and direct bandgap Eg.sub.2, wherein Eg.sub.2 >Eg.sub.1, said second semiconductor material substantially not being etched during said method, comprises subjecting both materials to the same photon flux and to the same gaseous etchant under conditions where said etchant would be ineffective for chemical etching of either material were the photons not present, said photons being of an energy greater than Eg.sub.1 but less than Eg.sub.2, whereby said first semiconductor material is photochemically etched and said second material is substantially not etched.

Electric field induced spin-polarized current

DOEpatents

Murakami, Shuichi; Nagaosa, Naoto; Zhang, Shoucheng

2006-05-02

A device and a method for generating an electric-field-induced spin current are disclosed. A highly spin-polarized electric current is generated using a semiconductor structure and an applied electric field across the semiconductor structure. The semiconductor structure can be a hole-doped semiconductor having finite or zero bandgap or an undoped semiconductor of zero bandgap. In one embodiment, a device for injecting spin-polarized current into a current output terminal includes a semiconductor structure including first and second electrodes, along a first axis, receiving an applied electric field and a third electrode, along a direction perpendicular to the first axis, providing the spin-polarized current. The semiconductor structure includes a semiconductor material whose spin orbit coupling energy is greater than room temperature (300 Kelvin) times the Boltzmann constant. In one embodiment, the semiconductor structure is a hole-doped semiconductor structure, such as a p-type GaAs semiconductor layer.

Visible light photoreduction of CO.sub.2 using heterostructured catalysts

DOEpatents

Matranga, Christopher; Thompson, Robert L; Wang, Congjun

2015-03-24

The method provides for use of sensitized photocatalyst for the photocatalytic reduction of CO.sub.2 under visible light illumination. The photosensitized catalyst is comprised of a wide band gap semiconductor material, a transition metal co-catalyst, and a semiconductor sensitizer. The semiconductor sensitizer is photoexcited by visible light and forms a Type II band alignment with the wide band gap semiconductor material. The wide band gap semiconductor material and the semiconductor sensitizer may be a plurality of particles, and the particle diameters may be selected to accomplish desired band widths and optimize charge injection under visible light illumination by utilizing quantum size effects. In a particular embodiment, CO.sub.2 is reduced under visible light illumination using a CdSe/Pt/TiO2 sensitized photocatalyst with H.sub.2O as a hydrogen source.

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Producing Silicon Carbide for Semiconductor Devices

NASA Technical Reports Server (NTRS)

Hsu, G. C.; Rohatgi, N. K.

1986-01-01

Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

Inelastic tunnel diodes

NASA Technical Reports Server (NTRS)

Anderson, L. M. (Inventor)

1984-01-01

Power is extracted from plasmons, photons, or other guided electromagnetic waves at infrared to midultraviolet frequencies by inelastic tunneling in metal-insulator-semiconductor-metal diodes. Inelastic tunneling produces power by absorbing plasmons to pump electrons to higher potential. Specifically, an electron from a semiconductor layer absorbs a plasmon and simultaneously tunnels across an insulator into metal layer which is at higher potential. The diode voltage determines the fraction of energy extracted from the plasmons; any excess is lost to heat.

Stabilized CdSe-CoPi composite photoanode for light-assisted water oxidation by transformation of a CdSe/cobalt metal thin film.

PubMed

Costi, Ronny; Young, Elizabeth R; Bulović, Vladimir; Nocera, Daniel G

2013-04-10

Integration of water splitting catalysts with visible-light-absorbing semiconductors would enable direct solar-energy-to-fuel conversion schemes such as those based on water splitting. A disadvantage of some common semiconductors that possess desirable optical bandgaps is their chemical instability under the conditions needed for oxygen evolution reaction (OER). In this study, we demonstrate the dual benefits gained from using a cobalt metal thin-film as the precursor for the preparation of cobalt-phosphate (CoPi) OER catalyst on cadmium chalcogenide photoanodes. The cobalt layer protects the underlying semiconductor from oxidation and degradation while forming the catalyst and simultaneously facilitates the advantageous incorporation of the cadmium chalcogenide layer into the CoPi layer during continued processing of the electrode. The resulting hybrid material forms a stable photoactive anode for light-assisted water splitting.

Power module packaging with double sided planar interconnection and heat exchangers

DOEpatents

Liang, Zhenxian; Marlino, Laura D.; Ning, Puqi; Wang, Fei

2015-05-26

A double sided cooled power module package having a single phase leg topology includes two IGBT and two diode semiconductor dies. Each IGBT die is spaced apart from a diode semiconductor die, forming a switch unit. Two switch units are placed in a planar face-up and face-down configuration. A pair of DBC or other insulated metallic substrates is affixed to each side of the planar phase leg semiconductor dies to form a sandwich structure. Attachment layers are disposed on outer surfaces of the substrates and two heat exchangers are affixed to the substrates by rigid bond layers. The heat exchangers, made of copper or aluminum, have passages for carrying coolant. The power package is manufactured in a two-step assembly and heating process where direct bonds are formed for all bond layers by soldering, sintering, solid diffusion bonding or transient liquid diffusion bonding, with a specially designed jig and fixture.

Complexes of dipolar excitons in layered quasi-two-dimensional nanostructures

NASA Astrophysics Data System (ADS)

Bondarev, Igor V.; Vladimirova, Maria R.

2018-04-01

We discuss neutral and charged complexes (biexcitons and trions) formed by indirect excitons in layered quasi-two-dimensional semiconductor heterostructures. Indirect excitons—long-lived neutral Coulomb-bound pairs of electrons and holes of different layers—have been known for semiconductor coupled quantum wells and have recently been reported for van der Waals heterostructures such as double bilayer graphene and transition-metal dichalcogenides. Using the configuration space approach, we derive the analytical expressions for the trion and biexciton binding energies as a function of interlayer distance. The method captures essential kinematics of complex formation to reveal significant binding energies, up to a few tens of meV for typical interlayer distances ˜3 -5 Å , with the trion binding energy always being greater than that of the biexciton. Our results can contribute to the understanding of more complex many-body phenomena such as exciton Bose-Einstein condensation and Wigner-like electron-hole crystallization in layered semiconductor heterostructures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Zhemin; Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552; Taguchi, Dai

The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial chargingmore » in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.« less

Semiconductor light-emitting devices having concave microstructures providing improved light extraction efficiency and method for producing same

DOEpatents

Tansu, Nelson; Gilchrist, James F; Ee, Yik-Khoon; Kumnorkaew, Pisist

2013-11-19

A conventional semiconductor LED is modified to include a microlens layer over its light-emitting surface. The LED may have an active layer including at least one quantum well layer of InGaN and GaN. The microlens layer includes a plurality of concave microstructures that cause light rays emanating from the LED to diffuse outwardly, leading to an increase in the light extraction efficiency of the LED. The concave microstructures may be arranged in a substantially uniform array, such as a close-packed hexagonal array. The microlens layer is preferably constructed of curable material, such as polydimethylsiloxane (PDMS), and is formed by soft-lithography imprinting by contacting fluid material of the microlens layer with a template bearing a monolayer of homogeneous microsphere crystals, to cause concave impressions, and then curing the material to fix the concave microstructures in the microlens layer and provide relatively uniform surface roughness.

Strain-compensated infrared photodetector and photodetector array

DOEpatents

Kim, Jin K; Hawkins, Samuel D; Klem, John F; Cich, Michael J

2013-05-28

A photodetector is disclosed for the detection of infrared light with a long cutoff wavelength in the range of about 4.5-10 microns. The photodetector, which can be formed on a semiconductor substrate as an nBn device, has a light absorbing region which includes InAsSb light-absorbing layers and tensile-strained layers interspersed between the InAsSb light-absorbing layers. The tensile-strained layers can be formed from GaAs, InAs, InGaAs or a combination of these III-V compound semiconductor materials. A barrier layer in the photodetector can be formed from AlAsSb or AlGaAsSb; and a contact layer in the photodetector can be formed from InAs, GaSb or InAsSb. The photodetector is useful as an individual device, or to form a focal plane array.

Subnanosecond Scintillation Detector

NASA Technical Reports Server (NTRS)

Hoenk, Michael (Inventor); Hennessy, John (Inventor); Hitlin, David (Inventor)

2017-01-01

A scintillation detector, including a scintillator that emits scintillation; a semiconductor photodetector having a surface area for receiving the scintillation, wherein the surface area has a passivation layer configured to provide a peak quantum efficiency greater than 40% for a first component of the scintillation, and the semiconductor photodetector has built in gain through avalanche multiplication; a coating on the surface area, wherein the coating acts as a bandpass filter that transmits light within a range of wavelengths corresponding to the first component of the scintillation and suppresses transmission of light with wavelengths outside said range of wavelengths; and wherein the surface area, the passivation layer, and the coating are controlled to increase the temporal resolution of the semiconductor photodetector.

Laser ablation mechanism of transparent layers on semiconductors with ultrashort laser pulses

NASA Astrophysics Data System (ADS)

Rublack, Tino; Hartnauer, Stefan; Mergner, Michael; Muchow, Markus; Seifert, Gerhard

2011-12-01

Transparent dielectric layers on semiconductors are used as anti-reflection coatings both for photovoltaic applications and for mid-infrared optical elements. We have shown recently that selective ablation of such layers is possible using ultrashort laser pulses at wavelengths being absorbed by the semiconductor. To get a deeper understanding of the ablation mechanism, we have done ablation experiments for different transparent materials, in particular SiO2 and SixNy on silicon, using a broad range of wavelengths ranging from UV to IR, and pulse durations between 50 and 2000 fs. The characterization of the ablated regions was done by light microscopy and atomic force microscopy (AFM). Utilizing laser wavelengths above the silicon band gap, selective ablation of the dielectric layer without noticeable damage of the opened silicon surface is possible. In contrast, ultrashort pulses (1-2 ps) at mid-infrared wavelengths already cause damage in the silicon at lower intensities than in the dielectric layer, even when a vibrational resonance (e.g. at λ = 9.26 μm for SiO2) is addressed. The physical processes behind this, on the first glance counterintuitive, observation will be discussed.

Optoelectronics of supported and suspended 2D semiconductors

NASA Astrophysics Data System (ADS)

Bolotin, Kirill

2014-03-01

Two-dimensional semiconductors, materials such monolayer molybdenum disulfide (MoS2) are characterized by strong spin-orbit and electron-electron interactions. However, both electronic and optoelectronic properties of these materials are dominated by disorder-related scattering. In this talk, we investigate approaches to reduce scattering and explore physical phenomena arising in intrinsic 2D semiconductors. First, we discuss fabrication of pristine suspended monolayer MoS2 and use photocurrent spectroscopy measurements to study excitons in this material. We observe band-edge and van Hove singularity excitons and estimate their binding energies. Furthermore, we study dissociation of these excitons and uncover the mechanism of their contribution to photoresponse of MoS2. Second, we study strain-induced modification of bandstructures of 2D semiconductors. With increasing strain, we find large and controllable band gap reduction of both single- and bi-layer MoS2. We also detect experimental signatures consistent with strain-induced transition from direct to indirect band gap in monolayer MoS2. Finally, we fabricate heterostructures of dissimilar 2D semiconductors and study their photoresponse. For closely spaced 2D semiconductors we detect charge transfer, while for separation larger than 10nm we observe Forster-like energy transfer between excitations in different layers.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Veselov, D. A., E-mail: dmitriy90@list.ru; Shashkin, I. S.; Bakhvalov, K. V.

Semiconductor lasers based on MOCVD-grown AlGaInAs/InP separate-confinement heterostructures are studied. It is shown that raising only the energy-gap width of AlGaInAs-waveguides without the introduction of additional barriers results in more pronounced current leakage into the cladding layers. It is found that the introduction of additional barrier layers at the waveguide–cladding-layer interface blocks current leakage into the cladding layers, but results in an increase in the internal optical loss with increasing pump current. It is experimentally demonstrated that the introduction of blocking layers makes it possible to obtain maximum values of the internal quantum efficiency of stimulated emission (92%) and continuouswavemore » output optical power (3.2 W) in semiconductor lasers in the eye-safe wavelength range (1400–1600 nm).« less

Hetero-junction photovoltaic device and method of fabricating the device

DOEpatents

Aytug, Tolga; Christen, David K; Paranthaman, Mariappan Parans; Polat, Ozgur

2014-02-10

A hetero-junction device and fabrication method in which phase-separated n-type and p-type semiconductor pillars define vertically-oriented p-n junctions extending above a substrate. Semiconductor materials are selected for the p-type and n-type pillars that are thermodynamically stable and substantially insoluble in one another. An epitaxial deposition process is employed to form the pillars on a nucleation layer and the mutual insolubility drives phase separation of the materials. During the epitaxial deposition process, the orientation is such that the nucleation layer initiates propagation of vertical columns resulting in a substantially ordered, three-dimensional structure throughout the deposited material. An oxidation state of at least a portion of one of the p-type or the n-type semiconductor materials is altered relative to the other, such that the band-gap energy of the semiconductor materials differ with respect to stoichiometric compositions and the device preferentially absorbs particular selected bands of radiation.

Chitin Liquid-Crystal-Templated Oxide Semiconductor Aerogels.

PubMed

Chau, Trang The Lieu; Le, Dung Quang Tien; Le, Hoa Thi; Nguyen, Cuong Duc; Nguyen, Long Viet; Nguyen, Thanh-Dinh

2017-09-13

Chitin nanocrystals have been used as a liquid crystalline template to fabricate layered oxide semiconductor aerogels. Anisotropic chitin liquid crystals are transformed to sponge-like aerogels by hydrothermally cross-linked gelation and lyophilization-induced solidification. The hydrothermal gelation of chitin aqueous suspensions then proceeds with peroxotitanate to form hydrogel composites that recover to form aerogels after freeze-drying. The homogeneous peroxotitanate/chitin composites are calcined to generate freestanding titania aerogels that exhibit the nanostructural integrity of layered chitin template. Our extended investigations show that coassembling chitin nanocrystals with other metal-based precursors also yielded semiconductor aerogels of perovskite BaTiO 3 and CuO x nanocrystals. The potential of these materials is great to investigate these chitin sponges for biomedicine and these semiconductor aerogels for photocatalysis, gas sensing, and other applications. Our results present a new aerogel templating method of highly porous, ultralight materials with chitin liquid crystals.

Exchanging Ohmic Losses in Metamaterial Absorbers with Useful Optical Absorption for Photovoltaics

PubMed Central

Vora, Ankit; Gwamuri, Jephias; Pala, Nezih; Kulkarni, Anand; Pearce, Joshua M.; Güney, Durdu Ö.

2014-01-01

Using metamaterial absorbers, we have shown that metallic layers in the absorbers do not necessarily constitute undesired resistive heating problem for photovoltaics. Tailoring the geometric skin depth of metals and employing the natural bulk absorbance characteristics of the semiconductors in those absorbers can enable the exchange of undesired resistive losses with the useful optical absorbance in the active semiconductors. Thus, Ohmic loss dominated metamaterial absorbers can be converted into photovoltaic near-perfect absorbers with the advantage of harvesting the full potential of light management offered by the metamaterial absorbers. Based on experimental permittivity data for indium gallium nitride, we have shown that between 75%–95% absorbance can be achieved in the semiconductor layers of the converted metamaterial absorbers. Besides other metamaterial and plasmonic devices, our results may also apply to photodectors and other metal or semiconductor based optical devices where resistive losses and power consumption are important pertaining to the device performance. PMID:24811322

Potential barrier heights at metal on oxygen-terminated diamond interfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muret, P., E-mail: pierre.muret@neel.cnrs.fr; Traoré, A.; Maréchal, A.

2015-11-28

Electrical properties of metal-semiconductor (M/SC) and metal/oxide/SC structures built with Zr or ZrO{sub 2} deposited on oxygen-terminated surfaces of (001)-oriented diamond films, comprised of a stack of lightly p-doped diamond on a heavily doped layer itself homoepitaxially grown on an Ib substrate, are investigated experimentally and compared to different models. In Schottky barrier diodes, the interfacial oxide layer evidenced by high resolution transmission electron microscopy and electron energy losses spectroscopy before and after annealing, and barrier height inhomogeneities accounts for the measured electrical characteristics until flat bands are reached, in accordance with a model which generalizes that by Tung [Phys.more » Rev. B 45, 13509 (1992)] and permits to extract physically meaningful parameters of the three kinds of interface: (a) unannealed ones, (b) annealed at 350 °C, (c) annealed at 450 °C with the characteristic barrier heights of 2.2–2.5 V in case (a) while as low as 0.96 V in case (c). Possible models of potential barriers for several metals deposited on well defined oxygen-terminated diamond surfaces are discussed and compared to experimental data. It is concluded that interface dipoles of several kinds present at these compound interfaces and their chemical evolution due to annealing are the suitable ingredients that are able to account for the Mott-Schottky behavior when the effect of the metal work function is ignored, and to justify the reverted slope observed regarding metal work function, in contrast to the trend always reported for all other metal-semiconductor interfaces.« less

Two-dimensional transition metal dichalcogenides as atomically thin semiconductors: opportunities and challenges.

PubMed

Duan, Xidong; Wang, Chen; Pan, Anlian; Yu, Ruqin; Duan, Xiangfeng

2015-12-21

The discovery of graphene has ignited intensive interest in two-dimensional layered materials (2DLMs). These 2DLMs represent a new class of nearly ideal 2D material systems for exploring fundamental chemistry and physics at the limit of single-atom thickness, and have the potential to open up totally new technological opportunities beyond the reach of existing materials. In general, there are a wide range of 2DLMs in which the atomic layers are weakly bonded together by van der Waals interactions and can be isolated into single or few-layer nanosheets. The van der Waals interactions between neighboring atomic layers could allow much more flexible integration of distinct materials to nearly arbitrarily combine and control different properties at the atomic scale. The transition metal dichalcogenides (TMDs) (e.g., MoS2, WSe2) represent a large family of layered materials, many of which exhibit tunable band gaps that can undergo a transition from an indirect band gap in bulk crystals to a direct band gap in monolayer nanosheets. These 2D-TMDs have thus emerged as an exciting class of atomically thin semiconductors for a new generation of electronic and optoelectronic devices. Recent studies have shown exciting potential of these atomically thin semiconductors, including the demonstration of atomically thin transistors, a new design of vertical transistors, as well as new types of optoelectronic devices such as tunable photovoltaic devices and light emitting devices. In parallel, there have also been considerable efforts in developing diverse synthetic approaches for the rational growth of various forms of 2D materials with precisely controlled chemical composition, physical dimension, and heterostructure interface. Here we review the recent efforts, progress, opportunities and challenges in exploring the layered TMDs as a new class of atomically thin semiconductors.

Twisted bilayer blue phosphorene: A direct band gap semiconductor

NASA Astrophysics Data System (ADS)

Ospina, D. A.; Duque, C. A.; Correa, J. D.; Suárez Morell, Eric

2016-09-01

We report that two rotated layers of blue phosphorene behave as a direct band gap semiconductor. The optical spectrum shows absorption peaks in the visible region of the spectrum and in addition the energy of these peaks can be tuned with the rotational angle. These findings makes twisted bilayer blue phosphorene a strong candidate as a solar cell or photodetection device. Our results are based on ab initio calculations of several rotated blue phosphorene layers.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, Arthur W.; Ellingboe, Albert R.

1998-01-01

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18-0.35 mm or less.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, A.W.; Ellingboe, A.R.

1998-10-20

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18--0.35 mm or less. 16 figs.

High performance thin film transistor with ZnO channel layer deposited by DC magnetron sputtering.

PubMed

Moon, Yeon-Keon; Moon, Dae-Yong; Lee, Sang-Ho; Jeong, Chang-Oh; Park, Jong-Wan

2008-09-01

Research in large area electronics, especially for low-temperature plastic substrates, focuses commonly on limitations of the semiconductor in thin film transistors (TFTs), in particular its low mobility. ZnO is an emerging example of a semiconductor material for TFTs that can have high mobility, while a-Si and organic semiconductors have low mobility (<1 cm2/Vs). ZnO-based TFTs have achieved high mobility, along with low-voltage operation low off-state current, and low gate leakage current. In general, ZnO thin films for the channel layer of TFTs are deposited with RF magnetron sputtering methods. On the other hand, we studied ZnO thin films deposited with DC magnetron sputtering for the channel layer of TFTs. After analyzing the basic physical and chemical properties of ZnO thin films, we fabricated a TFT-unit cell using ZnO thin films for the channel layer. The field effect mobility (micro(sat)) of 1.8 cm2/Vs and threshold voltage (Vth) of -0.7 V were obtained.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

PubMed Central

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-01-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters. PMID:26842997

Composition/bandgap selective dry photochemical etching of semiconductor materials

DOEpatents

Ashby, C.I.H.; Dishman, J.L.

1985-10-11

Disclosed is a method of selectively photochemically dry etching a first semiconductor material of a given composition and direct bandgap Eg/sub 1/ in the presence of a second semiconductor material of a different composition and direct bandgap Eg/sub 2/, wherein Eg/sub 2/ > Eg/sub 1/, said second semiconductor material substantially not being etched during said method. The method comprises subjecting both materials to the same photon flux and to the same gaseous etchant under conditions where said etchant would be ineffective for chemical etching of either material were the photons not present, said photons being of an energy greater than Eg/sub 1/ but less than Eg/sub 2/, whereby said first semiconductor material is photochemically etched and said second material is substantially not etched.

Lapped substrate for enhanced backsurface reflectivity in a thermophotovoltaic energy conversion system

DOEpatents

Baldasaro, Paul F; Brown, Edward J; Charache, Greg W; DePoy, David M

2000-01-01

A method for fabricating a thermophotovoltaic energy conversion cell including a thin semiconductor wafer substrate (10) having a thickness (.beta.) calculated to decrease the free carrier absorption on a heavily doped substrate; wherein the top surface of the semiconductor wafer substrate is provided with a thermophotovoltaic device (11), a metallized grid (12) and optionally an antireflective (AR) overcoating; and, the bottom surface (10') of the semiconductor wafer substrate (10) is provided with a highly reflecting coating which may comprise a metal coating (14) or a combined dielectric/metal coating (17).

Lapped substrate for enhanced backsurface reflectivity in a thermophotovoltaic energy conversion system

DOEpatents

Baldasaro, Paul F; Brown, Edward J; Charache, Greg W; DePoy, David M

2000-09-05

A method for fabricating a thermophotovoltaic energy conversion cell including a thin semiconductor wafer substrate (10) having a thickness (.beta.) calculated to decrease the free carrier absorption on a heavily doped substrate; wherein the top surface of the semiconductor wafer substrate is provided with a thermophotovoltaic device (11), a metallized grid (12) and optionally an antireflective (AR) overcoating; and, the bottom surface (10') of the semiconductor wafer substrate (10) is provided with a highly reflecting coating which may comprise a metal coating (14) or a combined dielectric/metal coating (17).

Thin film photovoltaic device

DOEpatents

Catalano, Anthony W.; Bhushan, Manjul

1982-01-01

A thin film photovoltaic solar cell which utilizes a zinc phosphide semiconductor is of the homojunction type comprising an n-type conductivity region forming an electrical junction with a p-type region, both regions consisting essentially of the same semiconductor material. The n-type region is formed by treating zinc phosphide with an extrinsic dopant such as magnesium. The semiconductor is formed on a multilayer substrate which acts as an opaque contact. Various transparent contacts may be used, including a thin metal film of the same chemical composition as the n-type dopant or conductive oxides or metal grids.

Modeling electrochemical deposition inside nanotubes to obtain metal-semiconductor multiscale nanocables or conical nanopores.

PubMed

Lebedev, Konstantin; Mafé, Salvador; Stroeve, Pieter

2005-08-04

Nanocables with a radial metal-semiconductor heterostructure have recently been prepared by electrochemical deposition inside metal nanotubes. First, a bare nanoporous polycarbonate track-etched membrane is coated uniformly with a metal film by electroless deposition. The film forms a working electrode for further deposition of a semiconductor layer that grows radially inside the nanopore when the deposition rate is slow. We propose a new physical model for the nanocable synthesis and study the effects of the deposited species concentration, potential-dependent reaction rate, and nanopore dimensions on the electrochemical deposition. The problem involves both axial diffusion through the nanopore and radial transport to the nanopore surface, with a surface reaction rate that depends on the axial position and the time. This is so because the radial potential drop across the deposited semiconductor layer changes with the layer thickness through the nanopore. Since axially uniform nanocables are needed for most applications, we consider the relative role of reaction and axial diffusion rates on the deposition process. However, in those cases where partial, empty-core deposition should be desirable (e.g., for producing conical nanopores to be used in single nanoparticle detection), we give conditions where asymmetric geometries can be experimentally realized.

Multi-layer MOS capacitor based polarization insensitive electro-optic intensity modulator.

PubMed

Qiu, Xiaoming; Ruan, Xiaoke; Li, Yanping; Zhang, Fan

2018-05-28

In this study, a multi-layer metal-oxide-semiconductor capacitor (MLMOSC) polarization insensitive modulator is proposed. The design is validated by numerical simulation with commercial software LUMERICAL SOLUTION. Based on the epsilon-near-zero (ENZ) effect of indium tin oxide (ITO), the device manages to uniformly modulate both the transverse electric (TE) and the transverse magnetic (TM) modes. With a 20μm-long double-layer metal-oxide-semiconductor capacitor (DLMOSC) polarization insensitive modulator, in which two metal-oxide-semiconductor (MOS) structures are formed by the n-doped Si/HfO 2 /ITO/HfO 2 / n-doped Si stack, the extinction ratios (ERs) of both the TE and the TM modes can be over 20dB. The polarization dependent losses of the device can be as low as 0.05dB for the "OFF" state and 0.004dB for the "ON" state. Within 1dB polarization dependent loss, the device can operate with over 20dB ERs at the S, C, and L bands. The polarization insensitive modulator offers various merits including ultra-compact size, broadband spectrum, and complementary metal oxide semiconductor (CMOS) compatibility.

Effect of temperature on terahertz photonic and omnidirectional band gaps in one-dimensional quasi-periodic photonic crystals composed of semiconductor InSb.

PubMed

Singh, Bipin K; Pandey, Praveen C

2016-07-20

Engineering of thermally tunable terahertz photonic and omnidirectional bandgaps has been demonstrated theoretically in one-dimensional quasi-periodic photonic crystals (PCs) containing semiconductor and dielectric materials. The considered quasi-periodic structures are taken in the form of Fibonacci, Thue-Morse, and double periodic sequences. We have shown that the photonic and omnidirectional bandgaps in the quasi-periodic structures with semiconductor constituents are strongly depend on the temperature, thickness of the constituted semiconductor and dielectric material layers, and generations of the quasi-periodic sequences. It has been found that the number of photonic bandgaps increases with layer thickness and generation of the quasi-periodic sequences. Omnidirectional bandgaps in the structures have also been obtained. Results show that the bandwidths of photonic and omnidirectional bandgaps are tunable by changing the temperature and lattice parameters of the structures. The generation of quasi-periodic sequences can also change the properties of photonic and omnidirectional bandgaps remarkably. The frequency range of the photonic and omnidirectional bandgaps can be tuned by the change of temperature and layer thickness of the considered quasi-periodic structures. This work will be useful to design tunable terahertz PC devices.

Single-mode very wide tunability in laterally coupled semiconductor lasers with electrically controlled reflectivities

NASA Astrophysics Data System (ADS)

Griffel, Giora; Chen, Howard Z.; Grave, Ilan; Yariv, Amnon

1991-04-01

The operation of a novel multisection structure comprised of laterally coupled gain-guided semiconductor lasers is demonstrated. It is shown that tunable single longitudinal mode operation can be achieved with a high degree of frequency selectivity. The device has a tuning range of 14.5 nm, the widest observed to date in a monolithic device.

High resolution scintillation detector with semiconductor readout

DOEpatents

Levin, Craig S.; Hoffman, Edward J.

2000-01-01

A novel high resolution scintillation detector array for use in radiation imaging such as high resolution Positron Emission Tomography (PET) which comprises one or more parallelepiped crystals with at least one long surface of each crystal being in intimate contact with a semiconductor photodetector such that photons generated within each crystal by gamma radiation passing therethrough is detected by the photodetector paired therewith.

Bimetallic alloy electrocatalysts with multilayered platinum-skin surfaces

DOEpatents

Stamenkovic, Vojislav R.; Wang, Chao; Markovic, Nenad M.

2016-01-26

Compositions and methods of preparing a bimetallic alloy having enhanced electrocatalytic properties are provided. The composition comprises a PtNi substrate having a surface layer, a near-surface layer, and an inner layer, where the surface layer comprises a nickel-depleted composition, such that the surface layer comprises a platinum skin having at least one atomic layer of platinum.

Method for manufacturing electrical contacts for a thin-film semiconductor device

DOEpatents

Carlson, David E.; Dickson, Charles R.; D'Aiello, Robert V.

1988-11-08

A method of fabricating spaced-apart back contacts on a thin film of semiconductor material by forming strips of buffer material on top of the semiconductor material in locations corresponding to the desired dividing lines between back contacts, forming a film of metal substantially covering the semiconductor material and buffer strips, and scribing portions of the metal film overlying the buffer strips with a laser without contacting the underlying semiconductor material to separate the metal layer into a plurality of back contacts. The buffer material serves to protect the underlying semiconductor material from being damaged during the laser scribing. Back contacts and multi-cell photovoltaic modules incorporating such back contacts also are disclosed.

Electrical contacts for a thin-film semiconductor device

DOEpatents

Carlson, David E.; Dickson, Charles R.; D'Aiello, Robert V.

1989-08-08

A method of fabricating spaced-apart back contacts on a thin film of semiconductor material by forming strips of buffer material on top of the semiconductor material in locations corresponding to the desired dividing lines between back contacts, forming a film of metal substantially covering the semiconductor material and buffer strips, and scribing portions of the metal film overlying the buffer strips with a laser without contacting the underlying semiconductor material to separate the metal layer into a plurality of back contacts. The buffer material serves to protect the underlying semiconductor material from being damaged during the laser scribing. Back contacts and multi-cell photovoltaic modules incorporating such back contacts also are disclosed.

Electro-optical SLS devices for operating at new wavelength ranges

DOEpatents

Osbourn, Gordon C.

1986-01-01

An intrinsic semiconductor electro-optical device includes a p-n junction intrinsically responsive, when cooled, to electromagnetic radiation in the wavelength range of 8-12 um. The junction consists of a strained-layer superlattice of alternating layers of two different III-V semiconductors having mismatched lattice constants when in bulk form. A first set of layers is either InAs.sub.1-x Sb.sub.x (where x is aobut 0.5 to 0.7) or In.sub.1-x Ga.sub.x As.sub.1-y Sb.sub.y (where x and y are chosen such that the bulk bandgap of the resulting layer is about the same as the minimum bandgap in the In.sub.1-x Ga.sub.x As.sub.1-y Sb.sub.y family). The second set of layers has a lattice constant larger than the lattice constant of the layers in the first set.

Charge-density study on layered oxyarsenides (LaO)MAs (M = Mn, Fe, Ni, Zn)

NASA Astrophysics Data System (ADS)

Takase, Kouichi; Hiramoto, Shozo; Fukushima, Tetsuya; Sato, Kazunori; Moriyoshi, Chikako; Kuroiwa, Yoshihiro

2017-12-01

Using synchrotron X-ray powder diffraction, we investigate the charge-density distributions of the layered oxypnictides (LaO)MnAs, (LaO)FeAs, (LaO)NiAs, and (LaO)ZnAs, which are an antiferromagnetic semiconductor, a parent material of an iron-based superconductor, a low-temperature superconductor, and a non-magnetic semiconductor, respectively. For the metallic samples, clear charge densities are observed in both the transition-metal pnictide layers and the rare-earth-oxide layers. However, in the semiconducting samples, there is no finite charge density between the transition-metal element and As. These differences in charge density reflect differences in physical properties. First-principles calculations using density functional theory reproduce the experimental results reasonably well.

Stable surface passivation process for compound semiconductors

DOEpatents

Ashby, Carol I. H.

2001-01-01

A passivation process for a previously sulfided, selenided or tellurated III-V compound semiconductor surface. The concentration of undesired mid-gap surface states on a compound semiconductor surface is reduced by the formation of a near-monolayer of metal-(sulfur and/or selenium and/or tellurium)-semiconductor that is effective for long term passivation of the underlying semiconductor surface. Starting with the III-V compound semiconductor surface, any oxidation present thereon is substantially removed and the surface is then treated with sulfur, selenium or tellurium to form a near-monolayer of chalcogen-semiconductor of the surface in an oxygen-free atmosphere. This chalcogenated surface is then contacted with a solution of a metal that will form a low solubility chalcogenide to form a near-monolayer of metal-chalcogen-semiconductor. The resulting passivating layer provides long term protection for the underlying surface at or above the level achieved by a freshly chalcogenated compound semiconductor surface in an oxygen free atmosphere.

Diagnostic system for profiling micro-beams

DOEpatents

Elmer, John W.; Palmer, Todd A.; Teruya, Alan T.; Walton, Chris C.

2007-10-30

An apparatus for characterization of a micro beam comprising a micro modified Faraday cup assembly including a first layer of material, a second layer of material operatively connected to the first layer of material, a third layer of material operatively connected to the second layer of material, and a fourth layer of material operatively connected to the third layer of material. The first layer of material comprises an electrical conducting material and has at least one first layer radial slit extending through the first layer. An electrical ground is connected to the first layer. The second layer of material comprises an insulating material and has at least one second layer radial slit corresponding to the first layer radial slit in the first layer of material. The second layer radial slit extends through the second layer. The third layer of material comprises a conducting material and has at least one third layer radial slit corresponding to the second layer radial slit in the second layer of material. The third layer radial slit extends through the third layer. The fourth layer of material comprises an electrical conducting material but does not have slits. An electrical measuring device is connected to the fourth layer. The micro modified Faraday cup assembly is positioned to be swept by the micro beam.

Photon extraction from nitride ultraviolet light-emitting devices

DOEpatents

Schowalter, Leo J; Chen, Jianfeng; Grandusky, James R

2015-02-24

In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.

Single-layer group IV-V and group V-IV-III-VI semiconductors: Structural stability, electronic structures, optical properties, and photocatalysis

NASA Astrophysics Data System (ADS)

Lin, Jia-He; Zhang, Hong; Cheng, Xin-Lu; Miyamoto, Yoshiyuki

2017-07-01

Recently, single-layer group III monochalcogenides have attracted both theoretical and experimental interest at their potential applications in photonic devices, electronic devices, and solar energy conversion. Excited by this, we theoretically design two kinds of highly stable single-layer group IV-V (IV =Si ,Ge , and Sn; V =N and P) and group V-IV-III-VI (IV =Si ,Ge , and Sn; V =N and P; III =Al ,Ga , and In; VI =O and S) compounds with the same structures with single-layer group III monochalcogenides via first-principles simulations. By using accurate hybrid functional and quasiparticle methods, we show the single-layer group IV-V and group V-IV-III-VI are indirect bandgap semiconductors with their bandgaps and band edge positions conforming to the criteria of photocatalysts for water splitting. By applying a biaxial strain on single-layer group IV-V, single-layer group IV nitrides show a potential on mechanical sensors due to their bandgaps showing an almost linear response for strain. Furthermore, our calculations show that both single-layer group IV-V and group V-IV-III-VI have absorption from the visible light region to far-ultraviolet region, especially for single-layer SiN-AlO and SnN-InO, which have strong absorption in the visible light region, resulting in excellent potential for solar energy conversion and visible light photocatalytic water splitting. Our research provides valuable insight for finding more potential functional two-dimensional semiconductors applied in optoelectronics, solar energy conversion, and photocatalytic water splitting.

Process for producing dispersed particulate composite materials

DOEpatents

Henager, Jr., Charles H.; Hirth, John P.

1995-01-01

This invention is directed to a process for forming noninterwoven dispersed particulate composite products. In one case a composite multi-layer film product comprises a substantially noninterwoven multi-layer film having a plurality of discrete layers. This noninterwoven film comprises at least one discrete layer of a first material and at least one discrete layer of a second material. In another case the first and second materials are blended together with each other. In either case, the first material comprises a metalloid and the second material a metal compound. At least one component of a first material in one discrete layer undergoes a solid state displacement reaction with at least one component of a second material thereby producing the requisite noninterwoven composite film product. Preferably, the first material comprises silicon, the second material comprises Mo.sub.2 C, the third material comprises SiC and the fourth material comprises MoSi.sub.2.

Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-12-09

Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.

Outline and comparison of the possible effects present in a metal-thin-film-insulator-semiconductor solar cell

NASA Technical Reports Server (NTRS)

Fonash, S. J.

1976-01-01

The advantages possible with the insertion of a thin-film insulating or semi-insulating layer between a metal and a semiconductor to form the MIS photovoltaic device have been presented previously in the literature. This MIS configuration may be considered as a specific example of a more general class of photovoltaic devices: electrode-thin-film-insulator-semiconductor devices. Since the advantages of the configuration were pointed out, there has been considerable experimental interest in these photovoltaic devices. Because the previous analysis showed that the introduction of the insulator layer could produce several different but advantageous effects, this paper presents a further outline giving a comparison of these effects together with their ramifications.

Intermediate type excitons in Schottky barriers of A3B6 layer semiconductors and UV photodetectors

NASA Astrophysics Data System (ADS)

Alekperov, O. Z.; Guseinov, N. M.; Nadjafov, A. I.

2006-09-01

Photoelectric and photovoltaic spectra of Schottky barrier (SB) structures of InSe, GaSe and GaS layered semiconductors (LS) are investigated at quantum energies from the band edge excitons of corresponding materials up to 6.5eV. Spectral dependences of photoconductivity (PC) of photo resistors and barrier structures are strongly different at the quantum energies corresponding to the intermediate type excitons (ITE) observed in these semiconductors. It was suggested that high UV photoconductivity of A3B6 LS is due to existence of high mobility light carriers in the depth of the band structure. It is shown that SB of semitransparent Au-InSe is high sensitive photo detector in UV region of spectra.

MOVPE Growth of LWIR AlInAs/GaInAs/InP Quantum Cascade Lasers: Impact of Growth and Material Quality on Laser Performance

DTIC Science & Technology

2017-02-01

MOVPE Growth of LWIR AlInAs/GaInAs/InP Quantum Cascade Lasers: Impact of Growth and Material Quality on Laser Performance (Invited paper) Christine A...epitaxial layers in quantum cascade lasers (QCLs) has a primary impact on QCL operation, and establishing correlations between epitaxial growth and materials...QCLs emitting in this range. Index terms – Quantum cascade lasers, semiconductor growth, semiconductor epitaxial layers, infrared emitters. I

Adhesive flexible barrier film, method of forming same, and organic electronic device including same

DOEpatents

Blizzard, John Donald; Weidner, William Kenneth

2013-02-05

An adhesive flexible barrier film comprises a substrate and a barrier layer disposed on the substrate. The barrier layer is formed from a barrier composition comprising an organosilicon compound. The adhesive flexible barrier film also comprises an adhesive layer disposed on the barrier layer and formed from an adhesive composition. A method of forming the adhesive flexible barrier film comprises the steps of disposing the barrier composition on the substrate to form the barrier layer, disposing the adhesive composition on the barrier layer to form the adhesive layer, and curing the barrier layer and the adhesive layer. The adhesive flexible barrier film may be utilized in organic electronic devices.

Photoluminescent Au-Ge composite nanodots formation on SiO2 surface by ion induced dewetting

NASA Astrophysics Data System (ADS)

Datta, D. P.; Siva, V.; Singh, A.; Kanjilal, D.; Sahoo, P. K.

2017-09-01

Medium energy ion irradiation on a bilayer of Au and Ge on SiO2 is observed to result in gradual morphological evolution from an interconnected network to a nanodot array on the insulator surface. Structural and compositional analyses reveal composite nature of the nanodots, comprising of both Au and Ge. The growing nanostructures are found to be photoluminescent at room temperature where the emission intensity and wavelengths vary with morphology. The growth of such nanostructures can be understood in terms of dewetting of the metal layer under ion irradiation due to ion-induced melting along the ion tracks. The visible PL emission is found to be related with evolution of the Au-Ge nanodots. The study indicates a route towards single step synthesis of metal-semiconductor nanodots on insulator surface.

Inorganic perovskite photocatalysts for solar energy utilization.

PubMed

Zhang, Guan; Liu, Gang; Wang, Lianzhou; Irvine, John T S

2016-10-24

The development and utilization of solar energy in environmental remediation and water splitting is being intensively studied worldwide. During the past few decades, tremendous efforts have been devoted to developing non-toxic, low-cost, efficient and stable photocatalysts for water splitting and environmental remediation. To date, several hundreds of photocatalysts mainly based on metal oxides, sulfides and (oxy)nitrides with different structures and compositions have been reported. Among them, perovskite oxides and their derivatives (layered perovskite oxides) comprise a large family of semiconductor photocatalysts because of their structural simplicity and flexibility. This review specifically focuses on the general background of perovskite and its related materials, summarizes the recent development of perovskite photocatalysts and their applications in water splitting and environmental remediation, discusses the theoretical modelling and calculation of perovskite photocatalysts and presents the key challenges and perspectives on the research of perovskite photocatalysts.

Process for selectively patterning epitaxial film growth on a semiconductor substrate

DOEpatents

Sheldon, P.; Hayes, R.E.

1984-12-04

Disclosed is a process for selectively patterning epitaxial film growth on a semiconductor substrate. The process includes forming a masking member on the surface of the substrate, the masking member having at least two layers including a first layer disposed on the substrate and the second layer covering the first layer. A window is then opened in a selected portion of the second layer by removing that portion to expose the first layer thereunder. The first layer is then subjected to an etchant introduced through the window to dissolve the first layer a sufficient amount to expose the substrate surface directly beneath the window, the first layer being adapted to preferentially dissolve at a substantially greater rate than the second layer so as to create an overhanging ledge portion with the second layer by undercutting the edges thereof adjacent the window. The epitaxial film is then deposited on the exposed substrate surface directly beneath the window. Finally, an etchant is introduced through the window to dissolve the remainder of the first layer so as to lift-off the second layer and materials deposited thereon to fully expose the balance of the substrate surface.

Process for selectively patterning epitaxial film growth on a semiconductor substrate

DOEpatents

Sheldon, Peter; Hayes, Russell E.

1986-01-01

A process is disclosed for selectively patterning epitaxial film growth on a semiconductor substrate. The process includes forming a masking member on the surface of the substrate, the masking member having at least two layers including a first layer disposed on the substrate and the second layer covering the first layer. A window is then opened in a selected portion of the second layer by removing that portion to expose the first layer thereunder. The first layer is then subjected to an etchant introduced through the window to dissolve a sufficient amount of the first layer to expose the substrate surface directly beneath the window, the first layer being adapted to preferentially dissolve at a substantially greater rate than the second layer so as to create an overhanging ledge portion with the second layer by undercutting the edges thereof adjacent to the window. The epitaxial film is then deposited on the exposed substrate surface directly beneath the window. Finally, an etchant is introduced through the window to dissolve the remainder of the first layer so as to lift-off the second layer and materials deposited thereon to fully expose the balance of the substrate surface.

Solid-state membrane module

DOEpatents

Hinklin, Thomas Ray; Lewinsohn, Charles Arthur

2015-06-30

A module for separating oxygen from an oxygen-containing gaseous mixture comprising planar solid-state membrane units, each membrane unit comprising planar dense mixed conducting oxides layers, planar channel-free porous support layers, and one or more planar intermediate support layers comprising at least one channeled porous support layer. The porosity of the planar channeled porous support layers is less than the porosity of the planar channel-free porous support layers.

Stacked Switchable Element and Diode Combination

DOEpatents

Branz, H. M.; Wang, Q.

2006-06-27

A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship so that the semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in response to the application of a forming voltage to the switchable element (14).

Metal-doped semiconductor nanoparticles and methods of synthesis thereof

NASA Technical Reports Server (NTRS)

Ren, Zhifeng (Inventor); Wang, Wenzhong (Inventor); Chen, Gang (Inventor); Dresselhaus, Mildred (Inventor); Poudel, Bed (Inventor); Kumar, Shankar (Inventor)

2009-01-01

The present invention generally relates to binary or higher order semiconductor nanoparticles doped with a metallic element, and thermoelectric compositions incorporating such nanoparticles. In one aspect, the present invention provides a thermoelectric composition comprising a plurality of nanoparticles each of which includes an alloy matrix formed of a Group IV element and Group VI element and a metallic dopant distributed within the matrix.

Metal-doped semiconductor nanoparticles and methods of synthesis thereof

DOEpatents

Ren, Zhifeng [Newton, MA; Chen, Gang [Carlisle, MA; Poudel, Bed [West Newton, MA; Kumar, Shankar [Newton, MA; Wang, Wenzhong [Beijing, CN; Dresselhaus, Mildred [Arlington, MA

2009-09-08

The present invention generally relates to binary or higher order semiconductor nanoparticles doped with a metallic element, and thermoelectric compositions incorporating such nanoparticles. In one aspect, the present invention provides a thermoelectric composition comprising a plurality of nanoparticles each of which includes an alloy matrix formed of a Group IV element and Group VI element and a metallic dopant distributed within the matrix.

Stacked switchable element and diode combination

DOEpatents

Branz, Howard M.; Wang, Qi

2006-06-27

A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship so that the semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in response to the application of a forming voltage to the switchable element (14).

Apparatus and methods of measuring minority carrier lifetime using a liquid probe

DOEpatents

Li, Jian

2016-04-12

Methods and apparatus for measuring minority carrier lifetimes using liquid probes are provided. In one embodiment, a method of measuring the minority carrier lifetime of a semiconductor material comprises: providing a semiconductor material having a surface; forming a rectifying junction at a first location on the surface by temporarily contacting the surface with a conductive liquid probe; electrically coupling a second junction to the semiconductor material at a second location, wherein the first location and the second location are physically separated; applying a forward bias to the rectifying junction causing minority carrier injection in the semiconductor material; measuring a total capacitance as a function of frequency between the rectifying junction and the second junction; determining an inflection frequency of the total capacitance; and determining a minority lifetime of the semiconductor material from the inflection frequency.

Effect of Water Vapor and Surface Morphology on the Low Temperature Response of Metal Oxide Semiconductor Gas Sensors

PubMed Central

Maier, Konrad; Helwig, Andreas; Müller, Gerhard; Hille, Pascal; Eickhoff, Martin

2015-01-01

In this work the low temperature response of metal oxide semiconductor gas sensors is analyzed. Important characteristics of this low-temperature response are a pronounced selectivity to acid- and base-forming gases and a large disparity of response and recovery time constants which often leads to an integrator-type of gas response. We show that this kind of sensor performance is related to the trend of semiconductor gas sensors to adsorb water vapor in multi-layer form and that this ability is sensitively influenced by the surface morphology. In particular we show that surface roughness in the nanometer range enhances desorption of water from multi-layer adsorbates, enabling them to respond more swiftly to changes in the ambient humidity. Further experiments reveal that reactive gases, such as NO2 and NH3, which are easily absorbed in the water adsorbate layers, are more easily exchanged across the liquid/air interface when the humidity in the ambient air is high. PMID:28793583

Regulation of depletion layer width in Pb(Zr,Ti)O3/Nb:SrTiO3 heterostructures

NASA Astrophysics Data System (ADS)

Bai, Yu; Jie Wang, Zhan; Cui, Jian Zhong; Zhang, Zhi Dong

2018-05-01

Improving the tunability of depletion layer width (DLW) in ferroelectric/semiconductor heterostructures is important for the performance of some devices. In this work, 200-nm-thick Pb(Zr0.4Ti0.6)O3 (PZT) films were deposited on different Nb-doped SrTiO3 (NSTO) substrates, and the tunability of DLW at PZT/NSTO interfaces were studied. Our results showed that the maximum tunability of the DLW was achieved at the NSTO substrate with 0.5 wt% Nb. On the basis of the modified capacitance model and the ferroelectric semiconductor theory, we suggest that the tunability of the DLW in PZT/NSTO heterostructures can be attributed to a delicate balance of the depletion layer charge and the ferroelectric polarization charge. Therefore, the performance of some devices related to the tunability of DLW in ferroelectric/semiconductor heterostructures can be improved by modulating the doping concentration in semiconducting electrode materials.

The effects of Bi4Ti3O12 interfacial ferroelectric layer on the dielectric properties of Au/n-Si structures

NASA Astrophysics Data System (ADS)

Gökçen, Muharrem; Yıldırım, Mert

2015-06-01

Au/n-Si metal-semiconductor (MS) and Au/Bi4Ti3O12/n-Si metal-ferroelectric-semiconductor (MFS) structures were fabricated and admittance measurements were held between 5 kHz and 1 MHz at room temperature so that dielectric properties of these structures could be investigated. The ferroelectric interfacial layer Bi4Ti3O12 decreased the polarization voltage by providing permanent dipoles at metal/semiconductor interface. Depending on different mechanisms, dispersion behavior was observed in dielectric constant, dielectric loss and loss tangent versus bias voltage plots of both MS and MFS structures. The real and imaginary parts of complex modulus of MFS structure take smaller values than those of MS structure, because permanent dipoles in ferroelectric layer cause a large spontaneous polarization mechanism. While the dispersion in AC conductivity versus frequency plots of MS structure was observed at high frequencies, for MFS structure it was observed at lower frequencies.

Formation of Ideal Rashba States on Layered Semiconductor Surfaces Steered by Strain Engineering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ming, Wenmei; Wang, Z. F.; Zhou, Miao

2015-12-10

Spin splitting of Rashba states in two-dimensional electron system provides a mechanism of spin manipulation for spintronics applications. However, Rashba states realized experimentally to date are often outnumbered by spin-degenerated substrate states at the same energy range, hindering their practical applications. Here, by density functional theory calculation, we show that Au one monolayer film deposition on a layered semiconductor surface β-InSe(0001) can possess “ideal” Rashba states with large spin splitting, which are completely situated inside the large band gap of the substrate. The position of the Rashba bands can be tuned over a wide range with respect to the substratemore » band edges by experimentally accessible strain. Furthermore, our nonequilibrium Green’s function transport calculation shows that this system may give rise to the long-sought strong current modulation when made into a device of Datta-Das transistor. Similar systems may be identified with other metal ultrathin films and layered semiconductor substrates to realize ideal Rashba states.« less

Visible light emitting vertical cavity surface emitting lasers

DOEpatents

Bryan, Robert P.; Olbright, Gregory R.; Lott, James A.; Schneider, Jr., Richard P.

1995-01-01

A vertical cavity surface emitting laser that emits visible radiation is built upon a substrate, then having mirrors, the first mirror on top of the substrate; both sets of mirrors being a distributed Bragg reflector of either dielectrics or other materials which affect the resistivity or of semiconductors, such that the structure within the mirror comprises a plurality of sets, each having a thickness of .lambda./2n where n is the index of refraction of each of the sets; each of the mirrors adjacent to spacers which are on either side of an optically active bulk or quantum well layer; and the spacers and the optically active layer are from one of the following material systems: In.sub.z (Al.sub.y Ga.sub.1-y).sub.1-z P, InAlGaAs, AlGaAs, InGaAs, or AlGaP/GaP, wherein the optically active region having a length equal to m .lambda./2n.sub.eff where m is an integer and n.sub.eff is the effective index of refraction of the laser cavity, and the spacer layer and one of the mirrors being transmissive to radiation having a wavelength of .lambda./n, typically within the green to red portion of the visible spectrum.

Visible light emitting vertical cavity surface emitting lasers

DOEpatents

Bryan, R.P.; Olbright, G.R.; Lott, J.A.; Schneider, R.P. Jr.

1995-06-27

A vertical cavity surface emitting laser that emits visible radiation is built upon a substrate, then having mirrors, the first mirror on top of the substrate; both sets of mirrors being a distributed Bragg reflector of either dielectrics or other materials which affect the resistivity or of semiconductors, such that the structure within the mirror comprises a plurality of sets, each having a thickness of {lambda}/2n where n is the index of refraction of each of the sets; each of the mirrors adjacent to spacers which are on either side of an optically active bulk or quantum well layer; and the spacers and the optically active layer are from one of the following material systems: In{sub z}(Al{sub y}Ga{sub 1{minus}y}){sub 1{minus}z}P, InAlGaAs, AlGaAs, InGaAs, or AlGaP/GaP, wherein the optically active region having a length equal to m {lambda}/2n{sub eff} where m is an integer and n{sub eff} is the effective index of refraction of the laser cavity, and the spacer layer and one of the mirrors being transmissive to radiation having a wavelength of {lambda}/n, typically within the green to red portion of the visible spectrum. 10 figs.

Development and characterization of semiconductor ion detectors for plasma diagnostics in the range over 0.3 keV

NASA Astrophysics Data System (ADS)

Cho, T.; Sakamoto, Y.; Hirata, M.; Kohagura, J.; Makino, K.; Kanke, S.; Takahashi, K.; Okamura, T.; Nakashima, Y.; Yatsu, K.; Tamano, T.; Miyoshi, S.

1997-01-01

For the purpose of plasma-ion-energy analyses in a wide-energy range from a few hundred eV to hundreds of keV, upgraded semiconductor detectors are newly fabricated and characterized using a test-ion-beam line from 0.3 to 12 keV. In particular, the detectable lowest-ion energy is drastically improved at least down to 0.3 keV; this energy is one to two orders-of-magnitude better than those for commercially available Si-surface-barrier diodes employed for previous plasma-ion diagnostics. A signal-to-noise ratio of two to three orders-of-magnitude better than that for usual metal-collector detectors is demonstrated for the compact-sized semiconductor along with the availability of the use under conditions of a good vacuum and a strong-magnetic field. Such characteristics are achieved due to the improving methods of the optimization of the thicknesses of a Si dead layer and a SiO2 layer, as well as the nitrogen-doping technique near the depletion layer along with minimizing impurity concentrations in Si. Such an upgraded capability of an extremely low-energy-ion detection with the low-noise characteristics enlarges research regimes of plasma-ion behavior using semiconductor detectors not only in the divertor regions of tokamaks but in wider spectra of open-field plasma devices including tandem mirrors. An application of the semiconductor ion detector for plasma-ion diagnostics is demonstrated in a specially designed ion-spectrometer structure.

Relating Structure to Efficiency in Surfactant-Free Polymer/Fullerene Nanoparticle-Based Organic Solar Cells.

PubMed

Gärtner, Stefan; Clulow, Andrew J; Howard, Ian A; Gilbert, Elliot P; Burn, Paul L; Gentle, Ian R; Colsmann, Alexander

2017-12-13

Nanoparticle dispersions open up an ecofriendly route toward printable organic solar cells. They can be formed from a variety of organic semiconductors by using miniemulsions that employ surfactants to stabilize the nanoparticles in dispersion and to prevent aggregation. However, whenever surfactant-based nanoparticle dispersions have been used to fabricate solar cells, the reported performances remain moderate. In contrast, solar cells from nanoparticle dispersions formed by precipitation (without surfactants) can exhibit power conversion efficiencies close to those of state-of-the-art solar cells processed from blend solutions using chlorinated solvents. In this work, we use small-angle neutron scattering measurements and transient absorption spectroscopy to investigate why surfactant-free nanoparticles give rise to efficient organic solar cells. We show that surfactant-free nanoparticles comprise a uniform distribution of small semiconductor domains, similar to that of bulk-heterojunction films formed using traditional solvent processing. This observation differs from surfactant-based miniemulsion nanoparticles that typically exhibit core-shell structures. Hence, the surfactant-free nanoparticles already possess the optimum morphology for efficient energy conversion before they are assembled into the photoactive layer of a solar cell. This structural property underpins the superior performance of the solar cells containing surfactant-free nanoparticles and is an important design criterion for future nanoparticle inks.

Multilayer Article Characterized by Low Coefficient of Thermal Expansion Outer Layer

NASA Technical Reports Server (NTRS)

Lee, Kang N. (Inventor)

2004-01-01

A multilayer article comprises a substrate comprising a ceramic or a silicon-containing metal alloy. The ceramic is a Si-containing ceramic or an oxide ceramic with or without silicon. An outer layer overlies the substrate and at least one intermediate layer is located between the outer layer and thc substrate. An optional bond layer is disposed between thc 1 least one intermediate layer and thc substrate. The at least one intermediate layer may comprise an optional chemical barrier layer adjacent the outer layer, a mullite-containing layer and an optional chemical barrier layer adjacent to the bond layer or substrate. The outer layer comprises a compound having a low coefficient of thermal expansion selected from one of the following systems: rare earth (RE) silicates; at least one of hafnia and hafnia-containing composite oxides; zirconia-containing composite oxides and combinations thereof.

Thin film photovoltaic device

DOEpatents

Catalano, A.W.; Bhushan, M.

1982-08-03

A thin film photovoltaic solar cell which utilizes a zinc phosphide semiconductor is of the homojunction type comprising an n-type conductivity region forming an electrical junction with a p-type region, both regions consisting essentially of the same semiconductor material. The n-type region is formed by treating zinc phosphide with an extrinsic dopant such as magnesium. The semiconductor is formed on a multilayer substrate which acts as an opaque contact. Various transparent contacts may be used, including a thin metal film of the same chemical composition as the n-type dopant or conductive oxides or metal grids. 5 figs.

Screenable contact structure and method for semiconductor devices

DOEpatents

Ross, Bernd

1980-08-26

An ink composition for deposition upon the surface of a semiconductor device to provide a contact area for connection to external circuitry is disclosed, the composition comprising an ink system containing a metal powder, a binder and vehicle, and a metal frit. The ink is screened onto the semiconductor surface in the desired pattern and is heated to a temperature sufficient to cause the metal frit to become liquid. The metal frit dissolves some of the metal powder and densifies the structure by transporting the dissolved metal powder in a liquid sintering process. The sintering process typically may be carried out in any type of atmosphere. A small amount of dopant or semiconductor material may be added to the ink systems to achieve particular results if desired.

Investigation of defect modes in a defective photonic crystal with a semiconductor metamaterial defect

NASA Astrophysics Data System (ADS)

Wu, Meng-Ru; Wu, Chien-Jang; Chang, Shoou-Jinn

2014-11-01

In this work, we theoretically investigate the properties of defect modes in a defective photonic crystal containing a semiconductor metamaterial defect. We consider the structure, (LH)N/DP/(LH)N, where N and P are respectively the stack numbers, L is SiO2, H is InP, and defect layer D is a semiconductor metamaterial composed of Al-doped ZnO (AZO) and ZnO. It is found that, within the photonic band gap, the number of defect modes (transmission peaks) will decrease as the defect thickness increases, in sharp contrast to the case of using usual dielectric defect. The peak height and position can be changed by the variation in the thickness of defect layer. In the angle-dependent defect mode, its position is shown to be blue-shifted as the angle of incidence increases for both TE and TM waves. The analysis of defect mode provides useful information for the design of tunable transmission filter in semiconductor optoelectronics.

Surface hole gas enabled transparent deep ultraviolet light-emitting diode

NASA Astrophysics Data System (ADS)

Zhang, Jianping; Gao, Ying; Zhou, Ling; Gil, Young-Un; Kim, Kyoung-Min

2018-07-01

The inherent deep-level nature of acceptors in wide-band-gap semiconductors makes p-ohmic contact formation and hole supply difficult, impeding progress for short-wavelength optoelectronics and high-power high-temperature bipolar electronics. We provide a general solution by demonstrating an ultrathin rather than a bulk wide-band-gap semiconductor to be a successful hole supplier and ohmic contact layer. Free holes in this ultrathin semiconductor are assisted to activate from deep acceptors and swept to surface to form hole gases by a large electric field, which can be provided by engineered spontaneous and piezoelectric polarizations. Experimentally, a 6 nm thick AlN layer with surface hole gas had formed p-ohmic contact to metals and provided sufficient hole injection to a 280 nm light-emitting diode, demonstrating a record electrical-optical conversion efficiency exceeding 8.5% at 20 mA (55 A cm‑2). Our approach of forming p-type wide-band-gap semiconductor ohmic contact is critical to realizing high-efficiency ultraviolet optoelectronic devices.

Chemical-mechanical polishing of recessed microelectromechanical devices

DOEpatents

Barron, Carole C.; Hetherington, Dale L.; Montague, Stephen

1999-01-01

A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g. CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate.

Micro-fabricated integrated coil and magnetic circuit and method of manufacturing thereof

DOEpatents

Mihailovich, Robert E.; Papavasiliou, Alex P.; Mehrotra, Vivek; Stupar, Philip A.; Borwick, III, Robert L.; Ganguli, Rahul; DeNatale, Jeffrey F.

2017-03-28

A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material.

Chemical-mechanical polishing of recessed microelectromechanical devices

DOEpatents

Barron, C.C.; Hetherington, D.L.; Montague, S.

1999-07-06

A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g., CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate. 23 figs.

Charge transfer at organic-inorganic interfaces—Indoline layers on semiconductor substrates

NASA Astrophysics Data System (ADS)

Meyenburg, I.; Falgenhauer, J.; Rosemann, N. W.; Chatterjee, S.; Schlettwein, D.; Heimbrodt, W.

2016-12-01

We studied the electron transfer from excitons in adsorbed indoline dye layers across the organic-inorganic interface. The hybrids consist of indoline derivatives on the one hand and different inorganic substrates (TiO2, ZnO, SiO2(0001), fused silica) on the other. We reveal the electron transfer times from excitons in dye layers to the organic-inorganic interface by analyzing the photoluminescence transients of the dye layers after femtosecond excitation and applying kinetic model calculations. A correlation between the transfer times and four parameters have been found: (i) the number of anchoring groups, (ii) the distance between the dye and the organic-inorganic interface, which was varied by the alkyl-chain lengths between the carboxylate anchoring group and the dye, (iii) the thickness of the adsorbed dye layer, and (iv) the level alignment between the excited dye ( π* -level) and the conduction band minimum of the inorganic semiconductor.

Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

PubMed

Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2018-05-08

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

Superheating Suppresses Structural Disorder in Layered BiI3 Semiconductors Grown by the Bridgman Method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johns, Paul M.; Sulekar, Soumitra; Yeo, Shinyoung

2016-01-01

The susceptibility of layered structures to stacking faults is a problem in some of the more attractive semiconductor materials for ambient-temperature radiation detectors. In the work presented here, Bridgman-grown BiI3 layered single crystals are investigated to understand and eliminate this structural disorder, which reduces radiation detector performance. The use of superheating gradients has been shown to improve crystal quality in non-layered semiconductor crystals; thus the technique was here explored to improve the growth of BiI3. When investigating the homogeneity of non-superheated crystals, highly geometric void defects were found to populate the bulk of the crystals. Applying a superheating gradient tomore » the melt prior to crystal growth improved structural quality and decreased defect density from the order of 4600 voids per cm3 to 300 voids per cm3. Corresponding moderate improvements to electronic properties also resulted from the superheat gradient method of crystal growth. Comparative measurements through infrared microscopy, etch-pit density, x-ray rocking curves, and sheet resistivity readings show that superheat gradients in BiI3 growth led to higher quality crystals.« less

Intracavity double diode structures with GaInP barrier layers for thermophotonic cooling

NASA Astrophysics Data System (ADS)

Tiira, Jonna; Radevici, Ivan; Haggren, Tuomas; Hakkarainen, Teemu; Kivisaari, Pyry; Lyytikäinen, Jari; Aho, Arto; Tukiainen, Antti; Guina, Mircea; Oksanen, Jani

2017-02-01

Optical cooling of semiconductors has recently been demonstrated both for optically pumped CdS nanobelts and for electrically injected GaInAsSb LEDs at very low powers. To enable cooling at larger power and to understand and overcome the main obstacles in optical cooling of conventional semiconductor structures, we study thermophotonic (TPX) heat transport in cavity coupled light emitters. Our structures consist of a double heterojunction (DHJ) LED with a GaAs active layer and a corresponding DHJ or a p-n-homojunction photodiode, enclosed within a single semiconductor cavity to eliminate the light extraction challenges. Our presently studied double diode structures (DDS) use GaInP barriers around the GaAs active layer instead of the AlGaAs barriers used in our previous structures. We characterize our updated double diode structures by four point probe IV- measurements and measure how the material modifications affect the recombination parameters and coupling quantum efficiencies in the structures. The coupling quantum efficiency of the new devices with InGaP barrier layers is found to be approximately 10 % larger than for the structures with AlGaAs barriers at the point of maximum efficiency.

Optical bandgap of single- and multi-layered amorphous germanium ultra-thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Pei; Zaslavsky, Alexander; Longo, Paolo

2016-01-07

Accurate optical methods are required to determine the energy bandgap of amorphous semiconductors and elucidate the role of quantum confinement in nanometer-scale, ultra-thin absorbing layers. Here, we provide a critical comparison between well-established methods that are generally employed to determine the optical bandgap of thin-film amorphous semiconductors, starting from normal-incidence reflectance and transmittance measurements. First, we demonstrate that a more accurate estimate of the optical bandgap can be achieved by using a multiple-reflection interference model. We show that this model generates more reliable results compared to the widely accepted single-pass absorption method. Second, we compare two most representative methods (Taucmore » and Cody plots) that are extensively used to determine the optical bandgap of thin-film amorphous semiconductors starting from the extracted absorption coefficient. Analysis of the experimental absorption data acquired for ultra-thin amorphous germanium (a-Ge) layers demonstrates that the Cody model is able to provide a less ambiguous energy bandgap value. Finally, we apply our proposed method to experimentally determine the optical bandgap of a-Ge/SiO{sub 2} superlattices with single and multiple a-Ge layers down to 2 nm thickness.« less

Atomic-order thermal nitridation of group IV semiconductors for ultra-large-scale integration

NASA Astrophysics Data System (ADS)

Murota, Junichi; Le Thanh, Vinh

2015-03-01

One of the main requirements for ultra-large-scale integration (ULSI) is atomic-order control of process technology. Our concept of atomically controlled processing for group IV semiconductors is based on atomic-order surface reaction control in Si-based CVD epitaxial growth. On the atomic-order surface nitridation of a few nm-thick Ge/about 4 nm-thick Si0.5Ge0.5/Si(100) by NH3, it is found that N atoms diffuse through nm-order thick Ge layer into Si0.5Ge0.5/Si(100) substrate and form Si nitride, even at 500 °C. By subsequent H2 heat treatment, although N atomic amount in Ge layer is reduced drastically, the reduction of the Si nitride is slight. It is suggested that N diffusion in Ge layer is suppressed by the formation of Si nitride and that Ge/atomic-order N layer/Si1-xGex/Si (100) heterostructure is formed. These results demonstrate the capability of CVD technology for atomically controlled nitridation of group IV semiconductors for ultra-large-scale integration. Invited talk at the 7th International Workshop on Advanced Materials Science and Nanotechnology IWAMSN2014, 2-6 November, 2014, Ha Long, Vietnam.

Removal of GaAs growth substrates from II-VI semiconductor heterostructures

NASA Astrophysics Data System (ADS)

Bieker, S.; Hartmann, P. R.; Kießling, T.; Rüth, M.; Schumacher, C.; Gould, C.; Ossau, W.; Molenkamp, L. W.

2014-04-01

We report on a process that enables the removal of II-VI semiconductor epilayers from their GaAs growth substrate and their subsequent transfer to arbitrary host environments. The technique combines mechanical lapping and layer selective chemical wet etching and is generally applicable to any II-VI layer stack. We demonstrate the non-invasiveness of the method by transferring an all-II-VI magnetic resonant tunneling diode. High resolution x-ray diffraction proves that the crystal integrity of the heterostructure is preserved. Transport characterization confirms that the functionality of the device is maintained and even improved, which is ascribed to completely elastic strain relaxation of the tunnel barrier layer.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

Metal-insulator-semiconductor heterostructures for plasmonic hot-carrier optoelectronics.

PubMed

García de Arquer, F Pelayo; Konstantatos, Gerasimos

2015-06-01

Plasmonic hot-electron devices are attractive candidates for light-energy harvesting and photodetection applications. For solid state devices, the most compact and straightforward architecture is the metal-semiconductor Schottky junction. However convenient, this structure introduces limitations such as the elevated dark current associated to thermionic emission, or constraints for device design due to the finite choice of materials. In this work we theoretically consider the metal-insulator-semiconductor heterojunction as a candidate for plasmonic hot-carrier photodetection and solar cells. The presence of the insulating layer can significantly reduce the dark current, resulting in increased device performance with predicted solar power conversion efficiencies up to 9%. For photodetection, the sensitivity can be extended well into the infrared by a judicious choice of the insulating layer, with up to 300-fold expected enhancement in detectivity.

Ultrathin metal-semiconductor-metal resonator for angle invariant visible band transmission filters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Kyu-Tae; Seo, Sungyong; Yong Lee, Jae

We present transmission visible wavelength filters based on strong interference behaviors in an ultrathin semiconductor material between two metal layers. The proposed devices were fabricated on 2 cm × 2 cm glass substrate, and the transmission characteristics show good agreement with the design. Due to a significantly reduced light propagation phase change associated with the ultrathin semiconductor layer and the compensation in phase shift of light reflecting from the metal surface, the filters show an angle insensitive performance up to ±70°, thus, addressing one of the key challenges facing the previously reported photonic and plasmonic color filters. This principle, described in this paper, canmore » have potential for diverse applications ranging from color display devices to the image sensors.« less

Coaxial metal-oxide-semiconductor (MOS) Au/Ga2O3/GaN nanowires.

PubMed

Hsieh, Chin-Hua; Chang, Mu-Tung; Chien, Yu-Jen; Chou, Li-Jen; Chen, Lih-Juann; Chen, Chii-Dong

2008-10-01

Coaxial metal-oxide-semiconductor (MOS) Au-Ga2O3-GaN heterostructure nanowires were successfully fabricated by an in situ two-step process. The Au-Ga2O3 core-shell nanowires were first synthesized by the reaction of Ga powder, a mediated Au thin layer, and a SiO2 substrate at 800 degrees C. Subsequently, these core-shell nanowires were nitridized in ambient ammonia to form a GaN coating layer at 600 degrees C. The GaN shell is a single crystal, an atomic flat interface between the oxide and semiconductor that ensures that the high quality of the MOS device is achieved. These novel 1D nitride-based MOS nanowires may have promise as building blocks to the future nitride-based vertical nanodevices.

Composite metal foil and ceramic fabric materials

DOEpatents

Webb, B.J.; Antoniak, Z.I.; Prater, J.T.; DeSteese, J.G.

1992-03-24

The invention comprises new materials useful in a wide variety of terrestrial and space applications. In one aspect, the invention comprises a flexible cloth-like material comprising a layer of flexible woven ceramic fabric bonded with a layer of metallic foil. In another aspect, the invention includes a flexible fluid impermeable barrier comprising a flexible woven ceramic fabric layer having metal wire woven therein. A metallic foil layer is incontinuously welded to the woven metal wire. In yet another aspect, the invention includes a material comprising a layer of flexible woven ceramic fabric bonded with a layer of an organic polymer. In still another aspect, the invention includes a rigid fabric structure comprising a flexible woven ceramic fabric and a resinous support material which has been hardened as the direct result of exposure to ultraviolet light. Inventive methods for producing such material are also disclosed. 11 figs.

Layer-by-layer modification of thin-film metal-semiconductor multilayers with ultrashort laser pulses

NASA Astrophysics Data System (ADS)

Romashevskiy, S. A.; Tsygankov, P. A.; Ashitkov, S. I.; Agranat, M. B.

2018-05-01

The surface modifications in a multilayer thin-film structure (50-nm alternating layers of Si and Al) induced by a single Gaussian-shaped femtosecond laser pulse (350 fs, 1028 nm) in the air are investigated by means of atomic-force microscopy (AFM), scanning electron microscopy (SEM), and optical microscopy (OM). Depending on the laser fluence, various modifications of nanometer-scale metal and semiconductor layers, including localized formation of silicon/aluminum nanofoams and layer-by-layer removal, are found. While the nanofoams with cell sizes in the range of tens to hundreds of nanometers are produced only in the two top layers, layer-by-layer removal is observed for the four top layers under single pulse irradiation. The 50-nm films of the multilayer structure are found to be separated at their interfaces, resulting in a selective removal of several top layers (up to 4) in the form of step-like (concentric) craters. The observed phenomenon is associated with a thermo-mechanical ablation mechanism that results in splitting off at film-film interface, where the adhesion force is less than the bulk strength of the used materials, revealing linear dependence of threshold fluences on the film thickness.

Wafer-fused semiconductor radiation detector

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Dielectric Covered Planar Antennas

NASA Technical Reports Server (NTRS)

Llombart Juan, Nuria (Inventor); Lee, Choonsup (Inventor); Chattopadhyay, Goutam (Inventor); Gill, John J. (Inventor); Skalare, Anders J. (Inventor); Siegel, Peter H. (Inventor)

2014-01-01

An antenna element suitable for integrated arrays at terahertz frequencies is disclosed. The antenna element comprises an extended spherical (e.g. hemispherical) semiconductor lens, e.g. silicon, antenna fed by a leaky wave waveguide feed. The extended spherical lens comprises a substantially spherical lens adjacent a substantially planar lens extension. A couple of TE/TM leaky wave modes are excited in a resonant cavity formed between a ground plane and the substantially planar lens extension by a waveguide block coupled to the ground plane. Due to these modes, the primary feed radiates inside the lens with a directive pattern that illuminates a small sector of the lens. The antenna structure is compatible with known semiconductor fabrication technology and enables production of large format imaging arrays.

Low-Resistivity Zinc Selenide for Heterojunctions

NASA Technical Reports Server (NTRS)

Stirn, R. J.

1986-01-01

Magnetron reactive sputtering enables doping of this semiconductor. Proposed method of reactive sputtering combined with doping shows potential for yielding low-resistivity zinc selenide films. Zinc selenide attractive material for forming heterojunctions with other semiconductor compounds as zinc phosphide, cadmium telluride, and gallium arsenide. Semiconductor junctions promising for future optoelectronic devices, including solar cells and electroluminescent displays. Resistivities of zinc selenide layers deposited by evaporation or chemical vapor deposition too high to form practical heterojunctions.

Inversion layer MOS solar cells

NASA Technical Reports Server (NTRS)

Ho, Fat Duen

1986-01-01

Inversion layer (IL) Metal Oxide Semiconductor (MOS) solar cells were fabricated. The fabrication technique and problems are discussed. A plan for modeling IL cells is presented. Future work in this area is addressed.

Planar heterostructures of single-layer transition metal dichalcogenides: Composite structures, Schottky junctions, tunneling barriers, and half metals

NASA Astrophysics Data System (ADS)

Aras, Mehmet; Kılıç, ćetin; Ciraci, S.

2017-02-01

Planar composite structures formed from the stripes of transition metal dichalcogenides joined commensurately along their zigzag or armchair edges can attain different states in a two-dimensional (2D), single-layer, such as a half metal, 2D or one-dimensional (1D) nonmagnetic metal and semiconductor. Widening of stripes induces metal-insulator transition through the confinements of electronic states to adjacent stripes, that results in the metal-semiconductor junction with a well-defined band lineup. Linear bending of the band edges of the semiconductor to form a Schottky barrier at the boundary between the metal and semiconductor is revealed. Unexpectedly, strictly 1D metallic states develop in a 2D system along the boundaries between stripes, which pins the Fermi level. Through the δ doping of a narrow metallic stripe one attains a nanowire in the 2D semiconducting sheet or narrow band semiconductor. A diverse combination of constituent stripes in either periodically repeating or finite-size heterostructures can acquire critical fundamental features and offer device capacities, such as Schottky junctions, nanocapacitors, resonant tunneling double barriers, and spin valves. These predictions are obtained from first-principles calculations performed in the framework of density functional theory.

Semiconductor projectile impact detector

NASA Technical Reports Server (NTRS)

Shriver, E. L. (Inventor)

1977-01-01

A semiconductor projectile impact detector is described for use in determining micrometeorite presence, as well as its flux and energy comprising a photovoltaic cell which generates a voltage according to the light and heat emitted by the micrometeorites upon impact. A counter and peak amplitude measuring device were used to indicate the number of particules which strike the surface of the cell as well as the kinetic energy of each of the particles.

Stacked switchable element and diode combination with a low breakdown switchable element

DOEpatents

Wang, Qi [Littleton, CO; Ward, James Scott [Englewood, CO; Hu, Jian [Englewood, CO; Branz, Howard M [Boulder, CO

2012-06-19

A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship. The semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in response to the application of a low-density forming current and/or a low voltage.

Photon induced non-linear quantized double layer charging in quaternary semiconducting quantum dots.

PubMed

Nair, Vishnu; Ananthoju, Balakrishna; Mohapatra, Jeotikanta; Aslam, M

2018-03-15

Room temperature quantized double layer charging was observed in 2 nm Cu 2 ZnSnS 4 (CZTS) quantum dots. In addition to this we observed a distinct non-linearity in the quantized double layer charging arising from UV light modulation of double layer. UV light irradiation resulted in a 26% increase in the integral capacitance at the semiconductor-dielectric (CZTS-oleylamine) interface of the quantum dot without any change in its core size suggesting that the cause be photocapacitive. The increasing charge separation at the semiconductor-dielectric interface due to highly stable and mobile photogenerated carriers cause larger electrostatic forces between the quantum dot and electrolyte leading to an enhanced double layer. This idea was supported by a decrease in the differential capacitance possible due to an enhanced double layer. Furthermore the UV illumination enhanced double layer gives us an AC excitation dependent differential double layer capacitance which confirms that the charging process is non-linear. This ultimately illustrates the utility of a colloidal quantum dot-electrolyte interface as a non-linear photocapacitor. Copyright © 2017 Elsevier Inc. All rights reserved.

Determination of layer-dependent exciton binding energies in few-layer black phosphorus

PubMed Central

Zhang, Guowei; Chaves, Andrey; Huang, Shenyang; Wang, Fanjie; Xing, Qiaoxia; Low, Tony; Yan, Hugen

2018-01-01

The attraction between electrons and holes in semiconductors forms excitons, which largely determine the optical properties of the hosting material, and hence the device performance, especially for low-dimensional systems. Mono- and few-layer black phosphorus (BP) are emerging two-dimensional (2D) semiconductors. Despite its fundamental importance and technological interest, experimental investigation of exciton physics has been rather limited. We report the first systematic measurement of exciton binding energies in ultrahigh-quality few-layer BP by infrared absorption spectroscopy, with layer (L) thickness ranging from 2 to 6 layers. Our experiments allow us to determine the exciton binding energy, decreasing from 213 meV (2L) to 106 meV (6L). The scaling behavior with layer numbers can be well described by an analytical model, which takes into account the nonlocal screening effect. Extrapolation to free-standing monolayer yields a large binding energy of ~800 meV. Our study provides insights into 2D excitons and their crossover from 2D to 3D, and demonstrates that few-layer BP is a promising high-quality optoelectronic material for potential infrared applications. PMID:29556530

Semiconductor-based optical refrigerator

DOEpatents

Epstein, Richard I.; Edwards, Bradley C.; Sheik-Bahae, Mansoor

2002-01-01

Optical refrigerators using semiconductor material as a cooling medium, with layers of material in close proximity to the cooling medium that carries away heat from the cooling material and preventing radiation trapping. In addition to the use of semiconducting material, the invention can be used with ytterbium-doped glass optical refrigerators.

Metallization for Yb14MnSb11-Based Thermoelectric Materials

NASA Technical Reports Server (NTRS)

Firdosy, Samad; Li, Billy Chun-Yip; Ravi, Vilupanur; Sakamoto, Jeffrey; Caillat, Thierry; Ewell, Richard C.; Brandon, Erik J.

2011-01-01

Thermoelectric materials provide a means for converting heat into electrical power using a fully solid-state device. Power-generating devices (which include individual couples as well as multicouple modules) require the use of ntype and p-type thermoelectric materials, typically comprising highly doped narrow band-gap semiconductors which are connected to a heat collector and electrodes. To achieve greater device efficiency and greater specific power will require using new thermoelectric materials, in more complex combinations. One such material is the p-type compound semiconductor Yb14MnSb11 (YMS), which has been demonstrated to have one of the highest ZT values at 1,000 C, the desired operational temperature of many space-based radioisotope thermoelectric generators (RTGs). Despite the favorable attributes of the bulk YMS material, it must ultimately be incorporated into a power-generating device using a suitable joining technology. Typically, processes such as diffusion bonding and/or brazing are used to join thermoelectric materials to the heat collector and electrodes, with the goal of providing a stable, ohmic contact with high thermal conductivity at the required operating temperature. Since YMS is an inorganic compound featuring chemical bonds with a mixture of covalent and ionic character, simple metallurgical diffusion bonding is difficult to implement. Furthermore, the Sb within YMS readily reacts with most metals to form antimonide compounds with a wide range of stoichiometries. Although choosing metals that react to form high-melting-point antimonides could be employed to form a stable reaction bond, it is difficult to limit the reactivity of Sb in YMS such that the electrode is not completely consumed at an operating temperature of 1,000 C. Previous attempts to form suitable metallization layers resulted in poor bonding, complete consumption of the metallization layer or fracture within the YMS thermoelement (or leg).