Photovoltaic cell with nano-patterned substrate

DOEpatents

Cruz-Campa, Jose Luis; Zhou, Xiaowang; Zubia, David

2016-10-18

A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, deceased, Roger J.; Dawson, Ralph; Fritz, Ian J.; Osbourn, Gordon C.; Zipperian, Thomas E.

1989-01-01

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space which includes a lowest energy .GAMMA.-valley and a next lowest energy L-valley, each k-vector corresponding to one of the orthogonal directions defined by the planes of said layers and the directions perpendicular thereto. The layer thicknesses of the quantum well layers are selected to provide a superlattice L.sub.2D -valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley.

Method of making silicon on insalator material using oxygen implantation

DOEpatents

Hite, Larry R.; Houston, Ted; Matloubian, Mishel

1989-01-01

The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dahal, Rajendra P.; Bhat, Ishwara B.; Chow, Tat-Sing

Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.

Silicon Alignment Pins: An Easy Way to Realize a Wafer-To-Wafer Alignment

NASA Technical Reports Server (NTRS)

Peralta, Alejandro (Inventor); Gill, John J. (Inventor); Toda, Risaku (Inventor); Lin, Robert H. (Inventor); Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Thomas, Bertrand (Inventor); Siles, Jose V. (Inventor); Lee, Choonsup (Inventor); Chattopadhyay, Goutam (Inventor)

2016-01-01

A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Planar heterostructures of single-layer transition metal dichalcogenides: Composite structures, Schottky junctions, tunneling barriers, and half metals

NASA Astrophysics Data System (ADS)

Aras, Mehmet; Kılıç, ćetin; Ciraci, S.

2017-02-01

Planar composite structures formed from the stripes of transition metal dichalcogenides joined commensurately along their zigzag or armchair edges can attain different states in a two-dimensional (2D), single-layer, such as a half metal, 2D or one-dimensional (1D) nonmagnetic metal and semiconductor. Widening of stripes induces metal-insulator transition through the confinements of electronic states to adjacent stripes, that results in the metal-semiconductor junction with a well-defined band lineup. Linear bending of the band edges of the semiconductor to form a Schottky barrier at the boundary between the metal and semiconductor is revealed. Unexpectedly, strictly 1D metallic states develop in a 2D system along the boundaries between stripes, which pins the Fermi level. Through the δ doping of a narrow metallic stripe one attains a nanowire in the 2D semiconducting sheet or narrow band semiconductor. A diverse combination of constituent stripes in either periodically repeating or finite-size heterostructures can acquire critical fundamental features and offer device capacities, such as Schottky junctions, nanocapacitors, resonant tunneling double barriers, and spin valves. These predictions are obtained from first-principles calculations performed in the framework of density functional theory.

Architectures and criteria for the design of high efficiency organic photovoltaic cells

DOEpatents

Rand, Barry; Forrest, Stephen R; Burk, Diana Pendergrast

2015-03-24

An organic photovoltaic cell includes an anode and a cathode, and a plurality of organic semiconductor layers between the anode and the cathode. At least one of the anode and the cathode is transparent. Each two adjacent layers of the plurality of organic semiconductor layers are in direct contact. The plurality of organic semiconductor layers includes an intermediate layer consisting essentially of a photoconductive material, and two sets of at least three layers. A first set of at least three layers is between the intermediate layer and the anode. Each layer of the first set consists essentially of a different organic semiconductor material having a higher LUMO and a higher HOMO, relative to the material of an adjacent layer of the plurality of organic semiconductor layers closer to the cathode. A second set of at least three layers is between the intermediate layer and the cathode. Each layer of the second set consists essentially of a different organic semiconductor material having a lower LUMO and a lower HOMO, relative to the material of an adjacent layer of the plurality of organic semiconductor layers closer to the anode.

Method of producing strained-layer semiconductor devices via subsurface-patterning

DOEpatents

Dodson, Brian W.

1993-01-01

A method is described for patterning subsurface features in a semiconductor device, wherein the semiconductor device includes an internal strained layer. The method comprises creating a pattern of semiconductor material over the semiconductor device, the semiconductor material having a predetermined thickness which stabilizes areas of the strained semiconductor layer that lie beneath the pattern. Subsequently, a heating step is applied to the semiconductor device to cause a relaxation in areas of the strained layer which do not lie beneath the semiconductor material pattern, whereby dislocations result in the relaxed areas and impair electrical transport therethrough.

Method of transferring a thin crystalline semiconductor layer

DOEpatents

Nastasi, Michael A [Sante Fe, NM; Shao, Lin [Los Alamos, NM; Theodore, N David [Mesa, AZ

2006-12-26

A method for transferring a thin semiconductor layer from one substrate to another substrate involves depositing a thin epitaxial monocrystalline semiconductor layer on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the thin semiconductor layer is bonded to a second substrate and the thin layer is separated away at the interface, which results in transferring the thin epitaxial semiconductor layer from one substrate to the other substrate.

Variable temperature semiconductor film deposition

DOEpatents

Li, X.; Sheldon, P.

1998-01-27

A method of depositing a semiconductor material on a substrate is disclosed. The method sequentially comprises (a) providing the semiconductor material in a depositable state such as a vapor for deposition on the substrate; (b) depositing the semiconductor material on the substrate while heating the substrate to a first temperature sufficient to cause the semiconductor material to form a first film layer having a first grain size; (c) continually depositing the semiconductor material on the substrate while cooling the substrate to a second temperature sufficient to cause the semiconductor material to form a second film layer deposited on the first film layer and having a second grain size smaller than the first grain size; and (d) raising the substrate temperature, while either continuing or not continuing to deposit semiconductor material to form a third film layer, to thereby anneal the film layers into a single layer having favorable efficiency characteristics in photovoltaic applications. A preferred semiconductor material is cadmium telluride deposited on a glass/tin oxide substrate already having thereon a film layer of cadmium sulfide.

Variable temperature semiconductor film deposition

DOEpatents

Li, Xiaonan; Sheldon, Peter

1998-01-01

A method of depositing a semiconductor material on a substrate. The method sequentially comprises (a) providing the semiconductor material in a depositable state such as a vapor for deposition on the substrate; (b) depositing the semiconductor material on the substrate while heating the substrate to a first temperature sufficient to cause the semiconductor material to form a first film layer having a first grain size; (c) continually depositing the semiconductor material on the substrate while cooling the substrate to a second temperature sufficient to cause the semiconductor material to form a second film layer deposited on the first film layer and having a second grain size smaller than the first grain size; and (d) raising the substrate temperature, while either continuing or not continuing to deposit semiconductor material to form a third film layer, to thereby anneal the film layers into a single layer having favorable efficiency characteristics in photovoltaic applications. A preferred semiconductor material is cadmium telluride deposited on a glass/tin oxide substrate already having thereon a film layer of cadmium sulfide.

Density-Gradient Theory: A Macroscopic Approach to Quantum Confinement and Tunneling in Semiconductor Devices

DTIC Science & Technology

2011-01-01

that are attractive as luminescent biolabels, and possibly also for optoelectronic devices and solar cells . The equilibrium nature of such situations...The boundary layers as- sociated with the diffusion and Debye lengths are familiar, while that of LQ defines the layer in which the quantum in...circuits, transmission lines Diffusion -drift, density-gradient Semi-classical electron dynamics, Boltzmann transport Schrödinger, density- matrix, Wigner

Laser warning receiver to identify the wavelength and angle of arrival of incident laser light

DOEpatents

Sinclair; Michael B.; Sweatt, William C.

2010-03-23

A laser warning receiver is disclosed which has up to hundreds of individual optical channels each optically oriented to receive laser light from a different angle of arrival. Each optical channel has an optical wedge to define the angle of arrival, and a lens to focus the laser light onto a multi-wavelength photodetector for that channel. Each multi-wavelength photodetector has a number of semiconductor layers which are located in a multi-dielectric stack that concentrates the laser light into one of the semiconductor layers according to wavelength. An electrical signal from the multi-wavelength photodetector can be processed to determine both the angle of arrival and the wavelength of the laser light.

Semiconductor nanocrystal-based phagokinetic tracking

DOEpatents

Alivisatos, A Paul; Larabell, Carolyn A; Parak, Wolfgang J; Le Gros, Mark; Boudreau, Rosanne

2014-11-18

Methods for determining metabolic properties of living cells through the uptake of semiconductor nanocrystals by cells. Generally the methods require a layer of neutral or hydrophilic semiconductor nanocrystals and a layer of cells seeded onto a culture surface and changes in the layer of semiconductor nanocrystals are detected. The observed changes made to the layer of semiconductor nanocrystals can be correlated to such metabolic properties as metastatic potential, cell motility or migration.

Group I-III-VI.sub.2 semiconductor films for solar cell application

DOEpatents

Basol, Bulent M.; Kapur, Vijay K.

1991-01-01

This invention relates to an improved thin film solar cell with excellent electrical and mechanical integrity. The device comprises a substrate, a Group I-III-VI.sub.2 semiconductor absorber layer and a transparent window layer. The mechanical bond between the substrate and the Group I-III-VI.sub.2 semiconductor layer is enhanced by an intermediate layer between the substrate and the Group I-III-VI.sub.2 semiconductor film being grown. The intermediate layer contains tellurium or substitutes therefor, such as Se, Sn, or Pb. The intermediate layer improves the morphology and electrical characteristics of the Group I-III-VI.sub.2 semiconductor layer.

Buried Porous Silicon-Germanium Layers in Monocrystalline Silicon Lattices

NASA Technical Reports Server (NTRS)

Fathauer, Robert W. (Inventor); George, Thomas (Inventor); Jones, Eric W. (Inventor)

1998-01-01

Monocrystalline semiconductor lattices with a buried porous semiconductor layer having different chemical composition is discussed and monocrystalline semiconductor superlattices with a buried porous semiconductor layers having different chemical composition than that of its monocrystalline semiconductor superlattice are discussed. Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si-Ge layers followed by patterning into mesa structures. The mesa structures are strain etched resulting in porosification of the Si-Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si-Ge layers produced in a similar manner emitted visible light at room temperature.

Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction

DOEpatents

Tauke-Pedretti, Anna; Nielson, Gregory N; Cederberg, Jeffrey G; Cruz-Campa, Jose Luis

2015-05-12

A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.

Conductive layer for biaxially oriented semiconductor film growth

DOEpatents

Findikoglu, Alp T.; Matias, Vladimir

2007-10-30

A conductive layer for biaxially oriented semiconductor film growth and a thin film semiconductor structure such as, for example, a photodetector, a photovoltaic cell, or a light emitting diode (LED) that includes a crystallographically oriented semiconducting film disposed on the conductive layer. The thin film semiconductor structure includes: a substrate; a first electrode deposited on the substrate; and a semiconducting layer epitaxially deposited on the first electrode. The first electrode includes a template layer deposited on the substrate and a buffer layer epitaxially deposited on the template layer. The template layer includes a first metal nitride that is electrically conductive and has a rock salt crystal structure, and the buffer layer includes a second metal nitride that is electrically conductive. The semiconducting layer is epitaxially deposited on the buffer layer. A method of making such a thin film semiconductor structure is also described.

Ion-implanted planar-buried-heterostructure diode laser

DOEpatents

Brennan, Thomas M.; Hammons, Burrell E.; Myers, David R.; Vawter, Gregory A.

1991-01-01

A Planar-Buried-Heterostructure, Graded-Index, Separate-Confinement-Heterostructure semiconductor diode laser 10 includes a single quantum well or multi-quantum well active stripe 12 disposed between a p-type compositionally graded Group III-V cladding layer 14 and an n-type compositionally graded Group III-V cladding layer 16. The laser 10 includes an ion implanted n-type region 28 within the p-type cladding layer 14 and further includes an ion implanted p-type region 26 within the n-type cladding layer 16. The ion implanted regions are disposed for defining a lateral extent of the active stripe.

Field-effect P-N junction

DOEpatents

Regan, William; Zettl, Alexander

2015-05-05

This disclosure provides systems, methods, and apparatus related to field-effect p-n junctions. In one aspect, a device includes an ohmic contact, a semiconductor layer disposed on the ohmic contact, at least one rectifying contact disposed on the semiconductor layer, a gate including a layer disposed on the at least one rectifying contact and the semiconductor layer and a gate contact disposed on the layer. A lateral width of the rectifying contact is less than a semiconductor depletion width of the semiconductor layer. The gate contact is electrically connected to the ohmic contact to create a self-gating feedback loop that is configured to maintain a gate electric field of the gate.

Organic photosensitive cells grown on rough electrode with nano-scale morphology control

DOEpatents

Yang, Fan [Piscataway, NJ; Forrest, Stephen R [Ann Arbor, MI

2011-06-07

An optoelectronic device and a method for fabricating the optoelectronic device includes a first electrode disposed on a substrate, an exposed surface of the first electrode having a root mean square roughness of at least 30 nm and a height variation of at least 200 nm, the first electrode being transparent. A conformal layer of a first organic semiconductor material is deposited onto the first electrode by organic vapor phase deposition, the first organic semiconductor material being a small molecule material. A layer of a second organic semiconductor material is deposited over the conformal layer. At least some of the layer of the second organic semiconductor material directly contacts the conformal layer. A second electrode is deposited over the layer of the second organic semiconductor material. The first organic semiconductor material is of a donor-type or an acceptor-type relative to the second organic semiconductor material, which is of the other material type.

Optimal doping control of magnetic semiconductors via subsurfactant epitaxy.

PubMed

Zeng, Changgan; Zhang, Zhenyu; van Benthem, Klaus; Chisholm, Matthew F; Weitering, Hanno H

2008-02-15

"Subsurfactant epitaxy" is established as a conceptually new approach for introducing manganese as a magnetic dopant into germanium. A kinetic pathway is devised in which the subsurface interstitial sites on Ge(100) are first selectively populated with Mn, while lateral diffusion and clustering on or underneath the surface are effectively suppressed. Subsequent Ge deposition as a capping layer produces a novel surfactantlike phenomenon as the interstitial Mn atoms float towards newly defined subsurface sites at the growth front. Furthermore, the Mn atoms that failed to float upwards are uniformly distributed within the Ge capping layer. The resulting doping levels of order 0.25 at. % would normally be considered too low for ferromagnetic ordering, but the Curie temperature exceeds room temperature by a comfortable margin. Subsurfactant epitaxy thus enables superior dopant control in magnetic semiconductors.

Numerical investigation of metal-semiconductor-insulator-semiconductor passivated hole contacts based on atomic layer deposited AlO x

NASA Astrophysics Data System (ADS)

Ke, Cangming; Xin, Zheng; Ling, Zhi Peng; Aberle, Armin G.; Stangl, Rolf

2017-08-01

Excellent c-Si tunnel layer surface passivation has been obtained recently in our lab, using atomic layer deposited aluminium oxide (ALD AlO x ) in the tunnel layer regime of 0.9 to 1.5 nm, investigated to be applied for contact passivation. Using the correspondingly measured interface properties, this paper compares the theoretical collection efficiency of a conventional metal-semiconductor (MS) contact on diffused p+ Si to a metal-semiconductor-insulator-semiconductor (MSIS) contact on diffused p+ Si or on undoped n-type c-Si. The influences of (1) the tunnel layer passivation quality at the tunnel oxide interface (Q f and D it), (2) the tunnel layer thickness and the electron and hole tunnelling mass, (3) the tunnel oxide material, and (4) the semiconductor capping layer material properties are investigated numerically by evaluation of solar cell efficiency, open-circuit voltage, and fill factor.

Method for removing semiconductor layers from salt substrates

DOEpatents

Shuskus, Alexander J.; Cowher, Melvyn E.

1985-08-27

A method is described for removing a CVD semiconductor layer from an alkali halide salt substrate following the deposition of the semiconductor layer. The semiconductor-substrate combination is supported on a material such as tungsten which is readily wet by the molten alkali halide. The temperature of the semiconductor-substrate combination is raised to a temperature greater than the melting temperature of the substrate but less than the temperature of the semiconductor and the substrate is melted and removed from the semiconductor by capillary action of the wettable support.

Alpha voltaic batteries and methods thereof

NASA Technical Reports Server (NTRS)

Jenkins, Phillip (Inventor); Scheiman, David (Inventor); Castro, Stephanie (Inventor); Raffaelle, Ryne P. (Inventor); Wilt, David (Inventor); Chubb, Donald (Inventor)

2011-01-01

An alpha voltaic battery includes at least one layer of a semiconductor material comprising at least one p/n junction, at least one absorption and conversion layer on the at least one layer of semiconductor layer, and at least one alpha particle emitter. The absorption and conversion layer prevents at least a portion of alpha particles from the alpha particle emitter from damaging the p/n junction in the layer of semiconductor material. The absorption and conversion layer also converts at least a portion of energy from the alpha particles into electron-hole pairs for collection by the one p/n junction in the layer of semiconductor material.

Controlled growth of larger heterojunction interface area for organic photosensitive devices

DOEpatents

Yang, Fan [Somerset, NJ; Forrest, Stephen R [Ann Arbor, MI

2009-12-29

An optoelectronic device and a method of fabricating a photosensitive optoelectronic device includes depositing a first organic semiconductor material on a first electrode to form a continuous first layer having protrusions, a side of the first layer opposite the first electrode having a surface area at least three times greater than an underlying lateral cross-sectional area; depositing a second organic semiconductor material directly on the first layer to form a discontinuous second layer, portions of the first layer remaining exposed; depositing a third organic semiconductor material directly on the second layer to form a discontinuous third layer, portions of at least the second layer remaining exposed; depositing a fourth organic semiconductor material on the third layer to form a continuous fourth layer, filling any exposed gaps and recesses in the first, second, and third layers; and depositing a second electrode on the fourth layer, wherein at least one of the first electrode and the second electrode is transparent, and the first and third organic semiconductor materials are both of a donor-type or an acceptor-type relative to second and fourth organic semiconductor materials, which are of the other material type.

High efficiency, low cost, thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

2001-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

1999-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

Semiconductor films on flexible iridium substrates

DOEpatents

Goyal, Amit

2005-03-29

A laminate semiconductor article includes a flexible substrate, an optional biaxially textured oxide buffer system on the flexible substrate, a biaxially textured Ir-based buffer layer on the substrate or the buffer system, and an epitaxial layer of a semiconductor. Ir can serve as a substrate with an epitaxial layer of a semiconductor thereon.

Light emitting diode with porous SiC substrate and method for fabricating

DOEpatents

Li, Ting; Ibbetson, James; Keller, Bernd

2005-12-06

A method and apparatus for forming a porous layer on the surface of a semiconductor material wherein an electrolyte is provided and is placed in contact with one or more surfaces of a layer of semiconductor material. The electrolyte is heated and a bias is introduced across said electrolyte and the semiconductor material causing a current to flow between the electrolyte and the semiconductor material. The current forms a porous layer on the one or more surfaces of the semiconductor material in contact with the electrolyte. The semiconductor material with its porous layer can serve as a substrate for a light emitter. A semiconductor emission region can be formed on the substrate. The emission region is capable of emitting light omnidirectionally in response to a bias, with the porous layer enhancing extraction of the emitting region light passing through the substrate.

Photovoltaic healing of non-uniformities in semiconductor devices

DOEpatents

Karpov, Victor G.; Roussillon, Yann; Shvydka, Diana; Compaan, Alvin D.; Giolando, Dean M.

2006-08-29

A method of making a photovoltaic device using light energy and a solution to normalize electric potential variations in the device. A semiconductor layer having nonuniformities comprising areas of aberrant electric potential deviating from the electric potential of the top surface of the semiconductor is deposited onto a substrate layer. A solution containing an electrolyte, at least one bonding material, and positive and negative ions is applied over the top surface of the semiconductor. Light energy is applied to generate photovoltage in the semiconductor, causing a redistribution of the ions and the bonding material to the areas of aberrant electric potential. The bonding material selectively bonds to the nonuniformities in a manner such that the electric potential of the nonuniformities is normalized relative to the electric potential of the top surface of the semiconductor layer. A conductive electrode layer is then deposited over the top surface of the semiconductor layer.

Overview of atomic layer etching in the semiconductor industry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanarik, Keren J., E-mail: keren.kanarik@lamresearch.com; Lill, Thorsten; Hudson, Eric A.

2015-03-15

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article providesmore » defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices.« less

Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates

DOEpatents

Norman, Andrew G; Ptak, Aaron J

2013-08-13

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

Method of fabricating germanium and gallium arsenide devices

NASA Technical Reports Server (NTRS)

Jhabvala, Murzban (Inventor)

1990-01-01

A method of semiconductor diode fabrication is disclosed which relies on the epitaxial growth of a precisely doped thickness layer of gallium arsenide or germanium on a semi-insulating or intrinsic substrate, respectively, of gallium arsenide or germanium by either molecular beam epitaxy (MBE) or by metal-organic chemical vapor deposition (MOCVD). The method involves: depositing a layer of doped or undoped silicon dioxide on a germanium or gallium arsenide wafer or substrate, selectively removing the silicon dioxide layer to define one or more surface regions for a device to be fabricated thereon, growing a matched epitaxial layer of doped germanium or gallium arsenide of an appropriate thickness using MBE or MOCVD techniques on both the silicon dioxide layer and the defined one or more regions; and etching the silicon dioxide and the epitaxial material on top of the silicon dioxide to leave a matched epitaxial layer of germanium or gallium arsenide on the germanium or gallium arsenide substrate, respectively, and upon which a field effect device can thereafter be formed.

Intermediate-band photosensitive device with quantum dots embedded in energy fence barrier

DOEpatents

Forrest, Stephen R.; Wei, Guodan

2010-07-06

A plurality of layers of a first semiconductor material and a plurality of dots-in-a-fence barriers disposed in a stack between a first electrode and a second electrode. Each dots-in-a-fence barrier consists essentially of a plurality of quantum dots of a second semiconductor material embedded between and in direct contact with two layers of a third semiconductor material. Wave functions of the quantum dots overlap as at least one intermediate band. The layers of the third semiconductor material are arranged as tunneling barriers to require a first electron and/or a first hole in a layer of the first material to perform quantum mechanical tunneling to reach the second material within a respective quantum dot, and to require a second electron and/or a second hole in a layer of the first semiconductor material to perform quantum mechanical tunneling to reach another layer of the first semiconductor material.

Energy resolution in semiconductor gamma radiation detectors using heterojunctions and methods of use and preparation thereof

DOEpatents

Nikolic, Rebecca J.; Conway, Adam M.; Nelson, Art J.; Payne, Stephen A.

2012-09-04

In one embodiment, a system comprises a semiconductor gamma detector material and a hole blocking layer adjacent the gamma detector material, the hole blocking layer resisting passage of holes therethrough. In another embodiment, a system comprises a semiconductor gamma detector material, and an electron blocking layer adjacent the gamma detector material, the electron blocking layer resisting passage of electrons therethrough, wherein the electron blocking layer comprises undoped HgCdTe. In another embodiment, a method comprises forming a hole blocking layer adjacent a semiconductor gamma detector material, the hole blocking layer resisting passage of holes therethrough. Additional systems and methods are also presented.

Monolithic in-based III-V compound semiconductor focal plane array cell with single stage CCD output

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Cunningham, Thomas J. (Inventor); Krabach, Timothy N. (Inventor); Staller, Craig O. (Inventor)

1994-01-01

A monolithic semiconductor imager includes an indium-based III-V compound semiconductor monolithic active layer of a first conductivity type, an array of plural focal plane cells on the active layer, each of the focal plane cells including a photogate over a top surface of the active layer, a readout circuit dedicated to the focal plane cell including plural transistors formed monolithically with the monolithic active layer and a single-stage charge coupled device formed monolithically with the active layer between the photogate and the readout circuit for transferring photo-generated charge accumulated beneath the photogate during an integration period to the readout circuit. The photogate includes thin epitaxial semiconductor layer of a second conductivity type overlying the active layer and an aperture electrode overlying a peripheral portion of the thin epitaxial semiconductor layer, the aperture electrode being connectable to a photogate bias voltage.

Transversal Kerr effect of In1- x Mn x As layers prepared by ion implantation followed by pulsed laser annealing

NASA Astrophysics Data System (ADS)

Gan'shina, Elena; Golik, Leonard; Kun'kova, Zoya; Bykov, Igor; Novikov, Andrey; Rukovishnikov, Alexander; Yuan, Ye; Zykov, Georgy; Böttger, Roman; Zhou, Shengqiang

2016-07-01

In1- x Mn x As (x = 6.9%) layers prepared by ion implantation and subsequent pulsed laser annealing have been studied using the magnetooptical transversal Kerr effect (TKE) and spectral ellipsometry. Ellipsometry data reveal the good crystal quality of the layers. The samples show ferromagnetic behaviour below 77 K. Near the absorption edge of the parent InAs semiconductor, large TKE values are observed. In the energy regions of the transitions in the Γ and L critical points of the InAs Brillouin zone, there are several clearly defined structures in the low-temperature TKE spectra. We have calculated the spectral dependences of the diagonal and nondiagonal components of the permittivity tensor (PT), as well as the spectrum of magnetic circular dichroism (MCD) for our samples. A number of extrema in the obtained MCD and PT spectra are close to the energies of transitions in the critical points of the parent semiconductor band structure, which confirms the intrinsic ferromagnetism of the Mn-doped InAs layers.

Lattice matched semiconductor growth on crystalline metallic substrates

DOEpatents

Norman, Andrew G; Ptak, Aaron J; McMahon, William E

2013-11-05

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.

Micrometer-scale fabrication of complex three dimensional lattice + basis structures in silicon

DOE PAGES

Burckel, D. Bruce; Resnick, Paul J.; Finnegan, Patrick S.; ...

2015-01-01

A complementary metal oxide semiconductor (CMOS) compatible version of membrane projection lithography (MPL) for fabrication of micrometer-scale three-dimensional structures is presented. The approach uses all inorganic materials and standard CMOS processing equipment. In a single layer, MPL is capable of creating all 5 2D-Bravais lattices. Furthermore, standard semiconductor processing steps can be used in a layer-by-layer approach to create fully three dimensional structures with any of the 14 3D-Bravais lattices. The unit cell basis is determined by the projection of the membrane pattern, with many degrees of freedom for defining functional inclusions. Here we demonstrate several unique structural motifs, andmore » characterize 2D arrays of unit cells with split ring resonators in a silicon matrix. The structures exhibit strong polarization dependent resonances and, for properly oriented split ring resonators (SRRs), coupling to the magnetic field of a normally incident transverse electromagnetic wave, a response unique to 3D inclusions.« less

Measuring the complete cross-cell carrier mobility distributions in bulk heterojunction solar cells

NASA Astrophysics Data System (ADS)

Seifter, Jason; Sun, Yanming; Choi, Hyosung; Lee, Byoung Hoon; Heeger, Alan

2015-03-01

Carbon nanotube-enabled, vertical, organic field effect transistors (CN-VFETs) based on the small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) have demonstrated high current, low-power operation suitable for driving active matix organic light emitting diode (AMOLED) displays. This performance is achieved without the need for costly high-resolution patterning, despite the low mobility of the organic semiconductor, by employing sub-micron channel widths, defined in the vertical devices by the thickness of the semiconducting layer. Replacing the thermally evaporated small molecule semiconductor with a solution-processed polymer would possibly further simplify the fabrication process and reduce manufacturing cost. Here we investigate several polymer systems as wide bandgap semiconducting channel layers for potentially air stable and transparent CN-VFETs. The field effect mobility and optical transparency of the polymer layers are determined, and the performance and air stability of CN-VFET devices are measured. A. S. gratefully acknowledges support from the National Science Foundation under DMR-1156737.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, B.L.

1999-04-27

A semiconductor device is described having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer. 9 figs.

Artifacts for Calibration of Submicron Width Measurements

NASA Technical Reports Server (NTRS)

Grunthaner, Frank; Grunthaner, Paula; Bryson, Charles, III

2003-01-01

Artifacts that are fabricated with the help of molecular-beam epitaxy (MBE) are undergoing development for use as dimensional calibration standards with submicron widths. Such standards are needed for calibrating instruments (principally, scanning electron microscopes and scanning probe microscopes) for measuring the widths of features in advanced integrated circuits. Dimensional calibration standards fabricated by an older process that involves lithography and etching of trenches in (110) surfaces of single-crystal silicon are generally reproducible to within dimensional tolerances of about 15 nm. It is anticipated that when the artifacts of the present type are fully developed, their critical dimensions will be reproducible to within 1 nm. These artifacts are expected to find increasing use in the semiconductor-device and integrated- circuit industries as the width tolerances on semiconductor devices shrink to a few nanometers during the next few years. Unlike in the older process, one does not rely on lithography and etching to define the critical dimensions. Instead, one relies on the inherent smoothness and flatness of MBE layers deposited under controlled conditions and defines the critical dimensions as the thicknesses of such layers. An artifact of the present type is fabricated in two stages (see figure): In the first stage, a multilayer epitaxial wafer is grown on a very flat substrate. In the second stage, the wafer is cleaved to expose the layers, then the exposed layers are differentially etched (taking advantage of large differences between the etch rates of the different epitaxial layer materials). The resulting structure includes narrow and well-defined trenches and a shelf with thicknesses determined by the thicknesses of the epitaxial layers from which they were etched. Eventually, it should be possible to add a third fabrication stage in which durable, electronically inert artifacts could be replicated in diamondlike carbon from a master made by MBE and etching as described above.

Thin film photovoltaic device with multilayer substrate

DOEpatents

Catalano, Anthony W.; Bhushan, Manjul

1984-01-01

A thin film photovoltaic device which utilizes at least one compound semiconductor layer chosen from Groups IIB and VA of the Periodic Table is formed on a multilayer substrate The substrate includes a lowermost support layer on which all of the other layers of the device are formed. Additionally, an uppermost carbide or silicon layer is adjacent to the semiconductor layer. Below the carbide or silicon layer is a metal layer of high conductivity and expansion coefficient equal to or slightly greater than that of the semiconductor layer.

Electroluminescent devices formed using semiconductor nanocrystals as an electron transport media and method of making such electroluminescent devices

DOEpatents

Alivisatos, A. Paul; Colvin, Vickie

1996-01-01

An electroluminescent device is described, as well as a method of making same, wherein the device is characterized by a semiconductor nanocrystal electron transport layer capable of emitting visible light in response to a voltage applied to the device. The wavelength of the light emitted by the device may be changed by changing either the size or the type of semiconductor nanocrystals used in forming the electron transport layer. In a preferred embodiment the device is further characterized by the capability of emitting visible light of varying wavelengths in response to changes in the voltage applied to the device. The device comprises a hole processing structure capable of injecting and transporting holes, and usually comprising a hole injecting layer and a hole transporting layer; an electron transport layer in contact with the hole processing structure and comprising one or more layers of semiconductor nanocrystals; and an electron injecting layer in contact with the electron transport layer for injecting electrons into the electron transport layer. The capability of emitting visible light of various wavelengths is principally based on the variations in voltage applied thereto, but the type of semiconductor nanocrystals used and the size of the semiconductor nanocrystals in the layers of semiconductor nanometer crystals may also play a role in color change, in combination with the change in voltage.

Tunnel barrier schottky

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chu, Rongming; Cao, Yu; Li, Zijian

2018-02-20

A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.

Method of making an ion-implanted planar-buried-heterostructure diode laser

DOEpatents

Brennan, Thomas M.; Hammons, Burrell E.; Myers, David R.; Vawter, Gregory A.

1992-01-01

Planar-buried-heterostructure, graded-index, separate-confinement-heterostructure semiconductor diode laser 10 includes a single quantum well or multi-quantum well active stripe 12 disposed between a p-type compositionally graded Group III-V cladding lever 14 and an n-type compositionally graded Group III-V cladding layer 16. The laser 10 includes an iion implanted n-type region 28 within the p-type cladding layer 14 and further includes an ion implanted p-type region 26 within the n-type cladding layer 16. The ion implanted regions are disposed for defining a lateral extent of the active stripe.

Voltage-matched, monolithic, multi-band-gap devices

DOEpatents

Wanlass, Mark W.; Mascarenhas, Angelo

2006-08-22

Monolithic, tandem, photonic cells include at least a first semiconductor layer and a second semiconductor layer, wherein each semiconductor layer includes an n-type region, a p-type region, and a given band-gap energy. Formed within each semiconductor layer is a sting of electrically connected photonic sub-cells. By carefully selecting the numbers of photonic sub-cells in the first and second layer photonic sub-cell string(s), and by carefully selecting the manner in which the sub-cells in a first and second layer photonic sub-cell string(s) are electrically connected, each of the first and second layer sub-cell strings may be made to achieve one or more substantially identical electrical characteristics.

Voltage-Matched, Monolithic, Multi-Band-Gap Devices

DOEpatents

Wanlass, M. W.; Mascarenhas, A.

2006-08-22

Monolithic, tandem, photonic cells include at least a first semiconductor layer and a second semiconductor layer, wherein each semiconductor layer includes an n-type region, a p-type region, and a given band-gap energy. Formed within each semiconductor layer is a string of electrically connected photonic sub-cells. By carefully selecting the numbers of photonic sub-cells in the first and second layer photonic sub-cell string(s), and by carefully selecting the manner in which the sub-cells in a first and second layer photonic sub-cell string(s) are electrically connected, each of the first and second layer sub-cell strings may be made to achieve one or more substantially identical electrical characteristics.

Photovoltaic devices comprising zinc stannate buffer layer and method for making

DOEpatents

Wu, Xuanzhi; Sheldon, Peter; Coutts, Timothy J.

2001-01-01

A photovoltaic device has a buffer layer zinc stannate Zn.sub.2 SnO.sub.4 disposed between the semiconductor junction structure and the transparent conducting oxide (TCO) layer to prevent formation of localized junctions with the TCO through a thin window semiconductor layer, to prevent shunting through etched grain boundaries of semiconductors, and to relieve stresses and improve adhesion between these layers.

Large-area, laterally-grown epitaxial semiconductor layers

DOEpatents

Han, Jung; Song, Jie; Chen, Danti

2017-07-18

Structures and methods for confined lateral-guided growth of a large-area semiconductor layer on an insulating layer are described. The semiconductor layer may be formed by heteroepitaxial growth from a selective growth area in a vertically-confined, lateral-growth guiding structure. Lateral-growth guiding structures may be formed in arrays over a region of a substrate, so as to cover a majority of the substrate region with laterally-grown epitaxial semiconductor tiles. Quality regions of low-defect, stress-free GaN may be grown on silicon.

Photovoltaic Device Including A Boron Doping Profile In An I-Type Layer

DOEpatents

Yang, Liyou

1993-10-26

A photovoltaic cell for use in a single junction or multijunction photovoltaic device, which includes a p-type layer of a semiconductor compound including silicon, an i-type layer of an amorphous semiconductor compound including silicon, and an n-type layer of a semiconductor compound including silicon formed on the i-type layer. The i-type layer including an undoped first sublayer formed on the p-type layer, and a boron-doped second sublayer formed on the first sublayer.

Back contact buffer layer for thin-film solar cells

DOEpatents

Compaan, Alvin D.; Plotnikov, Victor V.

2014-09-09

A photovoltaic cell structure is disclosed that includes a buffer/passivation layer at a CdTe/Back contact interface. The buffer/passivation layer is formed from the same material that forms the n-type semiconductor active layer. In one embodiment, the buffer layer and the n-type semiconductor active layer are formed from cadmium sulfide (CdS). A method of forming a photovoltaic cell includes the step of forming the semiconductor active layers and the buffer/passivation layer within the same deposition chamber and using the same material source.

Methods of producing free-standing semiconductors using sacrificial buffer layers and recyclable substrates

DOEpatents

Ptak, Aaron Joseph; Lin, Yong; Norman, Andrew; Alberi, Kirstin

2015-05-26

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices. The low-defect density semiconductor materials produced using this method result in the enhanced performance of the semiconductor devices that incorporate the semiconductor materials.

Use of layer strains in strained-layer superlattices to make devices for operation in new wavelength ranges, E. G. , InAsSb at 8 to 12. mu. m. [InAs/sub 1-x/Sb/sub x/

DOEpatents

Osbourn, G.C.

1983-10-06

An intrinsic semiconductor electro-optical device comprises a p-n junction intrinsically responsive, when cooled, to electromagnetic radiation in the wavelength range of 8 to 12 ..mu..m. This radiation responsive p-n junction comprises a strained-layer superlattice (SLS) of alternating layers of two different III-V semiconductors. The lattice constants of the two semiconductors are mismatched, whereby a total strain is imposed on each pair of alternating semiconductor layers in the SLS structure, the proportion of the total strain which acts on each layer of the pair being proportional to the ratio of the layer thicknesses of each layer in the pair.

Plasmon absorption modulator systems and methods

DOEpatents

Kekatpure, Rohan Deodatta; Davids, Paul

2014-07-15

Plasmon absorption modulator systems and methods are disclosed. A plasmon absorption modulator system includes a semiconductor substrate, a plurality of quantum well layers stacked on a top surface of the semiconductor substrate, and a metal layer formed on a top surface of the stack of quantum well layers. A method for modulating plasmonic current includes enabling propagation of the plasmonic current along a metal layer, and applying a voltage across the stack of quantum well layers to cause absorption of a portion of energy of the plasmonic current by the stack of quantum well layers. A metamaterial switching system includes a semiconductor substrate, a plurality of quantum well layers stacked on a top surface of the semiconductor substrate, and at least one metamaterial structure formed on a top surface of the stack of quantum well layers.

Surface preparation of substances for continuous convective assembly of fine particles

DOEpatents

Rossi, Robert

2003-01-01

A method for producing periodic nanometer-scale arrays of metal or semiconductor junctions on a clean semiconductor substrate surface is provided comprising the steps of: etching the substrate surface to make it hydrophilic, forming, under an inert atmosphere, a crystalline colloid layer on the substrate surface, depositing a metal or semiconductor material through the colloid layer onto the surface of the substrate, and removing the colloid from the substrate surface. The colloid layer is grown on the clean semiconductor surface by withdrawing the semiconductor substrate from a sol of colloid particles.

Thin-film solar cell fabricated on a flexible metallic substrate

DOEpatents

Tuttle, John R.; Noufi, Rommel; Hasoon, Falah S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

Thin-Film Solar Cell Fabricated on a Flexible Metallic Substrate

DOEpatents

Tuttle, J. R.; Noufi, R.; Hasoon, F. S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

Interconnected semiconductor devices

DOEpatents

Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

1990-10-23

Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

Thermally robust semiconductor optical amplifiers and laser diodes

DOEpatents

Dijaili, Sol P.; Patterson, Frank G.; Walker, Jeffrey D.; Deri, Robert J.; Petersen, Holly; Goward, William

2002-01-01

A highly heat conductive layer is combined with or placed in the vicinity of the optical waveguide region of active semiconductor components. The thermally conductive layer enhances the conduction of heat away from the active region, which is where the heat is generated in active semiconductor components. This layer is placed so close to the optical region that it must also function as a waveguide and causes the active region to be nearly the same temperature as the ambient or heat sink. However, the semiconductor material itself should be as temperature insensitive as possible and therefore the invention combines a highly thermally conductive dielectric layer with improved semiconductor materials to achieve an overall package that offers improved thermal performance. The highly thermally conductive layer serves two basic functions. First, it provides a lower index material than the semiconductor device so that certain kinds of optical waveguides may be formed, e.g., a ridge waveguide. The second and most important function, as it relates to this invention, is that it provides a significantly higher thermal conductivity than the semiconductor material, which is the principal material in the fabrication of various optoelectronic devices.

Unitary lens semiconductor device

DOEpatents

Lear, Kevin L.

1997-01-01

A unitary lens semiconductor device and method. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors.

Method for depositing high-quality microcrystalline semiconductor materials

DOEpatents

Guha, Subhendu [Bloomfield Hills, MI; Yang, Chi C [Troy, MI; Yan, Baojie [Rochester Hills, MI

2011-03-08

A process for the plasma deposition of a layer of a microcrystalline semiconductor material is carried out by energizing a process gas which includes a precursor of the semiconductor material and a diluent with electromagnetic energy so as to create a plasma therefrom. The plasma deposits a layer of the microcrystalline semiconductor material onto the substrate. The concentration of the diluent in the process gas is varied as a function of the thickness of the layer of microcrystalline semiconductor material which has been deposited. Also disclosed is the use of the process for the preparation of an N-I-P type photovoltaic device.

Unitary lens semiconductor device

DOEpatents

Lear, K.L.

1997-05-27

A unitary lens semiconductor device and method are disclosed. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors. 9 figs.

Low temperature production of large-grain polycrystalline semiconductors

DOEpatents

Naseem, Hameed A [Fayetteville, AR; Albarghouti, Marwan [Loudonville, NY

2007-04-10

An oxide or nitride layer is provided on an amorphous semiconductor layer prior to performing metal-induced crystallization of the semiconductor layer. The oxide or nitride layer facilitates conversion of the amorphous material into large grain polycrystalline material. Hence, a native silicon dioxide layer provided on hydrogenated amorphous silicon (a-Si:H), followed by deposited Al permits induced crystallization at temperatures far below the solid phase crystallization temperature of a-Si. Solar cells and thin film transistors can be prepared using this method.

Method for growing low defect, high purity crystalline layers utilizing lateral overgrowth of a patterned mask

NASA Technical Reports Server (NTRS)

Morrison, Andrew D. (Inventor); Daud, Taher (Inventor)

1986-01-01

A method for growing a high purity, low defect layer of semiconductor is described. This method involves depositing a patterned mask of a material impervious to impurities of the semiconductor on a surface of a blank. When a layer of semiconductor is grown on the mask, the semiconductor will first grow from the surface portions exposed by the openings in the mask and will bridge the connecting portions of the mask to form a continuous layer having improved purity, since only the portions overlying the openings are exposed to defects and impurities. The process can be iterated and the mask translated to further improve the quality of grown layers.

Laser pumping of thyristors for fast high current rise-times

DOEpatents

Glidden, Steven C.; Sanders, Howard D.

2013-06-11

An optically triggered semiconductor switch includes an anode metallization layer; a cathode metallization layer; a semiconductor between the anode metallization layer and the cathode metallization layer and a photon source. The semiconductor includes at least four layers of alternating doping in the form P-N-P-N, in which an outer layer adjacent to the anode metallization layer forms an anode and an outer layer adjacent the cathode metallization layer forms a cathode and in which the anode metallization layer has a window pattern of optically transparent material exposing the anode layer to light. The photon source emits light having a wavelength, with the light from the photon source being configured to match the window pattern of the anode metallization layer.

Optical devices featuring textured semiconductor layers

DOEpatents

Moustakas, Theodore D [Dover, MA; Cabalu, Jasper S [Cary, NC

2011-10-11

A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor.

Optical devices featuring textured semiconductor layers

DOEpatents

Moustakas, Theodore D [Dover, MA; Cabalu, Jasper S [Cary, NC

2012-08-07

A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor.

Sintered silver joints via controlled topography of electronic packaging subcomponents

DOEpatents

Wereszczak, Andrew A.

2014-09-02

Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.

Method for fabricating an interconnected array of semiconductor devices

DOEpatents

Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

1989-10-10

Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

High-resolution parallel-detection sensor array using piezo-phototronics effect

DOEpatents

Wang, Zhong L.; Pan, Caofeng

2015-07-28

A pressure sensor element includes a substrate, a first type of semiconductor material layer and an array of elongated light-emitting piezoelectric nanostructures extending upwardly from the first type of semiconductor material layer. A p-n junction is formed between each nanostructure and the first type semiconductor layer. An insulative resilient medium layer is infused around each of the elongated light-emitting piezoelectric nanostructures. A transparent planar electrode, disposed on the resilient medium layer, is electrically coupled to the top of each nanostructure. A voltage source is coupled to the first type of semiconductor material layer and the transparent planar electrode and applies a biasing voltage across each of the nanostructures. Each nanostructure emits light in an intensity that is proportional to an amount of compressive strain applied thereto.

Solid state radiative heat pump

DOEpatents

Berdahl, P.H.

1984-09-28

A solid state radiative heat pump operable at room temperature (300 K) utilizes a semiconductor having a gap energy in the range of 0.03-0.25 eV and operated reversibly to produce an excess or deficit of change carriers as compared equilibrium. In one form of the invention an infrared semiconductor photodiode is used, with forward or reverse bias, to emit an excess or deficit of infrared radiation. In another form of the invention, a homogenous semiconductor is subjected to orthogonal magnetic and electric fields to emit an excess or deficit of infrared radiation. Three methods of enhancing transmission of radiation the active surface of the semiconductor are disclosed. In one method, an anti-refection layer is coated into the active surface of the semiconductor, the anti-reflection layer having an index of refraction equal to the square root of that of the semiconductor. In the second method, a passive layer is speaced trom the active surface of the semiconductor by a submicron vacuum gap, the passive layer having an index of refractive equal to that of the semiconductor. In the third method, a coupler with a paraboloid reflecting surface surface is in contact with the active surface of the semiconductor, the coupler having an index of refraction about the same as that of the semiconductor.

Monocrystalline test structures, and use for calibrating instruments

DOEpatents

Cresswell, Michael W.; Ghoshtagore, R. N.; Linholm, Loren W.; Allen, Richard A.; Sniegowski, Jeffry J.

1997-01-01

An improved test structure for measurement of width of conductive lines formed on substrates as performed in semiconductor fabrication, and for calibrating instruments for such measurements, is formed from a monocrystalline starting material, having an insulative layer formed beneath its surface by ion implantation or the equivalent, leaving a monocrystalline layer on the surface. The monocrystalline surface layer is then processed by preferential etching to accurately define components of the test structure. The substrate can be removed from the rear side of the insulative layer to form a transparent window, such that the test structure can be inspected by transmissive-optical techniques. Measurements made using electrical and optical techniques can be correlated with other measurements, including measurements made using scanning probe microscopy.

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

1984-04-19

In a field-effect transistor comprising a semiconductor having therein a source, a drain, a channel and a gate in operational relationship, there is provided an improvement wherein said semiconductor is a superlattice comprising alternating quantum well and barrier layers, the quantum well layers comprising a first direct gap semiconductor material which in bulk form has a certain bandgap and a curve of electron velocity versus applied electric field which has a maximum electron velocity at a certain electric field, the barrier layers comprising a second semiconductor material having a bandgap wider than that of said first semiconductor material, wherein the layer thicknesses of said quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice having a curve of electron velocity versus applied electric field which has a maximum electron velocity at a certain electric field, and wherein the thicknesses of said quantum well layers are selected to provide a superlattice curve of electron velocity versus applied electric field whereby, at applied electric fields higher than that at which the maximum electron velocity occurs in said first material when in bulk form, the electron velocities are higher in said superlattice than they are in said first semiconductor material in bulk form.

Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

DOEpatents

Wu, Xuanzhi; Coutts, Timothy J.; Sheldon, Peter; Rose, Douglas H.

1999-01-01

A photovoltaic device having a substrate, a layer of Cd.sub.2 SnO.sub.4 disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd.sub.2 SnO.sub.4, and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd.sub.2 SnO.sub.4 layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd.sub.2 SnO.sub.4, and depositing an electrically conductive film onto the thin film of semiconductor materials.

Porous silicon carbide (SiC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

DOEpatents

Wu, X.; Coutts, T.J.; Sheldon, P.; Rose, D.H.

1999-07-13

A photovoltaic device is disclosed having a substrate, a layer of Cd[sub 2]SnO[sub 4] disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd[sub 2]SnO[sub 4], and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd[sub 2]SnO[sub 4] layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd[sub 2]SnO[sub 4], and depositing an electrically conductive film onto the thin film of semiconductor materials. 10 figs.

Dry texturing of solar cells

DOEpatents

Sopori, B.L.

1994-10-25

A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer. The result is a textured backside on an optically reflective, low resistivity alloy interface between the semiconductor substrate and the metal electrical contact layer. 9 figs.

Dry texturing of solar cells

DOEpatents

Sopori, Bhushan L.

1994-01-01

A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer. The result is a textured backside an optically reflective, low resistivity alloy interface between the semiconductor substrate and the metal electrical contact layer.

Nanomembrane structures having mixed crystalline orientations and compositions

DOEpatents

Lagally, Max G.; Scott, Shelley A.; Savage, Donald E.

2014-08-12

The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but which differs from the nanomembrane semiconductor materials in composition, crystal orientation, or both.

Die singulation method

DOEpatents

Swiler, Thomas P.; Garcia, Ernest J.; Francis, Kathryn M.

2013-06-11

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Die singulation method

DOEpatents

Swiler, Thomas P [Albuquerque, NM; Garcia, Ernest J [Albuquerque, NM; Francis, Kathryn M [Rio Rancho, NM

2014-01-07

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with a HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Method for depositing layers of high quality semiconductor material

DOEpatents

Guha, Subhendu; Yang, Chi C.

2001-08-14

Plasma deposition of substantially amorphous semiconductor materials is carried out under a set of deposition parameters which are selected so that the process operates near the amorphous/microcrystalline threshold. This threshold varies as a function of the thickness of the depositing semiconductor layer; and, deposition parameters, such as diluent gas concentrations, must be adjusted as a function of layer thickness. Also, this threshold varies as a function of the composition of the depositing layer, and in those instances where the layer composition is profiled throughout its thickness, deposition parameters must be adjusted accordingly so as to maintain the amorphous/microcrystalline threshold.

Lattice-mismatched GaInP LED devices and methods of fabricating same

DOEpatents

Mascarenhas, Angelo; Steiner, Myles A; Bhusal, Lekhnath; Zhang, Yong

2014-10-21

A method (100) of fabricating an LED or the active regions of an LED and an LED (200). The method includes growing, depositing or otherwise providing a bottom cladding layer (208) of a selected semiconductor alloy with an adjusted bandgap provided by intentionally disordering the structure of the cladding layer (208). A first active layer (202) may be grown above the bottom cladding layer (208) wherein the first active layer (202) is fabricated of the same semiconductor alloy, with however, a partially ordered structure. The first active layer (202) will also be fabricated to include a selected n or p type doping. The method further includes growing a second active layer (204) above the first active layer (202) where the second active layer (204) Is fabricated from the same semiconductor alloy.

Amorphous semiconductor solar cell

DOEpatents

Dalal, Vikram L.

1981-01-01

A solar cell comprising a back electrical contact, amorphous silicon semiconductor base and junction layers and a top electrical contact includes in its manufacture the step of heat treating the physical junction between the base layer and junction layer to diffuse the dopant species at the physical junction into the base layer.

Monolayer-Mediated Growth of Organic Semiconductor Films with Improved Device Performance.

PubMed

Huang, Lizhen; Hu, Xiaorong; Chi, Lifeng

2015-09-15

Increased interest in wearable and smart electronics is driving numerous research works on organic electronics. The control of film growth and patterning is of great importance when targeting high-performance organic semiconductor devices. In this Feature Article, we summarize our recent work focusing on the growth, crystallization, and device operation of organic semiconductors intermediated by ultrathin organic films (in most cases, only a monolayer). The site-selective growth, modified crystallization and morphology, and improved device performance of organic semiconductor films are demonstrated with the help of the inducing layers, including patterned and uniform Langmuir-Blodgett monolayers, crystalline ultrathin organic films, and self-assembled polymer brush films. The introduction of the inducing layers could dramatically change the diffusion of the organic semiconductors on the surface and the interactions between the active layer with the inducing layer, leading to improved aggregation/crystallization behavior and device performance.

Nanocrystal structures

DOEpatents

Eisler, Hans J [Stoneham, MA; Sundar, Vikram C [Stoneham, MA; Walsh, Michael E [Everett, MA; Klimov, Victor I [Los Alamos, NM; Bawendi, Moungi G [Cambridge, MA; Smith, Henry I [Sudbury, MA

2008-12-30

A structure including a grating and a semiconductor nanocrystal layer on the grating, can be a laser. The semiconductor nanocrystal layer can include a plurality of semiconductor nanocrystals including a Group II-VI compound, the nanocrystals being distributed in a metal oxide matrix. The grating can have a periodicity from 200 nm to 500 nm.

Nanocrystal structures

DOEpatents

Eisler, Hans J.; Sundar, Vikram C.; Walsh, Michael E.; Klimov, Victor I.; Bawendi, Moungi G.; Smith, Henry I.

2006-12-19

A structure including a grating and a semiconductor nanocrystal layer on the grating, can be a laser. The semiconductor nanocrystal layer can include a plurality of semiconductor nanocrystals including a Group II–VI compound, the nanocrystals being distributed in a metal oxide matrix. The grating can have a periodicity from 200 nm to 500 nm.

Solid state radiative heat pump

DOEpatents

Berdahl, Paul H.

1986-01-01

A solid state radiative heat pump (10, 50, 70) operable at room temperature (300.degree. K.) utilizes a semiconductor having a gap energy in the range of 0.03-0.25 eV and operated reversibly to produce an excess or deficit of charge carriers as compared to thermal equilibrium. In one form of the invention (10, 70) an infrared semiconductor photodiode (21, 71) is used, with forward or reverse bias, to emit an excess or deficit of infrared radiation. In another form of the invention (50), a homogeneous semiconductor (51) is subjected to orthogonal magnetic and electric fields to emit an excess or deficit of infrared radiation. Three methods of enhancing transmission of radiation through the active surface of the semiconductor are disclosed. In one method, an anti-reflection layer (19) is coated into the active surface (13) of the semiconductor (11), the anti-reflection layer (19) having an index of refraction equal to the square root of that of the semiconductor (11). In the second method, a passive layer (75) is spaced from the active surface (73) of the semiconductor (71) by a submicron vacuum gap, the passive layer having an index of refractive equal to that of the semiconductor. In the third method, a coupler (91) with a paraboloid reflecting surface (92) is in contact with the active surface (13, 53) of the semiconductor (11, 51), the coupler having an index of refraction about the same as that of the semiconductor.

Optical devices featuring nonpolar textured semiconductor layers

DOEpatents

Moustakas, Theodore D; Moldawer, Adam; Bhattacharyya, Anirban; Abell, Joshua

2013-11-26

A semiconductor emitter, or precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of nonpolar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the invention can be 70-80% or higher. The invention provides highly efficient light emitting diodes suitable for solid state lighting.

SCB initiator

DOEpatents

Bickes Jr., Robert W.; Renlund, Anita M.; Stanton, Philip L.

1994-11-01

A detonator for high explosives initiated by mechanical impact includes a cylindrical barrel, a layer of flyer material mechanically covering the barrel at one end, and a semiconductor bridge ignitor including a pair of electrically conductive pads connected by a semiconductor bridge. The bridge is in operational contact with the layer, whereby ignition of said bridge forces a portion of the layer through the barrel to detonate the explosive. Input means are provided for igniting the semiconductor bridge ignitor.

SCB initiator

DOEpatents

Bickes, Jr., Robert W.; Renlund, Anita M.; Stanton, Philip L.

1994-01-01

A detonator for high explosives initiated by mechanical impact includes a cylindrical barrel, a layer of flyer material mechanically covering the barrel at one end, and a semiconductor bridge ignitor including a pair of electrically conductive pads connected by a semiconductor bridge. The bridge is in operational contact with the layer, whereby ignition of said bridge forces a portion of the layer through the barrel to detonate the explosive. Input means are provided for igniting the semiconductor bridge ignitor.

Electron gas grid semiconductor radiation detectors

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

An electron gas grid semiconductor radiation detector (EGGSRAD) useful for gamma-ray and x-ray spectrometers and imaging systems is described. The radiation detector employs doping of the semiconductor and variation of the semiconductor detector material to form a two-dimensional electron gas, and to allow transistor action within the detector. This radiation detector provides superior energy resolution and radiation detection sensitivity over the conventional semiconductor radiation detector and the "electron-only" semiconductor radiation detectors which utilize a grid electrode near the anode. In a first embodiment, the EGGSRAD incorporates delta-doped layers adjacent the anode which produce an internal free electron grid well to which an external grid electrode can be attached. In a second embodiment, a quantum well is formed between two of the delta-doped layers, and the quantum well forms the internal free electron gas grid to which an external grid electrode can be attached. Two other embodiments which are similar to the first and second embodiment involve a graded bandgap formed by changing the composition of the semiconductor material near the first and last of the delta-doped layers to increase or decrease the conduction band energy adjacent to the delta-doped layers.

Method of transferring strained semiconductor structure

DOEpatents

Nastasi, Michael A [Santa Fe, NM; Shao, Lin [College Station, TX

2009-12-29

The transfer of strained semiconductor layers from one substrate to another substrate involves depositing a multilayer structure on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the deposited multilayer structure is bonded to a second substrate and is separated away at the interface, which results in transferring a multilayer structure from one substrate to the other substrate. The multilayer structure includes at least one strained semiconductor layer and at least one strain-induced seed layer. The strain-induced seed layer can be optionally etched away after the layer transfer.

Study and modeling of the transport mechanism in a Schottky diode on the basis of a GaAs semiinsulator

NASA Astrophysics Data System (ADS)

Resfa, A.; Smahi, Bourzig Y.; Menezla, Brahimi R.

2011-12-01

The current through a metal—semiconductor junction is mainly due to the majority carriers. Three distinctly different mechanisms exist in a Schottky diode: diffusion of the semiconductor carriers in metal, thermionic emission-diffusion (TED) of carriers through a Schottky gate, and a mechanical quantum that pierces a tunnel through the gate. The system was solved by using a coupled Poisson—Boltzmann algorithm. Schottky BH is defined as the difference in energy between the Fermi level and the metal band carrier majority of the metal—semiconductor junction to the semiconductor contacts. The insulating layer converts the MS device in an MIS device and has a strong influence on its current—voltage (I—V) and the parameters of a Schottky barrier from 3.7 to 15 eV. There are several possible reasons for the error that causes a deviation of the ideal behaviour of Schottky diodes with and without an interfacial insulator layer. These include the particular distribution of interface states, the series resistance, bias voltage and temperature. The GaAs and its large concentration values of trap centers will participate in an increase in the process of thermionic electrons and holes, which will in turn act on the I—V characteristic of the diode, and an overflow maximum value [NT = 3 × 1020] is obtained. The I—V characteristics of Schottky diodes are in the hypothesis of a parabolic summit.

InP solar cell with window layer

NASA Technical Reports Server (NTRS)

Jain, Raj K. (Inventor); Landis, Geoffrey A. (Inventor)

1994-01-01

The invention features a thin light transmissive layer of the ternary semiconductor indium aluminum arsenide (InAlAs) as a front surface passivation or 'window' layer for p-on-n InP solar cells. The window layers of the invention effectively reduce front surface recombination of the object semiconductors thereby increasing the efficiency of the cells.

Fabrication of optically reflecting ohmic contacts for semiconductor devices

DOEpatents

Sopori, Bhushan L.

1995-01-01

A method is provided to produce a low-resistivity ohmic contact having high optical reflectivity on one side of a semiconductor device. The contact is formed by coating the semiconductor substrate with a thin metal film on the back reflecting side and then optically processing the wafer by illuminating it with electromagnetic radiation of a predetermined wavelength and energy level through the front side of the wafer for a predetermined period of time. This method produces a thin epitaxial alloy layer between the semiconductor substrate and the metal layer when a crystalline substrate is used. The alloy layer provides both a low-resistivity ohmic contact and high optical reflectance.

Solid state photosensitive devices which employ isolated photosynthetic complexes

DOEpatents

Peumans, Peter; Forrest, Stephen R.

2009-09-22

Solid state photosensitive devices including photovoltaic devices are provided which comprise a first electrode and a second electrode in superposed relation; and at least one isolated Light Harvesting Complex (LHC) between the electrodes. Preferred photosensitive devices comprise an electron transport layer formed of a first photoconductive organic semiconductor material, adjacent to the LHC, disposed between the first electrode and the LHC; and a hole transport layer formed of a second photoconductive organic semiconductor material, adjacent to the LHC, disposed between the second electrode and the LHC. Solid state photosensitive devices of the present invention may comprise at least one additional layer of photoconductive organic semiconductor material disposed between the first electrode and the electron transport layer; and at least one additional layer of photoconductive organic semiconductor material, disposed between the second electrode and the hole transport layer. Methods of generating photocurrent are provided which comprise exposing a photovoltaic device of the present invention to light. Electronic devices are provided which comprise a solid state photosensitive device of the present invention.

All-vapor processing of p-type tellurium-containing II-VI semiconductor and ohmic contacts thereof

DOEpatents

McCandless, Brian E.

2001-06-26

An all dry method for producing solar cells is provided comprising first heat-annealing a II-VI semiconductor; enhancing the conductivity and grain size of the annealed layer; modifying the surface and depositing a tellurium layer onto the enhanced layer; and then depositing copper onto the tellurium layer so as to produce a copper tellurium compound on the layer.

p-Type semiconducting nickel oxide as an efficiency-enhancing anodal interfacial layer in bulk heterojunction solar cells

DOEpatents

Irwin, Michael D; Buchholz, Donald B; Marks, Tobin J; Chang, Robert P. H.

2014-11-25

The present invention, in one aspect, relates to a solar cell. In one embodiment, the solar cell includes an anode, a p-type semiconductor layer formed on the anode, and an active organic layer formed on the p-type semiconductor layer, where the active organic layer has an electron-donating organic material and an electron-accepting organic material.

Processes for multi-layer devices utilizing layer transfer

DOEpatents

Nielson, Gregory N; Sanchez, Carlos Anthony; Tauke-Pedretti, Anna; Kim, Bongsang; Cederberg, Jeffrey; Okandan, Murat; Cruz-Campa, Jose Luis; Resnick, Paul J

2015-02-03

A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, T.B.

1985-09-30

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron tunneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, Tomas B.

1987-01-01

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron funneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner.

Chemoresistive gas sensor

DOEpatents

Hirschfeld, T.B.

1987-06-23

A chemoresistive gas sensor is provided which has improved sensitivity. A layer of organic semiconductor is disposed between two electrodes which, in turn, are connected to a voltage source. High conductivity material is dispersed within the layer of organic semiconductor in the form of very small particles, or islands. The average interisland spacing is selected so that the predominant mode of current flow is by way of electron funneling. Adsorption of gaseous contaminant onto the layer of organic semiconductor modulates the tunneling current in a quantitative manner. 2 figs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Usanov, D. A., E-mail: UsanovDA@info.sgu.ru; Nikitov, S. A.; Skripal, A. V.

A method is proposed for the measurement of the electrophysical characteristics of semiconductor structures: the electrical conductivity of the n layer, which plays the role of substrate for a semiconductor structure, and the thickness and electrical conductivity of the strongly doped epitaxial n{sup +} layer. The method is based on the use of a one-dimensional microwave photonic crystal with a violation of periodicity containing the semiconductor structure under investigation. The characteristics of epitaxial gallium-arsenide structures consisting of an epitaxial layer and the semi-insulating substrate measured by this method are presented.

Selective epitaxy using the gild process

DOEpatents

Weiner, Kurt H.

1992-01-01

The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.1-x grown over silicon. Such a process may be used to manufacture small transistors that have a narrow base, heavy doping, and high gain. The narrowness allows a faster transistor, and the heavy doping reduces the resistance of the narrow layer. The process does not require high temperature annealing; therefore materials such as aluminum can be used. Furthermore, the process may be used to fabricate diodes that have a high reverse breakdown voltage and a low reverse leakage current.

Semiconductor devices incorporating multilayer interference regions

DOEpatents

Biefeld, Robert M.; Drummond, Timothy J.; Gourley, Paul L.; Zipperian, Thomas E.

1990-01-01

A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration.

Coincident site lattice-matched growth of semiconductors on substrates using compliant buffer layers

DOEpatents

Norman, Andrew

2016-08-23

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.

Method of manufacturing semiconductor having group II-group VI compounds doped with nitrogen

DOEpatents

Compaan, Alvin D.; Price, Kent J.; Ma, Xianda; Makhratchev, Konstantin

2005-02-08

A method of making a semiconductor comprises depositing a group II-group VI compound onto a substrate in the presence of nitrogen using sputtering to produce a nitrogen-doped semiconductor. This method can be used for making a photovoltaic cell using sputtering to apply a back contact layer of group II-group VI compound to a substrate in the presence of nitrogen, the back coating layer being doped with nitrogen. A semiconductor comprising a group II-group VI compound doped with nitrogen, and a photovoltaic cell comprising a substrate on which is deposited a layer of a group II-group VI compound doped with nitrogen, are also included.

Fabrication of optically reflecting ohmic contacts for semiconductor devices

DOEpatents

Sopori, B.L.

1995-07-04

A method is provided to produce a low-resistivity ohmic contact having high optical reflectivity on one side of a semiconductor device. The contact is formed by coating the semiconductor substrate with a thin metal film on the back reflecting side and then optically processing the wafer by illuminating it with electromagnetic radiation of a predetermined wavelength and energy level through the front side of the wafer for a predetermined period of time. This method produces a thin epitaxial alloy layer between the semiconductor substrate and the metal layer when a crystalline substrate is used. The alloy layer provides both a low-resistivity ohmic contact and high optical reflectance. 5 figs.

Semiconductor devices incorporating multilayer interference regions

DOEpatents

Biefeld, R.M.; Drummond, T.J.; Gourley, P.L.; Zipperian, T.E.

1987-08-31

A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration. 8 figs.

Graphene-Mesoporous Si Nanocomposite as a Compliant Substrate for Heteroepitaxy.

PubMed

Boucherif, Abderrahim Rahim; Boucherif, Abderraouf; Kolhatkar, Gitanjali; Ruediger, Andreas; Arès, Richard

2017-05-01

The ultimate performance of a solid state device is limited by the restricted number of crystalline substrates that are available for epitaxial growth. As a result, only a small fraction of semiconductors are usable. This study describes a novel concept for a tunable compliant substrate for epitaxy, based on a graphene-porous silicon nanocomposite, which extends the range of available lattice constants for epitaxial semiconductor alloys. The presence of graphene and its effect on the strain of the porous layer lattice parameter are discussed in detail and new remarkable properties are demonstrated. These include thermal stability up to 900 °C, lattice tuning up to 0.9 % mismatch, and compliance under stress for virtual substrate thicknesses of several micrometers. A theoretical model is proposed to define the compliant substrate design rules. These advances lay the foundation for the fabrication of a compliant substrate that could unlock the lattice constant restrictions for defect-free new epitaxial semiconductor alloys and devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Semiconductor ferroelectric compositions and their use in photovoltaic devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rappe, Andrew M; Davies, Peter K; Spanier, Jonathan E

Disclosed herein are ferroelectric perovskites characterized as having a band gap, Egap, of less than 2.5 eV. Also disclosed are compounds comprising a solid solution of KNbO3 and BaNi1/2Nb1/2O3-delta, wherein delta is in the range of from 0 to about 1. The specification also discloses photovoltaic devices comprising one or more solar absorbing layers, wherein at least one of the solar absorbing layers comprises a semiconducting ferroelectric layer. Finally, this patent application provides solar cell, comprising: a heterojunction of n- and p-type semiconductors characterized as comprising an interface layer disposed between the n- and p-type semiconductors, the interface layer comprisingmore » a semiconducting ferroelectric absorber layer capable of enhancing light absorption and carrier separation.« less

High efficiency photovoltaic device

DOEpatents

Guha, Subhendu; Yang, Chi C.; Xu, Xi Xiang

1999-11-02

An N-I-P type photovoltaic device includes a multi-layered body of N-doped semiconductor material which has an amorphous, N doped layer in contact with the amorphous body of intrinsic semiconductor material, and a microcrystalline, N doped layer overlying the amorphous, N doped material. A tandem device comprising stacked N-I-P cells may further include a second amorphous, N doped layer interposed between the microcrystalline, N doped layer and a microcrystalline P doped layer. Photovoltaic devices thus configured manifest improved performance, particularly when configured as tandem devices.

Curved grating fabrication techniques for concentric-circle grating, surface-emitting semiconductor lasers

NASA Technical Reports Server (NTRS)

Jordan, Rebecca H.; King, Oliver; Wicks, Gary W.; Hall, Dennis G.; Anderson, Erik H.; Rooks, Michael J.

1993-01-01

We describe the fabrication and operational characteristics of a novel, surface-emitting semiconductor laser that makes use of a concentric-circle grating to both define its resonant cavity and to provide surface emission. A properly fabricated circular grating causes the laser to operate in radially inward- and outward-going circular waves in the waveguide, thus, introducing the circular symmetry needed for the laser to emit a beam with a circular cross-section. The basic circular-grating-resonator concept can be implemented in any materials system; an AlGaAs/GaAs graded-index, separate confinement heterostructure (GRINSCH), single-quantum-well (SQW) semiconductor laser, grown by molecular beam epitaxy (MBE), was used for the experiments discussed here. Each concentric-circle grating was fabricated on the surface of the AlGaAs/GaAs semiconductor laser. The circular pattern was first defined by electron-beam (e-beam) lithography in a layer of polymethylmethacrylate (PMMA) and subsequently etched into the semiconductor surface using chemically-assisted (chlorine) ion-beam etching (CAIBE). We consider issues that affect the fabrication and quality of the gratings. These issues include grating design requirements, data representation of the grating pattern, and e-beam scan method. We provide examples of how these techniques can be implemented and their impact on the resulting laser performance. A comparison is made of the results obtained using two fundamentally different electron-beam writing systems. Circular gratings with period lambda = 0.25 microns and overall diameters ranging from 80 microns to 500 microns were fabricated. We also report our successful demonstration of an optically pumped, concentric-circle grating, semiconductor laser that emits a beam with a far-field divergence angle that is less than one degree. The emission spectrum is quite narrow (less than 0.1 nm) and is centered at wavelength lambda = 0.8175 microns.

Effect of the waveguide layer thickness on output characteristics of semiconductor lasers with emission wavelength from 1500 to 1600 nm

NASA Astrophysics Data System (ADS)

Marmalyuk, A. A.; Ryaboshtan, Yu L.; Gorlachuk, P. V.; Ladugin, M. A.; Padalitsa, A. A.; Slipchenko, S. O.; Lyutetskiy, A. V.; Veselov, D. A.; Pikhtin, N. A.

2018-03-01

The effect of the waveguide layer thickness on output characteristics of AlGaInAs/InP quantum-well semiconductor lasers is analysed. The samples of semiconductor lasers with narrow and wide waveguides are experimentally fabricated. Their comparison is carried out and the advantages of particular constructions depending on the current pump are demonstrated.

Flat-lying semiconductor-insulator interfacial layer in DNTT thin films.

PubMed

Jung, Min-Cherl; Leyden, Matthew R; Nikiforov, Gueorgui O; Lee, Michael V; Lee, Han-Koo; Shin, Tae Joo; Takimiya, Kazuo; Qi, Yabing

2015-01-28

The molecular order of organic semiconductors at the gate dielectric is the most critical factor determining carrier mobility in thin film transistors since the conducting channel forms at the dielectric interface. Despite its fundamental importance, this semiconductor-insulator interface is not well understood, primarily because it is buried within the device. We fabricated dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) thin film transistors by thermal evaporation in vacuum onto substrates held at different temperatures and systematically correlated the extracted charge mobility to the crystal grain size and crystal orientation. As a result, we identify a molecular layer of flat-lying DNTT molecules at the semiconductor-insulator interface. It is likely that such a layer might form in other material systems as well, and could be one of the factors reducing charge transport. Controlling this interfacial flat-lying layer may raise the ultimate possible device performance for thin film devices.

Wavelength-division multiplexed optical integrated circuit with vertical diffraction grating

NASA Technical Reports Server (NTRS)

Lang, Robert J. (Inventor); Forouhar, Siamak (Inventor)

1994-01-01

A semiconductor optical integrated circuit for wave division multiplexing has a semiconductor waveguide layer, a succession of diffraction grating points in the waveguide layer along a predetermined diffraction grating contour, a semiconductor diode array in the waveguide layer having plural optical ports facing the succession of diffraction grating points along a first direction, respective semiconductor diodes in the array corresponding to respective ones of a predetermined succession of wavelengths, an optical fiber having one end thereof terminated at the waveguide layer, the one end of the optical fiber facing the succession of diffraction grating points along a second direction, wherein the diffraction grating points are spatially distributed along the predetermined contour in such a manner that the succession of diffraction grating points diffracts light of respective ones of the succession of wavelengths between the one end of the optical fiber and corresponding ones of the optical ports.

Dye-sensitized solar cells

DOEpatents

Skotheim, T.A.

1980-03-04

A low-cost dye-sensitized Schottky barrier solar cell is comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent. 3 figs.

Dye-sensitized solar cells

DOEpatents

Skotheim, Terje A. [Berkeley, CA

1980-03-04

A low-cost dye-sensitized Schottky barrier solar cell comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent.

Dye-sensitized Schottky barrier solar cells

DOEpatents

Skotheim, Terje A.

1978-01-01

A low-cost dye-sensitized Schottky barrier solar cell comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current. The semiconductor material chosen to be the substrate is one having a wide bandgap and which therefore is transparent; the dye selected is one having a ground state within the bandgap of the semiconductor to generate carriers in the semiconductor, and a first excited state above the conduction band edge of the semiconductor to readily conduct electrons from the dye to the semiconductor; the reducing agent selected is one having a ground state above the ground state of the sensitizer to provide a plentiful source of electrons to the dye during current generation and thereby enhance the generation; and the metal for the thin-film layer of metal is selected to have a Fermi level in the vicinity of or above the ground state of the reducing agent to thereby amply supply electrons to the reducing agent.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Schwank, James R.; Fleetwood, Daniel M.; Shaneyfelt, Marty R.; Winokur, Peter S.; Devine, Roderick A. B.

1998-01-01

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

Quantum well multijunction photovoltaic cell

DOEpatents

Chaffin, R.J.; Osbourn, G.C.

1983-07-08

A monolithic, quantum well, multilayer photovoltaic cell comprises a p-n junction comprising a p-region on one side and an n-region on the other side, each of which regions comprises a series of at least three semiconductor layers, all p-type in the p-region and all n-type in the n-region; each of said series of layers comprising alternating barrier and quantum well layers, each barrier layer comprising a semiconductor material having a first bandgap and each quantum well layer comprising a semiconductor material having a second bandgap when in bulk thickness which is narrower than said first bandgap, the barrier layers sandwiching each quantum well layer and each quantum well layer being sufficiently thin that the width of its bandgap is between said first and second bandgaps, such that radiation incident on said cell and above an energy determined by the bandgap of the quantum well layers will be absorbed and will produce an electrical potential across said junction.

Quantum well multijunction photovoltaic cell

DOEpatents

Chaffin, Roger J.; Osbourn, Gordon C.

1987-01-01

A monolithic, quantum well, multilayer photovoltaic cell comprises a p-n junction comprising a p-region on one side and an n-region on the other side, each of which regions comprises a series of at least three semiconductor layers, all p-type in the p-region and all n-type in the n-region; each of said series of layers comprising alternating barrier and quantum well layers, each barrier layer comprising a semiconductor material having a first bandgap and each quantum well layer comprising a semiconductor material having a second bandgap when in bulk thickness which is narrower than said first bandgap, the barrier layers sandwiching each quantum well layer and each quantum well layer being sufficiently thin that the width of its bandgap is between said first and second bandgaps, such that radiation incident on said cell and above an energy determined by the bandgap of the quantum well layers will be absorbed and will produce an electrical potential across said junction.

Multifunctional Organic-Semiconductor Interfacial Layers for Solution-Processed Oxide-Semiconductor Thin-Film Transistor.

PubMed

Kwon, Guhyun; Kim, Keetae; Choi, Byung Doo; Roh, Jeongkyun; Lee, Changhee; Noh, Yong-Young; Seo, SungYong; Kim, Myung-Gil; Kim, Choongik

2017-06-01

The stabilization and control of the electrical properties in solution-processed amorphous-oxide semiconductors (AOSs) is crucial for the realization of cost-effective, high-performance, large-area electronics. In particular, impurity diffusion, electrical instability, and the lack of a general substitutional doping strategy for the active layer hinder the industrial implementation of copper electrodes and the fine tuning of the electrical parameters of AOS-based thin-film transistors (TFTs). In this study, the authors employ a multifunctional organic-semiconductor (OSC) interlayer as a solution-processed thin-film passivation layer and a charge-transfer dopant. As an electrically active impurity blocking layer, the OSC interlayer enhances the electrical stability of AOS TFTs by suppressing the adsorption of environmental gas species and copper-ion diffusion. Moreover, charge transfer between the organic interlayer and the AOS allows the fine tuning of the electrical properties and the passivation of the electrical defects in the AOS TFTs. The development of a multifunctional solution-processed organic interlayer enables the production of low-cost, high-performance oxide semiconductor-based circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Mixed ternary heterojunction solar cell

DOEpatents

Chen, Wen S.; Stewart, John M.

1992-08-25

A thin film heterojunction solar cell and a method of making it has a p-type layer of mixed ternary I-III-VI.sub.2 semiconductor material in contact with an n-type layer of mixed binary II-VI semiconductor material. The p-type semiconductor material includes a low resistivity copper-rich region adjacent the back metal contact of the cell and a composition gradient providing a minority carrier mirror that improves the photovoltaic performance of the cell. The p-type semiconductor material preferably is CuInGaSe.sub.2 or CuIn(SSe).sub.2.

Photoelectrochemical cells for conversion of solar energy to electricity and methods of their manufacture

DOEpatents

Skotheim, Terje

1984-04-10

A photoelectric device is disclosed which comprises first and second layers of semiconductive material, each of a different bandgap, with a layer of dry solid polymer electrolyte disposed between the two semiconductor layers. A layer of a polymer blend of a highly conductive polymer and a solid polymer electrolyte is further interposed between the dry solid polymer electrolyte and the first semiconductor layer. A method of manufacturing such devices is also disclosed.

Near single-crystalline, high-carrier-mobility silicon thin film on a polycrystalline/amorphous substrate

DOEpatents

Findikoglu, Alp T [Los Alamos, NM; Jia, Quanxi [Los Alamos, NM; Arendt, Paul N [Los Alamos, NM; Matias, Vladimir [Santa Fe, NM; Choi, Woong [Los Alamos, NM

2009-10-27

A template article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material; is provided, together with a semiconductor article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material, and, a top-layer of semiconductor material upon the buffer material layer.

Method for sputtering a PIN microcrystalline/amorphous silicon semiconductor device with the P and N-layers sputtered from boron and phosphorous heavily doped targets

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-04-02

A silicon PIN microcrystalline/amorphous silicon semiconductor device is constructed by the sputtering of N, and P layers of silicon from silicon doped targets and the I layer from an undoped target, and at least one semi-transparent ohmic electrode.

Electrodynamic properties of a hypercrystal with ferrite and semiconductor layers in an external magnetic field

NASA Astrophysics Data System (ADS)

Fedorin, Illia V.

2018-01-01

Electrodynamic properties of a photonic hypercrystal formed by periodically alternating two types of anisotropic metamaterials are studied. The first metamaterial consists of ferrite and dielectric layers, while the second metamaterial consists of semiconductor and dielectric layers. The system is assumed to be placed in an external magnetic field, which applied parallel to the boundaries of the layers. An effective medium theory which is suitable for calculation of properties of long-wavelength electromagnetic modes is applied in order to derive averaged expressions for effective constitutive parameters. It has been shown that providing a conscious choice of the constitutive parameters and material fractions of magnetic, semiconductor, and dielectric layers, the system under study shows hypercrystal properties for both TE and TM waves in the different frequency ranges.

Process for fabricating polycrystalline semiconductor thin-film solar cells, and cells produced thereby

DOEpatents

Wu, Xuanzhi; Sheldon, Peter

2000-01-01

A novel, simplified method for fabricating a thin-film semiconductor heterojunction photovoltaic device includes initial steps of depositing a layer of cadmium stannate and a layer of zinc stannate on a transparent substrate, both by radio frequency sputtering at ambient temperature, followed by the depositing of dissimilar layers of semiconductors such as cadmium sulfide and cadmium telluride, and heat treatment to convert the cadmium stannate to a substantially single-phase material of a spinel crystal structure. Preferably, the cadmium sulfide layer is also deposited by radio frequency sputtering at ambient temperature, and the cadmium telluride layer is deposited by close space sublimation at an elevated temperature effective to convert the amorphous cadmium stannate to the polycrystalline cadmium stannate with single-phase spinel structure.

Architectures and criteria for the design of high efficiency organic photovoltaic cells

DOEpatents

Rand, Barry; Forrest, Stephen R; Pendergrast Burk, Diane

2015-03-31

A method for fabricating an organic photovoltaic cell includes providing a first electrode; depositing a series of at least seven layers onto the first electrode, each layer consisting essentially of a different organic semiconductor material, the organic semiconductor material of at least an intermediate layer of the sequence being a photoconductive material; and depositing a second electrode onto the sequence of at least seven layers. One of the first electrode and the second electrode is an anode and the other is a cathode. The organic semiconductor materials of the series of at least seven layers are arranged to provide a sequence of decreasing lowest unoccupied molecular orbitals (LUMOs) and a sequence of decreasing highest occupied molecular orbitals (HOMOs) across the series from the anode to the cathode.

Charge dissipative dielectric for cryogenic devices

NASA Technical Reports Server (NTRS)

Cantor, Robin Harold (Inventor); Hall, John Addison (Inventor)

2007-01-01

A Superconducting Quantum Interference Device (SQUID) is disclosed comprising a pair of resistively shunted Josephson junctions connected in parallel within a superconducting loop and biased by an external direct current (dc) source. The SQUID comprises a semiconductor substrate and at least one superconducting layer. The metal layer(s) are separated by or covered with a semiconductor material layer having the properties of a conductor at room temperature and the properties of an insulator at operating temperatures (generally less than 100 Kelvins). The properties of the semiconductor material layer greatly reduces the risk of electrostatic discharge that can damage the device during normal handling of the device at room temperature, while still providing the insulating properties desired to allow normal functioning of the device at its operating temperature. A method of manufacturing the SQUID device is also disclosed.

Ion traps fabricated in a CMOS foundry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mehta, K. K.; Ram, R. J.; Eltony, A. M.

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size.more » This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.« less

Electroless epitaxial etching for semiconductor applications

DOEpatents

McCarthy, Anthony M.

2002-01-01

A method for fabricating thin-film single-crystal silicon on insulator substrates using electroless etching for achieving efficient etch stopping on epitaxial silicon substrates. Microelectric circuits and devices are prepared on epitaxial silicon wafers in a standard fabrication facility. The wafers are bonded to a holding substrate. The silicon bulk is removed using electroless etching leaving the circuit contained within the epitaxial layer remaining on the holding substrate. A photolithographic operation is then performed to define streets and wire bond pad areas for electrical access to the circuit.

Back wall solar cell

NASA Technical Reports Server (NTRS)

Brandhorst, H. W., Jr. (Inventor)

1978-01-01

A solar cell is disclosed which comprises a first semiconductor material of one conductivity type with one face having the same conductivity type but more heavily doped to form a field region arranged to receive the radiant energy to be converted to electrical energy, and a layer of a second semiconductor material, preferably highly doped, of opposite conductivity type on the first semiconductor material adjacent the first semiconductor material at an interface remote from the heavily doped field region. Instead of the opposite conductivity layer, a metallic Schottky diode layer may be used, in which case no additional back contact is needed. A contact such as a gridded contact, previous to the radiant energy may be applied to the heavily doped field region of the more heavily doped, same conductivity material for its contact.

Use of separate ZnTe interface layers to form ohmic contacts to p-CdTe films

DOEpatents

Gessert, T.A.

1999-06-01

A method of is disclosed improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising: depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurium-containing II-VI semiconductor, but thin enough to minimize affects of series resistance; depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; and depositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact. 11 figs.

Use of separate ZnTe interface layers to form OHMIC contacts to p-CdTe films

DOEpatents

Gessert, Timothy A.

1999-01-01

A method of improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising: depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurim-containing II-VI semiconductor, but thin enough to minimize affects of series resistance; depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; and depositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact.

A Designed Room Temperature Multilayered Magnetic Semiconductor

NASA Astrophysics Data System (ADS)

Bouma, Dinah Simone; Charilaou, Michalis; Bordel, Catherine; Duchin, Ryan; Barriga, Alexander; Farmer, Adam; Hellman, Frances; Materials Science Division, Lawrence Berkeley National Lab Team

2015-03-01

A room temperature magnetic semiconductor has been designed and fabricated by using an epitaxial antiferromagnet (NiO) grown in the (111) orientation, which gives surface uncompensated magnetism for an odd number of planes, layered with the lightly doped semiconductor Al-doped ZnO (AZO). Magnetization and Hall effect measurements of multilayers of NiO and AZO are presented for varying thickness of each. The magnetic properties vary as a function of the number of Ni planes in each NiO layer; an odd number of Ni planes yields on each NiO layer an uncompensated moment which is RKKY-coupled to the moments on adjacent NiO layers via the carriers in the AZO. This RKKY coupling oscillates with the AZO layer thickness, and it disappears entirely in samples where the AZO is replaced with undoped ZnO. The anomalous Hall effect data indicate that the carriers in the AZO are spin-polarized according to the direction of the applied field at both low temperature and room temperature. NiO/AZO multilayers are therefore a promising candidate for spintronic applications demanding a room-temperature semiconductor.

Abrupt Depletion Layer Approximation for the Metal Insulator Semiconductor Diode.

ERIC Educational Resources Information Center

Jones, Kenneth

1979-01-01

Determines the excess surface change carrier density, surface potential, and relative capacitance of a metal insulator semiconductor diode as a function of the gate voltage, using the precise questions and the equations derived with the abrupt depletion layer approximation. (Author/GA)

Gain in three-dimensional metamaterials utilizing semiconductor quantum structures

NASA Astrophysics Data System (ADS)

Schwaiger, Stephan; Klingbeil, Matthias; Kerbst, Jochen; Rottler, Andreas; Costa, Ricardo; Koitmäe, Aune; Bröll, Markus; Heyn, Christian; Stark, Yuliya; Heitmann, Detlef; Mendach, Stefan

2011-10-01

We demonstrate gain in a three-dimensional metal/semiconductor metamaterial by the integration of optically active semiconductor quantum structures. The rolling-up of a metallic structure on top of strained semiconductor layers containing a quantum well allows us to achieve a tightly bent superlattice consisting of alternating layers of lossy metallic and amplifying gain material. We show that the transmission through the superlattice can be enhanced by exciting the quantum well optically under both pulsed or continuous wave excitation. This points out that our structures can be used as a starting point for arbitrary three-dimensional metamaterials including gain.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Schwank, J.R.; Fleetwood, D.M.; Shaneyfelt, M.R.; Winokur, P.S.; Devine, R.A.B.

1998-07-28

A method is disclosed for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer. 5 figs.

SLS complementary logic devices with increase carrier mobility

DOEpatents

Chaffin, R.J.; Osbourn, G.C.; Zipperian, T.E.

1991-07-09

In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated. 5 figures.

SLS complementary logic devices with increase carrier mobility

DOEpatents

Chaffin, Roger J.; Osbourn, Gordon C.; Zipperian, Thomas E.

1991-01-01

In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubenko, E. B., E-mail: eugene.chubenko@gmail.com; Redko, S. V.; Sherstnyov, A. I.

2016-03-15

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materialsmore » on the basis of porous silicon and nanostructures with a high aspect ratio.« less

Electrically pumped edge-emitting photonic bandgap semiconductor laser

DOEpatents

Lin, Shawn-Yu; Zubrzycki, Walter J.

2004-01-06

A highly efficient, electrically pumped edge-emitting semiconductor laser based on a one- or two-dimensional photonic bandgap (PBG) structure is described. The laser optical cavity is formed using a pair of PBG mirrors operating in the photonic band gap regime. Transverse confinement is achieved by surrounding an active semiconductor layer of high refractive index with lower-index cladding layers. The cladding layers can be electrically insulating in the passive PBG mirror and waveguide regions with a small conducting aperture for efficient channeling of the injection pump current into the active region. The active layer can comprise a quantum well structure. The quantum well structure can be relaxed in the passive regions to provide efficient extraction of laser light from the active region.

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

Traditional Semiconductors in the Two-Dimensional Limit.

PubMed

Lucking, Michael C; Xie, Weiyu; Choe, Duk-Hyun; West, Damien; Lu, Toh-Ming; Zhang, S B

2018-02-23

Interest in two-dimensional materials has exploded in recent years. Not only are they studied due to their novel electronic properties, such as the emergent Dirac fermion in graphene, but also as a new paradigm in which stacking layers of distinct two-dimensional materials may enable different functionality or devices. Here, through first-principles theory, we reveal a large new class of two-dimensional materials which are derived from traditional III-V, II-VI, and I-VII semiconductors. It is found that in the ultrathin limit the great majority of traditional binary semiconductors studied (a series of 28 semiconductors) are not only kinetically stable in a two-dimensional double layer honeycomb structure, but more energetically stable than the truncated wurtzite or zinc-blende structures associated with three dimensional bulk. These findings both greatly increase the landscape of two-dimensional materials and also demonstrate that in the double layer honeycomb form, even ordinary semiconductors, such as GaAs, can exhibit exotic topological properties.

Cadmium-free junction fabrication process for CuInSe.sub.2 thin film solar cells

DOEpatents

Ramanathan, Kannan V.; Contreras, Miguel A.; Bhattacharya, Raghu N.; Keane, James; Noufi, Rommel

1999-01-01

The present invention provides an economical, simple, dry and controllable semiconductor layer junction forming process to make cadmium free high efficiency photovoltaic cells having a first layer comprised primarily of copper indium diselenide having a thin doped copper indium diselenide n-type region, generated by thermal diffusion with a group II(b) element such as zinc, and a halide, such as chlorine, and a second layer comprised of a conventional zinc oxide bilayer. A photovoltaic device according the present invention includes a first thin film layer of semiconductor material formed primarily from copper indium diselenide. Doping of the copper indium diselenide with zinc chloride is accomplished using either a zinc chloride solution or a solid zinc chloride material. Thermal diffusion of zinc chloride into the copper indium diselenide upper region creates the thin n-type copper indium diselenide surface. A second thin film layer of semiconductor material comprising zinc oxide is then applied in two layers. The first layer comprises a thin layer of high resistivity zinc oxide. The second relatively thick layer of zinc oxide is doped to exhibit low resistivity.

Scalable quantum computer architecture with coupled donor-quantum dot qubits

DOEpatents

Schenkel, Thomas; Lo, Cheuk Chi; Weis, Christoph; Lyon, Stephen; Tyryshkin, Alexei; Bokor, Jeffrey

2014-08-26

A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, wherein a first voltage applied across at least one pair of the aligned quantum dot and donor atom controls a donor-quantum dot coupling. A method of performing quantum computing in a scalable architecture quantum computing apparatus includes arranging a pattern of single spin memory donor atoms in a semiconductor layer, forming a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, applying a first voltage across at least one aligned pair of a quantum dot and donor atom to control a donor-quantum dot coupling, and applying a second voltage between one or more quantum dots to control a Heisenberg exchange J coupling between quantum dots and to cause transport of a single spin polarized electron between quantum dots.

Self-cleaning and surface chemical reactions during hafnium dioxide atomic layer deposition on indium arsenide.

PubMed

Timm, Rainer; Head, Ashley R; Yngman, Sofie; Knutsson, Johan V; Hjort, Martin; McKibbin, Sarah R; Troian, Andrea; Persson, Olof; Urpelainen, Samuli; Knudsen, Jan; Schnadt, Joachim; Mikkelsen, Anders

2018-04-12

Atomic layer deposition (ALD) enables the ultrathin high-quality oxide layers that are central to all modern metal-oxide-semiconductor circuits. Crucial to achieving superior device performance are the chemical reactions during the first deposition cycle, which could ultimately result in atomic-scale perfection of the semiconductor-oxide interface. Here, we directly observe the chemical reactions at the surface during the first cycle of hafnium dioxide deposition on indium arsenide under realistic synthesis conditions using photoelectron spectroscopy. We find that the widely used ligand exchange model of the ALD process for the removal of native oxide on the semiconductor and the simultaneous formation of the first hafnium dioxide layer must be significantly revised. Our study provides substantial evidence that the efficiency of the self-cleaning process and the quality of the resulting semiconductor-oxide interface can be controlled by the molecular adsorption process of the ALD precursors, rather than the subsequent oxide formation.

Digital Alloy Absorber for Photodetectors

NASA Technical Reports Server (NTRS)

Hill, Cory J. (Inventor); Ting, David Z. (Inventor); Gunapala, Sarath D. (Inventor)

2016-01-01

In order to increase the spectral response range and improve the mobility of the photo-generated carriers (e.g. in an nBn photodetector), a digital alloy absorber may be employed by embedding one (or fraction thereof) to several monolayers of a semiconductor material (insert layers) periodically into a different host semiconductor material of the absorber layer. The semiconductor material of the insert layer and the host semiconductor materials may have lattice constants that are substantially mismatched. For example, this may performed by periodically embedding monolayers of InSb into an InAsSb host as the absorption region to extend the cutoff wavelength of InAsSb photodetectors, such as InAsSb based nBn devices. The described technique allows for simultaneous control of alloy composition and net strain, which are both key parameters for the photodetector operation.

GUARD RING SEMICONDUCTOR JUNCTION

DOEpatents

Goulding, F.S.; Hansen, W.L.

1963-12-01

A semiconductor diode having a very low noise characteristic when used under reverse bias is described. Surface leakage currents, which in conventional diodes greatly contribute to noise, are prevented from mixing with the desired signal currents. A p-n junction is formed with a thin layer of heavily doped semiconductor material disposed on a lightly doped, physically thick base material. An annular groove cuts through the thin layer and into the base for a short distance, dividing the thin layer into a peripheral guard ring that encircles the central region. Noise signal currents are shunted through the guard ring, leaving the central region free from such currents. (AEC)

Self bleaching photoelectrochemical-electrochromic device

DOEpatents

Bechinger, Clemens S.; Gregg, Brian A.

2002-04-09

A photoelectrochemical-electrochromic device comprising a first transparent electrode and a second transparent electrode in parallel, spaced relation to each other. The first transparent electrode is electrically connected to the second transparent electrode. An electrochromic material is applied to the first transparent electrode and a nanoporous semiconductor film having a dye adsorbed therein is applied to the second transparent electrode. An electrolyte layer contacts the electrochromic material and the nanoporous semiconductor film. The electrolyte layer has a redox couple whereby upon application of light, the nanoporous semiconductor layer dye absorbs the light and the redox couple oxidizes producing an electric field across the device modulating the effective light transmittance through the device.

Mechanisms of Current Transfer in Electrodeposited Layers of Submicron Semiconductor Particles

NASA Astrophysics Data System (ADS)

Zhukov, N. D.; Mosiyash, D. S.; Sinev, I. V.; Khazanov, A. A.; Smirnov, A. V.; Lapshin, I. V.

2017-12-01

Current-voltage ( I- V) characteristics of conductance in multigrain layers of submicron particles of silicon, gallium arsenide, indium arsenide, and indium antimonide have been studied. Nanoparticles of all semiconductors were obtained by processing initial single crystals in a ball mill and applied after sedimentation onto substrates by means of electrodeposition. Detailed analysis of the I- V curves of electrodeposited layers shows that their behavior is determined by the mechanism of intergranular tunneling emission from near-surface electron states of submicron particles. Parameters of this emission process have been determined. The proposed multigrain semiconductor structures can be used in gas sensors, optical detectors, IR imagers, etc.

Metallization of a Rashba wire by a superconducting layer in the strong-proximity regime

NASA Astrophysics Data System (ADS)

Reeg, Christopher; Loss, Daniel; Klinovaja, Jelena

2018-04-01

Semiconducting quantum wires defined within two-dimensional electron gases and strongly coupled to thin superconducting layers have been extensively explored in recent experiments as promising platforms to host Majorana bound states. We study numerically such a geometry, consisting of a quasi-one-dimensional wire coupled to a disordered three-dimensional superconducting layer. We find that, in the strong-coupling limit of a sizable proximity-induced superconducting gap, all transverse subbands of the wire are significantly shifted in energy relative to the chemical potential of the wire. For the lowest subband, this band shift is comparable in magnitude to the spacing between quantized levels that arises due to the finite thickness of the superconductor (which typically is ˜500 meV for a 10-nm-thick layer of aluminum); in higher subbands, the band shift is much larger. Additionally, we show that the width of the system, which is usually much larger than the thickness, and moderate disorder within the superconductor have almost no impact on the induced gap or band shift. We provide a detailed discussion of the ramifications of our results, arguing that a huge band shift and significant renormalization of semiconducting material parameters in the strong-coupling limit make it challenging to realize a topological phase in such a setup, as the strong coupling to the superconductor essentially metallizes the semiconductor. This metallization of the semiconductor can be tested experimentally through the measurement of the band shift.

Two-dimensional layered semiconductor/graphene heterostructures for solar photovoltaic applications.

PubMed

Shanmugam, Mariyappan; Jacobs-Gedrim, Robin; Song, Eui Sang; Yu, Bin

2014-11-07

Schottky barriers formed by graphene (monolayer, bilayer, and multilayer) on 2D layered semiconductor tungsten disulfide (WS2) nanosheets are explored for solar energy harvesting. The characteristics of the graphene-WS2 Schottky junction vary significantly with the number of graphene layers on WS2, resulting in differences in solar cell performance. Compared with monolayer or stacked bilayer graphene, multilayer graphene helps in achieving improved solar cell performance due to superior electrical conductivity. The all-layered-material Schottky barrier solar cell employing WS2 as a photoactive semiconductor exhibits efficient photon absorption in the visible spectral range, yielding 3.3% photoelectric conversion efficiency with multilayer graphene as the Schottky contact. Carrier transport at the graphene/WS2 interface and the interfacial recombination process in the Schottky barrier solar cells are examined.

Proximity charge sensing for semiconductor detectors

DOEpatents

Luke, Paul N; Tindall, Craig S; Amman, Mark

2013-10-08

A non-contact charge sensor includes a semiconductor detector having a first surface and an opposing second surface. The detector includes a high resistivity electrode layer on the first surface and a low resistivity electrode on the high resistivity electrode layer. A portion of the low resistivity first surface electrode is deleted to expose the high resistivity electrode layer in a portion of the area. A low resistivity electrode layer is disposed on the second surface of the semiconductor detector. A voltage applied between the first surface low resistivity electrode and the second surface low resistivity electrode causes a free charge to drift toward the first or second surface according to a polarity of the free charge and the voltage. A charge sensitive preamplifier coupled to a non-contact electrode disposed at a distance from the exposed high resistivity electrode layer outputs a signal in response to movement of free charge within the detector.

Conversion of type of quantum well structure

NASA Technical Reports Server (NTRS)

Ning, Cun-Zheng (Inventor)

2007-01-01

A method for converting a Type 2 quantum well semiconductor material to a Type 1 material. A second layer of undoped material is placed between first and third layers of selectively doped material, which are separated from the second layer by undoped layers having small widths. Doping profiles are chosen so that a first electrical potential increment across a first layer-second layer interface is equal to a first selected value and/or a second electrical potential increment across a second layer-third layer interface is equal to a second selected value. The semiconductor structure thus produced is useful as a laser material and as an incident light detector material in various wavelength regions, such as a mid-infrared region.

Conversion of Type of Quantum Well Structure

NASA Technical Reports Server (NTRS)

Ning, Cun-Zheng (Inventor)

2007-01-01

A method for converting a Type 2 quantum well semiconductor material to a Type 1 material. A second layer of undoped material is placed between first and third layers of selectively doped material, which are separated from the second layer by undoped layers having small widths. Doping profiles are chosen so that a first electrical potential increment across a first layer-second layer interface is equal to a first selected value and/or a second electrical potential increment across a second layer-third layer interface is equal to a second selected value. The semiconductor structure thus produced is useful as a laser material and as an incident light detector material in various wavelength regions, such as a mid-infrared region.

Electrically tunable infrared metamaterial devices

DOEpatents

Brener, Igal; Jun, Young Chul

2015-07-21

A wavelength-tunable, depletion-type infrared metamaterial optical device is provided. The device includes a thin, highly doped epilayer whose electrical permittivity can become negative at some infrared wavelengths. This highly-doped buried layer optically couples with a metamaterial layer. Changes in the transmission spectrum of the device can be induced via the electrical control of this optical coupling. An embodiment includes a contact layer of semiconductor material that is sufficiently doped for operation as a contact layer and that is effectively transparent to an operating range of infrared wavelengths, a thin, highly doped buried layer of epitaxially grown semiconductor material that overlies the contact layer, and a metallized layer overlying the buried layer and patterned as a resonant metamaterial.

Thick layered semiconductor devices with water top-gates: High on-off ratio field-effect transistors and aqueous sensors.

PubMed

Huang, Yuan; Sutter, Eli; Wu, Liangmei; Xu, Hong; Bao, Lihong; Gao, Hong-Jun; Zhou, Xingjiang; Sutter, Peter

2018-06-21

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal sub-threshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels where such control is difficult to realize with conventional back-gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Visible-wavelength semiconductor lasers and arrays

DOEpatents

Schneider, Jr., Richard P.; Crawford, Mary H.

1996-01-01

A visible semiconductor laser. The visible semiconductor laser includes an InAlGaP active region surrounded by one or more AlGaAs layers on each side, with carbon as the sole p-type dopant. Embodiments of the invention are provided as vertical-cavity surface-emitting lasers (VCSELs) and as edge-emitting lasers (EELs). One or more transition layers comprised of a substantially indium-free semiconductor alloy such as AlAsP, AlGaAsP, or the like may be provided between the InAlGaP active region and the AlGaAS DBR mirrors or confinement layers to improve carrier injection and device efficiency by reducing any band offsets. Visible VCSEL devices fabricated according to the invention with a one-wavelength-thick (1.lambda.) optical cavity operate continuous-wave (cw) with lasing output powers up to 8 mW, and a peak power conversion efficiency of up to 11%.

Method for producing a hybridization of detector array and integrated circuit for readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

1993-01-01

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Method and structure for passivating semiconductor material

DOEpatents

Pankove, Jacques I.

1981-01-01

A structure for passivating semiconductor material comprises a substrate of crystalline semiconductor material, a relatively thin film of carbon disposed on a surface of the crystalline material, and a layer of hydrogenated amorphous silicon deposited on the carbon film.

Release strategies for making transferable semiconductor structures, devices and device components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rogers, John A.; Nuzzo, Ralph G.; Meitl, Matthew

2016-05-24

Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Controlled growth of semiconductor crystals

DOEpatents

Bourret-Courchesne, Edith D.

1992-01-01

A method for growth of III-V, II-VI and related semiconductor single crystals that suppresses random nucleation and sticking of the semiconductor melt at the crucible walls. Small pieces of an oxide of boron B.sub.x O.sub.y are dispersed throughout the comminuted solid semiconductor charge in the crucible, with the oxide of boron preferably having water content of at least 600 ppm. The crucible temperature is first raised to a temperature greater than the melt temperature T.sub.m1 of the oxide of boron (T.sub.m1 =723.degree. K. for boron oxide B.sub.2 O.sub.3), and the oxide of boron is allowed to melt and form a reasonably uniform liquid layer between the crucible walls and bottom surfaces and the still-solid semiconductor charge. The temperature is then raised to approximately the melt temperature T.sub.m2 of the semiconductor charge material, and crystal growth proceeds by a liquid encapsulated, vertical gradient freeze process. About half of the crystals grown have a dislocation density of less than 1000/cm.sup.2. If the oxide of boron has water content less than 600 ppm, the crucible material should include boron nitride, a layer of the inner surface of the crucible should be oxidized before the oxide of boron in the crucible charge is melted, and the sum of thicknesses of the solid boron oxide layer and liquid boron oxide layer should be at least 50 .mu.m.

Controlled growth of semiconductor crystals

DOEpatents

Bourret-Courchesne, E.D.

1992-07-21

A method is disclosed for growth of III-V, II-VI and related semiconductor single crystals that suppresses random nucleation and sticking of the semiconductor melt at the crucible walls. Small pieces of an oxide of boron B[sub x]O[sub y] are dispersed throughout the comminuted solid semiconductor charge in the crucible, with the oxide of boron preferably having water content of at least 600 ppm. The crucible temperature is first raised to a temperature greater than the melt temperature T[sub m1] of the oxide of boron (T[sub m1]=723 K for boron oxide B[sub 2]O[sub 3]), and the oxide of boron is allowed to melt and form a reasonably uniform liquid layer between the crucible walls and bottom surfaces and the still-solid semiconductor charge. The temperature is then raised to approximately the melt temperature T[sub m2] of the semiconductor charge material, and crystal growth proceeds by a liquid encapsulated, vertical gradient freeze process. About half of the crystals grown have a dislocation density of less than 1000/cm[sup 2]. If the oxide of boron has water content less than 600 ppm, the crucible material should include boron nitride, a layer of the inner surface of the crucible should be oxidized before the oxide of boron in the crucible charge is melted, and the sum of thicknesses of the solid boron oxide layer and liquid boron oxide layer should be at least 50 [mu]m. 7 figs.

Electroless silver plating of the surface of organic semiconductors.

PubMed

Campione, Marcello; Parravicini, Matteo; Moret, Massimo; Papagni, Antonio; Schröter, Bernd; Fritz, Torsten

2011-10-04

The integration of nanoscale processes and devices demands fabrication routes involving rapid, cost-effective steps, preferably carried out under ambient conditions. The realization of the metal/organic semiconductor interface is one of the most demanding steps of device fabrication, since it requires mechanical and/or thermal treatments which increment costs and are often harmful in respect to the active layer. Here, we provide a microscopic analysis of a room temperature, electroless process aimed at the deposition of a nanostructured metallic silver layer with controlled coverage atop the surface of single crystals and thin films of organic semiconductors. This process relies on the reaction of aqueous AgF solutions with the nonwettable crystalline surface of donor-type organic semiconductors. It is observed that the formation of a uniform layer of silver nanoparticles can be accomplished within 20 min contact time. The electrical characterization of two-terminal devices performed before and after the aforementioned treatment shows that the metal deposition process is associated with a redox reaction causing the p-doping of the semiconductor. © 2011 American Chemical Society

The preparation method of terahertz monolithic integrated device

NASA Astrophysics Data System (ADS)

Zhang, Cong; Su, Bo; He, Jingsuo; Zhang, Hongfei; Wu, Yaxiong; Zhang, Shengbo; Zhang, Cunlin

2018-01-01

The terahertz monolithic integrated device is to integrate the pumping area of the terahertz generation, the detection area of the terahertz receiving and the metal waveguide of terahertz transmission on the same substrate. The terahertz generation and detection device use a photoconductive antenna structure the metal waveguide use a microstrip line structure. The evanescent terahertz-bandwidth electric field extending above the terahertz transmission line interacts with, and is modified by, overlaid dielectric samples, thus enabling the characteristic vibrational absorption resonances in the sample to be probed. In this device structure, since the semiconductor substrate of the photoconductive antenna is located between the strip conductor and the dielectric layer of the microstrip line, and the semiconductor substrate cannot grow on the dielectric layer directly. So how to prepare the semiconductor substrate of the photoconductive antenna and how to bond the semiconductor substrate to the dielectric layer of the microstrip line is a key step in the terahertz monolithic integrated device. In order to solve this critical problem, the epitaxial wafer structure of the two semiconductor substrates is given and transferred to the desired substrate by two methods, respectively.

Casimir Pressure in Mds-Structures

NASA Astrophysics Data System (ADS)

Yurova, V. A.; Bukina, M. N.; Churkin, Yu. V.; Fedortsov, A. B.; Klimchitskaya, G. L.

2012-07-01

The Casimir pressure on the dielectric layer in metal-dielectric-semiconductor (MDS) structures is calculated in the framework of the Lifshitz theory at nonzero temperature. In this calculation the standard parameters of semiconductor devices with a thin dielectric layer are used. We consider the thickness of a layer decreasing from 40 to 1 nm. At the shortest thickness the Casimir pressure achieves 8 MPa. At small thicknesses the results are compared with the predictions of nonrelativistic theory.

Graphene-on-semiconductor substrates for analog electronics

DOEpatents

Lagally, Max G.; Cavallo, Francesca; Rojas-Delgado, Richard

2016-04-26

Electrically conductive material structures, analog electronic devices incorporating the structures and methods for making the structures are provided. The structures include a layer of graphene on a semiconductor substrate. The graphene layer and the substrate are separated by an interfacial region that promotes transfer of charge carriers from the surface of the substrate to the graphene.

Low temperature junction growth using hot-wire chemical vapor deposition

DOEpatents

Wang, Qi; Page, Matthew; Iwaniczko, Eugene; Wang, Tihu; Yan, Yanfa

2014-02-04

A system and a process for forming a semi-conductor device, and solar cells (10) formed thereby. The process includes preparing a substrate (12) for deposition of a junction layer (14); forming the junction layer (14) on the substrate (12) using hot wire chemical vapor deposition; and, finishing the semi-conductor device.

Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

DOEpatents

Fitzgerald, Jr., Eugene A.; Ast, Dieter G.

1992-01-01

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10.times. critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers

DOEpatents

Fitzgerald, Jr., Eugene A.; Ast, Dieter G.

1991-01-01

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10x critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

DOEpatents

Fitzgerald, E.A. Jr.; Ast, D.G.

1992-10-20

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10[times] critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In[sub 0.05]Ga[sub 0.95]As/(001)GaAs interface was controlled by fabricating 2-[mu]m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500 [angstrom] of In[sub 0.05]Ga[sub 0.95]As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-[mu]m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 [mu]m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density. 7 figs.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Semiconductor light source with electrically tunable emission wavelength

DOEpatents

Belenky, Gregory [Port Jefferson, NY; Bruno, John D [Bowie, MD; Kisin, Mikhail V [Centereach, NY; Luryi, Serge [Setauket, NY; Shterengas, Leon [Centereach, NY; Suchalkin, Sergey [Centereach, NY; Tober, Richard L [Elkridge, MD

2011-01-25

A semiconductor light source comprises a substrate, lower and upper claddings, a waveguide region with imbedded active area, and electrical contacts to provide voltage necessary for the wavelength tuning. The active region includes single or several heterojunction periods sandwiched between charge accumulation layers. Each of the active region periods comprises higher and lower affinity semiconductor layers with type-II band alignment. The charge carrier accumulation in the charge accumulation layers results in electric field build-up and leads to the formation of generally triangular electron and hole potential wells in the higher and lower affinity layers. Nonequillibrium carriers can be created in the active region by means of electrical injection or optical pumping. The ground state energy in the triangular wells and the radiation wavelength can be tuned by changing the voltage drop across the active region.

Narrow energy band gap gallium arsenide nitride semi-conductors and an ion-cut-synthesis method for producing the same

DOEpatents

Weng, Xiaojun; Goldman, Rachel S.

2006-06-06

A method for forming a semi-conductor material is provided that comprises forming a donor substrate constructed of GaAs, providing a receiver substrate, implanting nitrogen into the donor substrate to form an implanted layer comprising GaAs and nitrogen. The implanted layer is bonded to the receiver substrate and annealed to form GaAsN and nitrogen micro-blisters in the implanted layer. The micro-blisters allow the implanted layer to be cleaved from the donor substrate.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y. Simon; Deb, Satyen K.

1990-01-01

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

Low resistance barrier layer for isolating, adhering, and passivating copper metal in semiconductor fabrication

DOEpatents

Weihs, Timothy P.; Barbee, Jr., Troy W.

2002-01-01

Cubic or metastable cubic refractory metal carbides act as barrier layers to isolate, adhere, and passivate copper in semiconductor fabrication. One or more barrier layers of the metal carbide are deposited in conjunction with copper metallizations to form a multilayer characterized by a cubic crystal structure with a strong (100) texture. Suitable barrier layer materials include refractory transition metal carbides such as vanadium carbide (VC), niobium carbide (NbC), tantalum carbide (TaC), chromium carbide (Cr.sub.3 C.sub.2), tungsten carbide (WC), and molybdenum carbide (MoC).

Miniaturized Metal (Metal Alloy)/PdO(x)/SiC Hydrogen and Hydrocarbon Gas Sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO(x)). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600 C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sided sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Megahertz organic/polymer diodes

DOEpatents

Katz, Howard Edan; Sun, Jia; Pal, Nath Bhola

2012-12-11

Featured is an organic/polymer diode having a first layer composed essentially of one of an organic semiconductor material or a polymeric semiconductor material and a second layer formed on the first layer and being electrically coupled to the first layer such that current flows through the layers in one direction when a voltage is applied in one direction. The second layer is essentially composed of a material whose characteristics and properties are such that when formed on the first layer, the diode is capable of high frequency rectifications on the order of megahertz rectifications such as for example rectifications at one of above 100KHz, 500KhZ, IMHz, or 10 MHz. In further embodiments, the layers are arranged so as to be exposed to atmosphere.

Photoelectrochemical cell including Ga(Sb.sub.x)N.sub.1-x semiconductor electrode

DOEpatents

Menon, Madhu; Sheetz, Michael; Sunkara, Mahendra Kumar; Pendyala, Chandrashekhar; Sunkara, Swathi; Jasinski, Jacek B.

2017-09-05

The composition of matter comprising Ga(Sb.sub.x)N.sub.1-x where x=0.01 to 0.06 is characterized by a band gap between 2.4 and 1.7 eV. A semiconductor device includes a semiconductor layer of that composition. A photoelectric cell includes that semiconductor device.

Surface and Interface Engineering of Organometallic and Two Dimensional Semiconductor

NASA Astrophysics Data System (ADS)

Park, Jun Hong

For over half a century, inorganic Si and III-V materials have led the modern semiconductor industry, expanding to logic transistor and optoelectronic applications. However, these inorganic materials have faced two different fundamental limitations, flexibility for wearable applications and scaling limitation as logic transistors. As a result, the organic and two dimensional have been studied intentionally for various fields. In the present dissertation, three different studies will be presented with followed order; (1) the chemical response of organic semiconductor in NO2 exposure. (2) The surface and stability of WSe2 in ambient air. (3) Deposition of dielectric on two dimensional materials using organometallic seeding layer. The organic molecules rely on the van der Waals interaction during growth of thin films, contrast to covalent bond inorganic semiconductors. Therefore, the morphology and electronic property at surface of organic semiconductor in micro scale is more sensitive to change in gaseous conditions. In addition, metal phthalocyanine, which is one of organic semiconductor materials, change their electronic property as reaction with gaseous analytes, suggesting as potential chemical sensing platforms. In the present part, the growth behavior of metal phthalocyanine and surface response to gaseous condition will be elucidated using scanning tunneling microscopy (STM). In second part, the surface of layered transition metal dichalcogenides and their chemical response to exposure ambient air will be investigated, using STM. Layered transition metal dichalcogenides (TMDs) have attracted widespread attention in the scientific community for electronic device applications because improved electrostatic gate control and suppression of short channel leakage resulted from their atomic thin body. To fabricate the transistor based on TMDs, TMDs should be exposed to ambient conditions, while the effect of air exposure has not been understood fully. In this part, the effect of ambient air on TMDs will be investigated and partial oxidation of TMDs. In the last part, uniform deposition of dielectric layers on 2D materials will be presented, employing organic seedling layer. Although 2D materials have been expected as next generation semiconductor platform, direct deposition of dielectric is still challenging and induces leakage current commonly, because inertness of their surface resulted from absent of dangling bond. Here, metal phthalocyanine monolayer (ML) is employed as seedling layers and the growth of atomic layer deposition (ALD) dielectric is investigated in each step using STM.

Transparent contacts for stacked compound photovoltaic cells

DOEpatents

Tauke-Pedretti, Anna; Cederberg, Jeffrey; Nielson, Gregory N.; Okandan, Murat; Cruz-Campa, Jose Luis

2016-11-29

A microsystems-enabled multi-junction photovoltaic (MEM-PV) cell includes a first photovoltaic cell having a first junction, the first photovoltaic cell including a first semiconductor material employed to form the first junction, the first semiconductor material having a first bandgap. The MEM-PV cell also includes a second photovoltaic cell comprising a second junction. The second photovoltaic cell comprises a second semiconductor material employed to form the second junction, the second semiconductor material having a second bandgap that is less than the first bandgap, the second photovoltaic cell further comprising a first contact layer disposed between the first junction of the first photovoltaic cell and the second junction of the second photovoltaic cell, the first contact layer composed of a third semiconductor material having a third bandgap, the third bandgap being greater than or equal to the first bandgap.

Design and fabrication of 6.1-.ANG. family semiconductor devices using semi-insulating A1Sb substrate

DOEpatents

Sherohman, John W [Livermore, CA; Coombs, III, Arthur W.; Yee, Jick Hong [Livermore, CA; Wu, Kuang Jen J [Cupertino, CA

2007-05-29

For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-.ANG. family heterostructure devices.

Dry etching method for compound semiconductors

DOEpatents

Shul, Randy J.; Constantine, Christopher

1997-01-01

A dry etching method. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators.

Dry etching method for compound semiconductors

DOEpatents

Shul, R.J.; Constantine, C.

1997-04-29

A dry etching method is disclosed. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators. 1 fig.

Photodetector with enhanced light absorption

DOEpatents

Kane, James

1985-01-01

A photodetector including a light transmissive electrically conducting layer having a textured surface with a semiconductor body thereon. This layer traps incident light thereby enhancing the absorption of light by the semiconductor body. A photodetector comprising a textured light transmissive electrically conducting layer of SnO.sub.2 and a body of hydrogenated amorphous silicon has a conversion efficiency about fifty percent greater than that of comparative cells. The invention also includes a method of fabricating the photodetector of the invention.

Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-07-09

A high efficiency amorphous silicon PIN semiconductor device having partially crystallized (microcrystalline) P and N layers is constructed by the sequential sputtering of N, I and P layers and at least one semi-transparent ohmic electrode. The method of construction produces a PIN device, exhibiting enhanced electrical and optical properties, improved physical integrity, and facilitates the preparation in a singular vacuum system and vacuum pump down procedure.

Apparatus and method of manufacture for an imager equipped with a cross-talk barrier

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2012-01-01

An imager apparatus and associated starting material are provided. In one embodiment, an imager is provided including a silicon layer of a first conductivity type acting as a junction anode. Such silicon layer is adapted to convert light to photoelectrons. Also included is a semiconductor well of a second conductivity type formed in the silicon layer for acting as a junction cathode. Still yet, a barrier is formed adjacent to the semiconductor well. In another embodiment, a starting material is provided including a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Also included is a second silicon layer disposed adjacent to the oxide layer opposite the first silicon layer. Such second silicon layer is further equipped with an associated passivation layer and/or barrier.

Observation of turnover of spontaneous polarization in ferroelectric layer of pentacene/poly-(vinylidene-trifluoroethylene) double-layer capacitor under photo illumination by optical second-harmonic generation measurement

NASA Astrophysics Data System (ADS)

Shi, Zhemin; Taguchi, Dai; Manaka, Takaaki; Iwamoto, Mitsumasa

2016-04-01

The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial charging in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.

van der Waals epitaxial two-dimensional CdSxSe(1-x) semiconductor alloys with tunable-composition and application to flexible optoelectronics.

PubMed

Xia, Jing; Zhao, Yun-Xuan; Wang, Lei; Li, Xuan-Ze; Gu, Yi-Yi; Cheng, Hua-Qiu; Meng, Xiang-Min

2017-09-21

Despite the substantial progress in the development of two-dimensional (2D) materials from conventional layered crystals, it still remains particularly challenging to produce high-quality 2D non-layered semiconductor alloys which may bring in some unique properties and new functions. In this work, the synthesis of well-oriented 2D non-layered CdS x Se (1-x) semiconductor alloy flakes with tunable compositions and optical properties is established. Structural analysis reveals that the 2D non-layered alloys follow an incommensurate van der Waals epitaxial growth pattern. Photoluminescence measurements show that the 2D alloys have composition-dependent direct bandgaps with the emission peak varying from 1.8 eV to 2.3 eV, coinciding well with the density functional theory calculations. Furthermore, photodetectors based on the CdS x Se (1-x) flakes exhibit a high photoresponsivity of 703 A W -1 with an external quantum efficiency of 1.94 × 10 3 and a response time of 39 ms. Flexible devices fabricated on a thin mica substrate display good mechanical stability upon repeated bending. This work suggests a facile and general method to produce high-quality 2D non-layered semiconductor alloys for next-generation optoelectronic devices.

Device and method for luminescence enhancement by resonant energy transfer from an absorptive thin film

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akselrod, Gleb M.; Bawendi, Moungi G.; Bulovic, Vladimir

Disclosed are a device and a method for the design and fabrication of the device for enhancing the brightness of luminescent molecules, nanostructures, and thin films. The device includes a mirror, a dielectric medium or spacer, an absorptive layer, and a luminescent layer. The absorptive layer is a continuous thin film of a strongly absorbing organic or inorganic material. The luminescent layer may be a continuous luminescent thin film or an arrangement of isolated luminescent species, e.g., organic or metal-organic dye molecules, semiconductor quantum dots, or other semiconductor nanostructures, supported on top of the absorptive layer.

Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

DOEpatents

Seager, C.H.; Evans, J.T. Jr.

1998-11-24

A method is described for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100 C and 300 C for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer. 1 fig.

Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

DOEpatents

Seager, Carleton H.; Evans, Jr., Joseph Tate

1998-01-01

A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.

Suppression of planar defects in the molecular beam epitaxy of GaAs/ErAs/GaAs heterostructures

NASA Astrophysics Data System (ADS)

Crook, Adam M.; Nair, Hari P.; Ferrer, Domingo A.; Bank, Seth R.

2011-08-01

We present a growth method that overcomes the mismatch in rotational symmetry of ErAs and conventional III-V semiconductors, allowing for epitaxially integrated semimetal/semiconductor heterostructures. Transmission electron microscopy and reflection high-energy electron diffraction reveal defect-free overgrowth of ErAs layers, consisting of >2× the total amount of ErAs that can be embedded with conventional layer-by-layer growth methods. We utilize epitaxial ErAs nanoparticles, overgrown with GaAs, as a seed to grow full films of ErAs. Growth proceeds by diffusion of erbium atoms through the GaAs spacer, which remains registered to the underlying substrate, preventing planar defect formation during subsequent GaAs growth. This growth method is promising for metal/semiconductor heterostructures that serve as embedded Ohmic contacts to epitaxial layers and epitaxially integrated active plasmonic devices.

Conduit for high temperature transfer of molten semiconductor crystalline material

NASA Technical Reports Server (NTRS)

Fiegl, George (Inventor); Torbet, Walter (Inventor)

1983-01-01

A conduit for high temperature transfer of molten semiconductor crystalline material consists of a composite structure incorporating a quartz transfer tube as the innermost member, with an outer thermally insulating layer designed to serve the dual purposes of minimizing heat losses from the quartz tube and maintaining mechanical strength and rigidity of the conduit at the elevated temperatures encountered. The composite structure ensures that the molten semiconductor material only comes in contact with a material (quartz) with which it is compatible, while the outer layer structure reinforces the quartz tube, which becomes somewhat soft at molten semiconductor temperatures. To further aid in preventing cooling of the molten semiconductor, a distributed, electric resistance heater is in contact with the surface of the quartz tube over most of its length. The quartz tube has short end portions which extend through the surface of the semiconductor melt and which are lef bare of the thermal insulation. The heater is designed to provide an increased heat input per unit area in the region adjacent these end portions.

Photodetector having high speed and sensitivity

DOEpatents

Morse, Jeffrey D.; Mariella, Jr., Raymond P.

1991-01-01

The present invention provides a photodetector having an advantageous combination of sensitivity and speed; it has a high sensitivity while retaining high speed. In a preferred embodiment, visible light is detected, but in some embodiments, x-rays can be detected, and in other embodiments infrared can be detected. The present invention comprises a photodetector having an active layer, and a recombination layer. The active layer has a surface exposed to light to be detected, and comprises a semiconductor, having a bandgap graded so that carriers formed due to interaction of the active layer with the incident radiation tend to be swept away from the exposed surface. The graded semiconductor material in the active layer preferably comprises Al.sub.1-x Ga.sub.x As. An additional sub-layer of graded In.sub.1-y Ga.sub.y As may be included between the Al.sub.1-x Ga.sub.x As layer and the recombination layer. The recombination layer comprises a semiconductor material having a short recombination time such as a defective GaAs layer grown in a low temperature process. The recombination layer is positioned adjacent to the active layer so that carriers from the active layer tend to be swept into the recombination layer. In an embodiment, the photodetector may comprise one or more additional layers stacked below the active and recombination layers. These additional layers may include another active layer and another recombination layer to absorb radiation not absorbed while passing through the first layers. A photodetector having a stacked configuration may have enhanced sensitivity and responsiveness at selected wavelengths such as infrared.

Infrared emitting device and method

DOEpatents

Kurtz, S.R.; Biefeld, R.M.; Dawson, L.R.; Howard, A.J.; Baucom, K.C.

1997-04-29

The infrared emitting device comprises a III-V compound semiconductor substrate upon which are grown a quantum-well active region having a plurality of quantum-well layers formed of a ternary alloy comprising InAsSb sandwiched between barrier layers formed of a ternary alloy having a smaller lattice constant and a larger energy bandgap than the quantum-well layers. The quantum-well layers are preferably compressively strained to increase the threshold energy for Auger recombination; and a method is provided for determining the preferred thickness for the quantum-well layers. Embodiments of the present invention are described having at least one cladding layer to increase the optical and carrier confinement in the active region, and to provide for waveguiding of the light generated within the active region. Examples have been set forth showing embodiments of the present invention as surface- and edge-emitting light emitting diodes (LEDs), an optically-pumped semiconductor laser, and an electrically-injected semiconductor diode laser. The light emission from each of the infrared emitting devices of the present invention is in the midwave infrared region of the spectrum from about 2 to 6 microns. 8 figs.

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2011-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x ). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Xu, Jennifer C. (Inventor); Hunter, Gary W. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Estimation of carrier mobility and charge behaviors of organic semiconductor films in metal-insulator-semiconductor diodes consisting of high-k oxide/organic semiconductor double layers

NASA Astrophysics Data System (ADS)

Chosei, Naoya; Itoh, Eiji

2018-02-01

We have comparatively studied the charge behaviors of organic semiconductor films based on charge extraction by linearly increasing voltage in a metal-insulator-semiconductor (MIS) diode structure (MIS-CELIV) and by classical capacitance-voltage measurement. The MIS-CELIV technique allows the selective measurement of electron and hole mobilities of n- and p-type organic films with thicknesses representative of those of actual devices. We used an anodic oxidized sputtered Ta or Hf electrode as a high-k layer, and it effectively blocked holes at the insulator/semiconductor interface. We estimated the hole mobilities of the polythiophene derivatives regioregular poly(3-hexylthiophene) (P3HT) and poly(3,3‧‧‧-didodecylquarterthiophene) (PQT-12) before and after heat treatment in the ITO/high-k/(thin polymer insulator)/semiconductor/MoO3/Ag device structure. The hole mobility of PQT-12 was improved from 1.1 × 10-5 to 2.1 × 10-5 cm2 V-1 s-1 by the heat treatment of the device at 100 °C for 30 min. An almost two orders of magnitude higher mobility was obtained in MIS diodes with P3HT as the p-type layer. We also determined the capacitance from the displacement current in MIS diodes at a relatively low-voltage sweep, and it corresponded well to the classical capacitance-voltage and frequency measurement results.

Method for making a photodetector with enhanced light absorption

DOEpatents

Kane, James

1987-05-05

A photodetector including a light transmissive electrically conducting layer having a textured surface with a semiconductor body thereon. This layer traps incident light thereby enhancing the absorption of light by the semiconductor body. A photodetector comprising a textured light transmissive electrically conducting layer of SnO.sub.2 and a body of hydrogenated amorphous silicon has a conversion efficiency about fifty percent greater than that of comparative cells. The invention also includes a method of fabricating the photodetector of the invention.

Epitaxial growth of CoO films on semiconductor and metal substrates by constructing a complex heterostructure

NASA Astrophysics Data System (ADS)

Entani, S.; Kiguchi, M.; Saiki, K.; Koma, A.

2003-01-01

Epitaxial growth of CoO films was studied using reflection high-energy electron diffraction (RHEED), electron energy loss spectroscopy (EELS), ultraviolet photoelectron spectroscopy (UPS) and Auger electron spectroscopy (AES). The RHEED results indicated that an epitaxial CoO film grew on semiconductor and metal substrates (CoO (0 0 1)∥GaAs (0 0 1), Cu (0 0 1), Ag (0 0 1) and [1 0 0]CoO∥[1 0 0] substrates) by constructing a complex heterostructure with two alkali halide buffer layers. The AES, EELS and UPS results showed that the grown CoO film had almost the same electronic structure as bulk CoO. We could show that use of alkali halide buffer layers was a good way to grow metal oxide films on semiconductor and metal substrates in an O 2 atmosphere. The alkali halide layers not only works as glue to connect very dissimilar materials but also prevents oxidation of metal and semiconductor substrates.

Photoelectrical Stimulation of Neuronal Cells by an Organic Semiconductor-Electrolyte Interface.

PubMed

Abdullaeva, Oliya S; Schulz, Matthias; Balzer, Frank; Parisi, Jürgen; Lützen, Arne; Dedek, Karin; Schiek, Manuela

2016-08-23

As a step toward the realization of neuroprosthetics for vision restoration, we follow an electrophysiological patch-clamp approach to study the fundamental photoelectrical stimulation mechanism of neuronal model cells by an organic semiconductor-electrolyte interface. Our photoactive layer consisting of an anilino-squaraine donor blended with a fullerene acceptor is supporting the growth of the neuronal model cell line (N2A cells) without an adhesion layer on it and is not impairing cell viability. The transient photocurrent signal upon illumination from the semiconductor-electrolyte layer is able to trigger a passive response of the neuronal cells under physiological conditions via a capacitive coupling mechanism. We study the dynamics of the capacitive transmembrane currents by patch-clamp recordings and compare them to the dynamics of the photocurrent signal and its spectral responsivity. Furthermore, we characterize the morphology of the semiconductor-electrolyte interface by atomic force microscopy and study the stability of the interface in dark and under illuminated conditions.

Microscopic properties of ionic liquid/organic semiconductor interfaces revealed by molecular dynamics simulations.

PubMed

Yokota, Yasuyuki; Miyamoto, Hiroo; Imanishi, Akihito; Takeya, Jun; Inagaki, Kouji; Morikawa, Yoshitada; Fukui, Ken-Ichi

2018-05-09

Electric double-layer transistors based on ionic liquid/organic semiconductor interfaces have been extensively studied during the past decade because of their high carrier densities at low operation voltages. Microscopic structures and the dynamics of ionic liquids likely determine the device performance; however, knowledge of these is limited by a lack of appropriate experimental tools. In this study, we investigated ionic liquid/organic semiconductor interfaces using molecular dynamics to reveal the microscopic properties of ionic liquids. The organic semiconductors include pentacene, rubrene, fullerene, and 7,7,8,8-tetracyanoquinodimethane (TCNQ). While ionic liquids close to the substrate always form the specific layered structures, the surface properties of organic semiconductors drastically alter the ionic dynamics. Ionic liquids at the fullerene interface behave as a two-dimensional ionic crystal because of the energy gain derived from the favorable electrostatic interaction on the corrugated periodic substrate.

The role of ultra-thin SiO2 layers in metal-insulator-semiconductor (MIS) photoelectrochemical devices (Presentation Recording)

NASA Astrophysics Data System (ADS)

Esposito, Daniel V.

2015-08-01

Solid-state junctions based on a metal-insulator-semiconductor (MIS) architecture are of great interest for a number of optoelectronic applications such as photovoltaics, photoelectrochemical cells, and photodetection. One major advantage of the MIS junction compared to the closely related metal-semiconductor junction, or Schottky junction, is that the thin insulating layer (1-3 nm thick) that separates the metal and semiconductor can significantly reduce the density of undesirable interfacial mid-gap states. The reduction in mid-gap states helps "un-pin" the junction, allowing for significantly higher built-in-voltages to be achieved. A second major advantage of the MIS junction is that the thin insulating layer can also protect the underlying semiconductor from corrosion in an electrochemical environment, making the MIS architecture well-suited for application in (photo)electrochemical applications. In this presentation, discontinuous Si-based MIS junctions immersed in electrolyte are explored for use as i.) photoelectrodes for solar-water splitting in photoelectrochemical cells (PECs) and ii.) position-sensitive photodetectors. The development and optimization of MIS photoelectrodes for both of these applications relies heavily on understanding how processing of the thin SiO2 layer impacts the properties of nano- and micro-scale MIS junctions, as well as the interactions of the insulating layer with the electrolyte. In this work, we systematically explore the effects of insulator thickness, synthesis method, and chemical treatment on the photoelectrochemical and electrochemical properties of these MIS devices. It is shown that electrolyte-induced inversion plays a critical role in determining the charge carrier dynamics within the MIS photoelectrodes for both applications.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y.S.; Deb, S.K.

1990-10-02

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

Improved method of preparing p-i-n junctions in amorphous silicon semiconductors

DOEpatents

Madan, A.

1984-12-10

A method of preparing p/sup +/-i-n/sup +/ junctions for amorphous silicon semiconductors includes depositing amorphous silicon on a thin layer of trivalent material, such as aluminum, indium, or gallium at a temperature in the range of 200/sup 0/C to 250/sup 0/C. At this temperature, the layer of trivalent material diffuses into the amorphous silicon to form a graded p/sup +/-i junction. A layer of n-type doped material is then deposited onto the intrinsic amorphous silicon layer in a conventional manner to finish forming the p/sup +/-i-n/sup +/ junction.

Release strategies for making transferable semiconductor structures, devices and device components

DOEpatents

Rogers, John A; Nuzzo, Ralph G; Meitl, Matthew; Ko, Heung Cho; Yoon, Jongseung; Menard, Etienne; Baca, Alfred J

2014-11-25

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Release strategies for making transferable semiconductor structures, devices and device components

DOEpatents

Rogers, John A [Champaign, IL; Nuzzo, Ralph G [Champaign, IL; Meitl, Matthew [Raleigh, NC; Ko, Heung Cho [Urbana, IL; Yoon, Jongseung [Urbana, IL; Menard, Etienne [Durham, NC; Baca, Alfred J [Urbana, IL

2011-04-26

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Novel nano-semiconductor film layer supported nano-Pd Complex Nanostructured Catalyst Pd/Ⓕ-MeOx/AC for High Efficient Selective Hydrogenation of Phenol to Cyclohexanone.

PubMed

Si, Jiaqi; Ouyang, Wenbing; Zhang, Yanji; Xu, Wentao; Zhou, Jicheng

2017-04-28

Supported metal as a type of heterogeneous catalysts are the most widely used in industrial processes. High dispersion of the metal particles of supported catalyst is a key factor in determining the performance of such catalysts. Here we report a novel catalyst Pd/Ⓕ-MeO x /AC with complex nanostructured, Pd nanoparticles supported on the platelike nano-semiconductor film/activated carbon, prepared by the photocatalytic reduction method, which exhibited high efficient catalytic performance for selective hydrogenation of phenol to cyclohexanone. Conversion of phenol achieved up to more than 99% with a lower mole ratio (0.5%) of active components Pd and phenol within 2 h at 70 °C. The synergistic effect of metal nanoparticles and nano-semiconductors support layer and the greatly increasing of contact interface of nano-metal-semiconductors may be responsible for the high efficiency. This work provides a clear demonstration that complex nanostructured catalysts with nano-metal and nano-semiconductor film layer supported on high specific surface AC can yield enhanced catalytic activity and can afford promising approach for developing new supported catalyst.

Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth

DOEpatents

Fan, John C. C.; Tsaur, Bor-Yeu; Gale, Ronald P.; Davis, Frances M.

1992-02-25

Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth

DOEpatents

Fan, John C. C.; Tsaur, Bor-Yeu; Gale, Ronald P.; Davis, Frances M.

1986-12-30

Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps

PubMed Central

Mei, Yaochuan; Diemer, Peter J.; Niazi, Muhammad R.; Hallani, Rawad K.; Jarolimek, Karol; Day, Cynthia S.; Risko, Chad; Anthony, John E.; Amassian, Aram

2017-01-01

The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms. PMID:28739934

Probing dynamic behavior of electric fields and band diagrams in complex semiconductor heterostructures

NASA Astrophysics Data System (ADS)

Turkulets, Yury; Shalish, Ilan

2018-01-01

Modern bandgap engineered electronic devices are typically made of multi-semiconductor multi-layer heterostructures that pose a major challenge to silicon-era characterization methods. As a result, contemporary bandgap engineering relies mostly on simulated band structures that are hardly ever verified experimentally. Here, we present a method that experimentally evaluates bandgap, band offsets, and electric fields, in complex multi-semiconductor layered structures, and it does so simultaneously in all the layers. The method uses a modest optical photocurrent spectroscopy setup at ambient conditions. The results are analyzed using a simple model for electro-absorption. As an example, we apply the method to a typical GaN high electron mobility transistor structure. Measurements under various external electric fields allow us to experimentally construct band diagrams, not only at equilibrium but also under any other working conditions of the device. The electric fields are then used to obtain the charge carrier density and mobility in the quantum well as a function of the gate voltage over the entire range of operating conditions of the device. The principles exemplified here may serve as guidelines for the development of methods for simultaneous characterization of all the layers in complex, multi-semiconductor structures.

Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps.

PubMed

Mei, Yaochuan; Diemer, Peter J; Niazi, Muhammad R; Hallani, Rawad K; Jarolimek, Karol; Day, Cynthia S; Risko, Chad; Anthony, John E; Amassian, Aram; Jurchescu, Oana D

2017-08-15

The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures.

PubMed

Chen, Ruei-San; Tang, Chih-Che; Shen, Wei-Chu; Huang, Ying-Sheng

2015-12-05

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal-semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 Ω(-) (1) cm(-) (1), with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2.

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

PubMed Central

Chen, Ruei-San; Tang, Chih-Che; Shen, Wei-Chu; Huang, Ying-Sheng

2015-01-01

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal–semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 Ω−1 cm−1, with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2. PMID:26710105

Infrared nanoantenna apparatus and method for the manufacture thereof

DOEpatents

Peters, David W.; Davids, Paul; Leonhardt, Darin; Kim, Jin K.; Wendt, Joel R.; Klem, John F.

2014-06-10

An exemplary embodiment of the present invention is a photodetector comprising a semiconductor body, a periodically patterned metal nanoantenna disposed on a surface of the semiconductor body, and at least one electrode separate from the nanoantenna. The semiconductor body comprises an active layer in sufficient proximity to the nanoantenna for plasmonic coupling thereto. The nanoantenna is dimensioned to absorb electromagnetic radiation in at least some wavelengths not more than 12 .mu.m that are effective for plasmonic coupling into the active layer. The electrode is part of an electrode arrangement for obtaining a photovoltage or photocurrent in operation under appropriate stimulation.

Plasma Reflection in Multigrain Layers of Narrow-Bandgap Semiconductors

NASA Astrophysics Data System (ADS)

Zhukov, N. D.; Shishkin, M. I.; Rokakh, A. G.

2018-04-01

Qualitatively similar spectral characteristics of plasma-resonance reflection in the region of 15-25 μm were obtained for layers of electrodeposited submicron particles of InSb, InAs, and GaAs and plates of these semiconductors ground with M1-grade diamond powder. The most narrow-bandgap semiconductor InSb (intrinsic absorption edge ˜7 μm) is characterized by an absorption band at 2.1-2.3 μm, which is interpreted in terms of the model of optical excitation of electrons coupled by the Coulomb interaction. The spectra of a multigrain layer of chemically deposited PbS nanoparticles (50-70 nm) exhibited absorption maxima at 7, 10, and 17 μm, which can be explained by electron transitions obeying the energy-quantization rules for quantum dots.

Metal-Insulator-Semiconductor Diode Consisting of Two-Dimensional Nanomaterials.

PubMed

Jeong, Hyun; Oh, Hye Min; Bang, Seungho; Jeong, Hyeon Jun; An, Sung-Jin; Han, Gang Hee; Kim, Hyun; Yun, Seok Joon; Kim, Ki Kang; Park, Jin Cheol; Lee, Young Hee; Lerondel, Gilles; Jeong, Mun Seok

2016-03-09

We present a novel metal-insulator-semiconductor (MIS) diode consisting of graphene, hexagonal BN, and monolayer MoS2 for application in ultrathin nanoelectronics. The MIS heterojunction structure was fabricated by vertically stacking layered materials using a simple wet chemical transfer method. The stacking of each layer was confirmed by confocal scanning Raman spectroscopy and device performance was evaluated using current versus voltage (I-V) and photocurrent measurements. We clearly observed better current rectification and much higher current flow in the MIS diode than in the p-n junction and the metal-semiconductor diodes made of layered materials. The I-V characteristic curve of the MIS diode indicates that current flows mainly across interfaces as a result of carrier tunneling. Moreover, we observed considerably high photocurrent from the MIS diode under visible light illumination.

Semiconductor laser devices having lateral refractive index tailoring

DOEpatents

Ashby, Carol I. H.; Hadley, G. Ronald; Hohimer, John P.; Owyoung, Adelbert

1990-01-01

A broad-area semiconductor laser diode includes an active lasing region interposed between an upper and a lower cladding layer, the laser diode further comprising structure for controllably varying a lateral refractive index profile of the diode to substantially compensate for an effect of junction heating during operation. In embodiments disclosed the controlling structure comprises resistive heating strips or non-radiative linear junctions disposed parallel to the active region. Another embodiment discloses a multi-layered upper cladding region selectively disordered by implanted or diffused dopant impurities. Still another embodiment discloses an upper cladding layer of variable thickness that is convex in shape and symmetrically disposed about a central axis of the active region. The teaching of the invention is also shown to be applicable to arrays of semiconductor laser diodes.

37 CFR 211.5 - Deposit of identifying material.

Code of Federal Regulations, 2011 CFR

2011-07-01

... fixed in the form of the semiconductor chip product in which it was first commercially exploited... photograph of each layer of the work fixed in a semiconductor chip product. The visually perceptible... complete form of the mask work as fixed in a semiconductor product. (ii) Where the mask work contribution...

Improved Stability and Performance of Visible Photoelectrochemical Water Splitting on Solution-Processed Organic Semiconductor Thin Films by Ultrathin Metal Oxide Passivation

DOE PAGES

Wang, Lei; Yan, Danhua; Shaffer, David W.; ...

2017-12-27

Solution-processable organic semiconductors have potentials as visible photoelectrochemical (PEC) water splitting photoelectrodes due to their tunable small band gap and electronic energy levels, but they are typically limited by poor stability and photocatalytic activity. In this study, we demonstrate the direct visible PEC water oxidation on solution-processed organic semiconductor thin films with improved stability and performance by ultrathin metal oxide passivation layers. N-type fullerene-derivative thin films passivated by sub-2 nm ZnO via atomic layer deposition enabled the visible PEC water oxidation at wavelengths longer than 600 nm in harsh alkaline electrolyte environments with up to 30 μA/cm 2 photocurrents atmore » the thermodynamic water-oxidation equilibrium potential and the photoanode half-lifetime extended to ~1000 s. The systematic investigation reveals the enhanced water oxidation catalytic activity afforded by ZnO passivation and the charge tunneling governing the hole transfer through passivation layers. Further enhanced PEC performances were realized by improving the bottom ohmic contact to the organic semiconductor, achieving ~60 μA/cm 2 water oxidation photocurrent at the equilibrium potential, the highest values reported for organic semiconductor thin films to our knowledge. The improved stability and performance of passivated organic photoelectrodes and discovered design rationales provide useful guidelines for realizing the stable visible solar PEC water splitting based on organic semiconductor thin films.« less

Improved Stability and Performance of Visible Photoelectrochemical Water Splitting on Solution-Processed Organic Semiconductor Thin Films by Ultrathin Metal Oxide Passivation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Lei; Yan, Danhua; Shaffer, David W.

Solution-processable organic semiconductors have potentials as visible photoelectrochemical (PEC) water splitting photoelectrodes due to their tunable small band gap and electronic energy levels, but they are typically limited by poor stability and photocatalytic activity. In this study, we demonstrate the direct visible PEC water oxidation on solution-processed organic semiconductor thin films with improved stability and performance by ultrathin metal oxide passivation layers. N-type fullerene-derivative thin films passivated by sub-2 nm ZnO via atomic layer deposition enabled the visible PEC water oxidation at wavelengths longer than 600 nm in harsh alkaline electrolyte environments with up to 30 μA/cm 2 photocurrents atmore » the thermodynamic water-oxidation equilibrium potential and the photoanode half-lifetime extended to ~1000 s. The systematic investigation reveals the enhanced water oxidation catalytic activity afforded by ZnO passivation and the charge tunneling governing the hole transfer through passivation layers. Further enhanced PEC performances were realized by improving the bottom ohmic contact to the organic semiconductor, achieving ~60 μA/cm 2 water oxidation photocurrent at the equilibrium potential, the highest values reported for organic semiconductor thin films to our knowledge. The improved stability and performance of passivated organic photoelectrodes and discovered design rationales provide useful guidelines for realizing the stable visible solar PEC water splitting based on organic semiconductor thin films.« less

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

1987-06-08

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space. The layer thicknesses of the quantum well layers are selected to provide a superlattice L/sub 2D/-valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley. 2 figs.

Influence of the Compositional Grading on Concentration of Majority Charge Carriers in Near-Surface Layers of n(p)-HgCdTe Grown by Molecular Beam Epitaxy

NASA Astrophysics Data System (ADS)

Voitsekhovskii, A. V.; Nesmelov, S. N.; Dzyadukh, S. M.

2018-02-01

The capacitive characteristics of metal-insulator-semiconductor (MIS) structures based on the compositionally graded Hg1-xCdxTe created by molecular beam epitaxy have been experimentally investigated in a wide temperature range (8-77 K). A program has been developed for numerical simulation of ideal capacitance-voltage (C-V) characteristics in the low-frequency and high-frequency approximations. The concentrations of the majority carriers in the near-surface semiconductor layer are determined from the values of the capacitances in the minima of low-frequency C-V curves. For MIS structures based on p-Hg1-xCdxTe, the effect of the presence of the compositionally graded layer on the hole concentration in the near-surface semiconductor layer, determined from capacitive measurements, has not been established. Perhaps this is due to the fact that the concentration of holes in the near-surface layer largely depends on the type of dielectric coating and the regimes of its application. For MIS structures based on n-Hg1-x Cd x Te (x = 0.22-0.23) without a graded-gap layer, the electron concentration determined by the proposed method is close to the average concentration determined by the Hall measurements. The electron concentration in the near-surface semiconductor layer of the compositionally graded n-Hg1-x Cd x Te (x = 0.22-0.23) found from the minimum capacitance value is much higher than the average electron concentration determined by the Hall measurements. The results are qualitatively explained by the creation of additional intrinsic donor-type defects in the near-surface compositionally graded layer of n-Hg1-x Cd x Te.

Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor)

2011-01-01

Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.

Planar varactor frequency multiplier devices with blocking barrier

NASA Technical Reports Server (NTRS)

Lieneweg, Udo (Inventor); Frerking, Margaret A. (Inventor); Maserjian, Joseph (Inventor)

1994-01-01

The invention relates to planar varactor frequency multiplier devices with a heterojunction blocking barrier for near millimeter wave radiation of moderate power from a fundamental input wave. The space charge limitation of the submillimeter frequency multiplier devices of the BIN(sup +) type is overcome by a diode structure comprising an n(sup +) doped layer of semiconductor material functioning as a low resistance back contact, a layer of semiconductor material with n-type doping functioning as a drift region grown on the back contact layer, a delta doping sheet forming a positive charge at the interface of the drift region layer with a barrier layer, and a surface metal contact. The layers thus formed on an n(sup +) doped layer may be divided into two isolated back-to-back BNN(sup +) diodes by separately depositing two surface metal contacts. By repeating the sequence of the drift region layer and the barrier layer with the delta doping sheet at the interfaces between the drift and barrier layers, a plurality of stacked diodes is formed. The novelty of the invention resides in providing n-type semiconductor material for the drift region in a GaAs/AlGaAs structure, and in stacking a plurality of such BNN(sup +) diodes stacked for greater output power with and connected back-to-back with the n(sup +) GaAs layer as an internal back contact and separate metal contact over an AlGaAs barrier layer on top of each stack.

Fast optical detecting media based on semiconductor nanostructures for recording images obtained using charges of free photocarriers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kasherininov, P. G., E-mail: peter.kasherininov@mail.ioffe.ru; Tomasov, A. A.; Beregulin, E. V.

2011-01-15

Available published data on the properties of optical recording media based on semiconductor structures are reviewed. The principles of operation, structure, parameters, and the range of application for optical recording media based on MIS structures formed of photorefractive crystals with a thick layer of insulator and MIS structures with a liquid crystal as the insulator (the MIS LC modulators), as well as the effect of optical bistability in semiconductor structures (semiconductor MIS structures with nanodimensionally thin insulator (TI) layer, M(TI)S nanostructures). Special attention is paid to recording media based on the M(TI)S nanostructures promising for fast processing of highly informativemore » images and to fabrication of optoelectronic correlators of images for noncoherent light.« less

Low temperature thin films formed from nanocrystal precursors

DOEpatents

Alivisatos, A. Paul; Goldstein, Avery N.

1993-01-01

Nanocrystals of semiconductor compounds are produced. When they are applied as a contiguous layer onto a substrate and heated they fuse into a continuous layer at temperatures as much as 250, 500, 750 or even 1000.degree. K below their bulk melting point. This allows continuous semiconductor films in the 0.25 to 25 nm thickness range to be formed with minimal thermal exposure.

Low temperature thin films formed from nanocrystal precursors

DOEpatents

Alivisatos, A.P.; Goldstein, A.N.

1993-11-16

Nanocrystals of semiconductor compounds are produced. When they are applied as a contiguous layer onto a substrate and heated they fuse into a continuous layer at temperatures as much as 250, 500, 750 or even 1000 K below their bulk melting point. This allows continuous semiconductor films in the 0.25 to 25 nm thickness range to be formed with minimal thermal exposure. 9 figures.

Interlayer Exciton Optoelectronics in a 2D Heterostructure p-n Junction.

PubMed

Ross, Jason S; Rivera, Pasqual; Schaibley, John; Lee-Wong, Eric; Yu, Hongyi; Taniguchi, Takashi; Watanabe, Kenji; Yan, Jiaqiang; Mandrus, David; Cobden, David; Yao, Wang; Xu, Xiaodong

2017-02-08

Semiconductor heterostructures are backbones for solid-state-based optoelectronic devices. Recent advances in assembly techniques for van der Waals heterostructures have enabled the band engineering of semiconductor heterojunctions for atomically thin optoelectronic devices. In two-dimensional heterostructures with type II band alignment, interlayer excitons, where Coulomb bound electrons and holes are confined to opposite layers, have shown promising properties for novel excitonic devices, including a large binding energy, micron-scale in-plane drift-diffusion, and a long population and valley polarization lifetime. Here, we demonstrate interlayer exciton optoelectronics based on electrostatically defined lateral p-n junctions in a MoSe 2 -WSe 2 heterobilayer. Applying a forward bias enables the first observation of electroluminescence from interlayer excitons. At zero bias, the p-n junction functions as a highly sensitive photodetector, where the wavelength-dependent photocurrent measurement allows the direct observation of resonant optical excitation of the interlayer exciton. The resulting photocurrent amplitude from the interlayer exciton is about 200 times smaller than the resonant excitation of intralayer exciton. This implies that the interlayer exciton oscillator strength is 2 orders of magnitude smaller than that of the intralayer exciton due to the spatial separation of electron and hole to the opposite layers. These results lay the foundation for exploiting the interlayer exciton in future 2D heterostructure optoelectronic devices.

Deposition method for producing silicon carbide high-temperature semiconductors

DOEpatents

Hsu, George C.; Rohatgi, Naresh K.

1987-01-01

An improved deposition method for producing silicon carbide high-temperature semiconductor material comprising placing a semiconductor substrate composed of silicon carbide in a fluidized bed silicon carbide deposition reactor, fluidizing the bed particles by hydrogen gas in a mildly bubbling mode through a gas distributor and heating the substrate at temperatures around 1200.degree.-1500.degree. C. thereby depositing a layer of silicon carbide on the semiconductor substrate.

Layered semiconductor neutron detectors

DOEpatents

Mao, Samuel S; Perry, Dale L

2013-12-10

Room temperature operating solid state hand held neutron detectors integrate one or more relatively thin layers of a high neutron interaction cross-section element or materials with semiconductor detectors. The high neutron interaction cross-section element (e.g., Gd, B or Li) or materials comprising at least one high neutron interaction cross-section element can be in the form of unstructured layers or micro- or nano-structured arrays. Such architecture provides high efficiency neutron detector devices by capturing substantially more carriers produced from high energy .alpha.-particles or .gamma.-photons generated by neutron interaction.

Tuning the Performance of Organic Spintronic Devices Using X-Ray Generated Traps

DTIC Science & Technology

2012-08-16

observed in organic devices using the same organic semiconductor, namely tris(8-hydroxyquinoli- nato)aluminium ( Alq3 ) [5,15]. Here we will show that the...manufacturing steps were carried out in a deposition chamber located inside a nitrogen glovebox. Next, the organic layer Alq3 (70 to 100 nm) followed by the...As the organic semiconductor spacer layer, the Alq3 layer was fabricated by thermal evaporation in a vacuum of 10Ś mbar at a rate of 0:1 nm=s. The Fe

Semiconductor laser having a non-absorbing passive region with beam guiding

NASA Technical Reports Server (NTRS)

Botez, Dan (Inventor)

1986-01-01

A laser comprises a semiconductor body having a pair of end faces and including an active region comprising adjacent active and guide layers which is spaced a distance from the end face and a passive region comprising adjacent non-absorbing guide and mode control layers which extends between the active region and the end face. The combination of the guide and mode control layers provides a weak positive index waveguide in the lateral direction thereby providing lateral mode control in the passive region between the active region and the end face.

Infrared emitting device and method

DOEpatents

Kurtz, Steven R.; Biefeld, Robert M.; Dawson, L. Ralph; Howard, Arnold J.; Baucom, Kevin C.

1997-01-01

An infrared emitting device and method. The infrared emitting device comprises a III-V compound semiconductor substrate upon which are grown a quantum-well active region having a plurality of quantum-well layers formed of a ternary alloy comprising InAsSb sandwiched between barrier layers formed of a ternary alloy having a smaller lattice constant and a larger energy bandgap than the quantum-well layers. The quantum-well layers are preferably compressively strained to increase the threshold energy for Auger recombination; and a method is provided for determining the preferred thickness for the quantum-well layers. Embodiments of the present invention are described having at least one cladding layer to increase the optical and carrier confinement in the active region, and to provide for waveguiding of the light generated within the active region. Examples have been set forth showing embodiments of the present invention as surface- and edge-emitting light emitting diodes (LEDs), an optically-pumped semiconductor laser, and an electrically-injected semiconductor diode laser. The light emission from each of the infrared emitting devices of the present invention is in the midwave infrared region of the spectrum from about 2 to 6 microns.

Photo-voltaic power generating means and methods

DOEpatents

Kroger, Ferdinand A.; Rod, Robert L.; Panicker, M. P. Ramachandra

1983-08-23

A photo-voltaic power cell based on a photoelectric semiconductor compound and the method of using and making the same. The semiconductor compound in the photo-voltaic power cell of the present invention can be electrolytically formed at a cathode in an electrolytic solution by causing discharge or decomposition of ions or molecules of a non-metallic component with deposition of the non-metallic component on the cathode and simultaneously providing ions of a metal component which discharge and combine with the non-metallic component at the cathode thereby forming the semiconductor compound film material thereon. By stoichiometrically adjusting the amounts of the components, or otherwise by introducing dopants into the desired amounts, an N-type layer can be formed and thereafter a P-type layer can be formed with a junction therebetween. The invention is effective in producing homojunction semiconductor materials and heterojunction semiconductor materials. The present invention also provides a method of using three electrodes in order to form the semiconductor compound material on one of these electrodes. Various examples are given for manufacturing different photo-voltaic cells in accordance with the present invention.

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Photo-voltaic power generating means and methods

DOEpatents

Kroger, Ferdinand A.; Rod, Robert L.; Panicker, Ramachandra M. P.; Knaster, Mark B.

1984-01-10

A photo-voltaic power cell based on a photoelectric semiconductor compound and the method of using and making the same. The semiconductor compound in the photo-voltaic power cell of the present invention can be electrolytically formed at a cathode in an electrolytic solution by causing discharge or decomposition of ions or molecules of a non-metallic component with deposition of the non-metallic component on the cathode and simultaneously providing ions of a metal component which discharge and combine with the non-metallic component at the cathode thereby forming the semiconductor compound film material thereon. By stoichiometrically adjusting the amounts of the components, or otherwise by introducing dopants into the desired amounts, an N-type layer can be formed and thereafter a P-type layer can be formed with a junction therebetween. The invention is effective in producing homojunction semiconductor materials and heterojunction semiconductor materials. The present invention also provides a method of using three electrodes in order to form the semiconductor compound material on one of these electrodes. Various examples are given for manufacturing different photo-voltaic cells in accordance with the present invention.

Time-Resolved Photoluminescence Microscopy for the Analysis of Semiconductor-Based Paint Layers

PubMed Central

Mosca, Sara; Gonzalez, Victor; Eveno, Myriam

2017-01-01

In conservation, science semiconductors occur as the constituent matter of the so-called semiconductor pigments, produced following the Industrial Revolution and extensively used by modern painters. With recent research highlighting the occurrence of various degradation phenomena in semiconductor paints, it is clear that their detection by conventional optical fluorescence imaging and microscopy is limited by the complexity of historical painting materials. Here, we illustrate and prove the capabilities of time-resolved photoluminescence (TRPL) microscopy, equipped with both spectral and lifetime sensitivity at timescales ranging from nanoseconds to hundreds of microseconds, for the analysis of cross-sections of paint layers made of luminescent semiconductor pigments. The method is sensitive to heterogeneities within micro-samples and provides valuable information for the interpretation of the nature of the emissions in samples. A case study is presented on micro samples from a painting by Henri Matisse and serves to demonstrate how TRPL can be used to identify the semiconductor pigments zinc white and cadmium yellow, and to inform future investigations of the degradation of a cadmium yellow paint. PMID:29160862

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Semiconductor cylinder fiber laser

NASA Astrophysics Data System (ADS)

Sandupatla, Abhinay; Flattery, James; Kornreich, Philipp

2015-12-01

We fabricated a fiber laser that uses a thin semiconductor layer surrounding the glass core as the gain medium. This is a completely new type of laser. The In2Te3 semiconductor layer is about 15-nm thick. The fiber laser has a core diameter of 14.2 μm, an outside diameter of 126 μm, and it is 25-mm long. The laser mirrors consist of a thick vacuum-deposited aluminum layer at one end and a thin semitransparent aluminum layer deposited at the other end of the fiber. The laser is pumped from the side with either light from a halogen tungsten incandescent lamp or a blue light emitting diode flash light. Both the In2Te3 gain medium and the aluminum mirrors have a wide bandwidth. Therefore, the output spectrum consists of a pedestal from a wavelength of about 454 to 623 nm with several peaks. There is a main peak at 545 nm. The main peak has an amplitude of 16.5 dB above the noise level of -73 dB.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

PubMed Central

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

Apparatus and methods for memory using in-plane polarization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Junwei; Chang, Kai; Ji, Shuai-Hua

A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process ismore » non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.« less

Metal-oxide-semiconductor devices using Ga2O3 dielectrics on n-type GaN

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Chen, Hong-Wei; Lee, Hsin-Ying

2003-06-01

Using a photoelectrochemical method involving a He-Cd laser, Ga2O3 oxide layers were directly grown on n-type GaN. We demonstrated the performance of the resultant metal-oxide-semiconductor devices based on the grown Ga2O3 layer. An extremely low reverse leakage current of 200 pA was achieved when devices operated at -20 V. Furthermore, high forward and reverse breakdown electric fields of 2.80 MV/cm and 5.70 MV/cm, respectively, were obtained. Using a photoassisted current-voltage method, a low interface state density of 2.53×1011 cm-2 eV-1 was estimated. The varactor devices permit formation of inversion layers, so that they may be applied for the fabrication of metal-oxide-semiconductor field-effect transistors.

Prediction of weak topological insulators in layered semiconductors.

PubMed

Yan, Binghai; Müchler, Lukas; Felser, Claudia

2012-09-14

We report the discovery of weak topological insulators by ab initio calculations in a honeycomb lattice. We propose a structure with an odd number of layers in the primitive unit cell as a prerequisite for forming weak topological insulators. Here, the single-layered KHgSb is the most suitable candidate for its large bulk energy gap of 0.24 eV. Its side surface hosts metallic surface states, forming two anisotropic Dirac cones. Although the stacking of even-layered structures leads to trivial insulators, the structures can host a quantum spin Hall layer with a large bulk gap, if an additional single layer exists as a stacking fault in the crystal. The reported honeycomb compounds can serve as prototypes to aid in the finding of new weak topological insulators in layered small-gap semiconductors.

Ultrafast and Ultrasensitive Gas Sensors Derived from a Large Fermi-Level Shift in the Schottky Junction with Sieve-Layer Modulation.

PubMed

Cheng, Ching-Cheng; Wu, Chia-Lin; Liao, Yu-Ming; Chen, Yang-Fang

2016-07-13

Gas sensors play an important role in numerous fields, covering a wide range of applications, including intelligent systems and detection of harmful and toxic gases. Even though they have attracted much attention, the response time on the order of seconds to minutes is still very slow. To circumvent the existing problems, here, we provide a seminal attempt with the integration of graphene, semiconductor, and an addition sieve layer forming a nanocomposite gas sensor with ultrahigh sensitivity and ultrafast response. The designed sieve layer has a suitable band structure that can serve as a blocking layer to prevent transfer of the charges induced by adsorbed gas molecules into the underlying semiconductor layer. We found that the sensitivity can be reduced to the parts per million level, and the ultrafast response of around 60 ms is unprecedented compared with published graphene-based gas sensors. The achieved high performance can be interpreted well by the large change of the Fermi level of graphene due to its inherent nature of the low density of states and blocking of the sieve layer to prevent charge transfer from graphene to the underlying semiconductor layer. Accordingly, our work is very useful and timely for the development of gas sensors with high performance for practical applications.

Broadband light-emitting diode

DOEpatents

Fritz, Ian J.; Klem, John F.; Hafich, Michael J.

1998-01-01

A broadband light-emitting diode. The broadband light-emitting diode (LED) comprises a plurality of III-V compound semiconductor layers grown on a semiconductor substrate, with the semiconductor layers including a pair of cladding layers sandwiched about a strained-quantum-well active region having a plurality of different energy bandgaps for generating light in a wavelength range of about 1.3-2 .mu.m. In one embodiment of the present invention, the active region may comprise a first-grown quantum-well layer and a last-grown quantum-well layer that are oppositely strained; whereas in another embodiment of the invention, the active region is formed from a short-period superlattice structure (i.e. a pseudo alloy) comprising alternating thin layers of InGaAs and InGaAlAs. The use a short-period superlattice structure for the active region allows different layers within the active region to be simply and accurately grown by repetitively opening and closing one or more shutters in an MBE growth apparatus to repetitively switch between different growth states therein. The broadband LED may be formed as either a surface-emitting LED or as an edge-emitting LED for use in applications such as chemical sensing, fiber optic gyroscopes, wavelength-division-multiplexed (WDM) fiber-optic data links, and WDM fiber-optic sensor networks for automobiles and aircraft.

Broadband light-emitting diode

DOEpatents

Fritz, I.J.; Klem, J.F.; Hafich, M.J.

1998-07-14

A broadband light-emitting diode is disclosed. The broadband light-emitting diode (LED) comprises a plurality of III-V compound semiconductor layers grown on a semiconductor substrate, with the semiconductor layers including a pair of cladding layers sandwiched about a strained-quantum-well active region having a plurality of different energy bandgaps for generating light in a wavelength range of about 1.3--2 {micro}m. In one embodiment of the present invention, the active region may comprise a first-grown quantum-well layer and a last-grown quantum-well layer that are oppositely strained; whereas in another embodiment of the invention, the active region is formed from a short-period superlattice structure (i.e. a pseudo alloy) comprising alternating thin layers of InGaAs and InGaAlAs. The use a short-period superlattice structure for the active region allows different layers within the active region to be simply and accurately grown by repetitively opening and closing one or more shutters in an MBE growth apparatus to repetitively switch between different growth states therein. The broadband LED may be formed as either a surface-emitting LED or as an edge-emitting LED for use in applications such as chemical sensing, fiber optic gyroscopes, wavelength-divisionmultiplexed (WDM) fiber-optic data links, and WDM fiber-optic sensor networks for automobiles and aircraft. 10 figs.

Method and apparatus for increasing the durability and yield of thin film photovoltaic devices

DOEpatents

Phillips, J.E.; Lasswell, P.G.

1987-02-03

Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device. 10 figs.

Method and apparatus for increasing the durability and yield of thin film photovoltaic devices

DOEpatents

Phillips, James E.; Lasswell, Patrick G.

1987-01-01

Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device.

Investigations on Substrate Temperature-Induced Growth Modes of Organic Semiconductors at Dielectric/semiconductor Interface and Their Correlation with Threshold Voltage Stability in Organic Field-Effect Transistors.

PubMed

Padma, Narayanan; Maheshwari, Priya; Bhattacharya, Debarati; Tokas, Raj B; Sen, Shashwati; Honda, Yoshihide; Basu, Saibal; Pujari, Pradeep Kumar; Rao, T V Chandrasekhar

2016-02-10

Influence of substrate temperature on growth modes of copper phthalocyanine (CuPc) thin films at the dielectric/semiconductor interface in organic field effect transistors (OFETs) is investigated. Atomic force microscopy (AFM) imaging at the interface reveals a change from 'layer+island' to "island" growth mode with increasing substrate temperatures, further confirmed by probing the buried interfaces using X-ray reflectivity (XRR) and positron annihilation spectroscopic (PAS) techniques. PAS depth profiling provides insight into the details of molecular ordering while positron lifetime measurements reveal the difference in packing modes of CuPc molecules at the interface. XRR measurements show systematic increase in interface width and electron density correlating well with the change from layer + island to coalesced huge 3D islands at higher substrate temperatures. Study demonstrates the usefulness of XRR and PAS techniques to study growth modes at buried interfaces and reveals the influence of growth modes of semiconductor at the interface on hole and electron trap concentrations individually, thereby affecting hysteresis and threshold voltage stability. Minimum hole trapping is correlated to near layer by layer formation close to the interface at 100 °C and maximum to the island formation with large voids between the grains at 225 °C.

Pump-probe surface photovoltage spectroscopy measurements on semiconductor epitaxial layers.

PubMed

Jana, Dipankar; Porwal, S; Sharma, T K; Kumar, Shailendra; Oak, S M

2014-04-01

Pump-probe Surface Photovoltage Spectroscopy (SPS) measurements are performed on semiconductor epitaxial layers. Here, an additional sub-bandgap cw pump laser beam is used in a conventional chopped light geometry SPS setup under the pump-probe configuration. The main role of pump laser beam is to saturate the sub-bandgap localized states whose contribution otherwise swamp the information related to the bandgap of material. It also affects the magnitude of Dember voltage in case of semi-insulating (SI) semiconductor substrates. Pump-probe SPS technique enables an accurate determination of the bandgap of semiconductor epitaxial layers even under the strong influence of localized sub-bandgap states. The pump beam is found to be very effective in suppressing the effect of surface/interface and bulk trap states. The overall magnitude of SPV signal is decided by the dependence of charge separation mechanisms on the intensity of the pump beam. On the contrary, an above bandgap cw pump laser can be used to distinguish the signatures of sub-bandgap states by suppressing the band edge related feature. Usefulness of the pump-probe SPS technique is established by unambiguously determining the bandgap of p-GaAs epitaxial layers grown on SI-GaAs substrates, SI-InP wafers, and p-GaN epilayers grown on Sapphire substrates.

The AMOS cell - An improved metal-semiconductor solar cell. [Antireflection coated Metal Oxide Semiconductor

NASA Technical Reports Server (NTRS)

Stirn, R. J.; Yeh, Y.-C. M.

1975-01-01

A new fabrication process is being developed which significantly improves the efficiency of metal-semiconductor solar cells. The resultant effect, a marked increase in the open-circuit voltage, is produced by the addition of an interfacial layer oxide on the semiconductor. Cells using gold on n-type gallium arsenide have been made in small areas (0.17 sq cm) with conversion efficiencies of 15% in terrestrial sunlight.

Materials Science and Device Physics of 2-Dimensional Semiconductors

NASA Astrophysics Data System (ADS)

Fang, Hui

Materials and device innovations are the keys to future technology revolution. For MOSFET scaling in particular, semiconductors with ultra-thin thickness on insulator platform is currently of great interest, due to the potential of integrating excellent channel materials with the industrially mature Si processing. Meanwhile, ultra-thin thickness also induces strong quantum confinement which in turn affect most of the material properties of these 2-dimensional (2-D) semiconductors, providing unprecedented opportunities for emerging technologies. In this thesis, multiple novel 2-D material systems are explored. Chapter one introduces the present challenges faced by MOSFET scaling. Chapter two covers the integration of ultrathin III V membranes with Si. Free standing ultrathin III-V is studied to enable high performance III-V on Si MOSFETs with strain engineering and alloying. Chapter three studies the light absorption in 2-D membranes. Experimental results and theoretical analysis reveal that light absorption in the 2-D quantum membranes is quantized into a fundamental physical constant, where we call it the quantum unit of light absorption, irrelevant of most of the material dependent parameters. Chapter four starts to focus on another 2-D system, atomic thin layered chalcogenides. Single and few layered chalcogenides are first explored as channel materials, with focuses in engineering the contacts for high performance MOSFETs. Contact treatment by molecular doping methods reveals that many layered chalcogenides other than MoS2 exhibit good transport properties at single layer limit. Finally, Chapter five investigated 2-D van der Waals heterostructures built from different single layer chalcogenides. The investigation in a WSe2/MoS2 hetero-bilayer shows a large Stokes like shift between photoluminescence peak and lowest absorption peak, as well as strong photoluminescence intensity, consistent with spatially indirect transition in a type II band alignment in this van der Waals heterostructure. This result enables new family of semiconductor heterostructures having tunable optoelectronic properties with customized composite layers and highlights the ability to build van der Waals semiconductor heterostructure lasers/LEDs.

Magnetism in Mn-nanowires and -clusters as δ-doped layers in group IV semiconductors (Si, Ge)

NASA Astrophysics Data System (ADS)

Simov, K. R.; Glans, P.-A.; Jenkins, C. A.; Liberati, M.; Reinke, P.

2018-01-01

Mn doping of group-IV semiconductors (Si/Ge) is achieved by embedding nanostructured Mn-layers in group-IV matrix. The Mn-nanostructures are monoatomic Mn-wires or Mn-clusters and capped with an amorphous Si or Ge layer. The precise fabrication of δ-doped Mn-layers is combined with element-specific detection of the magnetic signature with x-ray magnetic circular dichroism. The largest moment (2.5 μB/Mn) is measured for Mn-wires with ionic bonding character and a-Ge overlayer cap; a-Si capping reduces the moment due to variations of bonding in agreement with theoretical predictions. The moments in δ-doped layers dominated by clusters is quenched with an antiferromagnetic component from Mn-Mn bonding.

Ultra-thin ohmic contacts for p-type nitride light emitting devices

DOEpatents

Raffetto, Mark; Bharathan, Jayesh; Haberern, Kevin; Bergmann, Michael; Emerson, David; Ibbetson, James; Li, Ting

2014-06-24

A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 .ANG.. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

A lead-halide perovskite molecular ferroelectric semiconductor

PubMed Central

Liao, Wei-Qiang; Zhang, Yi; Hu, Chun-Li; Mao, Jiang-Gao; Ye, Heng-Yun; Li, Peng-Fei; Huang, Songping D.; Xiong, Ren-Gen

2015-01-01

Inorganic semiconductor ferroelectrics such as BiFeO3 have shown great potential in photovoltaic and other applications. Currently, semiconducting properties and the corresponding application in optoelectronic devices of hybrid organo-plumbate or stannate are a hot topic of academic research; more and more of such hybrids have been synthesized. Structurally, these hybrids are suitable for exploration of ferroelectricity. Therefore, the design of molecular ferroelectric semiconductors based on these hybrids provides a possibility to obtain new or high-performance semiconductor ferroelectrics. Here we investigated Pb-layered perovskites, and found the layer perovskite (benzylammonium)2PbCl4 is ferroelectric with semiconducting behaviours. It has a larger ferroelectric spontaneous polarization Ps=13 μC cm−2 and a higher Curie temperature Tc=438 K with a band gap of 3.65 eV. This finding throws light on the new properties of the hybrid organo-plumbate or stannate compounds and provides a new way to develop new semiconductor ferroelectrics. PMID:26021758

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2017-01-01

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2016-01-01

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Single-layer ZnMN2 (M = Si, Ge, Sn) zinc nitrides as promising photocatalysts.

PubMed

Bai, Yujie; Luo, Gaixia; Meng, Lijuan; Zhang, Qinfang; Xu, Ning; Zhang, Haiyang; Wu, Xiuqiang; Kong, Fanjie; Wang, Baolin

2018-05-30

Searching for two-dimensional semiconductor materials that are suitable for visible-light photocatalytic water splitting provides a sustainable solution to deal with the future energy crisis and environmental problems. Herein, based on first-principles calculations, single-layer ZnMN2 (M = Si, Ge, Sn) zinc nitrides are proposed as efficient photocatalysts for water splitting. Stability analyses show that the single-layer ZnMN2 zinc nitrides exhibit energetic and dynamical stability. The electronic properties reveal that all of the single-layer ZnMN2 zinc nitrides are semiconductors. Interestingly, single-layer ZnSnN2 is a direct band gap semiconductor with a desirable band gap (1.74 eV), and the optical adsorption spectrum confirms its optical absorption in the visible light region. The hydrogen evolution reaction (HER) calculations show that the catalytic activity for single-layer ZnMN2 (M = Ge, Sn) is better than that of single-layer ZnSiN2. Furthermore, the band gaps and band edge positions for the single-layer ZnMN2 zinc nitrides can be effectively tuned by biaxial strain. Especially, single-layer ZnGeN2 can be effectively tuned to match better with the redox potentials of water and enhance the light absorption in the visible light region at a tensile strain of 5%, which is confirmed by the corresponding optical absorption spectrum. Our results provide guidance for experimental synthesis efforts and future searches for single-layer materials suitable for photocatalytic water splitting.

Graded Index Silicon Geranium on Lattice Matched Silicon Geranium Semiconductor Alloy

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor); Elliott, James R., Jr. (Inventor); Stoakley, Diane M. (Inventor)

2009-01-01

A lattice matched silicon germanium (SiGe) semiconductive alloy is formed when a {111} crystal plane of a cubic diamond structure SiGe is grown on the {0001} C-plane of a single crystalline Al2O3 substrate such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,-1,0> orientation of the {0001} C-plane. A lattice match between the substrate and the SiGe is achieved by using a SiGe composition that is 0.7223 atomic percent silicon and 0.2777 atomic percent germanium. A layer of Si(1-x), ,Ge(x) is formed on the cubic diamond structure SiGe. The value of X (i) defines an atomic percent of germanium satisfying 0.2277

Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

NASA Astrophysics Data System (ADS)

Biyikli, Necmi; Haider, Ali

2017-09-01

In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

Method of passivating semiconductor surfaces

DOEpatents

Wanlass, M.W.

1990-06-19

A method is described for passivating Group III-V or II-VI semiconductor compound surfaces. The method includes selecting a passivating material having a lattice constant substantially mismatched to the lattice constant of the semiconductor compound. The passivating material is then grown as an ultrathin layer of passivating material on the surface of the Group III-V or II-VI semiconductor compound. The passivating material is grown to a thickness sufficient to maintain a coherent interface between the ultrathin passivating material and the semiconductor compound. In addition, a device formed from such method is also disclosed.

High resolution three-dimensional doping profiler

DOEpatents

Thundat, Thomas G.; Warmack, Robert J.

1999-01-01

A semiconductor doping profiler provides a Schottky contact at one surface and an ohmic contact at the other. While the two contacts are coupled to a power source, thereby establishing an electrical bias in the semiconductor, a localized light source illuminates the semiconductor to induce a photocurrent. The photocurrent changes in accordance with the doping characteristics of the semiconductor in the illuminated region. By changing the voltage of the power source the depth of the depletion layer can be varied to provide a three dimensional view of the local properties of the semiconductor.

Method of passivating semiconductor surfaces

DOEpatents

Wanlass, Mark W.

1990-01-01

A method of passivating Group III-V or II-VI semiconductor compound surfaces. The method includes selecting a passivating material having a lattice constant substantially mismatched to the lattice constant of the semiconductor compound. The passivating material is then grown as an ultrathin layer of passivating material on the surface of the Group III-V or II-VI semiconductor compound. The passivating material is grown to a thickness sufficient to maintain a coherent interface between the ultrathin passivating material and the semiconductor compound. In addition, a device formed from such method is also disclosed.

Two-step fabrication of single-layer rectangular SnSe flakes

NASA Astrophysics Data System (ADS)

Jiang, Jizhou; Wong, Calvin Pei Yu; Zou, Jing; Li, Shisheng; Wang, Qixing; Chen, Jianyi; Qi, Dianyu; Wang, Hongyu; Eda, Goki; Chua, Daniel H. C.; Shi, Yumeng; Zhang, Wenjing; Thye Shen Wee, Andrew

2017-06-01

Recent findings about ultrahigh thermoelectric performances in SnSe single crystals have stimulated research on this binary semiconductor material. Furthermore, single-layer SnSe is an interesting analogue of phosphorene, with potential applications in two-dimensional (2D) nanoelectronics. Although significant advances in the synthesis of SnSe nanocrystals have been made, fabrication of well-defined large-sized single-layer SnSe flakes in a facile way still remains a challenge. The growth of single-layer rectangular SnSe flakes with a thickness of ~6.8 Å and lateral dimensions of about 30 µm  ×  50 µm is demonstrated by a two-step synthesis method, where bulk rectangular SnSe flakes were synthesized first by a vapor transport deposition method followed by a nitrogen etching technique to fabricate single-layer rectangular SnSe flakes in an atmospheric pressure system. The as-obtained rectangular SnSe flakes exhibited a pure crystalline phase oriented along the a-axis direction. Field-effect transistor devices fabricated on individual single-layer rectangular SnSe flakes using gold electrodes exhibited p-doped ambipolar behavior and a hole mobility of about 0.16 cm2 V-1 s-1. This two-step fabrication method can be helpful for growing other similar 2D large-sized single-layer materials.

Electric field induced spin-polarized current

DOEpatents

Murakami, Shuichi; Nagaosa, Naoto; Zhang, Shoucheng

2006-05-02

A device and a method for generating an electric-field-induced spin current are disclosed. A highly spin-polarized electric current is generated using a semiconductor structure and an applied electric field across the semiconductor structure. The semiconductor structure can be a hole-doped semiconductor having finite or zero bandgap or an undoped semiconductor of zero bandgap. In one embodiment, a device for injecting spin-polarized current into a current output terminal includes a semiconductor structure including first and second electrodes, along a first axis, receiving an applied electric field and a third electrode, along a direction perpendicular to the first axis, providing the spin-polarized current. The semiconductor structure includes a semiconductor material whose spin orbit coupling energy is greater than room temperature (300 Kelvin) times the Boltzmann constant. In one embodiment, the semiconductor structure is a hole-doped semiconductor structure, such as a p-type GaAs semiconductor layer.

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Producing Silicon Carbide for Semiconductor Devices

NASA Technical Reports Server (NTRS)

Hsu, G. C.; Rohatgi, N. K.

1986-01-01

Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

Inelastic tunnel diodes

NASA Technical Reports Server (NTRS)

Anderson, L. M. (Inventor)

1984-01-01

Power is extracted from plasmons, photons, or other guided electromagnetic waves at infrared to midultraviolet frequencies by inelastic tunneling in metal-insulator-semiconductor-metal diodes. Inelastic tunneling produces power by absorbing plasmons to pump electrons to higher potential. Specifically, an electron from a semiconductor layer absorbs a plasmon and simultaneously tunnels across an insulator into metal layer which is at higher potential. The diode voltage determines the fraction of energy extracted from the plasmons; any excess is lost to heat.

Visible-wavelength semiconductor lasers and arrays

DOEpatents

Schneider, R.P. Jr.; Crawford, M.H.

1996-09-17

The visible semiconductor laser includes an InAlGaP active region surrounded by one or more AlGaAs layers on each side, with carbon as the sole p-type dopant. Embodiments of the invention are provided as vertical-cavity surface-emitting lasers (VCSELs) and as edge-emitting lasers (EELs). One or more transition layers comprised of a substantially indium-free semiconductor alloy such as AlAsP, AlGaAsP, or the like may be provided between the InAlGaP active region and the AlGaAS DBR mirrors or confinement layers to improve carrier injection and device efficiency by reducing any band offsets. Visible VCSEL devices fabricated according to the invention with a one-wavelength-thick (1{lambda}) optical cavity operate continuous-wave (cw) with lasing output powers up to 8 mW, and a peak power conversion efficiency of up to 11%. 5 figs.

Stabilized CdSe-CoPi composite photoanode for light-assisted water oxidation by transformation of a CdSe/cobalt metal thin film.

PubMed

Costi, Ronny; Young, Elizabeth R; Bulović, Vladimir; Nocera, Daniel G

2013-04-10

Integration of water splitting catalysts with visible-light-absorbing semiconductors would enable direct solar-energy-to-fuel conversion schemes such as those based on water splitting. A disadvantage of some common semiconductors that possess desirable optical bandgaps is their chemical instability under the conditions needed for oxygen evolution reaction (OER). In this study, we demonstrate the dual benefits gained from using a cobalt metal thin-film as the precursor for the preparation of cobalt-phosphate (CoPi) OER catalyst on cadmium chalcogenide photoanodes. The cobalt layer protects the underlying semiconductor from oxidation and degradation while forming the catalyst and simultaneously facilitates the advantageous incorporation of the cadmium chalcogenide layer into the CoPi layer during continued processing of the electrode. The resulting hybrid material forms a stable photoactive anode for light-assisted water splitting.

Power module packaging with double sided planar interconnection and heat exchangers

DOEpatents

Liang, Zhenxian; Marlino, Laura D.; Ning, Puqi; Wang, Fei

2015-05-26

A double sided cooled power module package having a single phase leg topology includes two IGBT and two diode semiconductor dies. Each IGBT die is spaced apart from a diode semiconductor die, forming a switch unit. Two switch units are placed in a planar face-up and face-down configuration. A pair of DBC or other insulated metallic substrates is affixed to each side of the planar phase leg semiconductor dies to form a sandwich structure. Attachment layers are disposed on outer surfaces of the substrates and two heat exchangers are affixed to the substrates by rigid bond layers. The heat exchangers, made of copper or aluminum, have passages for carrying coolant. The power package is manufactured in a two-step assembly and heating process where direct bonds are formed for all bond layers by soldering, sintering, solid diffusion bonding or transient liquid diffusion bonding, with a specially designed jig and fixture.

Complexes of dipolar excitons in layered quasi-two-dimensional nanostructures

NASA Astrophysics Data System (ADS)

Bondarev, Igor V.; Vladimirova, Maria R.

2018-04-01

We discuss neutral and charged complexes (biexcitons and trions) formed by indirect excitons in layered quasi-two-dimensional semiconductor heterostructures. Indirect excitons—long-lived neutral Coulomb-bound pairs of electrons and holes of different layers—have been known for semiconductor coupled quantum wells and have recently been reported for van der Waals heterostructures such as double bilayer graphene and transition-metal dichalcogenides. Using the configuration space approach, we derive the analytical expressions for the trion and biexciton binding energies as a function of interlayer distance. The method captures essential kinematics of complex formation to reveal significant binding energies, up to a few tens of meV for typical interlayer distances ˜3 -5 Å , with the trion binding energy always being greater than that of the biexciton. Our results can contribute to the understanding of more complex many-body phenomena such as exciton Bose-Einstein condensation and Wigner-like electron-hole crystallization in layered semiconductor heterostructures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Zhemin; Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552; Taguchi, Dai

The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial chargingmore » in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.« less

Semiconductor light-emitting devices having concave microstructures providing improved light extraction efficiency and method for producing same

DOEpatents

Tansu, Nelson; Gilchrist, James F; Ee, Yik-Khoon; Kumnorkaew, Pisist

2013-11-19

A conventional semiconductor LED is modified to include a microlens layer over its light-emitting surface. The LED may have an active layer including at least one quantum well layer of InGaN and GaN. The microlens layer includes a plurality of concave microstructures that cause light rays emanating from the LED to diffuse outwardly, leading to an increase in the light extraction efficiency of the LED. The concave microstructures may be arranged in a substantially uniform array, such as a close-packed hexagonal array. The microlens layer is preferably constructed of curable material, such as polydimethylsiloxane (PDMS), and is formed by soft-lithography imprinting by contacting fluid material of the microlens layer with a template bearing a monolayer of homogeneous microsphere crystals, to cause concave impressions, and then curing the material to fix the concave microstructures in the microlens layer and provide relatively uniform surface roughness.

Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

NASA Astrophysics Data System (ADS)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

2017-09-01

SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

Strain-compensated infrared photodetector and photodetector array

DOEpatents

Kim, Jin K; Hawkins, Samuel D; Klem, John F; Cich, Michael J

2013-05-28

A photodetector is disclosed for the detection of infrared light with a long cutoff wavelength in the range of about 4.5-10 microns. The photodetector, which can be formed on a semiconductor substrate as an nBn device, has a light absorbing region which includes InAsSb light-absorbing layers and tensile-strained layers interspersed between the InAsSb light-absorbing layers. The tensile-strained layers can be formed from GaAs, InAs, InGaAs or a combination of these III-V compound semiconductor materials. A barrier layer in the photodetector can be formed from AlAsSb or AlGaAsSb; and a contact layer in the photodetector can be formed from InAs, GaSb or InAsSb. The photodetector is useful as an individual device, or to form a focal plane array.

Subnanosecond Scintillation Detector

NASA Technical Reports Server (NTRS)

Hoenk, Michael (Inventor); Hennessy, John (Inventor); Hitlin, David (Inventor)

2017-01-01

A scintillation detector, including a scintillator that emits scintillation; a semiconductor photodetector having a surface area for receiving the scintillation, wherein the surface area has a passivation layer configured to provide a peak quantum efficiency greater than 40% for a first component of the scintillation, and the semiconductor photodetector has built in gain through avalanche multiplication; a coating on the surface area, wherein the coating acts as a bandpass filter that transmits light within a range of wavelengths corresponding to the first component of the scintillation and suppresses transmission of light with wavelengths outside said range of wavelengths; and wherein the surface area, the passivation layer, and the coating are controlled to increase the temporal resolution of the semiconductor photodetector.

Laser ablation mechanism of transparent layers on semiconductors with ultrashort laser pulses

NASA Astrophysics Data System (ADS)

Rublack, Tino; Hartnauer, Stefan; Mergner, Michael; Muchow, Markus; Seifert, Gerhard

2011-12-01

Transparent dielectric layers on semiconductors are used as anti-reflection coatings both for photovoltaic applications and for mid-infrared optical elements. We have shown recently that selective ablation of such layers is possible using ultrashort laser pulses at wavelengths being absorbed by the semiconductor. To get a deeper understanding of the ablation mechanism, we have done ablation experiments for different transparent materials, in particular SiO2 and SixNy on silicon, using a broad range of wavelengths ranging from UV to IR, and pulse durations between 50 and 2000 fs. The characterization of the ablated regions was done by light microscopy and atomic force microscopy (AFM). Utilizing laser wavelengths above the silicon band gap, selective ablation of the dielectric layer without noticeable damage of the opened silicon surface is possible. In contrast, ultrashort pulses (1-2 ps) at mid-infrared wavelengths already cause damage in the silicon at lower intensities than in the dielectric layer, even when a vibrational resonance (e.g. at λ = 9.26 μm for SiO2) is addressed. The physical processes behind this, on the first glance counterintuitive, observation will be discussed.

Optoelectronics of supported and suspended 2D semiconductors

NASA Astrophysics Data System (ADS)

Bolotin, Kirill

2014-03-01

Two-dimensional semiconductors, materials such monolayer molybdenum disulfide (MoS2) are characterized by strong spin-orbit and electron-electron interactions. However, both electronic and optoelectronic properties of these materials are dominated by disorder-related scattering. In this talk, we investigate approaches to reduce scattering and explore physical phenomena arising in intrinsic 2D semiconductors. First, we discuss fabrication of pristine suspended monolayer MoS2 and use photocurrent spectroscopy measurements to study excitons in this material. We observe band-edge and van Hove singularity excitons and estimate their binding energies. Furthermore, we study dissociation of these excitons and uncover the mechanism of their contribution to photoresponse of MoS2. Second, we study strain-induced modification of bandstructures of 2D semiconductors. With increasing strain, we find large and controllable band gap reduction of both single- and bi-layer MoS2. We also detect experimental signatures consistent with strain-induced transition from direct to indirect band gap in monolayer MoS2. Finally, we fabricate heterostructures of dissimilar 2D semiconductors and study their photoresponse. For closely spaced 2D semiconductors we detect charge transfer, while for separation larger than 10nm we observe Forster-like energy transfer between excitations in different layers.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Veselov, D. A., E-mail: dmitriy90@list.ru; Shashkin, I. S.; Bakhvalov, K. V.

Semiconductor lasers based on MOCVD-grown AlGaInAs/InP separate-confinement heterostructures are studied. It is shown that raising only the energy-gap width of AlGaInAs-waveguides without the introduction of additional barriers results in more pronounced current leakage into the cladding layers. It is found that the introduction of additional barrier layers at the waveguide–cladding-layer interface blocks current leakage into the cladding layers, but results in an increase in the internal optical loss with increasing pump current. It is experimentally demonstrated that the introduction of blocking layers makes it possible to obtain maximum values of the internal quantum efficiency of stimulated emission (92%) and continuouswavemore » output optical power (3.2 W) in semiconductor lasers in the eye-safe wavelength range (1400–1600 nm).« less

Photo-Spectrometer Realized In A Standard Cmos Ic Process

DOEpatents

Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

1999-10-12

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Chitin Liquid-Crystal-Templated Oxide Semiconductor Aerogels.

PubMed

Chau, Trang The Lieu; Le, Dung Quang Tien; Le, Hoa Thi; Nguyen, Cuong Duc; Nguyen, Long Viet; Nguyen, Thanh-Dinh

2017-09-13

Chitin nanocrystals have been used as a liquid crystalline template to fabricate layered oxide semiconductor aerogels. Anisotropic chitin liquid crystals are transformed to sponge-like aerogels by hydrothermally cross-linked gelation and lyophilization-induced solidification. The hydrothermal gelation of chitin aqueous suspensions then proceeds with peroxotitanate to form hydrogel composites that recover to form aerogels after freeze-drying. The homogeneous peroxotitanate/chitin composites are calcined to generate freestanding titania aerogels that exhibit the nanostructural integrity of layered chitin template. Our extended investigations show that coassembling chitin nanocrystals with other metal-based precursors also yielded semiconductor aerogels of perovskite BaTiO 3 and CuO x nanocrystals. The potential of these materials is great to investigate these chitin sponges for biomedicine and these semiconductor aerogels for photocatalysis, gas sensing, and other applications. Our results present a new aerogel templating method of highly porous, ultralight materials with chitin liquid crystals.

Exchanging Ohmic Losses in Metamaterial Absorbers with Useful Optical Absorption for Photovoltaics

PubMed Central

Vora, Ankit; Gwamuri, Jephias; Pala, Nezih; Kulkarni, Anand; Pearce, Joshua M.; Güney, Durdu Ö.

2014-01-01

Using metamaterial absorbers, we have shown that metallic layers in the absorbers do not necessarily constitute undesired resistive heating problem for photovoltaics. Tailoring the geometric skin depth of metals and employing the natural bulk absorbance characteristics of the semiconductors in those absorbers can enable the exchange of undesired resistive losses with the useful optical absorbance in the active semiconductors. Thus, Ohmic loss dominated metamaterial absorbers can be converted into photovoltaic near-perfect absorbers with the advantage of harvesting the full potential of light management offered by the metamaterial absorbers. Based on experimental permittivity data for indium gallium nitride, we have shown that between 75%–95% absorbance can be achieved in the semiconductor layers of the converted metamaterial absorbers. Besides other metamaterial and plasmonic devices, our results may also apply to photodectors and other metal or semiconductor based optical devices where resistive losses and power consumption are important pertaining to the device performance. PMID:24811322

Organic permeable-base transistors - superb power efficiency at highest frequencies (Conference Presentation)

NASA Astrophysics Data System (ADS)

Klinger, Markus P.; Fischer, Axel; Kaschura, Felix; Scholz, Reinhard; Lüssem, Björn; Kheradmand-Boroujeni, Bahman; Ellinger, Frank; Kasemann, Daniel; Leo, Karl

2016-11-01

Organic field-effect transistors (OFET) are important elements in thin-film electronics, being considered for flat-panel or flexible displays, radio frequency identification systems, and sensor arrays. To optimize the devices for high-frequency operation, the channel length, defined as the horizontal distance between the source and the drain contact, can be scaled down. Here, an architecture with a vertical current flow, in particular the Organic Permeable-Base Transistors (OPBT), opens up new opportunities, because the effective transit length in vertical direction is precisely tunable in the nanometer range by the thickness of the semiconductor layer. We present an advanced OPBT, competing with best OFETs while a low-cost, OLED-like fabrication with low-resolution shadow masks is used (Klinger et al., Adv. Mater. 27, 2015). Its design consists of a stack of three parallel electrodes separated by two semiconductor layers of C60 . The vertical current flow is controlled by the middle base electrode with nano-sized openings passivated by an native oxide. Using insulated layers to structure the active area, devices show an on/off ratio of 10⁶ , drive 11 A/cm² at an operation voltage of 1 V, and have a low subthreshold slope of 102 mV/decade. These OPBTs show a unity current-gain transit frequency of 2.2 MHz and off-state break-down fields above 1 MV/cm. Thus, our optimized setup does not only set a benchmark for vertical organic transistors, but also outperforms best lateral OFETs using similar low-cost structuring techniques in terms of power efficiency at high frequencies.

Two-dimensional transition metal dichalcogenides as atomically thin semiconductors: opportunities and challenges.

PubMed

Duan, Xidong; Wang, Chen; Pan, Anlian; Yu, Ruqin; Duan, Xiangfeng

2015-12-21

The discovery of graphene has ignited intensive interest in two-dimensional layered materials (2DLMs). These 2DLMs represent a new class of nearly ideal 2D material systems for exploring fundamental chemistry and physics at the limit of single-atom thickness, and have the potential to open up totally new technological opportunities beyond the reach of existing materials. In general, there are a wide range of 2DLMs in which the atomic layers are weakly bonded together by van der Waals interactions and can be isolated into single or few-layer nanosheets. The van der Waals interactions between neighboring atomic layers could allow much more flexible integration of distinct materials to nearly arbitrarily combine and control different properties at the atomic scale. The transition metal dichalcogenides (TMDs) (e.g., MoS2, WSe2) represent a large family of layered materials, many of which exhibit tunable band gaps that can undergo a transition from an indirect band gap in bulk crystals to a direct band gap in monolayer nanosheets. These 2D-TMDs have thus emerged as an exciting class of atomically thin semiconductors for a new generation of electronic and optoelectronic devices. Recent studies have shown exciting potential of these atomically thin semiconductors, including the demonstration of atomically thin transistors, a new design of vertical transistors, as well as new types of optoelectronic devices such as tunable photovoltaic devices and light emitting devices. In parallel, there have also been considerable efforts in developing diverse synthetic approaches for the rational growth of various forms of 2D materials with precisely controlled chemical composition, physical dimension, and heterostructure interface. Here we review the recent efforts, progress, opportunities and challenges in exploring the layered TMDs as a new class of atomically thin semiconductors.

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

Twisted bilayer blue phosphorene: A direct band gap semiconductor

NASA Astrophysics Data System (ADS)

Ospina, D. A.; Duque, C. A.; Correa, J. D.; Suárez Morell, Eric

2016-09-01

We report that two rotated layers of blue phosphorene behave as a direct band gap semiconductor. The optical spectrum shows absorption peaks in the visible region of the spectrum and in addition the energy of these peaks can be tuned with the rotational angle. These findings makes twisted bilayer blue phosphorene a strong candidate as a solar cell or photodetection device. Our results are based on ab initio calculations of several rotated blue phosphorene layers.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, Arthur W.; Ellingboe, Albert R.

1998-01-01

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18-0.35 mm or less.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, A.W.; Ellingboe, A.R.

1998-10-20

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18--0.35 mm or less. 16 figs.

High performance thin film transistor with ZnO channel layer deposited by DC magnetron sputtering.

PubMed

Moon, Yeon-Keon; Moon, Dae-Yong; Lee, Sang-Ho; Jeong, Chang-Oh; Park, Jong-Wan

2008-09-01

Research in large area electronics, especially for low-temperature plastic substrates, focuses commonly on limitations of the semiconductor in thin film transistors (TFTs), in particular its low mobility. ZnO is an emerging example of a semiconductor material for TFTs that can have high mobility, while a-Si and organic semiconductors have low mobility (<1 cm2/Vs). ZnO-based TFTs have achieved high mobility, along with low-voltage operation low off-state current, and low gate leakage current. In general, ZnO thin films for the channel layer of TFTs are deposited with RF magnetron sputtering methods. On the other hand, we studied ZnO thin films deposited with DC magnetron sputtering for the channel layer of TFTs. After analyzing the basic physical and chemical properties of ZnO thin films, we fabricated a TFT-unit cell using ZnO thin films for the channel layer. The field effect mobility (micro(sat)) of 1.8 cm2/Vs and threshold voltage (Vth) of -0.7 V were obtained.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

PubMed Central

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-01-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters. PMID:26842997

Modeling electrochemical deposition inside nanotubes to obtain metal-semiconductor multiscale nanocables or conical nanopores.

PubMed

Lebedev, Konstantin; Mafé, Salvador; Stroeve, Pieter

2005-08-04

Nanocables with a radial metal-semiconductor heterostructure have recently been prepared by electrochemical deposition inside metal nanotubes. First, a bare nanoporous polycarbonate track-etched membrane is coated uniformly with a metal film by electroless deposition. The film forms a working electrode for further deposition of a semiconductor layer that grows radially inside the nanopore when the deposition rate is slow. We propose a new physical model for the nanocable synthesis and study the effects of the deposited species concentration, potential-dependent reaction rate, and nanopore dimensions on the electrochemical deposition. The problem involves both axial diffusion through the nanopore and radial transport to the nanopore surface, with a surface reaction rate that depends on the axial position and the time. This is so because the radial potential drop across the deposited semiconductor layer changes with the layer thickness through the nanopore. Since axially uniform nanocables are needed for most applications, we consider the relative role of reaction and axial diffusion rates on the deposition process. However, in those cases where partial, empty-core deposition should be desirable (e.g., for producing conical nanopores to be used in single nanoparticle detection), we give conditions where asymmetric geometries can be experimentally realized.

Multi-layer MOS capacitor based polarization insensitive electro-optic intensity modulator.

PubMed

Qiu, Xiaoming; Ruan, Xiaoke; Li, Yanping; Zhang, Fan

2018-05-28

In this study, a multi-layer metal-oxide-semiconductor capacitor (MLMOSC) polarization insensitive modulator is proposed. The design is validated by numerical simulation with commercial software LUMERICAL SOLUTION. Based on the epsilon-near-zero (ENZ) effect of indium tin oxide (ITO), the device manages to uniformly modulate both the transverse electric (TE) and the transverse magnetic (TM) modes. With a 20μm-long double-layer metal-oxide-semiconductor capacitor (DLMOSC) polarization insensitive modulator, in which two metal-oxide-semiconductor (MOS) structures are formed by the n-doped Si/HfO 2 /ITO/HfO 2 / n-doped Si stack, the extinction ratios (ERs) of both the TE and the TM modes can be over 20dB. The polarization dependent losses of the device can be as low as 0.05dB for the "OFF" state and 0.004dB for the "ON" state. Within 1dB polarization dependent loss, the device can operate with over 20dB ERs at the S, C, and L bands. The polarization insensitive modulator offers various merits including ultra-compact size, broadband spectrum, and complementary metal oxide semiconductor (CMOS) compatibility.

Effect of temperature on terahertz photonic and omnidirectional band gaps in one-dimensional quasi-periodic photonic crystals composed of semiconductor InSb.

PubMed

Singh, Bipin K; Pandey, Praveen C

2016-07-20

Engineering of thermally tunable terahertz photonic and omnidirectional bandgaps has been demonstrated theoretically in one-dimensional quasi-periodic photonic crystals (PCs) containing semiconductor and dielectric materials. The considered quasi-periodic structures are taken in the form of Fibonacci, Thue-Morse, and double periodic sequences. We have shown that the photonic and omnidirectional bandgaps in the quasi-periodic structures with semiconductor constituents are strongly depend on the temperature, thickness of the constituted semiconductor and dielectric material layers, and generations of the quasi-periodic sequences. It has been found that the number of photonic bandgaps increases with layer thickness and generation of the quasi-periodic sequences. Omnidirectional bandgaps in the structures have also been obtained. Results show that the bandwidths of photonic and omnidirectional bandgaps are tunable by changing the temperature and lattice parameters of the structures. The generation of quasi-periodic sequences can also change the properties of photonic and omnidirectional bandgaps remarkably. The frequency range of the photonic and omnidirectional bandgaps can be tuned by the change of temperature and layer thickness of the considered quasi-periodic structures. This work will be useful to design tunable terahertz PC devices.

Method for manufacturing electrical contacts for a thin-film semiconductor device

DOEpatents

Carlson, David E.; Dickson, Charles R.; D'Aiello, Robert V.

1988-11-08

A method of fabricating spaced-apart back contacts on a thin film of semiconductor material by forming strips of buffer material on top of the semiconductor material in locations corresponding to the desired dividing lines between back contacts, forming a film of metal substantially covering the semiconductor material and buffer strips, and scribing portions of the metal film overlying the buffer strips with a laser without contacting the underlying semiconductor material to separate the metal layer into a plurality of back contacts. The buffer material serves to protect the underlying semiconductor material from being damaged during the laser scribing. Back contacts and multi-cell photovoltaic modules incorporating such back contacts also are disclosed.

Electrical contacts for a thin-film semiconductor device

DOEpatents

Carlson, David E.; Dickson, Charles R.; D'Aiello, Robert V.

1989-08-08

A method of fabricating spaced-apart back contacts on a thin film of semiconductor material by forming strips of buffer material on top of the semiconductor material in locations corresponding to the desired dividing lines between back contacts, forming a film of metal substantially covering the semiconductor material and buffer strips, and scribing portions of the metal film overlying the buffer strips with a laser without contacting the underlying semiconductor material to separate the metal layer into a plurality of back contacts. The buffer material serves to protect the underlying semiconductor material from being damaged during the laser scribing. Back contacts and multi-cell photovoltaic modules incorporating such back contacts also are disclosed.

Electro-optical SLS devices for operating at new wavelength ranges

DOEpatents

Osbourn, Gordon C.

1986-01-01

An intrinsic semiconductor electro-optical device includes a p-n junction intrinsically responsive, when cooled, to electromagnetic radiation in the wavelength range of 8-12 um. The junction consists of a strained-layer superlattice of alternating layers of two different III-V semiconductors having mismatched lattice constants when in bulk form. A first set of layers is either InAs.sub.1-x Sb.sub.x (where x is aobut 0.5 to 0.7) or In.sub.1-x Ga.sub.x As.sub.1-y Sb.sub.y (where x and y are chosen such that the bulk bandgap of the resulting layer is about the same as the minimum bandgap in the In.sub.1-x Ga.sub.x As.sub.1-y Sb.sub.y family). The second set of layers has a lattice constant larger than the lattice constant of the layers in the first set.

Charge-density study on layered oxyarsenides (LaO)MAs (M = Mn, Fe, Ni, Zn)

NASA Astrophysics Data System (ADS)

Takase, Kouichi; Hiramoto, Shozo; Fukushima, Tetsuya; Sato, Kazunori; Moriyoshi, Chikako; Kuroiwa, Yoshihiro

2017-12-01

Using synchrotron X-ray powder diffraction, we investigate the charge-density distributions of the layered oxypnictides (LaO)MnAs, (LaO)FeAs, (LaO)NiAs, and (LaO)ZnAs, which are an antiferromagnetic semiconductor, a parent material of an iron-based superconductor, a low-temperature superconductor, and a non-magnetic semiconductor, respectively. For the metallic samples, clear charge densities are observed in both the transition-metal pnictide layers and the rare-earth-oxide layers. However, in the semiconducting samples, there is no finite charge density between the transition-metal element and As. These differences in charge density reflect differences in physical properties. First-principles calculations using density functional theory reproduce the experimental results reasonably well.

Interlayer exciton optoelectronics in a 2D heterostructure p–n junction

DOE PAGES

Ross, Jason S.; Rivera, Pasqual; Schaibley, John; ...

2016-12-22

Semiconductor heterostructures are backbones for solid-state-based optoelectronic devices. Recent advances in assembly techniques for van der Waals heterostructures have enabled the band engineering of semiconductor heterojunctions for atomically thin optoelectronic devices. In two-dimensional heterostructures with type II band alignment, interlayer excitons, where Coulomb bound electrons and holes are confined to opposite layers, have shown promising properties for novel excitonic devices, including a large binding energy, micron-scale in-plane drift-diffusion, and a long population and valley polarization lifetime. Here, we demonstrate interlayer exciton optoelectronics based on electrostatically defined lateral p–n junctions in a MoSe 2–WSe 2 heterobilayer. Applying a forward bias enablesmore » the first observation of electroluminescence from interlayer excitons. At zero bias, the p–n junction functions as a highly sensitive photodetector, where the wavelength-dependent photocurrent measurement allows the direct observation of resonant optical excitation of the interlayer exciton. The resulting photocurrent amplitude from the interlayer exciton is about 200 times smaller than the resonant excitation of intralayer exciton. This implies that the interlayer exciton oscillator strength is 2 orders of magnitude smaller than that of the intralayer exciton due to the spatial separation of electron and hole to the opposite layers. Lastly, these results lay the foundation for exploiting the interlayer exciton in future 2D heterostructure optoelectronic devices.« less

Stable surface passivation process for compound semiconductors

DOEpatents

Ashby, Carol I. H.

2001-01-01

A passivation process for a previously sulfided, selenided or tellurated III-V compound semiconductor surface. The concentration of undesired mid-gap surface states on a compound semiconductor surface is reduced by the formation of a near-monolayer of metal-(sulfur and/or selenium and/or tellurium)-semiconductor that is effective for long term passivation of the underlying semiconductor surface. Starting with the III-V compound semiconductor surface, any oxidation present thereon is substantially removed and the surface is then treated with sulfur, selenium or tellurium to form a near-monolayer of chalcogen-semiconductor of the surface in an oxygen-free atmosphere. This chalcogenated surface is then contacted with a solution of a metal that will form a low solubility chalcogenide to form a near-monolayer of metal-chalcogen-semiconductor. The resulting passivating layer provides long term protection for the underlying surface at or above the level achieved by a freshly chalcogenated compound semiconductor surface in an oxygen free atmosphere.

Megavoltage imaging with a photoconductor based sensor

DOEpatents

Partain, Larry Dean [Los Altos, CA; Zentai, George [Mountain View, CA

2011-02-08

A photodetector for detecting megavoltage (MV) radiation comprises a semiconductor conversion layer having a first surface and a second surface disposed opposite the first surface, a first electrode coupled to the first surface, a second electrode coupled to the second surface, and a low density substrate including a detector array coupled to the second electrode opposite the semiconductor conversion layer. The photodetector includes a sufficient thickness of a high density material to create a sufficient number of photoelectrons from incident MV radiation, so that the photoelectrons can be received by the conversion layer and converted to a sufficient of recharge carriers for detection by the detector array.

Semiconductor materials for high frequency solid state sources

NASA Astrophysics Data System (ADS)

Grubin, H. L.

1983-03-01

The broad goal of the subject contract is to suggest candidate materials for high frequency device operation. During the initial phase of the study, attention has been focused on defining the general role of the band structure and associated scattering processes in determining the response of semiconductors to transient high-speed electrical signals. Moments of the Boltzmann transport equation form the basis of the study, and the scattering rates define the semiconductor under study. The selection of semiconductor materials proceeds from a set of simple, yet significant, set of scaling principles. During the first quarter scaling was associated with what can formally be identified as velocity invariants, but which in more practical terms identifies the relative speed advantages of e.g., InP over GaAs.

Photon extraction from nitride ultraviolet light-emitting devices

DOEpatents

Schowalter, Leo J; Chen, Jianfeng; Grandusky, James R

2015-02-24

In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.

Single-layer group IV-V and group V-IV-III-VI semiconductors: Structural stability, electronic structures, optical properties, and photocatalysis

NASA Astrophysics Data System (ADS)

Lin, Jia-He; Zhang, Hong; Cheng, Xin-Lu; Miyamoto, Yoshiyuki

2017-07-01

Recently, single-layer group III monochalcogenides have attracted both theoretical and experimental interest at their potential applications in photonic devices, electronic devices, and solar energy conversion. Excited by this, we theoretically design two kinds of highly stable single-layer group IV-V (IV =Si ,Ge , and Sn; V =N and P) and group V-IV-III-VI (IV =Si ,Ge , and Sn; V =N and P; III =Al ,Ga , and In; VI =O and S) compounds with the same structures with single-layer group III monochalcogenides via first-principles simulations. By using accurate hybrid functional and quasiparticle methods, we show the single-layer group IV-V and group V-IV-III-VI are indirect bandgap semiconductors with their bandgaps and band edge positions conforming to the criteria of photocatalysts for water splitting. By applying a biaxial strain on single-layer group IV-V, single-layer group IV nitrides show a potential on mechanical sensors due to their bandgaps showing an almost linear response for strain. Furthermore, our calculations show that both single-layer group IV-V and group V-IV-III-VI have absorption from the visible light region to far-ultraviolet region, especially for single-layer SiN-AlO and SnN-InO, which have strong absorption in the visible light region, resulting in excellent potential for solar energy conversion and visible light photocatalytic water splitting. Our research provides valuable insight for finding more potential functional two-dimensional semiconductors applied in optoelectronics, solar energy conversion, and photocatalytic water splitting.

Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-12-09

Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.

Outline and comparison of the possible effects present in a metal-thin-film-insulator-semiconductor solar cell

NASA Technical Reports Server (NTRS)

Fonash, S. J.

1976-01-01

The advantages possible with the insertion of a thin-film insulating or semi-insulating layer between a metal and a semiconductor to form the MIS photovoltaic device have been presented previously in the literature. This MIS configuration may be considered as a specific example of a more general class of photovoltaic devices: electrode-thin-film-insulator-semiconductor devices. Since the advantages of the configuration were pointed out, there has been considerable experimental interest in these photovoltaic devices. Because the previous analysis showed that the introduction of the insulator layer could produce several different but advantageous effects, this paper presents a further outline giving a comparison of these effects together with their ramifications.

Intermediate type excitons in Schottky barriers of A3B6 layer semiconductors and UV photodetectors

NASA Astrophysics Data System (ADS)

Alekperov, O. Z.; Guseinov, N. M.; Nadjafov, A. I.

2006-09-01

Photoelectric and photovoltaic spectra of Schottky barrier (SB) structures of InSe, GaSe and GaS layered semiconductors (LS) are investigated at quantum energies from the band edge excitons of corresponding materials up to 6.5eV. Spectral dependences of photoconductivity (PC) of photo resistors and barrier structures are strongly different at the quantum energies corresponding to the intermediate type excitons (ITE) observed in these semiconductors. It was suggested that high UV photoconductivity of A3B6 LS is due to existence of high mobility light carriers in the depth of the band structure. It is shown that SB of semitransparent Au-InSe is high sensitive photo detector in UV region of spectra.

MOVPE Growth of LWIR AlInAs/GaInAs/InP Quantum Cascade Lasers: Impact of Growth and Material Quality on Laser Performance

DTIC Science & Technology

2017-02-01

MOVPE Growth of LWIR AlInAs/GaInAs/InP Quantum Cascade Lasers: Impact of Growth and Material Quality on Laser Performance (Invited paper) Christine A...epitaxial layers in quantum cascade lasers (QCLs) has a primary impact on QCL operation, and establishing correlations between epitaxial growth and materials...QCLs emitting in this range. Index terms – Quantum cascade lasers, semiconductor growth, semiconductor epitaxial layers, infrared emitters. I

Process for selectively patterning epitaxial film growth on a semiconductor substrate

DOEpatents

Sheldon, P.; Hayes, R.E.

1984-12-04

Disclosed is a process for selectively patterning epitaxial film growth on a semiconductor substrate. The process includes forming a masking member on the surface of the substrate, the masking member having at least two layers including a first layer disposed on the substrate and the second layer covering the first layer. A window is then opened in a selected portion of the second layer by removing that portion to expose the first layer thereunder. The first layer is then subjected to an etchant introduced through the window to dissolve the first layer a sufficient amount to expose the substrate surface directly beneath the window, the first layer being adapted to preferentially dissolve at a substantially greater rate than the second layer so as to create an overhanging ledge portion with the second layer by undercutting the edges thereof adjacent the window. The epitaxial film is then deposited on the exposed substrate surface directly beneath the window. Finally, an etchant is introduced through the window to dissolve the remainder of the first layer so as to lift-off the second layer and materials deposited thereon to fully expose the balance of the substrate surface.

Process for selectively patterning epitaxial film growth on a semiconductor substrate

DOEpatents

Sheldon, Peter; Hayes, Russell E.

1986-01-01

A process is disclosed for selectively patterning epitaxial film growth on a semiconductor substrate. The process includes forming a masking member on the surface of the substrate, the masking member having at least two layers including a first layer disposed on the substrate and the second layer covering the first layer. A window is then opened in a selected portion of the second layer by removing that portion to expose the first layer thereunder. The first layer is then subjected to an etchant introduced through the window to dissolve a sufficient amount of the first layer to expose the substrate surface directly beneath the window, the first layer being adapted to preferentially dissolve at a substantially greater rate than the second layer so as to create an overhanging ledge portion with the second layer by undercutting the edges thereof adjacent to the window. The epitaxial film is then deposited on the exposed substrate surface directly beneath the window. Finally, an etchant is introduced through the window to dissolve the remainder of the first layer so as to lift-off the second layer and materials deposited thereon to fully expose the balance of the substrate surface.

Coffee-Ring Defined Short Channels for Inkjet-Printed Metal Oxide Thin-Film Transistors.

PubMed

Li, Yuzhi; Lan, Linfeng; Xiao, Peng; Sun, Sheng; Lin, Zhenguo; Song, Wei; Song, Erlong; Gao, Peixiong; Wu, Weijing; Peng, Junbiao

2016-08-03

Short-channel electronic devices several micrometers in length are difficult to implement by direct inkjet printing due to the limitation of position accuracy of the common inkjet printer system and the spread of functional ink on substrates. In this report, metal oxide thin-film transistors (TFTs) with channel lengths of 3.5 ± 0.7 μm were successfully fabricated with a common inkjet printer without any photolithography steps. Hydrophobic CYTOP coffee stripes, made by inkjet-printing and plasma-treating processes, were utilized to define the channel area of TFTs with channel lengths as short as ∼3.5 μm by dewetting the inks of the source/drain (S/D) precursors. Furthermore, by introduction of an ultrathin layer of PVA to modify the S/D surfaces, the spreading of precursor ink of the InOx semiconductor layer was well-controlled. The inkjet-printed short-channel TFTs exhibited a maximum mobility of 4.9 cm(2) V(-1) s(-1) and an on/off ratio of larger than 10(9). This approach of fabricating short-channel TFTs by inkjet printing will promote the large-area fabrication of short-channel TFTs in a cost-effective manner.

Effect of Water Vapor and Surface Morphology on the Low Temperature Response of Metal Oxide Semiconductor Gas Sensors

PubMed Central

Maier, Konrad; Helwig, Andreas; Müller, Gerhard; Hille, Pascal; Eickhoff, Martin

2015-01-01

In this work the low temperature response of metal oxide semiconductor gas sensors is analyzed. Important characteristics of this low-temperature response are a pronounced selectivity to acid- and base-forming gases and a large disparity of response and recovery time constants which often leads to an integrator-type of gas response. We show that this kind of sensor performance is related to the trend of semiconductor gas sensors to adsorb water vapor in multi-layer form and that this ability is sensitively influenced by the surface morphology. In particular we show that surface roughness in the nanometer range enhances desorption of water from multi-layer adsorbates, enabling them to respond more swiftly to changes in the ambient humidity. Further experiments reveal that reactive gases, such as NO2 and NH3, which are easily absorbed in the water adsorbate layers, are more easily exchanged across the liquid/air interface when the humidity in the ambient air is high. PMID:28793583

Regulation of depletion layer width in Pb(Zr,Ti)O3/Nb:SrTiO3 heterostructures

NASA Astrophysics Data System (ADS)

Bai, Yu; Jie Wang, Zhan; Cui, Jian Zhong; Zhang, Zhi Dong

2018-05-01

Improving the tunability of depletion layer width (DLW) in ferroelectric/semiconductor heterostructures is important for the performance of some devices. In this work, 200-nm-thick Pb(Zr0.4Ti0.6)O3 (PZT) films were deposited on different Nb-doped SrTiO3 (NSTO) substrates, and the tunability of DLW at PZT/NSTO interfaces were studied. Our results showed that the maximum tunability of the DLW was achieved at the NSTO substrate with 0.5 wt% Nb. On the basis of the modified capacitance model and the ferroelectric semiconductor theory, we suggest that the tunability of the DLW in PZT/NSTO heterostructures can be attributed to a delicate balance of the depletion layer charge and the ferroelectric polarization charge. Therefore, the performance of some devices related to the tunability of DLW in ferroelectric/semiconductor heterostructures can be improved by modulating the doping concentration in semiconducting electrode materials.

The effects of Bi4Ti3O12 interfacial ferroelectric layer on the dielectric properties of Au/n-Si structures

NASA Astrophysics Data System (ADS)

Gökçen, Muharrem; Yıldırım, Mert

2015-06-01

Au/n-Si metal-semiconductor (MS) and Au/Bi4Ti3O12/n-Si metal-ferroelectric-semiconductor (MFS) structures were fabricated and admittance measurements were held between 5 kHz and 1 MHz at room temperature so that dielectric properties of these structures could be investigated. The ferroelectric interfacial layer Bi4Ti3O12 decreased the polarization voltage by providing permanent dipoles at metal/semiconductor interface. Depending on different mechanisms, dispersion behavior was observed in dielectric constant, dielectric loss and loss tangent versus bias voltage plots of both MS and MFS structures. The real and imaginary parts of complex modulus of MFS structure take smaller values than those of MS structure, because permanent dipoles in ferroelectric layer cause a large spontaneous polarization mechanism. While the dispersion in AC conductivity versus frequency plots of MS structure was observed at high frequencies, for MFS structure it was observed at lower frequencies.

Formation of Ideal Rashba States on Layered Semiconductor Surfaces Steered by Strain Engineering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ming, Wenmei; Wang, Z. F.; Zhou, Miao

2015-12-10

Spin splitting of Rashba states in two-dimensional electron system provides a mechanism of spin manipulation for spintronics applications. However, Rashba states realized experimentally to date are often outnumbered by spin-degenerated substrate states at the same energy range, hindering their practical applications. Here, by density functional theory calculation, we show that Au one monolayer film deposition on a layered semiconductor surface β-InSe(0001) can possess “ideal” Rashba states with large spin splitting, which are completely situated inside the large band gap of the substrate. The position of the Rashba bands can be tuned over a wide range with respect to the substratemore » band edges by experimentally accessible strain. Furthermore, our nonequilibrium Green’s function transport calculation shows that this system may give rise to the long-sought strong current modulation when made into a device of Datta-Das transistor. Similar systems may be identified with other metal ultrathin films and layered semiconductor substrates to realize ideal Rashba states.« less

Development and characterization of semiconductor ion detectors for plasma diagnostics in the range over 0.3 keV

NASA Astrophysics Data System (ADS)

Cho, T.; Sakamoto, Y.; Hirata, M.; Kohagura, J.; Makino, K.; Kanke, S.; Takahashi, K.; Okamura, T.; Nakashima, Y.; Yatsu, K.; Tamano, T.; Miyoshi, S.

1997-01-01

For the purpose of plasma-ion-energy analyses in a wide-energy range from a few hundred eV to hundreds of keV, upgraded semiconductor detectors are newly fabricated and characterized using a test-ion-beam line from 0.3 to 12 keV. In particular, the detectable lowest-ion energy is drastically improved at least down to 0.3 keV; this energy is one to two orders-of-magnitude better than those for commercially available Si-surface-barrier diodes employed for previous plasma-ion diagnostics. A signal-to-noise ratio of two to three orders-of-magnitude better than that for usual metal-collector detectors is demonstrated for the compact-sized semiconductor along with the availability of the use under conditions of a good vacuum and a strong-magnetic field. Such characteristics are achieved due to the improving methods of the optimization of the thicknesses of a Si dead layer and a SiO2 layer, as well as the nitrogen-doping technique near the depletion layer along with minimizing impurity concentrations in Si. Such an upgraded capability of an extremely low-energy-ion detection with the low-noise characteristics enlarges research regimes of plasma-ion behavior using semiconductor detectors not only in the divertor regions of tokamaks but in wider spectra of open-field plasma devices including tandem mirrors. An application of the semiconductor ion detector for plasma-ion diagnostics is demonstrated in a specially designed ion-spectrometer structure.

Predicting synergy in atomic layer etching

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanarik, Keren J.; Tan, Samantha; Yang, Wenbing

2017-03-27

Atomic layer etching (ALE) is a multistep process used today in manufacturing for removing ultrathin layers of material. In this article, the authors report on ALE of Si, Ge, C, W, GaN, and SiO 2 using a directional (anisotropic) plasma-enhanced approach. The authors analyze these systems by defining an “ALE synergy” parameter which quantifies the degree to which a process approaches the ideal ALE regime. This parameter is inspired by the ion-neutral synergy concept introduced in the 1979 paper by Coburn and Winters. ALE synergy is related to the energetics of underlying surface interactions and is understood in terms ofmore » energy criteria for the energy barriers involved in the reactions. Synergistic behavior is observed for all of the systems studied, with each exhibiting behavior unique to the reactant–material combination. By systematically studying atomic layer etching of a group of materials, the authors show that ALE synergy scales with the surface binding energy of the bulk material. This insight explains why some materials are more or less amenable to the directional ALE approach. Furthermore, they conclude that ALE is both simpler to understand than conventional plasma etch processing and is applicable to metals, semiconductors, and dielectrics.« less

CoFe2O4-TiO2 and CoFe2O4-ZnO thin film nanostructures elaborated from colloidal chemistry and atomic layer deposition.

PubMed

Clavel, Guylhaine; Marichy, Catherine; Willinger, Marc-Georg; Ravaine, Serge; Zitoun, David; Pinna, Nicola

2010-12-07

CoFe(2)O(4)-TiO(2) and CoFe(2)O(4)-ZnO nanoparticles/film composites were prepared from directed assembly of colloidal CoFe(2)O(4) in a Langmuir-Blodgett monolayer and atomic layer deposition (ALD) of an oxide (TiO(2) or ZnO). The combination of these two methods permits the use of well-defined nanoparticles from colloidal chemistry, their assembly on a large scale, and the control over the interface between a ferrimagnetic material (CoFe(2)O(4)) and a semiconductor (TiO(2) or ZnO). Using this approach, architectures can be assembled with a precise control from the Angstrom scale (ALD) to the micrometer scale (Langmuir-Blodgett film). The resulting heterostructures present well-calibrated thicknesses. Electron microscopy and magnetic measurement studies give evidence that the size of the nanoparticles and their intrinsic magnetic properties are not altered by the various steps involved in the synthesis process. Therefore, the approach is suitable to obtain a layered composite with a quasi-monodisperse layer of ferrimagnetic nanoparticles embedded in an ultrathin film of semiconducting material.

Investigation of defect modes in a defective photonic crystal with a semiconductor metamaterial defect

NASA Astrophysics Data System (ADS)

Wu, Meng-Ru; Wu, Chien-Jang; Chang, Shoou-Jinn

2014-11-01

In this work, we theoretically investigate the properties of defect modes in a defective photonic crystal containing a semiconductor metamaterial defect. We consider the structure, (LH)N/DP/(LH)N, where N and P are respectively the stack numbers, L is SiO2, H is InP, and defect layer D is a semiconductor metamaterial composed of Al-doped ZnO (AZO) and ZnO. It is found that, within the photonic band gap, the number of defect modes (transmission peaks) will decrease as the defect thickness increases, in sharp contrast to the case of using usual dielectric defect. The peak height and position can be changed by the variation in the thickness of defect layer. In the angle-dependent defect mode, its position is shown to be blue-shifted as the angle of incidence increases for both TE and TM waves. The analysis of defect mode provides useful information for the design of tunable transmission filter in semiconductor optoelectronics.

Surface hole gas enabled transparent deep ultraviolet light-emitting diode

NASA Astrophysics Data System (ADS)

Zhang, Jianping; Gao, Ying; Zhou, Ling; Gil, Young-Un; Kim, Kyoung-Min

2018-07-01

The inherent deep-level nature of acceptors in wide-band-gap semiconductors makes p-ohmic contact formation and hole supply difficult, impeding progress for short-wavelength optoelectronics and high-power high-temperature bipolar electronics. We provide a general solution by demonstrating an ultrathin rather than a bulk wide-band-gap semiconductor to be a successful hole supplier and ohmic contact layer. Free holes in this ultrathin semiconductor are assisted to activate from deep acceptors and swept to surface to form hole gases by a large electric field, which can be provided by engineered spontaneous and piezoelectric polarizations. Experimentally, a 6 nm thick AlN layer with surface hole gas had formed p-ohmic contact to metals and provided sufficient hole injection to a 280 nm light-emitting diode, demonstrating a record electrical-optical conversion efficiency exceeding 8.5% at 20 mA (55 A cm‑2). Our approach of forming p-type wide-band-gap semiconductor ohmic contact is critical to realizing high-efficiency ultraviolet optoelectronic devices.

Chemical-mechanical polishing of recessed microelectromechanical devices

DOEpatents

Barron, Carole C.; Hetherington, Dale L.; Montague, Stephen

1999-01-01

A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g. CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate.

Micro-fabricated integrated coil and magnetic circuit and method of manufacturing thereof

DOEpatents

Mihailovich, Robert E.; Papavasiliou, Alex P.; Mehrotra, Vivek; Stupar, Philip A.; Borwick, III, Robert L.; Ganguli, Rahul; DeNatale, Jeffrey F.

2017-03-28

A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material.

Chemical-mechanical polishing of recessed microelectromechanical devices

DOEpatents

Barron, C.C.; Hetherington, D.L.; Montague, S.

1999-07-06

A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g., CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate. 23 figs.

Charge transfer at organic-inorganic interfaces—Indoline layers on semiconductor substrates

NASA Astrophysics Data System (ADS)

Meyenburg, I.; Falgenhauer, J.; Rosemann, N. W.; Chatterjee, S.; Schlettwein, D.; Heimbrodt, W.

2016-12-01

We studied the electron transfer from excitons in adsorbed indoline dye layers across the organic-inorganic interface. The hybrids consist of indoline derivatives on the one hand and different inorganic substrates (TiO2, ZnO, SiO2(0001), fused silica) on the other. We reveal the electron transfer times from excitons in dye layers to the organic-inorganic interface by analyzing the photoluminescence transients of the dye layers after femtosecond excitation and applying kinetic model calculations. A correlation between the transfer times and four parameters have been found: (i) the number of anchoring groups, (ii) the distance between the dye and the organic-inorganic interface, which was varied by the alkyl-chain lengths between the carboxylate anchoring group and the dye, (iii) the thickness of the adsorbed dye layer, and (iv) the level alignment between the excited dye ( π* -level) and the conduction band minimum of the inorganic semiconductor.

Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

PubMed

Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2018-05-08

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

Superheating Suppresses Structural Disorder in Layered BiI3 Semiconductors Grown by the Bridgman Method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johns, Paul M.; Sulekar, Soumitra; Yeo, Shinyoung

2016-01-01

The susceptibility of layered structures to stacking faults is a problem in some of the more attractive semiconductor materials for ambient-temperature radiation detectors. In the work presented here, Bridgman-grown BiI3 layered single crystals are investigated to understand and eliminate this structural disorder, which reduces radiation detector performance. The use of superheating gradients has been shown to improve crystal quality in non-layered semiconductor crystals; thus the technique was here explored to improve the growth of BiI3. When investigating the homogeneity of non-superheated crystals, highly geometric void defects were found to populate the bulk of the crystals. Applying a superheating gradient tomore » the melt prior to crystal growth improved structural quality and decreased defect density from the order of 4600 voids per cm3 to 300 voids per cm3. Corresponding moderate improvements to electronic properties also resulted from the superheat gradient method of crystal growth. Comparative measurements through infrared microscopy, etch-pit density, x-ray rocking curves, and sheet resistivity readings show that superheat gradients in BiI3 growth led to higher quality crystals.« less

Intracavity double diode structures with GaInP barrier layers for thermophotonic cooling

NASA Astrophysics Data System (ADS)

Tiira, Jonna; Radevici, Ivan; Haggren, Tuomas; Hakkarainen, Teemu; Kivisaari, Pyry; Lyytikäinen, Jari; Aho, Arto; Tukiainen, Antti; Guina, Mircea; Oksanen, Jani

2017-02-01

Optical cooling of semiconductors has recently been demonstrated both for optically pumped CdS nanobelts and for electrically injected GaInAsSb LEDs at very low powers. To enable cooling at larger power and to understand and overcome the main obstacles in optical cooling of conventional semiconductor structures, we study thermophotonic (TPX) heat transport in cavity coupled light emitters. Our structures consist of a double heterojunction (DHJ) LED with a GaAs active layer and a corresponding DHJ or a p-n-homojunction photodiode, enclosed within a single semiconductor cavity to eliminate the light extraction challenges. Our presently studied double diode structures (DDS) use GaInP barriers around the GaAs active layer instead of the AlGaAs barriers used in our previous structures. We characterize our updated double diode structures by four point probe IV- measurements and measure how the material modifications affect the recombination parameters and coupling quantum efficiencies in the structures. The coupling quantum efficiency of the new devices with InGaP barrier layers is found to be approximately 10 % larger than for the structures with AlGaAs barriers at the point of maximum efficiency.

Optical bandgap of single- and multi-layered amorphous germanium ultra-thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Pei; Zaslavsky, Alexander; Longo, Paolo

2016-01-07

Accurate optical methods are required to determine the energy bandgap of amorphous semiconductors and elucidate the role of quantum confinement in nanometer-scale, ultra-thin absorbing layers. Here, we provide a critical comparison between well-established methods that are generally employed to determine the optical bandgap of thin-film amorphous semiconductors, starting from normal-incidence reflectance and transmittance measurements. First, we demonstrate that a more accurate estimate of the optical bandgap can be achieved by using a multiple-reflection interference model. We show that this model generates more reliable results compared to the widely accepted single-pass absorption method. Second, we compare two most representative methods (Taucmore » and Cody plots) that are extensively used to determine the optical bandgap of thin-film amorphous semiconductors starting from the extracted absorption coefficient. Analysis of the experimental absorption data acquired for ultra-thin amorphous germanium (a-Ge) layers demonstrates that the Cody model is able to provide a less ambiguous energy bandgap value. Finally, we apply our proposed method to experimentally determine the optical bandgap of a-Ge/SiO{sub 2} superlattices with single and multiple a-Ge layers down to 2 nm thickness.« less

Atomic-order thermal nitridation of group IV semiconductors for ultra-large-scale integration

NASA Astrophysics Data System (ADS)

Murota, Junichi; Le Thanh, Vinh

2015-03-01

One of the main requirements for ultra-large-scale integration (ULSI) is atomic-order control of process technology. Our concept of atomically controlled processing for group IV semiconductors is based on atomic-order surface reaction control in Si-based CVD epitaxial growth. On the atomic-order surface nitridation of a few nm-thick Ge/about 4 nm-thick Si0.5Ge0.5/Si(100) by NH3, it is found that N atoms diffuse through nm-order thick Ge layer into Si0.5Ge0.5/Si(100) substrate and form Si nitride, even at 500 °C. By subsequent H2 heat treatment, although N atomic amount in Ge layer is reduced drastically, the reduction of the Si nitride is slight. It is suggested that N diffusion in Ge layer is suppressed by the formation of Si nitride and that Ge/atomic-order N layer/Si1-xGex/Si (100) heterostructure is formed. These results demonstrate the capability of CVD technology for atomically controlled nitridation of group IV semiconductors for ultra-large-scale integration. Invited talk at the 7th International Workshop on Advanced Materials Science and Nanotechnology IWAMSN2014, 2-6 November, 2014, Ha Long, Vietnam.

Removal of GaAs growth substrates from II-VI semiconductor heterostructures

NASA Astrophysics Data System (ADS)

Bieker, S.; Hartmann, P. R.; Kießling, T.; Rüth, M.; Schumacher, C.; Gould, C.; Ossau, W.; Molenkamp, L. W.

2014-04-01

We report on a process that enables the removal of II-VI semiconductor epilayers from their GaAs growth substrate and their subsequent transfer to arbitrary host environments. The technique combines mechanical lapping and layer selective chemical wet etching and is generally applicable to any II-VI layer stack. We demonstrate the non-invasiveness of the method by transferring an all-II-VI magnetic resonant tunneling diode. High resolution x-ray diffraction proves that the crystal integrity of the heterostructure is preserved. Transport characterization confirms that the functionality of the device is maintained and even improved, which is ascribed to completely elastic strain relaxation of the tunnel barrier layer.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

Metal-insulator-semiconductor heterostructures for plasmonic hot-carrier optoelectronics.

PubMed

García de Arquer, F Pelayo; Konstantatos, Gerasimos

2015-06-01

Plasmonic hot-electron devices are attractive candidates for light-energy harvesting and photodetection applications. For solid state devices, the most compact and straightforward architecture is the metal-semiconductor Schottky junction. However convenient, this structure introduces limitations such as the elevated dark current associated to thermionic emission, or constraints for device design due to the finite choice of materials. In this work we theoretically consider the metal-insulator-semiconductor heterojunction as a candidate for plasmonic hot-carrier photodetection and solar cells. The presence of the insulating layer can significantly reduce the dark current, resulting in increased device performance with predicted solar power conversion efficiencies up to 9%. For photodetection, the sensitivity can be extended well into the infrared by a judicious choice of the insulating layer, with up to 300-fold expected enhancement in detectivity.

Ultrathin metal-semiconductor-metal resonator for angle invariant visible band transmission filters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Kyu-Tae; Seo, Sungyong; Yong Lee, Jae

We present transmission visible wavelength filters based on strong interference behaviors in an ultrathin semiconductor material between two metal layers. The proposed devices were fabricated on 2 cm × 2 cm glass substrate, and the transmission characteristics show good agreement with the design. Due to a significantly reduced light propagation phase change associated with the ultrathin semiconductor layer and the compensation in phase shift of light reflecting from the metal surface, the filters show an angle insensitive performance up to ±70°, thus, addressing one of the key challenges facing the previously reported photonic and plasmonic color filters. This principle, described in this paper, canmore » have potential for diverse applications ranging from color display devices to the image sensors.« less

Coaxial metal-oxide-semiconductor (MOS) Au/Ga2O3/GaN nanowires.

PubMed

Hsieh, Chin-Hua; Chang, Mu-Tung; Chien, Yu-Jen; Chou, Li-Jen; Chen, Lih-Juann; Chen, Chii-Dong

2008-10-01

Coaxial metal-oxide-semiconductor (MOS) Au-Ga2O3-GaN heterostructure nanowires were successfully fabricated by an in situ two-step process. The Au-Ga2O3 core-shell nanowires were first synthesized by the reaction of Ga powder, a mediated Au thin layer, and a SiO2 substrate at 800 degrees C. Subsequently, these core-shell nanowires were nitridized in ambient ammonia to form a GaN coating layer at 600 degrees C. The GaN shell is a single crystal, an atomic flat interface between the oxide and semiconductor that ensures that the high quality of the MOS device is achieved. These novel 1D nitride-based MOS nanowires may have promise as building blocks to the future nitride-based vertical nanodevices.

Layer-by-layer modification of thin-film metal-semiconductor multilayers with ultrashort laser pulses

NASA Astrophysics Data System (ADS)

Romashevskiy, S. A.; Tsygankov, P. A.; Ashitkov, S. I.; Agranat, M. B.

2018-05-01

The surface modifications in a multilayer thin-film structure (50-nm alternating layers of Si and Al) induced by a single Gaussian-shaped femtosecond laser pulse (350 fs, 1028 nm) in the air are investigated by means of atomic-force microscopy (AFM), scanning electron microscopy (SEM), and optical microscopy (OM). Depending on the laser fluence, various modifications of nanometer-scale metal and semiconductor layers, including localized formation of silicon/aluminum nanofoams and layer-by-layer removal, are found. While the nanofoams with cell sizes in the range of tens to hundreds of nanometers are produced only in the two top layers, layer-by-layer removal is observed for the four top layers under single pulse irradiation. The 50-nm films of the multilayer structure are found to be separated at their interfaces, resulting in a selective removal of several top layers (up to 4) in the form of step-like (concentric) craters. The observed phenomenon is associated with a thermo-mechanical ablation mechanism that results in splitting off at film-film interface, where the adhesion force is less than the bulk strength of the used materials, revealing linear dependence of threshold fluences on the film thickness.

Circular electrode geometry metal-semiconductor-metal photodetectors

NASA Technical Reports Server (NTRS)

Mcaddo, James A. (Inventor); Towe, Elias (Inventor); Bishop, William L. (Inventor); Wang, Liang-Guo (Inventor)

1994-01-01

The invention comprises a high speed, metal-semiconductor-metal photodetector which comprises a pair of generally circular, electrically conductive electrodes formed on an optically active semiconductor layer. Various embodiments of the invention include a spiral, intercoiled electrode geometry and an electrode geometry comprised of substantially circular, concentric electrodes which are interposed. These electrode geometries result in photodetectors with lower capacitances, dark currents and lower inductance which reduces the ringing seen in the optical pulse response.

Low-Resistivity Zinc Selenide for Heterojunctions

NASA Technical Reports Server (NTRS)

Stirn, R. J.

1986-01-01

Magnetron reactive sputtering enables doping of this semiconductor. Proposed method of reactive sputtering combined with doping shows potential for yielding low-resistivity zinc selenide films. Zinc selenide attractive material for forming heterojunctions with other semiconductor compounds as zinc phosphide, cadmium telluride, and gallium arsenide. Semiconductor junctions promising for future optoelectronic devices, including solar cells and electroluminescent displays. Resistivities of zinc selenide layers deposited by evaporation or chemical vapor deposition too high to form practical heterojunctions.

Inversion layer MOS solar cells

NASA Technical Reports Server (NTRS)

Ho, Fat Duen

1986-01-01

Inversion layer (IL) Metal Oxide Semiconductor (MOS) solar cells were fabricated. The fabrication technique and problems are discussed. A plan for modeling IL cells is presented. Future work in this area is addressed.

Assembly, Structure, and Functionality of Metal-Organic Networks and Organic Semiconductor Layers at Surfaces

NASA Astrophysics Data System (ADS)

Tempas, Christopher D.

Self-assembled nanostructures at surfaces show promise for the development of next generation technologies including organic electronic devices and heterogeneous catalysis. In many cases, the functionality of these nanostructures is not well understood. This thesis presents strategies for the structural design of new on-surface metal-organic networks and probes their chemical reactivity. It is shown that creating uniform metal sites greatly increases selectivity when compared to ligand-free metal islands. When O2 reacts with single-site vanadium centers, in redox-active self-assembled coordination networks on the Au(100) surface, it forms one product. When O2 reacts with vanadium metal islands on the same surface, multiple products are formed. Other metal-organic networks described in this thesis include a mixed valence network containing Pt0 and PtII and a network where two Fe centers reside in close proximity. This structure is stable to temperatures >450 °C. These new on-surface assemblies may offer the ability to perform reactions of increasing complexity as future heterogeneous catalysts. The functionalization of organic semiconductor molecules is also shown. When a few molecular layers are grown on the surface, it is seen that the addition of functional groups changes both the film's structure and charge transport properties. This is due to changes in both first layer packing structure and the pi-electron distribution in the functionalized molecules compared to the original molecule. The systems described in this thesis were studied using high-resolution scanning tunneling microscopy, non-contact atomic force microscopy, and X-ray photoelectron spectroscopy. Overall, this work provides strategies for the creation of new, well-defined on-surface nanostructures and adds additional chemical insight into their properties.

Gate-Defined Quantum Confinement in InSe-based van der Waals Heterostructures.

PubMed

Hamer, Matthew J; Tóvári, Endre; Zhu, Mengjian; Thompson, Michael Dermot; Mayorov, Alexander S; Prance, Jonathan; Lee, Yongjin; Haley, Richard; Kudrynskyi, Zakhar R; Patanè, Amalia; Terry, Daniel; Kovalyuk, Zakhar D; Ensslin, Klaus; Kretinin, Andrey V; Geim, Andre K; Gorbachev, Roman Vladislavovich

2018-05-15

Indium selenide, a post-transition metal chalcogenide, is a novel two-dimensional (2D) semiconductor with interesting electronic properties. Its tunable band gap and high electron mobility have already attracted considerable research interest. Here we demonstrate strong quantum confinement and manipulation of single electrons in devices made from few-layer crystals of InSe using electrostatic gating. We report on gate-controlled quantum dots in the Coulomb blockade regime as well as one-dimensional quantization in point contacts, revealing multiple plateaus. The work represents an important milestone in the development of quality devices based on 2D materials and makes InSe a prime candidate for relevant electronic and optoelectronic applications.

Photon induced non-linear quantized double layer charging in quaternary semiconducting quantum dots.

PubMed

Nair, Vishnu; Ananthoju, Balakrishna; Mohapatra, Jeotikanta; Aslam, M

2018-03-15

Room temperature quantized double layer charging was observed in 2 nm Cu 2 ZnSnS 4 (CZTS) quantum dots. In addition to this we observed a distinct non-linearity in the quantized double layer charging arising from UV light modulation of double layer. UV light irradiation resulted in a 26% increase in the integral capacitance at the semiconductor-dielectric (CZTS-oleylamine) interface of the quantum dot without any change in its core size suggesting that the cause be photocapacitive. The increasing charge separation at the semiconductor-dielectric interface due to highly stable and mobile photogenerated carriers cause larger electrostatic forces between the quantum dot and electrolyte leading to an enhanced double layer. This idea was supported by a decrease in the differential capacitance possible due to an enhanced double layer. Furthermore the UV illumination enhanced double layer gives us an AC excitation dependent differential double layer capacitance which confirms that the charging process is non-linear. This ultimately illustrates the utility of a colloidal quantum dot-electrolyte interface as a non-linear photocapacitor. Copyright © 2017 Elsevier Inc. All rights reserved.

Determination of layer-dependent exciton binding energies in few-layer black phosphorus

PubMed Central

Zhang, Guowei; Chaves, Andrey; Huang, Shenyang; Wang, Fanjie; Xing, Qiaoxia; Low, Tony; Yan, Hugen

2018-01-01

The attraction between electrons and holes in semiconductors forms excitons, which largely determine the optical properties of the hosting material, and hence the device performance, especially for low-dimensional systems. Mono- and few-layer black phosphorus (BP) are emerging two-dimensional (2D) semiconductors. Despite its fundamental importance and technological interest, experimental investigation of exciton physics has been rather limited. We report the first systematic measurement of exciton binding energies in ultrahigh-quality few-layer BP by infrared absorption spectroscopy, with layer (L) thickness ranging from 2 to 6 layers. Our experiments allow us to determine the exciton binding energy, decreasing from 213 meV (2L) to 106 meV (6L). The scaling behavior with layer numbers can be well described by an analytical model, which takes into account the nonlocal screening effect. Extrapolation to free-standing monolayer yields a large binding energy of ~800 meV. Our study provides insights into 2D excitons and their crossover from 2D to 3D, and demonstrates that few-layer BP is a promising high-quality optoelectronic material for potential infrared applications. PMID:29556530

Semiconductor-based optical refrigerator

DOEpatents

Epstein, Richard I.; Edwards, Bradley C.; Sheik-Bahae, Mansoor

2002-01-01

Optical refrigerators using semiconductor material as a cooling medium, with layers of material in close proximity to the cooling medium that carries away heat from the cooling material and preventing radiation trapping. In addition to the use of semiconducting material, the invention can be used with ytterbium-doped glass optical refrigerators.

Silicon metal-semiconductor-metal photodetector

DOEpatents

Brueck, Steven R. J.; Myers, David R.; Sharma, Ashwani K.

1997-01-01

Silicon MSM photodiodes sensitive to radiation in the visible to near infrared spectral range are produced by altering the absorption characteristics of crystalline Si by ion implantation. The implantation produces a defected region below the surface of the silicon with the highest concentration of defects at its base which acts to reduce the contribution of charge carriers formed below the defected layer. The charge carriers generated by the radiation in the upper regions of the defected layer are very quickly collected between biased Schottky barrier electrodes which form a metal-semiconductor-metal structure for the photodiode.

Silicon metal-semiconductor-metal photodetector

DOEpatents

Brueck, Steven R. J.; Myers, David R.; Sharma, Ashwani K.

1995-01-01

Silicon MSM photodiodes sensitive to radiation in the visible to near infrared spectral range are produced by altering the absorption characteristics of crystalline Si by ion implantation. The implantation produces a defected region below the surface of the silicon with the highest concentration of defects at its base which acts to reduce the contribution of charge carriers formed below the defected layer. The charge carriers generated by the radiation in the upper regions of the defected layer are very quickly collected between biased Schottky barrier electrodes which form a metal-semiconductor-metal structure for the photodiode.

GaAs photoconductive semiconductor switch

DOEpatents

Loubriel, Guillermo M.; Baca, Albert G.; Zutavern, Fred J.

1998-01-01

A high gain, optically triggered, photoconductive semiconductor switch (PCSS) implemented in GaAs as a reverse-biased pin structure with a passivation layer above the intrinsic GaAs substrate in the gap between the two electrodes of the device. The reverse-biased configuration in combination with the addition of the passivation layer greatly reduces surface current leakage that has been a problem for prior PCSS devices and enables employment of the much less expensive and more reliable DC charging systems instead of the pulsed charging systems that needed to be used with prior PCSS devices.

Multi-junction solar cell device

DOEpatents

Friedman, Daniel J.; Geisz, John F.

2007-12-18

A multi-junction solar cell device (10) is provided. The multi-junction solar cell device (10) comprises either two or three active solar cells connected in series in a monolithic structure. The multi-junction device (10) comprises a bottom active cell (20) having a single-crystal silicon substrate base and an emitter layer (23). The multi-junction device (10) further comprises one or two subsequent active cells each having a base layer (32) and an emitter layer (23) with interconnecting tunnel junctions between each active cell. At least one layer that forms each of the top and middle active cells is composed of a single-crystal III-V semiconductor alloy that is substantially lattice-matched to the silicon substrate (22). The polarity of the active p-n junction cells is either p-on-n or n-on-p. The present invention further includes a method for substantially lattice matching single-crystal III-V semiconductor layers with the silicon substrate (22) by including boron and/or nitrogen in the chemical structure of these layers.

Computational discovery of ferromagnetic semiconducting single-layer CrSnTe 3

DOE PAGES

Zhuang, Houlong L.; Xie, Yu; Kent, P. R. C.; ...

2015-07-06

Despite many single-layer materials being reported in the past decade, few of them exhibit magnetism. Here we perform first-principles calculations using accurate hybrid density functional methods (HSE06) to predict that single-layer CrSnTe 3 (CST) is a ferromagnetic semiconductor, with band gaps of 0.9 and 1.2 eV for the majority and minority spin channels, respectively. We determine the Curie temperature as 170 K, significantly higher than that of single-layer CrSiTe 3 (90K) and CrGeTe 3 (130 K). This is due to the enhanced ionicity of the Sn-Te bond, which in turn increases the superexchange coupling between the magnetic Cr atoms. Wemore » further explore the mechanical and dynamical stability and strain response of this single-layer material for possible epitaxial growth. Lastly, our study provides an intuitive approach to understand and design novel single-layer magnetic semiconductors for a wide range of spintronics and energy applications.« less

Single-Layer Halide Perovskite Light-Emitting Diodes with Sub-Band Gap Turn-On Voltage and High Brightness.

PubMed

Li, Junqiang; Shan, Xin; Bade, Sri Ganesh R; Geske, Thomas; Jiang, Qinglong; Yang, Xin; Yu, Zhibin

2016-10-03

Charge-carrier injection into an emissive semiconductor thin film can result in electroluminescence and is generally achieved by using a multilayer device structure, which requires an electron-injection layer (EIL) between the cathode and the emissive layer and a hole-injection layer (HIL) between the anode and the emissive layer. The recent advancement of halide perovskite semiconductors opens up a new path to electroluminescent devices with a greatly simplified device structure. We report cesium lead tribromide light-emitting diodes (LEDs) without the aid of an EIL or HIL. These so-called single-layer LEDs have exhibited a sub-band gap turn-on voltage. The devices obtained a brightness of 591 197 cd m -2 at 4.8 V, with an external quantum efficiency of 5.7% and a power efficiency of 14.1 lm W -1 . Such an advancement demonstrates that very high efficiency of electron and hole injection can be obtained in perovskite LEDs even without using an EIL or HIL.

Near-Unity Absorption in van der Waals Semiconductors for Ultrathin Optoelectronics.

PubMed

Jariwala, Deep; Davoyan, Artur R; Tagliabue, Giulia; Sherrott, Michelle C; Wong, Joeson; Atwater, Harry A

2016-09-14

We demonstrate near-unity, broadband absorbing optoelectronic devices using sub-15 nm thick transition metal dichalcogenides (TMDCs) of molybdenum and tungsten as van der Waals semiconductor active layers. Specifically, we report that near-unity light absorption is possible in extremely thin (<15 nm) van der Waals semiconductor structures by coupling to strongly damped optical modes of semiconductor/metal heterostructures. We further fabricate Schottky junction devices using these highly absorbing heterostructures and characterize their optoelectronic performance. Our work addresses one of the key criteria to enable TMDCs as potential candidates to achieve high optoelectronic efficiency.

Fabricating porous silicon carbide

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

The formation of porous SiC occurs under electrochemical anodization. A sample of SiC is contacted electrically with nickel and placed into an electrochemical cell which cell includes a counter electrode and a reference electrode. The sample is encapsulated so that only a bare semiconductor surface is exposed. The electrochemical cell is filled with an HF electrolyte which dissolves the SiC electrochemically. A potential is applied to the semiconductor and UV light illuminates the surface of the semiconductor. By controlling the light intensity, the potential and the doping level, a porous layer is formed in the semiconductor and thus one produces porous SiC.

Inkjet-Printed Organic Transistors Based on Organic Semiconductor/Insulating Polymer Blends.

PubMed

Kwon, Yoon-Jung; Park, Yeong Don; Lee, Wi Hyoung

2016-08-02

Recent advances in inkjet-printed organic field-effect transistors (OFETs) based on organic semiconductor/insulating polymer blends are reviewed in this article. Organic semiconductor/insulating polymer blends are attractive ink candidates for enhancing the jetting properties, inducing uniform film morphologies, and/or controlling crystallization behaviors of organic semiconductors. Representative studies using soluble acene/insulating polymer blends as an inkjet-printed active layer in OFETs are introduced with special attention paid to the phase separation characteristics of such blended films. In addition, inkjet-printed semiconducting/insulating polymer blends for fabricating high performance printed OFETs are reviewed.

Inkjet-Printed Organic Transistors Based on Organic Semiconductor/Insulating Polymer Blends

PubMed Central

Kwon, Yoon-Jung; Park, Yeong Don; Lee, Wi Hyoung

2016-01-01

Recent advances in inkjet-printed organic field-effect transistors (OFETs) based on organic semiconductor/insulating polymer blends are reviewed in this article. Organic semiconductor/insulating polymer blends are attractive ink candidates for enhancing the jetting properties, inducing uniform film morphologies, and/or controlling crystallization behaviors of organic semiconductors. Representative studies using soluble acene/insulating polymer blends as an inkjet-printed active layer in OFETs are introduced with special attention paid to the phase separation characteristics of such blended films. In addition, inkjet-printed semiconducting/insulating polymer blends for fabricating high performance printed OFETs are reviewed. PMID:28773772

On a chaotic potential at the surface of a compensated semiconductor under conditions of the self-assembly of electrically active defects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bondarenko, V. B., E-mail: enter@spbstu.ru; Filimonov, A. V.

2015-09-15

Natural irregularities of the electric potential on the surface of a semiconductor under conditions of the partial self-assembly of electrically active defects, i.e., on the formation of donor–acceptor pairs in depletion layers, are studied. The amplitude and character of the spatial distribution of the chaotic potential on the surface of a semiconductor in the cases of localized and delocalized states are determined. The dependence of the amplitude of the chaotic potential on the degree of compensation of the semiconductor is obtained.

P-doped organic semiconductor: Potential replacement for PEDOT:PSS in organic photodetectors

NASA Astrophysics Data System (ADS)

Herrbach, J.; Revaux, A.; Vuillaume, D.; Kahn, A.

2016-08-01

In this work, we present an alternative to the use of PEDOT:PSS as hole transport and electron blocking layers in organic photodetectors processed by solution. As Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS) is known to be sensitive to humidity, oxygen, and UV, removing this layer is essential for lifetime improvements. As a first step to achieving this goal, we need to find an alternative layer that fulfills the same role in order to obtain a working diode with similar or better performance. As a replacement, a layer of poly[(4,8-bis-(2-ethylhexyloxy)-benzo(1,2-b:4,5-b')dithiophene)-2,6-diyl-alt-(4-(2-ethylhexanoyl)-thieno[3,4-b]thiophene-)-2-6-diyl)] (PBDTTT-c) p-doped with the dopant tris-[1-(trifluoroethanoyl)-2-(trifluoromethyl)ethane-1,2-dithiolene] (Mo(tfd-COCF3)3) is used. This p-doped layer effectively lowers the hole injection barrier, and the low electron affinity of the polymer prevents the injection of electrons into the active layer. We show similar device performance under light and the improvements of detection performance with the doped layer in comparison with PEDOT:PSS, leading to a detectivity of 1.9 × 1013 cm (Hz)1/2 (W)-1, competitive with silicon diodes used in imaging applications. Moreover, contrary to PEDOT:PSS, no localization of the p-doped layer is needed, leading to a diode active area defined by the patterned electrodes.

Observation of High-Harmonic Generation from an Atomically Thin Semiconductor [Observation of High Harmonics from and Atomically Thin Semiconductor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Hanzhe; Li, Yilei; You, Yongsing

We report the observation of nonperturbative high-harmonic generation from monolayer MoS 2. Here, the yield is higher in monolayer compared to a single layer of the bulk, an effect attributed to strong electron-hole interactions in the monolayer.

Observation of High-Harmonic Generation from an Atomically Thin Semiconductor [Observation of High Harmonics from and Atomically Thin Semiconductor

DOE PAGES

Liu, Hanzhe; Li, Yilei; You, Yongsing; ...

2016-01-01

We report the observation of nonperturbative high-harmonic generation from monolayer MoS 2. Here, the yield is higher in monolayer compared to a single layer of the bulk, an effect attributed to strong electron-hole interactions in the monolayer.

Investigation of semiconductor clad optical waveguides

NASA Technical Reports Server (NTRS)

Batchman, T. E.; Carson, R. F.

1985-01-01

A variety of techniques have been proposed for fabricating integrated optical devices using semiconductors, lithium niobate, and glasses as waveguides and substrates. The use of glass waveguides and their interaction with thin semiconductor cladding layers was studied. Though the interactions of these multilayer waveguide structures have been analyzed here using glass, they may be applicable to other types of materials as well. The primary reason for using glass is that it provides a simple, inexpensive way to construct waveguides and devices.

Measuring the lateral charge-carrier mobility in metal-insulator-semiconductor capacitors via Kelvin-probe.

PubMed

Milotti, Valeria; Pietsch, Manuel; Strunk, Karl-Philipp; Melzer, Christian

2018-01-01

We report a Kelvin-probe method to investigate the lateral charge-transport properties of semiconductors, most notably the charge-carrier mobility. The method is based on successive charging and discharging of a pre-biased metal-insulator-semiconductor stack by an alternating voltage applied to one edge of a laterally confined semiconductor layer. The charge carriers spreading along the insulator-semiconductor interface are directly measured by a Kelvin-probe, following the time evolution of the surface potential. A model is presented, describing the device response for arbitrary applied biases allowing the extraction of the lateral charge-carrier mobility from experimentally measured surface potentials. The method is tested using the organic semiconductor poly(3-hexylthiophene), and the extracted mobilities are validated through current voltage measurements on respective field-effect transistors. Our widely applicable approach enables robust measurements of the lateral charge-carrier mobility in semiconductors with weak impact from the utilized contact materials.

Measuring the lateral charge-carrier mobility in metal-insulator-semiconductor capacitors via Kelvin-probe

NASA Astrophysics Data System (ADS)

Milotti, Valeria; Pietsch, Manuel; Strunk, Karl-Philipp; Melzer, Christian

2018-01-01

We report a Kelvin-probe method to investigate the lateral charge-transport properties of semiconductors, most notably the charge-carrier mobility. The method is based on successive charging and discharging of a pre-biased metal-insulator-semiconductor stack by an alternating voltage applied to one edge of a laterally confined semiconductor layer. The charge carriers spreading along the insulator-semiconductor interface are directly measured by a Kelvin-probe, following the time evolution of the surface potential. A model is presented, describing the device response for arbitrary applied biases allowing the extraction of the lateral charge-carrier mobility from experimentally measured surface potentials. The method is tested using the organic semiconductor poly(3-hexylthiophene), and the extracted mobilities are validated through current voltage measurements on respective field-effect transistors. Our widely applicable approach enables robust measurements of the lateral charge-carrier mobility in semiconductors with weak impact from the utilized contact materials.

Centro-Apical Self-Organization of Organic Semiconductors in a Line-Printed Organic Semiconductor: Polymer Blend for One-Step Printing Fabrication of Organic Field-Effect Transistors

PubMed Central

Jin Lee, Su; Kim, Yong-Jae; Young Yeo, So; Lee, Eunji; Sun Lim, Ho; Kim, Min; Song, Yong-Won; Cho, Jinhan; Ah Lim, Jung

2015-01-01

Here we report the first demonstration for centro-apical self-organization of organic semiconductors in a line-printed organic semiconductor: polymer blend. Key feature of this work is that organic semiconductor molecules were vertically segregated on top of the polymer phase and simultaneously crystallized at the center of the printed line pattern after solvent evaporation without an additive process. The thickness and width of the centro-apically segregated organic semiconductor crystalline stripe in the printed blend pattern were controlled by varying the relative content of the organic semiconductors, printing speed, and solution concentrations. The centro-apical self-organization of organic semiconductor molecules in a printed polymer blend may be attributed to the combination of an energetically favorable vertical phase-separation and hydrodynamic fluids inside the droplet during solvent evaporation. Finally, a centro-apically phase-separated bilayer structure of organic semiconductor: polymer blend was successfully demonstrated as a facile method to form the semiconductor and dielectric layer for OFETs in one- step. PMID:26359068

Centro-Apical Self-Organization of Organic Semiconductors in a Line-Printed Organic Semiconductor: Polymer Blend for One-Step Printing Fabrication of Organic Field-Effect Transistors.

PubMed

Lee, Su Jin; Kim, Yong-Jae; Yeo, So Young; Lee, Eunji; Lim, Ho Sun; Kim, Min; Song, Yong-Won; Cho, Jinhan; Lim, Jung Ah

2015-09-11

Here we report the first demonstration for centro-apical self-organization of organic semiconductors in a line-printed organic semiconductor: polymer blend. Key feature of this work is that organic semiconductor molecules were vertically segregated on top of the polymer phase and simultaneously crystallized at the center of the printed line pattern after solvent evaporation without an additive process. The thickness and width of the centro-apically segregated organic semiconductor crystalline stripe in the printed blend pattern were controlled by varying the relative content of the organic semiconductors, printing speed, and solution concentrations. The centro-apical self-organization of organic semiconductor molecules in a printed polymer blend may be attributed to the combination of an energetically favorable vertical phase-separation and hydrodynamic fluids inside the droplet during solvent evaporation. Finally, a centro-apically phase-separated bilayer structure of organic semiconductor: polymer blend was successfully demonstrated as a facile method to form the semiconductor and dielectric layer for OFETs in one- step.

Lead Halide Perovskites as Charge Generation Layers for Electron Mobility Measurement in Organic Semiconductors.

PubMed

Love, John A; Feuerstein, Markus; Wolff, Christian M; Facchetti, Antonio; Neher, Dieter

2017-12-06

Hybrid lead halide perovskites are introduced as charge generation layers (CGLs) for the accurate determination of electron mobilities in thin organic semiconductors. Such hybrid perovskites have become a widely studied photovoltaic material in their own right, for their high efficiencies, ease of processing from solution, strong absorption, and efficient photogeneration of charge. Time-of-flight (ToF) measurements on bilayer samples consisting of the perovskite CGL and an organic semiconductor layer of different thickness are shown to be determined by the carrier motion through the organic material, consistent with the much higher charge carrier mobility in the perovskite. Together with the efficient photon-to-electron conversion in the perovskite, this high mobility imbalance enables electron-only mobility measurement on relatively thin application-relevant organic films, which would not be possible with traditional ToF measurements. This architecture enables electron-selective mobility measurements in single components as well as bulk-heterojunction films as demonstrated in the prototypical polymer/fullerene blends. To further demonstrate the potential of this approach, electron mobilities were measured as a function of electric field and temperature in an only 127 nm thick layer of a prototypical electron-transporting perylene diimide-based polymer, and found to be consistent with an exponential trap distribution of ca. 60 meV. Our study furthermore highlights the importance of high mobility charge transporting layers when designing perovskite solar cells.

Color-selective photodetection from intermediate colloidal quantum dots buried in amorphous-oxide semiconductors.

PubMed

Cho, Kyung-Sang; Heo, Keun; Baik, Chan-Wook; Choi, Jun Young; Jeong, Heejeong; Hwang, Sungwoo; Lee, Sang Yeol

2017-10-10

We report color-selective photodetection from intermediate, monolayered, quantum dots buried in between amorphous-oxide semiconductors. The proposed active channel in phototransistors is a hybrid configuration of oxide-quantum dot-oxide layers, where the gate-tunable electrical property of silicon-doped, indium-zinc-oxide layers is incorporated with the color-selective properties of quantum dots. A remarkably high detectivity (8.1 × 10 13 Jones) is obtained, along with three major findings: fast charge separation in monolayered quantum dots; efficient charge transport through high-mobility oxide layers (20 cm 2  V -1  s -1 ); and gate-tunable drain-current modulation. Particularly, the fast charge separation rate of 3.3 ns -1 measured with time-resolved photoluminescence is attributed to the intermediate quantum dots buried in oxide layers. These results facilitate the realization of efficient color-selective detection exhibiting a photoconductive gain of 10 7 , obtained using a room-temperature deposition of oxide layers and a solution process of quantum dots. This work offers promising opportunities in emerging applications for color detection with sensitivity, transparency, and flexibility.The development of highly sensitive photodetectors is important for image sensing and optical communication applications. Cho et al., report ultra-sensitive photodetectors based on monolayered quantum dots buried in between amorphous-oxide semiconductors and demonstrate color-detecting logic gates.

Photon and carrier management design for nonplanar thin-film copper indium gallium diselenide photovoltaics

DOEpatents

Atwater, Harry A.; Callahan, Dennis; Bukowsky, Colton

2017-11-21

Photovoltaic structures are disclosed. The structures can comprise randomly or periodically structured layers, a dielectric layer to reduce back diffusion of charge carriers, and a metallic layer to reflect photons back towards the absorbing semiconductor layers. This design can increase efficiency of photovoltaic structures. The structures can be fabricated by nanoimprint.

Epitaxial MoS2/GaN structures to enable vertical 2D/3D semiconductor heterostructure devices

NASA Astrophysics Data System (ADS)

Ruzmetov, D.; Zhang, K.; Stan, G.; Kalanyan, B.; Eichfeld, S.; Burke, R.; Shah, P.; O'Regan, T.; Crowne, F.; Birdwell, A. G.; Robinson, J.; Davydov, A.; Ivanov, T.

MoS2/GaN structures are investigated as a building block for vertical 2D/3D semiconductor heterostructure devices that utilize a 3D substrate (GaN) as an active component of the semiconductor device without the need of mechanical transfer of the 2D layer. Our CVD-grown monolayer MoS2 has been shown to be epitaxially aligned to the GaN lattice which is a pre-requisite for high quality 2D/3D interfaces desired for efficient vertical transport and large area growth. The MoS2 coverage is nearly 50 % including isolated triangles and monolayer islands. The GaN template is a double-layer grown by MOCVD on sapphire and allows for measurement of transport perpendicular to the 2D layer. Photoluminescence, Raman, XPS, Kelvin force probe microscopy, and SEM analysis identified high quality monolayer MoS2. The MoS2/GaN structures electrically conduct in the out-of-plane direction and across the van der Waals gap, as measured with conducting AFM (CAFM). The CAFM current maps and I-V characteristics are analyzed to estimate the MoS2/GaN contact resistivity to be less than 4 Ω-cm2 and current spreading in the MoS2 monolayer to be approx. 1 μm in diameter. Epitaxial MoS2/GaN heterostructures present a promising platform for the design of energy-efficient, high-speed vertical devices incorporating 2D layered materials with 3D semiconductors.

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Sung Ju; Park, Min; Kang, Hojin

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibilitymore » in transition metal dichalcogenide (TMD)-based electronics.« less

Systems and methods for producing low work function electrodes

DOEpatents

Kippelen, Bernard; Fuentes-Hernandez, Canek; Zhou, Yinhua; Kahn, Antoine; Meyer, Jens; Shim, Jae Won; Marder, Seth R.

2015-07-07

According to an exemplary embodiment of the invention, systems and methods are provided for producing low work function electrodes. According to an exemplary embodiment, a method is provided for reducing a work function of an electrode. The method includes applying, to at least a portion of the electrode, a solution comprising a Lewis basic oligomer or polymer; and based at least in part on applying the solution, forming an ultra-thin layer on a surface of the electrode, wherein the ultra-thin layer reduces the work function associated with the electrode by greater than 0.5 eV. According to another exemplary embodiment of the invention, a device is provided. The device includes a semiconductor; at least one electrode disposed adjacent to the semiconductor and configured to transport electrons in or out of the semiconductor.

Theoretical study in carrier mobility of two-dimensional materials

NASA Astrophysics Data System (ADS)

Huang, R.

2017-09-01

Recently, the theoretical prediction on carrier mobility of two-dimensional (2D) materials has aroused wild attention. At present, there is still a large gap between the theoretical prediction and the device performance of the semiconductor based on the 2D layer semiconductor materials such as graphene. It is particularly important to theoretically design and screen the high-performance 2D layered semiconductor materials with suitable band gap and high carrier mobility. This paper introduces some 2D materials with fine properties and deduces the formula for mobility of the isotropic materials on the basis of the deformation potential theory and Fermic golden rule under acoustic phonon scattering conditions, and then discusses the carrier mobility of anisotropic materials with Dirac cones. We point out the misconceptions in the existing literature and discuss the correct ones.

Density functional theory study of bulk and single-layer magnetic semiconductor CrPS4

NASA Astrophysics Data System (ADS)

Zhuang, Houlong L.; Zhou, Jia

2016-11-01

Searching for two-dimensional (2D) materials with multifunctionality is one of the main goals of current research in 2D materials. Magnetism and semiconducting are certainly two desirable functional properties for a single 2D material. In line with this goal, here we report a density functional theory (DFT) study of bulk and single-layer magnetic semiconductor CrPS4. We find that the ground-state magnetic structure of bulk CrPS4 exhibits the A-type antiferromagnetic ordering, which transforms to ferromagnetic (FM) ordering in single-layer CrPS4. The calculated formation energy and phonon spectrum confirm the stability of single-layer CrPS4. The band gaps of FM single-layer CrPS4 calculated with a hybrid density functional are within the visible-light range. We also study the effects of FM ordering on the optical absorption spectra and band alignments for water splitting, indicating that single-layer CrPS4 could be a potential photocatalyst. Our work opens up ample opportunities of energy-related applications of single-layer CrPS4.

Rhenium Dichalcogenides: Layered Semiconductors with Two Vertical Orientations.

PubMed

Hart, Lewis; Dale, Sara; Hoye, Sarah; Webb, James L; Wolverson, Daniel

2016-02-10

The rhenium and technetium diselenides and disulfides are van der Waals layered semiconductors in some respects similar to more well-known transition metal dichalcogenides (TMD) such as molybdenum sulfide. However, their symmetry is lower, consisting only of an inversion center, so that turning a layer upside-down (that is, applying a C2 rotation about an in-plane axis) is not a symmetry operation, but reverses the sign of the angle between the two nonequivalent in-plane crystallographic axes. A given layer thus can be placed on a substrate in two symmetrically nonequivalent (but energetically similar) ways. This has consequences for the exploitation of the anisotropic properties of these materials in TMD heterostructures and is expected to lead to a new source of domain structure in large-area layer growth. We produced few-layer ReS2 and ReSe2 samples with controlled "up" or "down" orientations by micromechanical cleavage and we show how polarized Raman microscopy can be used to distinguish these two orientations, thus establishing Raman as an essential tool for the characterization of large-area layers.

Facet-Selective Epitaxy of Compound Semiconductors on Faceted Silicon Nanowires.

PubMed

Mankin, Max N; Day, Robert W; Gao, Ruixuan; No, You-Shin; Kim, Sun-Kyung; McClelland, Arthur A; Bell, David C; Park, Hong-Gyu; Lieber, Charles M

2015-07-08

Integration of compound semiconductors with silicon (Si) has been a long-standing goal for the semiconductor industry, as direct band gap compound semiconductors offer, for example, attractive photonic properties not possible with Si devices. However, mismatches in lattice constant, thermal expansion coefficient, and polarity between Si and compound semiconductors render growth of epitaxial heterostructures challenging. Nanowires (NWs) are a promising platform for the integration of Si and compound semiconductors since their limited surface area can alleviate such material mismatch issues. Here, we demonstrate facet-selective growth of cadmium sulfide (CdS) on Si NWs. Aberration-corrected transmission electron microscopy analysis shows that crystalline CdS is grown epitaxially on the {111} and {110} surface facets of the Si NWs but that the Si{113} facets remain bare. Further analysis of CdS on Si NWs grown at higher deposition rates to yield a conformal shell reveals a thin oxide layer on the Si{113} facet. This observation and control experiments suggest that facet-selective growth is enabled by the formation of an oxide, which prevents subsequent shell growth on the Si{113} NW facets. Further studies of facet-selective epitaxial growth of CdS shells on micro-to-mesoscale wires, which allows tuning of the lateral width of the compound semiconductor layer without lithographic patterning, and InP shell growth on Si NWs demonstrate the generality of our growth technique. In addition, photoluminescence imaging and spectroscopy show that the epitaxial shells display strong and clean band edge emission, confirming their high photonic quality, and thus suggesting that facet-selective epitaxy on NW substrates represents a promising route to integration of compound semiconductors on Si.

FIBER AND INTEGRATED OPTICS: Emission properties of graded-index corrugated waveguides with a metal or semiconductor coating

NASA Astrophysics Data System (ADS)

Ataya, B. A.; Osovitskiĭ, A. N.

1992-02-01

A numerical method was used to investigate the emission of TE-polarized light from a graded-index corrugated waveguide coated with a metal or semiconductor and either with or without a buffer layer. The main emission characteristics of these systems were analyzed. In the case of metallized dielectric structures an optimal corrugation depth was established for which the emitted power is a maximum. It was found that when the parameters of a structure with a buffer layer were correctly chosen and a highly reflective metal coating was used, practically all the power in the waveguide wave could be emitted along a specified direction. A structure with a buffer layer and an aluminum coating was investigated experimentally.

Phosphorus doping a semiconductor particle

DOEpatents

Stevens, G.D.; Reynolds, J.S.

1999-07-20

A method of phosphorus doping a semiconductor particle using ammonium phosphate is disclosed. A p-doped silicon sphere is mixed with a diluted solution of ammonium phosphate having a predetermined concentration. These spheres are dried with the phosphorus then being diffused into the sphere to create either a shallow or deep p-n junction. A good PSG glass layer is formed on the surface of the sphere during the diffusion process. A subsequent segregation anneal process is utilized to strip metal impurities from near the p-n junction into the glass layer. A subsequent HF strip procedure is then utilized to removed the PSG layer. Ammonium phosphate is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirement. 1 fig.

Phosphorous doping a semiconductor particle

DOEpatents

Stevens, Gary Don; Reynolds, Jeffrey Scott

1999-07-20

A method (10) of phosphorus doping a semiconductor particle using ammonium phosphate. A p-doped silicon sphere is mixed with a diluted solution of ammonium phosphate having a predetermined concentration. These spheres are dried (16, 18), with the phosphorus then being diffused (20) into the sphere to create either a shallow or deep p-n junction. A good PSG glass layer is formed on the surface of the sphere during the diffusion process. A subsequent segregation anneal process is utilized to strip metal impurities from near the p-n junction into the glass layer. A subsequent HF strip procedure is then utilized to removed the PSG layer. Ammonium phosphate is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirement.

Semiconductor photoelectrochemistry

NASA Technical Reports Server (NTRS)

Buoncristiani, A. M.; Byvik, C. E.

1983-01-01

Semiconductor photoelectrochemical reactions are investigated. A model of the charge transport processes in the semiconductor, based on semiconductor device theory, is presented. It incorporates the nonlinear processes characterizing the diffusion and reaction of charge carriers in the semiconductor. The model is used to study conditions limiting useful energy conversion, specifically the saturation of current flow due to high light intensity. Numerical results describing charge distributions in the semiconductor and its effects on the electrolyte are obtained. Experimental results include: an estimate rate at which a semiconductor photoelectrode is capable of converting electromagnetic energy into chemical energy; the effect of cell temperature on the efficiency; a method for determining the point of zero zeta potential for macroscopic semiconductor samples; a technique using platinized titanium dioxide powders and ultraviolet radiation to produce chlorine, bromine, and iodine from solutions containing their respective ions; the photoelectrochemical properties of a class of layered compounds called transition metal thiophosphates; and a technique used to produce high conversion efficiency from laser radiation to chemical energy.

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors

PubMed Central

Matsushima, Toshinori; Sandanayaka, Atula S. D.; Esaki, Yu; Adachi, Chihaya

2015-01-01

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10–2 cm2/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm2/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost. PMID:26416434

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors.

PubMed

Matsushima, Toshinori; Sandanayaka, Atula S D; Esaki, Yu; Adachi, Chihaya

2015-09-29

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10(-2) cm(2)/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm(2)/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost.

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors

NASA Astrophysics Data System (ADS)

Matsushima, Toshinori; Sandanayaka, Atula S. D.; Esaki, Yu; Adachi, Chihaya

2015-09-01

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10-2 cm2/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm2/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost.

Highly Crystalline C8-BTBT Thin-Film Transistors by Lateral Homo-Epitaxial Growth on Printed Templates.

PubMed

Janneck, Robby; Pilet, Nicolas; Bommanaboyena, Satya Prakash; Watts, Benjamin; Heremans, Paul; Genoe, Jan; Rolin, Cedric

2017-11-01

Highly crystalline thin films of organic semiconductors offer great potential for fundamental material studies as well as for realizing high-performance, low-cost flexible electronics. The fabrication of these films directly on inert substrates is typically done by meniscus-guided coating techniques. The resulting layers show morphological defects that hinder charge transport and induce large device-to-device variability. Here, a double-step method for organic semiconductor layers combining a solution-processed templating layer and a lateral homo-epitaxial growth by a thermal evaporation step is reported. The epitaxial regrowth repairs most of the morphological defects inherent to meniscus-guided coatings. The resulting film is highly crystalline and features a mobility increased by a factor of three and a relative spread in device characteristics improved by almost half an order of magnitude. This method is easily adaptable to other coating techniques and offers a route toward the fabrication of high-performance, large-area electronics based on highly crystalline thin films of organic semiconductors. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

SiGe derivatization by spontaneous reduction of aryl diazonium salts

NASA Astrophysics Data System (ADS)

Girard, A.; Geneste, F.; Coulon, N.; Cardinaud, C.; Mohammed-Brahim, T.

2013-10-01

Germanium semiconductors have interesting properties for FET-based biosensor applications since they possess high surface roughness allowing the immobilization of a high amount of receptors on a small surface area. Since SiGe combined low cost of Si and intrinsic properties of Ge with high mobility carriers, we focused the study on this particularly interesting material. The comparison of the efficiency of a functionalization process involving the spontaneous reduction of diazonium salts is studied on Si(1 0 0), SiGe and Ge semiconductors. XPS analysis of the functionalized surfaces reveals the presence of a covalent grafted layer on all the substrates that was confirmed by AFM. Interestingly, the modified Ge derivatives have still higher surface roughness after derivatization. To support the estimated thickness by XPS, a step measurement of the organic layers is done by AFM or by profilometer technique after a O2 plasma etching of the functionalized layer. This original method is well-adapted to measure the thickness of thin organic films on rough substrates such as germanium. The analyses show a higher chemical grafting on SiGe substrates compared with Si and Ge semiconductors.

Pure silver ohmic contacts to N- and P- type gallium arsenide materials

DOEpatents

Hogan, Stephen J.

1986-01-01

Disclosed is an improved process for manufacturing gallium arsenide semiconductor devices having as its components an n-type gallium arsenide substrate layer and a p-type gallium arsenide diffused layer. The improved process comprises forming a pure silver ohmic contact to both the diffused layer and the substrate layer, wherein the n-type layer comprises a substantially low doping carrier concentration.

37 CFR 211.5 - Deposit of identifying material.

Code of Federal Regulations, 2010 CFR

2010-07-01

... perceptible representation of each layer of the mask work consisting of: (i) Sets of plastic color overlay... photograph of each layer of the work fixed in a semiconductor chip product. The visually perceptible... chip product. (c) Trade secret protection. Where specific layers of a mask work fixed in a...

Solar cell with back side contacts

DOEpatents

Nielson, Gregory N; Okandan, Murat; Cruz-Campa, Jose Luis; Resnick, Paul J; Wanlass, Mark Woodbury; Clews, Peggy J

2013-12-24

A III-V solar cell is described herein that includes all back side contacts. Additionally, the positive and negative electrical contacts contact compoud semiconductor layers of the solar cell other than the absorbing layer of the solar cell. That is, the positive and negative electrical contacts contact passivating layers of the solar cell.

Properties of nanocones formed on a surface of semiconductors by laser radiation: quantum confinement effect of electrons, phonons, and excitons

PubMed Central

2011-01-01

On the basis of the analysis of experimental results, a two-stage mechanism of nanocones formation on the irradiated surface of semiconductors by Nd:YAG laser is proposed for elementary semiconductors and solid solutions, such as Si, Ge, SiGe, and CdZnTe. Properties observed are explained in the frame of quantum confinement effect. The first stage of the mechanism is characterized by the formation of a thin strained top layer, due to redistribution of point defects in temperature-gradient field induced by laser radiation. The second stage is characterized by mechanical plastic deformation of the stained top layer leading to arising of nanocones, due to selective laser absorption of the top layer. The nanocones formed on the irradiated surface of semiconductors by Nd:YAG laser possessing the properties of 1D graded bandgap have been found for Si, Ge, and SiGe as well, however QD structure in CdTe was observed. The model is confirmed by "blue shift" of bands in photoluminescence spectrum, "red shift" of longitudinal optical line in Raman back scattering spectrum of Ge crystal, appearance of Ge phase in SiGe solid solution after irradiation by the laser at intensity 20 MW/cm2, and non-monotonous dependence of Si crystal micro-hardness as function of the laser intensity. PMID:22060172

The simulation of air recirculation and fire/explosion phenomena within a semiconductor factory.

PubMed

I, Yet-Pole; Chiu, Yi-Long; Wu, Shi-Jen

2009-04-30

The semiconductor industry is the collection of capital-intensive firms that employ a variety of hazardous chemicals and engage in the design and fabrication of semiconductor devices. Owing to its processing characteristics, the fully confined structure of the fabrication area (fab) and the vertical airflow ventilation design restrict the applications of traditional consequence analysis techniques that are commonly used in other industries. The adverse situation also limits the advancement of a fire/explosion prevention design for the industry. In this research, a realistic model of a semiconductor factory with a fab, sub-fabrication area, supply air plenum, and return air plenum structures was constructed and the computational fluid dynamics algorithm was employed to simulate the possible fire/explosion range and its severity. The semiconductor factory has fan module units with high efficiency particulate air filters that can keep the airflow uniform within the cleanroom. This condition was modeled by 25 fans, three layers of porous ceiling, and one layer of porous floor. The obtained results predicted very well the real airflow pattern in the semiconductor factory. Different released gases, leak locations, and leak rates were applied to investigate their influence on the hazard range and severity. Common mitigation measures such as a water spray system and a pressure relief panel were also provided to study their potential effectiveness to relieve thermal radiation and overpressure hazards within a fab. The semiconductor industry can use this simulation procedure as a reference on how to implement a consequence analysis for a flammable gas release accident within an air recirculation cleanroom.

Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

DOEpatents

Jansen, Kai W.; Maley, Nagi

2000-01-01

High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

DOEpatents

Jansen, Kai W.; Maley, Nagi

2001-01-01

High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

Mechanical scriber for semiconductor devices

DOEpatents

Lin, Peter T.

1985-01-01

A mechanical scriber using a scribing tip, such as a diamond, provides controlled scriber forces with a spring-loaded compound lever arrangement. The scribing force and range of scribing depth are adjusted by a pair of adjustable micrometer heads. A semiconductor device, such as a multilayer solar cell, can be formed into scribed strips at each layer.

Nanoparticle Solutions for Printed Electronics

DTIC Science & Technology

2013-09-19

the printed semiconductor materials and their nanoparticle and colloidal precursors. Without this basic knowledge, further development and the...titania, silica ) were investigated in the production of complementary inks for complex devices. These were either obtained commercially in...layers were also deposited on borosilicate glass and silicon wafers. In the photovoltaic program, hybrid inorganic-organic semiconductor combinations

Semiconductor-Insulator-Semiconductor Diode Consisting of Monolayer MoS2, h-BN, and GaN Heterostructure.

PubMed

Jeong, Hyun; Bang, Seungho; Oh, Hye Min; Jeong, Hyeon Jun; An, Sung-Jin; Han, Gang Hee; Kim, Hyun; Kim, Ki Kang; Park, Jin Cheol; Lee, Young Hee; Lerondel, Gilles; Jeong, Mun Seok

2015-10-27

We propose a semiconductor-insulator-semiconductor (SIS) heterojunction diode consisting of monolayer (1-L) MoS2, hexagonal boron nitride (h-BN), and epitaxial p-GaN that can be applied to high-performance nanoscale optoelectronics. The layered materials of 1-L MoS2 and h-BN, grown by chemical vapor deposition, were vertically stacked by a wet-transfer method on a p-GaN layer. The final structure was verified by confocal photoluminescence and Raman spectroscopy. Current-voltage (I-V) measurements were conducted to compare the device performance with that of a more classical p-n structure. In both structures (the p-n and SIS heterojunction diode), clear current-rectifying characteristics were observed. In particular, a current and threshold voltage were obtained for the SIS structure that was higher compared to that of the p-n structure. This indicated that tunneling is the predominant carrier transport mechanism. In addition, the photoresponse of the SIS structure induced by the illumination of visible light was observed by photocurrent measurements.

Vertical dielectric screening of few-layer van der Waals semiconductors.

PubMed

Koo, Jahyun; Gao, Shiyuan; Lee, Hoonkyung; Yang, Li

2017-10-05

Vertical dielectric screening is a fundamental parameter of few-layer van der Waals two-dimensional (2D) semiconductors. However, unlike the widely-accepted wisdom claiming that the vertical dielectric screening is sensitive to the thickness, our first-principles calculation based on the linear response theory (within the weak field limit) reveals that this screening is independent of the thickness and, in fact, it is the same as the corresponding bulk value. This conclusion is verified in a wide range of 2D paraelectric semiconductors, covering narrow-gap ones and wide-gap ones with different crystal symmetries, providing an efficient and reliable way to calculate and predict static dielectric screening of reduced-dimensional materials. Employing this conclusion, we satisfactorily explain the tunable band gap in gated 2D semiconductors. We further propose to engineer the vertical dielectric screening by changing the interlayer distance via vertical pressure or hybrid structures. Our predicted vertical dielectric screening can substantially simplify the understanding of a wide range of measurements and it is crucial for designing 2D functional devices.

A General Strategy to Achieve Colossal Permittivity and Low Dielectric Loss Through Constructing Insulator/Semiconductor/Insulator Multilayer Structures

NASA Astrophysics Data System (ADS)

Liu, Kai; Sun, Yalong; Zheng, Fengang; Tse, Mei-Yan; Sun, Qingbo; Liu, Yun; Hao, Jianhua

2018-06-01

In this work, we propose a route to realize high-performance colossal permittivity (CP) by creating multilayer structures of insulator/semiconductor/insulator. To prove the new concept, we made heavily reduced rutile TiO2 via annealing route in Ar/H2 atmosphere. Dielectric studies show that the maximum dielectric permittivity ( 3.0 × 104) of our prepared samples is about 100 times higher than that ( 300) of conventional TiO2. The minimum dielectric loss is 0.03 (at 104-105 Hz). Furthermore, CP is almost independent of the frequency (100-106 Hz) and the temperature (20-350 K). We suggest that the colossal permittivity is attributed to the high carrier concentration of the inner TiO2 semiconductor, while the low dielectric loss is due to the presentation of the insulator layer on the surface of TiO2. The method proposed here can be expanded to other material systems, such as semiconductor Si sandwiched by top and bottom insulator layers of Ga2O3.

Cross-plane thermal conductivity of (Ti,W)N/(Al,Sc)N metal/semiconductor superlattices

NASA Astrophysics Data System (ADS)

Saha, Bivas; Koh, Yee Rui; Comparan, Jonathan; Sadasivam, Sridhar; Schroeder, Jeremy L.; Garbrecht, Magnus; Mohammed, Amr; Birch, Jens; Fisher, Timothy; Shakouri, Ali; Sands, Timothy D.

2016-01-01

Reduction of cross-plane thermal conductivity and understanding of the mechanisms of heat transport in nanostructured metal/semiconductor superlattices are crucial for their potential applications in thermoelectric and thermionic energy conversion devices, thermal management systems, and thermal barrier coatings. We have developed epitaxial (Ti,W)N/(Al,Sc)N metal/semiconductor superlattices with periodicity ranging from 1 nm to 240 nm that show significantly lower thermal conductivity compared to the parent TiN/(Al,Sc)N superlattice system. The (Ti,W)N/(Al,Sc)N superlattices grow with [001] orientation on the MgO(001) substrates with well-defined coherent layers and are nominally single crystalline with low densities of extended defects. Cross-plane thermal conductivity (measured by time-domain thermoreflectance) decreases with an increase in the superlattice interface density in a manner that is consistent with incoherent phonon boundary scattering. Thermal conductivity values saturate at 1.7 W m-1K-1 for short superlattice periods possibly due to a delicate balance between long-wavelength coherent phonon modes and incoherent phonon scattering from heavy tungsten atomic sites and superlattice interfaces. First-principles density functional perturbation theory based calculations are performed to model the vibrational spectrum of the individual component materials, and transport models are used to explain the interface thermal conductance across the (Ti,W)N/(Al,Sc)N interfaces as a function of periodicity. The long-wavelength coherent phonon modes are expected to play a dominant role in the thermal transport properties of the short-period superlattices. Our analysis of the thermal transport properties of (Ti,W)N/(Al,Sc)N metal/semiconductor superlattices addresses fundamental questions about heat transport in multilayer materials.

Tunneling Nanoelectromechanical Switches Based on Compressible Molecular Thin Films.

PubMed

Niroui, Farnaz; Wang, Annie I; Sletten, Ellen M; Song, Yi; Kong, Jing; Yablonovitch, Eli; Swager, Timothy M; Lang, Jeffrey H; Bulović, Vladimir

2015-08-25

Abrupt switching behavior and near-zero leakage current of nanoelectromechanical (NEM) switches are advantageous properties through which NEMs can outperform conventional semiconductor electrical switches. To date, however, typical NEMs structures require high actuation voltages and can prematurely fail through permanent adhesion (defined as stiction) of device components. To overcome these challenges, in the present work we propose a NEM switch, termed a "squitch," which is designed to electromechanically modulate the tunneling current through a nanometer-scale gap defined by an organic molecular film sandwiched between two electrodes. When voltage is applied across the electrodes, the generated electrostatic force compresses the sandwiched molecular layer, thereby reducing the tunneling gap and causing an exponential increase in the current through the device. The presence of the molecular layer avoids direct contact of the electrodes during the switching process. Furthermore, as the layer is compressed, the increasing surface adhesion forces are balanced by the elastic restoring force of the deformed molecules which can promote zero net stiction and recoverable switching. Through numerical analysis, we demonstrate the potential of optimizing squitch design to enable large on-off ratios beyond 6 orders of magnitude with operation in the sub-1 V regime and with nanoseconds switching times. Our preliminary experimental results based on metal-molecule-graphene devices suggest the feasibility of the proposed tunneling switching mechanism. With optimization of device design and material engineering, squitches can give rise to a broad range of low-power electronic applications.

GaAs photoconductive semiconductor switch

DOEpatents

Loubriel, G.M.; Baca, A.G.; Zutavern, F.J.

1998-09-08

A high gain, optically triggered, photoconductive semiconductor switch (PCSS) implemented in GaAs as a reverse-biased pin structure with a passivation layer above the intrinsic GaAs substrate in the gap between the two electrodes of the device is disclosed. The reverse-biased configuration in combination with the addition of the passivation layer greatly reduces surface current leakage that has been a problem for prior PCSS devices and enables employment of the much less expensive and more reliable DC charging systems instead of the pulsed charging systems that needed to be used with prior PCSS devices. 5 figs.

High speed all optical logic gates based on quantum dot semiconductor optical amplifiers.

PubMed

Ma, Shaozhen; Chen, Zhe; Sun, Hongzhi; Dutta, Niloy K

2010-03-29

A scheme to realize all-optical Boolean logic functions AND, XOR and NOT using semiconductor optical amplifiers with quantum-dot active layers is studied. nonlinear dynamics including carrier heating and spectral hole-burning are taken into account together with the rate equations scheme. Results show with QD excited state and wetting layer serving as dual-reservoir of carriers, as well as the ultra fast carrier relaxation of the QD device, this scheme is suitable for high speed Boolean logic operations. Logic operation can be carried out up to speed of 250 Gb/s.

Method of making diode structures

DOEpatents

Compaan, Alvin D.; Gupta, Akhlesh

2006-11-28

A method of making a diode structure includes the step of depositing a transparent electrode layer of any one or more of the group ZnO, ZnS and CdO onto a substrate layer, and depositing an active semiconductor junction having an n-type layer and a p-type layer onto the transparent electrode layer under process conditions that avoid substantial degradation of the electrode layer. A back electrode coating layer is applied to form a diode structure.

Photovoltaic structures having a light scattering interface layer and methods of making the same

DOEpatents

Liu, Xiangxin; Compaan, Alvin D.; Paudel, Naba Raj

2015-10-13

Photovoltaic (PV) cell structures having an integral light scattering interface layer configured to diffuse or scatter light prior to entering a semiconductor material and methods of making the same are described.

Improved insulator layer for MIS devices

NASA Technical Reports Server (NTRS)

Miller, W. E.

1980-01-01

Insulating layer of supersonic conductor such as LaF sub 3 has been shown able to impart improved electrical properties to photoconductive detectors and promises to improve other metal/insulator/semiconductor (MIS) devices, e.g., MOSFET and integrated circuits.

Graphite based Schottky diodes formed semiconducting substrates

NASA Astrophysics Data System (ADS)

Schumann, Todd; Tongay, Sefaattin; Hebard, Arthur

2010-03-01

We demonstrate the formation of semimetal graphite/semiconductor Schottky barriers where the semiconductor is either silicon (Si), gallium arsenide (GaAs) or 4H-silicon carbide (4H-SiC). The fabrication can be as easy as allowing a dab of graphite paint to air dry on any one of the investigated semiconductors. Near room temperature, the forward-bias diode characteristics are well described by thermionic emission, and the extracted barrier heights, which are confirmed by capacitance voltage measurements, roughly follow the Schottky-Mott relation. Since the outermost layer of the graphite electrode is a single graphene sheet, we expect that graphene/semiconductor barriers will manifest similar behavior.

Ferroelectric polarization induces electric double layer bistability in electrolyte-gated field-effect transistors.

PubMed

Fabiano, Simone; Crispin, Xavier; Berggren, Magnus

2014-01-08

The dense surface charges expressed by a ferroelectric polymeric thin film induce ion displacement within a polyelectrolyte layer and vice versa. This is because the density of dipoles along the surface of the ferroelectric thin film and its polarization switching time matches that of the (Helmholtz) electric double layers formed at the ferroelectric/polyelectrolyte and polyelectrolyte/semiconductor interfaces. This combination of materials allows for introducing hysteresis effects in the capacitance of an electric double layer capacitor. The latter is advantageously used to control the charge accumulation in the semiconductor channel of an organic field-effect transistor. The resulting memory transistors can be written at a gate voltage of around 7 V and read out at a drain voltage as low as 50 mV. The technological implication of this large difference between write and read-out voltages lies in the non-destructive reading of this ferroelectric memory.

Formation of embedded plasmonic Ga nanoparticle arrays and their influence on GaAs photoluminescence

NASA Astrophysics Data System (ADS)

Kang, M.; Jeon, S.; Jen, T.; Lee, J.-E.; Sih, V.; Goldman, R. S.

2017-07-01

We introduce a novel approach to the seamless integration of plasmonic nanoparticle (NP) arrays into semiconductor layers and demonstrate their enhanced photoluminescence (PL) efficiency. Our approach utilizes focused ion beam-induced self-assembly of close-packed arrays of Ga NPs with tailorable NP diameters, followed by overgrowth of GaAs layers using molecular beam epitaxy. Using a combination of PL spectroscopy and electromagnetic computations, we identify a regime of Ga NP diameter and overgrown GaAs layer thickness where NP-array-enhanced absorption in GaAs leads to enhanced GaAs near-band-edge (NBE) PL efficiency, surpassing that of high-quality epitaxial GaAs layers. As the NP array depth and size are increased, the reduction in spontaneous emission rate overwhelms the NP-array-enhanced absorption, leading to a reduced NBE PL efficiency. This approach provides an opportunity to enhance the PL efficiency of a wide variety of semiconductor heterostructures.

Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

2016-12-01

The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

Fabricating metal-oxide-semiconductor field-effect transistors on a polyethylene terephthalate substrate by applying low-temperature layer transfer of a single-crystalline silicon layer by meniscus force

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sakaike, Kohei; Akazawa, Muneki; Nakamura, Shogo

2013-12-02

A low-temperature local-layer technique for transferring a single-crystalline silicon (c-Si) film by using a meniscus force was proposed, and an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) was fabricated on polyethylene terephthalate (PET) substrate. It was demonstrated that it is possible to transfer and form c-Si films in the required shape at the required position on PET substrates at extremely low temperatures by utilizing a meniscus force. The proposed technique for layer transfer was applied for fabricating high-performance c-Si MOSFETs on a PET substrate. The fabricated MOSFET showed a high on/off ratio of more than 10{sup 8} and a high field-effect mobilitymore » of 609 cm{sup 2} V{sup −1} s{sup −1}.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baker, Kevin L.

The purpose of this LDRD project was to demonstrate high spatial and temporal resolution x-ray imaging using optical detectors, and in particular the VISAR and OHRV diagnostics on the OMEGA laser. The x-ray source being imaged was a backlighter capsule being imploded by 39 beams of the OMEGA laser. In particular this approach utilized a semiconductor with the side facing the backlighter capsule coated with a thin aluminum layer to allow x rays to pass through the metal layer and then get absorbed in the semiconductor. The other side of the semiconductor was AR coated to allow the VISAR ormore » OHRV probe beam to sample the phase change of the semiconductor as the x rays were absorbed in the semiconductor. This technique is capable of acquiring sub-picosecond 2-D or 1-D x-ray images, detector spatial resolution of better than 10 um and the ability to operate in a high neutron flux environment expected on ignition shots with burning plasmas. In addition to demonstrating this technique on the OMEGA laser, several designs were made to improve the phase sensitivity, temporal resolution and number of frames over the existing diagnostics currently implemented on the OMEGA laser. These designs included both 2-d imaging diagnostics as well as improved 1-D imaging diagnostics which were streaked in time.« less

Three-dimensional cathodoluminescence characterization of a semipolar GaInN based LED sample

NASA Astrophysics Data System (ADS)

Hocker, Matthias; Maier, Pascal; Tischer, Ingo; Meisch, Tobias; Caliebe, Marian; Scholz, Ferdinand; Mundszinger, Manuel; Kaiser, Ute; Thonke, Klaus

2017-02-01

A semipolar GaInN based light-emitting diode (LED) sample is investigated by three-dimensionally resolved cathodoluminescence (CL) mapping. Similar to conventional depth-resolved CL spectroscopy (DRCLS), the spatial resolution perpendicular to the sample surface is obtained by calibration of the CL data with Monte-Carlo-simulations (MCSs) of the primary electron beam scattering. In addition to conventional MCSs, we take into account semiconductor-specific processes like exciton diffusion and the influence of the band gap energy. With this method, the structure of the LED sample under investigation can be analyzed without additional sample preparation, like cleaving of cross sections. The measurement yields the thickness of the p-type GaN layer, the vertical position of the quantum wells, and a defect analysis of the underlying n-type GaN, including the determination of the free charge carrier density. The layer arrangement reconstructed from the DRCLS data is in good agreement with the nominal parameters defined by the growth conditions.

Semiconducting Single-Walled Carbon Nanotubes in Solar Energy Harvesting

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blackburn, Jeffrey L.

Semiconducting single-walled carbon nanotubes (s-SWCNTs) represent a tunable model one-dimensional system with exceptional optical and electronic properties. High-throughput separation and purification strategies have enabled the integration of s-SWCNTs into a number of optoelectronic applications, including photovoltaics (PVs). In this Perspective, we discuss the fundamental underpinnings of two model PV interfaces involving s-SWCNTs. We first discuss s-SWCNT-fullerene heterojunctions where exciton dissociation at the donor-acceptor interface drives solar energy conversion. Next, we discuss charge extraction at the interface between s-SWCNTs and a photoexcited perovskite active layer. In each case, the use of highly enriched semiconducting SWCNT samples enables fundamental insights into themore » thermodynamic and kinetic mechanisms that drive the efficient conversion of solar photons into long-lived separated charges. As a result, these model systems help to establish design rules for next-generation PV devices containing well-defined organic semiconductor layers and help to frame a number of important outstanding questions that can guide future studies.« less

Semiconducting Single-Walled Carbon Nanotubes in Solar Energy Harvesting

DOE PAGES

Blackburn, Jeffrey L.

2017-06-14

Semiconducting single-walled carbon nanotubes (s-SWCNTs) represent a tunable model one-dimensional system with exceptional optical and electronic properties. High-throughput separation and purification strategies have enabled the integration of s-SWCNTs into a number of optoelectronic applications, including photovoltaics (PVs). In this Perspective, we discuss the fundamental underpinnings of two model PV interfaces involving s-SWCNTs. We first discuss s-SWCNT-fullerene heterojunctions where exciton dissociation at the donor-acceptor interface drives solar energy conversion. Next, we discuss charge extraction at the interface between s-SWCNTs and a photoexcited perovskite active layer. In each case, the use of highly enriched semiconducting SWCNT samples enables fundamental insights into themore » thermodynamic and kinetic mechanisms that drive the efficient conversion of solar photons into long-lived separated charges. As a result, these model systems help to establish design rules for next-generation PV devices containing well-defined organic semiconductor layers and help to frame a number of important outstanding questions that can guide future studies.« less

Interlayer couplings, Moiré patterns, and 2D electronic superlattices in MoS2/WSe2 hetero-bilayers

PubMed Central

Zhang, Chendong; Chuu, Chih-Piao; Ren, Xibiao; Li, Ming-Yang; Li, Lain-Jong; Jin, Chuanhong; Chou, Mei-Yin; Shih, Chih-Kang

2017-01-01

By using direct growth, we create a rotationally aligned MoS2/WSe2 hetero-bilayer as a designer van der Waals heterostructure. With rotational alignment, the lattice mismatch leads to a periodic variation of atomic registry between individual van der Waals layers, exhibiting a Moiré pattern with a well-defined periodicity. By combining scanning tunneling microscopy/spectroscopy, transmission electron microscopy, and first-principles calculations, we investigate interlayer coupling as a function of atomic registry. We quantitatively determine the influence of interlayer coupling on the electronic structure of the hetero-bilayer at different critical points. We show that the direct gap semiconductor concept is retained in the bilayer although the valence and conduction band edges are located at different layers. We further show that the local bandgap is periodically modulated in the X-Y direction with an amplitude of ~0.15 eV, leading to the formation of a two-dimensional electronic superlattice. PMID:28070558

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

NASA Astrophysics Data System (ADS)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

Long-range coupling of electron-hole pairs in spatially separated organic donor-acceptor layers

PubMed Central

Nakanotani, Hajime; Furukawa, Taro; Morimoto, Kei; Adachi, Chihaya

2016-01-01

Understanding exciton behavior in organic semiconductor molecules is crucial for the development of organic semiconductor-based excitonic devices such as organic light-emitting diodes and organic solar cells, and the tightly bound electron-hole pair forming an exciton is normally assumed to be localized on an organic semiconducting molecule. We report the observation of long-range coupling of electron-hole pairs in spatially separated electron-donating and electron-accepting molecules across a 10-nanometers-thick spacer layer. We found that the exciton energy can be tuned over 100 megaelectron volts and the fraction of delayed fluorescence can be increased by adjusting the spacer-layer thickness. Furthermore, increasing the spacer-layer thickness produced an organic light-emitting diode with an electroluminescence efficiency nearly eight times higher than that of a device without a spacer layer. Our results demonstrate the first example of a long-range coupled charge-transfer state between electron-donating and electron-accepting molecules in a working device. PMID:26933691

Static ferroelectric memory transistor having improved data retention

DOEpatents

Evans, Jr., Joseph T.; Warren, William L.; Tuttle, Bruce A.

1996-01-01

An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO.sub.3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentrations between 1% and 8%.

75 FR 447 - In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-01-05

... review (1) the finding that the claim term ``top layer'' recited in claim 1 of the '106 patent means ``an outer layer of the chip assembly upon which the terminals are fixed,'' the requirement that ``the `top layer' is a single layer,'' and the effect of the findings on the infringement analysis, invalidity...

Process for forming pure silver ohmic contacts to N- and P-type gallium arsenide materials

DOEpatents

Hogan, S.J.

1983-03-13

Disclosed is an improved process for manufacturing gallium arsenide semiconductor devices having as its components a n-type gallium arsenide substrate layer and a p-type gallium arsenide diffused layer. The improved process comprises forming a pure silver ohmic contact to both the diffuse layer and the substrate layer wherein the n-type layer comprises a substantially low doping carrier concentration.

Soft error rate simulation and initial design considerations of neutron intercepting silicon chip (NISC)

NASA Astrophysics Data System (ADS)

Celik, Cihangir

Advances in microelectronics result in sub-micrometer electronic technologies as predicted by Moore's Law, 1965, which states the number of transistors in a given space would double every two years. The most available memory architectures today have submicrometer transistor dimensions. The International Technology Roadmap for Semiconductors (ITRS), a continuation of Moore's Law, predicts that Dynamic Random Access Memory (DRAM) will have an average half pitch size of 50 nm and Microprocessor Units (MPU) will have an average gate length of 30 nm over the period of 2008-2012. Decreases in the dimensions satisfy the producer and consumer requirements of low power consumption, more data storage for a given space, faster clock speed, and portability of integrated circuits (IC), particularly memories. On the other hand, these properties also lead to a higher susceptibility of IC designs to temperature, magnetic interference, power supply, and environmental noise, and radiation. Radiation can directly or indirectly affect device operation. When a single energetic particle strikes a sensitive node in the micro-electronic device, it can cause a permanent or transient malfunction in the device. This behavior is called a Single Event Effect (SEE). SEEs are mostly transient errors that generate an electric pulse which alters the state of a logic node in the memory device without having a permanent effect on the functionality of the device. This is called a Single Event Upset (SEU) or Soft Error . Contrary to SEU, Single Event Latchup (SEL), Single Event Gate Rapture (SEGR), or Single Event Burnout (SEB) they have permanent effects on the device operation and a system reset or recovery is needed to return to proper operations. The rate at which a device or system encounters soft errors is defined as Soft Error Rate (SER). The semiconductor industry has been struggling with SEEs and is taking necessary measures in order to continue to improve system designs in nano-scale technologies. Prevention of SEEs has been studied and applied in the semiconductor industry by including radiation protection precautions in the system architecture or by using corrective algorithms in the system operation. Decreasing 10B content (20%of natural boron) in the natural boron of Borophosphosilicate glass (BPSG) layers that are conventionally used in the fabrication of semiconductor devices was one of the major radiation protection approaches for the system architecture. Neutron interaction in the BPSG layer was the origin of the SEEs because of the 10B (n,alpha) 7Li reaction products. Both of the particles produced have the capability of ionization in the silicon substrate region, whose thickness is comparable to the ranges of these particles. Using the soft error phenomenon in exactly the opposite manner of the semiconductor industry can provide a new neutron detection system based on the SERs in the semiconductor memories. By investigating the soft error mechanisms in the available semiconductor memories and enhancing the soft error occurrences in these devices, one can convert all memory using intelligent systems into portable, power efficient, directiondependent neutron detectors. The Neutron Intercepting Silicon Chip (NISC) project aims to achieve this goal by introducing 10B-enriched BPSG layers to the semiconductor memory architectures. This research addresses the development of a simulation tool, the NISC Soft Error Analysis Tool (NISCSAT), for soft error modeling and analysis in the semiconductor memories to provide basic design considerations for the NISC. NISCSAT performs particle transport and calculates the soft error probabilities, or SER, depending on energy depositions of the particles in a given memory node model of the NISC. Soft error measurements were performed with commercially available, off-the-shelf semiconductor memories and microprocessors to observe soft error variations with the neutron flux and memory supply voltage. Measurement results show that soft errors in the memories increase proportionally with the neutron flux, whereas they decrease with increasing the supply voltages. NISC design considerations include the effects of device scaling, 10B content in the BPSG layer, incoming neutron energy, and critical charge of the node for this dissertation. NISCSAT simulations were performed with various memory node models to account these effects. Device scaling simulations showed that any further increase in the thickness of the BPSG layer beyond 2 mum causes self-shielding of the incoming neutrons due to the BPSG layer and results in lower detection efficiencies. Moreover, if the BPSG layer is located more than 4 mum apart from the depletion region in the node, there are no soft errors in the node due to the fact that both of the reaction products have lower ranges in the silicon or any possible node layers. Calculation results regarding the critical charge indicated that the mean charge deposition of the reaction products in the sensitive volume of the node is about 15 fC. It is evident that the NISC design should have a memory architecture with a critical charge of 15 fC or less to obtain higher detection efficiencies. Moreover, the sensitive volume should be placed in close proximity to the BPSG layers so that its location would be within the range of alpha and 7Li particles. Results showed that the distance between the BPSG layer and the sensitive volume should be less than 2 mum to increase the detection efficiency of the NISC. Incoming neutron energy was also investigated by simulations and the results obtained from these simulations showed that NISC neutron detection efficiency is related with the neutron cross-sections of 10B (n,alpha) 7Li reaction, e.g., ratio of the thermal (0.0253 eV) to fast (2 MeV) neutron detection efficiencies is approximately equal to 8000:1. Environmental conditions and their effects on the NISC performance were also studied in this research. Cosmic rays were modeled and simulated via NISCSAT to investigate detection reliability of the NISC. Simulation results show that cosmic rays account for less than 2 % of the soft errors for the thermal neutron detection. On the other hand, fast neutron detection by the NISC, which already has a poor efficiency due to the low neutron cross-sections, becomes almost impossible at higher altitudes where the cosmic ray fluxes and their energies are higher. NISCSAT simulations regarding soft error dependency of the NISC for temperature and electromagnetic fields show that there are no significant effects in the NISC detection efficiency. Furthermore, the detection efficiency of the NISC decreases with both air humidity and use of moderators since the incoming neutrons scatter away before reaching the memory surface.

Deterministic strain-induced arrays of quantum emitters in a two-dimensional semiconductor

PubMed Central

Branny, Artur; Kumar, Santosh; Proux, Raphaël; Gerardot, Brian D

2017-01-01

An outstanding challenge in quantum photonics is scalability, which requires positioning of single quantum emitters in a deterministic fashion. Site positioning progress has been made in established platforms including defects in diamond and self-assembled quantum dots, albeit often with compromised coherence and optical quality. The emergence of single quantum emitters in layered transition metal dichalcogenide semiconductors offers new opportunities to construct a scalable quantum architecture. Here, using nanoscale strain engineering, we deterministically achieve a two-dimensional lattice of quantum emitters in an atomically thin semiconductor. We create point-like strain perturbations in mono- and bi-layer WSe2 which locally modify the band-gap, leading to efficient funnelling of excitons towards isolated strain-tuned quantum emitters that exhibit high-purity single photon emission. We achieve near unity emitter creation probability and a mean positioning accuracy of 120±32 nm, which may be improved with further optimization of the nanopillar dimensions. PMID:28530219

Lattice matched crystalline substrates for cubic nitride semiconductor growth

DOEpatents

Norman, Andrew G; Ptak, Aaron J; McMahon, William E

2015-02-24

Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline In.sub.xGa.sub.yAl.sub.1-x-yN alloy. The lattice parameter of the In.sub.xGa.sub.yAl.sub.1-x-yN or other group III-nitride alloy may be related to the substrate lattice parameter by (a')= 2(a) or (a')=(a)/ 2. The semiconductor alloy may be prepared to have a selected band gap.

Conductors and semiconductors for advanced organic electronics

NASA Astrophysics Data System (ADS)

Meyer-Friedrichsen, Timo; Elschner, Andreas; Keohan, Frank; Lövenich, Wilfried; Ponomarenko, Sergei A.

2009-08-01

The development of suitable materials for organic electronics is still one of the key points to access new application areas with this promising technology. Semiconductors based on thiophene chemistry show very high charge carrier mobilities. The functionalization with linker groups provided materials that built monomolecular layers of the semiconductors on the hydrolyzed oxide surface of a silicon-wafer. This approach lead to self-assembled mono-layer field-effect transistors (SAM-FETs) with mobilities of up to 0.04 cm2/Vs, which is comparable to the values of the respective bulk thin film. Transparent inorganic conductors like ITO are highly conductive but the costly processing and the brittleness hamper their use in cost-sensitive and/or flexible devices. Highly conductive PEDOT-grades have been developed with conductivities of up to 1000 S/cm which are easily applicable by printing techniques and can be used as ITO replacement in devices such as touch panels or organic photovoltaics.

Theory of negative refraction in periodic stratified metamaterials.

PubMed

Rukhlenko, Ivan D; Premaratne, Malin; Agrawal, Govind P

2010-12-20

We present a general theory of negative refraction in periodic stratified heterostructures with an arbitrary number of homogeneous, isotropic, nonmagnetic layers in a unit cell. With a 4×4-matrix technique, we derive analytic expressions for the normal modes of such a heterostructure slab, introduce the average refraction angles of the energy flow and wavevector for the TE- and TM-polarized plane waves falling obliquely on the slab, and derive expressions for the reflectivity and transmissivity of the whole slab. For a specific case, in which all layers in a unit cell are much thinner than the wavelength of light, we obtain approximate simple formulae for the effective refraction angles. Using the example of a semiconductor heterostructure slab with two layers in a unit cell, we demonstrate that ultrathin layers are preferable for metamaterial applications because they enable higher transmissivity within the frequency band of negative refraction. Our theory can be used to study the optical properties of any stratified metamaterial, irrespective of whether semiconductors or metals are employed for fabricating its various layers, because it includes absorption within each layer.

Organic solar cells with graded absorber layers processed from nanoparticle dispersions.

PubMed

Gärtner, Stefan; Reich, Stefan; Bruns, Michael; Czolk, Jens; Colsmann, Alexander

2016-03-28

The fabrication of organic solar cells with advanced multi-layer architectures from solution is often limited by the choice of solvents since most organic semiconductors dissolve in the same aromatic agents. In this work, we investigate multi-pass deposition of organic semiconductors from eco-friendly ethanol dispersion. Once applied, the nanoparticles are insoluble in the deposition agent, allowing for the application of further nanoparticulate layers and hence for building poly(3-hexylthiophene-2,5-diyl):indene-C60 bisadduct absorber layers with vertically graded polymer and conversely graded fullerene concentration. Upon thermal annealing, we observe some degrees of polymer/fullerene interdiffusion by means of X-ray photoelectron spectroscopy and Kelvin probe force microscopy. Replacing the common bulk-heterojunction by such a graded photo-active layer yields an enhanced fill factor of the solar cell due to an improved charge carrier extraction, and consequently an overall power conversion efficiency beyond 4%. Wet processing of such advanced device architectures paves the way for a versatile, eco-friendly and industrially feasible future fabrication of organic solar cells with advanced multi-layer architectures.

Band alignments in Fe/graphene/Si(001) junctions studied by x-ray photoemission spectroscopy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le Breton, J.-C., E-mail: jean-christophe.lebreton@univ-rennes1.fr; Tricot, S.; Delhaye, G.

2016-08-01

The control of tunnel contact resistance is of primary importance for semiconductor-based spintronic devices. This control is hardly achieved with conventional oxide-based tunnel barriers due to deposition-induced interface states. Manipulation of single 2D atomic crystals (such as graphene sheets) weakly interacting with their substrate might represent an alternative and efficient way to design new heterostructures for a variety of different purposes including spin injection into semiconductors. In the present paper, we study by x-ray photoemission spectroscopy the band alignments and interface chemistry of iron–graphene-hydrogenated passivated silicon (001) surfaces for a low and a high n-doping concentration. We find that themore » hydrogen passivation of the Si(001) surface remains efficient even with a graphene sheet on the Si(001) surface. For both doping concentrations, the semiconductor is close to flat-band conditions which indicates that the Fermi level is unpinned on the semiconductor side of the Graphene/Si(001):H interface. When iron is deposited on the graphene/Si(001):H structures, the Schottky barrier height remains mainly unaffected by the metallic overlayer with a very low barrier height for electrons, a sought-after property in semiconductor based spintronic devices. Finally, we demonstrate that the graphene layer intercalated between the metal and semiconductor also serves as a protection against iron-silicide formation even at elevated temperatures preventing from the formation of a Si-based magnetic dead layer.« less

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Band alignments in Fe/graphene/Si(001) junctions studied by x-ray photoemission spectroscopy

NASA Astrophysics Data System (ADS)

Le Breton, J.-C.; Tricot, S.; Delhaye, G.; Lépine, B.; Turban, P.; Schieffer, P.

2016-08-01

The control of tunnel contact resistance is of primary importance for semiconductor-based spintronic devices. This control is hardly achieved with conventional oxide-based tunnel barriers due to deposition-induced interface states. Manipulation of single 2D atomic crystals (such as graphene sheets) weakly interacting with their substrate might represent an alternative and efficient way to design new heterostructures for a variety of different purposes including spin injection into semiconductors. In the present paper, we study by x-ray photoemission spectroscopy the band alignments and interface chemistry of iron-graphene-hydrogenated passivated silicon (001) surfaces for a low and a high n-doping concentration. We find that the hydrogen passivation of the Si(001) surface remains efficient even with a graphene sheet on the Si(001) surface. For both doping concentrations, the semiconductor is close to flat-band conditions which indicates that the Fermi level is unpinned on the semiconductor side of the Graphene/Si(001):H interface. When iron is deposited on the graphene/Si(001):H structures, the Schottky barrier height remains mainly unaffected by the metallic overlayer with a very low barrier height for electrons, a sought-after property in semiconductor based spintronic devices. Finally, we demonstrate that the graphene layer intercalated between the metal and semiconductor also serves as a protection against iron-silicide formation even at elevated temperatures preventing from the formation of a Si-based magnetic dead layer.

Interlayer electron-hole pair multiplication by hot carriers in atomic layer semiconductor heterostructures

NASA Astrophysics Data System (ADS)

Barati, Fatemeh; Grossnickle, Max; Su, Shanshan; Lake, Roger; Aji, Vivek; Gabor, Nathaniel

Two-dimensional heterostructures composed of atomically thin transition metal dichalcogenides provide the opportunity to design novel devices for the study of electron-hole pair multiplication. We report on highly efficient multiplication of interlayer electron-hole pairs at the interface of a tungsten diselenide / molybdenum diselenide heterostructure. Electronic transport measurements of the interlayer current-voltage characteristics indicate that layer-indirect electron-hole pairs are generated by hot electron impact excitation. Our findings, which demonstrate an efficient energy relaxation pathway that competes with electron thermalization losses, make 2D semiconductor heterostructures viable for a new class of hot-carrier energy harvesting devices that exploit layer-indirect electron-hole excitations. SHINES, an Energy Frontier Research Center funded by the U.S. Department of Energy, Air Force Office of Scientific Research.

Substrate spacing and thin-film yield in chemical bath deposition of semiconductor thin films

NASA Astrophysics Data System (ADS)

Arias-Carbajal Reádigos, A.; García, V. M.; Gomezdaza, O.; Campos, J.; Nair, M. T. S.; Nair, P. K.

2000-11-01

Thin-film yield in the chemical bath deposition technique is studied as a function of separation between substrates in batch production. Based on a mathematical model, it is proposed and experimentally verified in the case of CdS thin films that the film thickness reaches an asymptotic maximum with increase in substrate separation. It is shown that at a separation less than 1 mm between substrates the yield, i.e. percentage in moles of a soluble cadmium salt deposited as a thin film of CdS, can exceed 50%. This behaviour is explained on the basis of the existence of a critical layer of solution near the substrate, within which the relevant ionic species have a higher probability of interacting with the thin-film layer than of contributing to precipitate formation. The critical layer depends on the solution composition and the temperature of the bath as well as the duration of deposition. An effective value for the critical layer thickness has been defined as half the substrate separation at which 90% of the maximum film thickness for the particular bath composition, bath temperature and duration of deposition is obtained. In the case of CdS thin films studied as an example, the critical layer is found to extend from 0.5 to 2.5 mm from the substrate surface, depending on the deposition conditions.

Structure for implementation of back-illuminated CMOS or CCD imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Cunningham, Thomas J. (Inventor)

2009-01-01

A structure for implementation of back-illuminated CMOS or CCD imagers. An epitaxial silicon layer is connected with a passivation layer, acting as a junction anode. The epitaxial silicon layer converts light passing through the passivation layer and collected by the imaging structure to photoelectrons. A semiconductor well is also provided, located opposite the passivation layer with respect to the epitaxial silicon layer, acting as a junction cathode. Prior to detection, light does not pass through a dielectric separating interconnection metal layers.

Internal Photoemission at Interaces of ALD TaiOx Insulating Layers Deposited on Si, InP and In0.53Ga0.47As

NASA Astrophysics Data System (ADS)

Chou, H. Y.; Afanas'ev, V. V.; Thoan, N. H.; Adelmann, C.; Lin, H. C.; Houssa, M.; Stesmans, A.

2012-12-01

Electrical analysis of interfaces of (100)Si, (100)InP, and (100)In0.53Ga0.47As with TaSiOx (Ta/Si≈1) films atomic-layer deposited using SiCl4, TaCl5, and H2O precursors suggests Ta silicate as a good insulating and surface passivating layer on all three semiconductors. However, when a positive voltage is applied to the top metal electrode in a metal/ TaSiOx /semiconductor configuration, considerable hysteresis of the capacitance-voltage curves, both at 300 and 77 K, is universally observed indicating electron injection and trapping in the insulator. To shed some light on the origin of this charge instability, we analyzed interface band alignment of the studied interfaces using the spectroscopies of internal photoemission and photoconductivity measurements. The latter reveals that independently of the semiconductor substrate material, TaSiOx layers exhibit a bandgap of only 4.5±0.1 eV, typical for a Ta2O5 network. The density of electron states associated with this narrow-gap network may account for the enhanced electron injection and trapping. Furthermore, while a sufficiently high energy barrier for electrons between Si and TaSiOx (3.1±0.1 eV) is found, much lower IPE thresholds are encountered at the (100)InP/TaSiOx and (100) In0.53Ga0.47As/TaSiOx interfaces, i.e., 2.4 and 2.0 eV, respectively. The lower barrier may be related by the formation of narrow-gap In-rich interlayers between AIIIBV semiconductors and TaSiOx.

Internal Photoemission at Interfaces of ALD TaSiOx Insulating Layers Deposited on Si, InP and In0.53Ga0.47As

NASA Astrophysics Data System (ADS)

Y Chou, H.; Afanas'ev, V. V.; Thoan, N. H.; Adelmann, C.; Lin, H. C.; Houssa, M.; Stesmans, A.

2012-10-01

Electrical analysis of interfaces of (100)Si, (100)InP, and (100)In0.53Ga0.47As with TaSiOx (Ta/Si≈1) films atomic-layer deposited using SiCl4, TaCl5, and H2O precursors suggests Ta silicate as a good insulating and surface passivating layer on all three semiconductors. However, when a positive voltage is applied to the top metal electrode in a metal/ TaSiOx /semiconductor configuration, considerable hysteresis of the capacitance-voltage curves, both at 300 and 77 K, is universally observed indicating electron injection and trapping in the insulator. To shed some light on the origin of this charge instability, we analyzed interface band alignment of the studied interfaces using the spectroscopies of internal photoemission and photoconductivity measurements. The latter reveals that independently of the semiconductor substrate material, TaSiOx layers exhibit a bandgap of only 4.5±0.1 eV, typical for a Ta2O5 network. The density of electron states associated with this narrow-gap network may account for the enhanced electron injection and trapping. Furthermore, while a sufficiently high energy barrier for electrons between Si and TaSiOx (3.1±0.1 eV) is found, much lower IPE thresholds are encountered at the (100)InP/TaSiOx and (100) In0.53Ga0.47As/TaSiOx interfaces, i.e., 2.4 and 2.0 eV, respectively. The lower barrier may be related by the formation of narrow-gap In-rich interlayers between AIIIBV semiconductors and TaSiOx.

MBE growth and processing of III/V-nitride semiconductor thin film structures: Growth of gallium indium arsenic nitride and nano-machining with focused ion beam and electron beam

NASA Astrophysics Data System (ADS)

Park, Yeonjoon

The advanced semiconductor material InGaAsN was grown with nitrogen plasma assisted Molecular Beam Epitaxy (MBE). The InGaAsN layers were characterized with High Resolution X-ray Diffraction (HRXDF), Atomic Fore Microscope (AFM), X-ray Photoemission Spectroscopy (XPS) and Photo-Luminescence (PL). The reduction of the band gap energy was observed with the incorporation of nitrogen and the lattice matched condition to the GaAs substrate was achieved with the additional incorporation of indium. A detailed investigation was made for the growth mode changes from planar layer-by-layer growth to 3D faceted growth with a higher concentration of nitrogen. A new X-ray diffraction analysis was developed and applied to the MBE growth on GaAs(111)B, which is one of the facet planes of InGaAsN. As an effort to enhance the processing tools for advanced semiconductor materials, gas assisted Focused Ion Beam (FIB) vertical milling was performed on GaN. The FIB processed area shows an atomically flat surface, which is good enough for the fabrication of Double Bragg Reflector (DBR) mirrors for the Blue GaN Vertical Cavity Surface Emitting Laser (VCSEL) Diodes. An in-situ electron beam system was developed to combine the enhanced lithographic processing capability with the atomic layer growth capability by MBE. The electron beam system has a compensation capability against substrate vibration and thermal drift. In-situ electron beam lithography was performed with the low pressure assisting gas. The advanced processing and characterization methods developed in this thesis will assist the development of superior semiconductor materials for the future.

Charged defects in two-dimensional semiconductors of arbitrary thickness and geometry: Formulation and application to few-layer black phosphorus

NASA Astrophysics Data System (ADS)

Wang, Dan; Han, Dong; Li, Xian-Bin; Chen, Nian-Ke; West, Damien; Meunier, Vincent; Zhang, Shengbai; Sun, Hong-Bo

2017-10-01

Energy evaluation of charged defects is tremendously important in two-dimensional (2D) semiconductors for the industrialization of 2D electronic devices because of its close relation with the corresponding type of conductivity and its strength. Although the method to calculate the energy of charged defects in single-layer one-atom-thick systems of equilateral unit-cell geometry has recently been proposed, few-layer 2D semiconductors are more common in device applications. As it turns out, one may not apply the one-layer formalism to multilayer cases without jeopardizing accuracy. Here, we generalize the approach to 2D systems of arbitrary cell geometry and thickness and use few-layer black phosphorus to illustrate how defect properties, mainly group-VI substitutional impurities, are affected. Within the framework of density functional theory, we show that substitutional Te (T eP) is the best candidate for n -type doping, and as the thickness increases, the ionization energy is found to decrease monotonically from 0.67 eV (monolayer) to 0.47 eV (bilayer) and further to 0.33 eV (trilayer). Although these results show the ineffectiveness of the dielectric screening at the monolayer limit, they also show how it evolves with increasing thickness whereby setting a new direction for the design of 2D electronics. The proposed method here is generally suitable to all the 2D materials regardless of their thickness and geometry.

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Jia, Yifan; Lv, Hongliang; Niu, Yingxi; Li, Ling; Song, Qingwen; Tang, Xiaoyan; Li, Chengzhan; Zhao, Yanli; Xiao, Li; Wang, Liangyong; Tang, Guangming; Zhang, Yimen; Zhang, Yuming

2016-09-01

The effect of nitric oxide (NO) annealing on charge traps in the oxide insulator and transition layer in n-type 4H-SiC metal-oxide-semiconductor (MOS) devices has been investigated using the time-dependent bias stress (TDBS), capacitance-voltage (C-V), and secondary ion mass spectroscopy (SIMS). It is revealed that two main categories of charge traps, near interface oxide traps (Nniot) and oxide traps (Not), have different responses to the TDBS and C-V characteristics in NO-annealed and Ar-annealed samples. The Nniot are mainly responsible for the hysteresis occurring in the bidirectional C-V characteristics, which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor. However, Not is mainly responsible for the TDBS induced C-V shifts. Electrons tunneling into the Not are hardly released quickly when suffering TDBS, resulting in the problem of the threshold voltage stability. Compared with the Ar-annealed sample, Nniot can be significantly suppressed by the NO annealing, but there is little improvement of Not. SIMS results demonstrate that the Nniot are distributed within the transition layer, which correlated with the existence of the excess silicon. During the NO annealing process, the excess Si atoms incorporate into nitrogen in the transition layer, allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot. Project supported by the National Natural Science Foundation of China (Grant Nos. 61404098 and 61274079), the Doctoral Fund of Ministry of Education of China (Grant No. 20130203120017), the National Key Basic Research Program of China (Grant No. 2015CB759600), the National Grid Science & Technology Project, China (Grant No. SGRI-WD-71-14-018), and the Key Specific Project in the National Science & Technology Program, China (Grant Nos. 2013ZX02305002-002 and 2015CB759600).

Mechanical scriber for semiconductor devices

DOEpatents

Lin, P.T.

1985-03-05

A mechanical scriber using a scribing tip, such as a diamond, provides controlled scriber forces with a spring-loaded compound lever arrangement. The scribing force and range of scribing depth are adjusted by a pair of adjustable micrometer heads. A semiconductor device, such as a multilayer solar cell, can be formed into scribed strips at each layer. 5 figs.

Hybrid method of making an amorphous silicon P-I-N semiconductor device

DOEpatents

Moustakas, Theodore D.; Morel, Don L.; Abeles, Benjamin

1983-10-04

The invention is directed to a hydrogenated amorphous silicon PIN semiconductor device of hybrid glow discharge/reactive sputtering fabrication. The hybrid fabrication method is of advantage in providing an ability to control the optical band gap of the P and N layers, resulting in increased photogeneration of charge carriers and device output.

Multilevel metallization method for fabricating a metal oxide semiconductor device

NASA Technical Reports Server (NTRS)

Hollis, B. R., Jr.; Feltner, W. R.; Bouldin, D. L.; Routh, D. E. (Inventor)

1978-01-01

An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield.

Mass sensing AlN sensors for waste water monitoring

NASA Astrophysics Data System (ADS)

Porrazzo, R.; Potter, G.; Lydecker, L.; Foraida, Z.; Gattu, S.; Tokranova, N.; Castracane, J.

2014-08-01

Monitoring the presence of nanomaterials in waste water from semiconductor facilities is a critical task for public health organizations. Advanced semiconductor technology allows the fabrication of sensitive piezoelectric-based mass sensors with a detection limit of less than 1.35 ng/cm2 of nanomaterials such as nanoparticles of alumina, amorphous silica, ceria, etc. The interactions between acoustic waves generated by the piezoelectric sensor and nanomaterial mass attached to its surface define the sensing response as a shift in the resonant frequency. In this article the development and characterization of a prototype AlN film bulk acoustic resonator (FBAR) are presented. DC reactive magnetron sputtering was used to create tilted c-axis oriented AlN films to generate shear waves which don't propagate in liquids thus minimizing the acoustic losses. The high acoustic velocity of AlN over quartz allows an increase in resonance frequency in comparison with a quartz crystal microbalance (QCM) and results in a higher frequency shift per mass change, and thus greater sensitivity. The membrane and electrodes were fabricated using state of the art semiconductor technology. The device surface functionalization was performed to demonstrate selectivity towards a specific nanomaterial. As a result, the devices were covered with a "docking" layer that allows the nanomaterials to be selectively attached to the surface. This was achieved using covalent modification of the surface, specifically targeting ZnO nanoparticles. Our functionalization approach was tested using two different types of nanoparticles, and binding specificity was confirmed with various analytical techniques.

Lateral amorphous selenium metal-insulator-semiconductor-insulator-metal photodetectors using ultrathin dielectric blocking layers for dark current suppression

NASA Astrophysics Data System (ADS)

Chang, Cheng-Yi; Pan, Fu-Ming; Lin, Jian-Siang; Yu, Tung-Yuan; Li, Yi-Ming; Chen, Chieh-Yang

2016-12-01

We fabricated amorphous selenium (a-Se) photodetectors with a lateral metal-insulator-semiconductor-insulator-metal (MISIM) device structure. Thermal aluminum oxide, plasma-enhanced chemical vapor deposited silicon nitride, and thermal atomic layer deposited (ALD) aluminum oxide and hafnium oxide (ALD-HfO2) were used as the electron and hole blocking layers of the MISIM photodetectors for dark current suppression. A reduction in the dark current by three orders of magnitude can be achieved at electric fields between 10 and 30 V/μm. The effective dark current suppression is primarily ascribed to electric field lowering in the dielectric layers as a result of charge trapping in deep levels. Photogenerated carriers in the a-Se layer can be transported across the blocking layers to the Al electrodes via Fowler-Nordheim tunneling because a high electric field develops in the ultrathin dielectric layers under illumination. Since the a-Se MISIM photodetectors have a very low dark current without significant degradation in the photoresponse, the signal contrast is greatly improved. The MISIM photodetector with the ALD-HfO2 blocking layer has an optimal signal contrast more than 500 times the contrast of the photodetector without a blocking layer at 15 V/μm.

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

PubMed Central

Rossi, Alessandro; Tanttu, Tuomo; Hudson, Fay E.; Sun, Yuxin; Möttönen, Mikko; Dzurak, Andrew S.

2015-01-01

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization. PMID:26067215

Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate

DOEpatents

Mazur, Eric [Concord, MA; Shen, Mengyan [Arlington, MA

2008-10-28

The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate

DOEpatents

Mazur, Eric; Shen, Mengyan

2015-09-15

The present invention generally provides semiconductor substrates having submicronsized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate

DOEpatents

Mazur, Eric , Shen; Mengyan, [Belmont, MA

2011-02-08

The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Efficient semiconductor light-emitting device and method

DOEpatents

Choquette, Kent D.; Lear, Kevin L.; Schneider, Jr., Richard P.

1996-01-01

A semiconductor light-emitting device and method. The semiconductor light-emitting device is provided with at least one control layer or control region which includes an annular oxidized portion thereof to channel an injection current into the active region, and to provide a lateral refractive index profile for index guiding the light generated within the device. A periodic composition grading of at least one of the mirror stacks in the device provides a reduced operating voltage of the device. The semiconductor light-emitting device has a high efficiency for light generation, and may be formed either as a resonant-cavity light-emitting diode (RCLED) or as a vertical-cavity surface-emitting laser (VCSEL).

Efficient semiconductor light-emitting device and method

DOEpatents

Choquette, K.D.; Lear, K.L.; Schneider, R.P. Jr.

1996-02-20

A semiconductor light-emitting device and method are disclosed. The semiconductor light-emitting device is provided with at least one control layer or control region which includes an annular oxidized portion thereof to channel an injection current into the active region, and to provide a lateral refractive index profile for index guiding the light generated within the device. A periodic composition grading of at least one of the mirror stacks in the device provides a reduced operating voltage of the device. The semiconductor light-emitting device has a high efficiency for light generation, and may be formed either as a resonant-cavity light-emitting diode (RCLED) or as a vertical-cavity surface-emitting laser (VCSEL). 12 figs.

Enhancing surface plasmon leakage at the metal/semiconductor interface: towards increased light outcoupling efficiency in organic optoelectronics.

PubMed

Kohl, Jesse; Pantina, Joseph A; O'Carroll, Deirdre M

2014-04-07

The light outcoupling efficiency of organic light-emitting optoelectronic devices is severely limited by excitation of tightly bound surface plasmon polaritons at the metal electrodes. We present a theoretical study of an organic semiconductor-silver-SiO(2) waveguide and demonstrate that by simple tuning of metal film thickness and the emission regime of the organic semiconductor, a significant fraction of surface plasmon polariton mode amplitude is leaked into the active semiconductor layer, thereby decreasing the amount of optical energy trapped by the metal. At visible wavelengths, mode leakage increases by factors of up to 3.8 and 88 by tuning metal film thickness and by addition of gain, respectively.

Silicon superlattices: Theory and application to semiconductor devices

NASA Technical Reports Server (NTRS)

Moriarty, J. A.

1981-01-01

Silicon superlattices and their applicability to improved semiconductor devices were studied. The device application potential of the atomic like dimension of III-V semiconductor superlattices fabricated in the form of ultrathin periodically layered heterostructures was examined. Whether this leads to quantum size effects and creates the possibility to alter familiar transport and optical properties over broad physical ranges was studied. Applications to improved semiconductor lasers and electrondevices were achieved. Possible application of silicon sperlattices to faster high speed computing devices was examined. It was found that the silicon lattices show features of smaller fundamental energyband gaps and reduced effective masses. The effects correlate strongly with both the chemical and geometrical nature of the superlattice.

Substrate solder barriers for semiconductor epilayer growth

DOEpatents

Drummond, Timothy J.; Ginley, David S.; Zipperian, Thomas E.

1989-01-01

During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

Substrate solder barriers for semiconductor epilayer growth

DOEpatents

Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

1989-05-09

During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

Substrate solder barriers for semiconductor epilayer growth

DOEpatents

Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

1987-10-23

During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In molecular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating. 1 tab.

Silicon Carbide Gas Sensors for Propulsion Emissions and Safety Applications

NASA Technical Reports Server (NTRS)

Hunter, G. W.; Xu, J.; Neudeck, P. G.; Lukco, D.; Trunek, A.; Spry, D.; Lampard, P.; Androjna, D.; Makel, D.; Ward, B.

2007-01-01

Silicon carbide (SiC) based gas sensors have the ability to meet the needs of a range of aerospace propulsion applications including emissions monitoring, leak detection, and hydrazine monitoring. These applications often require sensitive gas detection in a range of environments. An effective sensing approach to meet the needs of these applications is a Schottky diode based on a SiC semiconductor. The primary advantage of using SiC as a semiconductor is its inherent stability and capability to operate at a wide range of temperatures. The complete SiC Schottky diode gas sensing structure includes both the SiC semiconductor and gas sensitive thin film metal layers; reliable operation of the SiC-based gas sensing structure requires good control of the interface between these gas sensitive layers and the SiC. This paper reports on the development of SiC gas sensors. The focus is on two efforts to better control the SiC gas sensitive Schottky diode interface. First, the use of palladium oxide (PdOx) as a barrier layer between the metal and SiC is discussed. Second, the use of atomically flat SiC to provide an improved SiC semiconductor surface for gas sensor element deposition is explored. The use of SiC gas sensors in a multi-parameter detection system is briefly discussed. It is concluded that SiC gas sensors have potential in a range of propulsion system applications, but tailoring of the sensor for each application is necessary.

Better Ohmic Contacts For InP Semiconductor Devices

NASA Technical Reports Server (NTRS)

Weizer, Victor G.; Fatemi, Navid S.

1995-01-01

Four design modifications enable fabrication of improved ohmic contacts on InP-based semiconductor devices. First modification consists of insertion of layer of gold phosphide between n-doped InP and metal or other overlayer of contact material. Second, includes first modification plus use of particular metal overlayer to achieve very low contact resistivities. Third, also involves deposition of Au(2)P(3) interlayer; in addition, refractory metal (W or Ta) deposited to form contact overlayer. In fourth, contact layer of Auln alloy deposited directly on InP. Improved contacts exhibit low electrical resistances and fabricated without exposing devices to destructive predeposition or postdeposition treatments.

Quantum Confined Semiconductors for High Efficiency Photovoltaics

NASA Astrophysics Data System (ADS)

Beard, Matthew

2014-03-01

Semiconductor nanostructures, where at least one dimension is small enough to produce quantum confinement effects, provide new pathways for controlling energy flow and therefore have the potential to increase the efficiency of the primary photon-to-free energy conversion step. In this discussion, I will present the current status of research efforts towards utilizing the unique properties of colloidal quantum dots (NCs confined in three dimensions) in prototype solar cells and demonstrate that these unique systems have the potential to bypass the Shockley-Queisser single-junction limit for solar photon conversion. The solar cells are constructed using a low temperature solution based deposition of PbS or PbSe QDs as the absorber layer. Different chemical treatments of the QD layer are employed in order to obtain good electrical communication while maintaining the quantum-confined properties of the QDs. We have characterized the transport and carrier dynamics using a transient absorption, time-resolved THz, and temperature-dependent photoluminescence. I will discuss the interplay between carrier generation, recombination, and mobility within the QD layers. A unique aspect of our devices is that the QDs exhibit multiple exciton generation with an efficiency that is ~ 2 to 3 times greater than the parental bulk semiconductor.

Resistance change effect in SrTiO3/Si (001) isotype heterojunction

NASA Astrophysics Data System (ADS)

Huang, Xiushi; Gao, Zhaomeng; Li, Pei; Wang, Longfei; Liu, Xiansheng; Zhang, Weifeng; Guo, Haizhong

2018-02-01

Resistance switching has been observed in double and multi-layer structures of ferroelectric films. The higher switching ratio opens up a vast path for emerging ferroelectric semiconductor devices. An n-n+ isotype heterojunction has been fabricated by depositing an oxide SrTiO3 layer on a conventional n-type Si (001) substrate (SrTiO3/Si) by pulsed laser disposition. Rectification and resistive switching behaviors in the n-n+ SrTiO3/Si heterojunction were observed by a conductive atomic force microscopy, and the n-n+ SrTiO3/Si heterojunction exhibits excellent endurance and retention characteristics. The possible mechanism was proposed based on the band structure of the n-n+ SrTiO3/Si heterojunction, and the observed electrical behaviors could be attributed to the modulation effect of the electric field reversal on the width of accumulation and the depletion region, as well as the height of potential of the n-n+ junction formed at the STO/Si interface. Moreover, oxygen vacancies are also indicated to play a crucial role in causing insulator to semiconductor transition. These results open the way to potential application in future microelectronic devices based on perovskite oxide layers on conventional semiconductors.

Nanoimprinted Hybrid Metal-Semiconductor Plasmonic Multilayers with Controlled Surface Nano Architecture for Applications in NIR Detectors

PubMed Central

Khosroabadi, Akram A.; Gangopadhyay, Palash; Hernandez, Steven; Kim, Kyungjo; Peyghambarian, Nasser; Norwood, Robert A.

2015-01-01

We present a proof of concept for tunable plasmon resonance frequencies in a core shell nano-architectured hybrid metal-semiconductor multilayer structure, with Ag as the active shell and ITO as the dielectric modulation media. Our method relies on the collective change in the dielectric function within the metal semiconductor interface to control the surface. Here we report fabrication and optical spectroscopy studies of large-area, nanostructured, hybrid silver and indium tin oxide (ITO) structures, with feature sizes below 100 nm and a controlled surface architecture. The optical and electrical properties of these core shell electrodes, including the surface plasmon frequency, can be tuned by suitably changing the order and thickness of the dielectric layers. By varying the dimensions of the nanopillars, the surface plasmon wavelength of the nanopillar Ag can be tuned from 650 to 690 nm. Adding layers of ITO to the structure further shifts the resonance wavelength toward the IR region and, depending on the sequence and thickness of the layers within the structure, we show that such structures can be applied in sensing devices including enhancing silicon as a photodetection material. PMID:28793489

Integration of planar transformer and/or planar inductor with power switches in power converter

DOEpatents

Chen, Kanghua; Ahmed, Sayeed; Zhu, Lizhi

2007-10-30

A power converter integrates at least one planar transformer comprising a multi-layer transformer substrate and/or at least one planar inductor comprising a multi-layer inductor substrate with a number of power semiconductor switches physically and thermally coupled to a heat sink via one or more multi-layer switch substrates.

Solar cell with silicon oxynitride dielectric layer

DOEpatents

Shepherd, Michael; Smith, David D

2015-04-28

Solar cells with silicon oxynitride dielectric layers and methods of forming silicon oxynitride dielectric layers for solar cell fabrication are described. For example, an emitter region of a solar cell includes a portion of a substrate having a back surface opposite a light receiving surface. A silicon oxynitride (SiO.sub.xN.sub.y, 0

Spin-dependent transport phenomena in organic semiconductors

NASA Astrophysics Data System (ADS)

Bergeson, Jeremy D.

Thin-film organic semiconductors transport can have an anomalously high sensitivity to low magnetic fields. Such a response is unexpected considering that thermal fluctuation energies are greater than the energy associated with the intrinsic spin of charge carriers at a modest magnetic field of 100 Oe by a factor of more than 104 at room temperature and is still greater by 102 even at liquid helium temperatures. Nevertheless, we report experimental characterization of (1) spin-dependent injection, detection and transport of spin-polarized current through organic semiconductors and (2) the influence of a magnetic field on the spin dynamics of recombination-limited transport. The first focus of this work was accomplished by fabricating basic spin-valve devices consisting of two magnetic layers spatially separated by a nonmagnetic organic semiconductor. The spin-valve effect is a change in electrical resistance due to the magnetizations of the magnetic layers changing from parallel to antiparallel alignment, or vice versa. The conductivities of the metallic contacts and that of the semiconductor differed by many orders of magnitude, which inhibited the injection of a spin-polarized current from the magnet into the nonmagnet. We successfully overcame the problem of conductivity mismatch by inserting ultra-thin tunnel barriers at the metal/semiconductor interfaces which aided in yielding a ˜20% spin-valve effect at liquid helium temperatures and the effect persisted up to 150 K. We built on this achievement by constructing spin valves where one of the metallic contacts was replaced by the organic-based magnetic semiconductor vanadium tetracyanoethylene (V[TCNE]2). At 10 K these devices produced the switching behavior of the spin-valve effect. The second focus of this work was the bulk magnetoresistance (MR) of small molecule, oligomer and polymer organic semiconductors in thin-film structures. At room temperature the resistance can change up to 8% at 100 Oe and 15% at 1000 Oe. Depending on parameters such as temperature, layer thickness, or applied voltage, the resistance of these materials may increase or decrease as a function of field. A model for this phenomenon, termed magnetoresistance by the interconversion of singlets and triplets (MIST), is developed to account for this anomalous behavior. This model predicts that increasing the spin-orbit coupling in the organic semiconductor should decrease the magnitude of the MR. In an experiment where the small molecule Alq3 was doped with phosphorescent sensitizers, to increase the spin-orbit coupling, the MR was observed to decrease by an order of magnitude or more, depending on the doping. In addition to low-magnetic-field effects, we show the experimental observation of high-field MR in devices with and without magnetic contacts. To the best of our knowledge, we are the first to report (1) a tunnel-barrier-assisted spin-valve effect into an organic semiconductor using partially polarized metallic magnetic electrodes and (2) an experimental characterization of the central impact of the hyperfine interaction and spin-orbit coupling on MR in organic semiconductors.

Potential barrier heights at metal on oxygen-terminated diamond interfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muret, P., E-mail: pierre.muret@neel.cnrs.fr; Traoré, A.; Maréchal, A.

2015-11-28

Electrical properties of metal-semiconductor (M/SC) and metal/oxide/SC structures built with Zr or ZrO{sub 2} deposited on oxygen-terminated surfaces of (001)-oriented diamond films, comprised of a stack of lightly p-doped diamond on a heavily doped layer itself homoepitaxially grown on an Ib substrate, are investigated experimentally and compared to different models. In Schottky barrier diodes, the interfacial oxide layer evidenced by high resolution transmission electron microscopy and electron energy losses spectroscopy before and after annealing, and barrier height inhomogeneities accounts for the measured electrical characteristics until flat bands are reached, in accordance with a model which generalizes that by Tung [Phys.more » Rev. B 45, 13509 (1992)] and permits to extract physically meaningful parameters of the three kinds of interface: (a) unannealed ones, (b) annealed at 350 °C, (c) annealed at 450 °C with the characteristic barrier heights of 2.2–2.5 V in case (a) while as low as 0.96 V in case (c). Possible models of potential barriers for several metals deposited on well defined oxygen-terminated diamond surfaces are discussed and compared to experimental data. It is concluded that interface dipoles of several kinds present at these compound interfaces and their chemical evolution due to annealing are the suitable ingredients that are able to account for the Mott-Schottky behavior when the effect of the metal work function is ignored, and to justify the reverted slope observed regarding metal work function, in contrast to the trend always reported for all other metal-semiconductor interfaces.« less

Enhacement of intrafield overlay using a design based metrology system

NASA Astrophysics Data System (ADS)

Jo, Gyoyeon; Ji, Sunkeun; Kim, Shinyoung; Kang, Hyunwoo; Park, Minwoo; Kim, Sangwoo; Kim, Jungchan; Park, Chanha; Yang, Hyunjo; Maruyama, Kotaro; Park, Byungjun

2016-03-01

As the scales of the semiconductor devices continue to shrink, accurate measurement and control of the overlay have been emphasized for securing more overlay margin. Conventional overlay analysis methods are based on the optical measurement of the overlay mark. However, the overlay data obtained from these optical methods cannot represent the exact misregistration between two layers at the circuit level. The overlay mismatch may arise from the size or pitch difference between the overlay mark and the real pattern. Pattern distortion, caused by CMP or etching, could be a source of the overlay mismatch as well. Another issue is the overlay variation in the real circuit pattern which varies depending on its location. The optical overlay measurement methods, such as IBO and DBO that use overlay mark on the scribeline, are not capable of defining the exact overlay values of the real circuit. Therefore, the overlay values of the real circuit need to be extracted to integrate the semiconductor device properly. The circuit level overlay measurement using CDSEM is time-consuming in extracting enough data to indicate overall trend of the chip. However DBM tool is able to derive sufficient data to display overlay tendency of the real circuit region with high repeatability. An E-beam based DBM(Design Based Metrology) tool can be an alternative overlay measurement method. In this paper, we are going to certify that the overlay values extracted from optical measurement cannot represent the circuit level overlay values. We will also demonstrate the possibility to correct misregistration between two layers using the overlay data obtained from the DBM system.

Fabrication of ionic liquid electrodeposited Cu--Sn--Zn--S--Se thin films and method of making

DOEpatents

Bhattacharya, Raghu Nath

2016-01-12

A semiconductor thin-film and method for producing a semiconductor thin-films comprising a metallic salt, an ionic compound in a non-aqueous solution mixed with a solvent and processing the stacked layer in chalcogen that results in a CZTS/CZTSS thin films that may be deposited on a substrate is disclosed.

Sputtered pin amorphous silicon semi-conductor device and method therefor

DOEpatents

Moustakas, Theodore D.; Friedman, Robert A.

1983-11-22

A high efficiency amorphous silicon PIN semi-conductor device is constructed by the sequential sputtering of N, I and P layers of amorphous silicon and at least one semi-transparent ohmic electrode. A method of construction produces a PIN device, exhibiting enhanced physical integrity and facilitates ease of construction in a singular vacuum system and vacuum pump down procedure.

Tunable molecular orientation and elevated thermal stability of vapor-deposited organic semiconductors

PubMed Central

Walters, Diane M.; Lyubimov, Ivan; de Pablo, Juan J.; Ediger, M. D.

2015-01-01

Physical vapor deposition is commonly used to prepare organic glasses that serve as the active layers in light-emitting diodes, photovoltaics, and other devices. Recent work has shown that orienting the molecules in such organic semiconductors can significantly enhance device performance. We apply a high-throughput characterization scheme to investigate the effect of the substrate temperature (Tsubstrate) on glasses of three organic molecules used as semiconductors. The optical and material properties are evaluated with spectroscopic ellipsometry. We find that molecular orientation in these glasses is continuously tunable and controlled by Tsubstrate/Tg, where Tg is the glass transition temperature. All three molecules can produce highly anisotropic glasses; the dependence of molecular orientation upon substrate temperature is remarkably similar and nearly independent of molecular length. All three compounds form “stable glasses” with high density and thermal stability, and have properties similar to stable glasses prepared from model glass formers. Simulations reproduce the experimental trends and explain molecular orientation in the deposited glasses in terms of the surface properties of the equilibrium liquid. By showing that organic semiconductors form stable glasses, these results provide an avenue for systematic performance optimization of active layers in organic electronics. PMID:25831545

HfSe2 and ZrSe2: Two-dimensional semiconductors with native high-κ oxides

PubMed Central

Mleczko, Michal J.; Zhang, Chaofan; Lee, Hye Ryoung; Kuo, Hsueh-Hui; Magyari-Köpe, Blanka; Moore, Robert G.; Shen, Zhi-Xun; Fisher, Ian R.; Nishi, Yoshio; Pop, Eric

2017-01-01

The success of silicon as a dominant semiconductor technology has been enabled by its moderate band gap (1.1 eV), permitting low-voltage operation at reduced leakage current, and the existence of SiO2 as a high-quality “native” insulator. In contrast, other mainstream semiconductors lack stable oxides and must rely on deposited insulators, presenting numerous compatibility challenges. We demonstrate that layered two-dimensional (2D) semiconductors HfSe2 and ZrSe2 have band gaps of 0.9 to 1.2 eV (bulk to monolayer) and technologically desirable “high-κ” native dielectrics HfO2 and ZrO2, respectively. We use spectroscopic and computational studies to elucidate their electronic band structure and then fabricate air-stable transistors down to three-layer thickness with careful processing and dielectric encapsulation. Electronic measurements reveal promising performance (on/off ratio > 106; on current, ~30 μA/μm), with native oxides reducing the effects of interfacial traps. These are the first 2D materials to demonstrate technologically relevant properties of silicon, in addition to unique compatibility with high-κ dielectrics, and scaling benefits from their atomically thin nature. PMID:28819644

More Efficient Power Conversion for EVs: Gallium-Nitride Advanced Power Semiconductor and Packaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2010-02-01

Broad Funding Opportunity Announcement Project: Delphi is developing power converters that are smaller and more energy efficient, reliable, and cost-effective than current power converters. Power converters rely on power transistors which act like a very precisely controlled on-off switch, controlling the electrical energy flowing through an electrical circuit. Most power transistors today use silicon (Si) semiconductors. However, Delphi is using semiconductors made with a thin layer of gallium-nitride (GaN) applied on top of the more conventional Si material. The GaN layer increases the energy efficiency of the power transistor and also enables the transistor to operate at much higher temperatures,more » voltages, and power-density levels compared to its Si counterpart. Delphi is packaging these high-performance GaN semiconductors with advanced electrical connections and a cooling system that extracts waste heat from both sides of the device to further increase the device’s efficiency and allow more electrical current to flow through it. When combined with other electronic components on a circuit board, Delphi’s GaN power transistor package will help improve the overall performance and cost-effectiveness of HEVs and EVs.« less

3D Band Diagram and Photoexcitation of 2D-3D Semiconductor Heterojunctions.

PubMed

Li, Bo; Shi, Gang; Lei, Sidong; He, Yongmin; Gao, Weilu; Gong, Yongji; Ye, Gonglan; Zhou, Wu; Keyshar, Kunttal; Hao, Ji; Dong, Pei; Ge, Liehui; Lou, Jun; Kono, Junichiro; Vajtai, Robert; Ajayan, Pulickel M

2015-09-09

The emergence of a rich variety of two-dimensional (2D) layered semiconductor materials has enabled the creation of atomically thin heterojunction devices. Junctions between atomically thin 2D layers and 3D bulk semiconductors can lead to junctions that are fundamentally electronically different from the covalently bonded conventional semiconductor junctions. Here we propose a new 3D band diagram for the heterojunction formed between n-type monolayer MoS2 and p-type Si, in which the conduction and valence band-edges of the MoS2 monolayer are drawn for both stacked and in-plane directions. This new band diagram helps visualize the flow of charge carriers inside the device in a 3D manner. Our detailed wavelength-dependent photocurrent measurements fully support the diagrams and unambiguously show that the band alignment is type I for this 2D-3D heterojunction. Photogenerated electron-hole pairs in the atomically thin monolayer are separated and driven by an external bias and control the "on/off" states of the junction photodetector device. Two photoresponse regimes with fast and slow relaxation are also revealed in time-resolved photocurrent measurements, suggesting the important role played by charge trap states.

Thin film heterojunction photovoltaic cells and methods of making the same

DOEpatents

Basol, Bulent M.; Tseng, Eric S.; Rod, Robert L.

1983-06-14

A method of fabricating a thin film heterojunction photovoltaic cell which comprises depositing a film of a near intrinsic or n-type semiconductor compound formed of at least one of the metal elements of Class II B of the Periodic Table of Elements and at least tellurium and then heating said film at a temperature between about 250.degree. C. and 500.degree. C. for a time sufficient to convert said film to a suitably low resistivity p-type semiconductor compound. Such film may be deposited initially on the surface of an n-type semiconductor substrate. Alternatively, there may be deposited on the converted film a layer of n-type semiconductor compound different from the film semiconductor compound. The resulting photovoltaic cell exhibits a substantially increased power output over similar cells not subjected to the method of the present invention.

Electric Circuit Model Analogy for Equilibrium Lattice Relaxation in Semiconductor Heterostructures

NASA Astrophysics Data System (ADS)

Kujofsa, Tedi; Ayers, John E.

2018-01-01

The design and analysis of semiconductor strained-layer device structures require an understanding of the equilibrium profiles of strain and dislocations associated with mismatched epitaxy. Although it has been shown that the equilibrium configuration for a general semiconductor strained-layer structure may be found numerically by energy minimization using an appropriate partitioning of the structure into sublayers, such an approach is computationally intense and non-intuitive. We have therefore developed a simple electric circuit model approach for the equilibrium analysis of these structures. In it, each sublayer of an epitaxial stack may be represented by an analogous circuit configuration involving an independent current source, a resistor, an independent voltage source, and an ideal diode. A multilayered structure may be built up by the connection of the appropriate number of these building blocks, and the node voltages in the analogous electric circuit correspond to the equilibrium strains in the original epitaxial structure. This enables analysis using widely accessible circuit simulators, and an intuitive understanding of electric circuits can easily be extended to the relaxation of strained-layer structures. Furthermore, the electrical circuit model may be extended to continuously-graded epitaxial layers by considering the limit as the individual sublayer thicknesses are diminished to zero. In this paper, we describe the mathematical foundation of the electrical circuit model, demonstrate its application to several representative structures involving In x Ga1- x As strained layers on GaAs (001) substrates, and develop its extension to continuously-graded layers. This extension allows the development of analytical expressions for the strain, misfit dislocation density, critical layer thickness and widths of misfit dislocation free zones for a continuously-graded layer having an arbitrary compositional profile. It is similar to the transition from circuit theory, using lumped circuit elements, to electromagnetics, using distributed electrical quantities. We show this development using first principles, but, in a more general sense, Maxwell's equations of electromagnetics could be applied.