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Science.gov Websites

SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing (ERC ) ** Bringing Sustainability to Semiconductor Manufacturing ** A multi-university research center leading the way to environmentally friendly semiconductor manufacturing, sponsored by the Semiconductor Research

George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

NASA Astrophysics Data System (ADS)

Doering, Robert

In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

NASA Astrophysics Data System (ADS)

Almuslem, A. S.; Hanna, A. N.; Yapici, T.; Wehbe, N.; Diallo, E. M.; Kutbee, A. T.; Bahabry, R. R.; Hussain, M. M.

2017-02-01

In the recent past, with the advent of transient electronics for mostly implantable and secured electronic applications, the whole field effect transistor structure has been dissolved in a variety of chemicals. Here, we show simple water soluble nano-scale (sub-10 nm) germanium oxide (GeO2) as the dissolvable component to remove the functional structures of metal oxide semiconductor devices and then reuse the expensive germanium substrate again for functional device fabrication. This way, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured and billions are disposed, which extend the harmful impact to our environment. Therefore, this is a key study to show a pragmatic approach for water soluble high performance electronics for environmentally friendly manufacturing and bioresorbable electronic applications.

Semiconductors: In Situ Processing of Photovoltaic Devices

NASA Technical Reports Server (NTRS)

Curreri, Peter A.

1998-01-01

The possible processing of semiconductor photovoltaic devices is discussed. The requirements for lunar PV cells is reviewed, and the key challenges involved in their manufacturing are investigated. A schematic diagram of a passivated emitter and rear cell (PERC) is presented. The possible fabrication of large photovoltaic arrays in space from lunar materials is also discussed.

Abatement of waste gases and water during the processes of semiconductor fabrication.

PubMed

Wen, Rui-mei; Liang, Jun-wu

2002-10-01

The purpose of this article is to examine the methods and equipment for abating waste gases and water produced during the manufacture of semiconductor materials and devices. Three separating methods and equipment are used to control three different groups of electronic wastes. The first group includes arsine and phosphine emitted during the processes of semiconductor materials manufacture. The abatement procedure for this group of pollutants consists of adding iodates, cupric and manganese salts to a multiple shower tower (MST) structure. The second group includes pollutants containing arsenic, phosphorus, HF, HCl, NO2, and SO3 emitted during the manufacture of semiconductor materials and devices. The abatement procedure involves mixing oxidants and bases in an oval column with a separator in the middle. The third group consists of the ions of As, P and heavy metals contained in the waste water. The abatement procedure includes adding CaCO3 and ferric salts in a flocculation-sedimentation compact device equipment. Test results showed that all waste gases and water after the abatement procedures presented in this article passed the discharge standards set by the State Environmental Protection Administration of China.

Cost of ownership for inspection equipment

NASA Astrophysics Data System (ADS)

Dance, Daren L.; Bryson, Phil

1993-08-01

Cost of Ownership (CoO) models are increasingly a part of the semiconductor equipment evaluation and selection process. These models enable semiconductor manufacturers and equipment suppliers to quantify a system in terms of dollars per wafer. Because of the complex nature of the semiconductor manufacturing process, there are several key attributes that must be considered in order to accurately reflect the true 'cost of ownership'. While most CoO work to date has been applied to production equipment, the need to understand cost of ownership for inspection and metrology equipment presents unique challenges. Critical parameters such as detection sensitivity as a function of size and type of defect are not included in current CoO models yet are, without question, major factors in the technical evaluation process and life-cycle cost. This paper illustrates the relationship between these parameters, as components of the alpha and beta risk, and cost of ownership.

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

NASA Technical Reports Server (NTRS)

Bouldin, D. L.; Eastes, R. W.; Feltner, W. R.; Hollis, B. R.; Routh, D. E.

1979-01-01

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

78 FR 51737 - Notice of Issuance of Final Determination Concerning Certain Hard Disk Drives and Self-Encrypting...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-21

... the HDA incorporate semiconductor, magnetic, mechanical, and manufacturing process design into an..., mechanical surface design and manufacturing process design. It takes approximately [xxx] hours to design... brand names ``Barracuda'' and ``Desktop''. HDDs are designed in the United States and assembled either...

Method of Manufacturing a Light Emitting, Photovoltaic or Other Electronic Apparatus and System

NASA Technical Reports Server (NTRS)

Blanchard, Richard A. (Inventor); Lewandowski, Mark Allan (Inventor); Frazier, Donald Odell (Inventor); Ray, William Johnstone (Inventor); Fuller, Kirk A. (Inventor); Lowenthal, Mark David (Inventor); Shotton, Neil O. (Inventor)

2014-01-01

The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

Method of manufacturing a light emitting, photovoltaic or other electronic apparatus and system

NASA Technical Reports Server (NTRS)

Fuller, Kirk A. (Inventor); Frazier, Donald Odell (Inventor); Blanchard, Richard A. (Inventor); Lowenthal, Mark D. (Inventor); Lewandowski, Mark Allan (Inventor); Ray, William Johnstone (Inventor); Shotton, Neil O. (Inventor)

2012-01-01

The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

NASA Astrophysics Data System (ADS)

Singh, Anil; Agarwal, Alpana

2016-10-01

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

A stable solution-processed polymer semiconductor with record high-mobility for printed transistors

PubMed Central

Li, Jun; Zhao, Yan; Tan, Huei Shuan; Guo, Yunlong; Di, Chong-An; Yu, Gui; Liu, Yunqi; Lin, Ming; Lim, Suo Hon; Zhou, Yuhua; Su, Haibin; Ong, Beng S.

2012-01-01

Microelectronic circuits/arrays produced via high-speed printing instead of traditional photolithographic processes offer an appealing approach to creating the long-sought after, low-cost, large-area flexible electronics. Foremost among critical enablers to propel this paradigm shift in manufacturing is a stable, solution-processable, high-performance semiconductor for printing functionally capable thin-film transistors — fundamental building blocks of microelectronics. We report herein the processing and optimisation of solution-processable polymer semiconductors for thin-film transistors, demonstrating very high field-effect mobility, high on/off ratio, and excellent shelf-life and operating stabilities under ambient conditions. Exceptionally high-gain inverters and functional ring oscillator devices on flexible substrates have been demonstrated. This optimised polymer semiconductor represents a significant progress in semiconductor development, dispelling prevalent skepticism surrounding practical usability of organic semiconductors for high-performance microelectronic devices, opening up application opportunities hitherto functionally or economically inaccessible with silicon technologies, and providing an excellent structural framework for fundamental studies of charge transport in organic systems. PMID:23082244

Flat-plate solar array project: Experimental process system development unit for producing semiconductor-grade silicon using the silane-to-silicon process

NASA Technical Reports Server (NTRS)

1983-01-01

The process technology for the manufacture of semiconductor-grade silicon in a large commercial plant by 1986, at a price less than $14 per kilogram of silicon based on 1975 dollars is discussed. The engineering design, installation, checkout, and operation of an Experimental Process System Development unit was discussed. Quality control of scaling-up the process and an economic analysis of product and production costs are discussed.

Using the scanning electron microscope on the production line to assure quality semiconductors

NASA Technical Reports Server (NTRS)

Adolphsen, J. W.; Anstead, R. J.

1972-01-01

The use of the scanning electron microscope to detect metallization defects introduced during batch processing of semiconductor devices is discussed. A method of determining metallization integrity was developed which culminates in a procurement specification using the scanning microscope on the production line as a quality control tool. Batch process control of the metallization operation is monitored early in the manufacturing cycle.

Productivity improvement through industrial engineering in the semiconductor industry

NASA Astrophysics Data System (ADS)

Meyersdorf, Doron

1996-09-01

Industrial Engineering is fairly new to the semiconductor industry, though the awareness to its importance has increased in recent years. The US semiconductor industry in particular has come to the realization that in order to remain competitive in the global market it must take the lead not only in product development but also in manufacturing. Industrial engineering techniques offer one ofthe most effective strategies for achieving manufacturing excellence. Industrial engineers play an important role in the success of the manufacturing facility. This paper defines the Industrial engineers role in the IC facility, set the visions of excellence in semiconductor manufacturing and highlights 10 roadblocks on the journey towards manufacturing excellence.

X-ray topography as a process control tool in semiconductor and microcircuit manufacture

NASA Technical Reports Server (NTRS)

Parker, D. L.; Porter, W. A.

1977-01-01

A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.

78 FR 21344 - Grant of Authority for Subzone Status, Hemlock Semiconductor Corporation, (Polysilicon), Hemlock...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-10

... Status, Hemlock Semiconductor Corporation, (Polysilicon), Hemlock, Michigan Pursuant to its authority... polysilicon manufacturing facility of Hemlock Semiconductor Corporation, located in Hemlock, Michigan (FTZ... manufacturing of polysilicon at the facility of Hemlock Semiconductor Corporation, located in Hemlock, Michigan...

A system approach for reducing the environmental impact of manufacturing and sustainability improvement of nano-scale manufacturing

NASA Astrophysics Data System (ADS)

Yuan, Yingchun

This dissertation develops an effective and economical system approach to reduce the environmental impact of manufacturing. The system approach is developed by using a process-based holistic method for upstream analysis and source reduction of the environmental impact of manufacturing. The system approach developed consists of three components of a manufacturing system: technology, energy and material, and is useful for sustainable manufacturing as it establishes a clear link between manufacturing system components and its overall sustainability performance, and provides a framework for environmental impact reductions. In this dissertation, the system approach developed is applied for environmental impact reduction of a semiconductor nano-scale manufacturing system, with three case scenarios analyzed in depth on manufacturing process improvement, clean energy supply, and toxic chemical material selection. The analysis on manufacturing process improvement is conducted on Atomic Layer Deposition of Al2O3 dielectric gate on semiconductor microelectronics devices. Sustainability performance and scale-up impact of the ALD technology in terms of environmental emissions, energy consumption, nano-waste generation and manufacturing productivity are systematically investigated and the ways to improve the sustainability of the ALD technology are successfully developed. The clean energy supply is studied using solar photovoltaic, wind, and fuel cells systems for electricity generation. Environmental savings from each clean energy supply over grid power are quantitatively analyzed, and costs for greenhouse gas reductions on each clean energy supply are comparatively studied. For toxic chemical material selection, an innovative schematic method is developed as a visual decision tool for characterizing and benchmarking the human health impact of toxic chemicals, with a case study conducted on six chemicals commonly used as solvents in semiconductor manufacturing. Reliability of the schematic method is validated by comparing its benchmark results on 104 chemicals with that from the conventional Human Toxicity Potential (HTP) method. This dissertation concludes with discussions on environmental impact assessment of nanotechnologies and sustainability management of nano-particles. As nano-manufacturing is emerging for wide industrial applications, improvement and expansion of the system approach would be valuable for use in the environmental management of nano-manufacturing and in the risk control of nano-particles in the interests of public health and the environment.

Photo-Spectrometer Realized In A Standard Cmos Ic Process

DOEpatents

Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

1999-10-12

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Productivity improvement through industrial engineering in the semiconductor industry

NASA Astrophysics Data System (ADS)

Meyersdorf, Doron

1996-09-01

Industrial engineering is fairly new to the semiconductor industry, though the awareness to its importance has increased in recent years. The U.S. semiconductor industry in particular has come to the realization that in order to remain competitive in the global market it must take the lead not only in product development but also in manufacturing. Industrial engineering techniques offer one of the most effective strategies for achieving manufacturing excellence. Industrial engineers play an important role in the success of the manufacturing facility. This paper defines the industrial engineers role in the IC facility, sets the visions of excellence in semiconductor manufacturing and highlights 10 roadblocks on the journey towards manufacturing excellence.

In-Line Detection and Measurement of Molecular Contamination in Semiconductor Process Solutions

NASA Astrophysics Data System (ADS)

Wang, Jason; West, Michael; Han, Ye; McDonald, Robert C.; Yang, Wenjing; Ormond, Bob; Saini, Harmesh

2005-09-01

This paper discusses a fully automated metrology tool for detection and quantitative measurement of contamination, including cationic, anionic, metallic, organic, and molecular species present in semiconductor process solutions. The instrument is based on an electrospray ionization time-of-flight mass spectrometer (ESI-TOF/MS) platform. The tool can be used in diagnostic or analytical modes to understand process problems in addition to enabling routine metrology functions. Metrology functions include in-line contamination measurement with near real-time trend analysis. This paper discusses representative organic and molecular contamination measurement results in production process problem solving efforts. The examples include the analysis and identification of organic compounds in SC-1 pre-gate clean solution; urea, NMP (N-Methyl-2-pyrrolidone) and phosphoric acid contamination in UPW; and plasticizer and an organic sulfur-containing compound found in isopropyl alcohol (IPA). It is expected that these unique analytical and metrology capabilities will improve the understanding of the effect of organic and molecular contamination on device performance and yield. This will permit the development of quantitative correlations between contamination levels and process degradation. It is also expected that the ability to perform routine process chemistry metrology will lead to corresponding improvements in manufacturing process control and yield, the ability to avoid excursions and will improve the overall cost effectiveness of the semiconductor manufacturing process.

Timothy Remo | NREL

Science.gov Websites

Analysis Center. Areas of Expertise Photovoltaic and semiconductor manufacturing cost analysis Process , Norcross, GA (2011-2015) Production Engineer, Emcore Photovoltaic Corp, Albuquerque, NM (2008-2010

Pacifichem 2000 Symposium on Plasma Chemistry and Technology for Green Manufacturing, Pollution Control and Processing Applications

DTIC Science & Technology

2001-03-19

Plasma chemistry and technology represents a significant advance and improvement for green manufacturing, pollution control, and various processing...December 14-19, 2000 in Honolulu, HI. This Congress consists of over 120 symposia. amongst them the Symposium on Plasma Chemistry and Technology for...in the plasma chemistry many field beyond the more traditional and mature fields of semiconductor and materials processing. This symposium was focus on

Progress in ion torrent semiconductor chip based sequencing.

PubMed

Merriman, Barry; Rothberg, Jonathan M

2012-12-01

In order for next-generation sequencing to become widely used as a diagnostic in the healthcare industry, sequencing instrumentation will need to be mass produced with a high degree of quality and economy. One way to achieve this is to recast DNA sequencing in a format that fully leverages the manufacturing base created for computer chips, complementary metal-oxide semiconductor chip fabrication, which is the current pinnacle of large scale, high quality, low-cost manufacturing of high technology. To achieve this, ideally the entire sensory apparatus of the sequencer would be embodied in a standard semiconductor chip, manufactured in the same fab facilities used for logic and memory chips. Recently, such a sequencing chip, and the associated sequencing platform, has been developed and commercialized by Ion Torrent, a division of Life Technologies, Inc. Here we provide an overview of this semiconductor chip based sequencing technology, and summarize the progress made since its commercial introduction. We described in detail the progress in chip scaling, sequencing throughput, read length, and accuracy. We also summarize the enhancements in the associated platform, including sample preparation, data processing, and engagement of the broader development community through open source and crowdsourcing initiatives. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Method for anisotropic etching in the manufacture of semiconductor devices

NASA Technical Reports Server (NTRS)

Koontz, Steven L. (Inventor); Cross, Jon B. (Inventor)

1993-01-01

Hydrocarbon polymer coatings used in microelectronic manufacturing processes are anisotropically etched by hyperthermal atomic oxygen beams (translational energies of 0.2 to 20 eV, preferably 1 to 10 eV). Etching with hyperthermal oxygen atom species obtains highly anisotropic etching with sharp boundaries between etched and mask protected areas.

Method for anisotropic etching in the manufacture of semiconductor devices

DOEpatents

Koontz, Steven L.; Cross, Jon B.

1993-01-01

Hydrocarbon polymer coatings used in microelectronic manufacturing processes are anisotropically etched by atomic oxygen beams (translational energies of 0.2-20 eV, preferably 1-10 eV). Etching with hyperthermal (kinetic energy>1 eV) oxygen atom species obtains highly anisotropic etching with sharp boundaries between etched and mask-protected areas.

Cameras for semiconductor process control

NASA Technical Reports Server (NTRS)

Porter, W. A.; Parker, D. L.

1977-01-01

The application of X-ray topography to semiconductor process control is described, considering the novel features of the high speed camera and the difficulties associated with this technique. The most significant results on the effects of material defects on device performance are presented, including results obtained using wafers processed entirely within this institute. Defects were identified using the X-ray camera and correlations made with probe data. Also included are temperature dependent effects of material defects. Recent applications and improvements of X-ray topographs of silicon-on-sapphire and gallium arsenide are presented with a description of a real time TV system prototype and of the most recent vacuum chuck design. Discussion is included of our promotion of the use of the camera by various semiconductor manufacturers.

MEDEA+ project 2T302 MUSCLE: masks through user's supply chain: leadership by excellence

NASA Astrophysics Data System (ADS)

Torsy, Andreas

2008-04-01

The rapid evolution of our information society depends on the continuous developments and innovations of semiconductor products. The cost per chip functionality keeps reducing by a factor of 2 every 18 month. However, this performance and success of the semiconductor industry critically depends on the quality of the lithographic photomasks. The need for the high quality of photomask drives lithography costs sensitively, which is a key factor in the manufacture of microelectronics devices. Therefore, the aim is to reduce production costs while overcoming challenges in terms of feature sizes, complexity and cycle times. Consequently, lithography processes must provide highest possible quality at reasonable prices. This way, the leadership in the lithographic area can be maintained and European chipmakers can stay competitive with manufacturers in the Far East and the USA. Under the umbrella of MEDEA+, a project called MUSCLE (<< Masks through User's Supply Chain: Leadership by Excellence >>) has been started among leading semiconductor companies in Europe: ALTIS Semiconductor (Project Leader), ALCATEL Vacuum, ATMEL, CEA/LETI, Entegris, NXP Semiconductors, TOPPAN Photomasks, AMTC, Carl ZEISS SMS, DMS, Infineon Technologies, VISTEC Semiconductor, NIKON Precision, SCHOTT Lithotec, ASML, PHOTRONICS, IMEC, DCE, DNP Photomask, STMicroelectronics, XYALIS and iCADA. MUSCLE focuses particularly on mask data flow, photomask carrier, photomask defect characterization and photomask data handling. In this paper, we will discuss potential solutions like standardization and automation of the photomask data flow based on SEMI P10, the performance and the impact of the supply chain parameter within the photomask process, the standardization of photomask defect characterization and a discussion of the impact of new Reticle Enhancement Technologies (RET) such as mask process correction and finally a generic model to describe the photomasks key performance indicators for prototype photomasks.

Estimates of occupational safety and health impacts resulting from large-scale production of major photovoltaic technologies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Owens, T.; Ungers, L.; Briggs, T.

1980-08-01

The purpose of this study is to estimate both quantitatively and qualitatively, the worker and societal risks attributable to four photovoltaic cell (solar cell) production processes. Quantitative risk values were determined by use of statistics from the California semiconductor industry. The qualitative risk assessment was performed using a variety of both governmental and private sources of data. The occupational health statistics derived from the semiconductor industry were used to predict injury and fatality levels associated with photovoltaic cell manufacturing. The use of these statistics to characterize the two silicon processes described herein is defensible from the standpoint that many ofmore » the same process steps and materials are used in both the semiconductor and photovoltaic industries. These health statistics are less applicable to the gallium arsenide and cadmium sulfide manufacturing processes, primarily because of differences in the materials utilized. Although such differences tend to discourage any absolute comparisons among the four photovoltaic cell production processes, certain relative comparisons are warranted. To facilitate a risk comparison of the four processes, the number and severity of process-related chemical hazards were assessed. This qualitative hazard assessment addresses both the relative toxicity and the exposure potential of substances in the workplace. In addition to the worker-related hazards, estimates of process-related emissions and wastes are also provided.« less

Exposure Characteristics of Nanoparticles as Process By-products for the Semiconductor Manufacturing Industry.

PubMed

Choi, Kwang-Min; Kim, Jin-Ho; Park, Ju-Hyun; Kim, Kwan-Sick; Bae, Gwi-Nam

2015-01-01

This study aims to elucidate the exposure properties of nanoparticles (NPs; <100 nm in diameter) in semiconductor manufacturing processes. The measurements of airborne NPs were mainly performed around process equipment during fabrication processes and during maintenance. The number concentrations of NPs were measured using a water-based condensation particle counter having a size range of 10-3,000 nm. The chemical composition, size, and shape of NPs were determined by scanning electron microscopy and transmission electron microscopy techniques equipped with energy dispersive spectroscopy. The resulting concentrations of NPs ranged from 0.00-11.47 particles/cm(3). The concentration of NPs measured during maintenance showed a tendency to increase, albeit incrementally, compared to that measured during normal conditions (under typical process conditions without maintenance). However, the increment was small. When comparing the mean number concentration and standard deviation (n ± σ) of NPs, the chemical mechanical polishing (CMP) process was the highest (3.45 ± 3.65 particles/cm(3)), and the dry etch (ETCH) process was the lowest (0.11 ± 0.22 particles/cm(3)). The major NPs observed were silica (SiO2) and titania (TiO2) particles, which were mainly spherical agglomerates ranging in size from 25-280 nm. Sampling of semiconductor processes in CMP, chemical vapor deposition, and ETCH reveled NPs were <100 nm in those areas. On the other hand, particle size exceeded 100 nm in diffusion, metallization, ion implantation, and wet cleaning/etching process. The results show that the SiO2 and TiO2 are the major NPs present in semiconductor cleanroom environments.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, Arthur W.; Ellingboe, Albert R.

1998-01-01

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18-0.35 mm or less.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, A.W.; Ellingboe, A.R.

1998-10-20

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18--0.35 mm or less. 16 figs.

Semiconductor Manufacturing Comes to Virginia: Developing Partnerships for Workforce Education and Training.

ERIC Educational Resources Information Center

Cantor, Jeffrey A.

1998-01-01

In Virginia, a community college consortium for semiconductor education and training programs works with a semiconductor manufacturers' partnership to review programs based on a national core curriculum model. The results are being used to improve curriculum development, faculty training, facility improvement, and student recruitment. (SK)

77 FR 37900 - Agency Information Collection Activities; Submission to OMB for Review and Approval; Comment...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-25

... Activities; Submission to OMB for Review and Approval; Comment Request; NESHAP for Semiconductor...: NESHAP for Semiconductor Manufacturing (Renewal). ICR Numbers: EPA ICR Number 2042.05, OMB Control Number... the owners or operators of semiconductor manufacturing plants. Estimated Number of Respondents: 1...

Semiconductor with protective surface coating and method of manufacture thereof. [Patent application

DOEpatents

Hansen, W.L.; Haller, E.E.

1980-09-19

Passivation of predominantly crystalline semiconductor devices is provided for by a surface coating of sputtered hydrogenated amorphous semiconductor material. Passivation of a radiation detector germanium diode, for example, is realized by sputtering a coating of amorphous germanium onto the etched and quenched diode surface in a low pressure atmosphere of hydrogen and argon. Unlike prior germanium diode semiconductor devices, which must be maintained in vacuum at cryogenic temperatures to avoid deterioration, a diode processed in the described manner may be stored in air at room temperature or otherwise exposed to a variety of environmental conditions. The coating compensates for pre-existing undesirable surface states as well as protecting the semiconductor device against future impregnation with impurities.

Plasma Diagnostics: Use and Justification in an Industrial Environment

NASA Astrophysics Data System (ADS)

Loewenhardt, Peter

1998-10-01

The usefulness and importance of plasma diagnostics have played a major role in the development of plasma processing tools in the semiconductor industry. As can be seen through marketing materials from semiconductor equipment manufacturers, results from plasma diagnostic equipment can be a powerful tool in selling the technological leadership of tool design. Some diagnostics have long been used for simple process control such as optical emission for endpoint determination, but in recent years more sophisticated and involved diagnostic tools have been utilized in chamber and plasma source development and optimization. It is now common to find an assortment of tools at semiconductor equipment companies such as Langmuir probes, mass spectrometers, spatial optical emission probes, impedance, ion energy and ion flux probes. An outline of how the importance of plasma diagnostics has grown at an equipment manufacturer over the last decade will be given, with examples of significant and useful results obtained. Examples will include the development and optimization of an inductive plasma source, trends and hardware effects on ion energy distributions, mass spectrometry influences on process development and investigations of plasma-wall interactions. Plasma diagnostic focus, in-house development and proliferation in an environment where financial justification requirements are both strong and necessary will be discussed.

40 CFR 63.7180 - What is the purpose of this subpart?

Code of Federal Regulations, 2011 CFR

2011-07-01

... (CONTINUED) National Emission Standards for Hazardous Air Pollutants for Semiconductor Manufacturing What... emission standards for hazardous air pollutants (NESHAP) for semiconductor manufacturing facilities. This...

40 CFR 63.7180 - What is the purpose of this subpart?

Code of Federal Regulations, 2010 CFR

2010-07-01

... (CONTINUED) National Emission Standards for Hazardous Air Pollutants for Semiconductor Manufacturing What... emission standards for hazardous air pollutants (NESHAP) for semiconductor manufacturing facilities. This...

Process Control in Production-Worthy Plasma Doping Technology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Winder, Edmund J.; Fang Ziwei; Arevalo, Edwin

2006-11-13

As the semiconductor industry continues to scale devices of smaller dimensions and improved performance, many ion implantation processes require lower energy and higher doses. Achieving these high doses (in some cases {approx}1x1016 ions/cm2) at low energies (<3 keV) while maintaining throughput is increasingly challenging for traditional beamline implant tools because of space-charge effects that limit achievable beam density at low energies. Plasma doping is recognized as a technology which can overcome this problem. In this paper, we highlight the technology available to achieve process control for all implant parameters associated with modem semiconductor manufacturing.

High-throughput electrical characterization for robust overlay lithography control

NASA Astrophysics Data System (ADS)

Devender, Devender; Shen, Xumin; Duggan, Mark; Singh, Sunil; Rullan, Jonathan; Choo, Jae; Mehta, Sohan; Tang, Teck Jung; Reidy, Sean; Holt, Jonathan; Kim, Hyung Woo; Fox, Robert; Sohn, D. K.

2017-03-01

Realizing sensitive, high throughput and robust overlay measurement is a challenge in current 14nm and advanced upcoming nodes with transition to 300mm and upcoming 450mm semiconductor manufacturing, where slight deviation in overlay has significant impact on reliability and yield1). Exponentially increasing number of critical masks in multi-patterning lithoetch, litho-etch (LELE) and subsequent LELELE semiconductor processes require even tighter overlay specification2). Here, we discuss limitations of current image- and diffraction- based overlay measurement techniques to meet these stringent processing requirements due to sensitivity, throughput and low contrast3). We demonstrate a new electrical measurement based technique where resistance is measured for a macro with intentional misalignment between two layers. Overlay is quantified by a parabolic fitting model to resistance where minima and inflection points are extracted to characterize overlay control and process window, respectively. Analyses using transmission electron microscopy show good correlation between actual overlay performance and overlay obtained from fitting. Additionally, excellent correlation of overlay from electrical measurements to existing image- and diffraction- based techniques is found. We also discuss challenges of integrating electrical measurement based approach in semiconductor manufacturing from Back End of Line (BEOL) perspective. Our findings open up a new pathway for accessing simultaneous overlay as well as process window and margins from a robust, high throughput and electrical measurement approach.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Economics of polysilicon process: A view from Japan

NASA Technical Reports Server (NTRS)

Shimizu, Y.

1986-01-01

The production process of solar grade silicon (SOG-Si) through trichlorosilane (TCS) was researched in a program sponsored by New Energy Development Organization (NEDO). The NEDO process consists of the following two steps: TCS production from by-product silicon tetrachloride (STC) and SOG-Si formation from TCS using a fluidized bed reactor. Based on the data obtained during the research program, the manufacturing cost of the NEDO process and other polysilicon manufacturing processes were compared. The manufacturing cost was calculated on the basis of 1000 tons/year production. The cost estimate showed that the cost of producing silicon by all of the new processes is less than the cost by the conventional Siemens process. Using a new process, the cost of producing semiconductor grade silicon was found to be virtually the same with any to the TCS, diclorosilane, and monosilane processes when by-products were recycled. The SOG-Si manufacturing processes using the fluidized bed reactor, which needs further development, shows a greater probablility of cost reduction than the filament processes.

Fabrication and performance of pressure-sensing device consisting of electret film and organic semiconductor

NASA Astrophysics Data System (ADS)

Kodzasa, Takehito; Nobeshima, Daiki; Kuribara, Kazunori; Uemura, Sei; Yoshida, Manabu

2017-04-01

We propose a new concept of a pressure-sensitive device that consists of an organic electret film and an organic semiconductor. This device exhibits high sensitivity and selectivity against various types of pressure. The sensing mechanism of this device originates from a modulation of the electric conductivity of the organic semiconductor film induced by the interaction between the semiconductor film and the charged electret film placed face to face. It is expected that a complicated sensor array will be fabricated by using a roll-to-roll manufacturing system, because this device can be prepared by an all-printing and simple lamination process without high-level positional adjustment for printing processes. This also shows that this device with a simple structure is suitable for application to a highly flexible device array sheet for an Internet of Things (IoT) or wearable sensing system.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Reents, W.D. Jr.

Particles present in the environment have significant affects in many areas from personal health due to atmospheric particles to various industrial processes that can be ruined due to particulate contamination such as semiconductor device manufacture and manufacture of sterile health products. The ability to detect deleterious contamination requires appropriate instrumentation to detect these particles. To prevent such contamination, the particle source must be identified by determining the composition of the offending particles. In a controlled environment, particle contamination often occurs in transients. In order to identify unknown particles, a technique must obtain compositional and size information regardless of particle identity,more » and perform this analysis in real-time so as to separate {open_quotes}background{close_quotes} particles from those produced in the transient event. Since processes are sensitive to certain particle size regimes and possibly, compositions, the instrumentation must be designed with these needs in mind. The authors have developed an instrument, the Ultra-Sensitive Particle Analysis System (USPAS) for situations where ultrafine particles, down to 0.002 micron, are of concern, such as the semiconductor manufacturing industry and the ambient environment.« less

Planning for the semiconductor manufacturer of the future

NASA Technical Reports Server (NTRS)

Fargher, Hugh E.; Smith, Richard A.

1992-01-01

Texas Instruments (TI) is currently contracted by the Air Force Wright Laboratory and the Defense Advanced Research Projects Agency (DARPA) to develop the next generation flexible semiconductor wafer fabrication system called Microelectronics Manufacturing Science & Technology (MMST). Several revolutionary concepts are being pioneered on MMST, including the following: new single-wafer rapid thermal processes, in-situ sensors, cluster equipment, and advanced Computer Integrated Manufacturing (CIM) software. The objective of the project is to develop a manufacturing system capable of achieving an order of magnitude improvement in almost all aspects of wafer fabrication. TI was awarded the contract in Oct., 1988, and will complete development with a fabrication facility demonstration in April, 1993. An important part of MMST is development of the CIM environment responsible for coordinating all parts of the system. The CIM architecture being developed is based on a distributed object oriented framework made of several cooperating subsystems. The software subsystems include the following: process control for dynamic control of factory processes; modular processing system for controlling the processing equipment; generic equipment model which provides an interface between processing equipment and the rest of the factory; specification system which maintains factory documents and product specifications; simulator for modelling the factory for analysis purposes; scheduler for scheduling work on the factory floor; and the planner for planning and monitoring of orders within the factory. This paper first outlines the division of responsibility between the planner, scheduler, and simulator subsystems. It then describes the approach to incremental planning and the way in which uncertainty is modelled within the plan representation. Finally, current status and initial results are described.

78 FR 42777 - Application for Final Commitment for a Long-Term Loan or Financial Guarantee in Excess of $100...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-17

... the transaction: To support the export of U.S. manufactured semiconductor manufacturing equipment to... supports the manufacture of NAND flash semiconductors. To the extent that Ex-Im Bank is reasonably aware... exportation of goods or provision of services by a United States industry. Parties: Principal Supplier...

Metal organic chemical vapor deposition of 111-v compounds on silicon

DOEpatents

Vernon, Stanley M.

1986-01-01

Expitaxial composite comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) on single crystal silicon substrates are disclosed. Also disclosed is a process for manufacturing, by chemical deposition from the vapor phase, epitaxial composites as above described, and to semiconductor devices based on such epitaxial composites. The composites have particular utility for use in making light sensitive solid state solar cells.

40 CFR 63.7184 - What emission limitations, operating limits, and work practice standards must I meet?

Code of Federal Regulations, 2010 CFR

2010-07-01

... Pollutants for Semiconductor Manufacturing Emission Standards § 63.7184 What emission limitations, operating... this section on and after the compliance dates specified in § 63.7183. (b) Process vents—organic HAP emissions. For each organic HAP process vent, other than process vents from storage tanks, you must limit...

40 CFR 63.7184 - What emission limitations, operating limits, and work practice standards must I meet?

Code of Federal Regulations, 2011 CFR

2011-07-01

... Pollutants for Semiconductor Manufacturing Emission Standards § 63.7184 What emission limitations, operating... this section on and after the compliance dates specified in § 63.7183. (b) Process vents—organic HAP emissions. For each organic HAP process vent, other than process vents from storage tanks, you must limit...

Semiconductor Manufacturing Final Air Toxics Rules Fact Sheets

EPA Pesticide Factsheets

This page contains a February 2003 fact sheet for the final NESHAP for Semiconductor Manufacturing. This page also contains a July 2008 fact sheet with information regarding the final amendments to the 2003 final rule for the NESHAP.

Summary and recommendations. [reduced gravitational effects on materials manufactured in space

NASA Technical Reports Server (NTRS)

1975-01-01

An economic analysis using econometric and cost benefit analysis techniques was performed to determine the feasibility of space processing of certain products. The overall objectives of the analysis were (1) to determine specific products or processes uniquely connected with space manufacturing, (2) to select a specific product or process from each of the areas of semiconductors, metals, and biochemicals, and (3) to determine the overall price/cost structure of each product or process considered. The economic elements of the analysis involved a generalized decision making format for analyzing space manufacturing, a comparative cost study of the selected processes in space vs. earth manufacturing, and a supply and demand study of the economic relationships of one of the manufacturing processes. Space processing concepts were explored. The first involved the use of the shuttle as the factory with all operations performed during individual flights. The second concept involved a permanent unmanned space factory which would be launched separately. The shuttle in this case would be used only for maintenance and refurbishment. Finally, some consideration was given to a permanent manned space factory.

Advanced process control framework initiative

NASA Astrophysics Data System (ADS)

Hill, Tom; Nettles, Steve

1997-01-01

The semiconductor industry, one the world's most fiercely competitive industries, is driven by increasingly complex process technologies and global competition to improve cycle time, quality, and process flexibility. Due to the complexity of these problems, current process control techniques are generally nonautomated, time-consuming, reactive, nonadaptive, and focused on individual fabrication tools and processes. As the semiconductor industry moves into higher density processes, radical new approaches are required. To address the need for advanced factory-level process control in this environment, Honeywell, Advanced Micro Devices (AMD), and SEMATECH formed the Advanced Process Control Framework Initiative (APCFI) joint research project. The project defines and demonstrates an Advanced Process Control (APC) approach based on SEMATECH's Computer Integrated Manufacturing (CIM) Framework. Its scope includes the coordination of Manufacturing Execution Systems, process control tools, and wafer fabrication equipment to provide necessary process control capabilities. Moreover, it takes advantage of the CIM Framework to integrate and coordinate applications from other suppliers that provide services necessary for the overall system to function. This presentation discusses the key concept of model-based process control that differentiates the APC Framework. This major improvement over current methods enables new systematic process control by linking the knowledge of key process settings to desired product characteristics that reside in models created with commercial model development tools The unique framework-based approach facilitates integration of commercial tools and reuse of their data by tying them together in an object-based structure. The presentation also explores the perspective of each organization's involvement in the APCFI project. Each has complementary goals and expertise to contribute; Honeywell represents the supplier viewpoint, AMD represents the user with 'real customer requirements', and SEMATECH provides a consensus-building organization that widely disseminates technology to suppliers and users in the semiconductor industry that face similar equipment and factory control systems challenges.

Technology-design-manufacturing co-optimization for advanced mobile SoCs

NASA Astrophysics Data System (ADS)

Yang, Da; Gan, Chock; Chidambaram, P. R.; Nallapadi, Giri; Zhu, John; Song, S. C.; Xu, Jeff; Yeap, Geoffrey

2014-03-01

How to maintain the Moore's Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

The measurement of alpha particle emissions from semiconductor memory materials

NASA Astrophysics Data System (ADS)

Bouldin, D. P.

1981-07-01

With the increasing concern for the affects of alpha particles on the reliability of semiconductor memories, an interest has arisen in characterizing semiconductor manufacturing materials for extremely low-level alpha-emitting contaminants. It is shown that four elements are of primary concern: uranium, thorium, radium, and polonium. Measurement of contamination levels are given relevance by first correlating them with alpha flux emission levels and then corre1ating these flux values with device soft error rates. Measurement techniques involve either measurements of elemental concentrations-applicable to only uranium and thorium - or direct measurements of alpha emission fluxes. Alpha fluxes are most usefully measured by means of ZnS scintillation counting, practical details of which are discussed. Materials measurements are reported for ceramics, solder, silicon, quartz, and various metals and organic materials. Ceramics and most metals have contamination levels of concern, but the high temperature processing normally used in semiconductor manufacturing and low total amounts reduce problems, at least for metals. Silicon, silicon compounds, and organic materials have been found to have no detectable alpha emitters. Finally, a brief discussion of the calibration of alpha sources for accelerated device testing is given, including practical details on the affects of source/chip separation and alignment variations.

Emission characteristics of volatile organic compounds from semiconductor manufacturing.

PubMed

Chein, HungMin; Chen, Tzu Ming

2003-08-01

A huge amount of volatile organic compounds (VOCs) is produced and emitted with waste gases from semiconductor manufacturing processes, such as cleaning, etching, and developing. VOC emissions from semiconductor factories located at Science-Based Industrial Park, Hsin-chu, Taiwan, were measured and characterized in this study. A total of nine typical semiconductor fabricators (fabs) were monitored over a 12-month period (October 2000-September 2001). A flame ionization analyzer was employed to measure the VOC emission rate continuously in a real-time fashion. The amount of chemical use was adopted from the data that were reported to the Environmental Protection Bureau in Hsin-chu County as per the regulation of the Taiwan Environmental Protection Administration. The VOC emission factor, defined as the emission rate (kg/month) divided by the amount of chemical use (L/month), was determined to be 0.038 +/- 0.016 kg/L. A linear regression equation is proposed to fit the data with the correlation coefficient (R2)=0.863. The emission profiles of VOCs, which were drawn using the gas chromatograph/mass spectrometer analysis method, show that isopropyl alcohol is the dominant compound in most of the fabs.

Rapid Three-Dimensional Printing in Water Using Semiconductor-Metal Hybrid Nanoparticles as Photoinitiators.

PubMed

Pawar, Amol Ashok; Halivni, Shira; Waiskopf, Nir; Ben-Shahar, Yuval; Soreni-Harari, Michal; Bergbreiter, Sarah; Banin, Uri; Magdassi, Shlomo

2017-07-12

Additive manufacturing processes enable fabrication of complex and functional three-dimensional (3D) objects ranging from engine parts to artificial organs. Photopolymerization, which is the most versatile technology enabling such processes through 3D printing, utilizes photoinitiators that break into radicals upon light absorption. We report on a new family of photoinitiators for 3D printing based on hybrid semiconductor-metal nanoparticles. Unlike conventional photoinitiators that are consumed upon irradiation, these particles form radicals through a photocatalytic process. Light absorption by the semiconductor nanorod is followed by charge separation and electron transfer to the metal tip, enabling redox reactions to form radicals in aerobic conditions. In particular, we demonstrate their use in 3D printing in water, where they simultaneously form hydroxyl radicals for the polymerization and consume dissolved oxygen that is a known inhibitor. We also demonstrate their potential for two-photon polymerization due to their giant two-photon absorption cross section.

Splendidly blended: a machine learning set up for CDU control

NASA Astrophysics Data System (ADS)

Utzny, Clemens

2017-06-01

As the concepts of machine learning and artificial intelligence continue to grow in importance in the context of internet related applications it is still in its infancy when it comes to process control within the semiconductor industry. Especially the branch of mask manufacturing presents a challenge to the concepts of machine learning since the business process intrinsically induces pronounced product variability on the background of small plate numbers. In this paper we present the architectural set up of a machine learning algorithm which successfully deals with the demands and pitfalls of mask manufacturing. A detailed motivation of this basic set up followed by an analysis of its statistical properties is given. The machine learning set up for mask manufacturing involves two learning steps: an initial step which identifies and classifies the basic global CD patterns of a process. These results form the basis for the extraction of an optimized training set via balanced sampling. A second learning step uses this training set to obtain the local as well as global CD relationships induced by the manufacturing process. Using two production motivated examples we show how this approach is flexible and powerful enough to deal with the exacting demands of mask manufacturing. In one example we show how dedicated covariates can be used in conjunction with increased spatial resolution of the CD map model in order to deal with pathological CD effects at the mask boundary. The other example shows how the model set up enables strategies for dealing tool specific CD signature differences. In this case the balanced sampling enables a process control scheme which allows usage of the full tool park within the specified tight tolerance budget. Overall, this paper shows that the current rapid developments off the machine learning algorithms can be successfully used within the context of semiconductor manufacturing.

Non- contacting capacitive diagnostic device

DOEpatents

Ellison, Timothy

2005-07-12

A non-contacting capacitive diagnostic device includes a pulsed light source for producing an electric field in a semiconductor or photovoltaic device or material to be evaluated and a circuit responsive to the electric field. The circuit is not in physical contact with the device or material being evaluated and produces an electrical signal characteristic of the electric field produced in the device or material. The diagnostic device permits quality control and evaluation of semiconductor or photovoltaic device properties in continuous manufacturing processes.

MM&T Program to Establish Production Techniques for the Automatic Detection and Qualification of Trace Elements Present in the Production of Microwave Semiconductors.

DTIC Science & Technology

1981-03-01

lots. A single store of partially processed devices may serve as a source for several different product lines. Because the manufacture of microwave...matrix, or react chem- ically with some of the semiconductor materials. In some cases these element impurities may migrate to an interface inducing... different viscosity, the background intensity varied independently of the signal, a significant error could be introduced. A more effec- tive method

Yield: it's now an entitlement

NASA Astrophysics Data System (ADS)

George, Bill

1994-09-01

Only a few years ago, the primary method of cost reduction and productivity improvement in the semiconductor industry was increasing manufacturing yields throughout the process. Many of the remarkable reliability improvements realized over the past decade have come about as a result of actions that were originally taken primarily to improve device yields. Obviously, the practice of productivity improvement through yield enhancement is limited to the attainment of 100% yield, at which point some other mechanism must be employed. Traditionally, new products have been introduced to manufacturing at a point of relative immaturity, and semiconductor producers have relied on the traditional `learning curve' method of yield improvement to attain profitable levels of manufacturing yield. Recently, results of a survey of several fabs by a group of University of California at Berkeley researchers in the Competitive Semiconductor Manufacturing Program indicate that most factories learn at about the same rate after startup, in terms of both line yield and defectivity. If this is indeed generally true, then the most competitive factor is the one that starts with the highest yield, and it is difficult to displace a leader once his lead has been established. The two observations made above carry enormous implications for the semiconductor development or manufacturing professional. First, one must achieve very high yields in order to even play the game. Second, the achievement of competitive yields over time in the life of a factory is determined even before the factory is opened, in the planning and development phase. Third, and perhaps most uncomfortable for those of us who have relied on yield improvement as a cost driver, the winners of the nineties will find new levers to drive costs down, having already gotten the benefit of very high yield. This paper looks at the question of how the winners will achieve the critical measures of success, high initial yield and utilization of other cost reduction levers.

Manufacturability improvements in EUV resist processing toward NXE:3300 processing

NASA Astrophysics Data System (ADS)

Kuwahara, Yuhei; Matsunaga, Koichi; Shimoaoki, Takeshi; Kawakami, Shinichiro; Nafus, Kathleen; Foubert, Philippe; Goethals, Anne-Marie; Shimura, Satoru

2014-03-01

As the design rule of semiconductor process gets finer, extreme ultraviolet lithography (EUVL) technology is aggressively studied as a process for 22nm half pitch and beyond. At present, the studies for EUV focus on manufacturability. It requires fine resolution, uniform, smooth patterns and low defectivity, not only after lithography but also after the etch process. In the first half of 2013, a CLEAN TRACKTM LITHIUS ProTMZ-EUV was installed at imec for POR development in preparation of the ASML NXE:3300. This next generation coating/developing system is equipped with state of the art defect reduction technology. This tool with advanced functions can achieve low defect levels. This paper reports on the progress towards manufacturing defectivity levels and latest optimizations towards the NXE:3300 POR for both lines/spaces and contact holes at imec.

Microeconomics of advanced process window control for 50-nm gates

NASA Astrophysics Data System (ADS)

Monahan, Kevin M.; Chen, Xuemei; Falessi, Georges; Garvin, Craig; Hankinson, Matt; Lev, Amir; Levy, Ady; Slessor, Michael D.

2002-07-01

Fundamentally, advanced process control enables accelerated design-rule reduction, but simple microeconomic models that directly link the effects of advanced process control to profitability are rare or non-existent. In this work, we derive these links using a simplified model for the rate of profit generated by the semiconductor manufacturing process. We use it to explain why and how microprocessor manufacturers strive to avoid commoditization by producing only the number of dies required to satisfy the time-varying demand in each performance segment. This strategy is realized using the tactic known as speed binning, the deliberate creation of an unnatural distribution of microprocessor performance that varies according to market demand. We show that the ability of APC to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process window variation.

Diode step stress program for JANTX1N5615

NASA Technical Reports Server (NTRS)

1979-01-01

The effect of power/temperature step stress when applied to the switching diode JANTX1N5615 manufactured by Semtech and Micro semiconductor was examined. A total of 48 samples from each manufacturer were submitted to the process. In addition, two control sample units were maintained for verification of the electrical parametric testing. All test samples were subjected to the electrical tests after completing the prior power/temperature step stress point. Results are presented.

Water Purification Systems

NASA Technical Reports Server (NTRS)

1992-01-01

A water purification/recycling system developed by Photo-Catalytics, Inc. (PCI) for NASA is commercially available. The system cleanses and recycles water, using a "photo-catalysis" process in which light or radiant energy sparks a chemical reaction. Chemically stable semiconductor powders are added to organically polluted water. The powder absorbs ultraviolet light, and pollutants are oxidized and converted to carbon dioxide. Potential markets for the system include research and pharmaceutical manufacturing applications, as well as microchip manufacture and wastewater cleansing.

A New Commercializable Route for the Preparation of Single-Source Precursors for Bulk, Thin-Film, and Nanocrystallite I-III-IV Semiconductors

NASA Technical Reports Server (NTRS)

Banger, Kulbinder K.; Jin, Michael H. C.; Harris, Jerry D.; Fanwick, Philip E.; Hepp, Aloysius F.

2004-01-01

We report a new simplified synthetic procedure for commercial manufacture of ternary single source precursors (SSP). This new synthetic process has been successfully implemented to fabricate known SSPs on bulk scale and the first liquid SSPs to the semiconductors CuInSe2 and AgIn(x)S(y). Single crystal X-ray determination reveals the first unsolvated ternary AgInS SSP. SSPs prepared via this new route have successfully been used in a spray assisted chemical vapor deposition (CVD) process to deposit polycrystalline thin films, and for preparing ternary nanocrystallites.

National Manufacturing Strategy: Is a National Manufacturing Strategy Essential to National Security?

DTIC Science & Technology

2011-05-01

cycle found nearly a quarter of all homeowners owning more than their home was worth. 11 Both Paul Volcker and Warren Buffet arrived at similar...November 15, 2010; Warren Buffet , Testimony, Financial Crisis Inquiry Commission, June 2, 2010; “Subprime Mortgage Crisis,” http://en.wikipedia.org...overseas manufacturing. Case Study: Semiconductor Wafer Industry. The history of the semiconductor industry is an instructive account . It begins with

The relationship between spontaneous abortion and female workers in the semiconductor industry.

PubMed

Kim, Heechan; Kwon, Ho-Jang; Rhie, Jeongbae; Lim, Sinye; Kang, Yun-Dan; Eom, Sang-Yong; Lim, Hyungryul; Myong, Jun-Pyo; Roh, Sangchul

2017-01-01

This study investigated the relationship between job type and the risk for spontaneous abortion to assess the reproductive toxicity of female workers in the semiconductor industry. A questionnaire survey was administered to current female workers of two semiconductor manufacturing plants in Korea. We included female workers who became pregnant at least 6 months after the start of their employment with the company. The pregnancy outcomes of 2,242 female workers who experienced 4,037 pregnancies were investigated. Personnel records were used to assign the subjects to one of three groups: fabrication process workers, packaging process workers, and clerical workers. To adjust for within-person correlations between pregnancies, a generalized estimating equation was used. The logistic regression analysis was limited to the first pregnancy after joining the company to satisfy the assumption of independence among pregnancies. Moreover, we stratified the analysis by time period (pregnancy in the years prior to 2008 vs. after 2009) to reflect differences in occupational exposure based on semiconductor production periods. The risk for spontaneous abortion in female semiconductor workers was not significantly higher for fabrication and packaging process workers than for clerical workers. However, when we stratified by time period, the odds ratio for spontaneous abortion was significantly higher for packaging process workers who became pregnant prior to 2008 when compared with clerical workers (odds ratio: 2.21; 95% confidence interval: 1.01-4.81). When examining the pregnancies of female semiconductor workers that occurred prior to 2008, packaging process workers showed a significantly higher risk for spontaneous abortions than did clerical workers. The two semiconductor production periods in our study (prior to 2008 vs. after 2009) had different automated processes, chemical exposure levels, and working environments. Thus, the conditions prior to 2008 may have increased the risk for spontaneous abortions in packaging process workers in the semiconductor industry.

Design for manufacturability production management activity report

NASA Astrophysics Data System (ADS)

Miyazaki, Norihiko; Sato, T.; Honma, M.; Yoshioka, N.; Hosono, K.; Onodera, T.; Itoh, H.; Suzuki, H.; Uga, T.; Kadota, K.; Iriki, N.

2006-05-01

Design For Manufacturability Production Management (DFM-PM) Subcommittee has been started in succession to Reticle Management Subcommittee (RMS) in Semiconductor Manufacturing Technology Committee for Japan (SMTCJ) from 2005. Our activity focuses on the SoC (System On Chip) Business, and it pursues the improvement of communication in manufacturing technique. The first theme of activity is the investigation and examination of the new trends about production (manufacturer) technology and related information, and proposals of business solution. The second theme is the standardization activity about manufacture technology and the cooperation with related semiconductors' organizations. And the third theme is holding workshop and support for promotion and spread of the standardization technology throughout semiconductor companies. We expand a range of scope from design technology to wafer pattern reliability and we will propose the competition domain, the collaboration area and the standardization technology on DFM. Furthermore, we will be able to make up a SoC business model as the 45nm node technology beyond manufacturing platform in cooperating with the design information and the production information by utilizing EDA technology.

IEEE WMED 2016 Homepage

Science.gov Websites

characterization, design, and new device technologies. This workshop will consist of invited talks, contributed and Reliability Semiconductor package reliability, Design for Manufacturability, Stacked die packaging and Novel assembly processes Microelectronic Circuit Design New product design, high-speed and/or low

77 FR 65878 - Application for Final Commitment for a Long-term Loan or Financial Guarantee in Excess of $100...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-10-31

... export of semiconductor manufacturing equipment to Germany. Brief non-proprietary description of the anticipated use of the items being exported: Equipment supports the manufacture of logic semiconductors. To... United States industry. Parties: Principal Suppliers: Applied Materials, Inc., KLA-Tencor Corporation...

Automated defect spatial signature analysis for semiconductor manufacturing process

DOEpatents

Tobin, Jr., Kenneth W.; Gleason, Shaun S.; Karnowski, Thomas P.; Sari-Sarraf, Hamed

1999-01-01

An apparatus and method for performing automated defect spatial signature alysis on a data set representing defect coordinates and wafer processing information includes categorizing data from the data set into a plurality of high level categories, classifying the categorized data contained in each high level category into user-labeled signature events, and correlating the categorized, classified signature events to a present or incipient anomalous process condition.

Research and Development Strategies in the Semiconductor Industry

NASA Astrophysics Data System (ADS)

Bowling, Allen

2003-03-01

In the 21st Century semiconductor industry, there is a critical balance between internally funded semiconductor research and development (R) and externally funded R. External R may include jointly-funded research collaborations/partnerships with other device manufacturers, jointly-funded consortia-based R, and individually-funded research programs at universities and other contract research locations. Each of these approaches has merits and each has costs. There is a critical balance between keeping the internal research and development pipeline filled and keeping it from being overspent. To meet both competitive schedule and cost goals, a semiconductor device manufacturer must decide on a model for selection of internal versus external R. Today, one of the most critical decisions is whether or not to do semiconductor research and development on 300 mm silicon wafers. Equipment suppliers are doing first development on 300 mm equipment. So, for the device manufacturer, there is a balance between the cost of doing development on 300 mm wafers and the development time schedule driven by equipment availability. In the face of these cost and schedule elements, device manufacturers are looking to consortia such as SEMATECH, SRC, and SRC MARCO for early development and screening of new materials and device structure approaches. This also causes much more close development collaboration between device manufacturer and equipment supplier. Many device manufacturers are also making use of direct contract research with universities and other contract-research organizations, such as IMEC, LETI, and other government-funded research organizations around the world. To get the most out of these external research interactions, the company must develop a strategy for management and technology integration of external R.

Solar cells with low cost substrates, process of making same and article of manufacture

DOEpatents

Mitchell, K.W.

A solar cell is disclosed having a substrate and an intermediate recrystallized film and a semiconductor material capable of absorbing light with the substrate being selected from one of a synthetic organic resin, graphite, glass and a crystalline material having a grain size less than about 1 micron/sup 2/. The intermediate recrystallized film has a grain size in the range of from about 10 microns/sup 2/ to about 10,000 microns/sup 2/ and a lattice mismatch with the semiconductor material not greater than about 4%. The semiconductor material has a grain size not less than about 10 microns/sup 2/. An anti-reflective layer and electrical contact means are provided. Also disclosed is a subcombination of substrate, intermediate recrystallized film and semiconductor material. Also, methods of formulating the solar cell and subcombination are disclosed.

Microeconomics of yield learning and process control in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Monahan, Kevin M.

2003-06-01

Simple microeconomic models that directly link yield learning to profitability in semiconductor manufacturing have been rare or non-existent. In this work, we review such a model and provide links to inspection capability and cost. Using a small number of input parameters, we explain current yield management practices in 200mm factories. The model is then used to extrapolate requirements for 300mm factories, including the impact of technology transitions to 130nm design rules and below. We show that the dramatic increase in value per wafer at the 300mm transition becomes a driver for increasing metrology and inspection capability and sampling. These analyses correlate well wtih actual factory data and often identify millions of dollars in potential cost savings. We demonstrate this using the example of grating-based overlay metrology for the 65nm node.

Materials, Processes, and Facile Manufacturing for Bioresorbable Electronics: A Review.

PubMed

Yu, Xiaowei; Shou, Wan; Mahajan, Bikram K; Huang, Xian; Pan, Heng

2018-05-07

Bioresorbable electronics refer to a new class of advanced electronics that can completely dissolve or disintegrate with environmentally and biologically benign byproducts in water and biofluids. They have provided a solution to the growing electronic waste problem with applications in temporary usage of electronics such as implantable devices and environmental sensors. Bioresorbable materials such as biodegradable polymers, dissolvable conductors, semiconductors, and dielectrics are extensively studied, enabling massive progress of bioresorbable electronic devices. Processing and patterning of these materials are predominantly relying on vacuum-based fabrication methods so far. However, for the purpose of commercialization, nonvacuum, low-cost, and facile manufacturing/printing approaches are the need of the hour. Bioresorbable electronic materials are generally more chemically reactive than conventional electronic materials, which require particular attention in developing the low-cost manufacturing processes in ambient environment. This review focuses on material reactivity, ink availability, printability, and process compatibility for facile manufacturing of bioresorbable electronics. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Coherent diffractive imaging methods for semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Helfenstein, Patrick; Mochi, Iacopo; Rajeev, Rajendran; Fernandez, Sara; Ekinci, Yasin

2017-12-01

The paradigm shift of the semiconductor industry moving from deep ultraviolet to extreme ultraviolet lithography (EUVL) brought about new challenges in the fabrication of illumination and projection optics, which constitute one of the core sources of cost of ownership for many of the metrology tools needed in the lithography process. For this reason, lensless imaging techniques based on coherent diffractive imaging started to raise interest in the EUVL community. This paper presents an overview of currently on-going research endeavors that use a number of methods based on lensless imaging with coherent light.

Health and safety executive inspection of U.K. semiconductor manufacturers.

PubMed

Watterson, Andrew; LaDou, Joseph

2003-01-01

Europe plays a major role in the international semiconductor industry, but has conducted few studies of the occupational health of its workers. An exception is in the United Kingdom, where, in two small studies, the Health and Safety Executive (HSE) evaluated some health effects of semiconductor work. Neither of these studies, largely restricted to Scotland, produced definitive results, and both were misused by industry to assert that they demonstrated no adverse health effect on workers. The results of the studies prompted semiconductor industry inspections recently completed by the HSE that included chip manufacturers in Scotland and other U.K. areas. The results of these inspections are disappointing.

Technology development of high-quality semiconductor devices using solution-processed crystallization of pentacene

NASA Astrophysics Data System (ADS)

Liu, Hung-Wei

Organic electronic materials and processing techniques have attracted considerable attention for developing organic thin-film transistors (OTFTs), since they may be patterned on flexible substrates which may be bent into a variety of shapes for applications such as displays, smart cards, solar devices and sensors Various fabrication methods for building pentacene-based OTFTs have been demonstrated. Traditional vacuum deposition and vapor deposition methods have been studied for deposition on plastic and paper, but these are unlikely to scale well to large area printing. Researchers have developed methods for processing OTFTs from solution because of the potential for low-cost and large area device manufacturing, such as through inkjet or offset printing. Most methods require the use of precursors which are used to make pentacene soluble, and these methods have typically produced much lower carrier mobility than the best vacuum deposited devices. We have investigated devices built from solution-processed pentacene that is locally crystallized at room temperature on the polymer substrates. Pentacene crystals grown in this manner are highly localized at pre-determined sites, have good crystallinity and show good carrier mobility, making this an attractive method for large area manufacturing of semiconductor devices.

Process for forming pure silver ohmic contacts to N- and P-type gallium arsenide materials

DOEpatents

Hogan, S.J.

1983-03-13

Disclosed is an improved process for manufacturing gallium arsenide semiconductor devices having as its components a n-type gallium arsenide substrate layer and a p-type gallium arsenide diffused layer. The improved process comprises forming a pure silver ohmic contact to both the diffuse layer and the substrate layer wherein the n-type layer comprises a substantially low doping carrier concentration.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2012 CFR

2012-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2013 CFR

2013-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2014 CFR

2014-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

Pixel-based OPC optimization based on conjugate gradients.

PubMed

Ma, Xu; Arce, Gonzalo R

2011-01-31

Optical proximity correction (OPC) methods are resolution enhancement techniques (RET) used extensively in the semiconductor industry to improve the resolution and pattern fidelity of optical lithography. In pixel-based OPC (PBOPC), the mask is divided into small pixels, each of which is modified during the optimization process. Two critical issues in PBOPC are the required computational complexity of the optimization process, and the manufacturability of the optimized mask. Most current OPC optimization methods apply the steepest descent (SD) algorithm to improve image fidelity augmented by regularization penalties to reduce the complexity of the mask. Although simple to implement, the SD algorithm converges slowly. The existing regularization penalties, however, fall short in meeting the mask rule check (MRC) requirements often used in semiconductor manufacturing. This paper focuses on developing OPC optimization algorithms based on the conjugate gradient (CG) method which exhibits much faster convergence than the SD algorithm. The imaging formation process is represented by the Fourier series expansion model which approximates the partially coherent system as a sum of coherent systems. In order to obtain more desirable manufacturability properties of the mask pattern, a MRC penalty is proposed to enlarge the linear size of the sub-resolution assistant features (SRAFs), as well as the distances between the SRAFs and the main body of the mask. Finally, a projection method is developed to further reduce the complexity of the optimized mask pattern.

Nanoband array electrode as a platform for high sensitivity enzyme-based glucose biosensing.

PubMed

Falk, Magnus; Sultana, Reshma; Swann, Marcus J; Mount, Andrew R; Freeman, Neville J

2016-12-01

We describe a novel glucose biosensor based on a nanoband array electrode design, manufactured using standard semiconductor processing techniques, and bio-modified with glucose oxidase immobilized at the nanoband electrode surface. The nanoband array architecture allows for efficient diffusion of glucose and oxygen to the electrode, resulting in a thousand-fold improvement in sensitivity and wide linear range compared to a conventional electrode. The electrode constitutes a robust and manufacturable sensing platform. Copyright © 2016 Elsevier B.V. All rights reserved.

Enhanced photoconductivity by melt quenching method for amorphous organic photorefractive materials

NASA Astrophysics Data System (ADS)

Tsujimura, S.; Fujihara, T.; Sassa, T.; Kinashi, K.; Sakai, W.; Ishibashi, K.; Tsutsumi, N.

2014-10-01

For many optical semiconductor fields of study, the high photoconductivity of amorphous organic semiconductors has strongly been desired, because they make the manufacture of high-performance devices easy when controlling charge carrier transport and trapping is otherwise difficult. This study focuses on the correlation between photoconductivity and bulk state in amorphous organic photorefractive materials to probe the nature of the performance of photoconductivity and to enhance the response time and diffraction efficiency of photorefractivity. The general cooling processes of the quenching method achieved enhanced photoconductivity and a decreased filling rate for shallow traps. Therefore, sample processing, which was quenching in the present case, for photorefractive composites significantly relates to enhanced photorefractivity.

Novel EUV photoresist for sub-7nm node (Conference Presentation)

NASA Astrophysics Data System (ADS)

Furukawa, Tsuyoshi; Naruoka, Takehiko; Nakagawa, Hisashi; Miyata, Hiromu; Shiratani, Motohiro; Hori, Masafumi; Dei, Satoshi; Ayothi, Ramakrishnan; Hishiro, Yoshi; Nagai, Tomoki

2017-04-01

Extreme ultraviolet (EUV) lithography has been recognized as a promising candidate for the manufacturing of semiconductor devices as LS and CH pattern for 7nm node and beyond. EUV lithography is ready for high volume manufacturing stage. For the high volume manufacturing of semiconductor devices, significant improvement of sensitivity and line edge roughness (LWR) and Local CD Uniformity (LCDU) is required for EUV resist. It is well-known that the key challenge for EUV resist is the simultaneous requirement of ultrahigh resolution (R), low line edge roughness (L) and high sensitivity (S). Especially high sensitivity and good roughness is important for EUV lithography high volume manufacturing. We are trying to improve sensitivity and LWR/LCDU from many directions. From material side, we found that both sensitivity and LWR/LCDU are simultaneously improved by controlling acid diffusion length and efficiency of acid generation using novel resin and PAG. And optimizing EUV integration is one of the good solution to improve sensitivity and LWR/LCDU. We are challenging to develop new multi-layer materials to improve sensitivity and LWR/LCDU. Our new multi-layer materials are designed for best performance in EUV lithography system. From process side, we found that sensitivity was substantially improved maintaining LWR applying novel type of chemical amplified resist (CAR) and process. EUV lithography evaluation results obtained for new CAR EUV interference lithography. And also metal containing resist is one possibility to break through sensitivity and LWR trade off. In this paper, we will report the recent progress of sensitivity and LWR/LCDU improvement of JSR novel EUV resist and process.

Sulfide semiconductor materials prepared by high-speed electrodeposition and discussion of electrochemical reaction mechanism

NASA Astrophysics Data System (ADS)

Okamoto, Naoki; Kataoka, Kentaro; Saito, Takeyasu

2017-07-01

A manufacturing method for SnS using a one-step electrochemical technique was developed. The sulfide semiconductor was formed by electrodeposition using an aqueous bath at low temperatures. The sulfide semiconductor particles produced were characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM). The highest current density at which SnS was formed was 1800 mA/cm2 at a bath temperature of 293 K, which is 36 times larger than that in a previous deposition process. Analysis of the chronoamperometric current-time transients indicated that in the potential range from -1100 to -2000 mV vs saturated calomel electrode (SCE), the electrodeposition of SnS can be explained by an instantaneous nucleation model.

Using an extractive Fourier transform infrared spectrometer for improving cleanroom air quality in a semiconductor manufacturing plant.

PubMed

Li, Shou-Nan; Chang, Chin-Ta; Shih, Hui-Ya; Tang, Andy; Li, Alen; Chen, Yin-Yung

2003-01-01

A mobile extractive Fourier transform infrared (FTIR) spectrometer was successfully used to locate, identify, and quantify the "odor" sources inside the cleanroom of a semiconductor manufacturing plant. It was found that ozone (O(3)) gas with a peak concentration of 120 ppm was unexpectedly releasing from a headspace of a drain for transporting used ozonized water and that silicon tetrafluoride (SiF(4)) with a peak concentration of 3 ppm was off-gassed from silicon wafers after dry-etching processing. When the sources of the odors was pinpointed by the FTIR, engineering control measures were applied. For O(3) control, a water-sealed pipeline was added to prevent the O(3) gas (emitting from the ozonized water) from entering the mixing unit. A ventilation system also was applied to the mixing unit in case of O(3) release. For SiF(4) mitigation, before the wafer-out chamber was opened, N(2) gas with a flow rate of 150 L/min was used for 100 sec to purge the wafer-out chamber, and a vacuum system was simultaneously activated to pump away the purging N(2). The effectiveness of the control measures was assured by using the FTIR. In addition, the FTIR was used to monitor the potential hazardous gas emissions during preventative maintenance of the semiconductor manufacturing equipment.

High throughput wafer defect monitor for integrated metrology applications in photolithography

NASA Astrophysics Data System (ADS)

Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

2008-03-01

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Pure silver ohmic contacts to N- and P- type gallium arsenide materials

DOEpatents

Hogan, Stephen J.

1986-01-01

Disclosed is an improved process for manufacturing gallium arsenide semiconductor devices having as its components an n-type gallium arsenide substrate layer and a p-type gallium arsenide diffused layer. The improved process comprises forming a pure silver ohmic contact to both the diffused layer and the substrate layer, wherein the n-type layer comprises a substantially low doping carrier concentration.

Laser pattern generator challenges in airborne molecular contamination protection

NASA Astrophysics Data System (ADS)

Ekberg, Mats; Skotte, Per-Uno; Utterback, Tomas; Paul, Swaraj; Kishkovich, Oleg P.; Hudzik, James S.

2003-08-01

The introduction of photomask laser pattern generators presents new challenges to system designers and manufacturers. One of the laser pattern generator's environmental operating challenges is Airborne Molecular Contamination (AMC), which affects both chemically amplified resists (CAResist) and laser optics. Similar challenges in CAResist protection have already been addressed in semiconductor wafer lithography with reasonable solutions and experience gained by all those involved. However, photomask and photomask equipment manufacturers have not previously had a comparable experience, and some photomask AMC issues differ from those seen in semiconductor wafer lithography. Culminating years of AMC experience, the authors discuss specific requirements of Photomask AMC. Air sampling and material of construction analysis were performed to understand these particular AMC challenges and used to develop an appropriate filtration specification for different classes of contaminates. The authors portray the importance of cooperation between tool designers and AMC experts early in the design stage to assure goal attainment to maximize both process stability and machine productivity in advanced mask making. In conclusion, the authors provide valuable recommendations to both laser tool users and other equipment manufacturers.

Patterned wafer geometry grouping for improved overlay control

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

2017-03-01

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

40 CFR 469.10 - Applicability.

Code of Federal Regulations, 2010 CFR

2010-07-01

... ELECTRICAL AND ELECTRONIC COMPONENTS POINT SOURCE CATEGORY Semiconductor Subcategory § 469.10 Applicability... associated with the manufacture of semiconductors, except sputtering, vapor deposition, and electroplating. ...

40 CFR 469.10 - Applicability.

Code of Federal Regulations, 2011 CFR

2011-07-01

... ELECTRICAL AND ELECTRONIC COMPONENTS POINT SOURCE CATEGORY Semiconductor Subcategory § 469.10 Applicability... associated with the manufacture of semiconductors, except sputtering, vapor deposition, and electroplating. ...

New method of 2-dimensional metrology using mask contouring

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Yamagata, Yoshikazu; Sugiyama, Akiyuki; Toyoda, Yasutaka

2008-10-01

We have developed a new method of accurately profiling and measuring of a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, this edge detection method is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. This method realizes two-dimensional metrology for refined pattern that had been difficult to measure conventionally by utilizing high precision contour profile. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. This is to say, demands for quality is becoming strenuous because of enormous quantity of data growth with increasing of refined pattern on photo mask manufacture. In the result, massive amount of simulated error occurs on mask inspection that causes lengthening of mask production and inspection period, cost increasing, and long delivery time. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method of a DFM solution using two-dimensional metrology for refined pattern.

Does your SEM really tell the truth?--How would you know? Part 1.

PubMed

Postek, Michael T; Vladár, András E

2013-01-01

The scanning electron microscope (SEM) has gone through a tremendous evolution to become a critical tool for many and diverse scientific and industrial applications. The high resolution of the SEM is especially suited for both qualitative and quantitative applications especially for nanotechnology and nanomanufacturing. Quantitatively, measurement, or metrology is one of the main uses. It is likely that one of the first questions asked before even the first scanning electron micrograph was ever recorded was: "… how big is that?" The quality of that answer has improved a great deal over the past few years especially since today these instruments are being used as a primary measurement tool on semiconductor processing lines to monitor the manufacturing processes. The well-articulated needs of semiconductor production prompted a rapid evolution of the instrument and its capabilities. Over the past 20 years or so, instrument manufacturers, through substantial semiconductor industry investment of research and development (R&D) money, have vastly improved the performance of these instruments. All users have benefited from this investment, especially where quantitative measurements with an SEM are concerned. But, how good are these data? This article discusses some of the most important aspects and larger issues associated with imaging and measurements with the SEM that every user should know, and understand before any critical quantitative work is attempted. © Wiley Periodicals, Inc.

Adsorption treatment of oxide chemical mechanical polishing wastewater from a semiconductor manufacturing plant by electrocoagulation.

PubMed

Chou, Wei-Lung; Wang, Chih-Ta; Chang, Wen-Chun; Chang, Shih-Yu

2010-08-15

In this study, metal hydroxides generated during electrocoagulation (EC) were used to remove the chemical oxygen demand (COD) of oxide chemical mechanical polishing (oxide-CMP) wastewater from a semiconductor manufacturing plant by EC. Adsorption studies were conducted in a batch system for various current densities and temperatures. The COD concentration in the oxide-CMP wastewater was effectively removed and decreased by more than 90%, resulting in a final wastewater COD concentration that was below the Taiwan discharge standard (100 mg L(-1)). Since the processed wastewater quality exceeded the direct discharge standard, the effluent could be considered for reuse. The adsorption kinetic studies showed that the EC process was best described using the pseudo-second-order kinetic model at the various current densities and temperatures. The experimental data were also tested against different adsorption isotherm models to describe the EC process. The Freundlich adsorption isotherm model predictions matched satisfactorily with the experimental observations. Thermodynamic parameters, including the Gibbs free energy, enthalpy, and entropy, indicated that the COD adsorption of oxide-CMP wastewater on metal hydroxides was feasible, spontaneous and endothermic in the temperature range of 288-318 K. Copyright 2010 Elsevier B.V. All rights reserved.

Ge/IIIV fin field-effect transistor common gate process and numerical simulations

NASA Astrophysics Data System (ADS)

Chen, Bo-Yuan; Chen, Jiann-Lin; Chu, Chun-Lin; Luo, Guang-Li; Lee, Shyong; Chang, Edward Yi

2017-04-01

This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high- and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations.

The future of automation for high-volume wafer fabrication and ASIC manufacturing

NASA Astrophysics Data System (ADS)

Hughes, Randall A.; Shott, John D.

1986-12-01

A framework is given to analyze the future trends in semiconductor manufacturing automation systems, focusing specifically on the needs of ASIC (application-specific integrated circuit) or custom integrated circuit manufacturing. Advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating nonstandard functions on silicon. ASICs are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. Previously, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment.

Low-Cost and Large-Area Electronics, Roll-to-Roll Processing and Beyond

NASA Astrophysics Data System (ADS)

Wiesenhütter, Katarzyna; Skorupa, Wolfgang

In the following chapter, the authors conduct a literature survey of current advances in state-of-the-art low-cost, flexible electronics. A new emerging trend in the design of modern semiconductor devices dedicated to scaling-up, rather than reducing, their dimensions is presented. To realize volume manufacturing, alternative semiconductor materials with superior performance, fabricated by innovative processing methods, are essential. This review provides readers with a general overview of the material and technology evolution in the area of macroelectronics. Herein, the term macroelectronics (MEs) refers to electronic systems that can cover a large area of flexible media. In stark contrast to well-established micro- and nano-scale semiconductor devices, where property improvement is associated with downscaling the dimensions of the functional elements, in macroelectronic systems their overall size defines the ultimate performance (Sun and Rogers in Adv. Mater. 19:1897-1916, 2007). The major challenges of large-scale production are discussed. Particular attention has been focused on describing advanced, short-term heat treatment approaches, which offer a range of advantages compared to conventional annealing methods. There is no doubt that large-area, flexible electronic systems constitute an important research topic for the semiconductor industry. The ability to fabricate highly efficient macroelectronics by inexpensive processes will have a significant impact on a range of diverse technology sectors. A new era "towards semiconductor volume manufacturing…" has begun.

Selective epitaxy using the gild process

DOEpatents

Weiner, Kurt H.

1992-01-01

The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.1-x grown over silicon. Such a process may be used to manufacture small transistors that have a narrow base, heavy doping, and high gain. The narrowness allows a faster transistor, and the heavy doping reduces the resistance of the narrow layer. The process does not require high temperature annealing; therefore materials such as aluminum can be used. Furthermore, the process may be used to fabricate diodes that have a high reverse breakdown voltage and a low reverse leakage current.

EUV patterning improvement toward high-volume manufacturing

NASA Astrophysics Data System (ADS)

Kuwahara, Yuhei; Matsunaga, Koichi; Kawakami, Shinichiro; Nafus, Kathleen; Foubert, Philippe; Goethals, Anne-Marie

2015-03-01

Extreme ultraviolet lithography (EUVL) technology is a promising candidate for a semiconductor process for 18nm half pitch and beyond. So far, the studies of EUV for manufacturability have been focused on particular aspects. It still requires fine resolution, uniform and smooth patterns, and low defectivity, not only after lithography but also after the etch process. Tokyo Electron Limited and imec are continuously collaborating to improve manufacturing quality of the process of record (POR) on a CLEAN TRACKTM LITHIUS ProTMZ-EUV. This next generation coating/developing system has been upgraded with defectivity reduction enhancements which are applied along with TELTM best known methods. We have evaluated process defectivity post lithography and post etch. Apart from defectivity, FIRMTM rinse material and application compatibility with sub 18nm patterning is improved to prevent line pattern collapse and increase process window on next generation resist materials. This paper reports on the progress of defectivity and patterning performance optimization towards the NXE:3300 POR.

76 FR 59542 - Mandatory Reporting of Greenhouse Gases: Changes to Provisions for Electronics Manufacturing To...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-09-27

... Mandatory Reporting of Greenhouse Gases: Changes to Provisions for Electronics Manufacturing To Provide... regulation to amend the calculation and monitoring provisions in the Electronics Manufacturing portion of the... Electronics Manufacturing 334111 Microcomputer manufacturing facilities. 334413 Semiconductor, photovoltaic...

Evolutionary fuzzy ARTMAP neural networks for classification of semiconductor defects.

PubMed

Tan, Shing Chiang; Watada, Junzo; Ibrahim, Zuwairie; Khalid, Marzuki

2015-05-01

Wafer defect detection using an intelligent system is an approach of quality improvement in semiconductor manufacturing that aims to enhance its process stability, increase production capacity, and improve yields. Occasionally, only few records that indicate defective units are available and they are classified as a minority group in a large database. Such a situation leads to an imbalanced data set problem, wherein it engenders a great challenge to deal with by applying machine-learning techniques for obtaining effective solution. In addition, the database may comprise overlapping samples of different classes. This paper introduces two models of evolutionary fuzzy ARTMAP (FAM) neural networks to deal with the imbalanced data set problems in a semiconductor manufacturing operations. In particular, both the FAM models and hybrid genetic algorithms are integrated in the proposed evolutionary artificial neural networks (EANNs) to classify an imbalanced data set. In addition, one of the proposed EANNs incorporates a facility to learn overlapping samples of different classes from the imbalanced data environment. The classification results of the proposed evolutionary FAM neural networks are presented, compared, and analyzed using several classification metrics. The outcomes positively indicate the effectiveness of the proposed networks in handling classification problems with imbalanced data sets.

EUVL masks: paving the path for commercialization

NASA Astrophysics Data System (ADS)

Mangat, Pawitter J. S.; Hector, Scott D.

2001-09-01

Optical projection lithography has been the principal vehicle of semiconductor manufacturing for more than 20 years and is marching aggressively to satisfy the needs of semiconductor manufacturers for 100nm devices. However, the complexity of optical lithography continues to increase as wavelength reduction continues to 157nm. Extreme Ultraviolet Lithography (EUVL), with wavelength from 13-14 nm, is evolving as a leading next generation lithography option for semiconductor industry to stay on the path laid by Moore's Law. Masks are a critical part of the success of any technology and are considered to be high risk both for optical lithography and NGL technologies for sub-100nm lithography. Two key areas of EUV mask fabrication are reflective multilayer deposition and absorber patterning. In the case of reflective multilayers, delivering defect free multilayers for mask blanks is the biggest challenge. Defect mitigation is being explored as a possible option to smooth the multilayer defects in addition to optimization of the deposition process to reduce defect density. The mask patterning process needs focus on the defect-free absorber stack patterning process, mask cleaning, inspection and repair. In addition, there is considerable effort to understand by simulations, the defect printability, thermal and mechanical distortions, and non-telecentric illumination, to mention a few. To protect the finished mask from defects added during use, a removable pellicle strategy combined with thermophoretic protection during exposure is being developed. Recent migration to square form factor using low thermal expansion material (LTEM) is advantageous as historical developments in optical masks can be applied to EUV mask patterning. This paper addresses recent developments in the EUV mask patterning and highlights critical manufacturing process controls needed to fabricate defect-free full field masks with CD and image placement specifications for sub-70nm node lithography. No technology can be implemented without establishing the commercial infrastructure. The rising cost seems to be a major issue affecting the technology development. With respect to mask fabrication for commercial availability, a virtual mask shop analysis is presented that indicates that the process cost for EUVL masks are comparable to the high end optical mask with a reasonable yield. However, the cost for setting up a new mask facility is considerably high.

Radio frequency tags systems to initiate system processing

NASA Astrophysics Data System (ADS)

Madsen, Harold O.; Madsen, David W.

1994-09-01

This paper describes the automatic identification technology which has been installed at Applied Magnetic Corp. MR fab. World class manufacturing requires technology exploitation. This system combines (1) FluoroTrac cassette and operator tracking, (2) CELLworks cell controller software tools, and (3) Auto-Soft Inc. software integration services. The combined system eliminates operator keystrokes and errors during normal processing within a semiconductor fab. The methods and benefits of this system are described.

An Assessment of Critical Dimension Small Angle X-ray Scattering Metrology for Advanced Semiconductor Manufacturing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Settens, Charles M.

2015-01-01

Simultaneous migration of planar transistors to FinFET architectures, the introduction of a plurality of materials to ensure suitable electrical characteristics, and the establishment of reliable multiple patterning lithography schemes to pattern sub-10 nm feature sizes imposes formidable challenges to current in-line dimensional metrologies. Because the shape of a FinFET channel cross-section immediately influences the electrical characteristics, the evaluation of 3D device structures requires measurement of parameters beyond traditional critical dimension (CD), including their sidewall angles, top corner rounding and footing, roughness, recesses and undercuts at single nanometer dimensions; thus, metrologies require sub-nm and approaching atomic level measurement uncertainty. Synchrotron criticalmore » dimension small angle X-ray scattering (CD-SAXS) has unique capabilities to non-destructively monitor the cross-section shape of surface structures with single nanometer uncertainty and can perform overlay metrology to sub-nm uncertainty. In this dissertation, we perform a systematic experimental investigation using CD-SAXS metrology on a hierarchy of semiconductor 3D device architectures including, high-aspect-ratio contact holes, H2 annealed Si fins, and a series of grating type samples at multiple points along a FinFET fabrication process increasing in structural intricacy and ending with fully fabricated FinFET. Comparative studies between CD-SAXS metrology and other relevant semiconductor dimensional metrologies, particularly CDSEM, CD-AFM and TEM are used to determine physical limits of CD-SAXS approach for advanced semiconductor samples. CD-SAXS experimental tradeoffs, advice for model-dependent analysis and thoughts on the compatibility with a semiconductor manufacturing environment are discussed.« less

Contamination-Free Manufacturing: Tool Component Qualification, Verification and Correlation with Wafers

NASA Astrophysics Data System (ADS)

Tan, Samantha H.; Chen, Ning; Liu, Shi; Wang, Kefei

2003-09-01

As part of the semiconductor industry "contamination-free manufacturing" effort, significant emphasis has been placed on reducing potential sources of contamination from process equipment and process equipment components. Process tools contain process chambers and components that are exposed to the process environment or process chemistry and in some cases are in direct contact with production wafers. Any contamination from these sources must be controlled or eliminated in order to maintain high process yields, device performance, and device reliability. This paper discusses new nondestructive analytical methods for quantitative measurement of the cleanliness of metal, quartz, polysilicon and ceramic components that are used in process equipment tools. The goal of these new procedures is to measure the effectiveness of cleaning procedures and to verify whether a tool component part is sufficiently clean for installation and subsequent routine use in the manufacturing line. These procedures provide a reliable "qualification method" for tool component certification and also provide a routine quality control method for reliable operation of cleaning facilities. Cost advantages to wafer manufacturing include higher yields due to improved process cleanliness and elimination of yield loss and downtime resulting from the installation of "bad" components in process tools. We also discuss a representative example of wafer contamination having been linked to a specific process tool component.

Semiconductor assisted metal deposition for nanolithography applications

DOEpatents

Rajh, Tijana; Meshkov, Natalia; Nedelijkovic, Jovan M.; Skubal, Laura R.; Tiede, David M.; Thurnauer, Marion

2001-01-01

An article of manufacture and method of forming nanoparticle sized material components. A semiconductor oxide substrate includes nanoparticles of semiconductor oxide. A modifier is deposited onto the nanoparticles, and a source of metal ions are deposited in association with the semiconductor and the modifier, the modifier enabling electronic hole scavenging and chelation of the metal ions. The metal ions and modifier are illuminated to cause reduction of the metal ions to metal onto the semiconductor nanoparticles.

Semiconductor assisted metal deposition for nanolithography applications

DOEpatents

Rajh, Tijana; Meshkov, Natalia; Nedelijkovic, Jovan M.; Skubal, Laura R.; Tiede, David M.; Thurnauer, Marion

2002-01-01

An article of manufacture and method of forming nanoparticle sized material components. A semiconductor oxide substrate includes nanoparticles of semiconductor oxide. A modifier is deposited onto the nanoparticles, and a source of metal ions are deposited in association with the semiconductor and the modifier, the modifier enabling electronic hole scavenging and chelation of the metal ions. The metal ions and modifier are illuminated to cause reduction of the metal ions to metal onto the semiconductor nanoparticles.

Jet and flash imprint defectivity: assessment and reduction for semiconductor applications

NASA Astrophysics Data System (ADS)

Malloy, Matt; Litt, Lloyd C.; Johnson, Steve; Resnick, Douglas J.; Lovell, David

2011-04-01

Defectivity has been historically identified as a leading technical roadblock to the implementation of nanoimprint lithography for semiconductor high volume manufacturing. The lack of confidence in nanoimprint's ability to meet defect requirements originates in part from the industry's past experiences with 1X lithography and the shortage in end-user generated defect data. SEMATECH has therefore initiated a defect assessment aimed at addressing these concerns. The goal is to determine whether nanoimprint, specifically Jet and Flash Imprint Lithography from Molecular Imprints, is capable of meeting semiconductor industry defect requirements. At this time, several cycles of learning have been completed in SEMATECH's defect assessment, with promising results. J-FIL process random defectivity of < 0.1 def/cm2 has been demonstrated using a 120nm half-pitch template, providing proof of concept that a low defect nanoimprint process is possible. Template defectivity has also improved significantly as shown by a pre-production grade template at 80nm pitch. Cycles of learning continue on feature sizes down to 22nm.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, Choong Koo; Park, Hyo Jeong; Kim, In Chool

Reserve margins of Korea Electric Power Corporation (KEPCO) was 12% in 1993, however it was reduced to less than 3% in the summer of 1994 due to increase of electric power consumption caused by life style change based on economic growth. Therefore stable supply of electric power to industrial plant was threatened during last summer`s peak. The process of semiconductor manufacturing is very precious and full processing time reaches several months. Furthermore interruption of power supply to the process causes abortion of every product in the process. Therefore, power failure of less than one (1) second, may result in enormousmore » loss of capital. In order to protect disaster caused by power shortage during summer peaks. Samsung Electronics Co., Ltd (SEC) planned to construct LNG combined cycle power plant for the Klheung semiconductor plant which is the world`s leading maker of dynamic random access memory (DRAM) chips.« less

Silicon material technology status. [assessment for electronic and photovoltaic applications

NASA Technical Reports Server (NTRS)

Lutwack, R.

1983-01-01

Silicon has been the basic element for the electronic and photovoltaic industries. The use of silicon as the primary element for terrestrial photovoltaic solar arrays is projected to continue. The reasons for this projection are related to the maturity of silicon technology, the ready availability of extremely pure silicon, the performance of silicon solar cells, and the considerable present investment in technology and manufacturing facilities. The technologies for producing semiconductor grade silicon and, to a lesser extent, refined metallurgical grade silicon are considered. It is pointed out that nearly all of the semiconductor grade silicon is produced by processes based on the Siemens deposition reactor, a technology developed 26 years ago. The state-of-the-art for producing silicon by this process is discussed. It is expected that efforts to reduce polysilicon process costs will continue.

Thermodynamic analysis of resources used in manufacturing processes.

PubMed

Gutowski, Timothy G; Branham, Matthew S; Dahmus, Jeffrey B; Jones, Alissa J; Thiriez, Alexandre

2009-03-01

In this study we use a thermodynamic framework to characterize the material and energy resources used in manufacturing processes. The analysis and data span a wide range of processes from "conventional" processes such as machining, casting, and injection molding, to the so-called "advanced machining" processes such as electrical discharge machining and abrasive waterjet machining, and to the vapor-phase processes used in semiconductor and nanomaterials fabrication. In all, 20 processes are analyzed. The results show that the intensity of materials and energy used per unit of mass of material processed (measured either as specific energy or exergy) has increased by at least 6 orders of magnitude over the past several decades. The increase of material/energy intensity use has been primarily a consequence of the introduction of new manufacturing processes, rather than changes in traditional technologies. This phenomenon has been driven by the desire for precise small-scale devices and product features and enabled by stable and declining material and energy prices over this period. We illustrate the relevance of thermodynamics (including exergy analysis) for all processes in spite of the fact that long-lasting focus in manufacturing has been on product quality--not necessarily energy/material conversion efficiency. We promote the use of thermodynamics tools for analysis of manufacturing processes within the context of rapidly increasing relevance of sustainable human enterprises. We confirm that exergy analysis can be used to identify where resources are lost in these processes, which is the first step in proposing and/or redesigning new more efficient processes.

78 FR 24234 - Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same; Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-24

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-819] Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same; Notice of Request for Statements on the... order barring the entry of unlicensed DRAM semiconductor chips manufactured by Nanya Technology...

All-inkjet-printed flexible ZnO micro photodetector for a wearable UV monitoring device.

PubMed

Tran, Van-Thai; Wei, Yuefan; Yang, Hongyi; Zhan, Zhaoyao; Du, Hejun

2017-03-03

Fabrication of small-sized patterns of inorganic semiconductor onto flexible substrates is a major concern when manufacturing wearable devices for measuring either biometric or environmental parameters. In this study, micro-sized flexible ZnO UV photodetectors have been thoroughly prepared by a facile inkjet printing technology and followed with heat treatments. A simple ink recipe of zinc acetate precursor solution was investigated. It is found that the substrate temperature during zinc precursor ink depositing has significant effects on ZnO pattern shape, film morphology, and crystallization. The device fabricated from the additive manufacturing approach has good bendability, Ohmic contact, short response time as low as 0.3 s, and high on/off ratio of 3525. We observed the sensor's dependence of response/decay time by the illuminating UV light intensity. The whole process is based on additive manufacturing which has many benefits such as rapid prototyping, saving material, being environmentally friendly, and being capable of creating high-resolution patterns. In addition, this method can be applied to flexible substrates, which makes the device more applicable for applications requiring flexibility such as wearable devices. The proposed all-inkjet-printing approach for a micro-sized ZnO UV photodetector would significantly simplify the fabrication process of micro-sized inorganic semiconductor-based devices. A potential application is real-time monitoring of UV light exposure to warn users about unsafe direct sunlight to implement suitable avoidance solutions.

Space processing economics

NASA Technical Reports Server (NTRS)

Bredt, J. H.

1974-01-01

Two types of space processing operations may be considered economically justified; they are manufacturing operations that make profits and experiment operations that provide needed applied research results at lower costs than those of alternative methods. Some examples from the Skylab experiments suggest that applied research should become cost effective soon after the space shuttle and Spacelab become operational. In space manufacturing, the total cost of space operations required to process materials must be repaid by the value added to the materials by the processing. Accurate estimates of profitability are not yet possible because shuttle operational costs are not firmly established and the markets for future products are difficult to estimate. However, approximate calculations show that semiconductor products and biological preparations may be processed on a scale consistent with market requirements and at costs that are at least compatible with profitability using the Shuttle/Spacelab system.

Selective recovery of silver from waste low-temperature co-fired ceramic and valorization through silver nanoparticle synthesis.

PubMed

Swain, Basudev; Shin, Dongyoon; Joo, So Yeong; Ahn, Nak Kyoon; Lee, Chan Gi; Yoon, Jin-Ho

2017-11-01

Considering the value of silver metal and silver nanoparticles, the waste generated during manufacturing of low temperature co-fired ceramic (LTCC) were recycled through the simple yet cost effective process by chemical-metallurgy. Followed by leaching optimization, silver was selectively recovered through precipitation. The precipitated silver chloride was valorized though silver nanoparticle synthesis by a simple one-pot greener synthesis route. Through leaching-precipitation optimization, quantitative selective recovery of silver chloride was achieved, followed by homogeneous pure silver nanoparticle about 100nm size were synthesized. The reported recycling process is a simple process, versatile, easy to implement, requires minimum facilities and no specialty chemicals, through which semiconductor manufacturing industry can treat the waste generated during manufacturing of LTCC and reutilize the valorized silver nanoparticles in manufacturing in a close loop process. Our reported process can address issues like; (i) waste disposal, as well as value-added silver recovery, (ii) brings back the material to production stream and address the circular economy, and (iii) can be part of lower the futuristic carbon economy and cradle-to-cradle technology management, simultaneously. Copyright © 2017 Elsevier Ltd. All rights reserved.

X-ray mask fabrication advancements at the Microlithographic Mask Development Center

NASA Astrophysics Data System (ADS)

Kimmel, Kurt R.; Hughes, Patrick J.

1996-05-01

The Microlithographic Mask Development Center (MMD) was established as the X-ray mask manufacturing facility at the IBM Microelectronics Division semiconductor fabricator in Essex Junction, Vermont. This center, in operation for over two years, produces high yielding, defect-free X-ray masks for competitive logic and memory products at 250nm groundrules and below. The MMD is a complete mask facility that manufactures silicon membrane mask blanks in the NIST format and finished masks with electroplated gold X-ray absorber. Mask patterning, with dimensions as small as 180 nm, is accomplished using IBM-built variable shaped spot e-beam systems. Masks are routinely inspected and repaired using state-of-the-art equipment: two KLA SEM Specs for defect inspection, a Leica LMS 2000 for image placement characterization, an Amray 2040c for image dimension characterization and a Micrion 8000 XMR for defect repair. This facility maintains a baseline mask process with daily production of 250nm, 32Mb SRAM line monitor masks for the continuous improvement of mask quality and processes. Development masks are produced for several semiconductor manufacturers including IBM, Motorola, Loral, and Sanders. Masks for 64Mb and 256Mb DRAM (IBM) and advanced logic/SRAM (IBM and Motorola) designs have also been delivered. This paper describes the MMD facility and its technical capabilities. Key manufacturing metrics such as mask turnaround time, parametric yield learning and defect reduction activities are highlighted. The challenges associated with improved mask quality, sub-180nm mask fabrication, and the transition to refractory metal absorber are discussed.

A solution for exposure tool optimization at the 65-nm node and beyond

NASA Astrophysics Data System (ADS)

Itai, Daisuke

2007-03-01

As device geometries shrink, tolerances for critical dimension, focus, and overlay control decrease. For the stable manufacture of semiconductor devices at (and beyond) the 65nm node, both performance variability and drift in exposure tools are no longer negligible factors. With EES (Equipment Engineering System) as a guidepost, hopes of improving productivity of semiconductor manufacturing are growing. We are developing a system, EESP (Equipment Engineering Support Program), based on the concept of EES. The EESP system collects and stores large volumes of detailed data generated from Canon lithographic equipment while product is being manufactured. It uses that data to monitor both equipment characteristics and process characteristics, which cannot be examined without this system. The goal of EESP is to maximize equipment capabilities, by feeding the result back to APC/FDC and the equipment maintenance list. This was a collaborative study of the system's effectiveness at the device maker's factories. We analyzed the performance variability of exposure tools by using focus residual data. We also attempted to optimize tool performance using the analyzed results. The EESP system can make the optimum performance of exposure tools available to the device maker.

Bi-Se doped with Cu, p-type semiconductor

DOEpatents

Bhattacharya, Raghu Nath; Phok, Sovannary; Parilla, Philip Anthony

2013-08-20

A Bi--Se doped with Cu, p-type semiconductor, preferably used as an absorber material in a photovoltaic device. Preferably the semiconductor has at least 20 molar percent Cu. In a preferred embodiment, the semiconductor comprises at least 28 molar percent of Cu. In one embodiment, the semiconductor comprises a molar percentage of Cu and Bi whereby the molar percentage of Cu divided by the molar percentage of Bi is greater than 1.2. In a preferred embodiment, the semiconductor is manufactured as a thin film having a thickness less than 600 nm.

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

PubMed Central

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

Progress in nanoscale dry processes for fabrication of high-aspect-ratio features: How can we control critical dimension uniformity at the bottom?

NASA Astrophysics Data System (ADS)

Ishikawa, Kenji; Karahashi, Kazuhiro; Ishijima, Tatsuo; Cho, Sung Il; Elliott, Simon; Hausmann, Dennis; Mocuta, Dan; Wilson, Aaron; Kinoshita, Keizo

2018-06-01

In this review, we discuss the progress of emerging dry processes for nanoscale fabrication of high-aspect-ratio features, including emerging design technology for manufacturability. Experts in the fields of plasma processing have contributed to addressing the increasingly challenging demands of nanoscale deposition and etching technologies for high-aspect-ratio features. The discussion of our atomic-scale understanding of physicochemical reactions involving ion bombardment and neutral transport presents the major challenges shared across the plasma science and technology community. Focus is placed on advances in fabrication technology that control surface reactions on three-dimensional features, as well as state-of-the-art techniques used in semiconductor manufacturing with a brief summary of future challenges.

Process Challenges in Compound Semiconductors.

DTIC Science & Technology

1988-08-01

dielectric films , and metallization. It became evident during this examination that a major obstacle to the affordable, high-yield manufacture of...in surrounding regions. In both of the structures shown, the curvature of the layers is the characteristic solidification from solution in LPE ...pseudomorphic epitaxial growth is possible only with very thin films in which the structure is strained to match the lattice parameter of the

Reporting of occupational injury and illness in the semiconductor manufacturing industry.

PubMed

McCurdy, S A; Schenker, M B; Samuels, S J

1991-01-01

In the United States, occupational illness and injury cases meeting specific reporting criteria are recorded on company Occupational Safety and Health Administration (OSHA) 200 logs; case description data are submitted to participating state agencies for coding and entry in the national Supplementary Data System (SDS). We evaluated completeness of reporting (the percentage of reportable cases that were recorded in the company OSHA 200 log) in the semiconductor manufacturing industry by reviewing company health clinic records for 1984 of 10 manufacturing sites of member companies of a national semiconductor manufacturing industry trade association. Of 416 randomly selected work-related cases, 101 met OSHA reporting criteria. Reporting completeness was 60 percent and was lowest for occupational illnesses (44 percent). Case-description data from 150 reported cases were submitted twice to state coding personnel to evaluate coding reliability. Reliability was high (kappa 0.82-0.93) for "nature," "affected body part," "source," and "type" variables. Coding for the SDS appears reliable; reporting completeness may be improved by use of a stepwise approach by company personnel responsible for reporting decisions.

Application of laser spot cutting on spring contact probe for semiconductor package inspection

NASA Astrophysics Data System (ADS)

Lee, Dongkyoung; Cho, Jungdon; Kim, Chan Ho; Lee, Seung Hwan

2017-12-01

A packaged semiconductor has to be electrically tested to make sure they are free of any manufacturing defects. The test interface, typically employed between a Printed Circuit Board and the semiconductor devices, consists of densely populated Spring Contact Probe (SCP). A standard SCP typically consists of a plunger, a barrel, and an internal spring. Among these components, plungers are manufactured by a stamping process. After stamping, plunger connecting arms need to be cut into pieces. Currently, mechanical cutting has been used. However, it may damage to the body of plungers due to the mechanical force engaged at the cutting point. Therefore, laser spot cutting is considered to solve this problem. The plunger arm is in the shape of a rectangular beam, 50 μm (H) × 90 μm (W). The plunger material used for this research is gold coated beryllium copper. Laser parameters, such as power and elapsed time, have been selected to study laser spot cutting. Laser material interaction characteristics such as a crater size, material removal zone, ablation depth, ablation threshold, and full penetration are observed. Furthermore, a carefully chosen laser parameter (Etotal = 1000mJ) to test feasibility of laser spot cutting are applied. The result show that laser spot cutting can be applied to cut SCP.

A modular assembling platform for manufacturing of microsystems by optical tweezers

NASA Astrophysics Data System (ADS)

Ksouri, Sarah Isabelle; Aumann, Andreas; Ghadiri, Reza; Prüfer, Michael; Baer, Sebastian; Ostendorf, Andreas

2013-09-01

Due to the increased complexity in terms of materials and geometries for microsystems new assembling techniques are required. Assembling techniques from the semiconductor industry are often very specific and cannot fulfill all specifications in more complex microsystems. Therefore, holographic optical tweezers are applied to manipulate structures in micrometer range with highest flexibility and precision. As is well known non-spherical assemblies can be trapped and controlled by laser light and assembled with an additional light modulator application, where the incident laser beam is rearranged into flexible light patterns in order to generate multiple spots. The complementary building blocks are generated by a two-photon-polymerization process. The possibilities of manufacturing arbitrary microstructures and the potential of optical tweezers lead to the idea of combining manufacturing techniques with manipulation processes to "microrobotic" processes. This work presents the manipulation of generated complex microstructures with optical tools as well as a storage solution for 2PP assemblies. A sample holder has been developed for the manual feeding of 2PP building blocks. Furthermore, a modular assembling platform has been constructed for an `all-in-one' 2PP manufacturing process as a dedicated storage system. The long-term objective is the automation process of feeding and storage of several different 2PP micro-assemblies to realize an automated assembly process.

Photoelectrochemical cells for conversion of solar energy to electricity and methods of their manufacture

DOEpatents

Skotheim, Terje

1984-04-10

A photoelectric device is disclosed which comprises first and second layers of semiconductive material, each of a different bandgap, with a layer of dry solid polymer electrolyte disposed between the two semiconductor layers. A layer of a polymer blend of a highly conductive polymer and a solid polymer electrolyte is further interposed between the dry solid polymer electrolyte and the first semiconductor layer. A method of manufacturing such devices is also disclosed.

Educating Tomorrow's Workforce: A Report on the Semiconductor Industry's Commitment to Youth in K-12.

ERIC Educational Resources Information Center

Semiconductor Industry Association, San Jose, CA.

The U.S. semiconductor industry, now the nation's largest manufacturing industry, displays its commitment to training its current workers and educating future workers by supporting educational efforts on the K-12 level. This catalog describes innovative actions by 16 Semiconductor Industry Association companies to improve education at the K-12…

Manufacturing Demonstration Facility: Roll-to-Roll Processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Datskos, Panos G; Joshi, Pooran C; List III, Frederick Alyious

This Manufacturing Demonstration Facility (MDF)e roll-to-roll processing effort described in this report provided an excellent opportunity to investigate a number of advanced manufacturing approaches to achieve a path for low cost devices and sensors. Critical to this effort is the ability to deposit thin films at low temperatures using nanomaterials derived from nanofermentation. The overarching goal of this project was to develop roll-to-roll manufacturing processes of thin film deposition on low-cost flexible substrates for electronics and sensor applications. This project utilized ORNL s unique Pulse Thermal Processing (PTP) technologies coupled with non-vacuum low temperature deposition techniques, ORNL s clean roommore » facility, slot dye coating, drop casting, spin coating, screen printing and several other equipment including a Dimatix ink jet printer and a large-scale Kyocera ink jet printer. The roll-to-roll processing project had three main tasks: 1) develop and demonstrate zinc-Zn based opto-electronic sensors using low cost nanoparticulate structures manufactured in a related MDF Project using nanofermentation techniques, 2) evaluate the use of silver based conductive inks developed by project partner NovaCentrix for electronic device fabrication, and 3) demonstrate a suite of low cost printed sensors developed using non-vacuum deposition techniques which involved the integration of metal and semiconductor layers to establish a diverse sensor platform technology.« less

Launching the dialogue: Safety and innovation as partners for success in advanced manufacturing.

PubMed

Geraci, C L; Tinkle, S S; Brenner, S A; Hodson, L L; Pomeroy-Carter, C A; Neu-Baker, N

2018-06-01

Emerging and novel technologies, materials, and information integrated into increasingly automated and networked manufacturing processes or into traditional manufacturing settings are enhancing the efficiency and productivity of manufacturing. Globally, there is a move toward a new era in manufacturing that is characterized by: (1) the ability to create and deliver more complex designs of products; (2) the creation and use of materials with new properties that meet a design need; (3) the employment of new technologies, such as additive and digital techniques that improve on conventional manufacturing processes; and (4) a compression of the time from initial design concept to the creation of a final product. Globally, this movement has many names, but "advanced manufacturing" has become the shorthand for this complex integration of material and technology elements that enable new ways to manufacture existing products, as well as new products emerging from new technologies and new design methods. As the breadth of activities associated with advanced manufacturing suggests, there is no single advanced manufacturing industry. Instead, aspects of advanced manufacturing can be identified across a diverse set of business sectors that use manufacturing technologies, ranging from the semiconductors and electronics to the automotive and pharmaceutical industries. The breadth and diversity of advanced manufacturing may change the occupational and environmental risk profile, challenge the basic elements of comprehensive health and safety (material, process, worker, environment, product, and general public health and safety), and provide an opportunity for development and dissemination of occupational and environmental health and safety (OEHS) guidance and best practices. It is unknown how much the risk profile of different elements of OEHS will change, thus requiring an evolution of health and safety practices. These changes may be accomplished most effectively through multi-disciplinary, multi-sector, public-private dialogue that identifies issues and offers solutions.

Power module packaging with double sided planar interconnection and heat exchangers

DOEpatents

Liang, Zhenxian; Marlino, Laura D.; Ning, Puqi; Wang, Fei

2015-05-26

A double sided cooled power module package having a single phase leg topology includes two IGBT and two diode semiconductor dies. Each IGBT die is spaced apart from a diode semiconductor die, forming a switch unit. Two switch units are placed in a planar face-up and face-down configuration. A pair of DBC or other insulated metallic substrates is affixed to each side of the planar phase leg semiconductor dies to form a sandwich structure. Attachment layers are disposed on outer surfaces of the substrates and two heat exchangers are affixed to the substrates by rigid bond layers. The heat exchangers, made of copper or aluminum, have passages for carrying coolant. The power package is manufactured in a two-step assembly and heating process where direct bonds are formed for all bond layers by soldering, sintering, solid diffusion bonding or transient liquid diffusion bonding, with a specially designed jig and fixture.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

40 CFR 63.5935 - What definitions apply to this subpart?

Code of Federal Regulations, 2010 CFR

2010-07-01

... plating; semiconductor manufacturing; petroleum production, refining, and storage; mining; textile... manufacture, it must be used for repair or replacement, and the manufacturing schedule must be based on the... National Emissions Standards for Hazardous Air Pollutants: Reinforced Plastic Composites Production Other...

Submillimeter Spectroscopic Study of Semiconductor Processing Plasmas

NASA Astrophysics Data System (ADS)

Helal, Yaser H.

Plasmas used for manufacturing processes of semiconductor devices are complex and challenging to characterize. The development and improvement of plasma processes and models rely on feedback from experimental measurements. Current diagnostic methods are not capable of measuring absolute densities of plasma species with high resolution without altering the plasma, or without input from other measurements. At pressures below 100 mTorr, spectroscopic measurements of rotational transitions in the submillimeter/terahertz (SMM) spectral region are narrow enough in relation to the sparsity of spectral lines that absolute specificity of measurement is possible. The frequency resolution of SMM sources is such that spectral absorption features can be fully resolved. Processing plasmas are a similar pressure and temperature to the environment used to study astrophysical species in the SMM spectral region. Many of the molecular neutrals, radicals, and ions present in processing plasmas have been studied in the laboratory and their absorption spectra have been cataloged or are in the literature for the purpose of astrophysical study. Recent developments in SMM devices have made its technology commercially available for applications outside of specialized laboratories. The methods developed over several decades in the SMM spectral region for these laboratory studies are directly applicable for diagnostic measurements in the semiconductor manufacturing industry. In this work, a continuous wave, intensity calibrated SMM absorption spectrometer was developed as a remote sensor of gas and plasma species. A major advantage of intensity calibrated rotational absorption spectroscopy is its ability to determine absolute concentrations and temperatures of plasma species from first principles without altering the plasma environment. An important part of this work was the design of the optical components which couple 500 - 750 GHz radiation through a commercial inductively coupled plasma chamber. The measurement of transmission spectra was simultaneously fit for background and absorption signal. The measured absorption signal was used to calculate absolute densities and temperatures of polar species. Measurements of molecular species were demonstrated for inductively coupled plasmas.

Capital investment in semiconductors: The lifeblood of the US semiconductor industry

NASA Astrophysics Data System (ADS)

Finan, William F.

1990-09-01

An analysis is given of four proposals designed to improve capital formation for U.S. industry in general, and the semiconductor industry in particular. The National Advisory Committee on Semiconductors recommendations were to make the current research and experimentation (R and E) tax credit more effective, to reduce taxes on capital gains, to increase personal savings incentives, and to improve semiconductor manufacturing equipment depreciation rules. The results of the qualitative analysis of the proposals as well as a description of the methodology employed are given.

Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

NASA Astrophysics Data System (ADS)

Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

2003-07-01

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

All-inkjet-printed flexible ZnO micro photodetector for a wearable UV monitoring device

NASA Astrophysics Data System (ADS)

Tran, Van-Thai; Wei, Yuefan; Yang, Hongyi; Zhan, Zhaoyao; Du, Hejun

2017-03-01

Fabrication of small-sized patterns of inorganic semiconductor onto flexible substrates is a major concern when manufacturing wearable devices for measuring either biometric or environmental parameters. In this study, micro-sized flexible ZnO UV photodetectors have been thoroughly prepared by a facile inkjet printing technology and followed with heat treatments. A simple ink recipe of zinc acetate precursor solution was investigated. It is found that the substrate temperature during zinc precursor ink depositing has significant effects on ZnO pattern shape, film morphology, and crystallization. The device fabricated from the additive manufacturing approach has good bendability, Ohmic contact, short response time as low as 0.3 s, and high on/off ratio of 3525. We observed the sensor’s dependence of response/decay time by the illuminating UV light intensity. The whole process is based on additive manufacturing which has many benefits such as rapid prototyping, saving material, being environmentally friendly, and being capable of creating high-resolution patterns. In addition, this method can be applied to flexible substrates, which makes the device more applicable for applications requiring flexibility such as wearable devices. The proposed all-inkjet-printing approach for a micro-sized ZnO UV photodetector would significantly simplify the fabrication process of micro-sized inorganic semiconductor-based devices. A potential application is real-time monitoring of UV light exposure to warn users about unsafe direct sunlight to implement suitable avoidance solutions.

Dimension Reduction of Multivariable Optical Emission Spectrometer Datasets for Industrial Plasma Processes

PubMed Central

Yang, Jie; McArdle, Conor; Daniels, Stephen

2014-01-01

A new data dimension-reduction method, called Internal Information Redundancy Reduction (IIRR), is proposed for application to Optical Emission Spectroscopy (OES) datasets obtained from industrial plasma processes. For example in a semiconductor manufacturing environment, real-time spectral emission data is potentially very useful for inferring information about critical process parameters such as wafer etch rates, however, the relationship between the spectral sensor data gathered over the duration of an etching process step and the target process output parameters is complex. OES sensor data has high dimensionality (fine wavelength resolution is required in spectral emission measurements in order to capture data on all chemical species involved in plasma reactions) and full spectrum samples are taken at frequent time points, so that dynamic process changes can be captured. To maximise the utility of the gathered dataset, it is essential that information redundancy is minimised, but with the important requirement that the resulting reduced dataset remains in a form that is amenable to direct interpretation of the physical process. To meet this requirement and to achieve a high reduction in dimension with little information loss, the IIRR method proposed in this paper operates directly in the original variable space, identifying peak wavelength emissions and the correlative relationships between them. A new statistic, Mean Determination Ratio (MDR), is proposed to quantify the information loss after dimension reduction and the effectiveness of IIRR is demonstrated using an actual semiconductor manufacturing dataset. As an example of the application of IIRR in process monitoring/control, we also show how etch rates can be accurately predicted from IIRR dimension-reduced spectral data. PMID:24451453

Interface design for CMOS-integrated Electrochemical Impedance Spectroscopy (EIS) biosensors.

PubMed

Manickam, Arun; Johnson, Christopher Andrew; Kavusi, Sam; Hassibi, Arjang

2012-10-29

Electrochemical Impedance Spectroscopy (EIS) is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs) that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

Developing quartz wafer mold manufacturing process for patterned media

NASA Astrophysics Data System (ADS)

Chiba, Tsuyoshi; Fukuda, Masaharu; Ishikawa, Mikio; Itoh, Kimio; Kurihara, Masaaki; Hoga, Morihisa

2009-04-01

Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

15 CFR 700.15 - Extension of priority ratings.

Code of Federal Regulations, 2011 CFR

2011-01-01

... receipt of a DO-A3 rated order for a navigation system and needs to purchase semiconductors for its manufacture, that person must use a DO-A3 rated order to obtain the needed semiconductors. (b) The priority...

Laser processing of ceramics for microelectronics manufacturing

NASA Astrophysics Data System (ADS)

Sposili, Robert S.; Bovatsek, James; Patel, Rajesh

2017-03-01

Ceramic materials are used extensively in the microelectronics, semiconductor, and LED lighting industries because of their electrically insulating and thermally conductive properties, as well as for their high-temperature-service capabilities. However, their brittleness presents significant challenges for conventional machining processes. In this paper we report on a series of experiments that demonstrate and characterize the efficacy of pulsed nanosecond UV and green lasers in machining ceramics commonly used in microelectronics manufacturing, such as aluminum oxide (alumina) and aluminum nitride. With a series of laser pocket milling experiments, fundamental volume ablation rate and ablation efficiency data were generated. In addition, techniques for various industrial machining processes, such as shallow scribing and deep scribing, were developed and demonstrated. We demonstrate that lasers with higher average powers offer higher processing rates with the one exception of deep scribes in aluminum nitride, where a lower average power but higher pulse energy source outperformed a higher average power laser.

Fabrication of Circuit QED Quantum Processors, Part 2: Advanced Semiconductor Manufacturing Perspectives

NASA Astrophysics Data System (ADS)

Michalak, D. J.; Bruno, A.; Caudillo, R.; Elsherbini, A. A.; Falcon, J. A.; Nam, Y. S.; Poletto, S.; Roberts, J.; Thomas, N. K.; Yoscovits, Z. R.; Dicarlo, L.; Clarke, J. S.

Experimental quantum computing is rapidly approaching the integration of sufficient numbers of quantum bits for interesting applications, but many challenges still remain. These challenges include: realization of an extensible design for large array scale up, sufficient material process control, and discovery of integration schemes compatible with industrial 300 mm fabrication. We present recent developments in extensible circuits with vertical delivery. Toward the goal of developing a high-volume manufacturing process, we will present recent results on a new Josephson junction process that is compatible with current tooling. We will then present the improvements in NbTiN material uniformity that typical 300 mm fabrication tooling can provide. While initial results on few-qubit systems are encouraging, advanced processing control is expected to deliver the improvements in qubit uniformity, coherence time, and control required for larger systems. Research funded by Intel Corporation.

Dry etching technologies for the advanced binary film

NASA Astrophysics Data System (ADS)

Iino, Yoshinori; Karyu, Makoto; Ita, Hirotsugu; Yoshimori, Tomoaki; Azumano, Hidehito; Muto, Makoto; Nonaka, Mikio

2011-11-01

ABF (Advanced Binary Film) developed by Hoya as a photomask for 32 (nm) and larger specifications provides excellent resistance to both mask cleaning and 193 (nm) excimer laser and thereby helps extend the lifetime of the mask itself compared to conventional photomasks and consequently reduces the semiconductor manufacturing cost [1,2,3]. Because ABF uses Ta-based films, which are different from Cr film or MoSi films commonly used for photomask, a new process is required for its etching technology. A patterning technology for ABF was established to perform the dry etching process for Ta-based films by using the knowledge gained from absorption layer etching for EUV mask that required the same Ta-film etching process [4]. Using the mask etching system ARES, which is manufactured by Shibaura Mechatronics, and its optimized etching process, a favorable CD (Critical Dimension) uniformity, a CD linearity and other etching characteristics were obtained in ABF patterning. Those results are reported here.

Environmental and workplace contamination in the semiconductor industry: implications for future health of the workforce and community.

PubMed Central

Edelman, P

1990-01-01

The semiconductor industry has been an enormous worldwide growth industry. At the heart of computer and other electronic technological advances, the environment in and around these manufacturing facilities has not been scrutinized to fully detail the health effects to the workers and the community from such exposures. Hazard identification in this industry leads to the conclusion that there are many sources of potential exposure to chemicals including arsenic, solvents, photoactive polymers and other materials. As the size of the semiconductor work force expands, the potential for adverse health effects, ranging from transient irritant symptoms to reproductive effects and cancer, must be determined and control measures instituted. Risk assessments need to be effected for areas where these facilities conduct manufacturing. The predominance of women in the manufacturing areas requires evaluating the exposures to reproductive hazards and outcomes. Arsenic exposures must also be evaluated and minimized, especially for maintenance workers; evaluation for lung and skin cancers is also appropriate. PMID:2401268

Alternating phase-shifted mask for logic gate levels, design, and mask manufacturing

NASA Astrophysics Data System (ADS)

Liebmann, Lars W.; Graur, Ioana C.; Leipold, William C.; Oberschmidt, James M.; O'Grady, David S.; Regaill, Denis

1999-07-01

While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBM's Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBM's internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBM's internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.

An integrated semiconductor device enabling non-optical genome sequencing.

PubMed

Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

2011-07-20

The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

From Bell Labs to Silicon Valley: A Saga of Technology Transfer, 1954-1961

NASA Astrophysics Data System (ADS)

Riordan, Michael

2009-03-01

Although Bell Telephone Laboratories invented the transistor and developed most of the associated semiconductor technology, the integrated circuit or microchip emerged elsewhere--at Texas Instruments and Fairchild Semiconductor Company. I recount how the silicon technology required to make microchips possible was first developed at Bell Labs in the mid-1950s. Much of it reached the San Francisco Bay Area when transistor pioneer William Shockley left Bell Labs in 1955 to establish the Shockley Semiconductor Laboratory in Mountain View, hiring a team of engineers and scientists to develop and manufacture transistors and related semiconductor devices. But eight of them--including Gordon Moore and Robert Noyce, eventually the co-founders of Intel--resigned en masse in September 1957 to start Fairchild, bringing with them the scientific and technological expertise they had acquired and further developed at Shockley's firm. This event marked the birth of Silicon Valley, both technologically and culturally. By March 1961 the company was marketing its Micrologic integrated circuits, the first commercial silicon microchips, based on the planar processing technique developed at Fairchild by Jean Hoerni.

Organic transistors manufactured using inkjet technology with subfemtoliter accuracy

PubMed Central

Sekitani, Tsuyoshi; Noguchi, Yoshiaki; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2008-01-01

A major obstacle to the development of organic transistors for large-area sensor, display, and circuit applications is the fundamental compromise between manufacturing efficiency, transistor performance, and power consumption. In the past, improving the manufacturing efficiency through the use of printing techniques has inevitably resulted in significantly lower performance and increased power consumption, while attempts to improve performance or reduce power have led to higher process temperatures and increased manufacturing cost. Here, we lift this fundamental limitation by demonstrating subfemtoliter inkjet printing to define metal contacts with single-micrometer resolution on the surface of high-mobility organic semiconductors to create high-performance p-channel and n-channel transistors and low-power complementary circuits. The transistors employ an ultrathin low-temperature gate dielectric based on a self-assembled monolayer that allows transistors and circuits on rigid and flexible substrates to operate with very low voltages. PMID:18362348

HVM die yield improvement as a function of DRSEM ADC

NASA Astrophysics Data System (ADS)

Maheshwary, Sonu; Haas, Terry; McGarvey, Steve

2010-03-01

Given the current manufacturing technology roadmap and the competitiveness of the global semiconductor manufacturing environment in conjunction with the semiconductor manufacturing market dynamics, the market place continues to demand a reduced die manufacturing cost. This continuous pressure on lowering die cost in turn drives an aggressive yield learning curve, a key component of which is defect reduction of manufacturing induced anomalies. In order to meet and even exceed line and die yield targets there is a need to revamp defect classification strategies and place a greater emphasize on increasing the accuracy and purity of the Defect Review Scanning Electron Microscope (DRSEM) Automated Defect Classification (ADC) results while placing less emphasis on the ADC results of patterned/un-patterned wafer inspection systems. The increased emphasis on DRSEM ADC results allows for a high degree of automation and consistency in the classification data and eliminates variance induced by the manufacturing staff. This paper examines the use of SEM based Auto Defect Classification in a high volume manufacturing environment as a key driver in the reduction of defect limited yields.

New method of contour-based mask-shape compiler

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Sugiyama, Akiyuki; Onizawa, Akira; Sato, Hidetoshi; Toyoda, Yasutaka

2007-10-01

We have developed a new method of accurately profiling a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, it is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method for a DFM solution in which two dimensional data are extracted for an error free practical simulation by precise reproduction of a real mask shape in addition to the mask data simulation. The flow centering around the design data is fully automated and provides an environment where optimization and verification for fully automated model calibration with much less error is available. It also allows complete consolidation of input and output functions with an EDA system by constructing a design data oriented system structure. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Hydrogen fluoride (HF) substance flow analysis for safe and sustainable chemical industry.

PubMed

Kim, Junbeum; Hwang, Yongwoo; Yoo, Mijin; Chen, Sha; Lee, Ik-Mo

2017-11-01

In this study, the chemical substance flow of hydrogen fluoride (hydrofluoric acid, HF) in domestic chemical industries in 2014 was analyzed in order to provide a basic material and information for the establishment of organized management system to ensure safety during HF applications. A total of 44,751 tons of HF was made by four domestic companies (in 2014); import amount was 95,984 tons in 2014 while 21,579 tons of HF was imported in 2005. The export amount of HF was 2180 tons, of which 2074 ton (China, 1422 tons, U.S. 524 tons, and Malaysia, 128 tons) was exported for the manufacturing of semiconductors. Based on the export and import amounts, it can be inferred that HF was used for manufacturing semiconductors. The industries applications of 161,123 tons of HF were as follows: manufacturing of basic inorganic chemical substance (27,937 tons), manufacturing of other chemical products such as detergents (28,208 tons), manufacturing of flat display (24,896 tons), and manufacturing of glass container package (22,002 tons). In this study, an analysis of the chemical substance flow showed that HF was mainly used in the semiconductor industry as well as glass container manufacturing. Combined with other risk management tools and approaches in the chemical industry, the chemical substance flow analysis (CSFA) can be a useful tool and method for assessment and management. The current CSFA results provide useful information for policy making in the chemical industry and national systems. Graphical abstract Hydrogen fluoride chemical substance flows in 2014 in South Korea.

A miniature electronic nose system based on an MWNT-polymer microsensor array and a low-power signal-processing chip.

PubMed

Chiu, Shih-Wen; Wu, Hsiang-Chiu; Chou, Ting-I; Chen, Hsin; Tang, Kea-Tiong

2014-06-01

This article introduces a power-efficient, miniature electronic nose (e-nose) system. The e-nose system primarily comprises two self-developed chips, a multiple-walled carbon nanotube (MWNT)-polymer based microsensor array, and a low-power signal-processing chip. The microsensor array was fabricated on a silicon wafer by using standard photolithography technology. The microsensor array comprised eight interdigitated electrodes surrounded by SU-8 "walls," which restrained the material-solvent liquid in a defined area of 650 × 760 μm(2). To achieve a reliable sensor-manufacturing process, we used a two-layer deposition method, coating the MWNTs and polymer film as the first and second layers, respectively. The low-power signal-processing chip included array data acquisition circuits and a signal-processing core. The MWNT-polymer microsensor array can directly connect with array data acquisition circuits, which comprise sensor interface circuitry and an analog-to-digital converter; the signal-processing core consists of memory and a microprocessor. The core executes the program, classifying the odor data received from the array data acquisition circuits. The low-power signal-processing chip was designed and fabricated using the Taiwan Semiconductor Manufacturing Company 0.18-μm 1P6M standard complementary metal oxide semiconductor process. The chip consumes only 1.05 mW of power at supply voltages of 1 and 1.8 V for the array data acquisition circuits and the signal-processing core, respectively. The miniature e-nose system, which used a microsensor array, a low-power signal-processing chip, and an embedded k-nearest-neighbor-based pattern recognition algorithm, was developed as a prototype that successfully recognized the complex odors of tincture, sorghum wine, sake, whisky, and vodka.

76 FR 63281 - Foreign-Trade Zone 78-Nashville, TN, Application for Subzone, Hemlock Semiconductor, L.L.C...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-12

... DEPARTMENT OF COMMERCE Foreign-Trade Zones Board [Docket 62-2011] Foreign-Trade Zone 78--Nashville, TN, Application for Subzone, Hemlock Semiconductor, L.L.C. (Polysilicon); Clarksville, TN An... polysilicon manufacturing facility of [[Page 63282

Tuning exchange interactions in organometallic semiconductors

NASA Astrophysics Data System (ADS)

Rawat, Naveen; Manning, Lane W.; Hua, Kim-Ngan; Headrick, Randall L.; Cherian, Judy G.; Bishop, Michael M.; McGill, Stephen A.; Furis, Madalina I.

2015-09-01

Organic semiconductors are emerging as a leading area of research as they are expected to overcome limitations of inorganic semiconductor devices for certain applications where low cost manufacturing, device transparency in the visible range or mechanical flexibility are more important than fast switching times. Solution processing methods produce thin films with millimeter sized crystalline grains at very low cost manufacturing prices, ideally suited for optical spectroscopy investigations of long range many-body effects in organic systems. To this end, we synthesized an entire family of organosoluble 3-d transition metal Pc's and successfully employed a novel solution-based pen-writing deposition technique to fabricate long range ordered thin films of mixtures of metal-free (H2Pc) molecule and organometallic phthalocyanines (MPc's). Our previous studies on the parent MPc crystalline thin films identified different electronic states mediating exchange interactions in these materials. This understanding of spin-dependent exchange interaction between delocalized π-electrons with unpaired d spins enabled the further tuning of these interactions by mixing CoPc and H2Pc in different ratios ranging from 1:1 to 1000:1 H2Pc:MPc. The magnitude of the exchange is also tunable as a function of the average distance between unpaired spins in these materials. Furthermore, high magnetic field (B < 25T) MCD and magneto-photoluminescence show evidence of spin-polarized band-edge excitons in the same materials.

Engineering English and the High-Tech Industry: A Case Study of an English Needs Analysis of Process Integration Engineers at a Semiconductor Manufacturing Company in Taiwan

ERIC Educational Resources Information Center

Spence, Paul; Liu, Gi-Zen

2013-01-01

The global high-tech industry is characterized by extreme competitiveness, innovation, and widespread use of English. Consequently, Taiwanese high-tech companies require engineers that are talented in both their engineering and English abilities. In response to the lack of knowledge regarding the English skills needed by engineers in Taiwan's…

Process tool monitoring and matching using interferometry technique

NASA Astrophysics Data System (ADS)

Anberg, Doug; Owen, David M.; Mileham, Jeffrey; Lee, Byoung-Ho; Bouche, Eric

2016-03-01

The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today's manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield. In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.

Hypersonic Composites Resist Extreme Heat and Stress

NASA Technical Reports Server (NTRS)

2007-01-01

Through research contracts with NASA, Materials and Electrochemical Research Corporation (MER), of Tucson, Arizona, contributed a number of technologies to record-breaking hypersonic flights. Through this research, MER developed a coating that successfully passed testing to simulate Mach 10 conditions, as well as provide several additional carbon-carbon (C-C) composite components for the flights. MER created all of the leading edges for the X-43A test vehicles at Dryden-considered the most critical parts of this experimental craft. In addition to being very heat resistant, the coating had to be very lightweight and thin, as the aircraft was designed to very precise specifications and could not afford to have a bulky coating. MER patented its carbon-carbon (C-C) composite process and then formed a spinoff company, Frontier Materials Corporation (FMC), also based in Tucson. FMC is using the patent in conjunction with low-cost PAN (polyacrylonitrile)-based fibers to introduce these materials to the commercial markets. The C-C composites are very lightweight and exceptionally strong and stiff, even at very high temperatures. The composites have been used in industrial heating applications, the automotive and aerospace industries, as well as in glass manufacturing and on semiconductors. Applications also include transfer components for glass manufacturing and structural members for carrier support in semiconductor processing.

Visualization and minimization of clustering of micro-pillars and walls due to liquid film evaporation

NASA Astrophysics Data System (ADS)

Kim, Tae-Hong; Kim, Jungchul; Kim, Ho-Young

2013-11-01

The spin drying, in which a rinsing liquid deposited on a wafer is rapidly dried by wafer spinning, is an essential step in the semiconductor manufacturing process. While the liquid evaporates, its meniscus straddles neighboring submicron-size patterns such as pillars and walls. Then the capillary effects that pull the patterns together may lead to direct contact of the patterns, which is often referred to as pattern leaning. This poses a problem becoming more and more serious as the pattern size shrinks and the aspect ratio of the patterns increases. While the clustering behavior of high-aspect-ratio micro- and nanopillars was investigated before, a technical strategy to prevent such clustering has been pursed in industrial practices without being supported by the recently established theory of elastocapillarity. Here we visualize the clustering behavior of polymer micropatterns with the evaporation of liquid film while varying the sizes and temperature of the micropatterns. We find a critical role of substrate temperature in preventing the leaning of the patterns via changing the evaporation rate and behavior of the liquid film. Also, we construct a regime map that guides us to find a process condition to avoid pattern leaning in semiconductor manufacturing. This work was supported by the National Research Foundation of Korea (grant no. 2012-008023).

Rare resource supply crisis and solution technology for semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Fukuda, Hitomi; Hu, Sophia; Yoo, Youngsun; Takahisa, Kenji; Enami, Tatsuo

2016-03-01

There are growing concerns over future environmental impact and earth resource shortage throughout the world and in many industries. Our semiconductor industry is not excluded. "Green" has become an important topic as production volume become larger and more powerful. Especially, the rare gases are widely used in semiconductor manufacturing because of its inertness and extreme chemical stability. One major component of an Excimer laser system is Neon. It is used as a buffer gas for Argon (Ar) and Krypton (Kr) gases used in deep ultraviolet (DUV) lithography laser systems. Since Neon gas accounting for more than 96% of the laser gas mixture, a fairly large amount of neon gas is consumed to run these DUV lasers. However, due to country's instability both in politics and economics in Ukraine, the main producer of neon gas today, supply reduction has become an issue and is causing increasing concern. This concern is not only based on price increases, but has escalated to the point of supply shortages in 2015. This poses a critical situation for the semiconductor industry, which represents the leading consumer of neon gas in the world. Helium is another noble gas used for Excimer laser operation. It is used as a purge gas for optical component modules to prevent from being damaged by active gases and impurities. Helium has been used in various industries, including for medical equipment, linear motor cars, and semiconductors, and is indispensable for modern life. But consumption of helium in manufacturing has been increased dramatically, and its unstable supply and price rise has been a serious issue today. In this article, recent global supply issue of rare resources, especially Neon gas and Helium gas, and its solution technology to support semiconductor industry will be discussed.

A Self-Aligned InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated through a Lift-Off-Free Front-End Process

NASA Astrophysics Data System (ADS)

Lin, Jianqiang; Kim, Tae-Woo; Antoniadis, Dimitri A.; del Alamo, Jesús A.

2012-06-01

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm2 V-1 s-1.

Metrology needs for the semiconductor industry over the next decade

NASA Astrophysics Data System (ADS)

Melliar-Smith, Mark; Diebold, Alain C.

1998-11-01

Metrology will continue to be a key enabler for the development and manufacture of future generations of integrated circuits. During 1997, the Semiconductor Industry Association renewed the National Technology Roadmap for Semiconductors (NTRS) through the 50 nm technology generation and for the first time included a Metrology Roadmap (1). Meeting the needs described in the Metrology Roadmap will be both a technological and financial challenge. In an ideal world, metrology capability would be available at the start of process and tool development, and silicon suppliers would have 450 mm wafer capable metrology tools in time for development of that wafer size. Unfortunately, a majority of the metrology suppliers are small companies that typically can't afford the additional two to three year wait for return on R&D investment. Therefore, the success of the semiconductor industry demands that we expand cooperation between NIST, SEMATECH, the National Labs, SRC, and the entire community. In this paper, we will discuss several critical metrology topics including the role of sensor-based process control, in-line microscopy, focused measurements for transistor and interconnect fabrication, and development needs. Improvements in in-line microscopy must extend existing critical dimension measurements up to 100 nm generations and new methods may be required for sub 100 nm generations. Through development, existing metrology dielectric thickness and dopant dose and junction methods can be extended to 100 nm, but new and possibly in-situ methods are needed beyond 100 nm. Interconnect process control will undergo change before 100 nm due to the introduction of copper metallization, low dielectric constant interlevel dielectrics, and Damascene process flows.

Future reticle demand and next-generation lithography technologies

NASA Astrophysics Data System (ADS)

Behringer, Uwe F. W.; Ehrlich, Christian; Fortange, Olaf

1999-04-01

Mask technology has often been considered an enabling for semiconductor fabrication. But today photomasks have evolved to a bottle neck in the every increasing integration process of semiconductor circuits. Regarding to the 1997 SIA roadmap there are very stringent requirements for mask making. Even with the momentary weak Asian market the worldwide demand for reticles will continue to grow. The anticipation of larger reticles has been discussed over years. What ever the reason for the need of larger reticles, the move to the 230 mm X 230 mm reticle size will provide size will provide unique challenges to both the mask equipment manufacturers and mask fabricator. Next Generation Lithography together with their mask techniques are in development and try to come into the market.

Method for manufacturing electrical contacts for a thin-film semiconductor device

DOEpatents

Carlson, David E.; Dickson, Charles R.; D'Aiello, Robert V.

1988-11-08

A method of fabricating spaced-apart back contacts on a thin film of semiconductor material by forming strips of buffer material on top of the semiconductor material in locations corresponding to the desired dividing lines between back contacts, forming a film of metal substantially covering the semiconductor material and buffer strips, and scribing portions of the metal film overlying the buffer strips with a laser without contacting the underlying semiconductor material to separate the metal layer into a plurality of back contacts. The buffer material serves to protect the underlying semiconductor material from being damaged during the laser scribing. Back contacts and multi-cell photovoltaic modules incorporating such back contacts also are disclosed.

Dispersion of Heat Flux Sensors Manufactured in Silicon Technology.

PubMed

Ziouche, Katir; Lejeune, Pascale; Bougrioua, Zahia; Leclercq, Didier

2016-06-09

In this paper, we focus on the dispersion performances related to the manufacturing process of heat flux sensors realized in CMOS (Complementary metal oxide semi-conductor) compatible 3-in technology. In particular, we have studied the performance dispersion of our sensors and linked these to the physical characteristics of dispersion of the materials used. This information is mandatory to ensure low-cost manufacturing and especially to reduce production rejects during the fabrication process. The results obtained show that the measured sensitivity of the sensors is in the range 3.15 to 6.56 μV/(W/m²), associated with measured resistances ranging from 485 to 675 kΩ. The dispersions correspond to a Gaussian-type distribution with more than 90% determined around average sensitivity S e ¯ = 4.5 µV/(W/m²) and electrical resistance R ¯ = 573.5 kΩ within the interval between the average and, more or less, twice the relative standard deviation.

Architecture for distributed design and fabrication

NASA Astrophysics Data System (ADS)

McIlrath, Michael B.; Boning, Duane S.; Troxel, Donald E.

1997-01-01

We describe a flexible, distributed system architecture capable of supporting collaborative design and fabrication of semi-conductor devices and integrated circuits. Such capabilities are of particular importance in the development of new technologies, where both equipment and expertise are limited. Distributed fabrication enables direct, remote, physical experimentation in the development of leading edge technology, where the necessary manufacturing resources are new, expensive, and scarce. Computational resources, software, processing equipment, and people may all be widely distributed; their effective integration is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages current vendor and consortia developments to define software interfaces and infrastructure based on existing and merging networking, CIM, and CAD standards. Process engineers and product designers access processing and simulation results through a common interface and collaborate across the distributed manufacturing environment.

On-line photolithography modeling using spectrophotometry and Prolith/2

NASA Astrophysics Data System (ADS)

Engstrom, Herbert L.; Beacham, Jeanne E.

1994-05-01

Spectrophotometry has been applied to optimizing photolithography processes in semiconductor manufacturing. For many years thin film measurement systems have been used in manufacturing for controlling film deposition processes. The combination of film thickness mapping with photolithography modeling has expanded the applications of this technology. Experimental measurements of dose-to-clear, the minimum light exposure dose required to fully develop a photoresist, are described. It is shown how dose-to-clear and photoresist contrast may be determined rapidly and conveniently from measurements of a dose exposure matrix on a monitor wafer. Such experimental measurements may underestimate the dose-to- clear because of thickness variations of the photoresist and underlying layers on the product wafer. Online modeling of the photolithographic process together with film thickness maps of the entire wafer can overcome this problem. Such modeling also provides maps of dose-to- clear and resist linewidth that can be used to estimate and optimize yield.

Occupational injury and illness in the semiconductor manufacturing industry.

PubMed

McCurdy, S A; Schenker, M B; Lassiter, D V

1989-01-01

Two thousand nine hundred and ninety-four reports of OSHA-reportable occupational injury or illness cases in 1984 from member companies of a national trade association of semiconductor manufacturing firms were analyzed. The 37 participating manufacturing facilities represented 16 companies employing over 95,000 persons, or approximately one-third of the U.S. work force for this industry in 1984. The annual incidence rate for all reportable injuries and illnesses was 2.7 per 100 full-time employees (FTE) for men and 3.7 per 100 FTE for women. Strains, sprains, or dislocations were the most frequently reported incidents (N = 956 [31.9%]), followed by cuts, lacerations, punctures, scratches, and abrasions (N = 445 [14.9%]), and chemical burns (N = 401 [13.4%]). Increased work-loss days per case were associated with manufacturing sites that did not have an employee health clinic on the premises, with custodial occupations, and with female gender.

Advanced applications of scatterometry based optical metrology

NASA Astrophysics Data System (ADS)

Dixit, Dhairya; Keller, Nick; Kagalwala, Taher; Recchia, Fiona; Lifshitz, Yevgeny; Elia, Alexander; Todi, Vinit; Fronheiser, Jody; Vaid, Alok

2017-03-01

The semiconductor industry continues to drive patterning solutions that enable devices with higher memory storage capacity, faster computing performance, and lower cost per transistor. These developments in the field of semiconductor manufacturing along with the overall minimization of the size of transistors require continuous development of metrology tools used for characterization of these complex 3D device architectures. Optical scatterometry or optical critical dimension (OCD) is one of the most prevalent inline metrology techniques in semiconductor manufacturing because it is a quick, precise and non-destructive metrology technique. However, at present OCD is predominantly used to measure the feature dimensions such as line-width, height, side-wall angle, etc. of the patterned nano structures. Use of optical scatterometry for characterizing defects such as pitch-walking, overlay, line edge roughness, etc. is fairly limited. Inspection of process induced abnormalities is a fundamental part of process yield improvement. It provides process engineers with important information about process errors, and consequently helps optimize materials and process parameters. Scatterometry is an averaging technique and extending it to measure the position of local process induced defectivity and feature-to-feature variation is extremely challenging. This report is an overview of applications and benefits of using optical scatterometry for characterizing defects such as pitch-walking, overlay and fin bending for advanced technology nodes beyond 7nm. Currently, the optical scatterometry is based on conventional spectroscopic ellipsometry and spectroscopic reflectometry measurements, but generalized ellipsometry or Mueller matrix spectroscopic ellipsometry data provides important, additional information about complex structures that exhibit anisotropy and depolarization effects. In addition the symmetry-antisymmetry properties associated with Mueller matrix (MM) elements provide an excellent means of measuring asymmetry present in the structure. The useful additional information as well as symmetry-antisymmetry properties of MM elements is used to characterize fin bending, overlay defects and design improvements in the OCD test structures are used to boost OCDs' sensitivity to pitch-walking. In addition, the validity of the OCD based results is established by comparing the results to the top down critical dimensionscanning electron microscope (CD-SEM) and cross-sectional transmission electron microscope (TEM) images.

Walk-through survey report: Control technology for integrated circuit fabrication, Xerox Corporation, El Segundo, California

NASA Astrophysics Data System (ADS)

Mihlan, G. J.; Ungers, L. J.; Smith, R. K.; Mitchell, R. I.; Jones, J. H.

1983-05-01

A preliminary control technology assessment survey was conducted at the facility which manufactures N-channel metal oxide semiconductor (NMOS) integrated circuits. The facility has industrial hygiene review procedures for evaluating all new and existing process equipment. Employees are trained in safety, use of personal protective equipment, and emergency response. Workers potentially exposed to arsenic are monitored for urinary arsenic levels. The facility should be considered a candidate for detailed study based on the diversity of process operations encountered and the use of state-of-the-art technology and process equipment.

Method for manufacturing compound semiconductor field-effect transistors with improved DC and high frequency performance

DOEpatents

Zolper, John C.; Sherwin, Marc E.; Baca, Albert G.

2000-01-01

A method for making compound semiconductor devices including the use of a p-type dopant is disclosed wherein the dopant is co-implanted with an n-type donor species at the time the n-channel is formed and a single anneal at moderate temperature is then performed. Also disclosed are devices manufactured using the method. In the preferred embodiment n-MESFETs and other similar field effect transistor devices are manufactured using C ions co-implanted with Si atoms in GaAs to form an n-channel. C exhibits a unique characteristic in the context of the invention in that it exhibits a low activation efficiency (typically, 50% or less) as a p-type dopant, and consequently, it acts to sharpen the Si n-channel by compensating Si donors in the region of the Si-channel tail, but does not contribute substantially to the acceptor concentration in the buried p region. As a result, the invention provides for improved field effect semiconductor and related devices with enhancement of both DC and high-frequency performance.

A convenient method of manufacturing liquid-gated MoS2 field effect transistors

NASA Astrophysics Data System (ADS)

Lin, Kabin; Yuan, Zhishan; Yu, Yu; Li, Kun; Li, Zhongwu; Sha, Jingjie; Li, Tie; Chen, Yunfei

2017-10-01

In this paper, we present a simple and convenient method of manufacturing liquid-gated MoS2 field effect transistors (FETs). A Si3N4 chip is firstly fabricated by the semiconductor manufacturing process, then the mechanical exfoliation MoS2 is transferred onto the Si3N4 chip and is connected with the gold electrodes by depositing platinum to construct the MoS2 FETs. The liquid-gated is formed by injecting 0.1 M NaCl solution into reservoir to contact the back side of the Si3N4. Our measured results show that the contact properties between MoS2 and electrodes are in well condition and the liquid-gated MoS2 FETs have a high mobility that can reach up to 109 cm2 V-1 s-1.

Qualification of an evaluated butterfly-packaged DFB laser designed for space applications

NASA Astrophysics Data System (ADS)

Tornow, S.; Stier, C.; Buettner, T.; Laurent, T.; Kneier, M.; Bru, J.; Lien, Y.

2017-11-01

An extended qualification program has proven the quality of a previously evaluated semiconductor laser diode, which is intended to be used in a subsystem for the GAIA mission. We report on results of several reliability tests performed in subgroups. The requirements of the procurement specification with respect to reliability and desired manufacturing processes were confirmed. This is an example for successful collaboration between component supplier, system integrator and payload responsible party.

Implementation of activity-based costing (ABC) to drive cost reduction efforts in a semiconductor manufacturing operation

NASA Astrophysics Data System (ADS)

Naguib, Hussein; Bol, Igor I.; Lora, J.; Chowdhry, R.

1994-09-01

This paper presents a case study on the implementation of ABC to calculate the cost per wafer and to drive cost reduction efforts for a new IC product line. The cost reduction activities were conducted through the efforts of 11 cross-functional teams which included members of the finance, purchasing, technology development, process engineering, equipment engineering, production control, and facility groups. The activities of these cross functional teams were coordinated by a cost council. It will be shown that these activities have resulted in a 57% reduction in the wafer manufacturing cost of the new product line. Factors contributed to successful implementation of an ABC management system are discussed.

Optical computing, optical memory, and SBIRs at Foster-Miller

NASA Astrophysics Data System (ADS)

Domash, Lawrence H.

1994-03-01

A desktop design and manufacturing system for binary diffractive elements, MacBEEP, was developed with the optical researcher in mind. Optical processing systems for specialized tasks such as cellular automation computation and fractal measurement were constructed. A new family of switchable holograms has enabled several applications for control of laser beams in optical memories. New spatial light modulators and optical logic elements have been demonstrated based on a more manufacturable semiconductor technology. Novel synthetic and polymeric nonlinear materials for optical storage are under development in an integrated memory architecture. SBIR programs enable creative contributions from smaller companies, both product oriented and technology oriented, and support advances that might not otherwise be developed.

Technician Training for the Semiconductor Microdevices Industry. Final Report.

ERIC Educational Resources Information Center

Center for Occupational Research and Development, Inc., Waco, TX.

The Center for Occupational Research and Development (CORD) carried out four activities to foster semiconductor manufacturing technician (SMT) training: (1) collaboration with industry experts and educators while developing a curriculum to train SMTs; (2) implementation and testing of the curriculum at a technical college; (3) dissemination of…

Amorphous semiconductor solar cell

DOEpatents

Dalal, Vikram L.

1981-01-01

A solar cell comprising a back electrical contact, amorphous silicon semiconductor base and junction layers and a top electrical contact includes in its manufacture the step of heat treating the physical junction between the base layer and junction layer to diffuse the dopant species at the physical junction into the base layer.

15 CFR 700.15 - Extension of priority ratings.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) BUREAU OF INDUSTRY AND SECURITY, DEPARTMENT OF COMMERCE NATIONAL SECURITY INDUSTRIAL BASE REGULATIONS... receipt of a DO-A3 rated order for a navigation system and needs to purchase semiconductors for its manufacture, that person must use a DO-A3 rated order to obtain the needed semiconductors. (b) The priority...

Context-based virtual metrology

NASA Astrophysics Data System (ADS)

Ebersbach, Peter; Urbanowicz, Adam M.; Likhachev, Dmitriy; Hartig, Carsten; Shifrin, Michael

2018-03-01

Hybrid and data feed forward methodologies are well established for advanced optical process control solutions in highvolume semiconductor manufacturing. Appropriate information from previous measurements, transferred into advanced optical model(s) at following step(s), provides enhanced accuracy and exactness of the measured topographic (thicknesses, critical dimensions, etc.) and material parameters. In some cases, hybrid or feed-forward data are missed or invalid for dies or for a whole wafer. We focus on approaches of virtual metrology to re-create hybrid or feed-forward data inputs in high-volume manufacturing. We discuss missing data inputs reconstruction which is based on various interpolation and extrapolation schemes and uses information about wafer's process history. Moreover, we demonstrate data reconstruction approach based on machine learning techniques utilizing optical model and measured spectra. And finally, we investigate metrics that allow one to assess error margin of virtual data input.

Technology Roadmaps for Compound Semiconductors

PubMed Central

Bennett, Herbert S.

2000-01-01

The roles cited for compound semiconductors in public versions of existing technology roadmaps from the National Electronics Manufacturing Initiative, Inc., Optoelectronics Industry Development Association, Microelectronics Advanced Research Initiative on Optoelectronic Interconnects, and Optoelectronics Industry and Technology Development Association (OITDA) are discussed and compared within the context of trends in the Si CMOS industry. In particular, the extent to which these technology roadmaps treat compound semiconductors at the materials processing and device levels will be presented for specific applications. For example, OITDA’s Optical Communications Technology Roadmap directly connects the information demand of delivering 100 Mbit/s to the home to the requirement of producing 200 GHz heterojunction bipolar transistors with 30 nm bases and InP high electron mobility transistors with 100 nm gates. Some general actions for progress towards the proposed International Technology Roadmap for Compound Semiconductors (ITRCS) and methods for determining the value of an ITRCS will be suggested. But, in the final analysis, the value added by an ITRCS will depend on how industry leaders respond. The technical challenges and economic opportunities of delivering high quality digital video to consumers provide concrete examples of where the above actions and methods could be applied. PMID:27551615

Manufacture of radio frequency micromachined switches with annealing.

PubMed

Lin, Cheng-Yang; Dai, Ching-Liang

2014-01-17

The fabrication and characterization of a radio frequency (RF) micromachined switch with annealing were presented. The structure of the RF switch consists of a membrane, coplanar waveguide (CPW) lines, and eight springs. The RF switch is manufactured using the complementary metal oxide semiconductor (CMOS) process. The switch requires a post-process to release the membrane and springs. The post-process uses a wet etching to remove the sacrificial silicon dioxide layer, and to obtain the suspended structures of the switch. In order to improve the residual stress of the switch, an annealing process is applied to the switch, and the membrane obtains an excellent flatness. The finite element method (FEM) software CoventorWare is utilized to simulate the stress and displacement of the RF switch. Experimental results show that the RF switch has an insertion loss of 0.9 dB at 35 GHz and an isolation of 21 dB at 39 GHz. The actuation voltage of the switch is 14 V.

Manufacture of Radio Frequency Micromachined Switches with Annealing

PubMed Central

Lin, Cheng-Yang; Dai, Ching-Liang

2014-01-01

The fabrication and characterization of a radio frequency (RF) micromachined switch with annealing were presented. The structure of the RF switch consists of a membrane, coplanar waveguide (CPW) lines, and eight springs. The RF switch is manufactured using the complementary metal oxide semiconductor (CMOS) process. The switch requires a post-process to release the membrane and springs. The post-process uses a wet etching to remove the sacrificial silicon dioxide layer, and to obtain the suspended structures of the switch. In order to improve the residual stress of the switch, an annealing process is applied to the switch, and the membrane obtains an excellent flatness. The finite element method (FEM) software CoventorWare is utilized to simulate the stress and displacement of the RF switch. Experimental results show that the RF switch has an insertion loss of 0.9 dB at 35 GHz and an isolation of 21 dB at 39 GHz. The actuation voltage of the switch is 14 V. PMID:24445415

Optics education for machine operators in the semiconductor industry: moving beyond button pushing

NASA Astrophysics Data System (ADS)

Karakekes, Meg; Currier, Deborah

1995-10-01

In the competitive semiconductor manufacturing industry, employees who operate equipment are able to make greater contributions if they understand how the equipment works. By understanding the 'why' behind the 'what', the equipment operators can better partner with other technical staff to produce quality integrated circuits efficiently and effectively. This additional knowledge also opens equipment operators to job enrichment and enlargement opportunities. Advanced Micro Devices (AMD) is in the process of upgrading the skills of its equipment operators. This paper is an overview of a pilot program that employs optics education to upgrade stepper operators' skills. The paper starts with stepper tasks that require optics knowledge, examines teaching methods, reports both end-of-course and three months post-training knowledge retention, and summarizes how the training has impacted the production floor.

Metrologies for quantitative nanomechanical testing and quality control in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Pratt, Jon R.; Kramar, John A.; Newell, David B.; Smith, Douglas T.

2005-05-01

If nanomechanical testing is to evolve into a tool for process and quality control in semiconductor fabrication, great advances in throughput, repeatability, and accuracy of the associated instruments and measurements will be required. A recent grant awarded by the NIST Advanced Technology Program seeks to address the throughput issue by developing a high-speed AFM-based platform for quantitative nanomechanical measurements. The following paper speaks to the issue of quantitative accuracy by presenting an overview of various standards and techniques under development at NIST and other national metrology institutes (NMIs) that can provide a metrological basis for nanomechanical testing. The infrastructure we describe places firm emphasis on traceability to the International System of Units, paving the way for truly quantitative, rather than qualitative, physical property testing.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jornet, N; Carrasco de Fez, P; Jordi, O

Purpose: To evaluate the accuracy in total scatter factor (Sc,p) determination for small fields using commercial plastic scintillator detector (PSD). The manufacturer's spectral discrimination method to subtract Cerenkov light from the signal is discussed. Methods: Sc,p for field sizes ranging from 0.5 to 10 cm were measured using PSD Exradin (Standard Imaging) connected to two channel electrometer measuring the signals in two different spectral regions to subtract the Cerenkov signal from the PSD signal. A Pinpoint ionisation chamber 31006 (PTW) and a non-shielded semiconductor detector EFD (Scanditronix) were used for comparison. Measures were performed for a 6 MV X-ray beam.more » The Sc,p are measured at 10 cm depth in water for a SSD=100 cm and normalized to a 10'10 cm{sup 2} field size at the isocenter. All detectors were placed with their symmetry axis parallel to the beam axis.We followed the manufacturer's recommended calibration methodology to subtract the Cerenkov contribution to the signal as well as a modified method using smaller field sizes. The Sc,p calculated by using both calibration methodologies were compared. Results: Sc,p measured with the semiconductor and the PinPoint detectors agree, within 1.5%, for field sizes between 10'10 and 1'1 cm{sup 2}. Sc,p measured with the PSD using the manufacturer's calibration methodology were systematically 4% higher than those measured with the semiconductor detector for field sizes smaller than 5'5 cm{sup 2}. By using a modified calibration methodology for smalls fields and keeping the manufacturer calibration methodology for fields larger than 5'5cm{sup 2} field Sc,p matched semiconductor results within 2% field sizes larger than 1.5 cm. Conclusion: The calibration methodology proposed by the manufacturer is not appropriate for dose measurements in small fields. The calibration parameters are not independent of the incident radiation spectrum for this PSD. This work was partially financed by grant 2012 of Barcelona board of the AECC.« less

47 CFR 95.667 - CB transmitter power.

Code of Federal Regulations, 2013 CFR

2013-10-01

... transmitter power. The dissipation rating of all the semiconductors or electron tubes which supply RF power to... semiconductor. These values may be temperature de-rated by no more than 50 °C. For an electron tube, the... the manufacturer of the electron tube. [53 FR 36789, Sept. 22, 1988. Redesignated at 61 FR 28769, June...

47 CFR 95.667 - CB transmitter power.

Code of Federal Regulations, 2012 CFR

2012-10-01

... transmitter power. The dissipation rating of all the semiconductors or electron tubes which supply RF power to... semiconductor. These values may be temperature de-rated by no more than 50 °C. For an electron tube, the... the manufacturer of the electron tube. [53 FR 36789, Sept. 22, 1988. Redesignated at 61 FR 28769, June...

47 CFR 95.667 - CB transmitter power.

Code of Federal Regulations, 2014 CFR

2014-10-01

... transmitter power. The dissipation rating of all the semiconductors or electron tubes which supply RF power to... semiconductor. These values may be temperature de-rated by no more than 50 °C. For an electron tube, the... the manufacturer of the electron tube. [53 FR 36789, Sept. 22, 1988. Redesignated at 61 FR 28769, June...

Gold Coating

NASA Technical Reports Server (NTRS)

1997-01-01

Epner Technology Inc. responded to a need from Goddard Space Flight Center for the ultimate in electroplated reflectivity needed for the Mars Global Surveyor Mars Orbiter Laser Altimeter (MOLA). Made of beryllium, the MOLA mirror was coated by Epner Technology Laser Gold process, specially improved for the project. Improved Laser Gold- coated reflectors have found use in an epitaxial reactor built for a large semiconductor manufacturer as well as the waveguide in Braun-Thermoscan tympanic thermometer and lasing cavities in various surgical instruments.

Challenges of image placement and overlay at the 90-nm and 65-nm nodes

NASA Astrophysics Data System (ADS)

Trybula, Walter J.

2003-05-01

The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. INTERNATIONAL SE-MATECH has been leading and supporting efforts to investigate the impact of the tech-nology introduction. This paper examines the issue of manufacturing tolerances available for image placement on adjacent critical levels (overlay) at the 90nm and 65nm technol-ogy nodes. The allowable values from the 2001 release of the ITRS Roadmap are 32nm for the 90nm node, and 23nm for the 65nm node. Even the 130nm node has overlay requirements of only 46nm. Employing tolerances that can be predicted, the impact of existing production/processing tolerance accumulation can provide an indication of the challenges facing the manufacturer in the production of 90nm and 65nm Node devices.

Prolonged menstrual cycles in female workers exposed to ethylene glycol ethers in the semiconductor manufacturing industry.

PubMed

Hsieh, G-Y; Wang, J-D; Cheng, T-J; Chen, P-C

2005-08-01

It has been shown that female workers exposed to ethylene glycol ethers (EGEs) in the semiconductor industry have higher risks of spontaneous abortion, subfertility, and menstrual disturbances, and prolonged waiting time to pregnancy. To examine whether EGEs or other chemicals are associated with long menstrual cycles in female workers in the semiconductor manufacturing industry. Cross-sectional questionnaire survey during the annual health examination at a wafer manufacturing company in Taiwan in 1997. A three tiered exposure-assessment strategy was used to analyse the risk. A short menstrual cycle was defined to be a cycle less than 24 days and a long cycle to be more than 35 days. There were 606 valid questionnaires from 473 workers in fabrication jobs and 133 in non-fabrication areas. Long menstrual cycles were associated with workers in fabrication areas compared to those in non-fabrication areas. Using workers in non-fabrication areas as referents, workers in photolithography and diffusion areas had higher risks for long menstrual cycles. Workers exposed to EGEs and isopropanol, and hydrofluoric acid, isopropanol, and phosphorous compounds also showed increased risks of a long menstrual cycle. Exposure to multiple chemicals, including EGEs in photolithography, might be associated with long menstrual cycles, and may play an important role in a prolonged time to pregnancy in the wafer manufacturing industry; however, the prevalence in the design, possible exposure misclassification, and chance should be considered.

Programme and Abstracts. Workshop on Expert Evaluation and Control of Compound Semiconductor Materials and Technologies (1st) Held in Ecole Centrale De Lyon, France on 19 -22 May 1992. (EXAMTEC’ 92)

DTIC Science & Technology

1992-05-22

Evaluation and Control of Compound Semiconductor Materials and Technologies (EXMATEC󈨠) at Ecole Centrale de Lyon (Ecully, France, 19th to 22nd May...semiconductor technologies to manufacture advanced devices with improved reproducibility, better reliability and lower cost. -’Device structures...concepts are required for expert evaluation and control of still developing technologies . In this context, the EXMATEC series will constitute a major

World wide matching of registration metrology tools of various generations

NASA Astrophysics Data System (ADS)

Laske, F.; Pudnos, A.; Mackey, L.; Tran, P.; Higuchi, M.; Enkrich, C.; Roeth, K.-D.; Schmidt, K.-H.; Adam, D.; Bender, J.

2008-10-01

Turn around time/cycle time is a key success criterion in the semiconductor photomask business. Therefore, global mask suppliers typically allocate work loads based on fab capability and utilization capacity. From a logistical point of view, the manufacturing location of a photomask should be transparent to the customer (mask user). Matching capability of production equipment and especially metrology tools is considered a key enabler to guarantee cross site manufacturing flexibility. Toppan, with manufacturing sites in eight countries worldwide, has an on-going program to match the registration metrology systems of all its production sites. This allows for manufacturing flexibility and risk mitigation.In cooperation with Vistec Semiconductor Systems, Toppan has recently completed a program to match the Vistec LMS IPRO systems at all production sites worldwide. Vistec has developed a new software feature which allows for significantly improved matching of LMS IPRO(x) registration metrology tools of various generations. We will report on the results of the global matching campaign of several of the leading Toppan sites.

Final Scientific/Technical Report -- Single-Junction Organic Solar Cells with >15% Efficiency

DOE Office of Scientific and Technical Information (OSTI.GOV)

Starkenburg, Daken; Weldeab, Asmerom; Fagnani, Dan

Organic solar cells have the potential to offer low-cost solar energy conversion due to low material costs and compatibility with low-temperature and high throughput manufacturing processes. This project aims to further improve the efficiency of organic solar cells by applying a previously demonstrated molecular self-assembly approach to longer-wavelength light-absorbing organic materials. The team at the University of Florida designed and synthesized a series of low-bandgap organic semiconductors with functional hydrogen-bonding groups, studied their assembly characteristics and optoelectronic properties in solid-state thin film, and fabricated organic solar cells using solution processing. These new organic materials absorb light up 800 nm wavelength,more » and provide a maximum open-circuit voltage of 1.05 V in the resulted solar cells. The results further confirmed the effectiveness in this approach to guide the assembly of organic semiconductors in thin films to yield higher photovoltaic performance for solar energy conversion. Through this project, we have gained important understanding on designing, synthesizing, and processing organic semiconductors that contain appropriately functionalized groups to control the morphology of the organic photoactive layer in solar cells. Such fundamental knowledge could be used to further develop new functional organic materials to achieve higher photovoltaic performance, and contribute to the eventual commercialization of the organic solar cell technology.« less

Overview of atomic layer etching in the semiconductor industry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanarik, Keren J., E-mail: keren.kanarik@lamresearch.com; Lill, Thorsten; Hudson, Eric A.

2015-03-15

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article providesmore » defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices.« less

Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits.

PubMed

Baeg, Kang-Jun; Kim, Juhwan; Khim, Dongyoon; Caironi, Mario; Kim, Dong-Yu; You, In-Kyu; Quinn, Jordan R; Facchetti, Antonio; Noh, Yong-Young

2011-08-01

Ambipolar π-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (∼4.1 eV) compared to that of a pristine Au electrode (∼4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ∼0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ∼0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) < 70 nA when I(on) > 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ∼12 kHz) based on a solution-processed ambipolar polymer are demonstrated.

Sol-gel process for the manufacture of high power switches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Landingham, Richard L.; Satcher, Jr, Joe; Reibold, Robert

According to one embodiment, a photoconductive semiconductor switch includes a structure of nanopowder of a high band gap material, where the nanopowder is optically transparent, and where the nanopowder has a physical characteristic of formation from a sol-gel process. According to another embodiment, a method includes mixing a sol-gel precursor compound, a hydroxy benzene and an aldehyde in a solvent thereby creating a mixture, causing the mixture to gel thereby forming a wet gel, drying the wet gel to form a nanopowder, and applying a thermal treatment to form a SiC nanopowder.

Introduction of Nano-seconds Pulsed Discharge Plasma and its Applications

NASA Astrophysics Data System (ADS)

Namihira, Takao; Wang, Douyan; Matsumoto, Takao; Okada, Sho; Akiyama, Hidenori

During the decades, the developments of high power semiconductor switch, magnetic core and etc have allowed us to manufacture the pulsed power source having higher energy transfer efficiency. As the results, the pulsed discharge has been recognized as one of the promised non-thermal plasma to practical use. In this paper, a generation process, electron energy, impedance and a temperature of the pulsed discharge plasma would be explained. In addition, a nano-seconds pulsed discharge plasma would be introduced as the non-thermal plasma processing giving us the highest energy efficiency and be demonstrated it.

Ceramic membrane development in NGK

NASA Astrophysics Data System (ADS)

Araki, Kiyoshi; Sakai, Hitoshi

2011-05-01

NGK Insulators, Ltd. was established in 1919 to manufacture the electric porcelain insulators for power transmission lines. Since then, our business has grown as one of the world-leading ceramics manufacturing companies and currently supply with the various environmentally-benign ceramic products to worldwide. In this paper, ceramic membrane development in NGK is described in detail. We have been selling ceramic microfiltration (MF) membranes and ultra-filtration (UF) membranes for many years to be used for solid/liquid separation in various fields such as pharmaceutical, chemical, food and semiconductor industries. In Corporate R&D, new ceramic membranes with sub-nanometer sized pores, which are fabricated on top of the membrane filters as support, are under development for gas and liquid/liquid separation processes.

Measuring the complete cross-cell carrier mobility distributions in bulk heterojunction solar cells

NASA Astrophysics Data System (ADS)

Seifter, Jason; Sun, Yanming; Choi, Hyosung; Lee, Byoung Hoon; Heeger, Alan

2015-03-01

Carbon nanotube-enabled, vertical, organic field effect transistors (CN-VFETs) based on the small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) have demonstrated high current, low-power operation suitable for driving active matix organic light emitting diode (AMOLED) displays. This performance is achieved without the need for costly high-resolution patterning, despite the low mobility of the organic semiconductor, by employing sub-micron channel widths, defined in the vertical devices by the thickness of the semiconducting layer. Replacing the thermally evaporated small molecule semiconductor with a solution-processed polymer would possibly further simplify the fabrication process and reduce manufacturing cost. Here we investigate several polymer systems as wide bandgap semiconducting channel layers for potentially air stable and transparent CN-VFETs. The field effect mobility and optical transparency of the polymer layers are determined, and the performance and air stability of CN-VFET devices are measured. A. S. gratefully acknowledges support from the National Science Foundation under DMR-1156737.

An ergonomics study of a semiconductors factory in an IDC for improvement in occupational health and safety.

PubMed

Bin, Wong Saw; Richardson, Stanley; Yeow, Paul H P

2010-01-01

The study aimed to conduct an ergonomic intervention on a conventional line (CL) in a semiconductor factory in Malaysia, an industrially developing country (IDC), to improve workers' occupational health and safety (OHS). Low-cost and simple (LCS) ergonomics methods were used (suitable for IDCs), e.g., subjective assessment, direct observation, use of archival data and assessment of noise. It was found that workers were facing noise irritation, neck and back pains and headache in the various processes in the CL. LCS ergonomic interventions to rectify the problems included installing noise insulating covers, providing earplugs, installing elevated platforms, slanting visual display terminals and installing extra exhaust fans. The interventions cost less than 3 000 USD but they significantly improved workers' OHS, which directly correlated with an improvement in working conditions and job satisfaction. The findings are useful in solving OHS problems in electronics industries in IDCs as they share similar manufacturing processes, problems and limitations.

Recursive least squares estimation and its application to shallow trench isolation

NASA Astrophysics Data System (ADS)

Wang, Jin; Qin, S. Joe; Bode, Christopher A.; Purdy, Matthew A.

2003-06-01

In recent years, run-to-run (R2R) control technology has received tremendous interest in semiconductor manufacturing. One class of widely used run-to-run controllers is based on the exponentially weighted moving average (EWMA) statistics to estimate process deviations. Using an EWMA filter to smooth the control action on a linear process has been shown to provide good results in a number of applications. However, for a process with severe drifts, the EWMA controller is insufficient even when large weights are used. This problem becomes more severe when there is measurement delay, which is almost inevitable in semiconductor industry. In order to control drifting processes, a predictor-corrector controller (PCC) and a double EWMA controller have been developed. Chen and Guo (2001) show that both PCC and double-EWMA controller are in effect Integral-double-Integral (I-II) controllers, which are able to control drifting processes. However, since offset is often within the noise of the process, the second integrator can actually cause jittering. Besides, tuning the second filter is not as intuitive as a single EWMA filter. In this work, we look at an alternative way Recursive Least Squares (RLS), to estimate and control the drifting process. EWMA and double-EWMA are shown to be the least squares estimate for locally constant mean model and locally constant linear trend model. Then the recursive least squares with exponential factor is applied to shallow trench isolation etch process to predict the future etch rate. The etch process, which is a critical process in the flash memory manufacturing, is known to suffer from significant etch rate drift due to chamber seasoning. In order to handle the metrology delay, we propose a new time update scheme. RLS with the new time update method gives very good result. The estimate error variance is smaller than that from EWMA, and mean square error decrease more than 10% compared to that from EWMA.

Processing materials in space - The history and the future

NASA Technical Reports Server (NTRS)

Chassay, Roger; Carswell, Bill

1987-01-01

The development of materials processing in space, and some of the Soyuz, Apollo, Skylab, and Shuttle orbital materials experiments are reviewed. Consideration is given to protein crystal growth, electrophoresis, low-gravity isoelectric focusing, phase partitioning, a monodisperse latex reactor, semiconductor crystal growth, solution crystal growth, the triglycine sulfate experiment, vapor crystal growth experiments, the mercuric iodide experiment, electronic and electrooptical materials, organic thin films and crystalline solids, deep undercooling of metals and alloys, magnetic materials, immiscible materials, metal solidification research, reluctant glass-forming materials, and containerless glass formation. The space processing apparatuses and ground facilities, for materials processing are described. Future facilities for commercial research, development, and manufacturing in space are proposed.

Editorial

NASA Astrophysics Data System (ADS)

Bruzzi, Mara; Cartiglia, Nicolo; Pace, Emanuele; Talamonti, Cinzia

2015-10-01

The 10th edition of the International Conference on Radiation Effects on Semiconductor Materials, Detectors and Devices (RESMDD) was held in Florence, at Dipartimento di Fisica ed Astronomia on October 8-10, 2014. It has been aimed at discussing frontier research activities in several application fields as nuclear and particle physics, astrophysics, medical and solid-state physics. Main topics discussed in this conference concern performance of heavily irradiated silicon detectors, developments required for the luminosity upgrade of the Large Hadron Collider (HL-LHC), ultra-fast silicon detectors design and manufacturing, high-band gap semiconductor detectors, novel semiconductor-based devices for medical applications, radiation damage issues in semiconductors and related radiation-hardening technologies.

A quick method for AlCu interconnect electromigration performance predicting and monitoring

NASA Astrophysics Data System (ADS)

Zhang, Wenjie; Yi, Leeward; Tao, Kai; Ma, Yue; Chang, Pingyi; Mao, Duli; Wu, Jin; Zou, S. C.

2006-05-01

The film properties and microstructures of (bottom)Si/SiO2/Ti(top) and (bottom)Si/SiO2/Ti/TiN/AlCu(top) stacks deposited by different processes were characterized. The resistivities of thin Ti films and the reflectivities of AlCu alloy films were found to correlate with the microstructure as well as the mean time to failure (MTTF) in the electromigration (EM) test. A quick-turn monitor for AlCu interconnect reliability in the semiconductor manufacturing industry was established.

High Volume Manufacturing and Field Stability of MEMS Products

NASA Astrophysics Data System (ADS)

Martin, Jack

Low volume MEMS/NEMS production is practical when an attractive concept is implemented with business, manufacturing, packaging, and test support. Moving beyond this to high volume production adds requirements on design, process control, quality, product stability, market size, market maturity, capital investment, and business systems. In a broad sense, this chapter uses a case study approach: It describes and compares the silicon-based MEMS accelerometers, pressure sensors, image projection systems, and gyroscopes that are in high volume production. Although they serve several markets, these businesses have common characteristics. For example, the manufacturing lines use automated semiconductor equipment and standard material sets to make consistent products in large quantities. Standard, well controlled processes are sometimes modified for a MEMS product. However, novel processes that cannot run with standard equipment and material sets are avoided when possible. This reliance on semiconductor tools, as well as the organizational practices required to manufacture clean, particle-free products partially explains why the MEMS market leaders are integrated circuit manufacturers. There are other factors. MEMS and NEMS are enabling technologies, so it can take several years for high volume applications to develop. Indeed, market size is usually a strong function of price. This becomes a vicious circle, because low price requires low cost - a result that is normally achieved only after a product is in high volume production. During the early years, IC companies reduced cost and financial risk by using existing facilities for low volume MEMS production. As a result, product architectures are partially determined by capabilities developed for previous products. This chapter includes a discussion of MEMS product architecture with particular attention to the impact of electronic integration, packaging, and surfaces. Packaging and testing are critical, because they are significant factors in MEMS product cost. These devices have extremelyhigh surface/volume ratios, so performance and stability may depend on the control of surface characteristics after packaging. Looking into the future, the competitive advantage of IC suppliers will decrease as small companies learn to integrate MEMS/NEMS devices on CMOS foundry wafers. Packaging challenges still remain, because most MEMS/NEMS products must interact with the environment without degrading stability or reliability. Generic packaging solutions are unlikely. However, packaging subcontractors recognize that MEMS/NEMS is a growth opportunity. They will spread the overhead burden of high-capital-cost-facilities by developing flexible processes in order to package several types of moderate volume integrated MEMS/NEMS products on the same equipment.

High Volume Manufacturing and Field Stability of MEMS Products

NASA Astrophysics Data System (ADS)

Martin, Jack

Low volume MEMS/NEMS production is practical when an attractive concept is implemented with business, manufacturing, packaging, and test support. Moving beyond this to high volume production adds requirements on design, process control, quality, product stability, market size, market maturity, capital investment, and business systems. In a broad sense, this chapter uses a case study approach: It describes and compares the silicon-based MEMS accelerometers, pressure sensors, image projection systems, and gyroscopes that are in high volume production. Although they serve several markets, these businesses have common characteristics. For example, the manufacturing lines use automated semiconductor equipment and standard material sets to make consistent products in large quantities. Standard, well controlled processes are sometimes modified for a MEMS product. However, novel processes that cannot run with standard equipment and material sets are avoided when possible. This reliance on semiconductor tools, as well as the organizational practices required to manufacture clean, particle-free products partially explains why the MEMS market leaders are integrated circuit manufacturers. There are other factors. MEMS and NEMS are enabling technologies, so it can take several years for high volume applications to develop. Indeed, market size is usually a strong function of price. This becomes a vicious circle, because low price requires low cost - a result that is normally achieved only after a product is in high volume production. During the early years, IC companies reduced cost and financial risk by using existing facilities for low volume MEMS production. As a result, product architectures are partially determined by capabilities developed for previous products. This chapter includes a discussion of MEMS product architecture with particular attention to the impact of electronic integration, packaging, and surfaces. Packaging and testing are critical, because they are significant factors in MEMS product cost. These devices have extremely high surface/volume ratios, so performance and stability may depend on the control of surface characteristics after packaging. Looking into the future, the competitive advantage of IC suppliers will decrease as small companies learn to integrate MEMS/NEMS devices on CMOS foundry wafers. Packaging challenges still remain, because most MEMS/NEMS products must interact with the environment without degrading stability or reliability. Generic packaging solutions are unlikely. However, packaging subcontractors recognize that MEMS/NEMS is a growth opportunity. They will spread the overhead burden of high-capital-cost-facilities by developing flexible processes in order to package several types of moderate volume integrated MEMS/NEMS products on the same equipment.

Effective EUVL mask cleaning technology solutions for mask manufacturing and in-fab mask maintenance

NASA Astrophysics Data System (ADS)

Dietze, Uwe; Dress, Peter; Waehler, Tobias; Singh, Sherjang; Jonckheere, Rik; Baudemprez, Bart

2011-03-01

Extreme Ultraviolet Lithography (EUVL) is considered the leading lithography technology choice for semiconductor devices at 16nm HP node and beyond. However, before EUV Lithography can enter into High Volume Manufacturing (HVM) of advanced semiconductor devices, the ability to guarantee mask integrity at point-of-exposure must be established. Highly efficient, damage free mask cleaning plays a critical role during the mask manufacturing cycle and throughout the life of the mask, where the absence of a pellicle to protect the EUV mask increases the risk of contamination during storage, handling and use. In this paper, we will present effective EUVL mask cleaning technology solutions for mask manufacturing and in-fab mask maintenance, which employs an intelligent, holistic approach to maximize Mean Time Between Cleans (MBTC) and extend the useful life span of the reticle. The data presented will demonstrate the protection of the capping and absorber layers, preservation of pattern integrity as well as optical and mechanical properties to avoid unpredictable CD-linewidth and overlay shifts. Experiments were performed on EUV blanks and pattern masks using various process conditions. Conditions showing high particle removal efficiency (PRE) and minimum surface layer impact were then selected for durability studies. Surface layer impact was evaluated over multiple cleaning cycles by means of UV reflectivity metrology XPS analysis and wafer prints. Experimental results were compared to computational models. Mask life time predictions where made using the same computational models. The paper will provide a generic overview of the cleaning sequence which yielded best results, but will also provide recommendations for an efficient in-fab mask maintenance scheme, addressing handling, storage, cleaning and inspection.

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors

PubMed Central

Matsushima, Toshinori; Sandanayaka, Atula S. D.; Esaki, Yu; Adachi, Chihaya

2015-01-01

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10–2 cm2/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm2/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost. PMID:26416434

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors.

PubMed

Matsushima, Toshinori; Sandanayaka, Atula S D; Esaki, Yu; Adachi, Chihaya

2015-09-29

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10(-2) cm(2)/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm(2)/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost.

Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors

NASA Astrophysics Data System (ADS)

Matsushima, Toshinori; Sandanayaka, Atula S. D.; Esaki, Yu; Adachi, Chihaya

2015-09-01

We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10-2 cm2/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm2/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost.

Environmental and health risks of chlorine trifluoride (ClF3), an alternative to potent greenhouse gases in the semiconductor industry.

PubMed

Tsai, Wen-Tien

2011-06-15

The first accident involving chlorine trifluoride (ClF(3)) in the history of semiconductor fabrication processes occurred on 28 July 2006 at Hsinchu (Taiwan), resulting in a large release of the highly reactive material and causing the chemical burn to several workers. ClF(3) is used primarily as an in situ cleaning gas in the manufacture of semiconductor silicon-wafer devices in replacement of perfluorocompounds (PFCs) because they have the high potential to contribute significantly to the global warming. This article aimed at reviewing ClF(3) in the physicochemical properties, the industrial uses, and the environmental implications on the basis of its toxicity, reactivity, health hazards and exposure limits. The health hazards of probable decomposition/hydrolysis products from ClF(3) were also evaluated based on their basic physicochemical properties and occupational exposure limits. The occupational exposure assessment was further discussed to understand potentially hazardous risks caused by hydrogen fluoride and fluorides from the decomposition/hydrolysis products of ClF(3). Copyright © 2010 Elsevier B.V. All rights reserved.

Improvement of sub-20nm pattern quality with dose modulation technique for NIL template production

NASA Astrophysics Data System (ADS)

Yagawa, Keisuke; Ugajin, Kunihiro; Suenaga, Machiko; Kanamitsu, Shingo; Motokawa, Takeharu; Hagihara, Kazuki; Arisawa, Yukiyasu; Kobayashi, Sachiko; Saito, Masato; Ito, Masamitsu

2016-04-01

Nanoimprint lithography (NIL) technology is in the spotlight as a next-generation semiconductor manufacturing technique for integrated circuits at 22 nm and beyond. NIL is the unmagnified lithography technique using template which is replicated from master templates. On the other hand, master templates are currently fabricated by electron-beam (EB) lithography[1]. In near future, finer patterns less than 15nm will be required on master template and EB data volume increases exponentially. So, we confront with a difficult challenge. A higher resolution EB mask writer and a high performance fabrication process will be required. In our previous study, we investigated a potential of photomask fabrication process for finer patterning and achieved 15.5nm line and space (L/S) pattern on template by using VSB (Variable Shaped Beam) type EB mask writer and chemically amplified resist. In contrast, we found that a contrast loss by backscattering decreases the performance of finer patterning. For semiconductor devices manufacturing, we must fabricate complicated patterns which includes high and low density simultaneously except for consecutive L/S pattern. Then it's quite important to develop a technique to make various size or coverage patterns all at once. In this study, a small feature pattern was experimentally formed on master template with dose modulation technique. This technique makes it possible to apply the appropriate exposure dose for each pattern size. As a result, we succeed to improve the performance of finer patterning in bright field area. These results show that the performance of current EB lithography process have a potential to fabricate NIL template.

Highly Sensitive and Very Stretchable Strain Sensor Based on a Rubbery Semiconductor.

PubMed

Kim, Hae-Jin; Thukral, Anish; Yu, Cunjiang

2018-02-07

There is a growing interest in developing stretchable strain sensors to quantify the large mechanical deformation and strain associated with the activities for a wide range of species, such as humans, machines, and robots. Here, we report a novel stretchable strain sensor entirely in a rubber format by using a solution-processed rubbery semiconductor as the sensing material to achieve high sensitivity, large mechanical strain tolerance, and hysteresis-less and highly linear responses. Specifically, the rubbery semiconductor exploits π-π stacked poly(3-hexylthiophene-2,5-diyl) nanofibrils (P3HT-NFs) percolated in silicone elastomer of poly(dimethylsiloxane) to yield semiconducting nanocomposite with a large mechanical stretchability, although P3HT is a well-known nonstretchable semiconductor. The fabricated strain sensors exhibit reliable and reversible sensing capability, high gauge factor (gauge factor = 32), high linearity (R 2 > 0.996), and low hysteresis (degree of hysteresis <12%) responses at the mechanical strain of up to 100%. A strain sensor in this format can be scalably manufactured and implemented as wearable smart gloves. Systematic investigations in the materials design and synthesis, sensor fabrication and characterization, and mechanical analysis reveal the key fundamental and application aspects of the highly sensitive and very stretchable strain sensors entirely from rubbers.

Sub-ppb Oxygen Contaminant Detection in Semi-Conductor Processing

NASA Technical Reports Server (NTRS)

Man, K. F.

1995-01-01

Gaseous contaminants such as oxygen, water vapor, nitrogen and hydrocarbons are often present in the processing environment in semiconductor device fabrication and in containerless materials processing. The contaminants arise as a result of outgassing from hot surfaces or they may be part of the impurities in commercial ultra-high purity gases. Among these gaseous contaminants, oxygen is the most reactive and, therefore, has the most adverse effects on the end product. There has been an intense effort at the Jet Propulsion Laboratory to develop different types of oxygen sorbents to reduce oxygen concentration in a microgravity processing environment to sub-ppb (parts-per-billion) levels. Higher concentrations can lead to rapid surface oxide formation, hence reducing the quality of semiconductor devices. If the concentration of oxygen in a processing chamber at 1000oC is in the ppb level, it will only take approximately 10 seconds for an oxide layer to form on the surface of a sample. The interaction of oxygen with the water surface can lead to the formation of localized defects in semi-conductor devices, hence decreasing the manufacturing yield. For example, efficient production of 64 Mb RAM chips requires contaminations below ppb levels. This paper describes a technique for measuring trace quantities of oxygen contaminants by recording the monoatomic negative ions, O-, using mass spectrometry. The O- formation from the e--O2 interaction utilizes the electron dissociative attachment method that is greatly enhanced at the resonant energy (6.8 eV). The device combines a small gridded electron ionizer with a compact mass spectrometer. The concentrations of oxygen have been measured using the method of standard additions by diluting O2 in N2. The lowest detection limit obtained was 1.2 kHz (O- count rate) at a concentration of 10-10, corresponding to 0.1 ppb.

Janus droplets: liquid marbles coated with dielectric/semiconductor particles.

PubMed

Bormashenko, Edward; Bormashenko, Yelena; Pogreb, Roman; Gendelman, Oleg

2011-01-04

The manufacturing of water droplets wrapped with two different powders, carbon black (semiconductor) and polytetrafluoroethylene (dielectric), is presented. Droplets composed of two hemispheres (Janus droplets) characterized by various physical and chemical properties are reported first. Watermelon-like striped liquid marbles are reported. Janus droplets remained stable on solid and liquid supports and could be activated with an electric field.

Improvement of screening methods for silicon planar semiconductor devices

NASA Technical Reports Server (NTRS)

Berger, W. M.

1972-01-01

The results of the program for the development of a more sensitive method for selecting silicon planar semiconductor devices for long life applications are reported. The manufacturing technologies (MOS and Bipolar) are discussed along with the screening procedures developed as a result of the tests and evaluations, and the effectiveness of the MOS and Bilayer screening procedures are evaluated.

Implementation of Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.; Kamp, David A.; Isaacson, Alan F.

2000-01-01

Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications.

Increased risk of death with congenital anomalies in the offspring of male semiconductor workers.

PubMed

Lin, Ching-Chun; Wang, Jung-Der; Hsieh, Gong-Yih; Chang, Yu-Yin; Chen, Pau-Chung

2008-01-01

Female workers in the semiconductor industry have higher risks of subfertility and spontaneous abortion, but no studies exploring male-mediated developmental toxicity have been published. This study aimed to investigate whether the offspring of male workers employed in the semiconductor manufacturing industry had an increased risk of death with congenital anomalies. The 6,834 male workers had been employed in the eight semiconductor companies in Taiwan between 1980 and 1994. We identified the live born children with or without congenital anomalies of the workers using the National Birth and Death Registries from the Department of Health, Taiwan. Multiple logistic regression models were used to estimate the odds ratios (OR) of birth outcomes and deaths, controlling for infant sex, maternal age, and paternal education. A total of 5,702 children were born to male workers during the period 1980-1994. There were increased risks of deaths with congenital anomalies (adjusted OR, 3.26; and 95% confidence interval [CI], 1.12-9.44) and heart anomalies (OR, 4.15; 95% CI, 1.08-15.95) in the offspring of male workers who were employed during the two months before conception. We found evidence of a possible link between paternal preconception exposure of semiconductor manufacturing and an increased risk of congenital anomalies, especially of the heart. The possible etiological basis needs to be corroborated in further research.

Mass production of silicon pore optics for ATHENA

NASA Astrophysics Data System (ADS)

Wille, Eric; Bavdaz, Marcos; Collon, Maximilien

2016-07-01

Silicon Pore Optics (SPO) provide high angular resolution with low effective area density as required for the Advanced Telescope for High Energy Astrophysics (Athena). The x-ray telescope consists of several hundreds of SPO mirror modules. During the development of the process steps of the SPO technology, specific requirements of a future mass production have been considered right from the beginning. The manufacturing methods heavily utilise off-the-shelf equipment from the semiconductor industry, robotic automation and parallel processing. This allows to upscale the present production flow in a cost effective way, to produce hundreds of mirror modules per year. Considering manufacturing predictions based on the current technology status, we present an analysis of the time and resources required for the Athena flight programme. This includes the full production process starting with Si wafers up to the integration of the mirror modules. We present the times required for the individual process steps and identify the equipment required to produce two mirror modules per day. A preliminary timeline for building and commissioning the required infrastructure, and for flight model production of about 1000 mirror modules, is presented.

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique

PubMed Central

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique.

PubMed

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

Method of manufacturing semiconductor having group II-group VI compounds doped with nitrogen

DOEpatents

Compaan, Alvin D.; Price, Kent J.; Ma, Xianda; Makhratchev, Konstantin

2005-02-08

A method of making a semiconductor comprises depositing a group II-group VI compound onto a substrate in the presence of nitrogen using sputtering to produce a nitrogen-doped semiconductor. This method can be used for making a photovoltaic cell using sputtering to apply a back contact layer of group II-group VI compound to a substrate in the presence of nitrogen, the back coating layer being doped with nitrogen. A semiconductor comprising a group II-group VI compound doped with nitrogen, and a photovoltaic cell comprising a substrate on which is deposited a layer of a group II-group VI compound doped with nitrogen, are also included.

Inorganic acid emission factors of semiconductor manufacturing processes.

PubMed

Chein, HungMin; Chen, Tzu Ming; Aggarwal, Shankar Gopala; Tsai, Chuen-Jinn; Huang, Chun-Chao

2004-02-01

A huge amount of inorganic acids can be produced and emitted with waste gases from integrated circuit manufacturing processes such as cleaning and etching. Emission of inorganic acids from selected semiconductor factories was measured in this study. The sampling of the inorganic acids was based on the porous metal denuders, and samples were then analyzed by ion chromatography. The amount of chemical usage was adopted from the data that were reported to the Environmental Protection Bureau in Hsin-chu County according to the Taiwan Environmental Protection Agency regulation. The emission factor is defined as the emission rate (kg/month) divided by the amount of chemical usage (L/month). Emission factors of three inorganic acids (i.e., hydrofluoric acid [HF], hydrochloric acid [HCl], and sulfuric acid [H2SO4]) were estimated by the same method. The emission factors of HF and HCl were determined to be 0.0075 kg/L (coefficient of variation [CV] = 60.7%, n = 80) and 0.0096 kg/L (CV = 68.2%, n = 91), respectively. Linear regression equations are proposed to fit the data with correlation coefficient square (R2) = 0.82 and 0.9, respectively. The emission factor of H2SO4, which is in the droplet form, was determined to be 0.0016 kg/L (CV = 99.2%, n = 107), and its R2 was 0.84. The emission profiles of gaseous inorganic acids show that HF is the dominant chemical in most of the fabricators.

The Design and Assessment of a Hypermedia Course on Semiconductor Manufacturing.

ERIC Educational Resources Information Center

Schank, Patrick K.; Rowe, Lawrence A.

1993-01-01

Describes the design and evaluation of a multimedia course on integrated circuit manufacturing that was developed at the University of California at Berkeley using IC-HIP (Integrated Circuit-Hypermedia in PICASSO), a hypermedia-based instructional system. Learning effects based on prior knowledge, methods of navigation, and other factors are…

Ion-beam-induced bending of semiconductor nanowires.

PubMed

Hanif, Imran; Camara, Osmane; Tunes, Matheus A; Harrison, Robert W; Greaves, Graeme; Donnelly, Stephen E; Hinks, Jonathan A

2018-08-17

The miniaturisation of technology increasingly requires the development of both new structures as well as novel techniques for their manufacture and modification. Semiconductor nanowires (NWs) are a prime example of this and as such have been the subject of intense scientific research for applications ranging from microelectronics to nano-electromechanical devices. Ion irradiation has long been a key processing step for semiconductors and the natural extension of this technique to the modification of semiconductor NWs has led to the discovery of ion beam-induced deformation effects. In this work, transmission electron microscopy with in situ ion bombardment has been used to directly observe the evolution of individual silicon and germanium NWs under irradiation. Silicon NWs were irradiated with either 6 keV neon ions or xenon ions at 5, 7 or 9.5 keV with a flux of 3 × 10 13 ions cm -2 s -1 . Germanium NWs were irradiated with 30 or 70 keV xenon ions with a flux of 10 13 ions cm -2 s -1 . These new results are combined with those reported in the literature in a systematic analysis using a custom implementation of the transport of ions in matter Monte Carlo computer code to facilitate a direct comparison with experimental results taking into account the wide range of experimental conditions. Across the various studies this has revealed underlying trends and forms the basis of a critical review of the various mechanisms which have been proposed to explain the deformation of semiconductor NWs under ion irradiation.

Low-Temperature UV-Assisted Fabrication of Metal Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Zhu, Shuanglin

Solution processed metal oxide semiconductors have attracted intensive attention in the last several decades and have emerged as a promising candidate for the application of thin film transistor (TFT) due to their nature of transparency, flexibility, high mobility, simple processing technique and potential low manufacturing cost. However, metal oxide thin film fabricated by solution process usually requires a high temperature (over 300 °C), which is above the glass transition temperature of some conventional polymer substrates. In order to fabricate the flexible electronic device on polymer substrates, it is necessary to find a facile approach to lower the fabrication temperature and minimize defects in metal oxide thin film. In this thesis, the electrical properties dependency on temperature is discussed and an UV-assisted annealing method incorporating Deep ultraviolet (DUV)-decomposable additives is demonstrated, which can effectively improve electrical properties solution processed metal oxide semiconductors processed at temperature as low as 220 °C. By studying a widely used indium oxide (In2O3) TFT as a model system, it is worth noted that compared with the sample without UV treatment, the linear mobility and saturation mobility of UV-annealing sample are improved by 56% and 40% respectively. Meanwhile, the subthreshold swing is decreased by 32%, indicating UV-treated device could turn on and off more efficiently. In addition to pure In2O3 film, the similar phenomena have also been observed in indium oxide based Indium-Gallium-Zinc Oxide (IGZO) system. These finding presented in this thesis suggest that the UV assisted annealing process open a new route to fabricate high performance metal oxide semiconductors under low temperatures.

FY 2016 Research Highlights

DOE Office of Scientific and Technical Information (OSTI.GOV)

This fact sheet summarizes the research highlights for the Clean Energy Manufacturing Analysis Center (CEMAC) for Fiscal Year 2106. Topics covered include additive manufacturing for the wind industry, biomass-based chemicals substitutions, carbon fiber manufacturing facility siting, geothermal power plant turbines, hydrogen refueling stations, hydropower turbines, LEDs and lighting, light-duty automotive lithium-ion cells, magnetocaloric refrigeration, silicon carbide power electronics for variable frequency motor drives, solar photovoltaics, and wide bandgap semiconductor opportunities in power electronics.

A Survey of Terrestrial Approaches to the Challenge of Lunar Dust Containment

NASA Technical Reports Server (NTRS)

Aguilera, Tatiana; Perry, Jay L.

2009-01-01

Numerous technical challenges exist to successfully extend lunar surface exploration beyond the tantalizing first steps of Apollo. Among these is the challenge of lunar dust intrusion into the cabin environment. Addressing this challenge includes the design of barriers to intrusion as well as techniques for removing the dust from the cabin atmosphere. Opportunities exist for adapting approaches employed in dusty industrial operations and pristine manufacturing environments to cabin environmental quality maintenance applications. A survey of process technologies employed by the semiconductor, pharmaceutical, food processing, and mining industries offers insight into basic approaches that may be suitable for adaptation to lunar surface exploration applications.

A Silicon Nanocrystal Schottky Junction Solar Cell produced from Colloidal Silicon Nanocrystals

PubMed Central

2010-01-01

Solution-processed semiconductors are seen as a promising route to reducing the cost of the photovoltaic device manufacture. We are reporting a single-layer Schottky photovoltaic device that was fabricated by spin-coating intrinsic silicon nanocrystals (Si NCs) from colloidal suspension. The thin-film formation process was based on Si NCs without any ligand attachment, exchange, or removal reactions. The Schottky junction device showed a photovoltaic response with a power conversion efficiency of 0.02%, a fill factor of 0.26, short circuit-current density of 0.148 mA/cm2, and open-circuit voltage of 0.51 V. PMID:20676200

Method for forming metal contacts

DOEpatents

Reddington, Erik; Sutter, Thomas C; Bu, Lujia; Cannon, Alexandra; Habas, Susan E; Curtis, Calvin J; Miedaner, Alexander; Ginley, David S; Van Hest, Marinus Franciscus Antonius Maria

2013-09-17

Methods of forming metal contacts with metal inks in the manufacture of photovoltaic devices are disclosed. The metal inks are selectively deposited on semiconductor coatings by inkjet and aerosol apparatus. The composite is heated to selective temperatures where the metal inks burn through the coating to form an electrical contact with the semiconductor. Metal layers are then deposited on the electrical contacts by light induced or light assisted plating.

Method for fabricating pixelated silicon device cells

DOEpatents

Nielson, Gregory N.; Okandan, Murat; Cruz-Campa, Jose Luis; Nelson, Jeffrey S.; Anderson, Benjamin John

2015-08-18

A method, apparatus and system for flexible, ultra-thin, and high efficiency pixelated silicon or other semiconductor photovoltaic solar cell array fabrication is disclosed. A structure and method of creation for a pixelated silicon or other semiconductor photovoltaic solar cell array with interconnects is described using a manufacturing method that is simplified compared to previous versions of pixelated silicon photovoltaic cells that require more microfabrication steps.

Particle dispersing system and method for testing semiconductor manufacturing equipment

DOEpatents

Chandrachood, Madhavi; Ghanayem, Steve G.; Cantwell, Nancy; Rader, Daniel J.; Geller, Anthony S.

1998-01-01

The system and method prepare a gas stream comprising particles at a known concentration using a particle disperser for moving particles from a reservoir of particles into a stream of flowing carrier gas. The electrostatic charges on the particles entrained in the carrier gas are then neutralized or otherwise altered, and the resulting particle-laden gas stream is then diluted to provide an acceptable particle concentration. The diluted gas stream is then split into a calibration stream and the desired output stream. The particles in the calibration stream are detected to provide an indication of the actual size distribution and concentration of particles in the output stream that is supplied to a process chamber being analyzed. Particles flowing out of the process chamber within a vacuum pumping system are detected, and the output particle size distribution and concentration are compared with the particle size distribution and concentration of the calibration stream in order to determine the particle transport characteristics of a process chamber, or to determine the number of particles lodged in the process chamber as a function of manufacturing process parameters such as pressure, flowrate, temperature, process chamber geometry, particle size, particle charge, and gas composition.

Scalable maskless patterning of nanostructures using high-speed scanning probe arrays

NASA Astrophysics Data System (ADS)

Chen, Chen; Akella, Meghana; Du, Zhidong; Pan, Liang

2017-08-01

Nanoscale patterning is the key process to manufacture important products such as semiconductor microprocessors and data storage devices. Many studies have shown that it has the potential to revolutionize the functions of a broad range of products for a wide variety of applications in energy, healthcare, civil, defense and security. However, tools for mass production of these devices usually cost tens of million dollars each and are only affordable to the established semiconductor industry. A new method, nominally known as "pattern-on-the- y", that involves scanning an array of optical or electrical probes at high speed to form nanostructures and offers a new low-cost approach for nanoscale additive patterning. In this paper, we report some progress on using this method to pattern self-assembled monolayers (SAMs) on silicon substrate. We also functionalize the substrate with gold nanoparticle based on the SAM to show the feasibility of preparing amphiphilic and multi-functional surfaces.

Research and Design on a Product Data Definition System of Semiconductor Packaging Industry

NASA Astrophysics Data System (ADS)

Shi, Jinfei; Ma, Qingyao; Zhou, Yifan; Chen, Ruwen

2017-12-01

This paper develops a product data definition (PDD) system for a semiconductor packaging and testing company with independent intellectual property rights. The new PDD system can solve the problems such as, the effective control of production plans, the timely feedback of production processes, and the efficient schedule of resources. Firstly, this paper introduces the general requirements of the PDD system and depicts the operation flow and the data flow of the PDD system. Secondly, the overall design scheme of the PDD system is put forward. After that, the physical data model is developed using the Power Designer15.0 tool, and the database system is built. Finally, the function realization and running effects of the PDD system are analysed. The successful operation of the PDD system can realize the information flow among various production departments of the enterprise to meet the standard of the enterprise manufacturing integration and improve the efficiency of production management.

Ultracoherent operation of spin qubits with superexchange coupling

NASA Astrophysics Data System (ADS)

Rančić, Marko J.; Burkard, Guido

2017-11-01

With the use of nuclear-spin-free materials such as silicon and germanium, spin-based quantum bits (qubits) have evolved to become among the most coherent systems for quantum information processing. The new frontier for spin qubits has therefore shifted to the ubiquitous charge noise and spin-orbit interaction, which are limiting the coherence times and gate fidelities of solid-state qubits. In this paper we investigate superexchange, as a means of indirect exchange interaction between two single electron spin qubits, each embedded in a single semiconductor quantum dot (QD), mediated by an intermediate, empty QD. Our results suggest the existence of "supersweet spots", in which the qubit operations implemented by superexchange interaction are simultaneously first-order-insensitive to charge noise and to errors due to spin-orbit interaction. The proposed spin-qubit architecture is scalable and within the manufacturing capabilities of semiconductor industry.

Large-area triple-junction a-Si alloy production scaleup. Annual subcontract report, 17 March 1993--18 March 1994

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oswald, R.; Morris, J.

1994-11-01

The objective of this subcontract over its three-year duration is to advance Solarex`s photovoltaic manufacturing technologies, reduce its a-Si:H module production costs, increase module performance and expand the Solarex commercial production capacity. Solarex shall meet these objectives by improving the deposition and quality of the transparent front contact, by optimizing the laser patterning process, scaling-up the semiconductor deposition process, improving the back contact deposition, scaling-up and improving the encapsulation and testing of its a-Si:H modules. In the Phase 2 portion of this subcontract, Solarex focused on improving deposition of the front contact, investigating alternate feed stocks for the front contact,more » maximizing throughput and area utilization for all laser scribes, optimizing a-Si:H deposition equipment to achieve uniform deposition over large-areas, optimizing the triple-junction module fabrication process, evaluating the materials to deposit the rear contact, and optimizing the combination of isolation scribe and encapsulant to pass the wet high potential test. Progress is reported on the following: Front contact development; Laser scribe process development; Amorphous silicon based semiconductor deposition; Rear contact deposition process; Frit/bus/wire/frame; Materials handling; and Environmental test, yield and performance analysis.« less

Infrared nanoantenna apparatus and method for the manufacture thereof

DOEpatents

Peters, David W.; Davids, Paul; Leonhardt, Darin; Kim, Jin K.; Wendt, Joel R.; Klem, John F.

2014-06-10

An exemplary embodiment of the present invention is a photodetector comprising a semiconductor body, a periodically patterned metal nanoantenna disposed on a surface of the semiconductor body, and at least one electrode separate from the nanoantenna. The semiconductor body comprises an active layer in sufficient proximity to the nanoantenna for plasmonic coupling thereto. The nanoantenna is dimensioned to absorb electromagnetic radiation in at least some wavelengths not more than 12 .mu.m that are effective for plasmonic coupling into the active layer. The electrode is part of an electrode arrangement for obtaining a photovoltage or photocurrent in operation under appropriate stimulation.

Augmenting SCA project management and automation framework

NASA Astrophysics Data System (ADS)

Iyapparaja, M.; Sharma, Bhanupriya

2017-11-01

In our daily life we need to keep the records of the things in order to manage it in more efficient and proper way. Our Company manufactures semiconductor chips and sale it to the buyer. Sometimes it manufactures the entire product and sometimes partially and sometimes it sales the intermediary product obtained during manufacturing, so for the better management of the entire process there is a need to keep the track record of all the entity involved in it. Materials and Methods: Therefore to overcome with the problem the need raised to develop the framework for the maintenance of the project and for the automation testing. Project management framework provides an architecture which supports in managing the project by marinating the records of entire requirements, the test cases that were created for testing each unit of the software, defect raised from the past years. So through this the quality of the project can be maintained. Results: Automation framework provides the architecture which supports the development and implementation of the automation test script for the software testing process. Conclusion: For implementing project management framework the product of HP that is Application Lifecycle management is used which provides central repository to maintain the project.

Addressing Production System Failures Using Multi-agent Control

NASA Astrophysics Data System (ADS)

Gautam, Rajesh; Miyashita, Kazuo

Output in high-volume production facilities is limited by bottleneck machines. We propose a control mechanism by modeling workstations as agents that pull jobs from other agents based on their current WIP level and requirements. During failures, when flows of some jobs are disrupted, the agents pull alternative jobs to maintain utilization of their capacity at a high level. In this paper, we empirically demonstrate that the proposed mechanism can react to failures more appropriately than other control mechanisms using a benchmark problem of a semiconductor manufacturing process.

Large Bandgap Shrinkage from Doping and Dielectric Interface in Semiconducting Carbon Nanotubes

NASA Astrophysics Data System (ADS)

Comfort, Everett; Lee, Ji Ung

2016-06-01

The bandgap of a semiconductor is one of its most important electronic properties. It is often considered to be a fixed property of the semiconductor. As the dimensions of semiconductors reduce, however, many-body effects become dominant. Here, we show that doping and dielectric, two critical features of semiconductor device manufacturing, can dramatically shrink (renormalize) the bandgap. We demonstrate this in quasi-one-dimensional semiconducting carbon nanotubes. Specifically, we use a four-gated device, configured as a p-n diode, to investigate the fundamental electronic structure of individual, partially supported nanotubes of varying diameter. The four-gated construction allows us to combine both electrical and optical spectroscopic techniques to measure the bandgap over a wide doping range.

Flow-Directed Crystallization for Printed Electronics.

PubMed

Qu, Ge; Kwok, Justin J; Diao, Ying

2016-12-20

The solution printability of organic semiconductors (OSCs) represents a distinct advantage for materials processing, enabling low-cost, high-throughput, and energy-efficient manufacturing with new form factors that are flexible, stretchable, and transparent. While the electronic performance of OSCs is not comparable to that of crystalline silicon, the solution processability of OSCs allows them to complement silicon by tackling challenging aspects for conventional photolithography, such as large-area electronics manufacturing. Despite this, controlling the highly nonequilibrium morphology evolution during OSC printing remains a challenge, hindering the achievement of high electronic device performance and the elucidation of structure-property relationships. Many elegant morphological control methodologies have been developed in recent years including molecular design and novel processing approaches, but few have utilized fluid flow to control morphology in OSC thin films. In this Account, we discuss flow-directed crystallization as an effective strategy for controlling the crystallization kinetics during printing of small molecule and polymer semiconductors. Introducing the concept of flow-directed crystallization to the field of printed electronics is inspired by recent advances in pharmaceutical manufacturing and flow processing of flexible-chain polymers. Although flow-induced crystallization is well studied in these areas, previous findings may not apply directly to the field of printed electronics where the molecular structures (i.e., rigid π-conjugated backbone decorated with flexible side chains) and the intermolecular interactions (i.e., π-π interactions, quadrupole interactions) of OSCs differ substantially from those of pharmaceuticals or flexible-chain polymers. Another critical difference is the important role of solvent evaporation in open systems, which defines the flow characteristics and determines the crystallization kinetics and pathways. In other words, flow-induced crystallization is intimately coupled with the mass transport processes driven by solvent evaporation during printing. In this Account, we will highlight these distinctions of flow-directed crystallization for printed electronics. In the context of solution printing of OSCs, the key issue that flow-directed crystallization addresses is the kinetics mismatch between crystallization and various transport processes during printing. We show that engineering fluid flows can tune the kinetics of OSC crystallization by expediting the nucleation and crystal growth processes, significantly enhancing thin film morphology and device performance. For small molecule semiconductors, nucleation can be enhanced and patterned by directing the evaporative flux via contact line engineering, and defective crystal growth can be alleviated by enhancing mass transport to yield significantly improved coherence length and reduced grain boundaries. For conjugated polymers, extensional and shear flow can expedite nucleation through flow-induced conformation change, facilitating the control of microphase separation, degree of crystallinity, domain alignment, and percolation. Although the nascent concept of flow-directed solution printing has not yet been widely adopted in the field of printed electronics, we anticipate that it can serve as a platform technology in the near future for improving device performance and for systematically tuning thin film morphology to construct structure-property relationships. From a fundamental perspective, it is imperative to develop a better understanding of the effects of fluid flow and mass transport on OSC crystallization as these processes are ubiquitous across all solution processing techniques and can critically impact charge transport properties.

Modifying the Interface Edge to Control the Electrical Transport Properties of Nanocontacts to Nanowires.

PubMed

Lord, Alex M; Ramasse, Quentin M; Kepaptsoglou, Despoina M; Evans, Jonathan E; Davies, Philip R; Ward, Michael B; Wilks, Steve P

2017-02-08

Selecting the electrical properties of nanomaterials is essential if their potential as manufacturable devices is to be reached. Here, we show that the addition or removal of native semiconductor material at the edge of a nanocontact can be used to determine the electrical transport properties of metal-nanowire interfaces. While the transport properties of as-grown Au nanocatalyst contacts to semiconductor nanowires are well-studied, there are few techniques that have been explored to modify the electrical behavior. In this work, we use an iterative analytical process that directly correlates multiprobe transport measurements with subsequent aberration-corrected scanning transmission electron microscopy to study the effects of chemical processes that create structural changes at the contact interface edge. A strong metal-support interaction that encapsulates the Au nanocontacts over time, adding ZnO material to the edge region, gives rise to ohmic transport behavior due to the enhanced quantum-mechanical tunneling path. Removal of the extraneous material at the Au-nanowire interface eliminates the edge-tunneling path, producing a range of transport behavior that is dependent on the final interface quality. These results demonstrate chemically driven processes that can be factored into nanowire-device design to select the final properties.

Method and apparatus for increasing the durability and yield of thin film photovoltaic devices

DOEpatents

Phillips, J.E.; Lasswell, P.G.

1987-02-03

Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device. 10 figs.

Method and apparatus for increasing the durability and yield of thin film photovoltaic devices

DOEpatents

Phillips, James E.; Lasswell, Patrick G.

1987-01-01

Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device.

A vertical-energy-thresholding procedure for data reduction with multiple complex curves.

PubMed

Jung, Uk; Jeong, Myong K; Lu, Jye-Chyi

2006-10-01

Due to the development of sensing and computer technology, measurements of many process variables are available in current manufacturing processes. It is very challenging, however, to process a large amount of information in a limited time in order to make decisions about the health of the processes and products. This paper develops a "preprocessing" procedure for multiple sets of complicated functional data in order to reduce the data size for supporting timely decision analyses. The data type studied has been used for fault detection, root-cause analysis, and quality improvement in such engineering applications as automobile and semiconductor manufacturing and nanomachining processes. The proposed vertical-energy-thresholding (VET) procedure balances the reconstruction error against data-reduction efficiency so that it is effective in capturing key patterns in the multiple data signals. The selected wavelet coefficients are treated as the "reduced-size" data in subsequent analyses for decision making. This enhances the ability of the existing statistical and machine-learning procedures to handle high-dimensional functional data. A few real-life examples demonstrate the effectiveness of our proposed procedure compared to several ad hoc techniques extended from single-curve-based data modeling and denoising procedures.

A System for Planning Ahead

NASA Technical Reports Server (NTRS)

2002-01-01

A software system that uses artificial intelligence techniques to help with complex Space Shuttle scheduling at Kennedy Space Center is commercially available. Stottler Henke Associates, Inc.(SHAI), is marketing its automatic scheduling system, the Automated Manifest Planner (AMP), to industries that must plan and project changes many different times before the tasks are executed. The system creates optimal schedules while reducing manpower costs. Using information entered into the system by expert planners, the system automatically makes scheduling decisions based upon resource limitations and other constraints. It provides a constraint authoring system for adding other constraints to the scheduling process as needed. AMP is adaptable to assist with a variety of complex scheduling problems in manufacturing, transportation, business, architecture, and construction. AMP can benefit vehicle assembly plants, batch processing plants, semiconductor manufacturing, printing and textiles, surface and underground mining operations, and maintenance shops. For most of SHAI's commercial sales, the company obtains a service contract to customize AMP to a specific domain and then issues the customer a user license.

Silicon pore optics for future x-ray telescopes

NASA Astrophysics Data System (ADS)

Wille, Eric; Bavdaz, Marcos; Wallace, Kotska; Shortt, Brian; Collon, Maximilien; Ackermann, Marcelo; Günther, Ramses; Olde Riekerink, Mark; Koelewijn, Arenda; Haneveld, Jeroen; van Baren, Coen; Erhard, Markus; Kampf, Dirk; Christensen, Finn; Krumrey, Michael; Freyberg, Michael; Burwitz, Vadim

2017-11-01

Lightweight X-ray Wolter optics with a high angular resolution will enable the next generation of X-ray telescopes in space. The candidate mission ATHENA (Advanced Telescope for High Energy Astrophysics) required a mirror assembly of 1 m2 effective area (at 1 keV) and an angular resolution of 10 arcsec or better. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is being developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor industry. We present the recent upgrades made to the manufacturing processes and equipment, ranging from the manufacture of single mirror plates towards complete focusing mirror modules mounted in flight configuration, and results from first vibration tests. The performance of the mirror modules is tested at X-ray facilities that were recently extended to measure optics at a focal distance up to 20 m.

Study of correlation between overlay and displacement measured by Coherent Gradient Sensing (CGS) interferometry

NASA Astrophysics Data System (ADS)

Mileham, Jeffrey; Tanaka, Yasushi; Anberg, Doug; Owen, David M.; Lee, Byoung-Ho; Bouche, Eric

2016-03-01

Within the semiconductor lithographic process, alignment control is one of the most critical considerations. In order to realize high device performance, semiconductor technology is approaching the 10 nm design rule, which requires progressively smaller overlay budgets. Simultaneously, structures are expanding in the 3rd dimension, thereby increasing the potential for inter-layer distortion. For these reasons, device patterning is becoming increasingly difficult as the portion of the overlay budget attributed to process-induced variation increases. After lithography, overlay gives valuable feedback to the lithography tool; however overlay measurements typically have limited density, especially at the wafer edge, due to throughput considerations. Moreover, since overlay is measured after lithography, it can only react to, but not predict the process-induced overlay. This study is a joint investigation in a high-volume manufacturing environment of the portion of overlay associated with displacement induced by a single process across many chambers. Displacement measurements are measured by Coherent Gradient Sensing (CGS) interferometry, which generates high-density displacement maps (>3 million points on a 300 mm wafer) such that the stresses induced die-by-die and process-by-process can be tracked in detail. The results indicate the relationship between displacement and overlay shows the ability to forecast overlay values before the lithographic process. Details of the correlation including overlay/displacement range, and lot-to-lot displacement variability are considered.

All-semiconductor high-speed akinetic swept-source for OCT

NASA Astrophysics Data System (ADS)

Minneman, Michael P.; Ensher, Jason; Crawford, Michael; Derickson, Dennis

2011-12-01

A novel swept-wavelength laser for optical coherence tomography (OCT) using a monolithic semiconductor device with no moving parts is presented. The laser is a Vernier-Tuned Distributed Bragg Reflector (VT-DBR) structure exhibiting a single longitudinal mode. All-electronic wavelength tuning is achieved at a 200 kHz sweep repetition rate, 20 mW output power, over 100 nm sweep width and coherence length longer than 40 mm. OCT point-spread functions with 45- 55 dB dynamic range are demonstrated; lasers at 1550 nm, and now 1310 nm, have been developed. Because the laser's long-term tuning stability allows for electronic sample trigger generation at equal k-space intervals (electronic k-clock), the laser does not need an external optical k-clock for measurement interferometer sampling. The non-resonant, allelectronic tuning allows for continuously adjustable sweep repetition rates from mHz to 100s of kHz. Repetition rate duty cycles are continuously adjustable from single-trigger sweeps to over 99% duty cycle. The source includes a monolithically integrated power leveling feature allowing flat or Gaussian power vs. wavelength profiles. Laser fabrication is based on reliable semiconductor wafer-scale processes, leading to low and rapidly decreasing cost of manufacture.

2001 Industry Studies: Electronics

DTIC Science & Technology

2001-01-01

Center, Dallas, TX Northrop Grumman Corp, Electronic Sensors & Systems, Baltimore, MD International Acer Incorporated, Hsin Chu, Taiwan Aerospace...manufacturing. Many of the large-scale fabrication foundries are offshore in such countries as Taiwan, Singapore and Malaysia .5 - 5 - The largest market for...done in the US. However, more of the actual mass manufacturing of the chips are done in Taiwan, Singapore, and Malaysia . A new semiconductor facility

Methods for manufacturing geometric multi-crystalline cast materials

DOEpatents

Stoddard, Nathan G

2013-11-26

Methods are provided for casting one or more of a semi-conductor, an oxide, and an intermetallic material. With such methods, a cast body of a geometrically ordered multi-crystalline form of the one or more of a semiconductor, an oxide, and an intermetallic material may be formed that is free or substantially free of radially-distributed impurities and defects and having at least two dimensions that are each at least about 10 cm.

Methods for manufacturing monocrystalline or near-monocrystalline cast materials

DOEpatents

Stoddard, Nathan G

2014-04-29

Methods are provided for casting one or more of a semiconductor, an oxide, and an intermetallic material. With such methods, a cast body of a monocrystalline form of the one or more of a semiconductor, an oxide, and an intermetallic material may be formed that is free of, or substantially free of, radially-distributed impurities and defects and having at least two dimensions that are each at least about 35 cm.

Computers and Employment.

ERIC Educational Resources Information Center

McConnell, Sheila; And Others

1996-01-01

Includes "Role of Computers in Reshaping the Work Force" (McConnell); "Semiconductors" (Moris); "Computer Manufacturing" (Warnke); "Commercial Banking Transformed by Computer Technology" (Morisi); "Software, Engineering Industries: Threatened by Technological Change?" (Goodman); "Job Creation…

Virtual Metrology applied in Run-to-Run Control for a Chemical Mechanical Planarization process

NASA Astrophysics Data System (ADS)

Jebri, M. A.; El Adel, E. M.; Graton, G.; Ouladsine, M.; Pinaton, J.

2017-01-01

This paper deals with missing data in semiconductor manufacturing derived from a measurement sampling strategies. The idea is to construct a virtual metrology module to estimate non measured variables using a new modified Just-In-Time Learning approach (JITL). The aim of this paper is to integrate estimated data into product control loop. In collaboration with our industrial partner STMicroelectronics Rousset, the accuracy of the proposed method is illustrated by using industrial data-sets derived from Chemical Mechanical Planarization (CMP) process that enables us to compare results obtained with the classical and the modified version of JITL approach. Then, the contribution of the estimated data is shown in product quality improvement.

Technological innovations for a sustainable business model in the semiconductor industry

NASA Astrophysics Data System (ADS)

Levinson, Harry J.

2014-09-01

Increasing costs of wafer processing, particularly for lithographic processes, have made it increasingly difficult to achieve simultaneous reductions in cost-per-function and area per device. Multiple patterning techniques have made possible the fabrication of circuit layouts below the resolution limit of single optical exposures but have led to significant increases in the costs of patterning. Innovative techniques, such as self-aligned double patterning (SADP) have enabled good device performance when using less expensive patterning equipment. Other innovations have directly reduced the cost of manufacturing. A number of technical challenges must be overcome to enable a return to single-exposure patterning using short wavelength optical techniques, such as EUV patterning.

Multilayer Semiconductor Charged-Particle Spectrometers for Accelerator Experiments

NASA Astrophysics Data System (ADS)

Gurov, Yu. B.; Lapushkin, S. V.; Sandukovsky, V. G.; Chernyshev, B. A.

2018-03-01

The current state of studies in the field of development of multilayer semiconductor systems (semiconductor detector (SCD) telescopes), which allow the energy to be precisely measured within a large dynamic range (from a few to a few hundred MeV) and the particles to be identified in a wide mass range (from pions to multiply charged nuclear fragments), is presented. The techniques for manufacturing the SCD telescopes from silicon and high-purity germanium are described. The issues of measuring characteristics of the constructed detectors and their impact on the energy resolution of the SCD telescopes and on the quality of the experimental data are considered. Much attention is given to the use of the constructed semiconductor devices in experimental studies at accelerators of PNPI (Gatchina), LANL (Los Alamos) and CELSIUS (Uppsala).

Presidential Green Chemistry Challenge: 2002 Small Business Award

EPA Pesticide Factsheets

Presidential Green Chemistry Challenge 2002 award winner, SC Fluids, with Los Alamos National Laboratory, developed supercritical CO2 resist remover technology to clean residues from semiconductor wafers during manufacture.

Injection molding of high precision optics for LED applications made of liquid silicone rubber

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hopmann, Christian; Röbig, Malte

Light Emitting Diodes (LED) conquer the growing global market of lighting technologies. Due to their advantages, they are increasingly used in consumer products, in lighting applications in the home and in the mobility sector as well as in industrial applications. Particularly, with regard to the increasing use of high-power LED (HP-LED) the materials in the surrounding area of the light emitting semiconductor chip are of utmost importance. While the materials behind the semiconductor chip are optimized for maximum heat dissipation, the materials currently used for the encapsulation of the semiconductor chip (primary optics) and the secondary optics encounter their limitsmore » due to the high temperatures. In addition certain amounts of blue UV radiation degrade the currently used materials such as epoxy resins or polyurethanes for primary optics. In the context of an ongoing joint research project with various partners from the industry, an innovative manufacturing method for high precision optics for LED applications made of liquid silicone rubber (LSR) is analyzed at the Institut of Plastics Processing (IKV), Aachen. The aim of this project is to utilize the material-specific advantages of high transparent LSR, especially the excellent high temperature resistance and the great freedom in design. Therefore, a high integrated injection molding process is developed. For the production of combined LED primary and secondary optics a LED board is placed in an injection mold and overmolded with LSR. Due to the integrated process and the reduction of subcomponents like the secondary optics the economics of the production process can be improved significantly. Furthermore combined LED optics offer an improved effectiveness, because there are no losses of the light power at the transition of the primary and secondary optics.« less

Advanced Microelectronics Technologies for Future Small Satellite Systems

NASA Technical Reports Server (NTRS)

Alkalai, Leon

1999-01-01

Future small satellite systems for both Earth observation as well as deep-space exploration are greatly enabled by the technological advances in deep sub-micron microelectronics technologies. Whereas these technological advances are being fueled by the commercial (non-space) industries, more recently there has been an exciting new synergism evolving between the two otherwise disjointed markets. In other words, both the commercial and space industries are enabled by advances in low-power, highly integrated, miniaturized (low-volume), lightweight, and reliable real-time embedded systems. Recent announcements by commercial semiconductor manufacturers to introduce Silicon On Insulator (SOI) technology into their commercial product lines is driven by the need for high-performance low-power integrated devices. Moreover, SOI has been the technology of choice for many space semiconductor manufacturers where radiation requirements are critical. This technology has inherent radiation latch-up immunity built into the process, which makes it very attractive to space applications. In this paper, we describe the advanced microelectronics and avionics technologies under development by NASA's Deep Space Systems Technology Program (also known as X2000). These technologies are of significant benefit to both the commercial satellite as well as the deep-space and Earth orbiting science missions. Such a synergistic technology roadmap may truly enable quick turn-around, low-cost, and highly capable small satellite systems for both Earth observation as well as deep-space missions.

Protons, Aerospace, and Electronics: A National Interest

NASA Technical Reports Server (NTRS)

Label, Kenneth A.; Turflinger, Thomas L.

2017-01-01

The aerospace and semiconductor industries lost 2000 hours annually of research access when IUCF closed. An ad hoc team between the U.S. government and industry was formed to evaluate other facility options. In this presentation, we will discuss: 1) Why aerospace, semiconductor manufacturers, and others are interested in proton facility access, as well as, 2) Some of the basics of a typical test for electronics, and 3) We'll conclude with the brief current status on progress.

Protons, Aerospace, and Electronics: A National Interest

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Turflinger, Thomas L.

2018-01-01

The aerospace and semiconductor industries lost approximately 2000 hours annually of research access when IUCF closed. An ad hoc team between the U.S. government and industry was formed to evaluate other facility options. In this presentation, we will discuss: 1) Why aerospace, semiconductor manufacturers, and others are interested in proton facility access, as well as, 2) Some of the basics of a typical tests for electronics, and 3) We'll conclude with the brief current status on progress.

Protons, Aerospace, and Electronics: A National Interest

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Turflinger, Thomas L.

2018-01-01

The aerospace and semiconductor industries lost approx. 2000 hours annually of research access when IUCF closed. An ad hoc team between the U.S. government and industry was formed to evaluate other facility options. In this presentation, we will discuss: 1) Why aerospace, semiconductor manufacturers, and others are interested in proton facility access, as well as, 2) Some of the basics of a typical test for electronics, and 3) We"ll conclude with the brief current status on progress.

Organic Diode Rectifiers Based on a High-Performance Conjugated Polymer for a Near-Field Energy-Harvesting Circuit.

PubMed

Higgins, Stuart G; Agostinelli, Tiziano; Markham, Steve; Whiteman, Robert; Sirringhaus, Henning

2017-12-01

Organic diodes manufactured on a plastic substrate capable of rectifying a high-frequency radio-frequency identification signal (13.56 MHz), with sufficient power to operate an interactive smart tag, are reported. A high-performance conjugated semiconductor (an indacenodithiophene-benzothiadiazole copolymer) is combined with a carefully optimized architecture to satisfy the electrical requirements for an organic-semiconductor-based logic chip. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

PULSION® HP: Tunable, High Productivity Plasma Doping

NASA Astrophysics Data System (ADS)

Felch, S. B.; Torregrosa, F.; Etienne, H.; Spiegel, Y.; Roux, L.; Turnbaugh, D.

2011-01-01

Plasma doping has been explored for many implant applications for over two decades and is now being used in semiconductor manufacturing for two applications: DRAM polysilicon counter-doping and contact doping. The PULSION HP is a new plasma doping tool developed by Ion Beam Services for high-volume production that enables customer control of the dominant mechanism—deposition, implant, or etch. The key features of this tool are a proprietary, remote RF plasma source that enables a high density plasma with low chamber pressure, resulting in a wide process space, and special chamber and wafer electrode designs that optimize doping uniformity.

Real-Time Optical Detection of Single Nanoparticles and Viruses Using Heterodyne Interferometry

NASA Astrophysics Data System (ADS)

Mitra, Anirban; Novotny, Lukas

Nanoparticles play a significant role in various fields such as biomedical imaging and diagnostics [1-4], process control in semiconductor manufacturing [5], explosives [6], environmental monitoring and climate change [7, 8], and various other fields. Inhalation of ultrafine particulates in air has been shown to have adverse effects, such as inflammation of lungs or pulmonary and cardiovascular diseases [9, 10]. Nano-sized biological agents and pathogens such as viruses are known to be responsible for a wide variety of human diseases such as flu, AIDS and herpes, and have been used as biowarfare agents [11, 12].

WAMA: a method of optimizing reticle/die placement to increase litho cell productivity

NASA Astrophysics Data System (ADS)

Dor, Amos; Schwarz, Yoram

2005-05-01

This paper focuses on reticle/field placement methodology issues, the disadvantages of typical methods used in the industry, and the innovative way that the WAMA software solution achieves optimized placement. Typical wafer placement methodologies used in the semiconductor industry considers a very limited number of parameters, like placing the maximum amount of die on the wafer circle and manually modifying die placement to minimize edge yield degradation. This paper describes how WAMA software takes into account process characteristics, manufacturing constraints and business objectives to optimize placement for maximum stepper productivity and maximum good die (yield) on the wafer.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

Quantum control and process tomography of a semiconductor quantum dot hybrid qubit.

PubMed

Kim, Dohun; Shi, Zhan; Simmons, C B; Ward, D R; Prance, J R; Koh, Teck Seng; Gamble, John King; Savage, D E; Lagally, M G; Friesen, Mark; Coppersmith, S N; Eriksson, Mark A

2014-07-03

The similarities between gated quantum dots and the transistors in modern microelectronics--in fabrication methods, physical structure and voltage scales for manipulation--have led to great interest in the development of quantum bits (qubits) in semiconductor quantum dots. Although quantum dot spin qubits have demonstrated long coherence times, their manipulation is often slower than desired for important future applications, such as factoring. Furthermore, scalability and manufacturability are enhanced when qubits are as simple as possible. Previous work has increased the speed of spin qubit rotations by making use of integrated micromagnets, dynamic pumping of nuclear spins or the addition of a third quantum dot. Here we demonstrate a qubit that is a hybrid of spin and charge. It is simple, requiring neither nuclear-state preparation nor micromagnets. Unlike previous double-dot qubits, the hybrid qubit enables fast rotations about two axes of the Bloch sphere. We demonstrate full control on the Bloch sphere with π-rotation times of less than 100 picoseconds in two orthogonal directions, which is more than an order of magnitude faster than any other double-dot qubit. The speed arises from the qubit's charge-like characteristics, and its spin-like features result in resistance to decoherence over a wide range of gate voltages. We achieve full process tomography in our electrically controlled semiconductor quantum dot qubit, extracting high fidelities of 85 per cent for X rotations (transitions between qubit states) and 94 per cent for Z rotations (phase accumulation between qubit states).

Progress in a novel architecture for high performance processing

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Liu, Meng; Liu, Zijun; Du, Xueliang; Xie, Shaolin; Ma, Hong; Ding, Guangxin; Ren, Weili; Zhou, Fabiao; Sun, Wenqin; Wang, Huijuan; Wang, Donglin

2018-04-01

The high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance. It is suitable for data intensive applications like supercomputing, machine learning and wireless communication. An example chip with four application-specific integrated circuit (ASIC) cores which is the first generation of HPP cores has been taped out successfully under Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm low power process. The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU). Compared with MaPU, HPP has made great improvement in architecture. The chip with 32 HPP cores is being developed under TSMC 16 nm field effect transistor (FFC) technology process and is planed to use commercially. The peak performance of this chip can reach 4.3 teraFLOPS (TFLOPS) and its power efficiency is up to 89.5 gigaFLOPS per watt (GFLOPS/W).

Workplace Safety and Health Topics: Industries and Occupations

MedlinePlus

... Workplace Exposure Control Nanotechnology Occupational Health Psychology Office Environment and Worker Safety and Health Outdoor Workers Poultry Industry Workers Productive Aging and Work Safe, Green, and Sustainable Construction Semiconductor Manufacturing Small Business ...

Coutts Earns Prestigious Research Award

Science.gov Websites

cells—their manufacture uses less of the expensive semiconductor material that converts light into , a technology that uses heat instead of sunlight to generate electricity, and has authored or co

Photo-voltaic power generating means and methods

DOEpatents

Kroger, Ferdinand A.; Rod, Robert L.; Panicker, M. P. Ramachandra

1983-08-23

A photo-voltaic power cell based on a photoelectric semiconductor compound and the method of using and making the same. The semiconductor compound in the photo-voltaic power cell of the present invention can be electrolytically formed at a cathode in an electrolytic solution by causing discharge or decomposition of ions or molecules of a non-metallic component with deposition of the non-metallic component on the cathode and simultaneously providing ions of a metal component which discharge and combine with the non-metallic component at the cathode thereby forming the semiconductor compound film material thereon. By stoichiometrically adjusting the amounts of the components, or otherwise by introducing dopants into the desired amounts, an N-type layer can be formed and thereafter a P-type layer can be formed with a junction therebetween. The invention is effective in producing homojunction semiconductor materials and heterojunction semiconductor materials. The present invention also provides a method of using three electrodes in order to form the semiconductor compound material on one of these electrodes. Various examples are given for manufacturing different photo-voltaic cells in accordance with the present invention.

Photo-voltaic power generating means and methods

DOEpatents

Kroger, Ferdinand A.; Rod, Robert L.; Panicker, Ramachandra M. P.; Knaster, Mark B.

1984-01-10

A photo-voltaic power cell based on a photoelectric semiconductor compound and the method of using and making the same. The semiconductor compound in the photo-voltaic power cell of the present invention can be electrolytically formed at a cathode in an electrolytic solution by causing discharge or decomposition of ions or molecules of a non-metallic component with deposition of the non-metallic component on the cathode and simultaneously providing ions of a metal component which discharge and combine with the non-metallic component at the cathode thereby forming the semiconductor compound film material thereon. By stoichiometrically adjusting the amounts of the components, or otherwise by introducing dopants into the desired amounts, an N-type layer can be formed and thereafter a P-type layer can be formed with a junction therebetween. The invention is effective in producing homojunction semiconductor materials and heterojunction semiconductor materials. The present invention also provides a method of using three electrodes in order to form the semiconductor compound material on one of these electrodes. Various examples are given for manufacturing different photo-voltaic cells in accordance with the present invention.

2012 Mask Industry Survey

NASA Astrophysics Data System (ADS)

Malloy, Matt; Litt, Lloyd C.

2012-11-01

A survey supported by SEMATECH and administered by David Powell Consulting was sent to semiconductor industry leaders to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of semiconductor company mask technologists and merchant mask suppliers. 2012 marks the 11th consecutive year for the mask industry survey. This year's survey and reporting structure are similar to those of the previous years with minor modifications based on feedback from past years and the need to collect additional data on key topics. Categories include general mask information, mask processing, data and write time, yield and yield loss, delivery times, and maintenance and returns. Within each category are multiple questions that result in a detailed profile of both the business and technical status of the mask industry. Results, initial observations, and key comparisons between the 2011 and 2012 survey responses are shown here, including multiple indications of a shift towards the manufacturing of higher end photomasks.

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down tomore » the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.« less

Polycrystalline silicon availability for photovoltaic and semiconductor industries

NASA Technical Reports Server (NTRS)

Ferber, R. R.; Costogue, E. N.; Pellin, R.

1982-01-01

Markets, applications, and production techniques for Siemens process-produced polycrystalline silicon are surveyed. It is noted that as of 1982 a total of six Si materials suppliers were servicing a worldwide total of over 1000 manufacturers of Si-based devices. Besides solar cells, the Si wafers are employed for thyristors, rectifiers, bipolar power transistors, and discrete components for control systems. An estimated 3890 metric tons of semiconductor-grade polycrystalline Si will be used in 1982, and 6200 metric tons by 1985. Although the amount is expected to nearly triple between 1982-89, research is being carried out on the formation of thin films and ribbons for solar cells, thereby eliminating the waste produced in slicing Czolchralski-grown crystals. The free-world Si production in 1982 is estimated to be 3050 metric tons. Various new technologies for the formation of polycrystalline Si at lower costs and with less waste are considered. New entries into the industrial Si formation field are projected to produce a 2000 metric ton excess by 1988.

Toward Cost-Effective Manufacturing of Silicon Solar Cells: Electrodeposition of High-Quality Si Films in a CaCl2 -based Molten Salt.

PubMed

Yang, Xiao; Ji, Li; Zou, Xingli; Lim, Taeho; Zhao, Ji; Yu, Edward T; Bard, Allen J

2017-11-20

Electrodeposition of Si films from a Si-containing electrolyte is a cost-effective approach for the manufacturing of solar cells. Proposals relying on fluoride-based molten salts have suffered from low product quality due to difficulties in impurity control. Here we demonstrate the successful electrodeposition of high-quality Si films from a CaCl 2 -based molten salt. Soluble Si IV -O anions generated from solid SiO 2 are electrodeposited onto a graphite substrate to form a dense film of crystalline Si. Impurities in the deposited Si film are controlled at low concentrations (both B and P are less than 1 ppm). In the photoelectrochemical measurements, the film shows p-type semiconductor character and large photocurrent. A p-n junction fabricated from the deposited Si film exhibits clear photovoltaic effects. This study represents the first step to the ultimate goal of developing a cost-effective manufacturing process for Si solar cells based on electrodeposition. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Challenges to Scaling CIGS Photovoltaics

NASA Astrophysics Data System (ADS)

Stanbery, B. J.

2011-03-01

The challenges of scaling any photovoltaic technology to terawatts of global capacity are arguably more economic than technological or resource constraints. All commercial thin-film PV technologies are based on direct bandgap semiconductors whose absorption coefficient and bandgap alignment with the solar spectrum enable micron-thick coatings in lieu to hundreds of microns required using indirect-bandgap c-Si. Although thin-film PV reduces semiconductor materials cost, its manufacture is more capital intensive than c-Si production, and proportional to deposition rate. Only when combined with sufficient efficiency and cost of capital does this tradeoff yield lower manufacturing cost. CIGS has the potential to become the first thin film technology to achieve the terawatt benchmark because of its superior conversion efficiency, making it the only commercial thin film technology which demonstrably delivers performance comparable to the dominant incumbent, c-Si. Since module performance leverages total systems cost, this competitive advantage bears directly on CIGS' potential to displace c-Si and attract the requisite capital to finance the tens of gigawatts of annual production capacity needed to manufacture terawatts of PV modules apace with global demand growth.

Investigation of model-based physical design restrictions (Invited Paper)

NASA Astrophysics Data System (ADS)

Lucas, Kevin; Baron, Stanislas; Belledent, Jerome; Boone, Robert; Borjon, Amandine; Couderc, Christophe; Patterson, Kyle; Riviere-Cazaux, Lionel; Rody, Yves; Sundermann, Frank; Toublan, Olivier; Trouiller, Yorick; Urbani, Jean-Christophe; Wimmer, Karl

2005-05-01

As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions. Therefore, similar to the semiconductor industry's transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

1.05-GHz CMOS oscillator based on lateral- field-excited piezoelectric AlN contour- mode MEMS resonators.

PubMed

Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca

2010-01-01

This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contourmode resonators. The oscillator shows a phase noise level of -81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-microm complementary metaloxide- semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt 2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications.

Logic gate scanner focus control in high-volume manufacturing using scatterometry

NASA Astrophysics Data System (ADS)

Dare, Richard J.; Swain, Bryan; Laughery, Michael

2004-05-01

Tool matching and optimal process control are critical requirements for success in semiconductor manufacturing. It is imperative that a tool"s operating conditions are understood and controlled in order to create a process that is repeatable and produces devices within specifications. Likewise, it is important where possible to match multiple systems using some methodology, so that regardless of which tool is used the process remains in control. Agere Systems is currently using Timbre Technologies" Optical Digital Profilometry (ODP) scatterometry for controlling Nikon scanner focus at the most critical lithography layer; logic gate. By adjusting focus settings and verifying the resultant changes in resist profile shape using ODP, it becomes possible to actively control scanner focus to achieve a desired resist profile. Since many critical lithography processes are designed to produce slightly re-entrant resist profiles, this type of focus control is not possible via Critical Dimension Scanning Electron Microscopy (CDSEM) where reentrant profiles cannot be accurately determined. Additionally, the high throughput and non-destructive nature of this measurement technique saves both cycle time and wafer costs compared to cross-section SEM. By implementing an ODP daily process check and after any maintenance on a scanner, Agere successfully enabled focus drift control, i.e. making necessary focus or equipment changes in order to maintain a desired resist profile.

Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

NASA Astrophysics Data System (ADS)

Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

2005-09-01

The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore the capability of the tool for characterizing multiple geometric parameters associated with the manufacturing process that are important to the yield and performance of advanced bottle DRAM devices.

Solar Photovoltaic Array With Mini-Dome Fresnel Lenses

NASA Technical Reports Server (NTRS)

Piszczor, Michael F., Jr.; O'Neill, Mark J.

1994-01-01

Mini-dome Fresnel lenses concentrate sunlight onto individual photovoltaic cells. Facets of Fresnel lens designed to refract incident light at angle of minimum deviation to minimize reflective losses. Prismatic cover on surface of each cell reduces losses by redirecting incident light away from metal contacts toward bulk of semiconductor, where it is usefully absorbed. Simple design of mini-dome concentrator array easily adaptable to automated manufacturing techniques currently used by semiconductor industry. Attractive option for variety of future space missions.

Analysis of field usage failure rate data for plastic encapsulated solid state devices

NASA Technical Reports Server (NTRS)

1981-01-01

Survey and questionnaire techniques were used to gather data from users and manufacturers on the failure rates in the field of plastic encapsulated semiconductors. It was found that such solid state devices are being successfully used by commercial companies which impose certain screening and qualification procedures. The reliability of these semiconductors is now adequate to support their consideration in NASA systems, particularly in low cost systems. The cost of performing necessary screening for NASA applications was assessed.

Scalable Directed Assembly of Highly Crystalline 2,7-Dioctyl[1]benzothieno[3,2- b][1]benzothiophene (C8-BTBT) Films.

PubMed

Chai, Zhimin; Abbasi, Salman A; Busnaina, Ahmed A

2018-05-30

Assembly of organic semiconductors with ordered crystal structure has been actively pursued for electronics applications such as organic field-effect transistors (OFETs). Among various film deposition methods, solution-based film growth from small molecule semiconductors is preferable because of its low material and energy consumption, low cost, and scalability. Here, we show scalable and controllable directed assembly of highly crystalline 2,7-dioctyl[1]benzothieno[3,2- b][1]benzothiophene (C8-BTBT) films via a dip-coating process. Self-aligned stripe patterns with tunable thickness and morphology over a centimeter scale are obtained by adjusting two governing parameters: the pulling speed of a substrate and the solution concentration. OFETs are fabricated using the C8-BTBT films assembled at various conditions. A field-effect hole mobility up to 3.99 cm 2 V -1 s -1 is obtained. Owing to the highly scalable crystalline film formation, the dip-coating directed assembly process could be a great candidate for manufacturing next-generation electronics. Meanwhile, the film formation mechanism discussed in this paper could provide a general guideline to prepare other organic semiconducting films from small molecule solutions.

Mask replication using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Selinidis, Kosta S.; Jones, Chris; Doyle, Gary F.; Brown, Laura; Imhof, Joseph; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2011-11-01

The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 104 - 105imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and the semiconductor mask replication process. A PerfectaTM MR5000 mask replication tool has been developed specifically to pattern replica masks from an ebeam written master. Performance results, including image placement, critical dimension uniformity, and pattern transfer are covered in detail.

Finding the right way: DFM versus area efficiency for 65 nm gate layer lithography

NASA Astrophysics Data System (ADS)

Sarma, Chandra S.; Scheer, Steven; Herold, Klaus; Fonseca, Carlos; Thomas, Alan; Schroeder, Uwe P.

2006-03-01

DFM (Design for Manufacturing) has become a buzzword for lithography since the 90nm node. Implementing DFM intelligently can boost yield rates and reliability in semiconductor manufacturing significantly. However, any restriction on the design space will always result in an area loss, thus diminishing the effective shrink factor for a given technology. For a lithographer, the key task is to develop a manufacturable process, while not sacrificing too much area. We have developed a high performing lithography process for attenuated gate level lithography that is based on aggressive illumination and a newly optimized SRAF placement schemes. In this paper we present our methodology and results for this optimization, using an anchored simulation model. The wafer results largely confirm the predictions of the simulations. The use of aggressive SRAF (Sub Resolution Assist Features) strategy leads to reduction of forbidden pitch regions without any SRAF printing. The data show that our OPC is capable of correcting the PC tip to tip distance without bridging between the tips in dense SRAM cells. SRAF strategy for various 2D cases has also been verified on wafer. We have shown that aggressive illumination schemes yielding a high performing lithography process can be employed without sacrificing area. By carefully choosing processing conditions, we were able develop a process that has very little restrictions for design. In our approach, the remaining issues can be addressed by DFM, partly in data prep procedures, which are largely area neutral and transparent to the designers. Hence, we have shown successfully, that DFM and effective technology shrinks are not mutually exclusive.

Integration of mask and silicon metrology in DFM

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Sugiyama, Akiyuki; Toyoda, Yasutaka

2009-03-01

We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based on the profiling method of the field proven CD metrology algorithm. The detected edges are then converted to GDSII format, which is a standard format for a design data, and utilized for various DFM systems such as simulation. Namely, by integrating pattern shapes of mask and silicon formed during a manufacturing process into GDSII format, it makes it possible to bridge highly accurate pattern profile information over to the design field of various EDA systems. These are fully integrated into design data and automated. Bi-directional cross probing between mask data and process control data is allowed by linking them. This method is a solution for total optimization that covers Design, MDP, mask production and silicon device producing. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Exploration of Gas Discharges with GaAs, GaP and ZnSe Electrodes Under Atmospheric Pressure

NASA Astrophysics Data System (ADS)

Kurt, H. Hilal

2018-03-01

This work reports on the electrical and optical characterization of the atmospheric pressure glow discharge regimes for different semiconductor electrodes made of GaAs, GaP and ZnSe. The discharge cell is driven by DC feeding voltages at a wide pressure range of 0.66-120 kPa in argon and air media for different interelectrode gaps. The discharge phenomena including different stages of discharges such as glow and Townsend breakdown have been examined. In addition, the infrared sensitivities of the semiconducting materials are evaluated in the micro-discharge cell and discharge light emission measurements have been performed. The qualities of the semiconducting electrode samples can be determined by seeking the homogeneity of the discharge light emission for the optoelectronic device applications. Operation of optical devices under atmospheric pressures gives certain advantages for manufacturing of the devices including the material processing and surface treatment procedures. Besides, finite element analyses of the overall experimental system have been performed for the abovementioned semiconductors. The electron densities and potential patterns have been determined on the discharge cell plane between the electrodes. The findings have proven that the electron densities along the plasma cell depend on both the semiconductor type and plasma parameters.

An ultra-low-voltage electronic implementation of inertial neuron model with nonmonotonous Liao's activation function.

PubMed

Kant, Nasir Ali; Dar, Mohamad Rafiq; Khanday, Farooq Ahmad

2015-01-01

The output of every neuron in neural network is specified by the employed activation function (AF) and therefore forms the heart of neural networks. As far as the design of artificial neural networks (ANNs) is concerned, hardware approach is preferred over software one because it promises the full utilization of the application potential of ANNs. Therefore, besides some arithmetic blocks, designing AF in hardware is the most important for designing ANN. While attempting to design the AF in hardware, the designs should be compatible with the modern Very Large Scale Integration (VLSI) design techniques. In this regard, the implemented designs should: only be in Metal Oxide Semiconductor (MOS) technology in order to be compatible with the digital designs, provide electronic tunability feature, and be able to operate at ultra-low voltage. Companding is one of the promising circuit design techniques for achieving these goals. In this paper, 0.5 V design of Liao's AF using sinh-domain technique is introduced. Furthermore, the function is tested by implementing inertial neuron model. The performance of the AF and inertial neuron model have been evaluated through simulation results, using the PSPICE software with the MOS transistor models provided by the 0.18-μm Taiwan Semiconductor Manufacturer Complementary Metal Oxide Semiconductor (TSM CMOS) process.

Quantitative Acoustic Model for Adhesion Evaluation of Pmma/silicon Film Structures

NASA Astrophysics Data System (ADS)

Ju, H. S.; Tittmann, B. R.

2010-02-01

A Poly-methyl-methacrylate (PMMA) film on a silicon substrate is a main structure for photolithography in semiconductor manufacturing processes. This paper presents a potential of scanning acoustic microscopy (SAM) for nondestructive evaluation of the PMMA/Si film structure, whose adhesion failure is commonly encountered during the fabrication and post-fabrication processes. A physical model employing a partial discontinuity in displacement is developed for rigorously quantitative evaluation of the interfacial weakness. The model is implanted to the matrix method for the surface acoustic wave (SAW) propagation in anisotropic media. Our results show that variations in the SAW velocity and reflectance are predicted to show their sensitivity to the adhesion condition. Experimental results by the v(z) technique and SAW velocity reconstruction verify the prediction.

Dry soldering with hot filament produced atomic hydrogen

DOEpatents

Panitz, Janda K. G.; Jellison, James L.; Staley, David J.

1995-01-01

A system for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs.

Process for forming shaped group III-V semiconductor nanocrystals, and product formed using process

DOEpatents

Alivisatos, A. Paul; Peng, Xiaogang; Manna, Liberato

2001-01-01

A process for the formation of shaped Group III-V semiconductor nanocrystals comprises contacting the semiconductor nanocrystal precursors with a liquid media comprising a binary mixture of phosphorus-containing organic surfactants capable of promoting the growth of either spherical semiconductor nanocrystals or rod-like semiconductor nanocrystals, whereby the shape of the semiconductor nanocrystals formed in said binary mixture of surfactants is controlled by adjusting the ratio of the surfactants in the binary mixture.

Process for forming shaped group II-VI semiconductor nanocrystals, and product formed using process

DOEpatents

Alivisatos, A. Paul; Peng, Xiaogang; Manna, Liberato

2001-01-01

A process for the formation of shaped Group II-VI semiconductor nanocrystals comprises contacting the semiconductor nanocrystal precursors with a liquid media comprising a binary mixture of phosphorus-containing organic surfactants capable of promoting the growth of either spherical semiconductor nanocrystals or rod-like semiconductor nanocrystals, whereby the shape of the semiconductor nanocrystals formed in said binary mixture of surfactants is controlled by adjusting the ratio of the surfactants in the binary mixture.

Applications of picosecond lasers and pulse-bursts in precision manufacturing

NASA Astrophysics Data System (ADS)

Knappe, Ralf

2012-03-01

Just as CW and quasi-CW lasers have revolutionized the materials processing world, picosecond lasers are poised to change the world of micromachining, where lasers outperform mechanical tools due to their flexibility, reliability, reproducibility, ease of programming, and lack of mechanical force or contamination to the part. Picosecond lasers are established as powerful tools for micromachining. Industrial processes like micro drilling, surface structuring and thin film ablation benefit from a process, which provides highest precision and minimal thermal impact for all materials. Applications such as microelectronics, semiconductor, and photovoltaic industries use picosecond lasers for maximum quality, flexibility, and cost efficiency. The range of parts, manufactured with ps lasers spans from microscopic diamond tools over large printing cylinders with square feet of structured surface. Cutting glass for display and PV is a large application, as well. With a smart distribution of energy into groups of ps-pulses at ns-scale separation (known as burst mode) ablation rates can be increased by one order of magnitude or more for some materials, also providing a better surface quality under certain conditions. The paper reports on the latest results of the laser technology, scaling of ablation rates, and various applications in ps-laser micromachining.

Scaling Properties of Algorithms in Nanotechnology

NASA Technical Reports Server (NTRS)

Saini, Subhash; Bailey, David H.; Chancellor, Marisa K. (Technical Monitor)

1996-01-01

At the present time, several technologies are pressing the limits of microminiature manufacturing. In semiconductor technology, for example, the Intel Pentium Pro (which is used in the Department of Energy's ASCI 'red' parallel supercomputer system) and the DEC Alpha 21164 (which is used in the CRAY T3E) both are fabricated using 0.35 micron process technology. Recently Texas Instruments (TI) announced the availability of 0.25 micron technology chips by the end of 1996 and plans to have 0.18 micron devices in production within two years. However, some significant challenges lie down the road. These include the skyrocketing cost of manufacturing plants, the 0.1 micron foreseeable limit of the photolithography process, quantum effects, data communication bandwidth limitations, heat dissipation, and others. Some related microminiature technologies include micro-electromechanical systems (MEMS), opto-electronic devices, quantum computing, biological computing, and others. All of these technologies require the fabrication of devices whose sizes are approaching the nanometer level. As such they are often collectively referred to with the name 'nanotechnology'. Clearly nanotechnology in this general sense is destined to be a very important technology of the 21st century. The ultimate dream in this arena is 'molecular nanotechnology', in other words the fabrication of devices and materials with most or all atoms and molecules in a pre-programmed position, possibly placed there by 'nano-robots'. This futuristic capability will probably not be achieved for at least two decades. However, it appears that somewhat less ambitious variations of molecular nanotechnology, such as devices and materials based on 'buckyballs' and 'nanotubes' may be realized significantly sooner, possibly within ten years or so. Even at the present time, semiconductor devices are approaching the regime where quantum chemical effects must be considered in design.

CMOS compatible IR sensors by cytochrome c protein

NASA Astrophysics Data System (ADS)

Liao, Chien-Jen; Su, Guo-Dung

2013-09-01

In recent years, due to the progression of the semiconductor industrial, the uncooled Infrared sensor - microbolometer has opened the opportunity for achieving low cost infrared imaging systems for both military and commercial applications. Therefore, various fabrication processes and different materials based microbolometer have been developed sequentially. The cytochrome c (protein) thin film has be reported high temperature coefficient of resistance (TCR), which is related to the performance of microbolometer directly. Hence the superior TCR value will increase the performance of microbolometer. In this paper, we introduced a novel fabrication process using aluminum which is compatible with the Taiwan Semiconductor Manufacture Company (TSMC) D35 2P4M process as the main structure material, which benefits the device to integrate with readout integrated circuit (ROIC).The aluminum split structure is suspended by sacrificial layer utilizing the standard photolithography technology and chemical etching. The height and thickness of the structure are already considered. Besides, cytochrome c solutions were ink-jetted onto the aluminum structure by using the inkjet printer, applying precise control of the Infrared absorbing layer. In measurement, incident Infrared radiation can be detected and later the heat can be transmitted to adjacent pads to readout the signal. This approach applies an inexpensive and simple fabrication process and makes the device suitable for integration. In addition, the performance can be further improved with low noise readout circuits.

Advanced excimer laser technologies enable green semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Fukuda, Hitomi; Yoo, Youngsun; Minegishi, Yuji; Hisanaga, Naoto; Enami, Tatsuo

2014-03-01

"Green" has fast become an important and pervasive topic throughout many industries worldwide. Many companies, especially in the manufacturing industries, have taken steps to integrate green initiatives into their high-level corporate strategies. Governments have also been active in implementing various initiatives designed to increase corporate responsibility and accountability towards environmental issues. In the semiconductor manufacturing industry, there are growing concerns over future environmental impact as enormous fabs expand and new generation of equipments become larger and more powerful. To address these concerns, Gigaphoton has implemented various green initiatives for many years under the EcoPhoton™ program. The objective of this program is to drive innovations in technology and services that enable manufacturers to significantly reduce both the financial and environmental "green cost" of laser operations in high-volume manufacturing environment (HVM) - primarily focusing on electricity, gas and heat management costs. One example of such innovation is Gigaphoton's Injection-Lock system, which reduces electricity and gas utilization costs of the laser by up to 50%. Furthermore, to support the industry's transition from 300mm to the next generation 450mm wafers, technologies are being developed to create lasers that offer double the output power from 60W to 120W, but reducing electricity and gas consumption by another 50%. This means that the efficiency of lasers can be improve by up to 4 times in 450mm wafer production environments. Other future innovations include the introduction of totally Heliumfree Excimer lasers that utilize Nitrogen gas as its replacement for optical module purging. This paper discusses these and other innovations by Gigaphoton to enable green manufacturing.

Porous Diblock Copolymer Thin Films in High-Performance Semiconductor Microelectronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, C.T.

2011-02-01

The engine fueling more than 40 years of performance improvements in semiconductor integrated circuits (ICs) has been industry's ability to pattern circuit elements at ever-higher resolution and with ever-greater precision. Steady advances in photolithography - the process wherein ultraviolet light chemically changes a photosensitive polymer resist material in order to create a latent image - have resulted in scaling of minimum printed feature sizes from tens of microns during the 1980s to sub-50 nanometer transistor gate lengths in today's state-of-the-art ICs. The history of semiconductor technology scaling as well as future technology requirements is documented in the International Technology Roadmapmore » for Semiconductors (ITRS). The progression of the semiconductor industry to the realm of nanometer-scale sizes has brought enormous challenges to device and circuit fabrication, rendering performance improvements by conventional scaling alone increasingly difficult. Most often this discussion is couched in terms of field effect transistor (FET) feature sizes such as the gate length or gate oxide thickness, however these challenges extend to many other aspects of the IC, including interconnect dimensions and pitch, device packing density, power consumption, and heat dissipation. The ITRS Technology Roadmap forecasts a difficult set of scientific and engineering challenges with no presently-known solutions. The primary focus of this chapter is the research performed at IBM on diblock copolymer films composed of polystyrene (PS) and poly(methyl-methacrylate) (PMMA) (PS-b-PMMA) with total molecular weights M{sub n} in the range of {approx}60K (g/mol) and polydispersities (PD) of {approx}1.1. These materials self assemble to form patterns having feature sizes in the range of 15-20nm. PS-b-PMMA was selected as a self-assembling patterning material due to its compatibility with the semiconductor microelectronics manufacturing infrastructure, as well as the significant body of existing research on understanding its material properties.« less

Consideration of correlativity between litho and etching shape

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Shinoda, Shinichi; Toyoda, Yasutaka

2012-03-01

We developed an effective method for evaluating the correlation of shape of Litho and Etching pattern. The purpose of this method, makes the relations of the shape after that is the etching pattern an index in wafer same as a pattern shape on wafer made by a lithography process. Therefore, this method measures the characteristic of the shape of the wafer pattern by the lithography process and can predict the hotspot pattern shape by the etching process. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used wafer CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and lithography management, and this has a big impact on the semiconductor market that centers on the semiconductor business. 2-dimensional shape of wafer quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. In this study, we conducted experiments for correlation method of the pattern (Measurement Based Contouring) as two-dimensional litho and etch evaluation technique. That is, observation of the identical position of a litho and etch was considered. It is possible to analyze variability of the edge of the same position with high precision.

40 CFR 63.7191 - What records must I keep?

Code of Federal Regulations, 2011 CFR

2011-07-01

... Section 63.7191 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL EMISSION STANDARDS FOR HAZARDOUS AIR POLLUTANTS FOR SOURCE CATEGORIES (CONTINUED) National Emission Standards for Hazardous Air Pollutants for Semiconductor Manufacturing Applications...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2010 CFR

2010-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer... where wastewater undergoes treatment (such as pH adjustment) before discharge, and are not used to...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2011 CFR

2011-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer... where wastewater undergoes treatment (such as pH adjustment) before discharge, and are not used to...

FIBER AND INTEGRATED OPTICS: Photodetector waveguide structures made of epitaxial InGaAs films and intended for integrated circuits manufactured from III-V semiconductor compounds

NASA Astrophysics Data System (ADS)

Shmal'ko, A. V.; Lamekin, V. F.; Smirnov, V. L.; Polyantsev, A. S.; Kogan, Yu I.; Babushkina, T. S.; Kuntsevich, T. S.; Peshkovskaya, O. G.

1990-08-01

Photodetector waveguide structures made of epitaxial InxGa1 - xAs solid-solution films were developed and investigated. These structures were intended for optical integrated circuits manufactured from III-V semiconductor compounds for operation in the wavelength range 1.0-1.5 μm. Two types of photodetector waveguide p-i-n structures were developed. They consisted of a composite waveguide and tunnel-coupled waveguides, respectively. A study was made of structural parameters, responsivity, spectral and time characteristics, and dark currents in photodetectors made of the waveguide structures. This investigation was carried out in the wavelength range 1.0-1.3 μm. The maximum spectral responsivity of one of the types of the waveguide photodetector was ~ 0.5 ± 0.1 A/W and the dark current did not exceed 10 - 7-10 - 8 A.

Micro-fabricated integrated coil and magnetic circuit and method of manufacturing thereof

DOEpatents

Mihailovich, Robert E.; Papavasiliou, Alex P.; Mehrotra, Vivek; Stupar, Philip A.; Borwick, III, Robert L.; Ganguli, Rahul; DeNatale, Jeffrey F.

2017-03-28

A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material.

Modeling and analysis of equipment managers in manufacturing execution systems for semiconductor packaging.

PubMed

Cheng, F T; Yang, H C; Luo, T L; Feng, C; Jeng, M

2000-01-01

Equipment Managers (EMs) play a major role in a Manufacturing Execution System (MES). They serve as the communication bridge between the components of an MES and the equipment. The purpose of this paper is to propose a novel methodology for developing analytical and simulation models for the EM such that the validity and performance of the EM can be evaluated. Domain knowledge and requirements are collected from a real semiconductor packaging factory. By using IDEFO and state diagrams, a static functional model and a dynamic state model of the EM are built. Next, these two models are translated into a Petri net model. This allows qualitative and quantitative analyses of the system. The EM net model is then expanded into the MES net model. Therefore, the performance of an EM in the MES environment can be evaluated. These evaluation results are good references for design and decision making.

Expert system and process optimization techniques for real-time monitoring and control of plasma processes

NASA Astrophysics Data System (ADS)

Cheng, Jie; Qian, Zhaogang; Irani, Keki B.; Etemad, Hossein; Elta, Michael E.

1991-03-01

To meet the ever-increasing demand of the rapidly-growing semiconductor manufacturing industry it is critical to have a comprehensive methodology integrating techniques for process optimization real-time monitoring and adaptive process control. To this end we have accomplished an integrated knowledge-based approach combining latest expert system technology machine learning method and traditional statistical process control (SPC) techniques. This knowledge-based approach is advantageous in that it makes it possible for the task of process optimization and adaptive control to be performed consistently and predictably. Furthermore this approach can be used to construct high-level and qualitative description of processes and thus make the process behavior easy to monitor predict and control. Two software packages RIST (Rule Induction and Statistical Testing) and KARSM (Knowledge Acquisition from Response Surface Methodology) have been developed and incorporated with two commercially available packages G2 (real-time expert system) and ULTRAMAX (a tool for sequential process optimization).

BNLs Synchrotron-radiation Research Hub for Characterizing Detection Materials and Devices for the NA-22 Community

DOE Office of Scientific and Technical Information (OSTI.GOV)

Camarda, G. S.; Bolotnikov, A. E.; Cui, Y.

The goal of this project is to obtain and characterize scintillators, emerging- and commercial-compoundsemiconductor radiation- detection materials and devices provided by vendors and research organizations. The focus of our proposed research is to clarify the role of the deleterious defects and impurities responsible for the detectors' non-uniformity in scintillating crystals, commercial semiconductor radiation-detector materials, and in emerging R&D ones. Some benefits of this project addresses the need for fabricating high-performance scintillators and compound-semiconductor radiation-detectors with the proven potential for large-scale manufacturing. The findings help researchers to resolve the problems of non-uniformities in scintillating crystals, commercial semiconductor radiation-detector materials, and inmore » emerging R&D ones.« less

Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

NASA Astrophysics Data System (ADS)

Bischoff, Paul

The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

Simulation of SiO2 etching in an inductively coupled CF4 plasma

NASA Astrophysics Data System (ADS)

Xu, Qing; Li, Yu-Xing; Li, Xiao-Ning; Wang, Jia-Bin; Yang, Fan; Yang, Yi; Ren, Tian-Ling

2017-02-01

Plasma etching technology is an indispensable processing method in the manufacturing process of semiconductor devices. Because of the high fluorine/carbon ratio of CF4, the CF4 gas is often used for etching SiO2. A commercial software ESI-CFD is used to simulate the process of plasma etching with an inductively coupled plasma model. For the simulation part, CFD-ACE is used to simulate the chamber, and CFD-TOPO is used to simulate the surface of the sample. The effects of chamber pressure, bias voltage and ICP power on the reactant particles were investigated, and the etching profiles of SiO2 were obtained. Simulation can be used to predict the effects of reaction conditions on the density, energy and angular distributions of reactant particles, which can play a good role in guiding the etching process.

Metal oxide semiconductor thin-film transistors for flexible electronics

NASA Astrophysics Data System (ADS)

Petti, Luisa; Münzenrieder, Niko; Vogt, Christian; Faber, Hendrik; Büthe, Lars; Cantarella, Giuseppe; Bottacchi, Francesca; Anthopoulos, Thomas D.; Tröster, Gerhard

2016-06-01

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This review reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.

Metal oxide semiconductor thin-film transistors for flexible electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petti, Luisa; Vogt, Christian; Büthe, Lars

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This reviewmore » reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.« less

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Amine control for DUV lithography: identifying hidden sources

NASA Astrophysics Data System (ADS)

Kishkovich, Oleg P.; Larson, Carl E.

2000-06-01

The impact of airborne basic molecular contamination (MB) on the performance of chemically amplified (CA) resist systems has been a long standing problem. Low ppb levels of MB may be sufficient for robust 0.25 micrometer lithography with today's advanced CA resist systems combined with adequate chemical air filtration. However, with minimum CD targets heading below 150 nm, the introduction of new resist chemistries for Next Generation Lithography, and the trend towards thinner resists, the impact of MB at low and sub-ppb levels again becomes a critical manufacturing issue. Maximizing process control at aggressive feature sizes requires that the level of MB be maintained below a certain limit, which depends on such parameters as the sensitivity of the CA resist, the type of production tools, product mix, and process characteristics. Three approaches have been identified to reduce the susceptibility of CA resists to MB: effective chemical air filtration, modifications to resist chemistry/processing and cleanroom protocols involving MB monitoring and removal of MB sources from the fab. The final MB concentration depends on the effectiveness of filtration resources and on the total pollution originating from different sources in and out of the cleanroom. There are many well-documented sources of MB. Among these are: ambient air; polluted exhaust from other manufacturing areas re-entering the cleanroom through make-up air handlers; manufacturing process chemicals containing volatile molecular bases; certain cleanroom construction materials, such as paint and ceiling tiles; and volatile, humidifier system boiler additives (corrosion inhibitors), such as morpholine, cyclohexylamine, and dimethylaminoethanol. However, there is also an indeterminate number of other 'hidden' pollution sources, which are neither obvious nor well-documented. None of these sources are new, but they had little impact on earlier semiconductor manufacturing processes because the contamination levels are low enough that they were tolerable. The purpose of this article is to investigate some of these frequently overlooked sources of basic molecular contamination and to thereby increase the reader's awareness of their potential risks.

76 FR 81912 - Notice of Petitions by Firms for Determination of Eligibility To Apply for Trade Adjustment...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-12-29

... parts and components such as plugs, clips, rings, handles and small doors. Applied Engineering, Inc... Dyess Ave. Rapid 12/1/2011 The firm manufactures City, SD 57701. semiconductor devices, nanotechnology...

Job Prospects for E/E Engineers.

ERIC Educational Resources Information Center

Basta, Nicholas

1986-01-01

Reviews job prospects for electrical/electronic E/E engineers, indicating that 1985 was not a banner year due to problems in the semiconductor manufacturing industries and in telecommunications. Also indicates that an upturn is expected for 1986 E/E graduates. (JN)

Diode step stress testing program for JANTX1N5550

NASA Technical Reports Server (NTRS)

1979-01-01

The effect was studied of power/temperature step stress when applied to the switching diode JANTX1N5550 manufactured by Semtech and Micro Semiconductor. The power/temperature stress tests are presented, and failure analyses are included.

Employment Lessons from the Electronics Industry.

ERIC Educational Resources Information Center

Alic, John A.; Harris, Martha Caldwell

1986-01-01

Semiskilled and "unskilled" workers in semiconductors, computer manufacturing, and consumer electronics industries are more likely than other workers to lose jobs because of technology, imports, and offshore production. However, advances in technology do tend to create jobs for skilled workers. (CT)

Hazardous Waste Cleanup: General Electric - Auburn Plant in Auburn, New York

EPA Pesticide Factsheets

GE purchased the property at Genesee Street in 1951 and constructed a manufacturing plant that produced a variety of electrical components including radar equipment, printed circuit boards and high voltage semiconductors. In January 1986, Powerex, Inc.,

Diagnostic for Plasma Enhanced Chemical Vapor Deposition and Etch Systems

NASA Technical Reports Server (NTRS)

Cappelli, Mark A.

1999-01-01

In order to meet NASA's requirements for the rapid development and validation of future generation electronic devices as well as associated materials and processes, enabling technologies ion the processing of semiconductor materials arising from understanding etch chemistries are being developed through a research collaboration between Stanford University and NASA-Ames Research Center, Although a great deal of laboratory-scale research has been performed on many of materials processing plasmas, little is known about the gas-phase and surface chemical reactions that are critical in many etch and deposition processes, and how these reactions are influenced by the variation in operating conditions. In addition, many plasma-based processes suffer from stability and reliability problems leading to a compromise in performance and a potentially increased cost for the semiconductor manufacturing industry. Such a lack of understanding has hindered the development of process models that can aid in the scaling and improvement of plasma etch and deposition systems. The research described involves the study of plasmas used in semiconductor processes. An inductively coupled plasma (ICP) source in place of the standard upper electrode assembly of the Gaseous Electronics Conference (GEC) radio-frequency (RF) Reference Cell is used to investigate the discharge characteristics and chemistries. This ICP source generates plasmas with higher electron densities (approximately 10(exp 12)/cu cm) and lower operating pressures (approximately 7 mTorr) than obtainable with the original parallel-plate version of the GEC Cell. This expanded operating regime is more relevant to new generations of industrial plasma systems being used by the microelectronics industry. The motivation for this study is to develop an understanding of the physical phenomena involved in plasma processing and to measure much needed fundamental parameters, such as gas-phase and surface reaction rates. species concentration, temperature, ion energy distribution, and electron number density. A wide variety of diagnostic techniques are under development through this consortium grant to measure these parameters. including molecular beam mass spectrometry (MBMS). Fourier transform infrared (FTIR) spectroscopy, broadband ultraviolet (UV) absorption spectroscopy, a compensated Langmuir probe. Additional diagnostics. Such as microwave interferometry and microwave absorption for measurements of plasma density and radical concentrations are also planned.

Tuning the Performance of Organic Spintronic Devices Using X-Ray Generated Traps

DTIC Science & Technology

2012-08-16

observed in organic devices using the same organic semiconductor, namely tris(8-hydroxyquinoli- nato)aluminium ( Alq3 ) [5,15]. Here we will show that the...manufacturing steps were carried out in a deposition chamber located inside a nitrogen glovebox. Next, the organic layer Alq3 (70 to 100 nm) followed by the...As the organic semiconductor spacer layer, the Alq3 layer was fabricated by thermal evaporation in a vacuum of 10Ś mbar at a rate of 0:1 nm=s. The Fe

Maintaining Moore's law: enabling cost-friendly dimensional scaling

NASA Astrophysics Data System (ADS)

Mallik, Arindam; Ryckaert, Julien; Mercha, Abdelkarim; Verkest, Diederik; Ronse, Kurt; Thean, Aaron

2015-03-01

Moore's Law (Moore's Observation) has been driving the progress in semiconductor technology for the past 50 years. The semiconductor industry is at a juncture where significant increase in manufacturing cost is foreseen to sustain the past trend of dimensional scaling. At N10 and N7 technology nodes, the industry is struggling to find a cost-friendly solution. At a device level, technologists have come up with novel devices (finFET, Gate-All-Around), material innovations (SiGe, Ge) to boost performance and reduce power consumption. On the other hand, from the patterning side, the relative slow ramp-up of alternative lithography technologies like EUVL and DSA pushes the industry to adopt a severely multi-patterning-based solution. Both of these technological transformations have a big impact on die yield and eventually die cost. This paper is aimed to analyze the impact on manufacturing cost to keep the Moore's law alive. We have proposed and analyzed various patterning schemes that can enable cost-friendly scaling. We evaluated the impact of EUVL introduction on tackling the high cost of manufacturing. The primary objective of this paper is to maintain Moore's scaling from a patterning perspective and analyzing EUV lithography introduction at a die level.

The Preemptive Stocker Dispatching Rule of Automatic Material Handling System in 300 mm Semiconductor Manufacturing Factories

NASA Astrophysics Data System (ADS)

Wang, C. N.; Lin, H. S.; Hsu, H. P.; Wang, Yen-Hui; Chang, Y. P.

2016-04-01

The integrated circuit (IC) manufacturing industry is one of the biggest output industries in this century. The 300mm wafer fabs is the major fab size of this industry. The automatic material handling system (AMHS) has become one of the most concerned issues among semiconductor manufacturers. The major lot delivery of 300mm fabs is used overhead hoist transport (OHT). The traffic jams are happened frequently due to the wide variety of products and big amount of OHTs moving in the fabs. The purpose of this study is to enhance the delivery performance of automatic material handling and reduce the delay and waiting time of product transportation for both hot lots and normal lots. Therefore, this study proposes an effective OHT dispatching rule: preemptive stocker dispatching (PSD). Simulation experiments are conducted and one of the best differentiated preemptive rule, differentiated preemptive dispatching (DPD), is used for comparison. Compared with DPD, The results indicated that PSD rule can reduce average variable delivery time of normal lots by 13.15%, decreasing average variable delivery time of hot lots by 17.67%. Thus, the PSD rule can effectively reduce the delivery time and enhance productivity in 300 mm wafer fabs.

Dry soldering with hot filament produced atomic hydrogen

DOEpatents

Panitz, J.K.G.; Jellison, J.L.; Staley, D.J.

1995-04-25

A system is disclosed for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs. 1 fig.

Effects of fluorine contamination on spin-on dielectric thickness in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Kim, Hyoung-ryeun; Hong, Soonsang; Kim, Samyoung; Oh, Changyeol; Hwang, Sung Min

2018-03-01

In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.

Method for depositing high-quality microcrystalline semiconductor materials

DOEpatents

Guha, Subhendu [Bloomfield Hills, MI; Yang, Chi C [Troy, MI; Yan, Baojie [Rochester Hills, MI

2011-03-08

A process for the plasma deposition of a layer of a microcrystalline semiconductor material is carried out by energizing a process gas which includes a precursor of the semiconductor material and a diluent with electromagnetic energy so as to create a plasma therefrom. The plasma deposits a layer of the microcrystalline semiconductor material onto the substrate. The concentration of the diluent in the process gas is varied as a function of the thickness of the layer of microcrystalline semiconductor material which has been deposited. Also disclosed is the use of the process for the preparation of an N-I-P type photovoltaic device.

Reducing measurement uncertainty drives the use of multiple technologies for supporting metrology

NASA Astrophysics Data System (ADS)

Banke, Bill, Jr.; Archie, Charles N.; Sendelbach, Matthew; Robert, Jim; Slinkman, James A.; Kaszuba, Phil; Kontra, Rick; DeVries, Mick; Solecky, Eric P.

2004-05-01

Perhaps never before in semiconductor microlithography has there been such an interest in the accuracy of measurement. This interest places new demands on our in-line metrology systems as well as the supporting metrology for verification. This also puts a burden on the users and suppliers of new measurement tools, which both challenge and complement existing manufacturing metrology. The metrology community needs to respond to these challenges by using new methods to assess the fab metrologies. An important part of this assessment process is the ability to obtain accepted reference measurements as a way of determining the accuracy and Total Measurement Uncertainty (TMU) of an in-line critical dimension (CD). In this paper, CD can mean any critical dimension including, for example, such measures as feature height or sidewall angle. This paper describes the trade-offs of in-line metrology systems as well as the limitations of Reference Measurement Systems (RMS). Many factors influence each application such as feature shape, material properties, proximity, sampling, and critical dimension. These factors, along with the metrology probe size, interaction volume, and probe type such as e-beam, optical beam, and mechanical probe, are considered. As the size of features shrinks below 100nm some of the stalwarts of reference metrology come into question, such as the electrically determined transistor gate length. The concept of the RMS is expanded to show how multiple metrologies are needed to achieve the right balance of accuracy and sampling. This is also demonstrated for manufacturing metrology. Various comparisons of CDSEM, scatterometry, AFM, cross section SEM, electrically determined CDs, and TEM are shown. An example is given which demonstrates the importance in obtaining TMU by balancing accuracy and precision for selecting manufacturing measurement strategy and optimizing manufacturing metrology. It is also demonstrated how the necessary supporting metrology will bring together formerly unlinked technology fields requiring new measurement science. The emphasis on accuracy will increase the importance and role of NIST and similar metrology organizations in supporting the semiconductor industry in this effort.

Accelerating yield ramp through design and manufacturing collaboration

NASA Astrophysics Data System (ADS)

Sarma, Robin C.; Dai, Huixiong; Smayling, Michael C.; Duane, Michael P.

2004-12-01

Ramping an integrated circuit from first silicon bring-up to production yield levels is a challenge for all semiconductor products on the path to profitable market entry. Two approaches to accelerating yield ramp are presented. The first is the use of laser mask writers for fast throughput, high yield, and cost effective pattern transfer. The second is the use of electrical test to find a defect and identify the physical region to probe in failure analysis that is most likely to uncover the root cause. This provides feedback to the design team on modifications to make to the design to avoid the yield issue in a future tape-out revision. Additionally, the process parameter responsible for the root cause of the defect is forward annotated through the design, mask and wafer coordinate systems so it can be monitored in-line on subsequent lots of the manufacturing run. This results in an improved recipe for the manufacturing equipment to potentially prevent the recurrence of the defect and raise yield levels on the following material. The test diagnostics approach is enabled by the seamless traceability of a feature across the design, photomask and wafer, made possible by a common data model for design, mask pattern generation and wafer fabrication.

A portable pattern-based design technology co-optimization flow to reduce optical proximity correction run-time

NASA Astrophysics Data System (ADS)

Chen, Yi-Chieh; Li, Tsung-Han; Lin, Hung-Yu; Chen, Kao-Tun; Wu, Chun-Sheng; Lai, Ya-Chieh; Hurat, Philippe

2018-03-01

Along with process improvement and integrated circuit (IC) design complexity increased, failure rate caused by optical getting higher in the semiconductor manufacture. In order to enhance chip quality, optical proximity correction (OPC) plays an indispensable rule in the manufacture industry. However, OPC, includes model creation, correction, simulation and verification, is a bottleneck from design to manufacture due to the multiple iterations and advanced physical behavior description in math. Thus, this paper presented a pattern-based design technology co-optimization (PB-DTCO) flow in cooperation with OPC to find out patterns which will negatively affect the yield and fixed it automatically in advance to reduce the run-time in OPC operation. PB-DTCO flow can generate plenty of test patterns for model creation and yield gaining, classify candidate patterns systematically and furthermore build up bank includes pairs of match and optimization patterns quickly. Those banks can be used for hotspot fixing, layout optimization and also be referenced for the next technology node. Therefore, the combination of PB-DTCO flow with OPC not only benefits for reducing the time-to-market but also flexible and can be easily adapted to diversity OPC flow.

Charge dissipative dielectric for cryogenic devices

NASA Technical Reports Server (NTRS)

Cantor, Robin Harold (Inventor); Hall, John Addison (Inventor)

2007-01-01

A Superconducting Quantum Interference Device (SQUID) is disclosed comprising a pair of resistively shunted Josephson junctions connected in parallel within a superconducting loop and biased by an external direct current (dc) source. The SQUID comprises a semiconductor substrate and at least one superconducting layer. The metal layer(s) are separated by or covered with a semiconductor material layer having the properties of a conductor at room temperature and the properties of an insulator at operating temperatures (generally less than 100 Kelvins). The properties of the semiconductor material layer greatly reduces the risk of electrostatic discharge that can damage the device during normal handling of the device at room temperature, while still providing the insulating properties desired to allow normal functioning of the device at its operating temperature. A method of manufacturing the SQUID device is also disclosed.

Etch Profile Simulation Using Level Set Methods

NASA Technical Reports Server (NTRS)

Hwang, Helen H.; Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Etching and deposition of materials are critical steps in semiconductor processing for device manufacturing. Both etching and deposition may have isotropic and anisotropic components, due to directional sputtering and redeposition of materials, for example. Previous attempts at modeling profile evolution have used so-called "string theory" to simulate the moving solid-gas interface between the semiconductor and the plasma. One complication of this method is that extensive de-looping schemes are required at the profile corners. We will present a 2D profile evolution simulation using level set theory to model the surface. (1) By embedding the location of the interface in a field variable, the need for de-looping schemes is eliminated and profile corners are more accurately modeled. This level set profile evolution model will calculate both isotropic and anisotropic etch and deposition rates of a substrate in low pressure (10s mTorr) plasmas, considering the incident ion energy angular distribution functions and neutral fluxes. We will present etching profiles of Si substrates in Ar/Cl2 discharges for various incident ion energies and trench geometries.

Past and Present of the Chinese and Korean Trainees and Survival of a Small Manufacturing Industry

NASA Astrophysics Data System (ADS)

Nishihata, Mikio

In 1973, the author established the Nippon Bell Parts Co., Ltd. in Funabashi-city under his estimation of the advances in communication, information, semiconductor and automotive industries, then he has focused on R&D and developed the manufacturing of precise parts. During the past 30 years, he has himself experienced the importance of the mutual exchange between Japan and China and Korea, for keeping the human capability as well as for the management and the technical development to avoid a bankruptcy. The author is intentionally acting for the education of craftsmen in small and medium-sized manufacturing industries.

Solar cell circuit and method for manufacturing solar cells

NASA Technical Reports Server (NTRS)

Mardesich, Nick (Inventor)

2010-01-01

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

New Methods of Sample Preparation for Atom Probe Specimens

NASA Technical Reports Server (NTRS)

Kuhlman, Kimberly, R.; Kowalczyk, Robert S.; Ward, Jennifer R.; Wishard, James L.; Martens, Richard L.; Kelly, Thomas F.

2003-01-01

Magnetite is a common conductive mineral found on Earth and Mars. Disk-shaped precipitates approximately 40 nm in diameter have been shown to have manganese and aluminum concentrations. Atom-probe field-ion microscopy (APFIM) is the only technique that can potentially quantify the composition of these precipitates. APFIM will be used to characterize geological and planetary materials, analyze samples of interest for geomicrobiology; and, for the metrology of nanoscale instrumentation. Prior to APFIM sample preparation was conducted by electropolishing, the method of sharp shards (MSS), or Bosch process (deep reactive ion etching) with focused ion beam (FIB) milling as a final step. However, new methods are required for difficult samples. Many materials are not easily fabricated using electropolishing, MSS, or the Bosch process, FIB milling is slow and expensive, and wet chemistry and the reactive ion etching are typically limited to Si and other semiconductors. APFIM sample preparation using the dicing saw is commonly used to section semiconductor wafers into individual devices following manufacture. The dicing saw is a time-effective method for preparing high aspect ratio posts of poorly conducting materials. Femtosecond laser micromachining is also suitable for preparation of posts. FIB time required is reduced by about a factor of 10 and multi-tip specimens can easily be fabricated using the dicing saw.

The influence of material type and composition of TiO2- ZnO on manufacturing of paste for the application of DSSC

NASA Astrophysics Data System (ADS)

Retnaningsih, L.; Muliani, L.; Aggraini, P. N.; Hidayat, J.

2016-11-01

Research, fabrication and material selection for the application of Dye- sensitized solar cell (DSSC) has been performed on glass FTO (Flour Tin Oxide). The material is used in the form of TiO2 paste, TiO2 powder and ZnO powder. Dye-sensitized solar cell (DSSC), is a fotoelektrokimia-based solar cells where the absorption process light done by the dye molecules and the process of separation of inorganic semiconductor materials by charge of Titanium dioxide (TiO2) and Zinc oxide (ZnO). The purpose of this research is to know the exact composition of TiO2 and ZnO materials in order to produce the best efficiency with DSSC. On this research was done making prototype dye-sensitized solar cell using dye Z 907, and semiconductor nanoparticles TiO2 and ZnO powder that is made into a paste by mixing different composition in two variations of samples: A = ZnO (powder) + 40% TiO2 (powder) and B = 60% TiO2 (powder) (40%) + TiO2 (pasta) 60%. The second variation of this high efficiency is value at sample B i.e. TiO2 (powder) + 40% TiO2 (paste) of 60%.

Improved Method of Manufacturing SiC Devices

NASA Technical Reports Server (NTRS)

Okojie, Robert S.

2005-01-01

The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.

Simulation and experimental verification of silicon dioxide deposition by PECVD

NASA Astrophysics Data System (ADS)

Xu, Qing; Li, Yu-Xing; Li, Xiao-Ning; Wang, Jia-Bin; Yang, Fan; Yang, Yi; Ren, Tian-Ling

2017-02-01

Deposition of silicon dioxide in high-density plasma is an important process in integrated circuit manufacturing. A software named CFD-ACE was used to simulate the mechanism of plasma in the chamber of plasma enhanced chemical vapor deposition (PECVD) system, and the evolution of the feature profile was simulated based on CFD-TOPO. Simulation and experiment of silicon dioxide that deposited in SiH4/N2O mixture by PECVD system was researched. The particle density, energy and angular distribution in the chamber were simulated and discussed. We also studied how the depth/width ratio affected the step coverage of the trench and analyzed the deposition rate of silicon dioxide on the feature scale. X-ray photoelectron spectroscopy (XPS) was used to analyze the elemental composition of thin films. Images of the feature profiles were taken by scanning electron microscope (SEM). The simulation results were in good agreement with experimental, which could guide the semiconductor device manufacture.

Digital terrain modeling and industrial surface metrology: Converging realms

USGS Publications Warehouse

Pike, R.J.

2001-01-01

Digital terrain modeling has a micro-and nanoscale counterpart in surface metrology, the numerical characterization of industrial surfaces. Instrumentation in semiconductor manufacturing and other high-technology fields can now contour surface irregularities down to the atomic scale. Surface metrology has been revolutionized by its ability to manipulate square-grid height matrices that are analogous to the digital elevation models (DEMs) used in physical geography. Because the shaping of industrial surfaces is a spatial process, the same concepts of analytical cartography that represent ground-surface form in geography evolved independently in metrology: The surface topography of manufactured components, exemplified here by automobile-engine cylinders, is routinely modeled by variogram analysis, relief shading, and most other techniques of parameterization and visualization familiar to geography. This article introduces industrial surface-metrology, examines the field in the context of terrain modeling and geomorphology and notes their similarities and differences, and raises theoretical issues to be addressed in progressing toward a unified practice of surface morphometry.

Ambipolar Graphene-Quantum Dot Hybrid Vertical Photodetector with a Graphene Electrode.

PubMed

Che, Yongli; Zhang, Yating; Cao, Xiaolong; Zhang, Haiting; Song, Xiaoxian; Cao, Mingxuan; Yu, Yu; Dai, Haitao; Yang, Junbo; Zhang, Guizhong; Yao, Jianquan

2017-09-20

A strategy to fabricate an ambipolar near-infrared vertical photodetector (VPD) by sandwiching a photoactive material as a channel film between the bottom graphene and top metal electrodes was developed. The channel length in the vertical architecture was determined by the channel layer thickness, which can provide an ultrashort channel length without the need for a high-precision manufacturing process. The performance of VPDs with two types of semiconductor layers, a graphene-PbS quantum dot hybrid (GQDH) and PbS quantum dots (QDs), was measured. The GQDH VPD showed better photoelectric properties than the QD VPD because of the high mobility of graphene doped in the channel. The GQDH VPD exhibited excellent photoresponse properties with a responsivity of 1.6 × 10 4 A/W in the p-type regime and a fast response speed with a rise time of 8 ms. The simple manufacture and the promising photoresponse of the GQDH VPDs reveal that an easy and effective way to fabricate high-performance ambipolar photodetectors was developed.

Crystal growth and materials research in photovoltaics: progress and challenges

NASA Astrophysics Data System (ADS)

Surek, Thomas

2005-02-01

Photovoltaics (PV) is solar electric power—a semiconductor-based technology that converts sunlight to electricity. Three decades of research has led to the discovery of new materials and devices and new processing techniques for low-cost manufacturing. This has resulted in improved sunlight-to-electricity conversion efficiencies, improved outdoor reliability, and lower module and system costs. The manufacture and sale of PV has grown into a $5 billion industry worldwide, with more than 740 megawatts of PV modules shipped in 2003. This paper reviews the significant progress that has occurred in PV materials and devices research over the past 30 years, focusing on the advances in crystal growth and materials research, and examines the challenges to reaching the ultimate potential of current-generation (crystalline silicon), next-generation (thin films and concentrators), and future-generation PV technologies. The latter includes innovative materials and device concepts that hold the promise of significantly higher conversion efficiencies and/or much lower costs.

75 FR 29723 - Foreign-Trade Zone 29-Louisville, KY; Application for Expansion and Expansion of Manufacturing...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-05-27

..., plates, filters, bearings, air pumps/compressors, valves, switches, electric motors, tubes/pipes/profiles... electric motors, pinions, magnets, ignition parts, diodes, transistors, resistors, semiconductors, liquid..., starter motors, motor/generator units, alternators, distributors, other static converters, inverter...

IRIS Toxicological Review of Thallium and Compounds (External Review Draft)

EPA Science Inventory

Thallium compounds are used in the semiconductor industry, the manufacture of optic lenses and low-melting glass, low-temperature thermometers, alloys, electronic devices, mercury lamps, fireworks, and imitation germs, and clinically as an imaging agent in the diagnosis of certai...

40 CFR 63.7189 - What applications and notifications must I submit and when?

Code of Federal Regulations, 2011 CFR

2011-07-01

... AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL EMISSION STANDARDS FOR HAZARDOUS AIR POLLUTANTS FOR SOURCE CATEGORIES (CONTINUED) National Emission Standards for Hazardous Air Pollutants for Semiconductor Manufacturing Applications, Notifications, Reports, and Records § 63.7189 What applications and notifications...

77 FR 24178 - Information Systems Technical Advisory Committee; Notice of Partially Closed Meeting

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-23

... and Introductions 2. Working Group Reports 3. Industry Presentation: E-beam Lithography 4. Industry Presentation: ENC Threshold for Satellite Modem 5. Industry Presentation: Semiconductor Manufacturing Equipment... DEPARTMENT OF COMMERCE Bureau of Industry and Security Information Systems Technical Advisory...

Knowledge Mapping: A Multipurpose Task Analysis Tool.

ERIC Educational Resources Information Center

Esque, Timm J.

1988-01-01

Describes knowledge mapping, a tool developed to increase the objectivity and accuracy of task difficulty ratings for job design. Application in a semiconductor manufacturing environment is discussed, including identifying prerequisite knowledge for a given task; establishing training development priorities; defining knowledge levels; identifying…

Hazardous Waste Cleanup: General Electric – Main Plant Site in Schenectady, New York

EPA Pesticide Factsheets

GE purchased the property at Genesee Street in 1951 and constructed a manufacturing plant that produced a variety of electrical components including radar equipment, printed circuit boards and high voltage semiconductors. In January 1986, Powerex, Inc., ac

Atomic-Scale Engineering of Abrupt Interface for Direct Spin Contact of Ferromagnetic Semiconductor with Silicon

PubMed Central

Averyanov, Dmitry V.; Karateeva, Christina G.; Karateev, Igor A.; Tokmachev, Andrey M.; Vasiliev, Alexander L.; Zolotarev, Sergey I.; Likhachev, Igor A.; Storchak, Vyacheslav G.

2016-01-01

Control and manipulation of the spin of conduction electrons in industrial semiconductors such as silicon are suggested as an operating principle for a new generation of spintronic devices. Coherent injection of spin-polarized carriers into Si is a key to this novel technology. It is contingent on our ability to engineer flawless interfaces of Si with a spin injector to prevent spin-flip scattering. The unique properties of the ferromagnetic semiconductor EuO make it a prospective spin injector into silicon. Recent advances in the epitaxial integration of EuO with Si bring the manufacturing of a direct spin contact within reach. Here we employ transmission electron microscopy to study the interface EuO/Si with atomic-scale resolution. We report techniques for interface control on a submonolayer scale through surface reconstruction. Thus we prevent formation of alien phases and imperfections detrimental to spin injection. This development opens a new avenue for semiconductor spintronics. PMID:26957146

Cancer and reproductive risks in the semiconductor industry.

PubMed

LaDou, Joseph; Bailar, John C

2007-01-01

Although many reproductive toxicants and carcinogens are used in the manufacture of semiconductor chips, and worrisome findings have been reported, no broad epidemiologic study has been conducted to define possible risks in a comprehensive way. With few exceptions, the American semiconductor industry has not supported access for independent studies. Older technologies are exported to newly industrialized countries as newer technologies are installed in Japan, the United States, and Europe. Thus there is particular concern about the many workers, mostly in countries that are still industrializing, who have jobs that use chemicals, technologies, and equipment that are no longer in use in developed countries. Since most countries lack cancer registries and have inadequate reproductive and cancer reporting mechanisms, industry efforts to control exposures to carcinogens are of particular importance. Government agencies, the courts, industry, publishers, and academia, on occasion, collude to ignore or to downplay the importance of occupational diseases. Examples of how this happens in the semiconductor industry are presented.

A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

PubMed

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-03-15

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Perspective: Optical measurement of feature dimensions and shapes by scatterometry

NASA Astrophysics Data System (ADS)

Diebold, Alain C.; Antonelli, Andy; Keller, Nick

2018-05-01

The use of optical scattering to measure feature shape and dimensions, scatterometry, is now routine during semiconductor manufacturing. Scatterometry iteratively improves an optical model structure using simulations that are compared to experimental data from an ellipsometer. These simulations are done using the rigorous coupled wave analysis for solving Maxwell's equations. In this article, we describe the Mueller matrix spectroscopic ellipsometry based scatterometry. Next, the rigorous coupled wave analysis for Maxwell's equations is presented. Following this, several example measurements are described as they apply to specific process steps in the fabrication of gate-all-around (GAA) transistor structures. First, simulations of measurement sensitivity for the inner spacer etch back step of horizontal GAA transistor processing are described. Next, the simulated metrology sensitivity for sacrificial (dummy) amorphous silicon etch back step of vertical GAA transistor processing is discussed. Finally, we present the application of plasmonically active test structures for improving the sensitivity of the measurement of metal linewidths.

Photo-thermal processing of semiconductor fibers and thin films

NASA Astrophysics Data System (ADS)

Gupta, Nishant

Furnace processing and rapid thermal processing (RTP) have been an integral part of several processing steps in semiconductor manufacturing. The performance of RTP techniques can be improved many times by exploiting quantum photo-effects of UV and vacuum ultraviolet (VUV) photons in thermal processing and this technique is known as rapid photo-thermal processing (RPP). As compared to furnace processing and RTP, RPP provides higher diffusion coefficient, lower stress and lower microscopic defects. In this work, a custom designed automated photo assisted processing system was built from individual parts and an incoherent light source. This photo-assisted processing system is used to anneal silica clad silicon fibers and deposit thin-films. To the best of our knowledge, incoherent light source based rapid photo-thermal processing (RPP) was used for the first time to anneal glass-clad silicon core optical fibers. X-ray diffraction examination, Raman spectroscopy and electrical measurements showed a considerable enhancement of structural and crystalline properties of RPP treated silicon fibers. Photons in UV and vacuum ultraviolet (VUV) regions play a very important role in improving the bulk and carrier transport properties of RPP-treated silicon optical fibers, and the resultant annealing permits a path forward to in situ enhancement of the structure and properties of these new crystalline core optical fibers. To explore further applications of RPP, thin-films of Calcium Copper Titanate (CaCu3Ti4O12) or CCTO and Copper (I) Oxide (Cu2O) were also deposited using photo-assisted metal-organic chemical vapor deposition (MOCVD) on Si/SiO2 and n-Si substrate respectively. CCTO is one of the most researched giant dielectric constant materials in recent years. The given photo-assisted MOCVD approach provided polycrystalline CCTO growth on a SiO2 surface with grain sizes as large as 410 nm. Copper (I) oxide (Cu2O) is a direct band gap semiconductor with p-type conductivity and is a potential candidate for multi-junction solar cells. X-ray diffraction study revealed a preferred orientation, as (200) oriented crystals of Cu2O are grown on both substrates. Also, electrical characterization of Cu2O/n-Si devices showed the lowest saturation current density of 1.5x10-12 A/cm 2 at zero bias. As a result, photo-assisted thermal processing has the potential of making the process more effective with enhanced device performance.

Semiconductor structure and recess formation etch technique

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Bin; Sun, Min; Palacios, Tomas Apostol

2017-02-14

A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching processmore » stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.« less

Identifying the hazard characteristics of powder byproducts generated from semiconductor fabrication processes.

PubMed

Choi, Kwang-Min; An, Hee-Chul; Kim, Kwan-Sick

2015-01-01

Semiconductor manufacturing processes generate powder particles as byproducts which potentially could affect workers' health. The chemical composition, size, shape, and crystal structure of these powder particles were investigated by scanning electron microscopy equipped with an energy dispersive spectrometer, Fourier transform infrared spectrometry, and X-ray diffractometry. The powders generated in diffusion and chemical mechanical polishing processes were amorphous silica. The particles in the chemical vapor deposition (CVD) and etch processes were TiO(2) and Al(2)O(3), and Al(2)O(3) particles, respectively. As for metallization, WO(3), TiO(2), and Al(2)O(3) particles were generated from equipment used for tungsten and barrier metal (TiN) operations. In photolithography, the size and shape of the powder particles showed 1-10 μm and were of spherical shape. In addition, the powders generated from high-current and medium-current processes for ion implantation included arsenic (As), whereas the high-energy process did not include As. For all samples collected using a personal air sampler during preventive maintenance of process equipment, the mass concentrations of total airborne particles were < 1 μg, which is the detection limit of the microbalance. In addition, the mean mass concentrations of airborne PM10 (particles less than 10 μm in diameter) using direct-reading aerosol monitor by area sampling were between 0.00 and 0.02 μg/m(3). Although the exposure concentration of airborne particles during preventive maintenance is extremely low, it is necessary to make continuous improvements to the process and work environment, because the influence of chronic low-level exposure cannot be excluded.

Technology Directions for the 21st Century, volume 1

NASA Technical Reports Server (NTRS)

Crimi, Giles F.; Verheggen, Henry; McIntosh, William; Botta, Robert

1996-01-01

For several decades, semiconductor device density and performance have been doubling about every 18 months (Moore's Law). With present photolithography techniques, this rate can continue for only about another 10 years. Continued improvement will need to rely on newer technologies. Transition from the current micron range for transistor size to the nanometer range will permit Moore's Law to operate well beyond 10 years. The technologies that will enable this extension include: single-electron transistors; quantum well devices; spin transistors; and nanotechnology and molecular engineering. Continuation of Moore's Law will rely on huge capital investments for manufacture as well as on new technologies. Much will depend on the fortunes of Intel, the premier chip manufacturer, which, in turn, depend on the development of mass-market applications and volume sales for chips of higher and higher density. The technology drivers are seen by different forecasters to include video/multimedia applications, digital signal processing, and business automation. Moore's Law will affect NASA in the areas of communications and space technology by reducing size and power requirements for data processing and data fusion functions to be performed onboard spacecraft. In addition, NASA will have the opportunity to be a pioneering contributor to nanotechnology research without incurring huge expenses.

Materials and processing approaches for foundry-compatible transient electronics.

PubMed

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A; Song, Enming; Yu, Xinge; Rogers, John A

2017-07-11

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for "green" electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are ( i ) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, ( ii ) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and ( iii ) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Materials and processing approaches for foundry-compatible transient electronics

NASA Astrophysics Data System (ADS)

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-07-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Evaluation of selected chemical processes for production of low-cost silicon

NASA Technical Reports Server (NTRS)

Blocher, J. M., Jr.; Browning, M. F.; Wilson, W. J.; Carmichael, D. C.

1976-01-01

Plant construction costs and manufacturing costs were estimated for the production of solar-grade silicon by the reduction of silicon tetrachloride in a fluidized bed of seed particles, and several modifications of the iodide process using either thermal decomposition on heated filaments (rods) or hydrogen reduction in a fluidized bed of seed particles. Energy consumption data for the zinc reduction process and each of the iodide process options are given and all appear to be acceptable from the standpoint of energy pay back. Information is presented on the experimental zinc reduction of SiCl4 and electrolytic recovery of zinc from ZnCl2. All of the experimental work performed thus far has supported the initial assumption as to technical feasibility of producing semiconductor silicon by the zinc reduction or iodide processes proposed. The results of a more thorough thermodynamic evaluation of the iodination of silicon oxide/carbon mixtures are presented which explain apparent inconsistencies in an earlier cursory examination of the system.

40 CFR 63.7190 - What reports must I submit and when?

Code of Federal Regulations, 2011 CFR

2011-07-01

... PROGRAMS (CONTINUED) NATIONAL EMISSION STANDARDS FOR HAZARDOUS AIR POLLUTANTS FOR SOURCE CATEGORIES (CONTINUED) National Emission Standards for Hazardous Air Pollutants for Semiconductor Manufacturing... 40 Protection of Environment 13 2011-07-01 2011-07-01 false What reports must I submit and when...

Methods for the additive manufacturing of semiconductor and crystal materials

DOEpatents

Stowe, Ashley C.; Speight, Douglas

2016-11-22

A method for the additive manufacturing of inorganic crystalline materials, including: physically combining a plurality of starting materials that are used to form an inorganic crystalline compound to be used as one or more of a semiconductor, scintillator, laser crystal, and optical filter; heating or melting successive regions of the combined starting materials using a directed heat source having a predetermined energy characteristic, thereby facilitating the reaction of the combined starting materials; and allowing each region of the combined starting materials to cool in a controlled manner, such that the desired inorganic crystalline compound results. The method also includes, prior to heating or melting the successive regions of the combined starting materials using the directed heat source, heating the combined starting materials to facilitate initial reaction of the combined starting materials. The method further includes translating the combined starting materials and/or the directed heat source between successive locations. The method still further includes controlling the mechanical, electrical, photonic, and/or optical properties of the inorganic crystalline compound.

Adsorption of Heavy Metals in Industrial Wastewater by Magnetic Nano-particles

NASA Astrophysics Data System (ADS)

Tu, Y.; You, C.

2010-12-01

Industrial wastewater containing heavy metals is of great concern because of their toxic impact to living species and environments. Removal of metal ions from industrial effluent using nano-particles is an area of extensive research. This study collected wastewaters and effluents from 11 industrial companies in tanning, electronic plating, printed circuit board manufacturing, semi-conductor, and metal surface treatment industry and studied in detailed the major and trace element compositions to develop potential fingerprinting technique for pollutant source identification. The results showed that electronic plating and metal surface treatment industry produce high Fe, Mn, Cr, Zn, Ni and Mo wastewater. The tanning industry and the printed circuit board manufacturing industry released wastewater with high Fe and Cr, Cu and Ni, respectively. For semi-conductor industry, significant dissolved In was detected in wastewater. The absorption experiments to remove heavy metals in waters were conducted using Fe3O4 nano-particles. Under optimal conditions, more than 99 % dissolved metals were removed in a few minutes.

AutoMOPS- B2B and B2C in mask making: Mask manufacturing performance and customer satisfaction improvement through better information flow management using generic models and standardized languages

NASA Astrophysics Data System (ADS)

Filies, Olaf; de Ridder, Luc; Rodriguez, Ben; Kujiken, Aart

2002-03-01

Semiconductor manufacturing has become a global business, in which companies of different size unite in virtual enterprises to meet new opportunities. Therefore Mask manufacturing is a key business, but mask ordering is a complex process and is always critical regarding design to market time, even though mask complexity and customer base are increasing using a wide variety of different mask order forms which are frequently faulty and very seldom complete. This is effectively blocking agile manufacturing and can tie wafer fabs to a single mask The goal of the project is elimination of the order verification through paperless, electronically linked information sharing/exchange between chip design, mask production and production stages, which will allow automation of the mask preparation. To cover these new techniques and their specifications as well as the common ones with automated tools a special generic Meta-model will be generated, based on the current standards for mask specifications, including the requirements from the involved partners (Alcatel Microelectronics, Altis, Compugraphics, Infineon, Nimble, Sigma-C), the project works out a pre-normative standard. The paper presents the current status of work. This work is partly funded by the Commission of the European Union under the Fifth Framework project IST-1999-10332 AutoMOPS.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon [Pinole, CA; Bruchez, Jr., Marcel; Alivisatos, Paul [Oakland, CA

2008-01-01

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) an affinity molecule linked to the semiconductor nanocrystal. The semiconductor nanocrystal is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. Exposure of the semiconductor nanocrystal to excitation energy will excite the semiconductor nanocrystal causing the emission of electromagnetic radiation. Further described are processes for respectively: making the luminescent semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Roadmap evolution: from NTRS to ITRS, from ITRS 2.0 to IRDS

NASA Astrophysics Data System (ADS)

Gargini, Paolo A.

2017-10-01

The semiconductor industry benefitted from roadmap guidance since the mid-60s. The roadmap anticipated and outlined the main needs of the semiconductor industry for years to come and identified future challenges and possible solutions. Making transistor smaller by means of advanced lithographic technologies enabled both increased integration levels and improved IC performance. The roadmap methodology allowed the removal of multiple "red brick walls". The NTRS and the ITRS constituted primarily a "bottom up" approach as standard microprocessors and memories where introduced at a blistering pace barely allowing time for system houses to integrate them in their products. The 1998 ITRS provided the vision that triggered research, development and manufacturing communities to develop a completely new transistor structure in addition to replacing aluminum interconnects with a more advanced technology. The advent of Foundries and Fabless companies transformed the electronics industry into a "top down" driven industry in the past 15 years. The ITRS adjusted to this new ecosystem and morphed into the International Roadmap for Devices and Systems (IRDS) sponsored by IEEE. The IRDS is addressing the requirements and needs of the renewed electronics industry. Furthermore, by the middle of the next decade the ability to layout integrated circuits in a 2D geometry grid will reach fundamental physical limits and the aggressive conversion to 3D architecture for integrated circuit must be pursued across the board as an avenue to continuously increasing transistor count and improving performance. EUV technology is finally approaching the manufacturing stage but with the advent of 3D monolithically integrated heterogeneous circuits approaching in the not-toodistant future should the semiconductor industry concentrate its resources on the next lithographic technology generation in order to enhance resolution or on providing a smooth transition to the new revolutionary 3D architecture of integrated circuits? It is essential for the whole semiconductor industry to come together and make fundamental choices leading to a cooperative and synchronized allocation of adequate resources to produce viable solutions that once introduced in a timely manner into manufacturing will enable the continuation of the growth of the electronic industry at a pace comparable or exceeding historical trends.

Optimizing process and equipment efficiency using integrated methods

NASA Astrophysics Data System (ADS)

D'Elia, Michael J.; Alfonso, Ted F.

1996-09-01

The semiconductor manufacturing industry is continually riding the edge of technology as it tries to push toward higher design limits. Mature fabs must cut operating costs while increasing productivity to remain profitable and cannot justify large capital expenditures to improve productivity. Thus, they must push current tool production capabilities to cut manufacturing costs and remain viable. Working to continuously improve mature production methods requires innovation. Furthermore, testing and successful implementation of these ideas into modern production environments require both supporting technical data and commitment from those working with the process daily. At AMD, natural work groups (NWGs) composed of operators, technicians, engineers, and supervisors collaborate to foster innovative thinking and secure commitment. Recently, an AMD NWG improved equipment cycle time on the Genus tungsten silicide (WSi) deposition system. The team used total productive manufacturing (TPM) to identify areas for process improvement. Improved in-line equipment monitoring was achieved by constructing a real time overall equipment effectiveness (OEE) calculator which tracked equipment down, idle, qualification, and production times. In-line monitoring results indicated that qualification time associated with slow Inspex turn-around time and machine downtime associated with manual cleans contributed greatly to reduced availability. Qualification time was reduced by 75% by implementing a new Inspex monitor pre-staging technique. Downtime associated with manual cleans was reduced by implementing an in-situ plasma etch back to extend the time between manual cleans. A designed experiment was used to optimize the process. Time between 18 hour manual cleans has been improved from every 250 to every 1500 cycles. Moreover defect density realized a 3X improvement. Overall, the team achieved a 35% increase in tool availability. This paper details the above strategies and accomplishments.

Hydrazine-Free Solution-Deposited CuIn(S,Se)2 Solar Cells by Spray Deposition of Metal Chalcogenides.

PubMed

Arnou, Panagiota; van Hest, Maikel F A M; Cooper, Carl S; Malkov, Andrei V; Walls, John M; Bowers, Jake W

2016-05-18

Solution processing of semiconductors, such as CuInSe2 and its alloys (CIGS), can significantly reduce the manufacturing costs of thin film solar cells. Despite the recent success of solution deposition approaches for CIGS, toxic reagents such as hydrazine are usually involved, which introduce health and safety concerns. Here, we present a simple and safer methodology for the preparation of high-quality CuIn(S, Se)2 absorbers from metal sulfide solutions in a diamine/dithiol mixture. The solutions are sprayed in air, using a chromatography atomizer, followed by a postdeposition selenization step. Two different selenization methods are explored resulting in power conversion efficiencies of up to 8%.

Accurate lithography simulation model based on convolutional neural networks

NASA Astrophysics Data System (ADS)

Watanabe, Yuki; Kimura, Taiki; Matsunawa, Tetsuaki; Nojima, Shigeki

2017-07-01

Lithography simulation is an essential technique for today's semiconductor manufacturing process. In order to calculate an entire chip in realistic time, compact resist model is commonly used. The model is established for faster calculation. To have accurate compact resist model, it is necessary to fix a complicated non-linear model function. However, it is difficult to decide an appropriate function manually because there are many options. This paper proposes a new compact resist model using CNN (Convolutional Neural Networks) which is one of deep learning techniques. CNN model makes it possible to determine an appropriate model function and achieve accurate simulation. Experimental results show CNN model can reduce CD prediction errors by 70% compared with the conventional model.

Photovoltaics Fact Sheet

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2016-02-01

This fact sheet is an overview of the Photovoltaics (PV) subprogram at the U.S. Department of Energy SunShot Initiative. The U.S. Department of Energy (DOE)’s Solar Energy Technologies Office works with industry, academia, national laboratories, and other government agencies to advance solar PV, which is the direct conversion of sunlight into electricity by a semiconductor, in support of the goals of the SunShot Initiative. SunShot supports research and development to aggressively advance PV technology by improving efficiency and reliability and lowering manufacturing costs. SunShot’s PV portfolio spans work from early-stage solar cell research through technology commercialization, including work on materials,more » processes, and device structure and characterization techniques.« less

Dissociative properties of 1,1,1,2-tetrafluoroethane obtained by computational chemistry

NASA Astrophysics Data System (ADS)

Hayashi, Toshio; Ishikawa, Kenji; Sekine, Makoto; Hori, Masaru

2018-06-01

The electronic properties and dissociative channels of the alternative to the CCl2F2 (CFC-12) refrigerant, 1,1,1,2-tetrafluoroethane (HFC-134a) with a low global warming potential (GWP, 1430), were revealed by computational chemistry. The results show that CF3 + and CHF2 + ions are mainly produced by ionization. The CF3CH2 + ion is produced by ion pair formation and by direct ionization in the energy region higher than approximately 15 eV, but also in small amounts by the ionization of the dissociated CF3CH2 radical. This information is useful for etching process engineers in leading-edge semiconductor manufacturing.

Hand-Held Devices Detect Explosives and Chemical Agents

NASA Technical Reports Server (NTRS)

2010-01-01

Ion Applications Inc., of West Palm Beach, Florida, partnered with Ames Research Center through Small Business Innovation Research (SBIR) agreements to develop a miniature version ion mobility spectrometer (IMS). While NASA was interested in the instrument for detecting chemicals during exploration of distant planets, moons, and comets, the company has incorporated the technology into a commercial hand-held IMS device for use by the military and other public safety organizations. Capable of detecting and identifying molecules with part-per-billion sensitivity, the technology now provides soldiers with portable explosives and chemical warfare agent detection. The device is also being adapted for detecting drugs and is employed in industrial processes such as semiconductor manufacturing.

Body of Knowledge (BOK) for Copper Wire Bonds

NASA Technical Reports Server (NTRS)

Rutkowski, E.; Sampson, M. J.

2015-01-01

Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate - approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling. Despite the difficult problems associated with the changeover to copper bonding wire, there are billions of copper wire bonded devices delivered annually to customers. It is noteworthy that Texas Instruments announced in October of 2014 that they are shipping microcircuits containing copper wire bonds for safety critical automotive applications. An evaluation of copper wire bond technology for applicability to spaceflight hardware may be warranted along with concurrently compiling a comprehensive understanding of the failure mechanisms involved with copper wire bonded semiconductor devices.

Dissolved air flotation of polishing wastewater from semiconductor manufacturer.

PubMed

Liu, J C; Lien, C Y

2006-01-01

The feasibility of the dissolved air flotation (DAF) process in treating chemical mechanical polishing (CMP) wastewater was evaluated in this study. Wastewater from a local semiconductor manufacturer was sampled and characterised. Nano-sized silica (77.6 nm) with turbidity of 130 +/- 3 NTU was found in the slightly alkaline wastewater with traces of other pollutants. Experimental results indicated removal efficiency of particles, measured as suspended particle or turbidity, increased with increasing concentration of cationic collector cetyltrimethyl ammonium bromide (CTAB). When CTAB concentration was 30 mg/L, pH of 6.5 +/- 0.1 and recycle ratio of 30%, very effective removal of particles (> 98%) was observed in saturation pressure range of 4 to 6 kg/cm2, and the reaction proceeded faster under higher pressure. Similarly, the reaction was faster under the higher recycle ratio, while final removal efficiency improved slightly as the recycle ratio increased from 20 to 40%. An insignificant effect of pH on treatment efficiency was found as pH varied from 4.5 to 8.5. The presence of activator, Al3+ and Fe3+, enhanced the system performance. It is proposed that CTAB adsorbs on silica particles in polishing wastewater through electrostatic interaction and makes particles more hydrophobic. The increase in hydrophobicity results in more effective bubble-particle collisions. In addition, flocculation of silica particles through bridging effect of collector was found; it is believed that flocculation of particles also contributed to flotation. Better attachment between gas bubble and solid, higher buoyancy and higher air to solid ratio all lead to effective flotation.

Determining the Concentrations and Temperatures of Products in a CF_4/CHF_3/N_2 Plasma via Submillimeter Absorption Spectroscopy

NASA Astrophysics Data System (ADS)

Helal, Yaser H.; Neese, Christopher F.; De Lucia, Frank C.; Ewing, Paul R.; Agarwal, Ankur; Craver, Barry; Stout, Phillip J.; Armacost, Michael D.

2017-06-01

Plasmas used for the manufacturing of semiconductor devices are similar in pressure and temperature to those used in the laboratory for the study of astrophysical species in the submillimeter (SMM) spectral region. The methods and technology developed in the SMM for these laboratory studies are directly applicable for diagnostic measurements in the semiconductor manufacturing industry. Many of the molecular neutrals, radicals, and ions present in processing plasmas have been studied and their spectra have been cataloged or are in the literature. In this work, a continuous wave, intensity calibrated SMM absorption spectrometer was developed as a remote sensor of gas and plasma species. A major advantage of intensity calibrated rotational absorption spectroscopy is its ability to determine absolute concentrations and temperatures of plasma species from first principles without altering the plasma environment. An important part of this work was the design of the optical components which couple 500-750 GHz radiation through a commercial inductively coupled plasma chamber. The measurement of transmission spectra was simultaneously fit for background and absorption signal. The measured absorption was used to calculate absolute densities and temperatures of polar species. Measurements for CHF_3, CF_2, FCN, HCN, and CN made in a CF_4/CHF_3/N_2 plasma will be presented. Temperature equilibrium among species will be shown and the common temperature is leveraged to obtain accurate density measurements for simultaneously observed species. The densities and temperatures of plasma species are studied as a function of plasma parameters, including flow rate, pressure, and discharge power.

Reducing bottom anti-reflective coating (BARC) defects: optimizing and decoupling the filtration and dispense process

NASA Astrophysics Data System (ADS)

Brakensiek, Nickolas L.; Martin, Gary; Simmons, Sean; Batchelder, Traci

2006-03-01

Semiconductor device manufacturing is one of the cleanest manufacturing operations that can be found in the world today. It has to be that way; a particle on a wafer today can kill an entire device, which raises the costs, and therefore reduces the profits, of the manufacturing company in two ways: it must produce extra wafers to make up for the lost die, and it has less product to sell. In today's state-of-the-art fab, everything is filtered to the lowest pore size available. This practice is fairly easy for gases because a gas molecule is very small compared to the pore size of the filter. Filtering liquids, especially photochemicals such as photoresists and BARCs, can be much harder because the molecules that form the polymers used to manufacture the photochemicals are approaching the filter pore size. As a result, filters may plug up, filtration rates may drop, pressure drops across the filter may increase, or a filter may degrade. These conditions can then cause polymer shearing, microbubble formation, gel particle formation, and BARC chemical changes to occur before the BARC reaches the wafer. To investigate these possible interactions, an Entegris(R) IntelliGen(R) pump was installed on a TEL Mk8 TM track to see if the filtration process would have an effect on the BARC chemistry and coating defects. Various BARC chemicals such as DUV112 and DUV42P were pumped through various filter media having a variety of pore sizes at different filtration rates to investigate the interaction between the dispense process and the filtration process. The IntelliGen2 pump has the capability to filter the BARC independent of the dispense process. By using a designed experiment to look at various parameters such as dispense rate, filtration rate, and dispense volume, the effects of the complete pump system can be learned, and appropriate conditions can be applied to yield the cleanest BARC coating process. Results indicate that filtration rate and filter pore size play a dramatic role in the defect density on a coated wafer with the actual dispense properties such as dispense wafer speed and dispense time playing a lesser role.

Decreased white blood cell counts in semiconductor manufacturing workers in Taiwan

PubMed Central

Luo, J; Hsieh, L; Chang, M; Hsu, K

2002-01-01

Objectives: To assess the systematic health effects on the liver, kidney, and haematological function tests of workers in semiconductors in Taiwan. Methods: 926 workers of a semiconductor plant in Taiwan in July 1995 were investigated. Complete blood tests including liver, kidney, and haematological functions were available from 227 workers. Results: There was a significantly lower mean (SD) white blood cell (WBC) count in male workers of photolithography (5870 (1190)/mm3, p=0.003) and implantation (6190 (1150)/mm3, p=0.018) than that of male control workers (7350 (1660)/mm3). There was a significantly higher prevalence of leukopenia in male photolithography workers (6 of 20; 30%) than in male control workers (1 of 18; 5.6%), the crude odds ratio (OR) was 7.3 (95% confidence interval (95% CI) 1 to 55.6), and the multivariate adjusted OR was 8.1 (95% CI 0.83 to 78.3). The tests for serum glutamic oxaloacetic transaminase (SGOT), serum glutamic pyruvic transaminase (SGPT), γ glutamyl transferase (RGT), and creatinine were not significant among male workers. Female workers in photolithography had abnormal SGPT and RGT of borderline significance, the multivariate adjusted ORs were 9.6 (95% CI 0.86 to 107) and 6.35 (95% CI 0.53 to 75.8), respectively. Conclusions: This study suggests that leukopenia is a potential health effect in male fabrication workers of the semiconductor industry. The tasks of the process, maintenance, and equipment engineers which consisted mostly of men put them at risk for intermittent short term peak exposure to glycol ethers, ionising radiation, arsenic, or other toxins. The findings of this medical surveillance are significant; however, a further investigation of the aetiological factors and the subsequent health effects is necessary. PMID:11836468

Selective etchant for oxide sacrificial material in semiconductor device fabrication

DOEpatents

Clews, Peggy J.; Mani, Seethambal S.

2005-05-17

An etching composition and method is disclosed for removing an oxide sacrificial material during manufacture of semiconductor devices including micromechanical, microelectromechanical or microfluidic devices. The etching composition and method are based on the combination of hydrofluoric acid (HF) and sulfuric acid (H.sub.2 SO.sub.4). These acids can be used in the ratio of 1:3 to 3:1 HF:H.sub.2 SO.sub.4 to remove all or part of the oxide sacrificial material while providing a high etch selectivity for non-oxide materials including polysilicon, silicon nitride and metals comprising aluminum. Both the HF and H.sub.2 SO.sub.4 can be provided as "semiconductor grade" acids in concentrations of generally 40-50% by weight HF, and at least 90% by weight H.sub.2 SO.sub.4.

Bacteria inside semiconductors as potential sensor elements: biochip progress.

PubMed

Sah, Vasu R; Baier, Robert E

2014-06-24

It was discovered at the beginning of this Century that living bacteria-and specifically the extremophile Pseudomonas syzgii-could be captured inside growing crystals of pure water-corroding semiconductors-specifically germanium-and thereby initiated pursuit of truly functional "biochip-based" biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips.

Building devices from colloidal quantum dots.

PubMed

Kagan, Cherie R; Lifshitz, Efrat; Sargent, Edward H; Talapin, Dmitri V

2016-08-26

The continued growth of mobile and interactive computing requires devices manufactured with low-cost processes, compatible with large-area and flexible form factors, and with additional functionality. We review recent advances in the design of electronic and optoelectronic devices that use colloidal semiconductor quantum dots (QDs). The properties of materials assembled of QDs may be tailored not only by the atomic composition but also by the size, shape, and surface functionalization of the individual QDs and by the communication among these QDs. The chemical and physical properties of QD surfaces and the interfaces in QD devices are of particular importance, and these enable the solution-based fabrication of low-cost, large-area, flexible, and functional devices. We discuss challenges that must be addressed in the move to solution-processed functional optoelectronic nanomaterials. Copyright © 2016, American Association for the Advancement of Science.

Quantum Confined Semiconductors - In-House Interim Research

DTIC Science & Technology

2013-04-01

Laboratory, Materials & Manufacturing Directorate, Wright Patterson AFB, OH 45433-7707, USA blnstituto de Ciencias Fisicas, Universidad Nacional Aut6noma...111is work was supported by the Ai1· Force Office of Scientific Research (AFRU RS E, Dr. Kitt Reinhardt). • Also with lnstituto de Ciencias Fisicas

Thermoelectric generator and method for the fabrication thereof

DOEpatents

Benson, David K.; Tracy, C. Edwin

1987-01-01

A thermoelectric generator using semiconductor elements for responding to a temperature gradient to produce electrical energy with all of the semiconductor elements being of the same type is disclosed. A continuous process for forming substrates on which the semiconductor elements and superstrates are deposited and a process for forming the semiconductor elements on the substrates are also disclosed. The substrates with the semiconductor elements thereon are combined with superstrates to form modules for use thermoelectric generators.

Thermoelectric generator and method for the fabrication thereof

DOEpatents

Benson, D.K.; Tracy, C.E.

1984-08-01

A thermoelectric generator using semiconductor elements for responding to a temperature gradient to produce electrical energy with all of the semiconductor elements being of the same type is disclosed. A continuous process for forming substrates on which the semiconductor elements and superstrates are deposited and a process for forming the semiconductor elements on the substrates are also disclosed. The substrates with the semiconductor elements thereon are combined with superstrates to form modules for use as thermoelectric generators.

A flexible architecture for advanced process control solutions

NASA Astrophysics Data System (ADS)

Faron, Kamyar; Iourovitski, Ilia

2005-05-01

Advanced Process Control (APC) is now mainstream practice in the semiconductor manufacturing industry. Over the past decade and a half APC has evolved from a "good idea", and "wouldn"t it be great" concept to mandatory manufacturing practice. APC developments have primarily dealt with two major thrusts, algorithms and infrastructure, and often the line between them has been blurred. The algorithms have evolved from very simple single variable solutions to sophisticated and cutting edge adaptive multivariable (input and output) solutions. Spending patterns in recent times have demanded that the economics of a comprehensive APC infrastructure be completely justified for any and all cost conscious manufacturers. There are studies suggesting integration costs as high as 60% of the total APC solution costs. Such cost prohibitive figures clearly diminish the return on APC investments. This has limited the acceptance and development of pure APC infrastructure solutions for many fabs. Modern APC solution architectures must satisfy the wide array of requirements from very manual R&D environments to very advanced and automated "lights out" manufacturing facilities. A majority of commercially available control solutions and most in house developed solutions lack important attributes of scalability, flexibility, and adaptability and hence require significant resources for integration, deployment, and maintenance. Many APC improvement efforts have been abandoned and delayed due to legacy systems and inadequate architectural design. Recent advancements (Service Oriented Architectures) in the software industry have delivered ideal technologies for delivering scalable, flexible, and reliable solutions that can seamlessly integrate into any fabs" existing system and business practices. In this publication we shall evaluate the various attributes of the architectures required by fabs and illustrate the benefits of a Service Oriented Architecture to satisfy these requirements. Blue Control Technologies has developed an advance service oriented architecture Run to Run Control System which addresses these requirements.

A Manufacturing Cost and Supply Chain Analysis of SiC Power Electronics Applicable to Medium-Voltage Motor Drives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horowitz, Kelsey; Remo, Timothy; Reese, Samantha

Wide bandgap (WBG) semiconductor devices are increasingly being considered for use in certain power electronics applications, where they can improve efficiency, performance, footprint, and, potentially, total system cost compared to systems using traditional silicon (Si) devices. Silicon carbide (SiC) devices in particular -- which are currently more mature than other WBG devices -- are poised for growth in the coming years. Today, the manufacturing of SiC wafers is concentrated in the United States, and chip production is split roughly equally between the United States, Japan, and Europe. Established contract manufacturers located throughout Asia typically carry out manufacturing of WBG powermore » modules. We seek to understand how global manufacturing of SiC components may evolve over time by illustrating the regional cost drivers along the supply chain and providing an overview of other factors that influence where manufacturing is sited. We conduct this analysis for a particular case study where SiC devices are used in a medium-voltage motor drive.« less

Generic process for preparing a crystalline oxide upon a group IV semiconductor substrate

DOEpatents

McKee, Rodney A.; Walker, Frederick J.; Chisholm, Matthew F.

2000-01-01

A process for growing a crystalline oxide epitaxially upon the surface of a Group IV semiconductor, as well as a structure constructed by the process, is described. The semiconductor can be germanium or silicon, and the crystalline oxide can generally be represented by the formula (AO).sub.n (A'BO.sub.3).sub.m in which "n" and "m" are non-negative integer repeats of planes of the alkaline earth oxides or the alkaline earth-containing perovskite oxides. With atomic level control of interfacial thermodynamics in a multicomponent semiconductor/oxide system, a highly perfect interface between a semiconductor and a crystalline oxide can be obtained.

Comparative analysis of redox and inflammatory properties of pristine nanomaterials and commonly used semiconductor manufacturing nano-abrasives.

PubMed

Flaherty, Nicole L; Chandrasekaran, Akshaya; del Pilar Sosa Peña, Maria; Roth, Gary A; Brenner, Sara A; Begley, Thomas J; Melendez, J Andrés

2015-12-15

Continued expansion of the nanotechnology industry has necessitated the self-assessment of manufacturing processes, specifically in regards to understanding the health related aspects following exposure to nanomaterials. There exists a growing concern over potential occupational exposure in the semiconductor industry where Al2O3, CeO2 and SiO2 nanoparticles are commonly featured as part of the chemical mechanical planarization (CMP) process. Chronic exposure to toxicants can result not only in acute cytotoxicity but also initiation of a chronic inflammatory state associated with diverse pathologies. In the current investigation, pristine nanoparticles and CMP slurry formulations of Al2O3, SiO2 and CeO2 were employed to assess their ability to induce cytotoxicity, inflammatory responses and reactive oxygen species in a mouse alveolar macrophage cell model. The pristine nanoparticles and slurries were not intrinsically cytotoxic and did not generate free radicals but were found to act as scavengers in the presence of an oxidant stimulant. Al2O3 and SiO2 nanoparticles increased levels of pro-inflammatory cytokines while pristine SiO2 nanoparticles induced generation of F2-Isoprostanes. In co-treatment studies, the pristine nanomaterials modulated the response to the inflammatory stimulant lipopolysaccharide. The studies have established that pristine nanoparticles and slurries do not impact the cells in a similar way indicating that they should not be used as slurry substitutes in toxicity evaluations. Further, we have defined how an alveolar cell line, which would likely be the first challenged upon nanomaterial aerosolization, responds to diverse mixtures of nanomaterials. Moreover, our findings reinforce the importance of using multiple analytic methods to define the redox state of the cell following exposure to commonly used industrial nanomaterials and toxicants. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

75 FR 879 - National Semiconductor Corporation Arlington Manufacturing Site Including On-Site Leased Workers...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-01-06

... Foods, Allied Barton Security, ASIL, ASML and Construction Mechanical Systems Arlington, TX; Amended... leased workers from ASML and Construction Mechanical Systems were employed on-site at the Arlington... Department is amending the certification to include workers leased from ASML and Construction Mechanical...

Plasma chemistry and its applications

NASA Technical Reports Server (NTRS)

Hozumi, K.

1980-01-01

The relationship between discharge phenomena and plasma chemistry, as well as the equipment and mechanisms of plasma chemical reactions are described. Various areas in which plasma chemistry is applied are surveyed, such as: manufacturing of semiconductor integrated circuits; synthetic fibers; high polymer materials for medical uses; optical lenses; and membrane filters (reverse penetration films).

Microwave Sintering of Ceramic Materials for Industrial Application Final Report CRADA No. TC-1116-95

DOE Office of Scientific and Technical Information (OSTI.GOV)

Caplan, M.; Tandon, R.; Callis, R.

The goal of this project was to develop the commercial capability in the US to sinter alumina oxide ceramic parts for the semiconductor manufacturing equipment industry. We planned to use the millimeter microwave (30 GHz) sintering system first developed by IAP in Russia.

40 CFR 63.7182 - What parts of my facility does this subpart cover?

Code of Federal Regulations, 2010 CFR

2010-07-01

... (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL EMISSION STANDARDS FOR HAZARDOUS AIR POLLUTANTS FOR SOURCE... subpart applies to each new, reconstructed, or existing affected source that you own or operate that manufactures semiconductors. (b) An affected source subject to this subpart is the collection of all...

40 CFR 63.7192 - In what form and how long must I keep my records?

Code of Federal Regulations, 2011 CFR

2011-07-01

... (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL EMISSION STANDARDS FOR HAZARDOUS AIR POLLUTANTS FOR SOURCE CATEGORIES (CONTINUED) National Emission Standards for Hazardous Air Pollutants for Semiconductor Manufacturing Applications, Notifications, Reports, and Records § 63.7192 In what form and how long must I keep...

Workplace Skills in Practice. Case Studies of Technical Work.

ERIC Educational Resources Information Center

Stasz, Cathleen; And Others

A study was conducted to explore skills and work-related dispositions in technical work. It used a sociocultural approach to examine skills in seven target jobs in worksites representing diverse industries--health care, traffic management, transportation, and semiconductor manufacturing. It explored employers' strategies for obtaining the skills…

Abatement of sulfur hexafluoride emissions from the semiconductor manufacturing process by atmospheric-pressure plasmas.

PubMed

Lee, How Ming; Chang, Moo Been; Wu, Kuan Yu

2004-08-01

Sulfur hexafluoride (SF6) is an important gas for plasma etching processes in the semiconductor industry. SF6 intensely absorbs infrared radiation and, consequently, aggravates global warming. This study investigates SF6 abatement by nonthermal plasma technologies under atmospheric pressure. Two kinds of nonthermal plasma processes--dielectric barrier discharge (DBD) and combined plasma catalysis (CPC)--were employed and evaluated. Experimental results indicated that as much as 91% of SF6 was removed with DBDs at 20 kV of applied voltage and 150 Hz of discharge frequency for the gas stream containing 300 ppm SF6, 12% oxygen (O2), and 40% argon (Ar), with nitrogen (N2) as the carrier gas. Four additives, including Ar, O2, ethylene (C2H4), and H2O(g), are effective in enhancing SF6 abatement in the range of conditions studied. DBD achieves a higher SF6 removal efficiency than does CPC at the same operation condition. But CPC achieves a higher electrical energy utilization compared with DBD. However, poisoning of catalysts by sulfur (S)-containing species needs further investigation. SF6 is mainly converted to SOF2, SO2F4, sulfur dioxide (SO2), oxygen difluoride (OF2), and fluoride (F2). They do not cause global warming and can be captured by either wet scrubbing or adsorption. This study indicates that DBD and CPC are feasible control technologies for reducing SF6 emissions.

Optical Metrology for Directed Self-assembly Patterning Using Mueller Matrix Spectroscopic Ellipsometry Based Scatterometry

NASA Astrophysics Data System (ADS)

Dixit, Dhairya J.

The semiconductor industry continues to drive patterning solutions that enable devices with higher memory storage capacity, faster computing performance, lower cost per transistors, and higher transistor density. These developments in the field of semiconductor manufacturing along with the overall minimization of the size of transistors require cutting-edge metrology tools for characterization. Directed self-assembly (DSA) patterning process can be used to fabricate nanoscale line-space patterns and contact holes via thermodynamically driven micro-phase separation of block copolymer (BCP) films with boundary constraints from guiding templates. Its main advantages are high pattern resolution (~10 nm), high throughput, no requirement of a high-resolution mask, and compatibility with standard fab-equipment and processes. Although research into DSA patterning has demonstrated a high potential as a nanoscale patterning process, there are critical challenges that must be overcome before transferring DSA into high volume manufacturing, including achievement of low defect density and high process stability. For this, advances in critical dimension (CD) and overlay measurement as well as rapid defect characterization are required. Both scatterometry and critical dimension-scanning electron microscopy (CD-SEM) are routinely used for inline dimensional metrology. CD-SEM inspection is limited, as it does not easily provide detailed line-shape information, whereas scatterometry has the capability of measuring important feature dimensions including: line-width, line-shape, sidewall-angle, and thickness of the patterned samples quickly and non-destructively. The present work describes the application of Mueller matrix spectroscopic ellipsometry (MMSE) based scatterometry to optically characterize DSA patterned line- space grating and contact hole structures fabricated with phase-separated polystyrene-b-polymethylmethacrylate (PS-b-PMMA) at various integration steps of BCP DSA based patterning process. This work focuses on understanding the efficacy of MMSE base scatterometry for characterizing complex DSA structures. For example, the use of symmetry-antisymmetry properties associated with Mueller matrix (MM) elements to understand the topography of the periodic nanostructures and measure defectivity. Simulations (the forward problem approach of scatterometry) are used to investigate MM elements' sensitivity to changes in DSA structure such as one vs. two contact hole patterns and predict sensitivity to dimensional changes. A regression-based approach is used to extract feature shape parameters of the DSA structures by fitting simulated optical spectra to experimental optical spectra. Detection of the DSA defects is a key to reducing defect density for eventual manufacturability and production use of DSA process. Simulations of optical models of structures containing defects are used to evaluate the sensitivity of MM elements to DSA defects. This study describes the application of MMSE to determine the DSA pattern defectivity via spectral comparisons based on optical anisotropy and depolarization. The use of depolarization and optical anisotropy for characterization of experimental MMSE data is a very recent development in scatterometry. In addition, reconstructed scatterometry models are used to calculate line edge roughness in 28 nm pitch Si fins fabricated using DSA patterning process.

Stable surface passivation process for compound semiconductors

DOEpatents

Ashby, Carol I. H.

2001-01-01

A passivation process for a previously sulfided, selenided or tellurated III-V compound semiconductor surface. The concentration of undesired mid-gap surface states on a compound semiconductor surface is reduced by the formation of a near-monolayer of metal-(sulfur and/or selenium and/or tellurium)-semiconductor that is effective for long term passivation of the underlying semiconductor surface. Starting with the III-V compound semiconductor surface, any oxidation present thereon is substantially removed and the surface is then treated with sulfur, selenium or tellurium to form a near-monolayer of chalcogen-semiconductor of the surface in an oxygen-free atmosphere. This chalcogenated surface is then contacted with a solution of a metal that will form a low solubility chalcogenide to form a near-monolayer of metal-chalcogen-semiconductor. The resulting passivating layer provides long term protection for the underlying surface at or above the level achieved by a freshly chalcogenated compound semiconductor surface in an oxygen free atmosphere.

Deposit heterogeneity and the dynamics of the organic semiconductors P3HT and PCBM solution under evaporation

NASA Astrophysics Data System (ADS)

Yu, H. P.; Luo, H.; Liu, T. T.; Jing, G. Y.

2015-04-01

The formation of organic semiconductor layer is the key procedure in the manufacture of organic photovoltaic solar cell, in which the natural evaporation of the solvent from the polymer solution plays the essential role for the conversion efficiency. Here, poly(3-hexylthiophene) (P3HT) and fullerene derivative [6,6]-phenyl-C61-butyric acid methyl ester (PCBM), as two types of semiconductor polymers, were selected as the active layer to form the deposit by drying the blend solution drops on the substrate. We explored the influences of droplet size and solute concentration on the homogeneity of the deposit. Additionally, the spatial distribution of molecular chains and grains and the instability of the droplet morphology during the drying were investigated. The results showed that the "coffee-ring" phenomenon occurred forming an annular deposit at the outermost edge and the width of the annular ring increased linearly with the concentration of the P3HT solution, until a saturation plateau is approached. On the other hand, the PCBM deposition presented a circular disk at low concentration, but displayed a sudden instability for an irregular perimeter at a critical concentration and there existed a second critical concentration above which the deposit exhibited the return of the stable circular shape. The results have an instructive impact on the performance of the device and the formation of fine structures during the process of printing, film preparation and painting.

Enhanced biosensing resolution with foundry fabricated individually addressable dual-gated ISFETs.

PubMed

Duarte-Guevara, Carlos; Lai, Fei-Lung; Cheng, Chun-Wen; Reddy, Bobby; Salm, Eric; Swaminathan, Vikhram; Tsui, Ying-Kit; Tuan, Hsiao Chin; Kalnitsky, Alex; Liu, Yi-Shao; Bashir, Rashid

2014-08-19

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that is fabricated with a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process by Taiwan Semiconductor Manufacturing Company (TSMC). In contrast to conventional SOI ISFETs, each transistor has an individually addressable back-gate and a gate oxide that is directly exposed to the solution. The elimination of the commonly used floating gate architecture reduces the chance of electrostatic discharge and increases the potential achievable transistor density. We show that when operated in a "dual-gate" mode, the transistor response can exhibit sensitivities to pH changes beyond the Nernst limit. This enhancement in sensitivity was shown to increase the sensor's signal-to-noise ratio, allowing the device to resolve smaller pH changes. An improved resolution can be used to enhance small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions. As a proof of concept, we demonstrate that the amplified sensitivity and improved resolution result in a shorter detection time and a larger output signal of a loop-mediated isothermal DNA amplification reaction (LAMP) targeting a pathogenic bacteria gene, showing benefits of the new structure for biosensing applications.

Plasmonics based micro/nano manufacturing

NASA Astrophysics Data System (ADS)

Garner, Quincy

Since the advent of the Information Age, there has been an ever growing demand to continually shrink and reduce the cost of semiconductor products. To meet this demand, a great amount of research has been done to improve our current micro/nano manufacturing processes and develop the next generation of semiconductor fabrication techniques. High throughput, low cost, smaller features, high repeatability, and the simplification of the manufacturing processes are all targets that researchers continually strive for. To this day, there are no perfect systems capable of simultaneously achieving all of these targets. For this reason, much research time is spent improving and developing new techniques in hopes of developing a system that will incorporate all of these targets. While there are numerous techniques being investigated and developed every year, one of the most promising areas of research that may one day be capable of achieving our desired targets is plasmonics. Plasmonics, or the study of the free electron oscillations in metals, is the driving phenomena in the applications reported in this paper. In chapter 2, the formation of ordered gold nanoparticles on a silicon substrate through the use of energetic surface plasmons is reported. Utilizing a gold/alumina nano-hole antenna and 1064 nm Nd:YAG laser system, semi-periodic gold nanoparticles were deposited onto the surface of a silicon substrate. The novel technique is simpler, faster, and safer than any known gold nanoparticle deposition technique reported in literature. The implementation of this technique has potential wide-ranging applications in photovoltaic cells, medical products, and many others. In chapter 3, a low cost lithography technique utilizing surface plasmons is reported. In this technique, a plasmonic photomask is created by coating a pre-made porous alumina membrane with a thin aluminum layer. A coherent, 337 nm UV laser source is used to expose the photomask and excite surface plasmons along the metal layer. The surface plasmons allow for features well below the wavelength of the incident light to be produced. Along with this technique, a unique texturing effect was discovered using the same photomask and 400 nm UV lamp source. The developed technique promises to greatly reduce the cost and complexity of sub-100 nm photolithography using only a UV light source and the novel plasmonic photomask.

Device overlay method for high volume manufacturing

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Kim, Youngsik; Kim, Myoungsoo; Heo, Hoyoung; Jeon, Sanghuck; Choi, DongSub; Nabeth, Jeremy; Brinster, Irina; Pierson, Bill; Robinson, John C.

2016-03-01

Advancing technology nodes with smaller process margins require improved photolithography overlay control. Overlay control at develop inspection (DI) based on optical metrology targets is well established in semiconductor manufacturing. Advances in target design and metrology technology have enabled significant improvements in overlay precision and accuracy. One approach to represent in-die on-device as-etched overlay is to measure at final inspection (FI) with a scanning electron microscope (SEM). Disadvantages to this approach include inability to rework, limited layer coverage due to lack of transparency, and higher cost of ownership (CoO). A hybrid approach is investigated in this report whereby infrequent DI/FI bias is characterized and the results are used to compensate the frequent DI overlay results. The bias characterization is done on an infrequent basis, either based on time or triggered from change points. On a per-device and per-layer basis, the optical target overlay at DI is compared with SEM on-device overlay at FI. The bias characterization results are validated and tracked for use in compensating the DI APC controller. Results of the DI/FI bias characterization and sources of variation are presented, as well as the impact on the DI correctables feeding the APC system. Implementation details in a high volume manufacturing (HVM) wafer fab will be reviewed. Finally future directions of the investigation will be discussed.

Procedure for pressure contact on high-power semiconductor devices free of thermal fatigue

NASA Technical Reports Server (NTRS)

Knobloch, J.

1979-01-01

To eliminate thermal fatigue, a procedure for manufacturing semiconductor power devices with pure pressure contact without solid binding was developed. Pressure contact without the use of a solid binding to avoid a limitation of the maximum surface in the contact was examined. A silicon wafer covered with a relatively thick metal layer is imbedded with the aid of a soft silver foil between two identically sized hard contact discs (molybdenum or tungsten) which are rotationally symmetrical. The advantages of this concept are shown for large diameters. The pressure contact was tested successfully in many devices in a large variety of applications.

Advances in polycrystalline thin-film photovoltaics for space applications

NASA Technical Reports Server (NTRS)

Lanning, Bruce R.; Armstrong, Joseph H.; Misra, Mohan S.

1994-01-01

Polycrystalline, thin-film photovoltaics represent one of the few (if not the only) renewable power sources which has the potential to satisfy the demanding technical requirements for future space applications. The demand in space is for deployable, flexible arrays with high power-to-weight ratios and long-term stability (15-20 years). In addition, there is also the demand that these arrays be produced by scalable, low-cost, high yield, processes. An approach to significantly reduce costs and increase reliability is to interconnect individual cells series via monolithic integration. Both CIS and CdTe semiconductor films are optimum absorber materials for thin-film n-p heterojunction solar cells, having band gaps between 0.9-1.5 ev and demonstrated small area efficiencies, with cadmium sulfide window layers, above 16.5 percent. Both CIS and CdTe polycrystalline thin-film cells have been produced on a laboratory scale by a variety of physical and chemical deposition methods, including evaporation, sputtering, and electrodeposition. Translating laboratory processes which yield these high efficiency, small area cells into the design of a manufacturing process capable of producing 1-sq ft modules, however, requires a quantitative understanding of each individual step in the process and its (each step) effect on overall module performance. With a proper quantification and understanding of material transport and reactivity for each individual step, manufacturing process can be designed that is not 'reactor-specific' and can be controlled intelligently with the design parameters of the process. The objective of this paper is to present an overview of the current efforts at MMC to develop large-scale manufacturing processes for both CIS and CdTe thin-film polycrystalline modules. CIS cells/modules are fabricated in a 'substrate configuration' by physical vapor deposition techniques and CdTe cells/modules are fabricated in a 'superstrate configuration' by wet chemical methods. Both laser and mechanical scribing operations are used to monolithically integrate (series interconnect) the individual cells into modules. Results will be presented at the cell and module development levels with a brief description of the test methods used to qualify these devices for space applications. The approach and development efforts are directed towards large-scale manufacturability of established thin-film, polycrystalline processing methods for large area modules with less emphasis on maximizing small area efficiencies.

TOPICAL REVIEW: Semiconductors for terahertz photonics applications

NASA Astrophysics Data System (ADS)

Krotkus, Arūnas

2010-07-01

Generation and measurement of ultrashort, subpicosecond pulses of electromagnetic radiation with their characteristic Fourier spectra that reach far into terahertz (THz) frequency range has recently become a versatile tool of far-infrared spectroscopy and imaging. This technique, THz time-domain spectroscopy, in addition to a femtosecond pulse laser, requires semiconductor components manufactured from materials with a short photoexcited carrier lifetime, high carrier mobility and large dark resistivity. Here we will review the most important developments in the field of investigation of such materials. The main characteristics of low-temperature-grown or ion-implanted GaAs and semiconducting compounds sensitive in the wavelength ranges around 1 µm and 1.5 µm will be surveyed. The second part of the paper is devoted to the effect of surface emission of THz transients from semiconductors illuminated by femtosecond laser pulses. The main physical mechanisms leading to this emission as well as their manifestation in various crystals will be described.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Strain-engineered growth of two-dimensional materials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ahn, Geun Ho; Amani, Matin; Rasool, Haider

The application of strain to semiconductors allows for controlled modification of their band structure. This principle is employed for the manufacturing of devices ranging from high-performance transistors to solid-state lasers. Traditionally, strain is typically achieved via growth on lattice-mismatched substrates. For two-dimensional (2D) semiconductors, this is not feasible as they typically do not interact epitaxially with the substrate. Here in this paper, we demonstrate controlled strain engineering of 2D semiconductors during synthesis by utilizing the thermal coefficient of expansion mismatch between the substrate and semiconductor. Using WSe 2 as a model system, we demonstrate stable built-in strains ranging from 1%more » tensile to 0.2% compressive on substrates with different thermal coefficient of expansion. Consequently, we observe a dramatic modulation of the band structure, manifested by a strain-driven indirect-to-direct bandgap transition and brightening of the dark exciton in bilayer and monolayer WSe 2, respectively. The growth method developed here should enable flexibility in design of more sophisticated devices based on 2D materials.« less

Strain-engineered growth of two-dimensional materials

DOE PAGES

Ahn, Geun Ho; Amani, Matin; Rasool, Haider; ...

2017-09-20

The application of strain to semiconductors allows for controlled modification of their band structure. This principle is employed for the manufacturing of devices ranging from high-performance transistors to solid-state lasers. Traditionally, strain is typically achieved via growth on lattice-mismatched substrates. For two-dimensional (2D) semiconductors, this is not feasible as they typically do not interact epitaxially with the substrate. Here in this paper, we demonstrate controlled strain engineering of 2D semiconductors during synthesis by utilizing the thermal coefficient of expansion mismatch between the substrate and semiconductor. Using WSe 2 as a model system, we demonstrate stable built-in strains ranging from 1%more » tensile to 0.2% compressive on substrates with different thermal coefficient of expansion. Consequently, we observe a dramatic modulation of the band structure, manifested by a strain-driven indirect-to-direct bandgap transition and brightening of the dark exciton in bilayer and monolayer WSe 2, respectively. The growth method developed here should enable flexibility in design of more sophisticated devices based on 2D materials.« less

Mineral commodity profiles: Germanium

USGS Publications Warehouse

Butterman, W.C.; Jorgenson, John D.

2005-01-01

Overview -- Germanium is a hard, brittle semimetal that first came into use a half-century ago as a semiconductor material in radar units and as the material from which the first transistor was made. Today it is used principally as a component of the glass in telecommunications fiber optics; as a polymerization catalyst for polyethylene terephthalate (PET), a commercially important plastic; in infrared (IR) night vision devices; and as a semiconductor and substrate in electronics circuitry. Most germanium is recovered as a byproduct of zinc smelting, although it also has been recovered at some copper smelters and from the fly ash of coal-burning industrial powerplants. It is a highly dispersed element, associated primarily with base-metal sulfide ores. In the United States, germanium is recovered from zinc smelter residues and manufacturing scrap and is refined by two companies at four germanium refineries. One of the four refineries is dedicated to processing scrap. In 2000, producers sold zone-refined (high-purity) germanium at about $1,250 per kilogram and electronic-grade germanium dioxide (GeO2) at $800 per kilogram. Domestic refined production was valued at $22 million. Germanium is a critical component in highly technical devices and processes. It is likely to remain in demand in the future at levels at least as high as those of 2000. U.S. resources of germanium are probably adequate to meet domestic needs for several decades.

Plasma Processing of Metallic and Semiconductor Thin Films in the Fisk Plasma Source

NASA Technical Reports Server (NTRS)

Lampkin, Gregory; Thomas, Edward, Jr.; Watson, Michael; Wallace, Kent; Chen, Henry; Burger, Arnold

1998-01-01

The use of plasmas to process materials has become widespread throughout the semiconductor industry. Plasmas are used to modify the morphology and chemistry of surfaces. We report on initial plasma processing experiments using the Fisk Plasma Source. Metallic and semiconductor thin films deposited on a silicon substrate have been exposed to argon plasmas. Results of microscopy and chemical analyses of processed materials are presented.

Interface and facet control during Czochralski growth of (111) InSb crystals for cost reduction and yield improvement of IR focal plane array substrates

NASA Astrophysics Data System (ADS)

Gray, Nathan W.; Perez-Rubio, Victor; Bolke, Joseph G.; Alexander, W. B.

2014-10-01

Focal plane arrays (FPAs) made on InSb wafers are the key cost-driving component in IR imaging systems. The electronic and crystallographic properties of the wafer directly determine the imaging device performance. The "facet effect" describes the non-uniform electronic properties of crystals resulting from anisotropic dopant segregation during bulk growth. When the segregation coefficient of dopant impurities changes notably across the melt/solid interface of a growing crystal the result is non-uniform electronic properties across wafers made from these crystals. The effect is more pronounced in InSb crystals grown on the (111) axis compared with other orientations and crystal systems. FPA devices made on these wafers suffer costly yield hits due to inconsistent device response and performance. Historically, InSb crystal growers have grown approximately 9-19 degree off-axis from the (111) to avoid the facet effect and produced wafers with improved uniformity of electronic properties. It has been shown by researchers in the 1960s that control of the facet effect can produce uniform small diameter crystals. In this paper, we share results employing a process that controls the facet effect when growing large diameter crystals from which 4, 5, and 6" wafers can be manufactured. The process change resulted in an increase in wafers yielded per crystal by several times, all with high crystal quality and uniform electronic properties. Since the crystals are grown on the (111) axis, manufacturing (111) oriented wafers is straightforward with standard semiconductor equipment and processes common to the high-volume silicon wafer industry. These benefits result in significant manufacturing cost savings and increased value to our customers.

Review of Portable and Low-Cost Sensors for the Ambient Air Monitoring of Benzene and Other Volatile Organic Compounds

PubMed Central

Kok, Gertjan; Persijn, Stefan; Sauerwald, Tilman

2017-01-01

This article presents a literature review of sensors for the monitoring of benzene in ambient air and other volatile organic compounds. Combined with information provided by stakeholders, manufacturers and literature, the review considers commercially available sensors, including PID-based sensors, semiconductor (resistive gas sensors) and portable on-line measuring devices as for example sensor arrays. The bibliographic collection includes the following topics: sensor description, field of application at fixed sites, indoor and ambient air monitoring, range of concentration levels and limit of detection in air, model descriptions of the phenomena involved in the sensor detection process, gaseous interference selectivity of sensors in complex VOC matrix, validation data in lab experiments and under field conditions. PMID:28657595

Review of Portable and Low-Cost Sensors for the Ambient Air Monitoring of Benzene and Other Volatile Organic Compounds.

PubMed

Spinelle, Laurent; Gerboles, Michel; Kok, Gertjan; Persijn, Stefan; Sauerwald, Tilman

2017-06-28

This article presents a literature review of sensors for the monitoring of benzene in ambient air and other volatile organic compounds. Combined with information provided by stakeholders, manufacturers and literature, the review considers commercially available sensors, including PID-based sensors, semiconductor (resistive gas sensors) and portable on-line measuring devices as for example sensor arrays. The bibliographic collection includes the following topics: sensor description, field of application at fixed sites, indoor and ambient air monitoring, range of concentration levels and limit of detection in air, model descriptions of the phenomena involved in the sensor detection process, gaseous interference selectivity of sensors in complex VOC matrix, validation data in lab experiments and under field conditions.

Demonstration of Al:ZnO as a plasmonic component for near-infrared metamaterials

PubMed Central

Naik, Gururaj V.; Liu, Jingjing; Kildishev, Alexander V.; Shalaev, Vladimir M.; Boltasseva, Alexandra

2012-01-01

Noble metals such as gold and silver are conventionally used as the primary plasmonic building blocks of optical metamaterials. Making subwavelength-scale structural elements from these metals not only seriously limits the optical performance of a device due to high absorption, it also substantially complicates the manufacturing process of nearly all metamaterial devices in the optical wavelength range. As an alternative to noble metals, we propose to use heavily doped oxide semiconductors that offer both functional and fabrication advantages in the near-infrared wavelength range. In this letter, we replace a metal with aluminum-doped zinc oxide as a new plasmonic material and experimentally demonstrate negative refraction in an Al:ZnO/ZnO metamaterial in the near-infrared range. PMID:22611188

Unity quantum yield of photogenerated charges and band-like transport in quantum-dot solids.

PubMed

Talgorn, Elise; Gao, Yunan; Aerts, Michiel; Kunneman, Lucas T; Schins, Juleon M; Savenije, T J; van Huis, Marijn A; van der Zant, Herre S J; Houtepen, Arjan J; Siebbeles, Laurens D A

2011-09-25

Solid films of colloidal quantum dots show promise in the manufacture of photodetectors and solar cells. These devices require high yields of photogenerated charges and high carrier mobilities, which are difficult to achieve in quantum-dot films owing to a strong electron-hole interaction and quantum confinement. Here, we show that the quantum yield of photogenerated charges in strongly coupled PbSe quantum-dot films is unity over a large temperature range. At high photoexcitation density, a transition takes place from hopping between localized states to band-like transport. These strongly coupled quantum-dot films have electrical properties that approach those of crystalline bulk semiconductors, while retaining the size tunability and cheap processing properties of colloidal quantum dots.

On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

PubMed

Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

2014-07-10

Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2006-03-01

Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

High-resolution inkjet printing of all-polymer transistor circuits.

PubMed

Sirringhaus, H; Kawase, T; Friend, R H; Shimoda, T; Inbasekaran, M; Wu, W; Woo, E P

2000-12-15

Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and self-organizing semiconductors. We show that the use of substrate surface energy patterning to direct the flow of water-based conducting polymer inkjet droplets enables high-resolution definition of practical channel lengths of 5 micrometers. High mobilities of 0.02 square centimeters per volt second and on-off current switching ratios of 10(5) were achieved.

CMOS Optoelectronic Lock-In Amplifier With Integrated Phototransistor Array.

PubMed

An Hu; Chodavarapu, Vamsy P

2010-10-01

We describe the design and development of an optoelectronic lock-in amplifier (LIA) for optical sensing and spectroscopy applications. The prototype amplifier is fabricated using Taiwan Semiconductor Manufacturing Co. complementary metal-oxide semiconductor 0.35-μm technology and uses a phototransistor array (total active area is 400 μm × 640μm) to convert the incident optical signals into electrical currents. The photocurrents are then converted into voltage signals using a transimpedance amplifier for subsequent convenient signal processing by the LIA circuitry. The LIA is optimized to be operational at 20-kHz modulation frequency but is operational in the frequency range from 13 kHz to 25 kHz. The system is tested with a light-emitting diode (LED) as the light source. The noise and signal distortions are suppressed with filters and a phase-locked loop (PLL) implemented in the LIA. The output dc voltage of the LIA is proportional to the incident optical power. The minimum measured dynamic reserve and sensitivity are 1.31 dB and 34 mV/μW, respectively. The output versus input relationship has shown good linearity. The LIA consumes an average power of 12.79 mW with a 3.3-V dc power supply.

A large-area wireless power-transmission sheet using printed organic transistors and plastic MEMS switches.

PubMed

Sekitani, Tsuyoshi; Takamiya, Makoto; Noguchi, Yoshiaki; Nakano, Shintaro; Kato, Yusaku; Sakurai, Takayasu; Someya, Takao

2007-06-01

The electronics fields face serious problems associated with electric power; these include the development of ecologically friendly power-generation systems and ultralow-power-consuming circuits. Moreover, there is a demand for developing new power-transmission methods in the imminent era of ambient electronics, in which a multitude of electronic devices such as sensor networks will be used in our daily life to enhance security, safety and convenience. We constructed a sheet-type wireless power-transmission system by using state-of-the-art printing technologies using advanced electronic functional inks. This became possible owing to recent progress in organic semiconductor technologies; the diversity of chemical syntheses and processes on organic materials has led to a new class of organic semiconductors, dielectric layers and metals with excellent electronic functionalities. The new system directly drives electronic devices by transmitting power of the order of tens of watts without connectors, thereby providing an easy-to-use and reliable power source. As all of the components are manufactured on plastic films, it is easy to place the wireless power-transmission sheet over desks, floors, walls and any other location imaginable.

Developments in optical modeling methods for metrology

NASA Astrophysics Data System (ADS)

Davidson, Mark P.

1999-06-01

Despite the fact that in recent years the scanning electron microscope has come to dominate the linewidth measurement application for wafer manufacturing, there are still many applications for optical metrology and alignment. These include mask metrology, stepper alignment, and overlay metrology. Most advanced non-optical lithographic technologies are also considering using topics for alignment. In addition, there have been a number of in-situ technologies proposed which use optical measurements to control one aspect or another of the semiconductor process. So optics is definitely not dying out in the semiconductor industry. In this paper a description of recent advances in optical metrology and alignment modeling is presented. The theory of high numerical aperture image simulation for partially coherent illumination is discussed. The implications of telecentric optics on the image simulation is also presented. Reciprocity tests are proposed as an important measure of numerical accuracy. Diffraction efficiencies for chrome gratings on reticles are one good way to test Kirchoff's approximation as compared to rigorous calculations. We find significant differences between the predictions of Kirchoff's approximation and rigorous methods. The methods for simulating brightfield, confocal, and coherence probe microscope imags are outlined, as are methods for describing aberrations such as coma, spherical aberration, and illumination aperture decentering.

Does technology acceleration equate to mask cost acceleration?

NASA Astrophysics Data System (ADS)

Trybula, Walter J.; Grenon, Brian J.

2003-06-01

The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor sup-plier community and the manufacturers. INTERNATIONAL SEMATECH has revaluated the projected cost of advanced technology masks. Building on the methodology developed in 1996 for mask costs, this work provided a critical review of mask yields and factors relating to the manufacture of photolithography masks. The impact of the yields provided insight into the learning curve for leading edge mask manufac-turing. The projected mask set cost was surprising, and the ability to provide first and second year cost estimates provided additional information on technology introduction. From this information, the impact of technology acceleration can be added to the projected yields to evaluate the impact on mask costs.

Exploring synchrotron radiation capabilities: The ALS-Intel CRADA

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gozzo, F.; Cossy-Favre, A; Trippleet, B.

1997-04-01

Synchrotron radiation spectroscopy and spectromicroscopy were applied, at the Advanced Light Source, to the analysis of materials and problems of interest to the commercial semiconductor industry. The authors discuss some of the results obtained at the ALS using existing capabilities, in particular the small spot ultra-ESCA instrument on beamline 7.0 and the AMS (Applied Material Science) endstation on beamline 9.3.2. The continuing trend towards smaller feature size and increased performance for semiconductor components has driven the semiconductor industry to invest in the development of sophisticated and complex instrumentation for the characterization of microstructures. Among the crucial milestones established by themore » Semiconductor Industry Association are the needs for high quality, defect free and extremely clean silicon wafers, very thin gate oxides, lithographies near 0.1 micron and advanced material interconnect structures. The requirements of future generations cannot be met with current industrial technologies. The purpose of the ALS-Intel CRADA (Cooperative Research And Development Agreement) is to explore, compare and improve the utility of synchrotron-based techniques for practical analysis of substrates of interest to semiconductor chip manufacturing. The first phase of the CRADA project consisted in exploring existing ALS capabilities and techniques on some problems of interest. Some of the preliminary results obtained on Intel samples are discussed here.« less

Carbon Nanotube Flexible and Stretchable Electronics

NASA Astrophysics Data System (ADS)

Cai, Le; Wang, Chuan

2015-08-01

The low-cost and large-area manufacturing of flexible and stretchable electronics using printing processes could radically change people's perspectives on electronics and substantially expand the spectrum of potential applications. Examples range from personalized wearable electronics to large-area smart wallpapers and from interactive bio-inspired robots to implantable health/medical apparatus. Owing to its one-dimensional structure and superior electrical property, carbon nanotube is one of the most promising material platforms for flexible and stretchable electronics. Here in this paper, we review the recent progress in this field. Applications of single-wall carbon nanotube networks as channel semiconductor in flexible thin-film transistors and integrated circuits, as stretchable conductors in various sensors, and as channel material in stretchable transistors will be discussed. Lastly, state-of-the-art advancement on printing process, which is ideal for large-scale fabrication of flexible and stretchable electronics, will also be reviewed in detail.

Carbon Nanotube Flexible and Stretchable Electronics.

PubMed

Cai, Le; Wang, Chuan

2015-12-01

The low-cost and large-area manufacturing of flexible and stretchable electronics using printing processes could radically change people's perspectives on electronics and substantially expand the spectrum of potential applications. Examples range from personalized wearable electronics to large-area smart wallpapers and from interactive bio-inspired robots to implantable health/medical apparatus. Owing to its one-dimensional structure and superior electrical property, carbon nanotube is one of the most promising material platforms for flexible and stretchable electronics. Here in this paper, we review the recent progress in this field. Applications of single-wall carbon nanotube networks as channel semiconductor in flexible thin-film transistors and integrated circuits, as stretchable conductors in various sensors, and as channel material in stretchable transistors will be discussed. Lastly, state-of-the-art advancement on printing process, which is ideal for large-scale fabrication of flexible and stretchable electronics, will also be reviewed in detail.

Composition, apparatus, and process, for sorption of gaseous compounds of group II-VII elements

DOEpatents

Tom, Glenn M.; McManus, James V.; Luxon, Bruce A.

1991-08-06

Scavenger compositions are disclosed, which have utility for effecting the sorptive removal of hazardous gases containing Group II-VII elements of the Periodic Table, such as are widely encountered in the manufacture of semiconducting materials and semiconductor devices. Gas sorption processes including the contacting of Group II-VII gaseous compounds with such scavenger compositions are likewise disclosed, together with critical space velocity contacting conditions pertaining thereto. Further described are gas contacting apparatus, including mesh structures which may be deployed in gas contacting vessels containing such scavenger compositions, to prevent solids from being introduced to or discharged from the contacting vessel in the gas stream undergoing treatment. A reticulate heat transfer structure also is disclosed, for dampening localized exothermic reaction fronts when gas mixtures comprising Group II-VII constituents are contacted with the scavenger compositions in bulk sorption contacting vessels according to the invention.

Preparation of a semiconductor thin film

DOEpatents

Pehnt, Martin; Schulz, Douglas L.; Curtis, Calvin J.; Ginley, David S.

1998-01-01

A process for the preparation of a semiconductor film. The process comprises depositing nanoparticles of a semiconductor material onto a substrate whose surface temperature during nanoparticle deposition thereon is sufficient to cause substantially simultaneous fusion of the nanoparticles to thereby coalesce with each other and effectuate film growth.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Jr., Marcel; Alivisatos, Paul

2006-09-05

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule. The compound is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. subsequent exposure to excitation energy will excite the semiconductor nanocrystal in the probe causing the emission of electromagnetic radiation. Further described are processes for respectively: making the luminescent semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon [Pinole, CA; Bruchez, Jr., Marcel; Alivisatos, Paul [Oakland, CA

2004-03-02

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule. The compound is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. Subsequent exposure to excitation energy will excite the semiconductor nanocrystal in the probe, causing the emission of electromagnetic radiation. Further described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Jr., Marcel; Alivisatos, Paul

2005-08-09

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule. The compound is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. Subsequent exposure to excitation energy will excite the semiconductor nanocrystal in the probe causing the emission of electromagnetic radiation. Further described are processes for respectively: making the luminescent semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Organo luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Jr., Marcel; Alivisatos, Paul

2002-01-01

A semiconductor nanocrystal compound is described capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affity molecule. The compound is linked to an affinity molecule to form a semiconductor nanocrystal probe capable of bonding with a detectable substance. Subsequent exposure to excitation energy will excite the semiconductor nanocrystal in he probe, causing the emission of electromagnetic radiation. Further described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and using the probe to determine the presence of a detectable substance in a material.

Semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Marcel; Alivisatos, Paul

2014-01-28

A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with one or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe.

Semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Weiss, Shimon; Bruchez, Marcel; Alivisatos, Paul A.

2016-12-27

A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with onemore » or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe.« less

ENVIRONMENTAL RESEARCH BRIEF: WASTE REDUCTION ACTIVITIES AND OPTIONS FOR A MANUFACTURER OF SYSTEMS TO PRODUCE SEMICONDUCTORS.

EPA Science Inventory

The U.S. Environmental Protection Agency (EPA) funded a project with the New Jersey Department of Environmental Protection and Energy (NJDEPE) to assist in conducting waste minimization assessments at thirty small- to medium-sized businesses in the state of New Jersey. ne of the ...

40 CFR Table I-12 to Subpart I of... - Default Emission Factors (1-Uij) for Gas Utilization Rates (Uij) and By-Product Formation Rates...

Code of Federal Regulations, 2014 CFR

2014-07-01

... Use With the Stack Test Method (300 mm and 450 mm Wafers) I Table I-12 to Subpart I of Part 98... (Bijk) for Semiconductor Manufacturing for Use With the Stack Test Method (300 mm and 450 mm Wafers...

40 CFR Table I-11 to Subpart I of... - Default Emission Factors (1-Uij) for Gas Utilization Rates (Uij) and By-Product Formation Rates...

Code of Federal Regulations, 2014 CFR

2014-07-01

... Use With the Stack Test Method (150 mm and 200 mm Wafers) I Table I-11 to Subpart I of Part 98... (Bijk) for Semiconductor Manufacturing for Use With the Stack Test Method (150 mm and 200 mm Wafers...

75 FR 38129 - Freescale Semiconductor, Inc., Hardware/Software Design and Manufacturing A Including On-Site...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-07-01

...Logic, Inc., Austin, TX; Amended Certification Regarding Eligibility To Apply for Worker Adjustment..., Design Solutions, Inc., Veriseo, SilconElite and MicroLogic, Inc. were employed on-site at the Austin...., Veriseo, SiliconElite and MicroLogic, Inc. working on-site at the Austin, Texas, location of Freescale...

An Industry Viewpoint on Electron Energy Distribution Function Control

NASA Astrophysics Data System (ADS)

Ventzek, Peter

2011-10-01

It is trite to note that plasmas play a key role in industrial technology. Lighting, laser, film coating and now medical technology require plasma science for their sustenance. One field stands out by virtue of its economic girth and impact. Semiconductor manufacturing and process science enabling its decades of innovation owe significant debt to progress in low temperature plasma science. Today, technology requires atomic level control from plasmas. Mere layers of atoms delineate good and bad device performance. While plasma sources meet nanoscale specifications over 100s cm scale dimensions, achieving atomic level control from plasmas is hindered by the absence of direct control of species velocity distribution functions. EEDF control translates to precise control of species flux and velocities at surfaces adjacent to the plasma. Electron energy distribution function (eedf) control is a challenge that, if successfully met, will have a huge impact on nanoscale device manufacturing. This lunchtime talk will attempt to provide context to the research advances presented at this Workshop. Touched on will be areas of new opportunity and the risks associated with missing these opportunities.

Metal-Halide Perovskite Transistors for Printed Electronics: Challenges and Opportunities.

PubMed

Lin, Yen-Hung; Pattanasattayavong, Pichaya; Anthopoulos, Thomas D

2017-12-01

Following the unprecedented rise in photovoltaic power conversion efficiencies during the past five years, metal-halide perovskites (MHPs) have emerged as a new and highly promising class of solar-energy materials. Their extraordinary electrical and optical properties combined with the abundance of the raw materials, the simplicity of synthetic routes, and processing versatility make MHPs ideal for cost-efficient, large-volume manufacturing of a plethora of optoelectronic devices that span far beyond photovoltaics. Herein looks beyond current applications in the field of energy, to the area of large-area electronics using MHPs as the semiconductor material. A comprehensive overview of the relevant fundamental material properties of MHPs, including crystal structure, electronic states, and charge transport, is provided first. Thereafter, recent demonstrations of MHP-based thin-film transistors and their application in logic circuits, as well as bi-functional devices such as light-sensing and light-emitting transistors, are discussed. Finally, the challenges and opportunities in the area of MHPs-based electronics, with particular emphasis on manufacturing, stability, and health and environmental concerns, are highlighted. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Sub-cell turning to accomplish micron-level alignment of precision assemblies

NASA Astrophysics Data System (ADS)

Kumler, James J.; Buss, Christian

2017-08-01

Higher performance expectations for complex optical systems demand tighter alignment requirements for lens assembly alignment. In order to meet diffraction limited imaging performance over wide spectral bands across the UV and visible wavebands, new manufacturing approaches and tools must be developed if the optical systems will be produced consistently in volume production. This is especially applicable in the field of precision microscope objectives for life science, semiconductor inspection and laser material processing systems. We observe a rising need for the improvement in the optical imaging performance of objective lenses. The key challenge lies in the micron-level decentration and tilt of each lens element. One solution for the production of high quality lens systems is sub-cell assembly with alignment turning. This process relies on an automatic alignment chuck to align the optical axis of a mounted lens to the spindle axis of the machine. Subsequently, the mount is cut with diamond tools on a lathe with respect to the optical axis of the mount. Software controlled integrated measurement technology ensures highest precision. In addition to traditional production processes, further dimensions can be controlled in a very precise manner, e.g. the air gaps between the lenses. Using alignment turning simplifies further alignment steps and reduces the risk of errors. This paper describes new challenges in microscope objective design and manufacturing, and addresses difficulties with standard production processes. A new measurement and alignment technique is described, and strengths and limitations are outlined.

ROI on yield data analysis systems through a business process management strategy

NASA Astrophysics Data System (ADS)

Rehani, Manu; Strader, Nathan; Hanson, Jeff

2005-05-01

The overriding motivation for yield engineering is profitability. This is achieved through application of yield management. The first application is to continually reduce waste in the form of yield loss. New products, new technologies and the dynamic state of the process and equipment keep introducing new ways to cause yield loss. In response, the yield management efforts have to continually come up with new solutions to minimize it. The second application of yield engineering is to aid in accurate product pricing. This is achieved through predicting future results of the yield engineering effort. The more accurate the yield prediction, the more accurate the wafer start volume, the more accurate the wafer pricing. Another aspect of yield prediction pertains to gauging the impact of a yield problem and predicting how long that will last. The ability to predict such impacts again feeds into wafer start calculations and wafer pricing. The question then is that if the stakes on yield management are so high why is it that most yield management efforts are run like science and engineering projects and less like manufacturing? In the eighties manufacturing put the theory of constraints1 into practice and put a premium on stability and predictability in manufacturing activities, why can't the same be done for yield management activities? This line of introspection led us to define and implement a business process to manage the yield engineering activities. We analyzed the best known methods (BKM) and deployed a workflow tool to make them the standard operating procedure (SOP) for yield managment. We present a case study in deploying a Business Process Management solution for Semiconductor Yield Engineering in a high-mix ASIC environment. We will present a description of the situation prior to deployment, a window into the development process and a valuation of the benefits.

Materials and processing approaches for foundry-compatible transient electronics

PubMed Central

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-01-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries. PMID:28652373

Acoustic biosensors.

PubMed

Fogel, Ronen; Limson, Janice; Seshia, Ashwin A

2016-06-30

Resonant and acoustic wave devices have been researched for several decades for application in the gravimetric sensing of a variety of biological and chemical analytes. These devices operate by coupling the measurand (e.g. analyte adsorption) as a modulation in the physical properties of the acoustic wave (e.g. resonant frequency, acoustic velocity, dissipation) that can then be correlated with the amount of adsorbed analyte. These devices can also be miniaturized with advantages in terms of cost, size and scalability, as well as potential additional features including integration with microfluidics and electronics, scaled sensitivities associated with smaller dimensions and higher operational frequencies, the ability to multiplex detection across arrays of hundreds of devices embedded in a single chip, increased throughput and the ability to interrogate a wider range of modes including within the same device. Additionally, device fabrication is often compatible with semiconductor volume batch manufacturing techniques enabling cost scalability and a high degree of precision and reproducibility in the manufacturing process. Integration with microfluidics handling also enables suitable sample pre-processing/separation/purification/amplification steps that could improve selectivity and the overall signal-to-noise ratio. Three device types are reviewed here: (i) bulk acoustic wave sensors, (ii) surface acoustic wave sensors, and (iii) micro/nano-electromechanical system (MEMS/NEMS) sensors. © 2016 The Author(s). Published by Portland Press Limited on behalf of the Biochemical Society.

Automated imprint mask cleaning for step-and-flash imprint lithography

NASA Astrophysics Data System (ADS)

Singh, Sherjang; Chen, Ssuwei; Selinidis, Kosta; Fletcher, Brian; McMackin, Ian; Thompson, Ecron; Resnick, Douglas J.; Dress, Peter; Dietze, Uwe

2009-03-01

Step-and-Flash Imprint Lithography (S-FIL) is a promising lithography strategy for semiconductor manufacturing at device nodes below 32nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by-field ink jet dispense of a low viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub 40nm CD lithography methods, the resulting high resolution, high throughput through clustering, 3D patterning capability, low process complexity, and low cost of ownership (CoO) of S-FIL makes it a widely accepted technology for patterned media as well as a promising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid risk of repeated printing of defects. The development of mask cleaning processes capable of removing particles adhered to the mask surface without damaging the mask is critical to meet high volume manufacturing requirements. In this paper we have presented various methods of residual (cross-linked) resist removal and final imprint mask cleaning demonstrated on the HamaTech MaskTrack automated mask cleaning system. Conventional and non-conventional (acid free) methods of particle removal have been compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

Progress in mask replication using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Selinidis, Kosta S.; Brooks, Cynthia B.; Doyle, Gary F.; Brown, Laura; Jones, Chris; Imhof, Joseph; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2011-04-01

The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 104 - 105imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and processes specifically for semiconductor applications. The requirements needed for semiconductors dictate the need for a well defined form factor for both master and replica masks which is also compatible with the existing mask infrastructure established for the 6025 semi standard, 6" x 6" x 0.25" photomasks. Complying with this standard provides the necessary tooling needed for mask fabrication processes, cleaning, metrology, and inspection. The replica form factor has additional features specific to imprinting such as a pre-patterned mesa. A PerfectaTM MR5000 mask replication tool has been developed specifically to pattern replica masks from an e-beam written master. The system specifications include a throughput of four replicas per hour with an added image placement component of 5nm, 3sigma and a critical dimension uniformity error of less than 1nm, 3sigma. A new process has been developed to fabricate replicas with high contrast alignment marks so that designs for imprint can fit within current device layouts and maximize the usable printed area on the wafer. Initial performance results of this marks are comparable to the baseline fused silica align marks.

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Preparation of a semiconductor thin film

DOEpatents

Pehnt, M.; Schulz, D.L.; Curtis, C.J.; Ginley, D.S.

1998-01-27

A process is disclosed for the preparation of a semiconductor film. The process comprises depositing nanoparticles of a semiconductor material onto a substrate whose surface temperature during nanoparticle deposition thereon is sufficient to cause substantially simultaneous fusion of the nanoparticles to thereby coalesce with each other and effectuate film growth.

Quantitative evaluation of manufacturability and performance for ILT produced mask shapes using a single-objective function

NASA Astrophysics Data System (ADS)

Choi, Heon; Wang, Wei-long; Kallingal, Chidam

2015-03-01

The continuous scaling of semiconductor devices is quickly outpacing the resolution improvements of lithographic exposure tools and processes. This one-sided progression has pushed optical lithography to its limits, resulting in the use of well-known techniques such as Sub-Resolution Assist Features (SRAF's), Source-Mask Optimization (SMO), and double-patterning, to name a few. These techniques, belonging to a larger category of Resolution Enhancement Techniques (RET), have extended the resolution capabilities of optical lithography at the cost of increasing mask complexity, and therefore cost. One such technique, called Inverse Lithography Technique (ILT), has attracted much attention for its ability to produce the best possible theoretical mask design. ILT treats the mask design process as an inverse problem, where the known transformation from mask to wafer is carried out backwards using a rigorous mathematical approach. One practical problem in the application of ILT is the resulting contour-like mask shapes that must be "Manhattanized" (composed of straight edges and 90-deg corners) in order to produce a manufacturable mask. This conversion process inherently degrades the mask quality as it is a departure from the "optimal mask" represented by the continuously curved shapes produced by ILT. However, simpler masks composed of longer straight edges reduce the mask cost as it lowers the shot count and saves mask writing time during mask fabrication, resulting in a conflict between manufacturability and performance for ILT produced masks1,2. In this study, various commonly used metrics will be combined into an objective function to produce a single number to quantitatively measure a particular ILT solution's ability to balance mask manufacturability and RET performance. Several metrics that relate to mask manufacturing costs (i.e. mask vertex count, ILT computation runtime) are appropriately weighted against metrics that represent RET capability (i.e. process-variation band, edge-placement-error) in order to reflect the desired practical balance. This well-defined scoring system allows direct comparison of several masks with varying degrees of complexities. Using this method, ILT masks produced with increasing mask constraints will be compared, and it will be demonstrated that using the smallest minimum width for mask shapes does not always produce the optimal solution.

The chemical deposition of semiconductor thin-films for photovoltaic devices

NASA Astrophysics Data System (ADS)

Breen, Marc Louis

Initially, possible precursors to metal sulfide films formed by metal-organic chemical vapor deposition (MOCVD), the standard commercial technique for manufacturing photovoltaic semiconductors, were synthesized. Triple-junction GaInP 2/GaAs/Ge solar cells, prepared by this method, were studied to understand how chemical properties and material defects can effect the performance of photovoltaic devices. Finally, novel methods for the low-temperature, solution growth of CdS, CdSe, and CuInSe2 photovoltaic materials were targeted which will reduce manufacturing costs and increase the economic feasibility of solar energy conversion. A series of dialkyldithiocarbamate copper, gallium and indium compounds were studied as possible metal sulfide MOCVD precursors. Metal powders were oxidized by dialkylthiurams in 3- or 4-methylpyridine using standard techniques for handling air and moisture-sensitive compounds. Metal chlorides reacted directly with the sodium dialkyldithiocarbamate salts. In these complexes, the metal was found in a roughly octahedral orientation, surrounded by dithiocarbamate ligands and/or solvent molecules. Triple-junction GaInP2/GaAs/Ge cells were composed of thin-films of GaInP2 and GaAs grown monolithically on top of a germanium substrate. Each layer of semiconductor material had a different bandgap and absorbed a different portion of the solar spectrum, thus improving the overall efficiency of the cell. Work focused on dark current-voltage behavior which is known to limit solar cell open-circuit voltage, fill factor, and conversion efficiency. Cells were studied using microscopic and spectroscopic techniques to correlate the effect of physical defects in the materials with poor performance of the devices as evaluated through current vs. voltage measurements. Films of US and CdSe were readily prepared in solution through an "ion-by-ion" deposition of Cd2+ and S2- (or Se 2-) generated from the slow hydrolysis of thiourea (or dimethylthiourea). The bath chemistry was carefully controlled by the adjustment of pH to slow hydrolysis and with chelating agents to sequester the cadmium ions. Triethanolamine and ethylenediamine were both effective chelators with the latter producing thicker, clearer films. Finally, US films were grown over electrodeposited CuInSe2 to form working photovoltaic devices. In summary, contributions were made which (a) advance current methods for manufacturing photovoltaic semiconductors and (b) offer an alternative route to producing new forms of thin-film solar cell devices.

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 μm CMOS Process

PubMed Central

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

PubMed Central

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature. PMID:22399944

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique.

PubMed

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature.

Micro ethanol sensors with a heater fabricated using the commercial 0.18 μm CMOS process.

PubMed

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-09-25

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm.

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

PubMed Central

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

PubMed

Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

2003-12-01

Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

The National Si-Soft Project

NASA Astrophysics Data System (ADS)

Chang, Chun-Yen; Trappey, Charles V.

2003-06-01

Taiwan's electronics industry emerged in the 1960s with the creation of a small but well planned integrated circuit (IC) packaging industry. This industry investment led to bolder investments in research, laboratories, and the island's first semiconductor foundries in the 1980s. Following the success of the emerging IC manufacturers and design houses, hundreds of service firms and related industries (software, legal services, substrate, chemical, and test firms among others) opened for business and completed Taiwan's IC manufacturing supply chain. The challenge for Taiwan's electronics industry is to take the lead in the design, manufacture, and marketing of name brand electronic products. This paper introduces the Si-Soft (silicon software) Project, a national initiative that builds on Taiwan's achievements in manufacturing (referred to as Si-Hard or silicon hardware) to launch a new wave of companies. These firms will contribute to the core underlying technology (intellectual property) used in the creation of electronic products.

Context-based automated defect classification system using multiple morphological masks

DOEpatents

Gleason, Shaun S.; Hunt, Martin A.; Sari-Sarraf, Hamed

2002-01-01

Automatic detection of defects during the fabrication of semiconductor wafers is largely automated, but the classification of those defects is still performed manually by technicians. This invention includes novel digital image analysis techniques that generate unique feature vector descriptions of semiconductor defects as well as classifiers that use these descriptions to automatically categorize the defects into one of a set of pre-defined classes. Feature extraction techniques based on multiple-focus images, multiple-defect mask images, and segmented semiconductor wafer images are used to create unique feature-based descriptions of the semiconductor defects. These feature-based defect descriptions are subsequently classified by a defect classifier into categories that depend on defect characteristics and defect contextual information, that is, the semiconductor process layer(s) with which the defect comes in contact. At the heart of the system is a knowledge database that stores and distributes historical semiconductor wafer and defect data to guide the feature extraction and classification processes. In summary, this invention takes as its input a set of images containing semiconductor defect information, and generates as its output a classification for the defect that describes not only the defect itself, but also the location of that defect with respect to the semiconductor process layers.

Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

NASA Astrophysics Data System (ADS)

Hohle, Christoph; Choi, Kang-Hoon; Gutsch, Manuela; Hanisch, Norbert; Seidel, Robert; Steidel, Katja; Thrun, Xaver; Werner, Thomas

2015-03-01

Electron beam direct write lithography (EBDW) potentially offers advantages for low-volume semiconductor manufacturing, rapid prototyping or design verification due to its high flexibility without the need of costly masks. However, the integration of this advanced patterning technology into complex CMOS manufacturing processes remains challenging. The low throughput of today's single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes. In the past we successfully proved that potential degradation effects of high-k materials or ULK shrink can be neglected and were excluded by demonstrating integrated electrical results of 28nm node transistor and BEOL performance following 50kV electron beam dry exposure [3]. Here we will give an update on the integration of EBDW in the 300mm CMOS manufacturing processes of advanced integrated circuits at the 28nm SRAM node of GLOBALFOUNDRIES Dresden. The work is an update to what has been previously published [4]. E-beam patterning results of BEOL full chip metal and via layers with a dual damascene integration scheme using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMSCNT are demonstrated. For the patterning of the Metal layer a Mix & Match concept based on the sequence litho - etch -litho -etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. Etch results are shown and compared to the POR. Results are also shown on overlay performance and optimized e-Beam exposure time using most advanced data prep solutions and resist processes. The patterning results have been verified using fully integrated electrical measurement of metal lines and vias on wafer level. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.

Evaluation of selected chemical processes for production of low-cost silicon. Quarterly progress report, 15 Dec 1975--31 Mar 1976

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blocher, J.M. Jr; Browning, M.F.; Wilson, W.J.

1976-04-08

Plant construction costs and manufacturing costs were estimmated for the production of solar-grade silicon by the reduction of silicon tetrachloride in a fluidized bed of seed particles, and several modifications of the iodide process using either thermal decomposition on heated filaments (rods) or hydrogen reduction in a fluidized bed of seed particles. Energy consumption data for the zinc reduction process and each of the iodide process options are given and all appear to be acceptable from the standpoint of energy pay back. Information is presented on the experimental zinc reduction of SiCl4 and electrolytic recovery of zinc from ZnCl2. Allmore » of the experimental work performed thus far has supported the initial assumption as to technical feasibility of producing semiconductor silicon by the zinc reduction or iodide processes proposed. The results of a more thorough thermodynamic evaluation of the iodination of silicon oxide/carbon mixtures are presented which explain apparent inconsistencies in an earlier cursory examination of the system.« less

Microminiature thermionic converters

DOEpatents

King, Donald B.; Sadwick, Laurence P.; Wernsman, Bernard R.

2001-09-25

Microminiature thermionic converts (MTCs) having high energy-conversion efficiencies and variable operating temperatures. Methods of manufacturing those converters using semiconductor integrated circuit fabrication and micromachine manufacturing techniques are also disclosed. The MTCs of the invention incorporate cathode to anode spacing of about 1 micron or less and use cathode and anode materials having work functions ranging from about 1 eV to about 3 eV. Existing prior art thermionic converter technology has energy conversion efficiencies ranging from 5-15%. The MTCs of the present invention have maximum efficiencies of just under 30%, and thousands of the devices can be fabricated at modest costs.

7/5nm logic manufacturing capabilities and requirements of metrology

NASA Astrophysics Data System (ADS)

Bunday, Benjamin; Bello, A. F.; Solecky, Eric; Vaid, Alok

2018-03-01

This paper will provide an update to previous works [2][4][9] to our view of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry, concentrating on logic technology for foundries. First, we will review of the needs of patterned defect, critical dimensional (CD/3D), overlay and films metrology, and present the extensive list of applications for which metrology solutions are needed. We will then update the industry's progress towards addressing gating technical limits of the most important of these metrology solutions, highlighting key metrology technology gaps requiring industry attention and investment.

Optical processing for semiconductor device fabrication

NASA Technical Reports Server (NTRS)

Sopori, Bhushan L.

1994-01-01

A new technique for semiconductor device processing is described that uses optical energy to produce local heating/melting in the vicinity of a preselected interface of the device. This process, called optical processing, invokes assistance of photons to enhance interface reactions such as diffusion and melting, as compared to the use of thermal heating alone. Optical processing is performed in a 'cold wall' furnace, and requires considerably lower energies than furnace or rapid thermal annealing. This technique can produce some device structures with unique properties that cannot be produced by conventional thermal processing. Some applications of optical processing involving semiconductor-metal interfaces are described.

Solution-Processed Donor-Acceptor Polymer Nanowire Network Semiconductors For High-Performance Field-Effect Transistors

PubMed Central

Lei, Yanlian; Deng, Ping; Li, Jun; Lin, Ming; Zhu, Furong; Ng, Tsz-Wai; Lee, Chun-Sing; Ong, Beng S.

2016-01-01

Organic field-effect transistors (OFETs) represent a low-cost transistor technology for creating next-generation large-area, flexible and ultra-low-cost electronics. Conjugated electron donor-acceptor (D-A) polymers have surfaced as ideal channel semiconductor candidates for OFETs. However, high-molecular weight (MW) D-A polymer semiconductors, which offer high field-effect mobility, generally suffer from processing complications due to limited solubility. Conversely, the readily soluble, low-MW D-A polymers give low mobility. We report herein a facile solution process which transformed a lower-MW, low-mobility diketopyrrolopyrrole-dithienylthieno[3,2-b]thiophene (I) into a high crystalline order and high-mobility semiconductor for OFETs applications. The process involved solution fabrication of a channel semiconductor film from a lower-MW (I) and polystyrene blends. With the help of cooperative shifting motion of polystyrene chain segments, (I) readily self-assembled and crystallized out in the polystyrene matrix as an interpenetrating, nanowire semiconductor network, providing significantly enhanced mobility (over 8 cm2V−1s−1), on/off ratio (107), and other desirable field-effect properties that meet impactful OFET application requirements. PMID:27091315

Surface modification using low energy ground state ion beams

NASA Technical Reports Server (NTRS)

Chutjian, Ara (Inventor); Hecht, Michael H. (Inventor); Orient, Otto J. (Inventor)

1990-01-01

A method of effecting modifications at the surfaces of materials using low energy ion beams of known quantum state, purity, flux, and energy is presented. The ion beam is obtained by bombarding ion-generating molecules with electrons which are also at low energy. The electrons used to bombard the ion generating molecules are separated from the ions thus obtained and the ion beam is directed at the material surface to be modified. Depending on the type of ion generating molecules used, different ions can be obtained for different types of surface modifications such as oxidation and diamond film formation. One area of application is in the manufacture of semiconductor devices from semiconductor wafers.

Development of a RadFET Linear Array for Intracavitary in vivo Dosimetry During External Beam Radiotherapy and Brachytherapy

NASA Astrophysics Data System (ADS)

Price, R. A.; Benson, C.; Joyce, M. J.; Rodgers, K.

2004-08-01

We present the details of a new linear array dosimeter consisting of a chain of semiconductors mounted on an ultra-thin (50 /spl mu/m thick) flexible substrate and housed in an intracavitary catheter. The semiconductors, manufactured by NMRC Cork, have not been packaging and incorporate a passivation layer that allows them to be mounted on the substrate using flip-chip-bonding. This paper reports, for the first time, the construction of a multiple (ten) detector array suited to in vivo dosimetry in the rectum, esophagus and vagina during external beam radiotherapy, as well as being adaptable to in vivo dosimetry during brachytherapy and diagnostic radiology.

Method of physical vapor deposition of metal oxides on semiconductors

DOEpatents

Norton, David P.

2001-01-01

A process for growing a metal oxide thin film upon a semiconductor surface with a physical vapor deposition technique in a high-vacuum environment and a structure formed with the process involves the steps of heating the semiconductor surface and introducing hydrogen gas into the high-vacuum environment to develop conditions at the semiconductor surface which are favorable for growing the desired metal oxide upon the semiconductor surface yet is unfavorable for the formation of any native oxides upon the semiconductor. More specifically, the temperature of the semiconductor surface and the ratio of hydrogen partial pressure to water pressure within the vacuum environment are high enough to render the formation of native oxides on the semiconductor surface thermodynamically unstable yet are not so high that the formation of the desired metal oxide on the semiconductor surface is thermodynamically unstable. Having established these conditions, constituent atoms of the metal oxide to be deposited upon the semiconductor surface are directed toward the surface of the semiconductor by a physical vapor deposition technique so that the atoms come to rest upon the semiconductor surface as a thin film of metal oxide with no native oxide at the semiconductor surface/thin film interface. An example of a structure formed by this method includes an epitaxial thin film of (001)-oriented CeO.sub.2 overlying a substrate of (001) Ge.

An ultrasensitive bio-surrogate for nanoporous filter membrane performance metrology directed towards contamination control in microlithography applications

NASA Astrophysics Data System (ADS)

Ahmad, Farhan; Mish, Barbara; Qiu, Jian; Singh, Amarnauth; Varanasi, Rao; Bedford, Eilidh; Smith, Martin

2016-03-01

Contamination tolerances in semiconductor manufacturing processes have changed dramatically in the past two decades, reaching below 20 nm according to the guidelines of the International Technology Roadmap for Semiconductors. The move to narrower line widths drives the need for innovative filtration technologies that can achieve higher particle/contaminant removal performance resulting in cleaner process fluids. Nanoporous filter membrane metrology tools that have been the workhorse over the past decade are also now reaching limits. For example, nanoparticle (NP) challenge testing is commonly applied for assessing particle retention performance of filter membranes. Factors such as high NP size dispersity, low NP detection sensitivity, and high NP particle-filter affinity impose challenges in characterizing the next generation of nanoporous filter membranes. We report a novel bio-surrogate, 5 nm DNA-dendrimer conjugate for evaluating particle retention performance of nanoporous filter membranes. A technique capable of single molecule detection is employed to detect sparse concentration of conjugate in filter permeate, providing >1000- fold higher detection sensitivity than any existing 5 nm-sized particle enumeration technique. This bio-surrogate also offers narrow size distribution, high stability and chemical tunability. This bio-surrogate can discriminate various sub-15 nm pore-rated nanoporous filter membranes based on their particle retention performance. Due to high bio-surrogate detection sensitivity, a lower challenge concentration of bio-surrogate (as compared to other NPs of this size) can be used for filter testing, providing a better representation of customer applications. This new method should provide better understanding of the next generation filter membranes for removing defect-causing contaminants from lithography processes.

Semiconductor photoelectrochemistry

NASA Technical Reports Server (NTRS)

Buoncristiani, A. M.; Byvik, C. E.

1983-01-01

Semiconductor photoelectrochemical reactions are investigated. A model of the charge transport processes in the semiconductor, based on semiconductor device theory, is presented. It incorporates the nonlinear processes characterizing the diffusion and reaction of charge carriers in the semiconductor. The model is used to study conditions limiting useful energy conversion, specifically the saturation of current flow due to high light intensity. Numerical results describing charge distributions in the semiconductor and its effects on the electrolyte are obtained. Experimental results include: an estimate rate at which a semiconductor photoelectrode is capable of converting electromagnetic energy into chemical energy; the effect of cell temperature on the efficiency; a method for determining the point of zero zeta potential for macroscopic semiconductor samples; a technique using platinized titanium dioxide powders and ultraviolet radiation to produce chlorine, bromine, and iodine from solutions containing their respective ions; the photoelectrochemical properties of a class of layered compounds called transition metal thiophosphates; and a technique used to produce high conversion efficiency from laser radiation to chemical energy.

Unitary lens semiconductor device

DOEpatents

Lear, Kevin L.

1997-01-01

A unitary lens semiconductor device and method. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors.

IMM Solar Cell Shows Its Versatility - Continuum Magazine | NREL

Science.gov Websites

. Inventing a new type of solar cell is one thing. Setting efficiency records with it and winning major awards add to the achievement. But when one of the world's leading manufacturers of compound semiconductor thin metal foil, and the substrate that the cell was grown on is removed. One advantage of this

Transistor step stress program for JANTX2N4150

NASA Technical Reports Server (NTRS)

1979-01-01

Reliability analysis of the transistor JANTX2N4150 manufactured by General Semiconductor and Transitron is reported. The discrete devices were subjected to power and temperature step stress tests and then to electrical tests after completing the power/temperature step stress point. Control sample units were maintained for verification of the electrical parametric testing. Results are presented.

Industrial Applications of Low Temperature Plasmas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bardsley, J N

2001-03-15

The use of low temperature plasmas in industry is illustrated by the discussion of four applications, to lighting, displays, semiconductor manufacturing and pollution control. The type of plasma required for each application is described and typical materials are identified. The need to understand radical formation, ionization and metastable excitation within the discharge and the importance of surface reactions are stressed.

Elements of Emotional Intelligence that Facilitate Exper-to-Peer Tacit Knowledge Transfer

ERIC Educational Resources Information Center

Berry, Catherine M.

2010-01-01

The purpose of this quantitative study was to compare the emotional intelligence competencies of a group of technical experts with high skills in problem-solving, leadership and mentoring (Group A) with a group of technical experts with lower skills in problem solving, leadership, and mentoring (Group B) at a semiconductor manufacturing factory in…

Organo Luminescent semiconductor nanocrystal probes for biological applications and process for making and using such probes

DOEpatents

Weiss, Shimon; Bruchez, Jr., Marcel; Alivisatos, Paul

1999-01-01

A luminescent semiconductor nanocrystal compound is described which is capable of linking to an affinity molecule. The compound comprises (1) a semiconductor nanocrystal capable of emitting electromagnetic radiation (luminescing) in a narrow wavelength band and/or absorbing energy, and/or scattering or diffracting electromagnetic radiation--when excited by an electromagnetic radiation source (of narrow or broad bandwidth) or a particle beam; and (2) at least one linking agent, having a first portion linked to the semiconductor nanocrystal and a second portion capable of linking to an affinity molecule. The luminescent semiconductor nanocrystal compound is linked to an affinity molecule to form an organo luminescent semiconductor nanocrystal probe capable of bonding with a detectable substance in a material being analyzed, and capable of emitting electromagnetic radiation in a narrow wavelength band and/or absorbing, scattering, or diffracting energy when excited by an electromagnetic radiation source (of narrow or broad bandwidth) or a particle beam. The probe is stable to repeated exposure to light in the presence of oxygen and/or other radicals. Further described is a process for making the luminescent semiconductor nanocrystal compound and for making the organo luminescent semiconductor nanocrystal probe comprising the luminescent semiconductor nanocrystal compound linked to an affinity molecule capable of bonding to a detectable substance. A process is also described for using the probe to determine the presence of a detectable substance in a material.

Illuminating the Potential of Thin-Film Photovoltaics

NASA Astrophysics Data System (ADS)

Katahara, John K.

Widespread adoption of photovoltaics (PV) as an alternative electricity source will be predicated upon improvements in price performance compared to traditional power sources. Solution processing of thin-film PV is one promising way to reduce the capital expenditure (CAPEX) of manufacturing solar cells. However, it is imperative that a shift to solution processing does not come at the expense of device performance. One particularly problematic parameter for thin-film PV has historically been the open-circuit voltage (VOC ). As such, there is a pressing need for characterization tools that allow us to quickly and accurately evaluate the potential performance of solution-processed PV absorber layers. This work describes recent progress in developing photoluminescence (PL) techniques for probing optoelectronic quality in semiconductors. We present a generalized model of absorption that encompasses ideal direct-gap semiconductor absorption and various band tail models. This powerful absorption model is used to fit absolute intensity PL data and extract quasi-Fermi level splitting (maximum attainable VOC) for a variety of PV absorber technologies. This technique obviates the need for full device fabrication to get feedback on optoelectronic quality of PV absorber layers and has expedited materials exploration. We then use this absorption model to evaluate the thermodynamic losses due to different band tail cases and estimate tail losses in Cu 2ZnSn(S,Se)4 (CZTSSe). The effect of sub-bandgap absorption on PL quantum yield (PLQY) and voltage is elucidated, and new analysis techniques for extracting VOC from PLQY are validated that reduce computation time and provide us even faster feedback on material quality. We then use PL imaging to develop a mechanism describing the degradation of solution-processed CH3NH3PbI3 films under applied bias and illumination.

Inkjet printing of single-crystal films.

PubMed

Minemawari, Hiromi; Yamada, Toshikazu; Matsui, Hiroyuki; Tsutsumi, Jun'ya; Haas, Simon; Chiba, Ryosuke; Kumai, Reiji; Hasegawa, Tatsuo

2011-07-13

The use of single crystals has been fundamental to the development of semiconductor microelectronics and solid-state science. Whether based on inorganic or organic materials, the devices that show the highest performance rely on single-crystal interfaces, with their nearly perfect translational symmetry and exceptionally high chemical purity. Attention has recently been focused on developing simple ways of producing electronic devices by means of printing technologies. 'Printed electronics' is being explored for the manufacture of large-area and flexible electronic devices by the patterned application of functional inks containing soluble or dispersed semiconducting materials. However, because of the strong self-organizing tendency of the deposited materials, the production of semiconducting thin films of high crystallinity (indispensable for realizing high carrier mobility) may be incompatible with conventional printing processes. Here we develop a method that combines the technique of antisolvent crystallization with inkjet printing to produce organic semiconducting thin films of high crystallinity. Specifically, we show that mixing fine droplets of an antisolvent and a solution of an active semiconducting component within a confined area on an amorphous substrate can trigger the controlled formation of exceptionally uniform single-crystal or polycrystalline thin films that grow at the liquid-air interfaces. Using this approach, we have printed single crystals of the organic semiconductor 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C(8)-BTBT) (ref. 15), yielding thin-film transistors with average carrier mobilities as high as 16.4 cm(2) V(-1) s(-1). This printing technique constitutes a major step towards the use of high-performance single-crystal semiconductor devices for large-area and flexible electronics applications.

Suppressing molecular vibrations in organic semiconductors by inducing strain

PubMed Central

Kubo, Takayoshi; Häusermann, Roger; Tsurumi, Junto; Soeda, Junshi; Okada, Yugo; Yamashita, Yu; Akamatsu, Norihisa; Shishido, Atsushi; Mitsui, Chikahiko; Okamoto, Toshihiro; Yanagisawa, Susumu; Matsui, Hiroyuki; Takeya, Jun

2016-01-01

Organic molecular semiconductors are solution processable, enabling the growth of large-area single-crystal semiconductors. Improving the performance of organic semiconductor devices by increasing the charge mobility is an ongoing quest, which calls for novel molecular and material design, and improved processing conditions. Here we show a method to increase the charge mobility in organic single-crystal field-effect transistors, by taking advantage of the inherent softness of organic semiconductors. We compress the crystal lattice uniaxially by bending the flexible devices, leading to an improved charge transport. The mobility increases from 9.7 to 16.5 cm2 V−1 s−1 by 70% under 3% strain. In-depth analysis indicates that compressing the crystal structure directly restricts the vibration of the molecules, thus suppresses dynamic disorder, a unique mechanism in organic semiconductors. Since strain can be easily induced during the fabrication process, we expect our method to be exploited to build high-performance organic devices. PMID:27040501

Suppressing molecular vibrations in organic semiconductors by inducing strain.

PubMed

Kubo, Takayoshi; Häusermann, Roger; Tsurumi, Junto; Soeda, Junshi; Okada, Yugo; Yamashita, Yu; Akamatsu, Norihisa; Shishido, Atsushi; Mitsui, Chikahiko; Okamoto, Toshihiro; Yanagisawa, Susumu; Matsui, Hiroyuki; Takeya, Jun

2016-04-04

Organic molecular semiconductors are solution processable, enabling the growth of large-area single-crystal semiconductors. Improving the performance of organic semiconductor devices by increasing the charge mobility is an ongoing quest, which calls for novel molecular and material design, and improved processing conditions. Here we show a method to increase the charge mobility in organic single-crystal field-effect transistors, by taking advantage of the inherent softness of organic semiconductors. We compress the crystal lattice uniaxially by bending the flexible devices, leading to an improved charge transport. The mobility increases from 9.7 to 16.5 cm(2) V(-1) s(-1) by 70% under 3% strain. In-depth analysis indicates that compressing the crystal structure directly restricts the vibration of the molecules, thus suppresses dynamic disorder, a unique mechanism in organic semiconductors. Since strain can be easily induced during the fabrication process, we expect our method to be exploited to build high-performance organic devices.

Bacteria Inside Semiconductors as Potential Sensor Elements: Biochip Progress

PubMed Central

Sah, Vasu R.; Baier, Robert E.

2014-01-01

It was discovered at the beginning of this Century that living bacteria—and specifically the extremophile Pseudomonas syzgii—could be captured inside growing crystals of pure water-corroding semiconductors—specifically germanium—and thereby initiated pursuit of truly functional “biochip-based” biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips. PMID:24961215

Sematech: Purpose and Performance

PubMed Central

Irwin, Douglas A.; Klenow, Peter J.

1996-01-01

In previous research, we have found a steep learning curve in the production of semiconductors. We estimated that most production knowledge remains internal to the firm, but that a significant fraction “spills over” to other firms. The existence of such spillovers may justify government actions to stimulate research on semiconductor manufacturing technology. The fact that not all production knowledge spills over, meanwhile, creates opportunities for firms to form joint ventures and slide down their learning curves more efficiently. With these considerations in mind, in 1987 14 leading U.S. semiconductor producers, with the assistance of the U.S. government in the form of $100 million in annual subsidies, formed a research and development (R&D) consortium called Sematech. In previous research, we estimated that Sematech has induced its member firms to lower their R&D spending. This may reflect more sharing and less duplication of research, i.e., more research being done with each R&D dollar. If this is the case, then Sematech members may wish to replace any funding withdrawn by the U.S. government. This in turn would imply that the U.S. government’s contributions to Sematech do not induce more semiconductor research than would otherwise occur. PMID:8917487