Development of Mid-infrared GeSn Light Emitting Diodes on a Silicon Substrate

DTIC Science & Technology

2015-04-22

Materials, Heterostrucuture Semiconductor, Light Emitting Devices, Molecular Beam Epitaxy 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT...LED) structure. Optimization of traditional and hetero- P-i-N structures designed and grown on Ge-buffer Si (001) wafers using molecular beam epitaxy ...designed structures were grown on Ge-buffer Si (001) wafers using molecular beam epitaxy (MBE) with the low-temperature growth technique. (The Ge-buffer

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

Controllable laser thermal cleavage of sapphire wafers

NASA Astrophysics Data System (ADS)

Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

2018-03-01

Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2017-01-01

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2016-01-01

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Schwank, James R.; Fleetwood, Daniel M.; Shaneyfelt, Marty R.; Winokur, Peter S.; Devine, Roderick A. B.

1998-01-01

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

Wafer scale oblique angle plasma etching

DOEpatents

Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

2017-05-23

Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

Commercial production of QWIP wafers by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Fastenau, J. M.; Liu, W. K.; Fang, X. M.; Lubyshev, D. I.; Pelzel, R. I.; Yurasits, T. R.; Stewart, T. R.; Lee, J. H.; Li, S. S.; Tidrow, M. Z.

2001-06-01

As the performance of quantum well infrared photodetectors (QWIPs) and QWIP-based imaging systems continues to improve, their demand will undoubtedly grow. This points to the importance of a reliable commercial supplier of semiconductor QWIP material on three inch and, in the near future, four-inch substrates. Molecular beam epitaxy (MBE) is the preferred technique for growing the demanding QWIP structure, as tight control is required over the material composition and layer thickness. We report the current status of MBE-grown GaAs-based QWIP structures in a commercial production environment at IQE. Uniformity data and run-to-run reproducibility on both three-inch and four-inch GaAs substrates are quantified using alloy composition and QW thickness. Initial results on growth technology transfer to a multi-wafer MBE reactor are also presented. High-resolution X-ray diffraction measurements demonstrate GaAs QW thickness variations and AlGaAs barrier compositions changes to be less than 4% and 1% Al, respectively, across four-inch QWIP wafers from both single- and multiple-wafer MBE platforms.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Schwank, J.R.; Fleetwood, D.M.; Shaneyfelt, M.R.; Winokur, P.S.; Devine, R.A.B.

1998-07-28

A method is disclosed for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer. 5 figs.

Chemical vapor deposition of epitaxial silicon

DOEpatents

Berkman, Samuel

1984-01-01

A single chamber continuous chemical vapor deposition (CVD) reactor is described for depositing continuously on flat substrates, for example, epitaxial layers of semiconductor materials. The single chamber reactor is formed into three separate zones by baffles or tubes carrying chemical source material and a carrier gas in one gas stream and hydrogen gas in the other stream without interaction while the wafers are heated to deposition temperature. Diffusion of the two gas streams on heated wafers effects the epitaxial deposition in the intermediate zone and the wafers are cooled in the final zone by coolant gases. A CVD reactor for batch processing is also described embodying the deposition principles of the continuous reactor.

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); Choi, Sang Hyouk (Inventor); King, Glen C. (Inventor)

2017-01-01

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Epitaxial growth of 100-μm thick M-type hexaferrite crystals on wide bandgap semiconductor GaN/Al{sub 2}O{sub 3} substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Bolin; Su, Zhijuan; Bennett, Steve

2014-05-07

Thick barium hexaferrite BaFe{sub 12}O{sub 19} (BaM) films having thicknesses of ∼100 μm were epitaxially grown on GaN/Al{sub 2}O{sub 3} substrates from a molten-salt solution by vaporizing the solvent. X-ray diffraction measurement verified the growth of BaM (001) textured growth of thick films. Saturation magnetization, 4πM{sub s}, was measured for as-grown films to be 4.6 ± 0.2 kG and ferromagnetic resonance measurements revealed a microwave linewidth of ∼100 Oe at X-band. Scanning electron microscopy indicated clear hexagonal crystals distributed on the semiconductor substrate. These results demonstrate feasibility of growing M-type hexaferrite crystal films on wide bandgap semiconductor substrates by using a simplemore » powder melting method. It also presents a potential pathway for the integration of ferrite microwave passive devices with active semiconductor circuit elements creating system-on-a-wafer architectures.« less

a Study of Oxygen Precipitation in Heavily Doped Silicon.

NASA Astrophysics Data System (ADS)

Graupner, Robert Kurt

Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation processes. This could lead to more effective control and use of oxygen precipitation for gettering. One of the principal purposes of this thesis is the extension of the infrared interstitial oxygen measurement technique to situations outside the measurement capacities of the standard technique. These situations include silicon slices exhibiting interfering precipitate absorption bands and heavily doped n-type silicon wafers. A new method is presented for correcting for the effect of multiple reflections in silicon wafers with optically rough surfaces. The technique for the measurement of interstitial oxygen in heavily doped n-type wafers is then used to perform a comparative study of oxygen precipitation in heavily antimony doped (.035 ohm-cm) silicon and lightly doped p-type silicon. A model is presented to quantitatively explain the observed suppression of defect formation in heavily doped n-type wafers.

Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

NASA Astrophysics Data System (ADS)

Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

The Effect of Dielectric Constants on Noble Metal/Semiconductor SERS Enhancement: FDTD Simulation and Experiment Validation of Ag/Ge and Ag/Si Substrates

PubMed Central

Wang, Tao; Zhang, Zhaoshun; Liao, Fan; Cai, Qian; Li, Yanqing; Lee, Shuit-Tong; Shao, Mingwang

2014-01-01

The finite-difference time-domain (FDTD) method was employed to simulate the electric field distribution for noble metal (Au or Ag)/semiconductor (Ge or Si) substrates. The simulation showed that noble metal/Ge had stronger SERS enhancement than noble metal/Si, which was mainly attributed to the different dielectric constants of semiconductors. In order to verify the simulation, Ag nanoparticles with the diameter of ca. 40 nm were grown on Ge or Si wafer (Ag/Ge or Ag/Si) and employed as surface-enhanced Raman scattering substrates to detect analytes in solution. The experiment demonstrated that both the two substrates exhibited excellent performance in the low concentration detection of Rhodamine 6G. Besides, the enhancement factor (1.3 × 109) and relative standard deviation values (less than 11%) of Ag/Ge substrate were both better than those of Ag/Si (2.9 × 107 and less than 15%, respectively), which was consistent with the FDTD simulation. Moreover, Ag nanoparticles were grown in-situ on Ge substrate, which kept the nanoparticles from aggregation in the detection. To data, Ag/Ge substrates showed the best performance for their sensitivity and uniformity among the noble metal/semiconductor ones. PMID:24514430

The effect of dielectric constants on noble metal/semiconductor SERS enhancement: FDTD simulation and experiment validation of Ag/Ge and Ag/Si substrates.

PubMed

Wang, Tao; Zhang, Zhaoshun; Liao, Fan; Cai, Qian; Li, Yanqing; Lee, Shuit-Tong; Shao, Mingwang

2014-02-11

The finite-difference time-domain (FDTD) method was employed to simulate the electric field distribution for noble metal (Au or Ag)/semiconductor (Ge or Si) substrates. The simulation showed that noble metal/Ge had stronger SERS enhancement than noble metal/Si, which was mainly attributed to the different dielectric constants of semiconductors. In order to verify the simulation, Ag nanoparticles with the diameter of ca. 40 nm were grown on Ge or Si wafer (Ag/Ge or Ag/Si) and employed as surface-enhanced Raman scattering substrates to detect analytes in solution. The experiment demonstrated that both the two substrates exhibited excellent performance in the low concentration detection of Rhodamine 6G. Besides, the enhancement factor (1.3 × 10(9)) and relative standard deviation values (less than 11%) of Ag/Ge substrate were both better than those of Ag/Si (2.9 × 10(7) and less than 15%, respectively), which was consistent with the FDTD simulation. Moreover, Ag nanoparticles were grown in-situ on Ge substrate, which kept the nanoparticles from aggregation in the detection. To data, Ag/Ge substrates showed the best performance for their sensitivity and uniformity among the noble metal/semiconductor ones.

Absorption Coefficient of a Semiconductor Thin Film from Photoluminescence

NASA Astrophysics Data System (ADS)

Rey, G.; Spindler, C.; Babbe, F.; Rachad, W.; Siebentritt, S.; Nuys, M.; Carius, R.; Li, S.; Platzer-Björkman, C.

2018-06-01

The photoluminescence (PL) of semiconductors can be used to determine their absorption coefficient (α ) using Planck's generalized law. The standard method, suitable only for self-supported thick samples, like wafers, is extended to multilayer thin films by means of the transfer-matrix method to include the effect of the substrate and optional front layers. α values measured on various thin-film solar-cell absorbers by both PL and photothermal deflection spectroscopy (PDS) show good agreement. PL measurements are extremely sensitive to the semiconductor absorption and allow us to advantageously circumvent parasitic absorption from the substrate; thus, α can be accurately determined down to very low values, allowing us to investigate deep band tails with a higher dynamic range than in any other method, including spectrophotometry and PDS.

Effects of fluorine contamination on spin-on dielectric thickness in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Kim, Hyoung-ryeun; Hong, Soonsang; Kim, Samyoung; Oh, Changyeol; Hwang, Sung Min

2018-03-01

In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.

Wafer-fused semiconductor radiation detector

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Flexible metal-semiconductor-metal device prototype on wafer-scale thick boron nitride layers grown by MOVPE.

PubMed

Li, Xin; Jordan, Matthew B; Ayari, Taha; Sundaram, Suresh; El Gmili, Youssef; Alam, Saiful; Alam, Muhbub; Patriarche, Gilles; Voss, Paul L; Paul Salvestrini, Jean; Ougazzaden, Abdallah

2017-04-11

Practical boron nitride (BN) detector applications will require uniform materials over large surface area and thick BN layers. To report important progress toward these technological requirements, 1~2.5 µm-thick BN layers were grown on 2-inch sapphire substrates by metal-organic vapor phase epitaxy (MOVPE). The structural and optical properties were carefully characterized and discussed. The thick layers exhibited strong band-edge absorption near 215 nm. A highly oriented two-dimensional h-BN structure was formed at the film/sapphire interface, which permitted an effective exfoliation of the thick BN film onto other adhesive supports. And this structure resulted in a metal-semiconductor-metal (MSM) device prototype fabricated on BN membrane delaminating from the substrate. MSM photodiode prototype showed low dark current of 2 nA under 100 V, and 100 ± 20% photoconductivity yield for deep UV light illumination. These wafer-scale MOVPE-grown thick BN layers present great potential for the development of deep UV photodetection applications, and even for flexible (opto-) electronics in the future.

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

Semiconductor Film Grown on a Circular Substrate: Predictive Modeling of Lattice-Misfit Stresses

NASA Astrophysics Data System (ADS)

Suhir, E.; Nicolics, J.; Khatibi, G.; Lederer, M.

2016-03-01

An effective and physically meaningful analytical predictive model is developed for the evaluation the lattice-misfit stresses (LMS) in a semiconductor film grown on a circular substrate (wafer). The two-dimensional (plane-stress) theory-of-elasticity approximation (TEA) is employed in the analysis. The addressed stresses include the interfacial shearing stress, responsible for the occurrence and growth of dislocations, as well as for possible delaminations and the cohesive strength of a buffering material, if any. Normal radial and circumferential (tangential) stresses acting in the film cross-sections and responsible for its short- and long-term strength (fracture toughness) are also addressed. The analysis is geared to the GaN technology.

A review of nanoimprint lithography for high-volume semiconductor device manufacturing

NASA Astrophysics Data System (ADS)

Resnick, Douglas J.; Choi, Jin

2017-06-01

Imprint lithography has been shown to be a promising technique for the replication of nanoscale features. Jet and flash imprint lithography (J-FIL) [jet and flash imprint lithography and J-FIL are trademarks of Molecular Imprints, Inc.] involves the field-by-field deposition and exposure of a low-viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid, which then quickly flows into the relief patterns in the mask by capillary action. After this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput, and defectivity. The most demanding devices now require an overlay of better than 4 nm, 3σ. Throughput for an imprint tool is generally targeted at 80 wafers/h. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. To address high-order corrections, a high-order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask and temperature correction to the wafer is described in detail. Examples are presented for the correction of K7, K11, and K17 distortions as well as distortions on actual device wafers.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Hybrid Integrated Platforms for Silicon Photonics

PubMed Central

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Compact Submillimeter-Wave Receivers Made with Semiconductor Nano-Fabrication Technologies

NASA Technical Reports Server (NTRS)

Jung, C.; Thomas, B.; Lee, C.; Peralta, A.; Chattopadhyay, G.; Gill, J.; Cooper, K.; Mehdi, I.

2011-01-01

Advanced semiconductor nanofabrication techniques are utilized to design, fabricate and demonstrate a super-compact, low-mass (<10 grams) submillimeter-wave heterodyne front-end. RF elements such as waveguides and channels are fabricated in a silicon wafer substrate using deep-reactive ion etching (DRIE). Etched patterns with sidewalls angles controlled with 1 deg precision are reported, while maintaining a surface roughness of better than 20 nm rms for the etched structures. This approach is being developed to build compact 2-D imaging arrays in the THz frequency range.

Method for imaging informational biological molecules on a semiconductor substrate

NASA Technical Reports Server (NTRS)

Coles, L. Stephen (Inventor)

1994-01-01

Imaging biological molecules such as DNA at rates several times faster than conventional imaging techniques is carried out using a patterned silicon wafer having nano-machined grooves which hold individual molecular strands and periodically spaced unique bar codes permitting repeatably locating all images. The strands are coaxed into the grooves preferably using gravity and pulsed electric fields which induce electric charge attraction to the molecular strands in the bottom surfaces of the grooves. Differential imaging removes substrate artifacts.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, Theodoer F.

1995-01-01

Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

InP-based photonic integrated circuit platform on SiC wafer.

PubMed

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

2016-10-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

PubMed

Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

2013-01-01

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

A new fabrication technique for back-to-back varactor diodes

NASA Technical Reports Server (NTRS)

Smith, R. Peter; Choudhury, Debabani; Martin, Suzanne; Frerking, Margaret A.; Liu, John K.; Grunthaner, Frank A.

1992-01-01

A new varactor diode process has been developed in which much of the processing is done from the back of an extremely thin semiconductor wafer laminated to a low-dielectric substrate. Back-to-back BNN diodes were fabricated with this technique; excellent DC and low-frequency capacitance measurements were obtained. Advantages of the new technique relative to other techniques include greatly reduced frontside wafer damage from exposure to process chemicals, improved capability to integrate devices (e.g. for antenna patterns, transmission lines, or wafer-scale grids), and higher line yield. BNN diodes fabricated with this technique exhibit approximately the expected capacitance-voltage characteristics while showing leakage currents under 10 mA at voltages three times that needed to deplete the varactor. This leakage is many orders of magnitude better than comparable Schottky diodes.

Evaluation and verification of epitaxial process sequence for silicon solar-cell production

NASA Technical Reports Server (NTRS)

Redfield, D.

1981-01-01

To achieve the program goals, 28 minimodules were fabricated and tested, using 600 cells made from three-inch-diameter wafers processed by the sequence chosen for this purpose. Of these 600 cells, half were made from epitaxially grown layers on potentially low-cost substrates. The other half were made from commercial semiconductor-grade (SG), single-crystal silicon wafers that served as controls. Cell processing was normally performed on mixed lots containing significant numbers of each of these two types of wafers. After evaluation of the performance of all cells, they were separated by types for incorporation into modules that were to be tested for electrical performance and response to environmental stress. A simplified flow chart displaying this scheme, for quantities representing half of the planned total to be processed, is presented.

Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies

NASA Astrophysics Data System (ADS)

Tanake, Katsuaki

We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of InP/Si substrates for bulk InP in the fabrication of such a four-junction solar cell could significantly reduce the substrate cost since the current prices for commercial InP substrates are much higher than those for Si substrates by two orders of magnitude. Direct heteroepitaxial growth of InP thin films on Si substrates has not produced the low dislocation-density high quality layers required for active InGaAs/InP in optoelectronic devices due to the ˜8% lattice mismatch between InP and Si. We successfully fabricated InP/Si substrates by He implantation of InP prior to bonding to a thermally oxidized Si substrate and annealing to exfoliate an InP thin film. The thickness of the exfoliated InP films was only 900 nm, which means hundreds of the InP/Si substrates could be prepared from a single InP wafer in principle. The photovoltaic current-voltage characteristics of the In0.53Ga0.47As cells fabricated on the wafer-bonded InP/Si substrates were comparable to those synthesized on commercially available epi-ready InP substrates, and had a ˜20% higher short-circuit current which we attribute to the high reflectivity of the InP/SiO2/Si bonding interface. This work provides an initial demonstration of wafer-bonded InP/Si substrates as an alternative to bulk InP substrates for solar cell applications. We have observed photocurrent enhancements up to 260% at 900 nm for a GaAs cell with a dense array of Ag nanoparticles with 150 nm diameter and 20 nm height deposited through porous alumina membranes by thermal evaporation on top of the cell, relative to reference GaAs cells with no metal nanoparticle array. This dramatic photocurrent enhancement is attributed to the effect of metal nanoparticles to scatter the incident light into photovoltaic layers with a wide range of angles to increase the optical path length in the absorber layer. GaAs solar cells with metallic structures at the bottom of the photovoltaic active layers, not only at the top, using semiconductor-metal direct bonding have been fabricated. These metallic back structures could incouple the incident light into surface plasmon mode propagating at the semiconductor/metal interface to increase the optical path, as well as simply act as back reflector, and we have observed significantly increased short-circuit current relative to reference cells without these metal components. (Abstract shortened by UMI.)

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, T.F.

1995-03-07

Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

Transfer of InP epilayers by wafer bonding

NASA Astrophysics Data System (ADS)

Hjort, Klas

2004-08-01

Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

Wafer-scale design of lightweight and transparent electronics that wraps around hairs

NASA Astrophysics Data System (ADS)

Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

2014-01-01

Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

Method of forming thermally stable high-resistivity regions in n-type indium phosphide by oxygen implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Thompson, P.E.; Dietrich, H.B.

1985-12-12

Objects of this invention are: to form high-temperature stable isolation regions in InP; to provide InP wafers that allow greater flexibility in the design and fabrication of discrete devices; to provide new and improved InP semiconductor devices in n-type InP; to provide high-resisitivity isolation regions in InP; to extend the usefulness of damage-induced isolation in n-type InP by making possible processes in which the isolation implantation precedes the alloying of ohmic contacts; and to provide n-type InP substrates without unwanted conductive layers. The above and other object are realized by an InP wafer comprising a S.I. InP substrate; a n-typemore » InP active layer disposed on the substrate; and oxygen ion implanted isolation regions disposed in the active layer. The S.I. InP dopant may comprise either Fe or Cr.« less

Growing Cobalt Silicide Columns In Silicon

NASA Technical Reports Server (NTRS)

Fathauer, Obert W.

1991-01-01

Codeposition by molecular-beam epitaxy yields variety of structures. Proposed fabrication process produces three-dimensional nanometer-sized structures on silicon wafers. Enables control of dimensions of metal and semiconductor epitaxial layers in three dimensions instead of usual single dimension (perpendicular to the plane of the substrate). Process used to make arrays of highly efficient infrared sensors, high-speed transistors, and quantum wires. For fabrication of electronic devices, both shapes and locations of columns controlled. One possible technique for doing this electron-beam lithography, see "Making Submicron CoSi2 Structures on Silicon Substrates" (NPO-17736).

Alternative Packaging for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Optic probe for semiconductor characterization

DOEpatents

Sopori, Bhushan L [Denver, CO; Hambarian, Artak [Yerevan, AM

2008-09-02

Described herein is an optical probe (120) for use in characterizing surface defects in wafers, such as semiconductor wafers. The optical probe (120) detects laser light reflected from the surface (124) of the wafer (106) within various ranges of angles. Characteristics of defects in the surface (124) of the wafer (106) are determined based on the amount of reflected laser light detected in each of the ranges of angles. Additionally, a wafer characterization system (100) is described that includes the described optical probe (120).

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Pump-probe surface photovoltage spectroscopy measurements on semiconductor epitaxial layers.

PubMed

Jana, Dipankar; Porwal, S; Sharma, T K; Kumar, Shailendra; Oak, S M

2014-04-01

Pump-probe Surface Photovoltage Spectroscopy (SPS) measurements are performed on semiconductor epitaxial layers. Here, an additional sub-bandgap cw pump laser beam is used in a conventional chopped light geometry SPS setup under the pump-probe configuration. The main role of pump laser beam is to saturate the sub-bandgap localized states whose contribution otherwise swamp the information related to the bandgap of material. It also affects the magnitude of Dember voltage in case of semi-insulating (SI) semiconductor substrates. Pump-probe SPS technique enables an accurate determination of the bandgap of semiconductor epitaxial layers even under the strong influence of localized sub-bandgap states. The pump beam is found to be very effective in suppressing the effect of surface/interface and bulk trap states. The overall magnitude of SPV signal is decided by the dependence of charge separation mechanisms on the intensity of the pump beam. On the contrary, an above bandgap cw pump laser can be used to distinguish the signatures of sub-bandgap states by suppressing the band edge related feature. Usefulness of the pump-probe SPS technique is established by unambiguously determining the bandgap of p-GaAs epitaxial layers grown on SI-GaAs substrates, SI-InP wafers, and p-GaN epilayers grown on Sapphire substrates.

Wafer-level packaging with compression-controlled seal ring bonding

DOEpatents

Farino, Anthony J

2013-11-05

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Reflective optical imaging system

DOEpatents

Shafer, David R.

2000-01-01

An optical system compatible with short wavelength (extreme ultraviolet) radiation comprising four reflective elements for projecting a mask image onto a substrate. The four optical elements are characterized in order from object to image as convex, concave, convex and concave mirrors. The optical system is particularly suited for step and scan lithography methods. The invention increases the slit dimensions associated with ringfield scanning optics, improves wafer throughput and allows higher semiconductor device density.

Reflective optical imaging method and circuit

DOEpatents

Shafer, David R.

2001-01-01

An optical system compatible with short wavelength (extreme ultraviolet) radiation comprising four reflective elements for projecting a mask image onto a substrate. The four optical elements are characterized in order from object to image as convex, concave, convex and concave mirrors. The optical system is particularly suited for step and scan lithography methods. The invention increases the slit dimensions associated with ringfield scanning optics, improves wafer throughput and allows higher semiconductor device density.

Bar-Coated Ultrathin Semiconductors from Polymer Blend for One-Step Organic Field-Effect Transistors.

PubMed

Ge, Feng; Liu, Zhen; Lee, Seon Baek; Wang, Xiaohong; Zhang, Guobing; Lu, Hongbo; Cho, Kilwon; Qiu, Longzhen

2018-06-27

One-step deposition of bi-functional semiconductor-dielectric layers for organic field-effect transistors (OFETs) is an effective way to simplify the device fabrication. However, the proposed method has rarely been reported in large-area flexible organic electronics. Herein, we demonstrate wafer-scale OFETs by bar coating the semiconducting and insulating polymer blend solution in one-step. The semiconducting polymer poly(3-hexylthiophene) (P3HT) segregates on top of the blend film, whereas dielectric polymethyl methacrylate (PMMA) acts as the bottom layer, which is achieved by a vertical phase separation structure. The morphology of blend film can be controlled by varying the concentration of P3HT and PMMA solutions. The wafer-scale one-step OFETs, with a continuous ultrathin P3HT film of 2.7 nm, exhibit high electrical reproducibility and uniformity. The one-step OFETs extend to substrate-free arrays that can be attached everywhere on varying substrates. In addition, because of the well-ordered molecular arrangement, the moderate charge transport pathway is formed, which resulted in stable OFETs under various organic solvent vapors and lights of different wavelengths. The results demonstrate that the one-step OFETs have promising potential in the field of large-area organic wearable electronics.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

Novel On-wafer Radiation Pattern Measurement Technique for MEMS Actuator Based Reconfigurable Patch Antennas

NASA Technical Reports Server (NTRS)

Simons, Rainee N.

2002-01-01

The paper presents a novel on-wafer, antenna far field pattern measurement technique for microelectromechanical systems (MEMS) based reconfigurable patch antennas. The measurement technique significantly reduces the time and the cost associated with the characterization of printed antennas, fabricated on a semiconductor wafer or dielectric substrate. To measure the radiation patterns, the RF probe station is modified to accommodate an open-ended rectangular waveguide as the rotating linearly polarized sampling antenna. The open-ended waveguide is attached through a coaxial rotary joint to a Plexiglas(Trademark) arm and is driven along an arc by a stepper motor. Thus, the spinning open-ended waveguide can sample the relative field intensity of the patch as a function of the angle from bore sight. The experimental results include the measured linearly polarized and circularly polarized radiation patterns for MEMS-based frequency reconfigurable rectangular and polarization reconfigurable nearly square patch antennas, respectively.

Work function characterization of solution-processed cobalt silicide

DOE PAGES

Ullah, Syed Shihab; Robinson, Matt; Hoey, Justin; ...

2012-05-08

Cobalt silicide thin films were prepared by spin-coating Si6H12-based inks onto various substrates followed by a thermal treatment. The work function of the solution processed Co-Si was determined by both capacitance-voltage (C-V) measurements of metal-oxide-semiconductor (MOS) structures as well as by ultraviolet photoelectron spectroscopy (UPS). The UPS-derived work function was 4.80 eV for a Co-Si film on Si (100) while C-V of MOS structures yielded a work function of 4.36 eV where the metal was solution-processed Co-Si, the oxide was SiO2 and the semiconductor was a B-doped Si wafer.

High throughput wafer defect monitor for integrated metrology applications in photolithography

NASA Astrophysics Data System (ADS)

Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

2008-03-01

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

NASA Astrophysics Data System (ADS)

Altan, Hakan

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

SiC Seeded Crystal Growth

NASA Astrophysics Data System (ADS)

Glass, R. C.; Henshall, D.; Tsvetkov, V. F.; Carter, C. H., Jr.

1997-07-01

The availability of relatively large (30 mm) SiC wafers has been a primary reason for the renewed high level of interest in SiC semiconductor technology. Projections that 75 mm SiC wafers will be available in 2 to 3 years have further peaked this interest. Now both 4H and 6H polytypes are available, however, the micropipe defects that occur to a varying extent in all wafers produced to date are seen by many as preventing the commercialization of many types of SiC devices, especially high current power devices. Most views on micropipe formation are based around Frank's theory of a micropipe being the hollow core of a screw dislocation with a huge Burgers vector (several times the unit cell) and with the diameter of the core having a direct relationship with the magnitude of the Burgers vector. Our results show that there are several mechanisms or combinations of these mechanisms which cause micropipes in SiC boules grown by the seeded sublimation method. Additional considerations such as polytype variations, dislocations and both impurity and diameter control add to the complexity of producing high quality wafers. Recent results at Cree Research, Inc., including wafers with micropipe densities of less than 1 cm - 2 (with 1 cm2 areas void of micropipes), indicate that micropipes will be reduced to a level that makes high current devices viable and that they may be totally eliminated in the next few years. Additionally, efforts towards larger diameter high quality substrates have led to production of 50 mm diameter 4H and 6H wafers for fabrication of LEDs and the demonstration of 75 mm wafers. Low resistivity and semi-insulating electrical properties have also been attained through improved process and impurity control. Although challenges remain, the industry continues to make significant progress towards large volume SiC-based semiconductor fabrication.

Contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication

DOEpatents

Sopori, Bhushan

2014-05-27

Methods for contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication are provided. In one embodiment, a method for fabricating an electrical semiconductor device comprises: a first step that includes gettering of impurities from a semiconductor wafer and forming a backsurface field; and a second step that includes forming a front contact for the semiconductor wafer, wherein the second step is performed after completion of the first step.

Reliability Analysis/Assessment of Advanced Technologies

DTIC Science & Technology

1990-05-01

34, Reliability Physics 1980 , IEEE, p. 165. 25. RADC-TR-83-244. 26. Towner, Janet M., et. al., "Aluminum Electromigration Under Pulsed D.C. Conditions...Duvvury, Redwine, Kitagawa, Haas, Chuang, Beydler, Hyslop , "Impact of Hot Carriers On DRAM circuits", 1987 IEEE/IRPS. 58. Cahoon, Thornewell, Tsai...et. a]., "Substrate for Large Silicon Chip and Full Wafer Packaging", Semiconductor International, pp. 149-156, April 1980 . 5. T.E. Lewis and D.L

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

Sub-Kelvin resistance thermometer

NASA Technical Reports Server (NTRS)

Castles, Stephen H. (Inventor)

1992-01-01

A device capable of accurate temperature measurement down to 0.01 K of a particular object is discussed. The device is comprised of the following: a heat sink wafer; a first conducting pad bonded near one end of the heat sink wafer; a second conducting pad bonded near the other end of the heat sink wafer; and an oblong doped semiconductor crystal such as germanium. The oblong doped semiconductor crystal has a third conducting pad bonded on its bottom surface with the oblong doped semiconductor crystal bonded to the heat sink wafer by having the fourth conducting pad bonded to the first conducting pad. A wire is bonded between the second and third conducting pads. Current and voltage wires bonded to the first and second conducting pads measure the change in resistance of the oblong doped semiconductor crystal; this indicates the temperature of the object whose temperature is to be measured.

Developing quartz wafer mold manufacturing process for patterned media

NASA Astrophysics Data System (ADS)

Chiba, Tsuyoshi; Fukuda, Masaharu; Ishikawa, Mikio; Itoh, Kimio; Kurihara, Masaaki; Hoga, Morihisa

2009-04-01

Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

X-ray topography as a process control tool in semiconductor and microcircuit manufacture

NASA Technical Reports Server (NTRS)

Parker, D. L.; Porter, W. A.

1977-01-01

A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.

Ergonomic risk factors of work processes in the semiconductor industry in Peninsular Malaysia.

PubMed

Chee, Heng-Leng; Rampal, Krishna Gopal; Chandrasakaran, Abherhame

2004-07-01

A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might have led to high pain prevalences in the low back (35.0% wafer preparation, 41.7% wafer polishing) and lower limbs (90.0% wafer preparation, 66.7% wafer polishing). Semiconductor front of line workers, who mostly walked around to operate machines in clean rooms, had the lowest prevalences of body pain. Semiconductor assembly middle of line workers, especially the molding workers, who did frequent lifting, had high pain prevalences in the neck/shoulders (54.8%) and upper back (43.5 %). In the semiconductor assembly end of line work section, chip inspection workers who were exposed to prolonged sitting without back support had high prevalences of neck/shoulder (62.2%) and upper back pain (50.0%), while chip testing workers who had to climb steps to load units had a high prevalence of lower limb pain (68.0%). Workers in the assembly of electronic components, carrying out repetitive tasks with hands and fingers, and standing in awkward postures had high pain prevalences in the neck/shoulders (61.5%), arms (38.5%), and hands/wrists (30.8%).

Tailored surface-enhanced Raman nanopillar arrays fabricated by laser-assisted replication for biomolecular detection using organic semiconductor lasers.

PubMed

Liu, Xin; Lebedkin, Sergei; Besser, Heino; Pfleging, Wilhelm; Prinz, Stephan; Wissmann, Markus; Schwab, Patrick M; Nazarenko, Irina; Guttmann, Markus; Kappes, Manfred M; Lemmer, Uli

2015-01-27

Organic semiconductor distributed feedback (DFB) lasers are of interest as external or chip-integrated excitation sources in the visible spectral range for miniaturized Raman-on-chip biomolecular detection systems. However, the inherently limited excitation power of such lasers as well as oftentimes low analyte concentrations requires efficient Raman detection schemes. We present an approach using surface-enhanced Raman scattering (SERS) substrates, which has the potential to significantly improve the sensitivity of on-chip Raman detection systems. Instead of lithographically fabricated Au/Ag-coated periodic nanostructures on Si/SiO2 wafers, which can provide large SERS enhancements but are expensive and time-consuming to fabricate, we use low-cost and large-area SERS substrates made via laser-assisted nanoreplication. These substrates comprise gold-coated cyclic olefin copolymer (COC) nanopillar arrays, which show an estimated SERS enhancement factor of up to ∼ 10(7). The effect of the nanopillar diameter (60-260 nm) and interpillar spacing (10-190 nm) on the local electromagnetic field enhancement is studied by finite-difference-time-domain (FDTD) modeling. The favorable SERS detection capability of this setup is verified by using rhodamine 6G and adenosine as analytes and an organic semiconductor DFB laser with an emission wavelength of 631.4 nm as the external fiber-coupled excitation source.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jana, Dipankar, E-mail: dip2602@gmail.com; Porwal, S.; Sharma, T. K., E-mail: tarun@rrcat.gov.in

Pump-probe Surface Photovoltage Spectroscopy (SPS) measurements are performed on semiconductor epitaxial layers. Here, an additional sub-bandgap cw pump laser beam is used in a conventional chopped light geometry SPS setup under the pump-probe configuration. The main role of pump laser beam is to saturate the sub-bandgap localized states whose contribution otherwise swamp the information related to the bandgap of material. It also affects the magnitude of Dember voltage in case of semi-insulating (SI) semiconductor substrates. Pump-probe SPS technique enables an accurate determination of the bandgap of semiconductor epitaxial layers even under the strong influence of localized sub-bandgap states. The pumpmore » beam is found to be very effective in suppressing the effect of surface/interface and bulk trap states. The overall magnitude of SPV signal is decided by the dependence of charge separation mechanisms on the intensity of the pump beam. On the contrary, an above bandgap cw pump laser can be used to distinguish the signatures of sub-bandgap states by suppressing the band edge related feature. Usefulness of the pump-probe SPS technique is established by unambiguously determining the bandgap of p-GaAs epitaxial layers grown on SI-GaAs substrates, SI-InP wafers, and p-GaN epilayers grown on Sapphire substrates.« less

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

Fast Optoelectronic Switching Processes in Surface-Emitting Semiconductor Lasers and Nonlinear Etalons

DTIC Science & Technology

1992-05-01

molecular beam epitaxy (MWE). The crystal growers have been persuaded of the importance of this work, and several substrate rotation arrangements and In...RPG VCSELS for optical pumping at 800 wm GaAs/GaAlAs RPA etalons without epitaxial reflectors. The first three wafers were destined for above- and below...of MOCVD-grown GaAs/GaAIAs RPO- VCSEL samples with 20 quantum wells and epitaXial multilayer high-reflectivity stacks with R=3.995 and 0.999 was pumped

Semiconductor solar cells: Recent progress in terrestrial applications

NASA Astrophysics Data System (ADS)

Avrutin, V.; Izyumskaya, N.; Morkoç, H.

2011-04-01

In the last decade, the photovoltaic industry grew at a rate exceeding 30% per year. Currently, solar-cell modules based on single-crystal and large-grain polycrystalline silicon wafers comprise more than 80% of the market. Bulk Si photovoltaics, which benefit from the highly advanced growth and fabrication processes developed for microelectronics industry, is a mature technology. The light-to-electric power conversion efficiency of the best modules offered on the market is over 20%. While there is still room for improvement, the device performance is approaching the thermodynamic limit of ˜28% for single-junction Si solar cells. The major challenge that the bulk Si solar cells face is, however, the cost reduction. The potential for price reduction of electrical power generated by wafer-based Si modules is limited by the cost of bulk Si wafers, making the electrical power cost substantially higher than that generated by combustion of fossil fuels. One major strategy to bring down the cost of electricity generated by photovoltaic modules is thin-film solar cells, whose production does not require expensive semiconductor substrates and very high temperatures and thus allows decreasing the cost per unit area while retaining a reasonable efficiency. Thin-film solar cells based on amorphous, microcrystalline, and polycrystalline Si as well as cadmium telluride and copper indium diselenide compound semiconductors have already proved their commercial viability and their market share is increasing rapidly. Another avenue to reduce the cost of photovoltaic electricity is to increase the cell efficiency beyond the Shockley-Queisser limit. A variety of concepts proposed along this avenue forms the basis of the so-called third generation photovoltaics technologies. Among these approaches, high-efficiency multi-junction solar cells based on III-V compound semiconductors, which initially found uses in space applications, are now being developed for terrestrial applications. In this article, we discuss the progress, outstanding problems, and environmental issues associated with bulk Si, thin-film, and high-efficiency multi-junction solar cells.

Strong emission of terahertz radiation from nanostructured Ge surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kang, Chul; Maeng, Inhee; Kee, Chul-Sik, E-mail: cskee@gist.ac.kr

2015-06-29

Indirect band gap semiconductors are not efficient emitters of terahertz radiation. Here, we report strong emission of terahertz radiation from germanium wafers with nanostructured surfaces. The amplitude of THz radiation from an array of nano-bullets (nano-cones) is more than five (three) times larger than that from a bare-Ge wafer. The power of the terahertz radiation from a Ge wafer with an array of nano-bullets is comparable to that from n-GaAs wafers, which have been widely used as a terahertz source. We find that the THz radiation from Ge wafers with the nano-bullets is even more powerful than that from n-GaAsmore » for frequencies below 0.6 THz. Our results suggest that introducing properly designed nanostructures on indirect band gap semiconductor wafers is a simple and cheap method to improve the terahertz emission efficiency of the wafers significantly.« less

Preliminary results for mask metrology using spatial heterodyne interferometry

NASA Astrophysics Data System (ADS)

Bingham, Philip R.; Tobin, Kenneth; Bennett, Marylyn H.; Marmillion, Pat

2003-12-01

Spatial heterodyne interferometry (SHI) is an imaging technique that captures both the phase and amplitude of a complex wavefront in a single high-speed image. This technology was developed at the Oak Ridge National Laboratory (ORNL) and is currently being implemented for semiconductor wafer inspection by nLine Corporation. As with any system that measures phase, metrology and inspection of surface structures is possible by capturing a wavefront reflected from the surface. The interpretation of surface structure heights for metrology applications can become very difficult with the many layers of various materials used on semiconductor wafers, so inspection (defect detection) has been the primary focus for semiconductor wafers. However, masks used for photolithography typically only contain a couple well-defined materials opening the doors to high-speed mask metrology in 3 dimensions in addition to inspection. Phase shift masks often contain structures etched out of the transparent substrate material for phase shifting. While these structures are difficult to inspect using only intensity, the phase and amplitude images captured with SHI can produce very good resolution of these structures. The phase images also provide depth information that is crucial for these phase shift regions. Preliminary testing has been performed to determine the feasibility of SHI for high-speed non-contact mask metrology using a prototype SHI system with 532 nm wavelength illumination named the Visible Alpha Tool (VAT). These results show that prototype SHI system is capable of performing critical dimension measurements on 400nm lines with a repeatability of 1.4nm and line height measurements with a repeatability of 0.26nm. Additionally initial imaging of an alternating aperture phase shift mask has shown the ability of SHI to discriminate between typical phase shift heights.

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

NASA Technical Reports Server (NTRS)

Choi, Sang; King, Glen; Park, Yeonjoon

2009-01-01

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

Nanoimprint system development and status for high volume semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Hiura, Hiromi; Takabayashi, Yukio; Takashima, Tsuneo; Emoto, Keiji; Choi, Jin; Schumaker, Phil

2016-10-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. For imprint lithography, recent attention has been given to the areas of overlay, throughput, defectivity, and mask replication. This paper reviews progress in these critical areas. Recent demonstrations have proven that mix and match overlay of less than 5nm can achieved. Further reductions require a higher order correction system. Modeling and experimental data are presented which provide a path towards reducing the overlay errors to less than 3nm. Throughput is mainly impacted by the fill time of the relief images on the mask. Improvement in resist materials provides a solution that allows 15 wafers per hour per station, or a tool throughput of 60 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. Finally, on the mask side, a new replication tool, the FPA-1100NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control and IP accuracy. In particular, by improving the specifications on the mask chuck, residual errors of only 1nm can be realized.

Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols.

PubMed

Lee, Dae-Sik; Yang, Haesik; Chung, Kwang-Hyo; Pyo, Hyeon-Bong

2005-08-15

Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.

Context-based automated defect classification system using multiple morphological masks

DOEpatents

Gleason, Shaun S.; Hunt, Martin A.; Sari-Sarraf, Hamed

2002-01-01

Automatic detection of defects during the fabrication of semiconductor wafers is largely automated, but the classification of those defects is still performed manually by technicians. This invention includes novel digital image analysis techniques that generate unique feature vector descriptions of semiconductor defects as well as classifiers that use these descriptions to automatically categorize the defects into one of a set of pre-defined classes. Feature extraction techniques based on multiple-focus images, multiple-defect mask images, and segmented semiconductor wafer images are used to create unique feature-based descriptions of the semiconductor defects. These feature-based defect descriptions are subsequently classified by a defect classifier into categories that depend on defect characteristics and defect contextual information, that is, the semiconductor process layer(s) with which the defect comes in contact. At the heart of the system is a knowledge database that stores and distributes historical semiconductor wafer and defect data to guide the feature extraction and classification processes. In summary, this invention takes as its input a set of images containing semiconductor defect information, and generates as its output a classification for the defect that describes not only the defect itself, but also the location of that defect with respect to the semiconductor process layers.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.

Manufacture of silicon-based devices having disordered sulfur-doped surface layers

DOEpatents

Carey, III; Edward, James [Newton, MA; Mazur, Eric [Concord, MA

2008-04-08

The present invention provides methods of fabricating a radiation-absorbing semiconductor wafer by irradiating at least one surface location of a silicon substrate, e.g., an n-doped crystalline silicon, by a plurality of temporally short laser pulses, e.g., femtosecond pulses, while exposing that location to a substance, e.g., SF.sub.6, having an electron-donating constituent so as to generate a substantially disordered surface layer (i.e., a microstructured layer) that incorporates a concentration of that electron-donating constituent, e.g., sulfur. The substrate is also annealed at an elevated temperature and for a duration selected to enhance the charge carrier density in the surface layer. For example, the substrate can be annealed at a temperature in a range of about 700 K to about 900 K.

Direct Growth of Graphene Film on Germanium Substrate

PubMed Central

Wang, Gang; Zhang, Miao; Zhu, Yun; Ding, Guqiao; Jiang, Da; Guo, Qinglei; Liu, Su; Xie, Xiaoming; Chu, Paul K.; Di, Zengfeng; Wang, Xi

2013-01-01

Graphene has been predicted to play a role in post-silicon electronics due to the extraordinary carrier mobility. Chemical vapor deposition of graphene on transition metals has been considered as a major step towards commercial realization of graphene. However, fabrication based on transition metals involves an inevitable transfer step which can be as complicated as the deposition of graphene itself. By ambient-pressure chemical vapor deposition, we demonstrate large-scale and uniform depositon of high-quality graphene directly on a Ge substrate which is wafer scale and has been considered to replace conventional Si for the next generation of high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs). The immiscible Ge-C system under equilibrium conditions dictates graphene depositon on Ge via a self-limiting and surface-mediated process rather than a precipitation process as observed from other metals with high carbon solubility. Our technique is compatible with modern microelectronics technology thus allowing integration with high-volume production of complementary metal-oxide-semiconductors (CMOS). PMID:23955352

Cancer mortality among US workers employed in semiconductor wafer fabrication.

PubMed

Boice, John D; Marano, Donald E; Munro, Heather M; Chadda, Bandana K; Signorello, Lisa B; Tarone, Robert E; Blot, William J; McLaughlin, Joseph K

2010-11-01

To evaluate potential cancer risks in the US semiconductor wafer fabrication industry. A cohort of 100,081 semiconductor workers employed between 1968 and 2002 was studied. Standardized mortality ratios and relative risks (RRs) were estimated. Standardized mortality ratios were similar and significantly low among fabrication and nonfabrication workers for all causes (0.54 and 0.54) and all cancers (0.74 and 0.72). Internal comparisons also showed similar overall cancer risks among fabrication workers (RR = 0.98), including process equipment operators and process equipment service technicians (OP/EST) employed in cleanrooms (RR = 0.97), compared with nonfabrication workers. Nonsignificantly elevated RRs were observed for a few cancer sites among OP/EST workers, but the numbers of deaths were small and there were no trends of increasing risk with duration of employment. Work in the US semiconductor industry, including semiconductor wafer fabrication in cleanrooms, was not associated with increased cancer mortality overall or mortality from any specific form of cancer. However, due to the young average age of this cohort and its associated relatively low numbers of deaths, regular mortality updates of this semiconductor worker cohort are warranted.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Interface and facet control during Czochralski growth of (111) InSb crystals for cost reduction and yield improvement of IR focal plane array substrates

NASA Astrophysics Data System (ADS)

Gray, Nathan W.; Perez-Rubio, Victor; Bolke, Joseph G.; Alexander, W. B.

2014-10-01

Focal plane arrays (FPAs) made on InSb wafers are the key cost-driving component in IR imaging systems. The electronic and crystallographic properties of the wafer directly determine the imaging device performance. The "facet effect" describes the non-uniform electronic properties of crystals resulting from anisotropic dopant segregation during bulk growth. When the segregation coefficient of dopant impurities changes notably across the melt/solid interface of a growing crystal the result is non-uniform electronic properties across wafers made from these crystals. The effect is more pronounced in InSb crystals grown on the (111) axis compared with other orientations and crystal systems. FPA devices made on these wafers suffer costly yield hits due to inconsistent device response and performance. Historically, InSb crystal growers have grown approximately 9-19 degree off-axis from the (111) to avoid the facet effect and produced wafers with improved uniformity of electronic properties. It has been shown by researchers in the 1960s that control of the facet effect can produce uniform small diameter crystals. In this paper, we share results employing a process that controls the facet effect when growing large diameter crystals from which 4, 5, and 6" wafers can be manufactured. The process change resulted in an increase in wafers yielded per crystal by several times, all with high crystal quality and uniform electronic properties. Since the crystals are grown on the (111) axis, manufacturing (111) oriented wafers is straightforward with standard semiconductor equipment and processes common to the high-volume silicon wafer industry. These benefits result in significant manufacturing cost savings and increased value to our customers.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

Forming electrical interconnections through semiconductor wafers

NASA Technical Reports Server (NTRS)

Anthony, T. R.

1981-01-01

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Uncooled pulsed zinc oxide semiconductor laser

NASA Astrophysics Data System (ADS)

Bogdankevich, O. V.; Darznek, S. A.; Zverev, M. M.; Kostin, N. N.; Krasavina, E. M.

1985-02-01

An optimized ZnO laser which operates at ambient temperature without cooling is reported, along with extension of the design to form a multielement high-power laser. ZnO single crystal plane-parallel wafers 0.22 mm thick, covered with total and semi-transparent coatings, were exposed to a 200 keV electron beam with a 10 nsec pulse and a current density up to 1 kA/sq cm. No damage was observed in the crystals at saturation. A 7 percent maximum efficiency at a reflection coefficient (RC) of 0.4 was associated with a maximum output of 25 kW and a light power density of 3 MW/sq cm. Cementing a ZnO wafer to a sapphire substrate, applying the same type of coatings and working with a RC of 0.6 yielded a maximum power of 300 kW/sq cm.

Heating device for semiconductor wafers

DOEpatents

Vosen, Steven R.

1999-01-01

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Heating device for semiconductor wafers

DOEpatents

Vosen, S.R.

1999-07-27

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

PubMed Central

Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

2016-01-01

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

Advances in silicon carbide Chemical Vapor Deposition (CVD) for semiconductor device fabrication

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Petit, Jeremy B.; Matus, Lawrence G.

1991-01-01

Improved SiC chemical vapor deposition films of both 3C and 6H polytypes were grown on vicinal (0001) 6H-SiC wafers cut from single-crystal boules. These films were produced from silane and propane in hydrogen at one atmosphere at a temperature of 1725 K. Among the more important factors which affected the structure and morphology of the grown films were the tilt angle of the substrate, the polarity of the growth surface, and the pregrowth surface treatment of the substrate. With proper pregrowth surface treatment, 6H films were grown on 6H substrates with tilt angles as small as 0.1 degrees. In addition, 3C could be induced to grow within selected regions on a 6H substrate. The polarity of the substrate was a large factor in the incorporation of dopants during epitaxial growth. A new growth model is discussed which explains the control of SiC polytype in epitaxial growth on vicinal (0001) SiC substrates.

Dynamic Curvature and Stress Studies for MBE CdTe on Si and GaAs Substrates

NASA Astrophysics Data System (ADS)

Jacobs, R. N.; Jaime Vasquez, M.; Lennon, C. M.; Nozaki, C.; Almeida, L. A.; Pellegrino, J.; Arias, J.; Taylor, C.; Wissman, B.

2015-09-01

Infrared focal plane arrays (IRFPA) based on HgCdTe semiconductor alloys have been shown to be ideal for tactical and strategic applications. High density (>1 M pixel), high operability HgCdTe detectors on large area, low-cost composite substrates, such as CdTe-buffered Si or GaAs, are envisioned for next-generation IRFPAs. Thermal expansion mismatch is among various material parameters that govern the structural properties of the final detector layer. It has previously been shown that thermal expansion mismatch plays the dominant role in the residual stress characteristics of these heteroepitaxial structures (Jacobs et al. in J Electron Mater 37:1480, 2008). The wafer curvature (bowing) resulting from residual stress, is a likely source of problems that may occur during subsequent processing. This includes cracking of the film and substrate during post-growth annealing processes or even certain characterization techniques. In this work, we examine dynamic curvature and stress during molecular beam epitaxy (MBE), of CdTe on Si and GaAs substrates. The effect of temperature changes on wafer curvature throughout the growth sequence is documented using a multi-beam optical sensor developed by K-Space Associates. This monitoring technique makes possible the study of growth sequences which employ annealing schemes and/or interlayers to influence the final residual stress state of the heteroepitaxial structures.

Single crystal and polycrystalline GaAs solar cells using AMOS technology

NASA Technical Reports Server (NTRS)

Stirn, R. J.; Yeh, Y. C. M.

1976-01-01

A description is given of current technology for fabricating single AMOS (antireflection-coated metal oxide semiconductor) solar cells, with attention given to thermal, plasma, and anodic oxidation, native oxide stripping, and X-ray photoelectron spectroscopy results. Some preliminary results are presented on the chemistry and electrical characterization of such cells, and the characteristics of cells fabricated on sliced polycrystalline GaAs wafers are examined. Consideration is also given to the recrystallization of evaporated Ge films for use as low-cost substrates for polycrystalline GaAs solar cells.

Reflective optical imaging systems with balanced distortion

DOEpatents

Hudyma, Russell M.

2001-01-01

Optical systems compatible with extreme ultraviolet radiation comprising four reflective elements for projecting a mask image onto a substrate are described. The four optical elements comprise, in order from object to image, convex, concave, convex and concave mirrors. The optical systems are particularly suited for step and scan lithography methods. The invention enables the use of larger slit dimensions associated with ring field scanning optics, improves wafer throughput, and allows higher semiconductor device density. The inventive optical systems are characterized by reduced dynamic distortion because the static distortion is balanced across the slit width.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

Micro-Raman spectroscopy as a tool for the characterization of silicon carbide in power semiconductor material processing

NASA Astrophysics Data System (ADS)

De Biasio, M.; Kraft, M.; Schultz, M.; Goller, B.; Sternig, D.; Esteve, R.; Roesner, M.

2017-05-01

Silicon carbide (SiC) is a wide band-gap semi-conductor material that is used increasingly for high voltage power devices, since it has a higher breakdown field strength and better thermal conductivity than silicon. However, in particular its hardness makes wafer processing difficult and many standard semi-conductor processes have to be specially adapted. We measure the effects of (i) mechanical processing (i.e. grinding of the backside) and (ii) chemical and thermal processing (i.e. doping and annealing), using confocal microscopy to measure the surface roughness of ground wafers and micro-Raman spectroscopy to measure the stresses induced in the wafers by grinding. 4H-SiC wafers with different dopings were studied before and after annealing, using depth-resolved micro-Raman spectroscopy to observe how doping and annealing affect: i.) the damage and stresses induced on the crystalline structure of the samples and ii.) the concentration of free electrical carriers. Our results show that mechanical, chemical and thermal processing techniques have effects on this semiconductor material that can be observed and characterized using confocal microscopy and high resolution micro Raman spectroscopy.

Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

NASA Astrophysics Data System (ADS)

Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

2017-06-01

As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

1.3-microm optically-pumped semiconductor disk laser by wafer fusion.

PubMed

Lyytikäinen, Jari; Rautiainen, Jussi; Toikkanen, Lauri; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

2009-05-25

We report a wafer-fused high power optically-pumped semiconductor disk laser operating at 1.3 microm. An InP-based active medium was fused with a GaAs/AlGaAs distributed Bragg reflector, resulting in an integrated monolithic gain mirror. Over 2.7 W of output power, obtained at temperature of 15 degrees C, represents the best achievement reported to date for this type of lasers. The results reveal an essential advantage of the wafer fusing technique over both monolithically grown AlGaInAs/GaInAsP- and GaInNAs-based structures.

Reduction of B-integral accumulation in lasers

DOEpatents

Meyerhofer, David D.; Konoplev, Oleg A.

2000-01-01

A pulsed laser is provided wherein the B-integral accumulated in the laser pulse is reduced using a semiconductor wafer. A laser pulse is generated by a laser pulse source. The laser pulse passes through a semiconductor wafer that has a negative nonlinear index of refraction. Thus, the laser pulse accumulates a negative B-integral. The laser pulse is then fed into a laser amplification medium, which has a positive nonlinear index of refraction. The laser pulse may make a plurality of passes through the laser amplification medium and accumulate a positive B-integral during a positive non-linear phase change. The semiconductor and laser pulse wavelength are chosen such that the negative B-integral accumulated in the semiconductor wafer substantially cancels the positive B-integral accumulated in the laser amplification medium. There may be additional accumulation of positive B-integral if the laser pulse passes through additional optical mediums such as a lens or glass plates. Thus, the effects of self-phase modulation in the laser pulse are substantially reduced.

Noncontact sheet resistance measurement technique for wafer inspection

NASA Astrophysics Data System (ADS)

Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

1995-12-01

A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

Broadband infrared absorption enhancement by electroless-deposited silver nanoparticles

NASA Astrophysics Data System (ADS)

Gritti, Claudia; Raza, Søren; Kadkhodazadeh, Shima; Kardynal, Beata; Malureanu, Radu; Mortensen, N. Asger; Lavrinenko, Andrei V.

2017-01-01

Decorating semiconductor surfaces with plasmonic nanoparticles (NPs) is considered a viable solution for enhancing the absorptive properties of photovoltaic and photodetecting devices. We propose to deposit silver NPs on top of a semiconductor wafer by a cheap and fast electroless plating technique. Optical characterization confirms that the random array of electroless-deposited NPs improves absorption by up to 20% in a broadband of near-infrared frequencies from the bandgap edge to 2000 nm. Due to the small filling fraction of particles, the reflection in the visible range is practically unchanged, which points to the possible applications of such deposition method for harvesting photons in nanophotonics and photovoltaics. The broadband absorption is a consequence of the resonant behavior of particles with different shapes and sizes, which strongly localize the incident light at the interface of a high-index semiconductor substrate. Our hypothesis is substantiated by examining the plasmonic response of the electroless-deposited NPs using both electron energy loss spectroscopy and numerical calculations.

Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

NASA Astrophysics Data System (ADS)

Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

2005-09-01

The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore the capability of the tool for characterizing multiple geometric parameters associated with the manufacturing process that are important to the yield and performance of advanced bottle DRAM devices.

Apparatus for use in examining the lattice of a semiconductor wafer by X-ray diffraction

NASA Technical Reports Server (NTRS)

Parker, D. L.; Porter, W. A. (Inventor)

1978-01-01

An improved apparatus for examining the crystal lattice of a semiconductor wafer utilizing X-ray diffraction techniques was presented. The apparatus is employed in a method which includes the step of recording the image of a wafer supported in a bent configuration conforming to a compound curve, produced through the use of a vacuum chuck provided for an X-ray camera. The entire surface thereof is illuminated simultaneously by a beam of incident X-rays which are projected from a distant point-source and satisfy conditions of the Bragg Law for all points on the surface of the water.

Visualization and minimization of clustering of micro-pillars and walls due to liquid film evaporation

NASA Astrophysics Data System (ADS)

Kim, Tae-Hong; Kim, Jungchul; Kim, Ho-Young

2013-11-01

The spin drying, in which a rinsing liquid deposited on a wafer is rapidly dried by wafer spinning, is an essential step in the semiconductor manufacturing process. While the liquid evaporates, its meniscus straddles neighboring submicron-size patterns such as pillars and walls. Then the capillary effects that pull the patterns together may lead to direct contact of the patterns, which is often referred to as pattern leaning. This poses a problem becoming more and more serious as the pattern size shrinks and the aspect ratio of the patterns increases. While the clustering behavior of high-aspect-ratio micro- and nanopillars was investigated before, a technical strategy to prevent such clustering has been pursed in industrial practices without being supported by the recently established theory of elastocapillarity. Here we visualize the clustering behavior of polymer micropatterns with the evaporation of liquid film while varying the sizes and temperature of the micropatterns. We find a critical role of substrate temperature in preventing the leaning of the patterns via changing the evaporation rate and behavior of the liquid film. Also, we construct a regime map that guides us to find a process condition to avoid pattern leaning in semiconductor manufacturing. This work was supported by the National Research Foundation of Korea (grant no. 2012-008023).

Reflective optical imaging system with balanced distortion

DOEpatents

Chapman, Henry N.; Hudyma, Russell M.; Shafer, David R.; Sweeney, Donald W.

1999-01-01

An optical system compatible with short wavelength (extreme ultraviolet) An optical system compatible with short wavelength (extreme ultraviolet) radiation comprising four reflective elements for projecting a mask image onto a substrate. The four optical elements comprise, in order from object to image, convex, concave, convex and concave mirrors. The optical system is particularly suited for step and scan lithography methods. The invention enables the use of larger slit dimensions associated with ring field scanning optics, improves wafer throughput and allows higher semiconductor device density. The inventive optical system is characterized by reduced dynamic distortion because the static distortion is balanced across the slit width.

Optical cavity furnace for semiconductor wafer processing

DOEpatents

Sopori, Bhushan L.

2014-08-05

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2012 CFR

2012-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2013 CFR

2013-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2014 CFR

2014-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Laser furnace and method for zone refining of semiconductor wafers

NASA Technical Reports Server (NTRS)

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kang, Dongseok; Young, James L.; Lim, Haneol

Despite their excellent photophysical properties and record-high solar-to-hydrogen conversion efficiency, the high cost and limited stability of III-V compound semiconductors prohibit their practical application in solar-driven photoelectrochemical water splitting. Here in this paper we present a strategy for III-V photocatalysis that can circumvent these difficulties via printed assemblies of epitaxially grown compound semiconductors. A thin film stack of GaAs-based epitaxial materials is released from the growth wafer and printed onto a non-native transparent substrate to form an integrated photocatalytic electrode for solar hydrogen generation. The heterogeneously integrated electrode configuration together with specialized epitaxial design serve to decouple the material interfacesmore » for illumination and electrocatalysis. Subsequently, this allows independent control and optimization of light absorption, carrier transport, charge transfer, and material stability. Using this approach, we construct a series-connected wireless tandem system of GaAs photoelectrodes and demonstrate 13.1% solar-to-hydrogen conversion efficiency of unassisted-mode water splitting.« less

Wafer defect detection by a polarization-insensitive external differential interference contrast module.

PubMed

Nativ, Amit; Feldman, Haim; Shaked, Natan T

2018-05-01

We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

NASA Astrophysics Data System (ADS)

Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

2017-09-01

The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

Exploring synchrotron radiation capabilities: The ALS-Intel CRADA

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gozzo, F.; Cossy-Favre, A; Trippleet, B.

1997-04-01

Synchrotron radiation spectroscopy and spectromicroscopy were applied, at the Advanced Light Source, to the analysis of materials and problems of interest to the commercial semiconductor industry. The authors discuss some of the results obtained at the ALS using existing capabilities, in particular the small spot ultra-ESCA instrument on beamline 7.0 and the AMS (Applied Material Science) endstation on beamline 9.3.2. The continuing trend towards smaller feature size and increased performance for semiconductor components has driven the semiconductor industry to invest in the development of sophisticated and complex instrumentation for the characterization of microstructures. Among the crucial milestones established by themore » Semiconductor Industry Association are the needs for high quality, defect free and extremely clean silicon wafers, very thin gate oxides, lithographies near 0.1 micron and advanced material interconnect structures. The requirements of future generations cannot be met with current industrial technologies. The purpose of the ALS-Intel CRADA (Cooperative Research And Development Agreement) is to explore, compare and improve the utility of synchrotron-based techniques for practical analysis of substrates of interest to semiconductor chip manufacturing. The first phase of the CRADA project consisted in exploring existing ALS capabilities and techniques on some problems of interest. Some of the preliminary results obtained on Intel samples are discussed here.« less

Reducing the substrate dependent scanner leveling effect in low-k1 contact printing

NASA Astrophysics Data System (ADS)

Chang, C. S.; Tseng, C. F.; Huang, C. H.; Yang, Elvis; Yang, T. H.; Chen, K. C.

2015-03-01

As the scaling down of design rule for high-density memory device, the small depth of focus (DoF) budget may be deteriorated by focus leveling errors, which arises in unpredicted reflectivity from multilayer structures on the topographic wafer. The leveling sensors of ASML scanner use near infrared (NIR) range wavelength which can penetrate through most of films using in semiconductor fabrication such as photo-resist, bottom anti reflective coating (BARC) and dielectric materials. Consequently, the reflected light from underlying substructures would disturb leveling sensors from accurate leveling. The different pattern densities and layout characteristics between array and periphery of a memory chip are expected to result in different leveling signals. Furthermore, the process dependent variations between wafer central and edge areas are also considered to yield different leveling performances during wafer exposure. In this study, lower blind contact immunity was observed for peripheral contacts comparing to the array contacts especially around wafer edge region. In order to overcome this problem, a series of investigations have been carried out. The wafer edge leveling optimization through circuit dependent focus edge clearance (CDFEC) option doesn't get improvement. Air gauge improved process leveling (AGILE) function of ASML immersion scanner doesn't show improved result either. The ILD uniformity improvement and step height treatments around wafer edge such as edge exclusion of film deposition and bevel etching are also ineffective to mitigate the blind contact problem of peripheral patterns. Altering the etch hard-mask stack is finally found to be an effective approach to alleviate the issue. For instance, through either containing high temperature deposition advanced patterning film (APF) in the hard-mask or inserting higher opaque film such as amorphous Si in between the hard-mask stack.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

Relation between sick leave and selected exposure variables among women semiconductor workers in Malaysia

PubMed Central

Chee, H; Rampal, K

2003-01-01

Aims: To determine the relation between sick leave and selected exposure variables among women semiconductor workers. Methods: This was a cross sectional survey of production workers from 18 semiconductor factories. Those selected had to be women, direct production operators up to the level of line leader, and Malaysian citizens. Sick leave and exposure to physical and chemical hazards were determined by self reporting. Three sick leave variables were used; number of sick leave days taken in the past year was the variable of interest in logistic regression models where the effects of age, marital status, work task, work schedule, work section, and duration of work in factory and work section were also explored. Results: Marital status was strongly linked to the taking of sick leave. Age, work schedule, and duration of work in the factory were significant confounders only in certain cases. After adjusting for these confounders, chemical and physical exposures, with the exception of poor ventilation and smelling chemicals, showed no significant relation to the taking of sick leave within the past year. Work section was a good predictor for taking sick leave, as wafer polishing workers faced higher odds of taking sick leave for each of the three cut off points of seven days, three days, and not at all, while parts assembly workers also faced significantly higher odds of taking sick leave. Conclusion: In Malaysia, the wafer fabrication factories only carry out a limited portion of the work processes, in particular, wafer polishing and the processes immediately prior to and following it. This study, in showing higher illness rates for workers in wafer polishing compared to semiconductor assembly, has implications for the governmental policy of encouraging the setting up of wafer fabrication plants with the full range of work processes. PMID:12660374

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Low-Temperature Wafer-Scale Deposition of Continuous 2D SnS2 Films.

PubMed

Mattinen, Miika; King, Peter J; Khriachtchev, Leonid; Meinander, Kristoffer; Gibbon, James T; Dhanak, Vin R; Räisänen, Jyrki; Ritala, Mikko; Leskelä, Markku

2018-04-19

Semiconducting 2D materials, such as SnS 2 , hold immense potential for many applications ranging from electronics to catalysis. However, deposition of few-layer SnS 2 films has remained a great challenge. Herein, continuous wafer-scale 2D SnS 2 films with accurately controlled thickness (2 to 10 monolayers) are realized by combining a new atomic layer deposition process with low-temperature (250 °C) postdeposition annealing. Uniform coating of large-area and 3D substrates is demonstrated owing to the unique self-limiting growth mechanism of atomic layer deposition. Detailed characterization confirms the 1T-type crystal structure and composition, smoothness, and continuity of the SnS 2 films. A two-stage deposition process is also introduced to improve the texture of the films. Successful deposition of continuous, high-quality SnS 2 films at low temperatures constitutes a crucial step toward various applications of 2D semiconductors. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Encapsulation of Au Nanoparticles on a Silicon Wafer During Thermal Oxidation

PubMed Central

2013-01-01

We report the behavior of Au nanoparticles anchored onto a Si(111) substrate and the evolution of the combined structure with annealing and oxidation. Au nanoparticles, formed by annealing a Au film, appear to “float” upon a growing layer of SiO2 during oxidation at high temperature, yet they also tend to become partially encapsulated by the growing silica layers. It is proposed that this occurs largely because of the differential growth rates of the silica layer on the silicon substrate between the particles and below the particles due to limited access of oxygen to the latter. This in turn is due to a combination of blockage of oxygen adsorption by the Au and limited oxygen diffusion under the gold. We think that such behavior is likely to be seen for other metal–semiconductor systems. PMID:24163715

Chemical Vapor Deposition Of Silicon Carbide

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Larkin, David J.; Matus, Lawrence G.; Petit, Jeremy B.

1993-01-01

Large single-crystal SiC boules from which wafers of large area cut now being produced commerically. Availability of wafers opens door for development of SiC semiconductor devices. Recently developed chemical vapor deposition (CVD) process produces thin single-crystal SiC films on SiC wafers. Essential step in sequence of steps used to fabricate semiconductor devices. Further development required for specific devices. Some potential high-temperature applications include sensors and control electronics for advanced turbine engines and automobile engines, power electronics for electromechanical actuators for advanced aircraft and for space power systems, and equipment used in drilling of deep wells. High-frequency applications include communication systems, high-speed computers, and microwave power transistors. High-radiation applications include sensors and controls for nuclear reactors.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

GaN-on-Silicon - Present capabilities and future directions

NASA Astrophysics Data System (ADS)

Boles, Timothy

2018-02-01

Gallium Nitride, in the form of epitaxial HEMT transistors on various substrate materials, is the newest and most promising semiconductor technology for high performance devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-Silicon based devices and MMIC's which enable both state-of-the-art high frequency functionality and the ability to scale production into large wafer diameter CMOS foundries. The design and development of GaN-on-Silicon structures and devices will be presented beginning with the basic material parameters, growth of the required epitaxial construction, and leading to the fundamental operational theory of high frequency, high power HEMTs. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including inherent frequency limiting transit time analysis, required impedance transformations, internal and external parasitic reactance, thermal impedance optimization, and challenges improved by full integration into monolithic MMICs. Lastly, future directions for implementing GaN-on-Silicon into mainstream CMOS silicon semiconductor technologies will be discussed.

Multijunction high-voltage solar cell

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.; Goradia, C.; Chai, A. T.

1981-01-01

Multijunction cell allows for fabrication of high-voltage solar cell on single semiconductor wafer. Photovoltaic energy source using cell is combined on wafer with circuit it is to power. Cell consists of many voltage-generating regions internally or externally interconnected to give desired voltage and current combination. For computer applications, module is built on silicon wafer with energy for internal information processing and readouts derived from external light source.

Method of fabricating germanium and gallium arsenide devices

NASA Technical Reports Server (NTRS)

Jhabvala, Murzban (Inventor)

1990-01-01

A method of semiconductor diode fabrication is disclosed which relies on the epitaxial growth of a precisely doped thickness layer of gallium arsenide or germanium on a semi-insulating or intrinsic substrate, respectively, of gallium arsenide or germanium by either molecular beam epitaxy (MBE) or by metal-organic chemical vapor deposition (MOCVD). The method involves: depositing a layer of doped or undoped silicon dioxide on a germanium or gallium arsenide wafer or substrate, selectively removing the silicon dioxide layer to define one or more surface regions for a device to be fabricated thereon, growing a matched epitaxial layer of doped germanium or gallium arsenide of an appropriate thickness using MBE or MOCVD techniques on both the silicon dioxide layer and the defined one or more regions; and etching the silicon dioxide and the epitaxial material on top of the silicon dioxide to leave a matched epitaxial layer of germanium or gallium arsenide on the germanium or gallium arsenide substrate, respectively, and upon which a field effect device can thereafter be formed.

Method for photolithographic definition of recessed features on a semiconductor wafer utilizing auto-focusing alignment

DOEpatents

Farino, A.J.; Montague, S.; Sniegowski, J.J.; Smith, J.H.; McWhorter, P.J.

1998-07-21

A method is disclosed for photolithographically defining device features up to the resolution limit of an auto-focusing projection stepper when the device features are to be formed in a wafer cavity at a depth exceeding the depth of focus of the stepper. The method uses a focusing cavity located in a die field at the position of a focusing light beam from the auto-focusing projection stepper, with the focusing cavity being of the same depth as one or more adjacent cavities wherein a semiconductor device is to be formed. The focusing cavity provides a bottom surface for referencing the focusing light beam and focusing the stepper at a predetermined depth below the surface of the wafer, whereat the device features are to be defined. As material layers are deposited in each device cavity to build up a semiconductor structure such as a microelectromechanical system (MEMS) device, the same material layers are deposited in the focusing cavity, raising the bottom surface and re-focusing the stepper for accurately defining additional device features in each succeeding material layer. The method is especially applicable for forming MEMS devices within a cavity or trench and integrating the MEMS devices with electronic circuitry fabricated on the wafer surface. 15 figs.

Method for photolithographic definition of recessed features on a semiconductor wafer utilizing auto-focusing alignment

DOEpatents

Farino, Anthony J.; Montague, Stephen; Sniegowski, Jeffry J.; Smith, James H.; McWhorter, Paul J.

1998-01-01

A method is disclosed for photolithographically defining device features up to the resolution limit of an auto-focusing projection stepper when the device features are to be formed in a wafer cavity at a depth exceeding the depth of focus of the stepper. The method uses a focusing cavity located in a die field at the position of a focusing light beam from the auto-focusing projection stepper, with the focusing cavity being of the same depth as one or more adjacent cavities wherein a semiconductor device is to be formed. The focusing cavity provides a bottom surface for referencing the focusing light beam and focusing the stepper at a predetermined depth below the surface of the wafer, whereat the device features are to be defined. As material layers are deposited in each device cavity to build up a semiconductor structure such as a microelectromechanical system (MEMS) device, the same material layers are deposited in the focusing cavity, raising the bottom surface and re-focusing the stepper for accurately defining additional device features in each succeeding material layer. The method is especially applicable for forming MEMS devices within a cavity or trench and integrating the MEMS devices with electronic circuitry fabricated on the wafer surface.

A spatially resolved retarding field energy analyzer design suitable for uniformity analysis across the surface of a semiconductor wafer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sharma, S., E-mail: shailesh.sharma6@mail.dcu.ie; National Centre for Plasma Science and Technology, Dublin City University, Glasnevin, Dublin 9; Gahan, D., E-mail: david.gahan@impedans.com

2014-04-15

A novel retarding field energy analyzer design capable of measuring the spatial uniformity of the ion energy and ion flux across the surface of a semiconductor wafer is presented. The design consists of 13 individual, compact-sized, analyzers, all of which are multiplexed and controlled by a single acquisition unit. The analyzers were tested to have less than 2% variability from unit to unit due to tight manufacturing tolerances. The main sensor assembly consists of a 300 mm disk to mimic a semiconductor wafer and the plasma sampling orifices of each sensor are flush with disk surface. This device is placedmore » directly on top of the rf biased electrode, at the wafer location, in an industrial capacitively coupled plasma reactor without the need for any modification to the electrode structure. The ion energy distribution, average ion energy, and average ion flux were measured at the 13 locations over the surface of the powered electrode to determine the degree of spatial nonuniformity. The ion energy and ion flux are shown to vary by approximately 20% and 5%, respectively, across the surface of the electrode for the range of conditions investigated in this study.« less

Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

NASA Astrophysics Data System (ADS)

Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

2003-07-01

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Design Considerations in Capacitively Coupled Plasmas

NASA Astrophysics Data System (ADS)

Song, Sang-Heon; Ventzek, Peter; Ranjan, Alok

2015-11-01

Microelectronics industry has driven transistor feature size scaling from 10-6 m to 10-9 m during the past 50 years, which is often referred to as Moore's law. It cannot be overstated that today's information technology would not have been so successful without plasma material processing. One of the major plasma sources for the microelectronics fabrication is capacitively coupled plasmas (CCPs). The CCP reactor has been intensively studied and developed for the deposition and etching of different films on the silicon wafer. As the feature size gets to around 10 nm, the requirement for the process uniformity is less than 1-2 nm across the wafer (300 mm). In order to achieve the desired uniformity, the hardware design should be as precise as possible before the fine tuning of process condition is applied to make it even better. In doing this procedure, the computer simulation can save a significant amount of resources such as time and money which are critical in the semiconductor business. In this presentation, we compare plasma properties using a 2-dimensional plasma hydrodynamics model for different kinds of design factors that can affect the plasma uniformity. The parameters studied in this presentation include chamber accessing port, pumping port, focus ring around wafer substrate, and the geometry of electrodes of CCP.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers.

PubMed

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-03-04

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers

PubMed Central

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-01-01

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications. PMID:26940260

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

NASA Astrophysics Data System (ADS)

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Waterproof AlInGaP optoelectronics on stretchable substrates with applications in biomedicine and robotics.

PubMed

Kim, Rak-Hwan; Kim, Dae-Hyeong; Xiao, Jianliang; Kim, Bong Hoon; Park, Sang-Il; Panilaitis, Bruce; Ghaffari, Roozbeh; Yao, Jimin; Li, Ming; Liu, Zhuangjian; Malyarchuk, Viktor; Kim, Dae Gon; Le, An-Phong; Nuzzo, Ralph G; Kaplan, David L; Omenetto, Fiorenzo G; Huang, Yonggang; Kang, Zhan; Rogers, John A

2010-11-01

Inorganic light-emitting diodes and photodetectors represent important, established technologies for solid-state lighting, digital imaging and many other applications. Eliminating mechanical and geometrical design constraints imposed by the supporting semiconductor wafers can enable alternative uses in areas such as biomedicine and robotics. Here we describe systems that consist of arrays of interconnected, ultrathin inorganic light-emitting diodes and photodetectors configured in mechanically optimized layouts on unusual substrates. Light-emitting sutures, implantable sheets and illuminated plasmonic crystals that are compatible with complete immersion in biofluids illustrate the suitability of these technologies for use in biomedicine. Waterproof optical-proximity-sensor tapes capable of conformal integration on curved surfaces of gloves and thin, refractive-index monitors wrapped on tubing for intravenous delivery systems demonstrate possibilities in robotics and clinical medicine. These and related systems may create important, unconventional opportunities for optoelectronic devices.

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

PubMed

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.

The microwave Hall effect measured using a waveguide tee

DOE Office of Scientific and Technical Information (OSTI.GOV)

Coppock, J. E.; Anderson, J. R.; Johnson, W. B.

2016-03-14

This paper describes a simple microwave apparatus to measure the Hall effect in semiconductor wafers. The advantage of this technique is that it does not require contacts on the sample or the use of a resonant cavity. Our method consists of placing the semiconductor wafer into a slot cut in an X-band (8–12 GHz) waveguide series tee, injecting microwave power into the two opposite arms of the tee, and measuring the microwave output at the third arm. A magnetic field applied perpendicular to the wafer gives a microwave Hall signal that is linear in the magnetic field and which reverses phasemore » when the magnetic field is reversed. The microwave Hall signal is proportional to the semiconductor mobility, which we compare for calibration purposes with d.c. mobility measurements obtained using the van der Pauw method. We obtain the resistivity by measuring the microwave reflection coefficient of the sample. This paper presents data for silicon and germanium samples doped with boron or phosphorus. The measured mobilities ranged from 270 to 3000 cm{sup 2}/(V s).« less

Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muir, R.; Heebner, J.

In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

DOE PAGES

Muir, R.; Heebner, J.

2017-10-24

In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

Metal-Free CVD Graphene Synthesis on 200 mm Ge/Si(001) Substrates.

PubMed

Lukosius, M; Dabrowski, J; Kitzmann, J; Fursenko, O; Akhtar, F; Lisker, M; Lippert, G; Schulze, S; Yamamoto, Y; Schubert, M A; Krause, H M; Wolff, A; Mai, A; Schroeder, T; Lupina, G

2016-12-14

Good quality, complementary-metal-oxide-semiconductor (CMOS) technology compatible, 200 mm graphene was obtained on Ge(001)/Si(001) wafers in this work. Chemical vapor depositions were carried out at the deposition temperatures of 885 °C using CH 4 as carbon source on epitaxial Ge(100) layers, which were grown on Si(100), prior to the graphene synthesis. Graphene layer with the 2D/G ratio ∼3 and low D mode (i.e., low concentration of defects) was measured over the entire 200 mm wafer by Raman spectroscopy. A typical full-width-at-half-maximum value of 39 cm -1 was extracted for the 2D mode, further indicating that graphene of good structural quality was produced. The study also revealed that the lack of interfacial oxide correlates with superior properties of graphene. In order to evaluate electrical properties of graphene, its 2 × 2 cm 2 pieces were transferred onto SiO 2 /Si substrates from Ge/Si wafers. The extracted sheet resistance and mobility values of transferred graphene layers were ∼1500 ± 100 Ω/sq and μ ≈ 400 ± 20 cm 2 /V s, respectively. The transferred graphene was free of metallic contaminations or mechanical damage. On the basis of results of DFT calculations, we attribute the high structural quality of graphene grown by CVD on Ge to hydrogen-induced reduction of nucleation probability, explain the appearance of graphene-induced facets on Ge(001) as a kinetic effect caused by surface step pinning at linear graphene nuclei, and clarify the orientation of graphene domains on Ge(001) as resulting from good lattice matching between Ge(001) and graphene nucleated on such nuclei.

Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

NASA Astrophysics Data System (ADS)

Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

2005-12-01

To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

Patterned wafer geometry grouping for improved overlay control

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

2017-03-01

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

Algan/Gan Hemt By Magnetron Sputtering System

NASA Astrophysics Data System (ADS)

Garcia Perez, Roman

In this thesis, the growth of the semiconductor materials AlGaN and GaN is achieved by magnetron sputtering for the fabrication of High Electron Mobility Transistors (HEMTs). The study of the deposited nitrides is conducted by spectroscopy, diffraction, and submicron scale microscope methods. The preparation of the materials is performed using different parameters in terms of power, pressure, temperature, gas, and time. Silicon (Si) and Sapphire (Al2O3) wafers are used as substrates. The chemical composition and surface topography of the samples are analyzed to calculate the materials atomic percentages and to observe the devices surface. The instruments used for the semiconductors characterization are X-ray Photoelectron Spectroscopy (XPS), X-ray Diffraction (XRD), Scanning Electron Microscopy (SEM), and Atomic Force Microscope (AFM). The project focused its attention on the reduction of impurities during the deposition, the controlled thicknesses of the thin-films, the atomic configuration of the alloy AlxGa1-xN, and the uniformity of the surfaces.

Semiconductor-metal phase transition of vanadium dioxide nanostructures on silicon substrate: Applications for thermal control of spacecraft

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leahu, G. L., E-mail: roberto.livoti@uniroma1.it; Li Voti, R., E-mail: roberto.livoti@uniroma1.it; Larciprete, M. C., E-mail: roberto.livoti@uniroma1.it

2014-06-19

We present a detailed infrared study of the semiconductor-to-metal transition (SMT) in a vanadium dioxide (VO2) film deposited on silicon wafer. The VO2 phase transition is studied in the mid-infrared (MIR) region by analyzing the transmittance and the reflectance measurements, and the calculated emissivity. The temperature behaviour of the emissivity during the SMT put into evidence the phenomenon of the anomalous absorption in VO2 which has been explained by applying the Maxwell Garnett effective medium approximation theory, together with a strong hysteresis phenomenon, both useful to design tunable thermal devices to be applied for the thermal control of spacecraft. Wemore » have also applied the photothermal radiometry in order to study the changes in the modulated emissivity induced by laser. Experimental results show how the use of these techniques represent a good tool for a quantitative measurement of the optothermal properties of vanadium dioxide based structures.« less

Printed assemblies of GaAs photoelectrodes with decoupled optical and reactive interfaces for unassisted solar water splitting

DOE PAGES

Kang, Dongseok; Young, James L.; Lim, Haneol; ...

2017-03-27

Despite their excellent photophysical properties and record-high solar-to-hydrogen conversion efficiency, the high cost and limited stability of III-V compound semiconductors prohibit their practical application in solar-driven photoelectrochemical water splitting. Here in this paper we present a strategy for III-V photocatalysis that can circumvent these difficulties via printed assemblies of epitaxially grown compound semiconductors. A thin film stack of GaAs-based epitaxial materials is released from the growth wafer and printed onto a non-native transparent substrate to form an integrated photocatalytic electrode for solar hydrogen generation. The heterogeneously integrated electrode configuration together with specialized epitaxial design serve to decouple the material interfacesmore » for illumination and electrocatalysis. Subsequently, this allows independent control and optimization of light absorption, carrier transport, charge transfer, and material stability. Using this approach, we construct a series-connected wireless tandem system of GaAs photoelectrodes and demonstrate 13.1% solar-to-hydrogen conversion efficiency of unassisted-mode water splitting.« less

Printed assemblies of GaAs photoelectrodes with decoupled optical and reactive interfaces for unassisted solar water splitting

NASA Astrophysics Data System (ADS)

Kang, Dongseok; Young, James L.; Lim, Haneol; Klein, Walter E.; Chen, Huandong; Xi, Yuzhou; Gai, Boju; Deutsch, Todd G.; Yoon, Jongseung

2017-03-01

Despite their excellent photophysical properties and record-high solar-to-hydrogen conversion efficiency, the high cost and limited stability of III-V compound semiconductors prohibit their practical application in solar-driven photoelectrochemical water splitting. Here we present a strategy for III-V photocatalysis that can circumvent these difficulties via printed assemblies of epitaxially grown compound semiconductors. A thin film stack of GaAs-based epitaxial materials is released from the growth wafer and printed onto a non-native transparent substrate to form an integrated photocatalytic electrode for solar hydrogen generation. The heterogeneously integrated electrode configuration together with specialized epitaxial design serve to decouple the material interfaces for illumination and electrocatalysis. Subsequently, this allows independent control and optimization of light absorption, carrier transport, charge transfer, and material stability. Using this approach, we construct a series-connected wireless tandem system of GaAs photoelectrodes and demonstrate 13.1% solar-to-hydrogen conversion efficiency of unassisted-mode water splitting.

Direct oriented growth of armchair graphene nanoribbons on germanium

PubMed Central

Jacobberger, Robert M.; Kiraly, Brian; Fortin-Deschenes, Matthieu; Levesque, Pierre L.; McElhinny, Kyle M.; Brady, Gerald J.; Rojas Delgado, Richard; Singha Roy, Susmit; Mannix, Andrew; Lagally, Max G.; Evans, Paul G.; Desjardins, Patrick; Martel, Richard; Hersam, Mark C.; Guisinger, Nathan P.; Arnold, Michael S.

2015-01-01

Graphene can be transformed from a semimetal into a semiconductor if it is confined into nanoribbons narrower than 10 nm with controlled crystallographic orientation and well-defined armchair edges. However, the scalable synthesis of nanoribbons with this precision directly on insulating or semiconducting substrates has not been possible. Here we demonstrate the synthesis of graphene nanoribbons on Ge(001) via chemical vapour deposition. The nanoribbons are self-aligning 3° from the Ge〈110〉 directions, are self-defining with predominantly smooth armchair edges, and have tunable width to <10 nm and aspect ratio to >70. In order to realize highly anisotropic ribbons, it is critical to operate in a regime in which the growth rate in the width direction is especially slow, <5 nm h−1. This directional and anisotropic growth enables nanoribbon fabrication directly on conventional semiconductor wafer platforms and, therefore, promises to allow the integration of nanoribbons into future hybrid integrated circuits. PMID:26258594

Silicon-on-insulator with hybrid orientations for heterogeneous integration of GaN on Si (100) substrate

NASA Astrophysics Data System (ADS)

Zhang, Runchun; Zhao, Beiji; Huang, Kai; You, Tiangui; Jia, Qi; Lin, Jiajie; Zhang, Shibin; Yan, Youquan; Yi, Ailun; Zhou, Min; Ou, Xin

2018-05-01

Heterogeneous integration of materials pave a new way for the development of the microsystem with miniaturization and complex functionalities. Two types of hybrid silicon on insulator (SOI) structures, i.e., Si (100)-on-Si (111) and Si (111)-on-Si (100), were prepared by the smart-cut technique, which is consist of ion-slicing and wafer bonding. The precise calculation of the lattice strain of the transferred films without the epitaxial matching relationship to the substrate was demonstrated based on X-ray diffraction (XRD) measurements. The XRD and Raman measurement results suggest that the transferred films possess single crystalline quality. With a chemical mechanical polishing (CMP) process, the surface roughness of the transferred thin films can be reduced from 5.57 nm to 0.30 nm. The 4-inch GaN thin film epitaxially grown on the as-prepared hybrid SOI of Si (111)-on-Si (100) by metalorganic chemical vapor deposition (MOCVD) is of improved quality with a full width at half maximum (FWHM) of 672.54 arcsec extracted from the XRD rocking curve and small surface roughness of 0.40 nm. The wafer-scale GaN on Si (111)-on-Si (100) can serve as a potential platform for the one chip integration of GaN-based high electron mobility transistors (HEMT) or photonics with the Si (100)-based complementary metal oxide semiconductor (CMOS).

Integration of Indium Phosphide Based Devices with Flexible Substrates

NASA Astrophysics Data System (ADS)

Chen, Wayne Huai

2011-12-01

Flexible substrates have many advantages in applications where bendability, space, or weight play important roles or where rigid circuits are undesirable. However, conventional flexible thin film transistors are typically characterized as having low carrier mobility as compared to devices used in the electronics industry. This is in part due to the limited temperature tolerance of plastic flexible substrates, which commonly reduces the highest processing temperature to below 200°C. Common approaches of implementation include low temperature deposition of organic, amorphous, or polycrystalline semiconductors, all of which result in carrier mobility well below 100 cm2V -1s-1. High quality, single crystalline III-V semiconductors such as indium phosphide (InP), on the other hand, have carrier mobility well over 1000 cm 2V-1s-1 at room temperature, depending on carrier concentration. Recently, the ion-cut process has been used in conjunction with wafer bonding to integrate thin layers of III-V material onto silicon for optoelectronic applications. This approach has the advantage of high scalability, reusability of the initial III-V substrate, and the ability to tailor the location (depth) of the layer splitting. However, the transferred substrate usually suffers from hydrogen implantation damage. This dissertation demonstrates a new approach to enable integration of InP with various substrates, called the double-flip transfer process. The process combines ion-cutting with adhesive bonding. The problem of hydrogen implantation was overcome by patterned ion-cut transfer. In this type of transfer, areas of interest are shielded from implantation but still transferred by surrounding implanted regions. We found that patterned ion-cut transfer is strongly dependent upon crystal orientation and that using cleavage-plane oriented donors can be beneficial in transferring large areas of high quality semiconductor material. InP-based devices were fabricated to demonstrate the transfer process and test functionality following transfer. Passive devices (photodetectors) as well as active transistors were transferred and fabricated on various substrates. The transferred device layers were either implanted through with a blanket implant or protected with an ion-mask during implantation. Results demonstrate the viability of the double-flip ion-cut process in achieving very high electron mobility (˜2800 cm2V-1s-1) transistors on plastic flexible substrates.

Active high-power RF switch and pulse compression system

DOEpatents

Tantawi, Sami G.; Ruth, Ronald D.; Zolotorev, Max

1998-01-01

A high-power RF switching device employs a semiconductor wafer positioned in the third port of a three-port RF device. A controllable source of directed energy, such as a suitable laser or electron beam, is aimed at the semiconductor material. When the source is turned on, the energy incident on the wafer induces an electron-hole plasma layer on the wafer, changing the wafer's dielectric constant, turning the third port into a termination for incident RF signals, and. causing all incident RF signals to be reflected from the surface of the wafer. The propagation constant of RF signals through port 3, therefore, can be changed by controlling the beam. By making the RF coupling to the third port as small as necessary, one can reduce the peak electric field on the unexcited silicon surface for any level of input power from port 1, thereby reducing risk of damaging the wafer by RF with high peak power. The switch is useful to the construction of an improved pulse compression system to boost the peak power of microwave tubes driving linear accelerators. In this application, the high-power RF switch is placed at the coupling iris between the charging waveguide and the resonant storage line of a pulse compression system. This optically controlled high power RF pulse compression system can handle hundreds of Megawatts of power at X-band.

A novel approach of chemical mechanical polishing using environment-friendly slurry for mercury cadmium telluride semiconductors

PubMed Central

Zhang, Zhenyu; Wang, Bo; Zhou, Ping; Guo, Dongming; Kang, Renke; Zhang, Bi

2016-01-01

A novel approach of chemical mechanical polishing (CMP) is developed for mercury cadmium telluride (HgCdTe or MCT) semiconductors. Firstly, fixed-abrasive lapping is used to machine the MCT wafers, and the lapping solution is deionized water. Secondly, the MCT wafers are polished using the developed CMP slurry. The CMP slurry consists of mainly SiO2 nanospheres, H2O2, and malic and citric acids, which are different from previous CMP slurries, in which corrosive and toxic chemical reagents are usually employed. Finally, the polished MCT wafers are cleaned and dried by deionized water and compressed air, respectively. The novel approach of CMP is environment-friendly. Surface roughness Ra, and peak-to-valley (PV) values of 0.45, and 4.74 nm are achieved, respectively on MCT wafers after CMP. The first and second passivating processes are observed in electrochemical measurements on MCT wafers. The fundamental mechanisms of CMP are proposed according to the X-ray photoelectron spectroscopy (XPS) and electrochemical measurements. Malic and citric acids dominate the first passivating process, and the CMP slurry governs the second process. Te4+3d peaks are absent after CMP induced by the developed CMP slurry, indicating the removing of oxidized films on MCT wafers, which is difficult to achieve using single H2O2 and malic and citric acids solutions. PMID:26926622

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

40 CFR Table I-12 to Subpart I of... - Default Emission Factors (1-Uij) for Gas Utilization Rates (Uij) and By-Product Formation Rates...

Code of Federal Regulations, 2014 CFR

2014-07-01

... Use With the Stack Test Method (300 mm and 450 mm Wafers) I Table I-12 to Subpart I of Part 98... (Bijk) for Semiconductor Manufacturing for Use With the Stack Test Method (300 mm and 450 mm Wafers...

40 CFR Table I-11 to Subpart I of... - Default Emission Factors (1-Uij) for Gas Utilization Rates (Uij) and By-Product Formation Rates...

Code of Federal Regulations, 2014 CFR

2014-07-01

... Use With the Stack Test Method (150 mm and 200 mm Wafers) I Table I-11 to Subpart I of Part 98... (Bijk) for Semiconductor Manufacturing for Use With the Stack Test Method (150 mm and 200 mm Wafers...

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

PubMed Central

Hazut, Ori; Agarwala, Arunava; Subramani, Thangavel; Waichman, Sharon; Yerushalmi, Roie

2013-01-01

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms. In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station. PMID:24326774

Consideration of correlativity between litho and etching shape

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Shinoda, Shinichi; Toyoda, Yasutaka

2012-03-01

We developed an effective method for evaluating the correlation of shape of Litho and Etching pattern. The purpose of this method, makes the relations of the shape after that is the etching pattern an index in wafer same as a pattern shape on wafer made by a lithography process. Therefore, this method measures the characteristic of the shape of the wafer pattern by the lithography process and can predict the hotspot pattern shape by the etching process. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used wafer CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and lithography management, and this has a big impact on the semiconductor market that centers on the semiconductor business. 2-dimensional shape of wafer quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. In this study, we conducted experiments for correlation method of the pattern (Measurement Based Contouring) as two-dimensional litho and etch evaluation technique. That is, observation of the identical position of a litho and etch was considered. It is possible to analyze variability of the edge of the same position with high precision.

In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

NASA Astrophysics Data System (ADS)

Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

2015-09-01

In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

High-efficiency thin-film GaAs solar cells, phase2

NASA Technical Reports Server (NTRS)

Yeh, Y. C. M.

1981-01-01

Thin GaAs epi-layers with good crystallographic quality were grown using a (100) Si-substrate on which a thin Ge epi-interlayer was grown by CVD from germane. Both antireflection-coated metal oxide semiconductor (AMOS) and n(+)/p homojunction structures were studied. The AMOS cells were fabricated on undoped-GaAs epi-layers deposited on bulk poly-Ge substrates using organo-metallic CVD film-growth, with the best achieved AM1 conversion efficiency being 9.1%. Both p-type and n(+)-type GaAs growth were optimized using 50 ppm dimethyl zinc and 1% hydrogen sulfide, respectively. A direct GaAs deposition method in fabricating ultra-thin top layer, epitaxial n(+)/p shallow homojunction solar cells on (100) GaAs substrates (without anodic thinning) was developed to produce large area (1 sq/cm) cells, with 19.4% AM1 conversion efficiency achieved. Additionally, an AM1 conversion efficiency of 18.4% (17.5% with 5% grid coverage) was achieved for a single crystal GaAs n(+)/p cell grown by OM-CVD on a Ge wafer.

Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction

DOEpatents

Tauke-Pedretti, Anna; Nielson, Gregory N; Cederberg, Jeffrey G; Cruz-Campa, Jose Luis

2015-05-12

A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell

NASA Astrophysics Data System (ADS)

Kewei, Cao; Tong, Liu; Jingming, Liu; Hui, Xie; Dongyan, Tao; Youwen, Zhao; Zhiyuan, Dong; Feng, Hui

2016-06-01

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters. Project supported by the National Natural Science Foundation of China (No. 61474104).

Composition and method for removing photoresist materials from electronic components

DOEpatents

Davenhall, Leisa B.; Rubin, James B.

2002-01-01

The invention is a combination of at least one dense phase fluid and at least one dense phase fluid modifier which can be used to contact substrates for electronic parts such as semiconductor wafers or chips to remove photoresist materials which are applied to the substrates during manufacture of the electronic parts. The dense phase fluid modifier is one selected from the group of cyclic, aliphatic or alicyclic compounds having the functional group: ##STR1## wherein Y is a carbon, oxygen, nitrogen, phosphorus or sulfur atom or a hydrocarbon group having from 1 to 10 carbon atoms, a halogen or halogenated hydrocarbon group having from 1 to 10 carbon atoms, silicon or a fluorinated silicon group; and wherein R.sub.1 and R.sub.2 can be the same or different substituents; and wherein, as in the case where X is nitrogen, R.sub.1 or R.sub.2 may not be present. The invention compositions generally are applied to the substrates in a pulsed fashion in order to remove the hard baked photoresist material remaining on the surface of the substrate after removal of soft baked photoresist material and etching of the barrier layer.

Reduction of the potential energy barrier and resistance at wafer-bonded n-GaAs/n-GaAs interfaces by sulfur passivation

NASA Astrophysics Data System (ADS)

Jackson, Michael J.; Jackson, Biyun L.; Goorsky, Mark S.

2011-11-01

Sulfur passivation and subsequent wafer-bonding treatments are demonstrated for III-V semiconductor applications using GaAs-GaAs direct wafer-bonded structures. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native-oxide-etch treatments. The electrical conductivity across a sulfur-treated 400 - °C-bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 min) at elevated temperatures (500-600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur-treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the observed temperature dependence of zero-bias conductance using a model for tunneling through a grain boundary reveals that the addition of sulfur at the interface lowered the interfacial energy barrier by 0.2 eV. The interface resistance for these sulfur-treated structures is 0.03 Ω.cm at room temperature. These results emphasize that sulfur-passivation techniques reduce interface states that otherwise limit the implementation of wafer bonding for high-efficiency solar cells and other devices.

Semiconductor Laser Joint Study Program with Rome Laboratory

DTIC Science & Technology

1994-09-01

VCSELs 3.3 Laser Wafer Growth by Molecular Beam Epitaxy 8 The VCSEL structures were grown by molecular beam ...cavity surface emittimg lasers ( VCSEL ), Optical 40 interconnects, Moelcular beam epitaxy It CECOOE 17. SECURfTY CLASWICATION SECURFlY CLASSIFICATION 1 Q...7 3.3 Laser Wafer Growth by Molecular Beam Epitax. ............ 8 3.4 VCSEL Fabrication Process ................................................

On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

PubMed

Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

2014-07-10

Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

A strain-isolation design for stretchable electronics

NASA Astrophysics Data System (ADS)

Wu, Jian; Li, Ming; Chen, Wei-Qiu; Kim, Dae-Hyeong; Kim, Yun-Soung; Huang, Yong-Gang; Hwang, Keh-Chih; Kang, Zhan; Rogers, John A.

2010-12-01

Stretchable electronics represents a direction of recent development in next-generation semiconductor devices. Such systems have the potential to offer the performance of conventional wafer-based technologies, but they can be stretched like a rubber band, twisted like a rope, bent over a pencil, and folded like a piece of paper. Isolating the active devices from strains associated with such deformations is an important aspect of design. One strategy involves the shielding of the electronics from deformation of the substrate through insertion of a compliant adhesive layer. This paper establishes a simple, analytical model and validates the results by the finite element method. The results show that a relatively thick, compliant adhesive is effective to reduce the strain in the electronics, as is a relatively short film.

MBE Growth of HgCdTe on Large-Area Si and CdZnTe Wafers for SWIR, MWIR and LWIR Detection

NASA Astrophysics Data System (ADS)

Reddy, M.; Peterson, J. M.; Lofgreen, D. D.; Franklin, J. A.; Vang, T.; Smith, E. P. G.; Wehner, J. G. A.; Kasai, I.; Bangs, J. W.; Johnson, S. M.

2008-09-01

Molecular beam epitaxy (MBE) growth of HgCdTe on large-size Si (211) and CdZnTe (211)B substrates is critical to meet the demands of extremely uniform and highly functional third-generation infrared (IR) focal-panel arrays (FPAs). We have described here the importance of wafer maps of HgCdTe thickness, composition, and the macrodefects across the wafer not only to qualify material properties against design specifications but also to diagnose and classify the MBE-growth-related issues on large-area wafers. The paper presents HgCdTe growth with exceptionally uniform composition and thickness and record low macrodefect density on large Si wafers up to 6-in in diameter for the detection of short-wave (SW), mid-wave (MW), and long-wave (LW) IR radiation. We have also proposed a cost-effective approach to use the growth of HgCdTe on low-cost Si substrates to isolate the growth- and substrate-related problems that one occasionally comes across with the CdZnTe substrates and tune the growth parameters such as growth rate, cutoff wavelength ( λ cutoff) and doping parameters before proceeding with the growth on costly large-area CdZnTe substrates. In this way, we demonstrated HgCdTe growth on large CdZnTe substrates of size 7 cm × 7 cm with excellent uniformity and low macrodefect density.

Method for removing semiconductor layers from salt substrates

DOEpatents

Shuskus, Alexander J.; Cowher, Melvyn E.

1985-08-27

A method is described for removing a CVD semiconductor layer from an alkali halide salt substrate following the deposition of the semiconductor layer. The semiconductor-substrate combination is supported on a material such as tungsten which is readily wet by the molten alkali halide. The temperature of the semiconductor-substrate combination is raised to a temperature greater than the melting temperature of the substrate but less than the temperature of the semiconductor and the substrate is melted and removed from the semiconductor by capillary action of the wettable support.

Conformal Electroless Nickel Plating on Silicon Wafers, Convex and Concave Pyramids, and Ultralong Nanowires.

PubMed

Gill, Thomas Mark; Zhao, Jiheng; Berenschot, Erwin J W; Tas, Niels; Zheng, Xiaolin

2018-06-25

Nickel (Ni) plating has garnered great commercial interest, as it provides excellent hardness, corrosion resistance, and electrical conductivity. Though Ni plating on conducting substrates is commonly employed via electrodeposition, plating on semiconductors and insulators often necessitates electroless approaches. Corresponding plating theory for deposition on planar substrates was developed as early as 1946, but for substrates with micro- and nanoscale features, very little is known of the relationships between plating conditions, Ni deposition quality, and substrate morphology. Herein, we describe the general theory and mechanisms of electroless Ni deposition on semiconducting silicon (Si) substrates, detailing plating bath failures and establishing relationships between critical plating bath parameters and the deposited Ni film quality. Through this theory, we develop two different plating recipes: galvanic displacement (GD) and autocatalytic deposition (ACD). Neither recipe requires pretreatment of the Si substrate, and both methods are capable of depositing uniform Ni films on planar Si substrates and convex Si pyramids. In comparison, ACD has better tunability than GD, and it provides a more conformal Ni coating on complex and high-aspect-ratio Si structures, such as inverse fractal Si pyramids and ultralong Si nanowires. Our methodology and theoretical analyses can be leveraged to develop electroless plating processes for other metals and metal alloys and to generally provide direction for the adaptation of electroless deposition to modern applications.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Carrier transport and collection in fully depleted semiconductors by a combined action of the space charge field and the field due to electrode voltages

DOEpatents

Rehak, P.; Gatti, E.

1984-02-24

A semiconductor charge transport device and method for making same, characterized by providing a thin semiconductor wafer having rectifying functions on its opposing major surfaces and including a small capacitance ohmic contact, in combination with bias voltage means and associated circuit means for applying a predetermined voltage to effectively deplete the wafer in regions thereof between the rectifying junctions and the ohmic contact. A charge transport device of the invention is usable as a drift chamber, a low capacitance detector, or a charge coupled device each constructed according to the methods of the invention for making such devices. Detectors constructed according to the principles of the invention are characterized by having significantly higher particle position indicating resolution than is attainable with prior art detectors, while at the same time requiring substantially fewer readout channels to realize such high resolution.

Carrier transport and collection in fully depleted semiconductors by a combined action of the space charge field and the field due to electrode voltages

DOEpatents

Rehak, Pavel; Gatti, Emilio

1987-01-01

A semiconductor charge transport device and method for making same, characterized by providing a thin semiconductor wafer having rectifying junctions on its opposing major surfaces and including a small capacitance ohmic contact, in combination with bias voltage means and associated circuit means for applying a predetermined voltage to effectively deplete the wafer in regions thereof between the rectifying junctions and the ohmic contact. A charge transport device of the invention is usable as a drift chamber, a low capacitance detector, or a charge coupled device each constructed according to the methods of the invention for making such devices. Detectors constructed according to the principles of the invention are characterized by having significantly higher particle position indicating resolution than is attainable with prior art detectors, while at the same time requiring substantially fewer readout channels to realize such high resolution.

Carrier transport and collection in fully depleted semiconductors by a combined action of the space charge field and the field due to electrode voltages

DOEpatents

Rehak, P.; Gatti, E.

1987-08-18

A semiconductor charge transport device and method for making same are disclosed, characterized by providing a thin semiconductor wafer having rectifying junctions on its opposing major surfaces and including a small capacitance ohmic contact, in combination with bias voltage means and associated circuit means for applying a predetermined voltage to effectively deplete the wafer in regions thereof between the rectifying junctions and the ohmic contact. A charge transport device of the invention is usable as a drift chamber, a low capacitance detector, or a charge coupled device each constructed according to the methods of the invention for making such devices. Detectors constructed according to the principles of the invention are characterized by having significantly higher particle position indicating resolution than is attainable with prior art detectors, while at the same time requiring substantially fewer readout channels to realize such high resolution. 16 figs.

Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

2009-01-01

The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

Development of SiC Large Tapered Crystal Growth

NASA Technical Reports Server (NTRS)

Neudeck, Phil

2010-01-01

Majority of very large potential benefits of wide band gap semiconductor power electronics have NOT been realized due in large part to high cost and high defect density of commercial wafers. Despite 20 years of development, present SiC wafer growth approach is yet to deliver majority of SiC's inherent performance and cost benefits to power systems. Commercial SiC power devices are significantly de-rated in order to function reliably due to the adverse effects of SiC crystal dislocation defects (thousands per sq cm) in the SiC wafer.

Controlling Wafer Contamination Using Automated On-Line Metrology during Wet Chemical Cleaning

NASA Astrophysics Data System (ADS)

Wang, Jason; Kingston, Skip; Han, Ye; Saini, Harmesh; McDonald, Robert; Mui, Rudy

2003-09-01

The capabilities of a trace contamination analyzer are discussed and demonstrated. This analytical tool utilizes an electrospray, time-of-flight mass spectrometer (ES-TOF-MS) for fully automated on-line monitoring of wafer cleaning solutions. The analyzer provides rich information on metallic, anionic, cationic, elemental, and organic species through its ability to provide harsh (elemental) and soft (molecular) ionization under both positive and negative modes. It is designed to meet semiconductor process control and yield management needs for the ever increasing complex new chemistries present in wafer fabrication.

Simultaneous dual-functioning InGaN/GaN multiple-quantum-well diode for transferrable optoelectronics

NASA Astrophysics Data System (ADS)

Shi, Zheng; Yuan, Jialei; Zhang, Shuai; Liu, Yuhuai; Wang, Yongjin

2017-10-01

We propose a wafer-level procedure for the fabrication of 1.5-mm-diameter dual functioning InGaN/GaN multiple-quantum-well (MQW) diodes on a GaN-on-silicon platform for transferrable optoelectronics. Nitride semiconductor materials are grown on (111) silicon substrates with intermediate Al-composition step-graded buffer layers, and membrane-type MQW-diode architectures are obtained by a combination of silicon removal and III-nitride film backside thinning. Suspended MQW-diodes are directly transferred from silicon to foreign substrates such as metal, glass and polyethylene terephthalate by mechanically breaking the support beams. The transferred MQW-diodes display strong electroluminescence under current injection and photodetection under light irradiation. Interestingly, they demonstrate a simultaneous light-emitting light-detecting function, endowing the 1.5-mm-diameter MQW-diode with the capability of producing transferrable optoelectronics for adjustable displays, wearable optical sensors, multifunctional energy harvesting, flexible light communication and monolithic photonic circuit.

Thermally grown oxide and diffusions for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1979-01-01

A totally automated facility for semiconductor oxidation and diffusion was developed using a state-of-the-art diffusion furnace and high temperature grown oxides. Major innovations include: (1) a process controller specifically for semiconductor processing; (2) an automatic loading system to accept wafers from an air track, insert them into a quartz carrier and then place the carrier on a paddle for insertion into the furnace; (3) automatic unloading of the wafers back onto the air track, and (4) boron diffusion using diborane with plus or minus 5 percent uniformity. Processes demonstrated include Wet and dry oxidation for general use and for gate oxide, boron diffusion, phosphorous diffusion, and sintering.

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

X-Ray Performance of Multilayer Diffraction Diagnostics

DTIC Science & Technology

1989-11-13

wafers to fused quartz and superpolished Zerodur were used. Multilayers were deposited onto Si wafer substrates nd cleaved to rectangular sections 3.2...except it was noted that for depositions made on the supersmooth quartz and Zerodur substrates that the multilayer surfaces were slightly smoother than...values from the multilavers deposited on supersmooth quartz and Zerodur substrates were noticeabLe Lower than the U/Si multilav;ers on silicon

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Ultrathin body GaSb-on-insulator p-channel metal-oxide-semiconductor field-effect transistors on Si fabricated by direct wafer bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yokoyama, Masafumi, E-mail: yokoyama@mosfet.t.u-tokyo.ac.jp; Takenaka, Mitsuru; Takagi, Shinichi

2015-02-16

We have realized ultrathin body GaSb-on-insulator (GaSb-OI) on Si wafers by direct wafer bonding technology using atomic-layer deposition (ALD) Al{sub 2}O{sub 3} and have demonstrated GaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si. A 23-nm-thick GaSb-OI p-MOSFET exhibits the peak effective mobility of ∼76 cm{sup 2}/V s. We have found that the effective hole mobility of the thin-body GaSb-OI p-MOSFETs decreases with a decrease in the GaSb-OI thickness or with an increase in Al{sub 2}O{sub 3} ALD temperature. The InAs passivation of GaSb-OI MOS interfaces can enhance the peak effective mobility up to 159 cm{sup 2}/V s for GaSb-OI p-MOSFETs with themore » 20-nm-thick GaSb layer.« less

Microeconomics of process control in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Monahan, Kevin M.

2003-06-01

Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.

Nanoparticle Solutions for Printed Electronics

DTIC Science & Technology

2013-09-19

the printed semiconductor materials and their nanoparticle and colloidal precursors. Without this basic knowledge, further development and the...titania, silica ) were investigated in the production of complementary inks for complex devices. These were either obtained commercially in...layers were also deposited on borosilicate glass and silicon wafers. In the photovoltaic program, hybrid inorganic-organic semiconductor combinations

Photovoltaic cell with nano-patterned substrate

DOEpatents

Cruz-Campa, Jose Luis; Zhou, Xiaowang; Zubia, David

2016-10-18

A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.

Development of graphene process control by industrial optical spectroscopy setup

NASA Astrophysics Data System (ADS)

Fursenko, O.; Lukosius, M.; Lupina, G.; Bauer, J.; Villringer, C.; Mai, A.

2017-06-01

The successful integration of graphene into microelectronic devices depends strongly on the availability of fast and nondestructive characterization methods of graphene grown by CVD on large diameter production wafers [1-3] which are in the interest of the semiconductor industry. Here, a high-throughput optical metrology method for measuring the thickness and uniformity of large-area graphene sheets is demonstrated. The method is based on the combination of spectroscopic ellipsometry and normal incidence reflectometry in UV-Vis wavelength range (200-800 nm) with small light spots ( 30 μm2) realized in wafer optical metrology tool. In the first step graphene layers were transferred on a SiO2/Si substrate in order to determine the optical constants of graphene by the combination of multi-angle ellipsometry and reflectometry. Then these data were used for the development of a process control recipe of CVD graphene on 200 mm Ge(100)/Si(100) wafers. The graphene layer quality was additionally monitored by Raman spectroscopy. Atomic force microscopy measurements were performed for micro topography evaluation. In consequence, a robust recipe for unambiguous thickness monitoring of all components of a multilayer film stack, including graphene, surface residuals or interface layer underneath graphene and surface roughness is developed. Optical monitoring of graphene thickness uniformity over a wafer has shown an excellent long term stability (s=0.004 nm) regardless of the growth of interfacial GeO2 and surface roughness. The sensitivity of the optical identification of graphene during microelectronic processing was evaluated. This optical metrology technique with combined data collection exhibit a fast and highly precise method allowing one an unambiguous detection of graphene after transferring as well as after the CVD deposition process on a Ge(100)/Si(100) wafer. This approach is well suited for industrial applications due to its repeatability and flexibility.

Variable temperature semiconductor film deposition

DOEpatents

Li, X.; Sheldon, P.

1998-01-27

A method of depositing a semiconductor material on a substrate is disclosed. The method sequentially comprises (a) providing the semiconductor material in a depositable state such as a vapor for deposition on the substrate; (b) depositing the semiconductor material on the substrate while heating the substrate to a first temperature sufficient to cause the semiconductor material to form a first film layer having a first grain size; (c) continually depositing the semiconductor material on the substrate while cooling the substrate to a second temperature sufficient to cause the semiconductor material to form a second film layer deposited on the first film layer and having a second grain size smaller than the first grain size; and (d) raising the substrate temperature, while either continuing or not continuing to deposit semiconductor material to form a third film layer, to thereby anneal the film layers into a single layer having favorable efficiency characteristics in photovoltaic applications. A preferred semiconductor material is cadmium telluride deposited on a glass/tin oxide substrate already having thereon a film layer of cadmium sulfide.

Variable temperature semiconductor film deposition

DOEpatents

Li, Xiaonan; Sheldon, Peter

1998-01-01

A method of depositing a semiconductor material on a substrate. The method sequentially comprises (a) providing the semiconductor material in a depositable state such as a vapor for deposition on the substrate; (b) depositing the semiconductor material on the substrate while heating the substrate to a first temperature sufficient to cause the semiconductor material to form a first film layer having a first grain size; (c) continually depositing the semiconductor material on the substrate while cooling the substrate to a second temperature sufficient to cause the semiconductor material to form a second film layer deposited on the first film layer and having a second grain size smaller than the first grain size; and (d) raising the substrate temperature, while either continuing or not continuing to deposit semiconductor material to form a third film layer, to thereby anneal the film layers into a single layer having favorable efficiency characteristics in photovoltaic applications. A preferred semiconductor material is cadmium telluride deposited on a glass/tin oxide substrate already having thereon a film layer of cadmium sulfide.

Mechanism of amino acid interaction with silicon nitride surface during chemical mechanical planarization

NASA Astrophysics Data System (ADS)

America, William George

Chemical-Mechanical Planarization (CMP) has become an essential technology for making modern semiconductor devices. This technique was originally applied to overcome the depth of focus limitations of lithography tools during pattern development of metal and dielectric films. As features of the semiconductor device became smaller the lithographic process shifted to shorter exposure wavelengths and the useable depth of focus became smaller. The topography differences on the wafer's surface from all of the previous processing steps became greater than the exposure tools could properly project. CMP helped solve this problem by bringing the features of the wafer surface to the same plane. As semiconductor fabrication technology progressed further, CMP was applied to other areas of the process, including shallow trench isolation and metal line Damascene processing. In its simplest application, CMP polishes on features projecting upward and higher than the average surface. These projections experience more work and are polished faster. Given sufficient time the surface becomes essentially flat, on a micro-scale, and the lithographic projection tools has the same plane onto which to focus. Thus, the pattern is properly and uniformly exposed and subsequent reactive ion etching (RIE) steps are executed. This technique was initially applied to later steps in the wafer processing scheme to render a new flat surface at each metal layer. Building on this success, CMP has been applied to a broad range of steps in the wafer processing particularly where surface topography warrants and when RIE of dielectric or metallic films is not practical. CMP has seen its greatest application in semiconductor logic and memory devices and most recently, a Damascene processing for copper lines and shallow trench isolation. This pattern dependent CMP issue is explored in this thesis as it pertains primarily to shallow trench isolation CMP coupled with a highly selective slurry chemistry.

Si Wire-Array Solar Cells

NASA Astrophysics Data System (ADS)

Boettcher, Shannon

2010-03-01

Micron-scale Si wire arrays are three-dimensional photovoltaic absorbers that enable orthogonalization of light absorption and carrier collection and hence allow for the utilization of relatively impure Si in efficient solar cell designs. The wire arrays are grown by a vapor-liquid-solid-catalyzed process on a crystalline (111) Si wafer lithographically patterned with an array of metal catalyst particles. Following growth, such arrays can be embedded in polymethyldisiloxane (PDMS) and then peeled from the template growth substrate. The result is an unusual photovoltaic material: a flexible, bendable, wafer-thickness crystalline Si absorber. In this paper I will describe: 1. the growth of high-quality Si wires with controllable doping and the evaluation of their photovoltaic energy-conversion performance using a test electrolyte that forms a rectifying conformal semiconductor-liquid contact 2. the observation of enhanced absorption in wire arrays exceeding the conventional light trapping limits for planar Si cells of equivalent material thickness and 3. single-wire and large-area solid-state Si wire-array solar cell results obtained to date with directions for future cell designs based on optical and device physics. In collaboration with Michael Kelzenberg, Morgan Putnam, Joshua Spurgeon, Daniel Turner-Evans, Emily Warren, Nathan Lewis, and Harry Atwater, California Institute of Technology.

Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

NASA Astrophysics Data System (ADS)

Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

2016-04-01

A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

Temperature measuring device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lauf, R.J.; Bible, D.W.; Sohns, C.W.

1999-10-19

Systems and methods are described for a wireless instrumented silicon wafer that can measure temperatures at various points and transmit those temperature readings to an external receiver. The device has particular utility in the processing of semiconductor wafers, where it can be used to map thermal uniformity on hot plates, cold plates, spin bowl chucks, etc. without the inconvenience of wires or the inevitable thermal perturbations attendant with them.

Temperature measuring device

DOEpatents

Lauf, Robert J.; Bible, Don W.; Sohns, Carl W.

1999-01-01

Systems and methods are described for a wireless instrumented silicon wafer that can measure temperatures at various points and transmit those temperature readings to an external receiver. The device has particular utility in the processing of semiconductor wafers, where it can be used to map thermal uniformity on hot plates, cold plates, spin bowl chucks, etc. without the inconvenience of wires or the inevitable thermal perturbations attendant with them.

Method of transferring a thin crystalline semiconductor layer

DOEpatents

Nastasi, Michael A [Sante Fe, NM; Shao, Lin [Los Alamos, NM; Theodore, N David [Mesa, AZ

2006-12-26

A method for transferring a thin semiconductor layer from one substrate to another substrate involves depositing a thin epitaxial monocrystalline semiconductor layer on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the thin semiconductor layer is bonded to a second substrate and the thin layer is separated away at the interface, which results in transferring the thin epitaxial semiconductor layer from one substrate to the other substrate.

Semiconductor films on flexible iridium substrates

DOEpatents

Goyal, Amit

2005-03-29

A laminate semiconductor article includes a flexible substrate, an optional biaxially textured oxide buffer system on the flexible substrate, a biaxially textured Ir-based buffer layer on the substrate or the buffer system, and an epitaxial layer of a semiconductor. Ir can serve as a substrate with an epitaxial layer of a semiconductor thereon.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

NASA Astrophysics Data System (ADS)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Method of making photovoltaic cell

DOEpatents

Cruz-Campa, Jose Luis; Zhou, Xiaowang; Zubia, David

2017-06-20

A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

Wet-chemical systems and methods for producing black silicon substrates

DOEpatents

Yost, Vernon; Yuan, Hao-Chih; Page, Matthew

2015-05-19

A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Strain Engineering of Epitaxially Transferred, Ultrathin Layers of III-V Semiconductor on Insulator

DTIC Science & Technology

2011-01-01

The structure of the source wafer is shown schematically in Fig. 2a, with both InAs and AlGaSb layers coherently strained to the GaSb 001...is due to the surface plasmon-LO phonon FIG. 2. Color online a The structure of GaSb /AlGaSb/InAs source wafer with an assumed strain state for...insulator layers obtained from an epitaxial transfer process is studied. The as-grown InAs epilayer 10–20 nm thick on the GaSb /AlGaSb source wafer has the

WAMA: a method of optimizing reticle/die placement to increase litho cell productivity

NASA Astrophysics Data System (ADS)

Dor, Amos; Schwarz, Yoram

2005-05-01

This paper focuses on reticle/field placement methodology issues, the disadvantages of typical methods used in the industry, and the innovative way that the WAMA software solution achieves optimized placement. Typical wafer placement methodologies used in the semiconductor industry considers a very limited number of parameters, like placing the maximum amount of die on the wafer circle and manually modifying die placement to minimize edge yield degradation. This paper describes how WAMA software takes into account process characteristics, manufacturing constraints and business objectives to optimize placement for maximum stepper productivity and maximum good die (yield) on the wafer.

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Oxygen precipitation and bulk microdefects induced by the pre- and postepitaxial annealing in N/N + (100) silicon wafers

NASA Astrophysics Data System (ADS)

Wijaranakula, W.; Matlock, J. H.; Mollenkopf, H.

1987-12-01

Substrate wafers used for fabrication of epitaxial silicon wafers heavily doped with antimony at the concentration of 1020 atoms/cm3 were preannealed at a temperature between 500 and 900 °C prior to epitaxial deposition. Device fabrication thermal simulation was performed by heat treating the preannealed epitaxial wafers at 1050 °C in dry oxygen ambient for 16 h. Postepitaxial nucleation heat treatment at 750 °C for 4 h prior to the 1050 °C heat treament cycle was also applied on some epitaxial wafers for the purpose of enhancing the oxygen precipitation in silicon. It was observed that morphology and density of the bulk defects induced by the thermal treatment are affected by the preannealing temperature. The results also indicate that nucleation and growth kinetics of oxygen precipitates in preannealed n+ degenerate silicon substrate is strongly governed by oxygen and point defect diffusion.

Emission factors of air toxics from semiconductor manufacturing in Korea.

PubMed

Eom, Yun-Sung; Hong, Ji-Hyung; Lee, Suk-Jo; Lee, Eun-Jung; Cha, Jun-Seok; Lee, Dae-Gyun; Bang, Sun-Ae

2006-11-01

The development of local, accurate emission factors is very important for the estimation of reliable national emissions and air quality management. For that, this study is performed for pollutants released to the atmosphere with source-specific emission tests from the semiconductor manufacturing industry. The semiconductor manufacturing industry is one of the major sources of air toxics or hazardous air pollutants (HAPs); thus, understanding the emission characteristics of the emission source is a very important factor in the development of a control strategy. However, in Korea, there is a general lack of information available on air emissions from the semiconductor industry. The major emission sources of air toxics examined from the semiconductor manufacturing industry were wet chemical stations, coating applications, gaseous operations, photolithography, and miscellaneous devices in the wafer fabrication and semiconductor packaging processes. In this study, analyses of emission characteristics, and the estimations of emission data and factors for air toxics, such as acids, bases, heavy metals, and volatile organic compounds from the semiconductor manufacturing process have been performed. The concentration of hydrogen chloride from the packaging process was the highest among all of the processes. In addition, the emission factor of total volatile organic compounds (TVOCs) for the packaging process was higher than that of the wafer fabrication process. Emission factors estimated in this study were compared with those of Taiwan for evaluation, and they were found to be of similar level in the case of TVOCs and fluorine compounds.

Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2006-03-01

Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

Characterization of reclaimed GaAs substrates and investigation of reuse for thin film InGaAlP LED epitaxial growth

DOE Office of Scientific and Technical Information (OSTI.GOV)

Englhard, M.; Klemp, C.; Behringer, M.

This study reports a method to reuse GaAs substrates with a batch process for thin film light emitting diode (TF-LED) production. The method is based on an epitaxial lift-off technique. With the developed reclaim process, it is possible to get an epi-ready GaAs surface without additional time-consuming and expensive grinding/polishing processes. The reclaim and regrowth process was investigated with a one layer epitaxial test structure. The GaAs surface was characterized by an atomic force microscope directly after the reclaim process. The crystal structure of the regrown In{sub 0.5}(Ga{sub 0.45}Al{sub 0.55}){sub 0.5}P (Q{sub 55}) layer was investigated by high resolution x-raymore » diffraction and scanning transmission electron microscopy. In addition, a complete TF-LED grown on reclaimed GaAs substrates was electro-optically characterized on wafer level. The crystal structure of the epitaxial layers and the performance of the TF-LED grown on reclaimed substrates are not influenced by the developed reclaim process. This process would result in reducing costs for LEDs and reducing much arsenic waste for the benefit of a green semiconductor production.« less

GaAs Solar Cells Grown on Unpolished, Spalled Ge Substrates: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cavalli, Alessandro; Johnston, Steven; Sulas, Dana

Decreasing the cost of single-crystal substrates by wafer reuse techniques has long been sought for III-V solar cells. Controlled spalling of III-V devices is a possible pathway for epitaxial liftoff, which would help reduce costs, but chemo- mechanical polishing after liftoff tends to limit the potential cost savings. Growth on an unpolished spalled surface would be an additional step toward lower costs, but it is crucial to show high efficiency solar cell devices on these unprocessed substrates. In this study, we spalled 2-inch Ge wafers using a Ni stressor layer, and then grew GaAs solar cells by HVPE on themore » spalled Ge surface without any other surface treatment. We show a 12.8% efficient single-junction device, without anti-reflection coating, with quantum efficiency very close to identical devices grown by HVPE on non-spalled GaAs substrates. Demonstrating a high carrier collection on unpolished spalled wafers is a step toward reducing substrate-related liftoff and reuse costs.« less

Surface preparation of substances for continuous convective assembly of fine particles

DOEpatents

Rossi, Robert

2003-01-01

A method for producing periodic nanometer-scale arrays of metal or semiconductor junctions on a clean semiconductor substrate surface is provided comprising the steps of: etching the substrate surface to make it hydrophilic, forming, under an inert atmosphere, a crystalline colloid layer on the substrate surface, depositing a metal or semiconductor material through the colloid layer onto the surface of the substrate, and removing the colloid from the substrate surface. The colloid layer is grown on the clean semiconductor surface by withdrawing the semiconductor substrate from a sol of colloid particles.

A Summary of Lightpipe Radiation Thermometry Research at NIST

PubMed Central

Tsai, Benjamin K.

2006-01-01

During the last 10 years, research in light-pipe radiation thermometry has significantly reduced the uncertainties for temperature measurements in semiconductor processing. The National Institute of Standards and Technology (NIST) has improved the calibration of lightpipe radiation thermometers (LPRTs), the characterization procedures for LPRTs, the in situ calibration of LPRTs using thin-film thermocouple (TFTC) test wafers, and the application of model-based corrections to improve LPRT spectral radiance temperatures. Collaboration with industry on implementing techniques and ideas established at NIST has led to improvements in temperature measurements in semiconductor processing. LPRTs have been successfully calibrated at NIST for rapid thermal processing (RTP) applications using a sodium heat-pipe blackbody between 700 °C and 900 °C with an uncertainty of about 0.3 °C (k = 1) traceable to the International Temperature Scale of 1990. Employing appropriate effective emissivity models, LPRTs have been used to determine the wafer temperature in the NIST RTP Test Bed with an uncertainty of 3.5 °C. Using a TFTC wafer for calibration, the LPRT can measure the wafer temperature in the NIST RTP Test Bed with an uncertainty of 2.3 °C. Collaborations with industry in characterizing and calibrating LPRTs will be summarized, and future directions for LPRT research will be discussed. PMID:27274914

A Summary of Lightpipe Radiation Thermometry Research at NIST.

PubMed

Tsai, Benjamin K

2006-01-01

During the last 10 years, research in light-pipe radiation thermometry has significantly reduced the uncertainties for temperature measurements in semiconductor processing. The National Institute of Standards and Technology (NIST) has improved the calibration of lightpipe radiation thermometers (LPRTs), the characterization procedures for LPRTs, the in situ calibration of LPRTs using thin-film thermocouple (TFTC) test wafers, and the application of model-based corrections to improve LPRT spectral radiance temperatures. Collaboration with industry on implementing techniques and ideas established at NIST has led to improvements in temperature measurements in semiconductor processing. LPRTs have been successfully calibrated at NIST for rapid thermal processing (RTP) applications using a sodium heat-pipe blackbody between 700 °C and 900 °C with an uncertainty of about 0.3 °C (k = 1) traceable to the International Temperature Scale of 1990. Employing appropriate effective emissivity models, LPRTs have been used to determine the wafer temperature in the NIST RTP Test Bed with an uncertainty of 3.5 °C. Using a TFTC wafer for calibration, the LPRT can measure the wafer temperature in the NIST RTP Test Bed with an uncertainty of 2.3 °C. Collaborations with industry in characterizing and calibrating LPRTs will be summarized, and future directions for LPRT research will be discussed.

Methods of producing free-standing semiconductors using sacrificial buffer layers and recyclable substrates

DOEpatents

Ptak, Aaron Joseph; Lin, Yong; Norman, Andrew; Alberi, Kirstin

2015-05-26

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices. The low-defect density semiconductor materials produced using this method result in the enhanced performance of the semiconductor devices that incorporate the semiconductor materials.

Ultra-high aggregate bandwidth two-dimensional multiple-wavelength diode laser arrays

NASA Astrophysics Data System (ADS)

Chang-Hasnain, Connie

1993-12-01

Two-dimensional (2D) multi-wavelength vertical cavity surface emitting laser (VCSEL) arrays is promising for ultrahigh aggregate capacity optical networks. A 2D VCSEL array emitting 140 distinct wavelengths was reported by implementing a spatially graded layer in the VCSEL structure, which in turn creates a wavelength spread. Concentrtion was on epitaxial growth techniques to make reproducible and repeatable multi-wavelength VCSEL arrays. Our approach to fabricate the spatially graded layer involves creating a nonuniform substrate surface temperature across the wafer during the growth of the cavity spacer region using the fact that the molecular beam epitaxy growth of GaAs is highly sensitive to the substrate temperature. Growth is investigated with the use of a patterned spacer (either a Ga or Si substrate) placed in-between the substrate and its heater. The temperature distribution on such wafers is used to guide our experiments. A reflectivity measurement apparatus that is capable of mapping a 2 in. wafer with a 100 microns diameter resolution was built for diagnosing our wafers. In this first six-month report, our calculations, the various experimental results, and a discussion on future directions are presented.

Back-side readout semiconductor photomultiplier

DOEpatents

Choong, Woon-Seng; Holland, Stephen E

2014-05-20

This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region.

Optically switched graphene/4H-SiC junction bipolar transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chandrashekhar, MVS; Sudarshan, Tangali S.; Omar, Sabih U.

A bi-polar device is provided, along with methods of making the same. The bi-polar device can include a semiconductor substrate doped with a first dopant, a semiconductor layer on the first surface of the semiconductor substrate, and a Schottky barrier layer on the semiconductor layer. The method of forming a bi-polar device can include: forming a semiconductor layer on a first surface of a semiconductor substrate, where the semiconductor substrate comprises a first dopant and where the semiconductor layer comprises a second dopant that has an opposite polarity than the first dopant; and forming a Schottky barrier layer on amore » first portion of the semiconductor layer while leaving a second portion of the semiconductor layer exposed.« less

Using an extractive Fourier transform infrared spectrometer for improving cleanroom air quality in a semiconductor manufacturing plant.

PubMed

Li, Shou-Nan; Chang, Chin-Ta; Shih, Hui-Ya; Tang, Andy; Li, Alen; Chen, Yin-Yung

2003-01-01

A mobile extractive Fourier transform infrared (FTIR) spectrometer was successfully used to locate, identify, and quantify the "odor" sources inside the cleanroom of a semiconductor manufacturing plant. It was found that ozone (O(3)) gas with a peak concentration of 120 ppm was unexpectedly releasing from a headspace of a drain for transporting used ozonized water and that silicon tetrafluoride (SiF(4)) with a peak concentration of 3 ppm was off-gassed from silicon wafers after dry-etching processing. When the sources of the odors was pinpointed by the FTIR, engineering control measures were applied. For O(3) control, a water-sealed pipeline was added to prevent the O(3) gas (emitting from the ozonized water) from entering the mixing unit. A ventilation system also was applied to the mixing unit in case of O(3) release. For SiF(4) mitigation, before the wafer-out chamber was opened, N(2) gas with a flow rate of 150 L/min was used for 100 sec to purge the wafer-out chamber, and a vacuum system was simultaneously activated to pump away the purging N(2). The effectiveness of the control measures was assured by using the FTIR. In addition, the FTIR was used to monitor the potential hazardous gas emissions during preventative maintenance of the semiconductor manufacturing equipment.

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

NASA Technical Reports Server (NTRS)

Speer, Kevin M.

2004-01-01

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate

NASA Astrophysics Data System (ADS)

Ren, Kun; Zheng, Jiachen; Lu, Haiyan; Liu, Jun; Wu, Lishu; Zhou, Wenyong; Cheng, Wei

2018-05-01

This paper investigated the DC and RF performance of the InP double heterojunction bipolar transistors (DHBTs) transferred to RF CMOS wafer substrate. The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger, of 0.8 μm in width and 5 μm in length, are changed unobviously, while the cut-off frequency and the maximum oscillation frequency are decreased from 220 to 171 GHz and from 204 to 154 GHz, respectively. In order to have a detailed insight on the degradation of the RF performance, small-signal models for the InP DHBT before and after substrate transferred are presented and comparably extracted. The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself. Project supported by the National Natural Science Foundation of China (No. 61331006) and the Natural Science Foundation of Zhejiang Province (No. Y14F010017).

Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

NASA Astrophysics Data System (ADS)

Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

2018-05-01

Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

Two-Axis Direct Fluid Shear Stress Sensor for Aerodynamic Applications

NASA Technical Reports Server (NTRS)

Bajikar, Sateesh S.; Scott, Michael A.; Adcock, Edward E.

2011-01-01

This miniature or micro-sized semiconductor sensor design provides direct, nonintrusive measurement of skin friction or wall shear stress in fluid flow situations in a two-axis configuration. The sensor is fabricated by microelectromechanical system (MEMS) technology, enabling small size and multiple, low-cost reproductions. The sensors may be fabricated by bonding a sensing element wafer to a fluid-coupling element wafer. Using this layered machine structure provides a truly three-dimensional device.

Predicted lattice-misfit stresses in a gallium-nitride (GaN) film

NASA Astrophysics Data System (ADS)

Suhir, E.; Yi, S.

2017-02-01

Effective, easy-to-use and physically meaningful analytical predictive models are developed for the evaluation the lattice-misfit stresses (LMS) in a semiconductor film grown on a circular substrate (wafer). The two-dimensional (plane-stress) theory-of-elasticity approximation (TEA) is employed. First of all, the interfacial shearing stresses are evaluated. These stresses might lead to the occurrence and growth of dislocations, as well as to possible delaminations (adhesive strength of the assembly) and the elevated stress and strain in the buffering material, if any (cohesive strength of the assembly). Second of all, the normal radial and circumferential (tangential) stresses acting in the film cross-sections are determined. These stresses determine the short- and long-term strength (fracture toughness) of the film material. It is shown that while the normal stresses in the semiconductor film are independent of its thickness, the interfacial shearing stresses increase with an increase in the induced force (not stress!) acting in the film cross-sections, and that this force increases with an increase in the film thickness. This leads, for a thick enough film, to the occurrence, growth and propagation of dislocations. These start at the assembly ends and propagate, when the film thickness increases, inwards the structure. The TEA data are compared with the results obtained using a simplified strength-of-materials approach (SMA). This approach considers, instead of an actual circular assembly, an elongated bi-material rectangular strip of unit width and of finite length equal to the wafer diameter. The analysis, although applicable to any semiconductor crystal growth (SCG) technology is geared in this analysis to the Gallium-Nitride (GaN) technology. The numerical example is carried out for a GaN film grown on a Silicon Carbide (SiC) substrate. It is concluded that the SMA model is acceptable for understanding the physics of the state of stress and for the prediction of the normal stresses acting in the major mid-portion of the assembly. The SMA model underestimates, however, the maximum interfacial shearing stress at the assembly periphery, and, because of the very nature of the SMA, is unable to address the circumferential stress. This stress can be quite high at the circular boundary of the assembly. At the assembly edge the circumferential stress is as high as σθ = (2-ν1)σ1, i.e., by the factor of 2-ν1 higher than the normal stress, σ1, in the mid-portion of the film. In this formula, ν1 is Poisson's ratio of the film material.

150-nm generation lithography equipment

NASA Astrophysics Data System (ADS)

Deguchi, Nobuyoshi; Uzawa, Shigeyuki

1999-07-01

Lithography by step-and-scan exposure is expected to be the mainstream for semiconductor manufacturing below 180 nm resolution patterns. We have developed a scanner for 150 nm features on either 200 mm or 300 mm wafers. For this system, the synchronous stage system has been redesigned which makes it possible to improve imaging performance and overlay accuracy. A new 300 mm wafer stage enhances productivity while weighting almost the same as the stage for 200 mm wafers. The mainbody mechanical frame incorporates reactive force receiver system to counter the inertial energy and vibrational issues associated with high speed wafer and reticle stage scanning. This report outlines the total system design, new technologies and performance data of the Cannon FPA-5000ES2 step-and-scan exposure tool developed for the 150 nm generation lithography.

Presidential Green Chemistry Challenge: 2002 Small Business Award

EPA Pesticide Factsheets

Presidential Green Chemistry Challenge 2002 award winner, SC Fluids, with Los Alamos National Laboratory, developed supercritical CO2 resist remover technology to clean residues from semiconductor wafers during manufacture.

Porous silicon carbide (SIC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

NASA Astrophysics Data System (ADS)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

Advanced in-situ control for III-nitride RF power device epitaxy

NASA Astrophysics Data System (ADS)

Brunner, F.; Zettler, J.-T.; Weyers, M.

2018-04-01

In this contribution, the latest improvements regarding wafer temperature measurement on 4H-SiC substrates and, based on this, of film thickness and composition control of GaN and AlGaN layers in power electronic device structures are presented. Simultaneous pyrometry at different wavelengths (950 nm and 405 nm) reveal the advantages and limits of the different temperature measurement approaches. Near-UV pyrometry gives a very stable wafer temperature signal without oscillations during GaN growth since the semi-insulating 4H-SiC substrate material becomes opaque at temperatures above 550 °C at the wavelength of 405 nm. A flat wafer temperature profile across the 100 mm substrate diameter is demonstrated despite a convex wafer shape at AlGaN growth conditions. Based on the precise assignment of wafer temperature during MOVPE we were able to improve the accuracy of the high-temperature n-k database for the materials involved. Consequently, the measurement accuracy of all film thicknesses grown under fixed temperature conditions improved. Comparison of in situ and ex situ determined layer thicknessess indicate an unintended etching of the topmost layer during cool-down. The details and limitations of real-time composition analysis for lower Al-content AlGaN barrier layers during transistor device epitaxy are shown.

Metal-optic and Plasmonic Semiconductor-based Nanolasers

DTIC Science & Technology

2012-05-07

provides a means to integrate laser sources for silicon photonics technology. Using wafer bonding techniques, the metal- clad nanocavity can be integrated...SUPPLEMENTARY NOTES 14. ABSTRACT Over the past few decades, semiconductor lasers have relentlessly followed the path towards miniaturization...Smaller lasers are more energy e cient, are cheaper to make, and open up new applications in sensing and displays, among many other things. Yet, up until

Optical surface analysis: a new technique for the inspection and metrology of optoelectronic films and wafers

NASA Astrophysics Data System (ADS)

Bechtler, Laurie; Velidandla, Vamsi

2003-04-01

In response to demand for higher volumes and greater product capability, integrated optoelectronic device processing is rapidly increasing in complexity, benefiting from techniques developed for conventional silicon integrated circuit processing. The needs for high product yield and low manufacturing cost are also similar to the silicon wafer processing industry. This paper discusses the design and use of an automated inspection instrument called the Optical Surface Analyzer (OSA) to evaluate two critical production issues in optoelectronic device manufacturing: (1) film thickness uniformity, and (2) defectivity at various process steps. The OSA measurement instrument is better suited to photonics process development than most equipment developed for conventional silicon wafer processing in two important ways: it can handle both transparent and opaque substrates (unlike most inspection and metrology tools), and it is a full-wafer inspection method that captures defects and film variations over the entire substrate surface (unlike most film thickness measurement tools). Measurement examples will be provided in the paper for a variety of films and substrates used for optoelectronics manufacturing.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

NASA Astrophysics Data System (ADS)

Schatz, A.; Pantel, D.; Hanemann, T.

2017-09-01

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

Anomalous luminescence phenomena of indium-doped ZnO nanostructures grown on Si substrates by the hydrothermal method

PubMed Central

2012-01-01

In recent years, zinc oxide (ZnO) has become one of the most popular research materials due to its unique properties and various applications. ZnO is an intrinsic semiconductor, with a wide bandgap (3.37 eV) and large exciton binding energy (60 meV) making it suitable for many optical applications. In this experiment, the simple hydrothermal method is used to grow indium-doped ZnO nanostructures on a silicon wafer, which are then annealed at different temperatures (400°C to 1,000°C) in an abundant oxygen atmosphere. This study discusses the surface structure and optical characteristic of ZnO nanomaterials. The structure of the ZnO nanostructures is analyzed by X-ray diffraction, the superficial state by scanning electron microscopy, and the optical measurements which are carried out using the temperature-dependent photoluminescence (PL) spectra. In this study, we discuss the broad peak energy of the yellow-orange emission which shows tendency towards a blueshift with the temperature increase in the PL spectra. This differs from other common semiconductors which have an increase in their peak energy of deep-level emission along with measurement temperature. PMID:22647253

Worker exposure to methanol vapors during cleaning of semiconductor wafers in a manufacturing setting.

PubMed

Gaffney, Shannon; Moody, Emily; McKinley, Meg; Knutsen, Jeffrey; Madl, Amy; Paustenbach, Dennis

2008-05-01

An exposure simulation was conducted to characterize methanol exposure of workers who cleaned wafers in quality control departments within the semiconductor industry. Short-term (15 min) and long-term (2-4 hr) personal and area samples (at distances of 1 m and 3-6 m from the source) were collected during the 2-day simulation. On the first day, 45 mL of methanol were used per hour by a single worker washing wafers in a 102 m(3) room with a ventilation rate of about 10 air changes per hour (ACH). Virtually all methanol volatilized. To assess exposures under conditions associated with higher productivity, on the second day, two workers cleaned wafers simultaneously, together using methanol at over twice the rate of the first day (95 mL/hr). On this day, the ventilation rate was halved (5 ACH). Personal concentrations on the first day averaged 60 ppm (SD = 46 ppm) and ranged from 10-140 ppm. On the second day, personal concentrations for both workers averaged 118 ppm (SD = 50 ppm; range: 64-270 ppm). Area concentrations measured on the first day at 1 m from the source and throughout the balance of the room averaged 29 ppm (SD = 19 ppm; range: 4-83 ppm) and 18 ppm (SD = 12 ppm; range: 3-42 ppm), respectively. As expected, area concentrations measured on the second day were higher than the first and averaged 73 ppm (SD = 25 ppm; range: 27-140 ppm) at 1 meter and 48 ppm (SD = 13 ppm; range: 21-67 ppm) throughout the balance of the room. The results of this simulation suggest that the use of methanol to clean semiconductor wafers without the use of local exhaust ventilation and with relatively low room ventilation rates is unlikely to result in worker exposures exceeding the current ACGIH(R) threshold limit value of 200 ppm. This study also confirmed prior studies suggesting that when a relatively volatile chemical is located within arm's length (near field), breathing zone concentrations will be about two- to threefold greater than the room concentration when the air exchange rate is 5-10 ACH.

Precision depth measurement of through silicon vias (TSVs) on 3D semiconductor packaging process.

PubMed

Jin, Jonghan; Kim, Jae Wan; Kang, Chu-Shik; Kim, Jong-Ahn; Lee, Sunghun

2012-02-27

We have proposed and demonstrated a novel method to measure depths of through silicon vias (TSVs) at high speed. TSVs are fine and deep holes fabricated in silicon wafers for 3D semiconductors; they are used for electrical connections between vertically stacked wafers. Because the high-aspect ratio hole of the TSV makes it difficult for light to reach the bottom surface, conventional optical methods using visible lights cannot determine the depth value. By adopting an optical comb of a femtosecond pulse laser in the infra-red range as a light source, the depths of TSVs having aspect ratio of about 7 were measured. This measurement was done at high speed based on spectral resolved interferometry. The proposed method is expected to be an alternative method for depth inspection of TSVs.

Exposure assessment among US workers employed in semiconductor wafer fabrication.

PubMed

Marano, Donald E; Boice, John D; Munro, Heather M; Chadda, Bandana K; Williams, Michael E; McCarthy, Colleen M; Kivel, Peggy F; Blot, William J; McLaughlin, Joseph K

2010-11-01

To classify 100,081 semiconductor workers employed during 1983-2002, and some as early as 1968, regarding potential for chemical exposures in cleanrooms during silicon wafer fabrication. This study involved site visits to 10 cities with fabrication facilities, evaluation of 12,300 personal air samples for >60 chemicals, and examination of >37,000 departments and >8600 job codes to develop exposure groupings. Each worker was classified into one of five exposure groups on the basis of job-department combinations: 1) fabrication process equipment operators or process equipment service technicians working in cleanrooms (n = 28,583); 2) professionals such as supervisors working in fabrication areas (n = 8642); 3) professionals and office workers in nonfabrication areas (n = 53,512); 4) back-end workers (n = 5256); or 5) other nonfabrication workers (n = 4088). More than 98% of the personal air samples were below current occupational exposure limits. Although specific chemical exposures at the level of the individual could not be quantified, semiconductor workers were classified into broad exposure groups for assessment of cancer mortality in an epidemiologic study.

Maskless wafer-level microfabrication of optical penetrating neural arrays out of soda-lime glass: Utah Optrode Array.

PubMed

Boutte, Ronald W; Blair, Steve

2016-12-01

Borrowing from the wafer-level fabrication techniques of the Utah Electrode Array, an optical array capable of delivering light for neural optogenetic studies is presented in this paper: the Utah Optrode Array. Utah Optrode Arrays are micromachined out of sheet soda-lime-silica glass using standard backend processes of the semiconductor and microelectronics packaging industries such as precision diamond grinding and wet etching. 9 × 9 arrays with 1100μ m × 100μ m optrodes and a 500μ m back-plane are repeatably reproduced on 2i n wafers 169 arrays at a time. This paper describes the steps and some of the common errors of optrode fabrication.

Electrostatic bonding of thin (approximately 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (approximately 2 mil) silicon wafers and solar cells

NASA Technical Reports Server (NTRS)

Egelkrout, D. W.; Horne, W. E.

1980-01-01

Electrostatic bonding (ESB) of thin (3 mil) Corning 7070 cover glasses to Ta2O5 AR-coated thin (2 mil) silicon wafers and solar cells is investigated. An experimental program was conducted to establish the effects of variations in pressure, voltage, temperature, time, Ta2O5 thickness, and various prebond glass treatments. Flat wafers without contact grids were used to study the basic effects for bonding to semiconductor surfaces typical of solar cells. Solar cells with three different grid patterns were used to determine additional requirements caused by the raised metallic contacts.

Computational overlay metrology with adaptive data analytics

NASA Astrophysics Data System (ADS)

Schmitt-Weaver, Emil; Subramony, Venky; Ullah, Zakir; Matsunobu, Masazumi; Somasundaram, Ravin; Thomas, Joel; Zhang, Linmiao; Thul, Klaus; Bhattacharyya, Kaustuve; Goossens, Ronald; Lambregts, Cees; Tel, Wim; de Ruiter, Chris

2017-03-01

With photolithography as the fundamental patterning step in the modern nanofabrication process, every wafer within a semiconductor fab will pass through a lithographic apparatus multiple times. With more than 20,000 sensors producing more than 700GB of data per day across multiple subsystems, the combination of a light source and lithographic apparatus provide a massive amount of information for data analytics. This paper outlines how data analysis tools and techniques that extend insight into data that traditionally had been considered unmanageably large, known as adaptive analytics, can be used to show how data collected before the wafer is exposed can be used to detect small process dependent wafer-towafer changes in overlay.

SERS Engineering Collaboration

DTIC Science & Technology

2012-06-01

laser beam. In the second approach, a pulsed laser was used to texture a silicon wafer to form sharp features. Silver was evaporated onto the wafer...orders of magnitude larger than that measured on a gold nanoparticle array on a glass substrate. The largest SERS enhancement for a silver device was...surface plasmons," Yizhuo Chu and Kenneth B. Crozier, Optics Letters vol. 34, 244 (2009) K3. "Gold nanorings as substrates for surface-enhanced Raman

Wafer-Level Vacuum Packaging of Smart Sensors.

PubMed

Hilton, Allan; Temple, Dorota S

2016-10-31

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2002-01-01

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Wafer-Level Vacuum Packaging of Smart Sensors

PubMed Central

Hilton, Allan; Temple, Dorota S.

2016-01-01

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

Thin-film solar cell fabricated on a flexible metallic substrate

DOEpatents

Tuttle, John R.; Noufi, Rommel; Hasoon, Falah S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

Thin-Film Solar Cell Fabricated on a Flexible Metallic Substrate

DOEpatents

Tuttle, J. R.; Noufi, R.; Hasoon, F. S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

National Manufacturing Strategy: Is a National Manufacturing Strategy Essential to National Security?

DTIC Science & Technology

2011-05-01

cycle found nearly a quarter of all homeowners owning more than their home was worth. 11 Both Paul Volcker and Warren Buffet arrived at similar...November 15, 2010; Warren Buffet , Testimony, Financial Crisis Inquiry Commission, June 2, 2010; “Subprime Mortgage Crisis,” http://en.wikipedia.org...overseas manufacturing. Case Study: Semiconductor Wafer Industry. The history of the semiconductor industry is an instructive account . It begins with

Advanced Photonic Sensors Enabled by Semiconductor Bonding

DTIC Science & Technology

2010-05-31

a dry scroll backing pump to maintain the high differential pressure between the UV gun and the sample/analysis chamber. We also replaced the...semiconductor materials in an ultra-high vacuum (UHV) environment where the properties of the interface can be controlled with atomic-level precision. Such...year research program, we designed and constructed a unique system capable of fusion bonding two wafers in an ultra-high vacuum environment. This system

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

NASA Technical Reports Server (NTRS)

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

11.72 sq cm SiC Wafer-scale Interconnected 64 kA PiN Diode

DTIC Science & Technology

2012-01-30

drop of 10.3 V. The dissipated energy was 382 J and the calculated action exceeded 1.7 MA2 -s. Preliminary development of high voltage interconnection...scale diode action (surge current integral), a key reliability parameter, exceeded 1.7 MA2 -s. Figure 6: The wafer-scale interconnected diode...scale diode was 382 J and the calculated action exceeded 1.7 MA2 -sec. High voltage operation of PiN diodes, thyristors, and other semiconductor

Electrically pumped 1.3 microm room-temperature InAs/GaAs quantum dot lasers on Si substrates by metal-mediated wafer bonding and layer transfer.

PubMed

Tanabe, Katsuaki; Guimard, Denis; Bordel, Damien; Iwamoto, Satoshi; Arakawa, Yasuhiko

2010-05-10

An electrically pumped InAs/GaAs quantum dot laser on a Si substrate has been demonstrated. The double-hetero laser structure was grown on a GaAs substrate by metal-organic chemical vapor deposition and layer-transferred onto a Si substrate by GaAs/Si wafer bonding mediated by a 380-nm-thick Au-Ge-Ni alloy layer. This broad-area Fabry-Perot laser exhibits InAs quantum dot ground state lasing at 1.31 microm at room temperature with a threshold current density of 600 A/cm(2). (c) 2010 Optical Society of America.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Lattice matched semiconductor growth on crystalline metallic substrates

DOEpatents

Norman, Andrew G; Ptak, Aaron J; McMahon, William E

2013-11-05

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.

Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

PubMed Central

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed. PMID:24459433

Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

PubMed

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

Wafer scale BN on sapphire substrates for improved graphene transport.

PubMed

Vangala, Shivashankar; Siegel, Gene; Prusnick, Timothy; Snure, Michael

2018-06-11

Wafer scale (2") BN grown by metal organic chemical vapor deposition (MOCVD) on sapphire was examined as a weakly interacting dielectric substrate for graphene, demonstrating improved transport properties over conventional sapphire and SiO 2 /Si substrates. Chemical vapor deposition grown graphene was transferred to BN/sapphire substrates for evaluation of more than 30 samples using Raman and Hall effects measurements. A more than 2x increase in Hall mobility and 10x reduction in sheet carrier density was measured for graphene on BN/sapphire compared to sapphire substrates. Through control of the MOCVD process, BN films with roughness ranging from <0.1 nm to >1 nm were grown and used to study the effects of substrate roughness on graphene transport. Arrays of graphene field effect transistors were fabricated on 2" BN/sapphire substrates demonstrating scalability and device performance enhancement.

Mask-to-wafer alignment system

DOEpatents

Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

2003-11-04

A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

Quantitative Exposure Assessment of Various Chemical Substances in a Wafer Fabrication Industry Facility

PubMed Central

Jang, Jae-Kil; Shin, Jung-Ah

2011-01-01

Objectives This study was designed to evaluate exposure levels of various chemicals used in wafer fabrication product lines in the semiconductor industry where work-related leukemia has occurred. Methods The research focused on 9 representative wafer fabrication bays among a total of 25 bays in a semiconductor product line. We monitored the chemical substances categorized as human carcinogens with respect to leukemia as well as harmful chemicals used in the bays and substances with hematologic and reproductive toxicities to evaluate the overall health effect for semiconductor industry workers. With respect to monitoring, active and passive sampling techniques were introduced. Eight-hour long-term and 15-minute short-term sampling was conducted for the area as well as on personal samples. Results The results of the measurements for each substance showed that benzene, toluene, xylene, n-butyl acetate, 2-methoxyethanol, 2-heptanone, ethylene glycol, sulfuric acid, and phosphoric acid were non-detectable (ND) in all samples. Arsine was either "ND" or it existed only in trace form in the bay air. The maximum exposure concentration of fluorides was approximately 0.17% of the Korea occupational exposure limits, with hydrofluoric acid at about 0.2%, hydrochloric acid 0.06%, nitric acid 0.05%, isopropyl alcohol 0.4%, and phosphine at about 2%. The maximum exposure concentration of propylene glycol monomethyl ether acetate (PGMEA) was 0.0870 ppm, representing only 0.1% or less than the American Industrial Hygiene Association recommended standard (100 ppm). Conclusion Benzene, a known human carcinogen for leukemia, and arsine, a hematologic toxin, were not detected in wafer fabrication sites in this study. Among reproductive toxic substances, n-butyl acetate was not detected, but fluorides and PGMEA existed in small amounts in the air. This investigation was focused on the air-borne chemical concentrations only in regular working conditions. Unconditional exposures during spills and/or maintenance tasks and by-product chemicals were not included. Supplementary studies might be required. PMID:22953186

TH-CD-201-12: Preliminary Evaluation of Organic Field Effect Transistors as Radiation Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Syme, A; Lin, H; Rubio-Sanchez, J

Purpose: To fabricate organic field effect transistors (OFETs) and evaluate their performance before and after exposure to ionizing radiation. To determine if OFETs have potential to function as radiation dosimeters. Methods: OFETs were fabricated on both Si/SiO{sub 2} wafers and flexible polymer substrates using standard processing techniques. Pentacene was used as the organic semiconductor material and the devices were fabricated in a bottom gate configuration. Devices were irradiated using an orthovoltage treatment unit (120 kVp x-rays). Threshold voltage values were measured with the devices in saturation mode and quantified as a function of cumulative dose. Current-voltage characteristics of the devicesmore » were measured using a Keithley 2614 SourceMeter SMU Instrument. The devices were connected to the reader but unpowered during irradiations. Results: Devices fabricated on Si/SiO2 wafers demonstrated excellent linearity (R{sup 2} > 0.997) with threshold voltages that ranged between 15 and 36 V. Devices fabricated on a flexible polymer substrate had substantially smaller threshold voltages (∼ 4 – 8 V) and slightly worse linearity (R{sup 2} > 0.98). The devices demonstrated excellent stability in I–V characteristics over a large number (>2000) cycles. Conclusion: OFETs have demonstrated excellent potential in radiation dosimetry applications. A key advantage of these devices is their composition, which can be substantially more tissue-equivalent at low photon energies relative to many other types of radiation detector. In addition, fabrication of organic electronics can employ techniques that are faster, simpler and cheaper than conventional silicon-based devices. These results support further development of organic electronic devices for radiation detection purposes. Funding Support, Disclosures, and Conflict of Interest: This work was funded by the Natural Sciences and Engineering Research Council of Canada.« less

Four-mirror extreme ultraviolet (EUV) lithography projection system

DOEpatents

Cohen, Simon J; Jeong, Hwan J; Shafer, David R

2000-01-01

The invention is directed to a four-mirror catoptric projection system for extreme ultraviolet (EUV) lithography to transfer a pattern from a reflective reticle to a wafer substrate. In order along the light path followed by light from the reticle to the wafer substrate, the system includes a dominantly hyperbolic convex mirror, a dominantly elliptical concave mirror, spherical convex mirror, and spherical concave mirror. The reticle and wafer substrate are positioned along the system's optical axis on opposite sides of the mirrors. The hyperbolic and elliptical mirrors are positioned on the same side of the system's optical axis as the reticle, and are relatively large in diameter as they are positioned on the high magnification side of the system. The hyperbolic and elliptical mirrors are relatively far off the optical axis and hence they have significant aspherical components in their curvatures. The convex spherical mirror is positioned on the optical axis, and has a substantially or perfectly spherical shape. The spherical concave mirror is positioned substantially on the opposite side of the optical axis from the hyperbolic and elliptical mirrors. Because it is positioned off-axis to a degree, the spherical concave mirror has some asphericity to counter aberrations. The spherical concave mirror forms a relatively large, uniform field on the wafer substrate. The mirrors can be tilted or decentered slightly to achieve further increase in the field size.

Design and fabrication of high-performance diamond triple-gate field-effect transistors

PubMed Central

Liu, Jiangwei; Ohsato, Hirotaka; Wang, Xi; Liao, Meiyong; Koide, Yasuo

2016-01-01

The lack of large-area single-crystal diamond wafers has led us to downscale diamond electronic devices. Here, we design and fabricate a hydrogenated diamond (H-diamond) triple-gate metal-oxide-semiconductor field-effect transistor (MOSFET) to extend device downscaling and increase device output current. The device’s electrical properties are compared with those of planar-type MOSFETs, which are fabricated simultaneously on the same substrate. The triple-gate MOSFET’s output current (174.2 mA mm−1) is much higher than that of the planar-type device (45.2 mA mm−1), and the on/off ratio and subthreshold swing are more than 108 and as low as 110 mV dec−1, respectively. The fabrication of these H-diamond triple-gate MOSFETs will drive diamond electronic device development forward towards practical applications. PMID:27708372

Increased fracture depth range in controlled spalling of (100)-oriented germanium via electroplating

DOE PAGES

Crouse, Dustin; Simon, John; Schulte, Kevin L.; ...

2018-01-31

Controlled spalling in (100)-oriented germanium using a nickel stressor layer shows promise for semiconductor device exfoliation and kerfless wafering. Demonstrated spall depths of 7-60 um using DC sputtering to deposit the stressor layer are appropriate for the latter application but spall depths < 5 um may be required to minimize waste for device applications. This work investigates the effect of tuning both electroplating current density and electrolyte chemistry on the residual stress in the nickel and on the achievable spall depth range for the Ni/Ge system as a lower-cost, higher-throughput alternative to sputtering. By tuning current density and electrolyte phosphorousmore » concentration, it is shown that electroplating can successfully span the same range of spalled thicknesses as has previously been demonstrated by sputtering and can reach sufficiently high stresses to enter a regime of thickness (<7 um) appropriate to minimize substrate consumption for device applications.« less

Increased fracture depth range in controlled spalling of (100)-oriented germanium via electroplating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crouse, Dustin; Simon, John; Schulte, Kevin L.

Controlled spalling in (100)-oriented germanium using a nickel stressor layer shows promise for semiconductor device exfoliation and kerfless wafering. Demonstrated spall depths of 7-60 um using DC sputtering to deposit the stressor layer are appropriate for the latter application but spall depths < 5 um may be required to minimize waste for device applications. This work investigates the effect of tuning both electroplating current density and electrolyte chemistry on the residual stress in the nickel and on the achievable spall depth range for the Ni/Ge system as a lower-cost, higher-throughput alternative to sputtering. By tuning current density and electrolyte phosphorousmore » concentration, it is shown that electroplating can successfully span the same range of spalled thicknesses as has previously been demonstrated by sputtering and can reach sufficiently high stresses to enter a regime of thickness (<7 um) appropriate to minimize substrate consumption for device applications.« less

Thermoelectric generator and method for the fabrication thereof

DOEpatents

Benson, David K.; Tracy, C. Edwin

1987-01-01

A thermoelectric generator using semiconductor elements for responding to a temperature gradient to produce electrical energy with all of the semiconductor elements being of the same type is disclosed. A continuous process for forming substrates on which the semiconductor elements and superstrates are deposited and a process for forming the semiconductor elements on the substrates are also disclosed. The substrates with the semiconductor elements thereon are combined with superstrates to form modules for use thermoelectric generators.

Thermoelectric generator and method for the fabrication thereof

DOEpatents

Benson, D.K.; Tracy, C.E.

1984-08-01

A thermoelectric generator using semiconductor elements for responding to a temperature gradient to produce electrical energy with all of the semiconductor elements being of the same type is disclosed. A continuous process for forming substrates on which the semiconductor elements and superstrates are deposited and a process for forming the semiconductor elements on the substrates are also disclosed. The substrates with the semiconductor elements thereon are combined with superstrates to form modules for use as thermoelectric generators.

First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

NASA Technical Reports Server (NTRS)

Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.;

Resonance ultrasonic vibrations in Cz-Si wafers as a possible diagnostic technique in ion implantation

NASA Astrophysics Data System (ADS)

Zhao, Z. Y.; Ostapenko, S.; Anundson, R.; Tvinnereim, M.; Belyaev, A.; Anthony, M.

2001-07-01

The semiconductor industry does not have effective metrology for well implants. The ability to measure such deep level implants will become increasingly important as we progress along the technology road map. This work explores the possibility of using the acoustic whistle effect on ion implanted silicon wafers. The technique detects the elastic stress and defects in silicon wafers by measuring the sub-harmonic f/2 resonant vibrations on a wafer induced via backside contact to create standing waves, which are measured by a non-contact ultrasonic probe. Preliminary data demonstrates that it is sensitive to implant damage, and there is a direct correlation between this sub-harmonic acoustic mode and some of the implant and anneal conditions. This work presents the results of a feasibility study to assess and quantify the correspondent whistle effect to implant damage, residual damage after annealing and intrinsic defects.

Silicon wafer temperature monitoring using all-fiber laser ultrasonics

NASA Astrophysics Data System (ADS)

Alcoz, Jorge J.; Duffer, Charles E.

1998-03-01

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

Study of thin film production of ceramic ZrO2 on silicon wafer using second harmonic Nd-Yag laser with pulsed laser deposition technique

NASA Astrophysics Data System (ADS)

Suliyanti, Maria M.; Hidayah, Affi Nur; Kurniawan, K. H.

2012-06-01

Study about thin film production using technique pulsed laser deposition have been done. The Pulsed Laser Deposition (PLD) method has been used for growing thin film of ZrO2 on silicon wafer substrate (111 single crystal, thickness 400μm and diameter 7.5 cm). The target made from Zirconia oxide powder mixing with PVA and press using pressure 100kgN. The laser beam was focused by a lens (f = 100mm) through a quartz window onto the sample surface and the substrate was placed in parallel line with target. The distance between the target and the substrate is about 1 cm. The early results of this synthesis using 75 mJ Nd-YAG second harmonic laser pulse (532 nm Nd-YAG) and low pressure chamber surrounding gas 5 Torr. The irradiation of laser take around 6000 shoots or 10 minutes using frequencies laser 10 Hz. The micro thickness of film can be produced on silicon wafer using this technique. The results of ZrO2 thin film on substrate about 26.92%.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2010 CFR

2010-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer... where wastewater undergoes treatment (such as pH adjustment) before discharge, and are not used to...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2011 CFR

2011-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer... where wastewater undergoes treatment (such as pH adjustment) before discharge, and are not used to...

A Knowledge Database on Thermal Control in Manufacturing Processes

NASA Astrophysics Data System (ADS)

Hirasawa, Shigeki; Satoh, Isao

A prototype version of a knowledge database on thermal control in manufacturing processes, specifically, molding, semiconductor manufacturing, and micro-scale manufacturing has been developed. The knowledge database has search functions for technical data, evaluated benchmark data, academic papers, and patents. The database also displays trends and future roadmaps for research topics. It has quick-calculation functions for basic design. This paper summarizes present research topics and future research on thermal control in manufacturing engineering to collate the information to the knowledge database. In the molding process, the initial mold and melt temperatures are very important parameters. In addition, thermal control is related to many semiconductor processes, and the main parameter is temperature variation in wafers. Accurate in-situ temperature measurment of wafers is important. And many technologies are being developed to manufacture micro-structures. Accordingly, the knowledge database will help further advance these technologies.

Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates

DOEpatents

Norman, Andrew G; Ptak, Aaron J

2013-08-13

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

X-Ray Diffraction Wafer Mapping Method for Rhombohedral Super-Hetero-Epitaxy

NASA Technical Reports Server (NTRS)

Park, Yoonjoon; Choi, Sang Hyouk; King, Glen C.; Elliott, James R.; Dimarcantonio, Albert L.

2010-01-01

A new X-ray diffraction (XRD) method is provided to acquire XY mapping of the distribution of single crystals, poly-crystals, and twin defects across an entire wafer of rhombohedral super-hetero-epitaxial semiconductor material. In one embodiment, the method is performed with a point or line X-ray source with an X-ray incidence angle approximating a normal angle close to 90 deg, and in which the beam mask is preferably replaced with a crossed slit. While the wafer moves in the X and Y direction, a narrowly defined X-ray source illuminates the sample and the diffracted X-ray beam is monitored by the detector at a predefined angle. Preferably, the untilted, asymmetric scans are of {440} peaks, for twin defect characterization.

Substrate induced changes in atomically thin 2-dimensional semiconductors: Fundamentals, engineering, and applications

NASA Astrophysics Data System (ADS)

Sun, Yinghui; Wang, Rongming; Liu, Kai

2017-03-01

Substrate has great influences on materials syntheses, properties, and applications. The influences are particularly crucial for atomically thin 2-dimensional (2D) semiconductors. Their thicknesses are less than 1 nm; however, the lateral sizes can reach up to several inches or more. Therefore, these materials must be placed onto a variety of substrates before subsequent post-processing techniques for final electronic or optoelectronic devices. Recent studies reveal that substrates have been employed as ways to modulate the optical, electrical, mechanical, and chemical properties of 2D semiconductors. In this review, we summarize recent progress upon the effects of substrates on properties of 2D semiconductors, mostly focused on 2D transition metal dichalcogenides, through viewpoints of both fundamental physics and device applications. First, we discuss various effects of substrates, including interface strain, charge transfer, dielectric screening, and optical interference. Second, we show the modulation of 2D semiconductors by substrate engineering, including novel substrates (patterned substrates, 2D-material substrates, etc.) and active substrates (phase transition materials, ferroelectric materials, flexible substrates, etc.). Last, we present prospectives and challenges in this research field. This review provides a comprehensive understanding of the substrate effects, and may inspire new ideas of novel 2D devices based on substrate engineering.

Substrate solder barriers for semiconductor epilayer growth

DOEpatents

Drummond, Timothy J.; Ginley, David S.; Zipperian, Thomas E.

1989-01-01

During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

Substrate solder barriers for semiconductor epilayer growth

DOEpatents

Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

1989-05-09

During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

Epitaxial gallium arsenide wafers

NASA Technical Reports Server (NTRS)

Black, J. F.; Robinson, L. B.

1971-01-01

The preparation of GaAs epitaxial layers by a vapor transport process using AsCl3, Ga and H2 was pursued to provide epitaxial wafers suitable for the fabrication of transferred electron oscillators and amplifiers operating in the subcritical region. Both n-n(+) structures, and n(++)-n-n(+) sandwich structures were grown using n(+) (Si-doped) GaAs substrates. Process variables such as the input AsCl3 concentration, gallium temperature, and substrate temperature and temperature gradient and their effects on properties are presented and discussed.

Overlay improvements using a real time machine learning algorithm

NASA Astrophysics Data System (ADS)

Schmitt-Weaver, Emil; Kubis, Michael; Henke, Wolfgang; Slotboom, Daan; Hoogenboom, Tom; Mulkens, Jan; Coogans, Martyn; ten Berge, Peter; Verkleij, Dick; van de Mast, Frank

2014-04-01

While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system's sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on-wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.

High voltage photo switch package module

DOEpatents

Sullivan, James S; Sanders, David M; Hawkins, Steven A; Sampayan, Stephen E

2014-02-18

A photo-conductive switch package module having a photo-conductive substrate or wafer with opposing electrode-interface surfaces, and at least one light-input surface. First metallic layers are formed on the electrode-interface surfaces, and one or more optical waveguides having input and output ends are bonded to the substrate so that the output end of each waveguide is bonded to a corresponding one of the light-input surfaces of the photo-conductive substrate. This forms a waveguide-substrate interface for coupling light into the photo-conductive wafer. A dielectric material such as epoxy is then used to encapsulate the photo-conductive substrate and optical waveguide so that only the metallic layers and the input end of the optical waveguide are exposed. Second metallic layers are then formed on the first metallic layers so that the waveguide-substrate interface is positioned under the second metallic layers.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Nondestructive SEM for surface and subsurface wafer imaging

NASA Technical Reports Server (NTRS)

Propst, Roy H.; Bagnell, C. Robert; Cole, Edward I., Jr.; Davies, Brian G.; Dibianca, Frank A.; Johnson, Darryl G.; Oxford, William V.; Smith, Craig A.

1987-01-01

The scanning electron microscope (SEM) is considered as a tool for both failure analysis as well as device characterization. A survey is made of various operational SEM modes and their applicability to image processing methods on semiconductor devices.

Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gajski, D.D.; Sameh, A.H.; Wisniewski, J.A.

1982-01-01

With the rapid advances in semiconductor technology, the construction of Wafer Scale Integration (WSI)-multiprocessors consisting of a large number of processors is now feasible. We illustrate the implementation of some basic linear algebra algorithms on such multiprocessors.

Deposition method for producing silicon carbide high-temperature semiconductors

DOEpatents

Hsu, George C.; Rohatgi, Naresh K.

1987-01-01

An improved deposition method for producing silicon carbide high-temperature semiconductor material comprising placing a semiconductor substrate composed of silicon carbide in a fluidized bed silicon carbide deposition reactor, fluidizing the bed particles by hydrogen gas in a mildly bubbling mode through a gas distributor and heating the substrate at temperatures around 1200.degree.-1500.degree. C. thereby depositing a layer of silicon carbide on the semiconductor substrate.

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

PubMed

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

Die singulation method and package formed thereby

DOEpatents

Anderson, Robert C [Tucson, AZ; Shul, Randy J [Albuquerque, NM; Clews, Peggy J [Tijeras, NM; Baker, Michael S [Albuquerque, NM; De Boer, Maarten P [Albuquerque, NM

2012-08-07

A method is disclosed for singulating die from a substrate having a sacrificial layer and one or more device layers, with a retainer being formed in the device layer(s) and anchored to the substrate. Deep Reactive Ion Etching (DRIE) etching of a trench through the substrate from the bottom side defines a shape for each die. A handle wafer is then attached to the bottom side of the substrate, and the sacrificial layer is etched to singulate the die and to form a frame from the retainer and the substrate. The frame and handle wafer, which retain the singulated die in place, can be attached together with a clamp or a clip and to form a package for the singulated die. One or more stops can be formed from the device layer(s) to limit a sliding motion of the singulated die.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

PubMed

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

Light emitting diode with porous SiC substrate and method for fabricating

DOEpatents

Li, Ting; Ibbetson, James; Keller, Bernd

2005-12-06

A method and apparatus for forming a porous layer on the surface of a semiconductor material wherein an electrolyte is provided and is placed in contact with one or more surfaces of a layer of semiconductor material. The electrolyte is heated and a bias is introduced across said electrolyte and the semiconductor material causing a current to flow between the electrolyte and the semiconductor material. The current forms a porous layer on the one or more surfaces of the semiconductor material in contact with the electrolyte. The semiconductor material with its porous layer can serve as a substrate for a light emitter. A semiconductor emission region can be formed on the substrate. The emission region is capable of emitting light omnidirectionally in response to a bias, with the porous layer enhancing extraction of the emitting region light passing through the substrate.

Combined VIS-IR spectrometer with vertical probe beam

NASA Astrophysics Data System (ADS)

Protopopov, V.

2017-12-01

A prototype of a combined visible-infrared spectrometer with a vertical probe beam is designed and tested. The combined spectral range is 0.4-20 μ with spatial resolution 1 mm. Basic features include the ability to measure both visibly transparent and opaque substances, as well as buried structures, such as in semiconductor industry; horizontal orientation of a sample, including semiconductor wafers; and reflection mode of operation, delivering twice the sensitivity compared to the transmission mode.

Atomically Flat Surfaces Developed for Improved Semiconductor Devices

NASA Technical Reports Server (NTRS)

Powell, J. Anthony

2001-01-01

New wide bandgap semiconductor materials are being developed to meet the diverse high temperature, -power, and -frequency demands of the aerospace industry. Two of the most promising emerging materials are silicon carbide (SiC) for high-temperature and high power applications and gallium nitride (GaN) for high-frequency and optical (blue-light-emitting diodes and lasers) applications. This past year Glenn scientists implemented a NASA-patented crystal growth process for producing arrays of device-size mesas whose tops are atomically flat (i.e., step-free). It is expected that these mesas can be used for fabricating SiC and GaN devices with major improvements in performance and lifetime. The promising new SiC and GaN devices are fabricated in thin-crystal films (known as epi films) that are grown on commercial single-crystal SiC wafers. At this time, no commercial GaN wafers exist. Crystal defects, known as screw defects and micropipes, that are present in the commercial SiC wafers propagate into the epi films and degrade the performance and lifetime of subsequently fabricated devices. The new technology isolates the screw defects in a small percentage of small device-size mesas on the surface of commercial SiC wafers. This enables atomically flat surfaces to be grown on the remaining defect-free mesas. We believe that the atomically flat mesas can also be used to grow GaN epi films with a much lower defect density than in the GaN epi films currently being grown. Much improved devices are expected from these improved low-defect epi films. Surface-sensitive SiC devices such as Schottky diodes and field effect transistors should benefit from atomically flat substrates. Also, we believe that the atomically flat SiC surface will be an ideal surface on which to fabricate nanoscale sensors and devices. The process for achieving atomically flat surfaces is illustrated. The surface steps present on the "as-received" commercial SiC wafer is also illustrated. because of the small tilt angle between the crystal "basal" plane and the polished wafer surface. These steps are used in normal SiC epi film growth in a process known as stepflow growth to produce material for device fabrication. In the new process, the first step is to etch an array of mesas on the SiC wafer top surface. Then, epi film growth is carried out in the step flow fashion until all steps have grown themselves out of existence on each defect-free mesa. If the size of the mesas is sufficiently small (about 0.1 by 0.1 mm), then only a small percentage of the mesas will contain an undesired screw defect. Mesas with screw defects supply steps during the growth process, allowing a rough surface with unwanted hillocks to form on the mesa. The improvement in SiC epi surface morphology achievable with the new technology is shown. An atomic force microscope image of a typical SiC commercial epilayer surface is also shown. A similar image of an SiC atomically flat epi surface grown in a Glenn laboratory is given. With the current screw defect density of commercial wafers (about 5000 defects/cm2), the yield of atomically free 0.1 by 0.l mm mesas is expected to be about 90 percent. This is large enough for many types of electronic and optical devices. The implementation of this new technology was recently published in Applied Physics Letters. This work was initially carried out in-house under a Director's Discretionary Fund project and is currently being further developed under the Information Technology Base Program.

Electrically-pumped 850-nm micromirror VECSELs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Geib, Kent Martin; Peake, Gregory Merwin; Serkland, Darwin Keith

Vertical-external-cavity surface-emitting lasers (VECSELs) combine high optical power and good beam quality in a device with surface-normal output. In this paper, we describe the design and operating characteristics of an electrically-pumped VECSEL that employs a wafer-scale fabrication process and operates at 850 nm. A curved micromirror output coupler is heterogeneously integrated with AlGaAs-based semiconductor material to form a compact and robust device. The structure relies on flip-chip bonding the processed epitaxial material to an aluminum nitride mount; this heatsink both dissipates thermal energy and permits high frequency modulation using coplanar traces that lead to the VECSEL mesa. Backside emission ismore » employed, and laser operation at 850 nm is made possible by removing the entire GaAs substrate through selective wet etching. While substrate removal eliminates absorptive losses, it simultaneously compromises laser performance by increasing series resistance and degrading the spatial uniformity of current injection. Several aspects of the VECSEL design help to mitigate these issues, including the use of a novel current-spreading n type distributed Bragg reflector (DBR). Additionally, VECSEL performance is improved through the use of a p-type DBR that is modified for low thermal resistance.« less

Electrically pumped 850-nm micromirror VECSELs

NASA Astrophysics Data System (ADS)

Keeler, Gordon A.; Serkland, Darwin K.; Geib, Kent M.; Peake, Gregory M.; Mar, Alan

2005-03-01

Vertical-external-cavity surface-emitting lasers (VECSELs) combine high optical power and good beam quality in a device with surface-normal output. In this paper, we describe the design and operating characteristics of an electrically-pumped VECSEL that employs a wafer-scale fabrication process and operates at 850 nm. A curved micromirror output coupler is heterogeneously integrated with AlGaAs-based semiconductor material to form a compact and robust device. The structure relies on flip-chip bonding the processed epitaxial material to an aluminum nitride mount; this heatsink both dissipates thermal energy and permits high frequency modulation using coplanar traces that lead to the VECSEL mesa. Backside emission is employed, and laser operation at 850 nm is made possible by removing the entire GaAs substrate through selective wet etching. While substrate removal eliminates absorptive losses, it simultaneously compromises laser performance by increasing series resistance and degrading the spatial uniformity of current injection. Several aspects of the VECSEL design help to mitigate these issues, including the use of a novel current-spreading n type distributed Bragg reflector (DBR). Additionally, VECSEL performance is improved through the use of a p-type DBR that is modified for low thermal resistance.

Prospects of III-nitride optoelectronics grown on Si.

PubMed

Zhu, D; Wallis, D J; Humphreys, C J

2013-10-01

The use of III-nitride-based light-emitting diodes (LEDs) is now widespread in applications such as indicator lamps, display panels, backlighting for liquid-crystal display TVs and computer screens, traffic lights, etc. To meet the huge market demand and lower the manufacturing cost, the LED industry is moving fast from 2 inch to 4 inch and recently to 6 inch wafer sizes. Although Al2O3 (sapphire) and SiC remain the dominant substrate materials for the epitaxy of nitride LEDs, the use of large Si substrates attracts great interest because Si wafers are readily available in large diameters at low cost. In addition, such wafers are compatible with existing processing lines for 6 inch and larger wafers commonly used in the electronics industry. During the last decade, much exciting progress has been achieved in improving the performance of GaN-on-Si devices. In this contribution, the status and prospects of III-nitride optoelectronics grown on Si substrates are reviewed. The issues involved in the growth of GaN-based LED structures on Si and possible solutions are outlined, together with a brief introduction to some novel in situ and ex situ monitoring/characterization tools, which are especially useful for the growth of GaN-on-Si structures.

CMUT Fabrication Based On A Thick Buried Oxide Layer.

PubMed

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O; Khuri-Yakub, Butrus T

2010-10-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required - in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate.

CMUT Fabrication Based On A Thick Buried Oxide Layer

PubMed Central

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O.; Khuri-Yakub, Butrus T.

2010-01-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required – in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate. PMID:22685377

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

NASA Astrophysics Data System (ADS)

Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

2014-08-01

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

NASA Technical Reports Server (NTRS)

Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

1997-01-01

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

High-performance and scalable metal-chalcogenide semiconductors and devices via chalco-gel routes

PubMed Central

Jo, Jeong-Wan; Kim, Hee-Joong; Kwon, Hyuck-In; Kim, Jaekyun; Ahn, Sangdoo; Kim, Yong-Hoon; Lee, Hyung-ik

2018-01-01

We report a general strategy for obtaining high-quality, large-area metal-chalcogenide semiconductor films from precursors combining chelated metal salts with chalcoureas or chalcoamides. Using conventional organic solvents, such precursors enable the expeditious formation of chalco-gels, which are easily transformed into the corresponding high-performance metal-chalcogenide thin films with large, uniform areas. Diverse metal chalcogenides and their alloys (MQx: M = Zn, Cd, In, Sb, Pb; Q = S, Se, Te) are successfully synthesized at relatively low processing temperatures (<400°C). The versatility of this scalable route is demonstrated by the fabrication of large-area thin-film transistors (TFTs), optoelectronic devices, and integrated circuits on a 4-inch Si wafer and 2.5-inch borosilicate glass substrates in ambient air using CdS, CdSe, and In2Se3 active layers. The CdSe TFTs exhibit a maximum field-effect mobility greater than 300 cm2 V−1 s−1 with an on/off current ratio of >107 and good operational stability (threshold voltage shift < 0.5 V at a positive gate bias stress of 10 ks). In addition, metal chalcogenide–based phototransistors with a photodetectivity of >1013 Jones and seven-stage ring oscillators operating at a speed of ~2.6 MHz (propagation delay of < 27 ns per stage) are demonstrated. PMID:29662951

Graphene optical modulator

NASA Astrophysics Data System (ADS)

Liu, Ming; Yin, Xiaobo; Wang, Feng; Zhang, Xiang

2011-10-01

Data communications have been growing at a speed even faster than Moore's Law, with a 44-fold increase expected within the next 10 years. Data Transfer on such scale would have to recruit optical communication technology and inspire new designs of light sources, modulators, and photodetectors. An ideal optical modulator will require high modulation speed, small device footprint and large operating bandwidth. Silicon modulators based on free carrier plasma dispersion effect and compound semiconductors utilizing direct bandgap transition have seen rapid improvement over the past decade. One of the key limitations for using silicon as modulator material is its weak refractive index change, which limits the footprint of silicon Mach-Zehnder interferometer modulators to millimeters. Other approaches such as silicon microring modulators reduce the operation wavelength range to around 100 pm and are highly sensitive to typical fabrication tolerances and temperature fluctuations. Growing large, high quality wafers of compound semiconductors, and integrating them on silicon or other substrates is expensive, which also restricts their commercialization. In this work, we demonstrate that graphene can be used as the active media for electroabsorption modulators. By tuning the Fermi energy level of the graphene layer, we induced changes in the absorption coefficient of graphene at communication wavelength and achieve a modulation depth above 3 dB. This integrated device also has the potential of working at high speed.

Artifacts for Calibration of Submicron Width Measurements

NASA Technical Reports Server (NTRS)

Grunthaner, Frank; Grunthaner, Paula; Bryson, Charles, III

2003-01-01

Artifacts that are fabricated with the help of molecular-beam epitaxy (MBE) are undergoing development for use as dimensional calibration standards with submicron widths. Such standards are needed for calibrating instruments (principally, scanning electron microscopes and scanning probe microscopes) for measuring the widths of features in advanced integrated circuits. Dimensional calibration standards fabricated by an older process that involves lithography and etching of trenches in (110) surfaces of single-crystal silicon are generally reproducible to within dimensional tolerances of about 15 nm. It is anticipated that when the artifacts of the present type are fully developed, their critical dimensions will be reproducible to within 1 nm. These artifacts are expected to find increasing use in the semiconductor-device and integrated- circuit industries as the width tolerances on semiconductor devices shrink to a few nanometers during the next few years. Unlike in the older process, one does not rely on lithography and etching to define the critical dimensions. Instead, one relies on the inherent smoothness and flatness of MBE layers deposited under controlled conditions and defines the critical dimensions as the thicknesses of such layers. An artifact of the present type is fabricated in two stages (see figure): In the first stage, a multilayer epitaxial wafer is grown on a very flat substrate. In the second stage, the wafer is cleaved to expose the layers, then the exposed layers are differentially etched (taking advantage of large differences between the etch rates of the different epitaxial layer materials). The resulting structure includes narrow and well-defined trenches and a shelf with thicknesses determined by the thicknesses of the epitaxial layers from which they were etched. Eventually, it should be possible to add a third fabrication stage in which durable, electronically inert artifacts could be replicated in diamondlike carbon from a master made by MBE and etching as described above.

Substrate solder barriers for semiconductor epilayer growth

DOEpatents

Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

1987-10-23

During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In molecular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating. 1 tab.

Research and Development Strategies in the Semiconductor Industry

NASA Astrophysics Data System (ADS)

Bowling, Allen

2003-03-01

In the 21st Century semiconductor industry, there is a critical balance between internally funded semiconductor research and development (R) and externally funded R. External R may include jointly-funded research collaborations/partnerships with other device manufacturers, jointly-funded consortia-based R, and individually-funded research programs at universities and other contract research locations. Each of these approaches has merits and each has costs. There is a critical balance between keeping the internal research and development pipeline filled and keeping it from being overspent. To meet both competitive schedule and cost goals, a semiconductor device manufacturer must decide on a model for selection of internal versus external R. Today, one of the most critical decisions is whether or not to do semiconductor research and development on 300 mm silicon wafers. Equipment suppliers are doing first development on 300 mm equipment. So, for the device manufacturer, there is a balance between the cost of doing development on 300 mm wafers and the development time schedule driven by equipment availability. In the face of these cost and schedule elements, device manufacturers are looking to consortia such as SEMATECH, SRC, and SRC MARCO for early development and screening of new materials and device structure approaches. This also causes much more close development collaboration between device manufacturer and equipment supplier. Many device manufacturers are also making use of direct contract research with universities and other contract-research organizations, such as IMEC, LETI, and other government-funded research organizations around the world. To get the most out of these external research interactions, the company must develop a strategy for management and technology integration of external R.

Clean solutions to the incoming wafer quality impact on lithography process yield limits in a dynamic copper/low-k research and development environment

NASA Astrophysics Data System (ADS)

Lysaght, Patrick S.; Ybarra, Israel; Sax, Harry; Gupta, Gaurav; West, Michael; Doros, Theodore G.; Beach, James V.; Mello, Jim

2000-06-01

The continued growth of the semiconductor manufacturing industry has been due, in large part, to improved lithographic resolution and overlay across increasingly larger chip areas. Optical lithography continues to be the mainstream technology for the industry with extensions of optical lithography being employed to support 180 nm product and process development. While the industry momentum is behind optical extensions to 130 nm, the key challenge will be maintaining an adequate and affordable process latitude (depth of focus/exposure window) necessary for 10% post-etch critical dimension (CD) control. If the full potential of optical lithography is to be exploited, the current lithographic systems can not be compromised by incoming wafer quality. Impurity specifications of novel Low-k dielectric materials, plating solutions, chemical-mechanical planarization (CMP) slurries, and chemical vapor deposition (CVD) precursors are not well understood and more stringent control measures will be required to meet defect density targets as identified in the National Technology Roadmap for Semiconductors (NTRS). This paper identifies several specific poor quality wafer issues that have been effectively addressed as a result of the introduction of a set of flexible and reliable wafer back surface clean processes developed on the SEZ Spin-Processor 203 configured for processing of 200 mm diameter wafers. Patterned wafers have been back surface etched by means of a novel spin process contamination elimination (SpCE) technique with the wafer suspended by a dynamic nitrogen (N2) flow, device side down, via the Bernoulli effect. Figure 1 illustrates the wafer-chuck orientation within the process chamber during back side etch processing. This paper addresses a number of direct and immediate benefits to the MicraScan IIITM deep-ultraviolet (DUV) step-and-scan system at SEMATECH. These enhancements have resulted from the resolution of three significant problems: (1) back surface particle/residual contamination, (2) wafer flatness, and (3) control of contaminant materials such as copper (Cu). Data associated with the SpCE process, optimized for flatness improvement, particle removal, and Cu contamination control is presented in this paper, as it relates to excessive consumption of the usable depth of focus (UDOF) and comprehensive yield enhancement in photolithography. Additionally, data illustrating a highly effective means of eliminating copper from the wafer backside, bevel/edge, and frontside edge exclusion zone (0.5 mm - 3 mm), is presented. The data, obtained within the framework of standard and experimental copper/low-k device production at SEMATECH, quantifies the benefits of implementing the SEZ SpCE clean operation. Furthermore, this data confirms the feasibility of utilizing existing (non-copper) process equipment in conjunction with the development of copper applications by verifying the reliability and cost effectiveness of SpCE functionality.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

On the design of GaN vertical MESFETs on commercial LED sapphire wafers

NASA Astrophysics Data System (ADS)

Atalla, Mahmoud R. M.; Noor Elahi, Asim M.; Mo, Chen; Jiang, Zhenyu; Liu, Jie; Ashok, S.; Xu, Jian

2016-12-01

Design of GaN-based vertical metal-semiconductor field-effect transistors (MESFETs) on commercial light-emitting-diode (LED) epi-wafers has been proposed and proof of principle devices have been fabricated. In order to better understand the IV curves, these devices have been simulated using the charge transport model. It was found that shrinking the drain pillar size would significantly help in reaching cut-off at much lower gate bias even at high carrier concentration of unintentionally doped GaN and considerable leakage current caused by the Schottky barrier lowering. The realization of these vertical MESFETs on LED wafers would allow their chip-level integration. This would open a way to many intelligent lighting applications like on-chip current regulator and signal regulation/communication in display technology.

Nonvolatile and Cryogenic-compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

Nonvolatile and Cryogenic-Compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

Coincident site lattice-matched growth of semiconductors on substrates using compliant buffer layers

DOEpatents

Norman, Andrew

2016-08-23

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.

Measurement and thermal modeling of sapphire substrate temperature at III-Nitride MOVPE conditions

DOE PAGES

Creighton, J. Randall; Coltrin, Michael E.; Figiel, Jeffrey J.

2017-04-01

Here, growth rates and alloy composition of AlGaN grown by MOVPE is often very temperature dependent due to the presence of gas-phase parasitic chemical processes. These processes make wafer temperature measurement highly important, but in fact such measurements are very difficult because of substrate transparency in the near- IR (~900 nm) where conventional pyrometers detect radiation. The transparency problem can be solved by using a mid-IR pyrometer operating at a wavelength (~7500 nm) where sapphire is opaque. We employ a mid- IR pyrometer to measure the sapphire wafer temperature and simultaneously a near-IR pyrometer to measure wafer pocket temperature, whilemore » varying reactor pressure in both a N 2 and H 2 ambient. Near 1300 °C, as the reactor pressure is lowered from 300 Torr to 10 Torr the wafer temperature drops dramatically, and the ΔT between the pocket and wafer increases from ~20 °C to ~250 °C. Without the mid-IR pyrometer the large wafer temperature change with pressure would not have been noted. In order to explain this behavior we have developed a quasi-2D thermal model that includes a proper accounting of the pressure-dependent thermal contact resistance, and also accounts for sapphire optical transmission. The model and experimental results demonstrate that at most growth conditions the majority of the heat is transported from the wafer pocket to the wafer via gas conduction, in the free molecular flow limit. In this limit gas conductivity is independent of gap size but first order in pressure, and can quantitatively explain results from 20 to 300 Torr. Further analysis yields a measure of the thermal accommodation coefficients; α(H 2) =0.23, α(N 2) =0.50, which are in the range typically measured.« less

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

NASA Astrophysics Data System (ADS)

Doering, Robert

In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

NASA Astrophysics Data System (ADS)

Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

2018-06-01

Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

Wafer-scale growth of VO2 thin films using a combinatorial approach

PubMed Central

Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

2015-01-01

Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

PubMed

Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

2003-12-01

Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

Hybrid Integration of III-V Solar Microcells for High Efficiency Concentrated Photovoltaic Modules

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tauke-Pedretti, Anna; Cederberg, Jeffery; Cruz-Campa, Jose Luis

The design, fabrication and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process which involved significant processing including the removal of the III-V substrate. Results from a number of hybrid cell configurations were reported. These cells employed integration techniques including wafer level bonding of processed cells and solder bonding of the cells. Lastly, the cells themselvesmore » showed evidence of degradation in spite of the integration process, which involved significant processing including the removal of the III-V substrate.« less

Hybrid Integration of III-V Solar Microcells for High Efficiency Concentrated Photovoltaic Modules

DOE PAGES

Tauke-Pedretti, Anna; Cederberg, Jeffery; Cruz-Campa, Jose Luis; ...

2018-03-09

The design, fabrication and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process which involved significant processing including the removal of the III-V substrate. Results from a number of hybrid cell configurations were reported. These cells employed integration techniques including wafer level bonding of processed cells and solder bonding of the cells. Lastly, the cells themselvesmore » showed evidence of degradation in spite of the integration process, which involved significant processing including the removal of the III-V substrate.« less

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

DTIC Science & Technology

2013-05-01

to this point. The inability to create GaN ingots as cost effective substrates (or Silicon Carbide ingots coupled with GaN deposition) means that...was vastly different than standard Silicon CMOS (e.g. HEMTs and GaN channel devices were included, but not III-V-channel MOS or Germanium-channel MOS...the same wafer, wafer bonding has been used by Chung et al. to attach GaN to Silicon wafers, where a p-type Si device can be used [15]. Since

78 FR 73886 - Atmel Corporation, Colorado Springs, Colorado; Amended Certification Regarding Eligibility To...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-12-09

..., Colorado Springs, Colorado; Amended Certification Regarding Eligibility To Apply for Worker Adjustment..., 2013, applicable to workers of Atmel Corporation, Colorado Springs, Colorado. The Department's notice..., Colorado Springs, Colorado were engaged in activities related to production of semiconductor wafers and...

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

PubMed

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

Experimental setup for camera-based measurements of electrically and optically stimulated luminescence of silicon solar cells and wafers.

PubMed

Hinken, David; Schinke, Carsten; Herlufsen, Sandra; Schmidt, Arne; Bothe, Karsten; Brendel, Rolf

2011-03-01

We report in detail on the luminescence imaging setup developed within the last years in our laboratory. In this setup, the luminescence emission of silicon solar cells or silicon wafers is analyzed quantitatively. Charge carriers are excited electrically (electroluminescence) using a power supply for carrier injection or optically (photoluminescence) using a laser as illumination source. The luminescence emission arising from the radiative recombination of the stimulated charge carriers is measured spatially resolved using a camera. We give details of the various components including cameras, optical filters for electro- and photo-luminescence, the semiconductor laser and the four-quadrant power supply. We compare a silicon charged-coupled device (CCD) camera with a back-illuminated silicon CCD camera comprising an electron multiplier gain and a complementary metal oxide semiconductor indium gallium arsenide camera. For the detection of the luminescence emission of silicon we analyze the dominant noise sources along with the signal-to-noise ratio of all three cameras at different operation conditions.

Highly-efficient GaN-based light-emitting diode wafers on La0.3Sr1.7AlTaO6 substrates

PubMed Central

Wang, Wenliang; Yang, Weijia; Gao, Fangliang; Lin, Yunhao; Li, Guoqiang

2015-01-01

Highly-efficient GaN-based light-emitting diode (LED) wafers have been grown on La0.3Sr1.7AlTaO6 (LSAT) substrates by radio-frequency molecular beam epitaxy (RF-MBE) with optimized growth conditions. The structural properties, surface morphologies, and optoelectronic properties of as-prepared GaN-based LED wafers on LSAT substrates have been characterized in detail. The characterizations have revealed that the full-width at half-maximums (FWHMs) for X-ray rocking curves of GaN(0002) and GaN(10-12) are 190.1 and 210.2 arcsec, respectively, indicating that high crystalline quality GaN films have been obtained. The scanning electron microscopy and atomic force microscopy measurements have shown the very smooth p-GaN surface with the surface root-mean-square (RMS) roughness of 1.3 nm. The measurements of low-temperature and room-temperature photoluminescence help to calculate the internal quantum efficiency of 79.0%. The as-grown GaN-based LED wafers have been made into LED chips with the size of 300 × 300 μm2 by the standard process. The forward voltage, the light output power and the external quantum efficiency for LED chips are 19.6 W, 2.78 V, and 40.2%, respectively, at a current of 20 mA. These results reveal the high optoelectronic properties of GaN-based LEDs on LSAT substrates. This work brings up a broad future application of GaN-based devices. PMID:25799042

Group I-III-VI.sub.2 semiconductor films for solar cell application

DOEpatents

Basol, Bulent M.; Kapur, Vijay K.

1991-01-01

This invention relates to an improved thin film solar cell with excellent electrical and mechanical integrity. The device comprises a substrate, a Group I-III-VI.sub.2 semiconductor absorber layer and a transparent window layer. The mechanical bond between the substrate and the Group I-III-VI.sub.2 semiconductor layer is enhanced by an intermediate layer between the substrate and the Group I-III-VI.sub.2 semiconductor film being grown. The intermediate layer contains tellurium or substitutes therefor, such as Se, Sn, or Pb. The intermediate layer improves the morphology and electrical characteristics of the Group I-III-VI.sub.2 semiconductor layer.

Monolithic integrated high-T.sub.c superconductor-semiconductor structure

NASA Technical Reports Server (NTRS)

Barfknecht, Andrew T. (Inventor); Garcia, Graham A. (Inventor); Russell, Stephen D. (Inventor); Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Clayton, Stanley R. (Inventor)

2000-01-01

A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Method of transferring strained semiconductor structure

DOEpatents

Nastasi, Michael A [Santa Fe, NM; Shao, Lin [College Station, TX

2009-12-29

The transfer of strained semiconductor layers from one substrate to another substrate involves depositing a multilayer structure on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the deposited multilayer structure is bonded to a second substrate and is separated away at the interface, which results in transferring a multilayer structure from one substrate to the other substrate. The multilayer structure includes at least one strained semiconductor layer and at least one strain-induced seed layer. The strain-induced seed layer can be optionally etched away after the layer transfer.

Single Layer Broadband Anti-Reflective Coatings for Plastic Substrates Produced by Full Wafer and Roll-to-Roll Step-and-Flash Nano-Imprint Lithography

PubMed Central

Burghoorn, Marieke; Roosen-Melsen, Dorrit; de Riet, Joris; Sabik, Sami; Vroon, Zeger; Yakimets, Iryna; Buskens, Pascal

2013-01-01

Anti-reflective coatings (ARCs) are used to lower the reflection of light on the surface of a substrate. Here, we demonstrate that the two main drawbacks of moth eye-structured ARCs—i.e., the lack of suitable coating materials and a process for large area, high volume applications—can be largely eliminated, paving the way for cost-efficient and large-scale production of durable moth eye-structured ARCs on polymer substrates. We prepared moth eye coatings on polymethylmethacrylate (PMMA) and polycarbonate using wafer-by-wafer step-and-flash nano-imprint lithography (NIL). The reduction in reflection in the visible field achieved with these coatings was 3.5% and 4.0%, respectively. The adhesion of the coating to both substrates was good. The moth eye coating on PMMA demonstrated good performance in three prototypical accelerated ageing tests. The pencil hardness of the moth eye coatings on both substrates was <4B, which is less than required for most applications and needs further optimization. Additionally, we developed a roll-to-roll UV NIL pilot scale process and produced moth eye coatings on polyethylene terephthalate (PET) at line speeds up to two meters per minute. The resulting coatings showed a good replication of the moth eye structures and, consequently, a lowering in reflection of the coated PET of 3.0%. PMID:28788301

Semiconductor laser using multimode interference principle

NASA Astrophysics Data System (ADS)

Gong, Zisu; Yin, Rui; Ji, Wei; Wu, Chonghao

2018-01-01

Multimode interference (MMI) structure is introduced in semiconductor laser used in optical communication system to realize higher power and better temperature tolerance. Using beam propagation method (BPM), Multimode interference laser diode (MMI-LD) is designed and fabricated in InGaAsP/InP based material. As a comparison, conventional semiconductor laser using straight single-mode waveguide is also fabricated in the same wafer. With a low injection current (about 230 mA), the output power of the implemented MMI-LD is up to 2.296 mW which is about four times higher than the output power of the conventional semiconductor laser. The implemented MMI-LD exhibits stable output operating at the wavelength of 1.52 μm and better temperature tolerance when the temperature varies from 283.15 K to 293.15 K.

ALD-Developed Plasmonic Two-Dimensional Au-WO3-TiO2 Heterojunction Architectonics for Design of Photovoltaic Devices.

PubMed

Karbalaei Akbari, Mohammad; Hai, Zhenyin; Wei, Zihan; Detavernier, Christophe; Solano, Eduardo; Verpoort, Francis; Zhuiykov, Serge

2018-03-28

Electrically responsive plasmonic devices, which benefit from the privilege of surface plasmon excited hot carries, have supported fascinating applications in the visible-light-assisted technologies. The properties of plasmonic devices can be tuned by controlling charge transfer. It can be attained by intentional architecturing of the metal-semiconductor (MS) interfaces. In this study, the wafer-scaled fabrication of two-dimensional (2D) TiO 2 semiconductors on the granular Au metal substrate is achieved using the atomic layer deposition (ALD) technique. The ALD-developed 2D MS heterojunctions exhibited substantial enhancement of the photoresponsivity and demonstrated the improvement of response time for 2D Au-TiO 2 -based plasmonic devices under visible light illumination. To circumvent the undesired dark current in the plasmonic devices, a 2D WO 3 nanofilm (∼0.7 nm) was employed as the intermediate layer on the MS interface to develop the metal-insulator-semiconductor (MIS) 2D heterostructure. As a result, 13.4% improvement of the external quantum efficiency was obtained for fabricated 2D Au-WO 3 -TiO 2 heterojunctions. The impedancometry measurements confirmed the modulation of charge transfer at the 2D MS interface using MIS architectonics. Broadband photoresponsivity from the UV to the visible light region was observed for Au-TiO 2 and Au-WO 3 -TiO 2 heterostructures, whereas near-infrared responsivity was not observed. Consequently, considering the versatile nature of the ALD technique, this approach can facilitate the architecturing and design of novel 2D MS and MIS heterojunctions for efficient plasmonic devices.

Ultra-wideband WDM VCSEL arrays by lateral heterogeneous integration

NASA Astrophysics Data System (ADS)

Geske, Jon

Advancements in heterogeneous integration are a driving factor in the development of evermore sophisticated and functional electronic and photonic devices. Such advancements will merge the optical and electronic capabilities of different material systems onto a common integrated device platform. This thesis presents a new lateral heterogeneous integration technology called nonplanar wafer bonding. The technique is capable of integrating multiple dissimilar semiconductor device structures on the surface of a substrate in a single wafer bond step, leaving different integrated device structures adjacent to each other on the wafer surface. Material characterization and numerical simulations confirm that the material quality is not compromised during the process. Nonplanar wafer bonding is used to fabricate ultra-wideband wavelength division multiplexed (WDM) vertical-cavity surface-emitting laser (VCSEL) arrays. The optically-pumped VCSEL arrays span 140 nm from 1470 to 1610 nm, a record wavelength span for devices operating in this wavelength range. The array uses eight wavelength channels to span the 140 nm with all channels separated by precisely 20 nm. All channels in the array operate single mode to at least 65°C with output power uniformity of +/- 1 dB. The ultra-wideband WDM VCSEL arrays are a significant first step toward the development of a single-chip source for optical networks based on coarse WDM (CWDM), a low-cost alternative to traditional dense WDM. The CWDM VCSEL arrays make use of fully-oxidized distributed Bragg reflectors (DBRs) to provide the wideband reflectivity required for optical feedback and lasing across 140 rim. In addition, a novel optically-pumped active region design is presented. It is demonstrated, with an analytical model and experimental results, that the new active-region design significantly improves the carrier uniformity in the quantum wells and results in a 50% lasing threshold reduction and a 20°C improvement in the peak operating temperature of the devices. This thesis investigates the integration and fabrication technologies required to fabricate ultra-wideband WDM VCSEL arrays. The complete device design and fabrication process is presented along with actual device results from completed CWDM VCSEL arrays. Future recommendations for improvements are presented, along with a roadmap toward a final electrically-pumped single-chip source for CWDM applications.

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

Preface for DRIP X proceedings

NASA Astrophysics Data System (ADS)

Landesman (Chairman), Jean-Pierre; Montgomery (Co-Chairman), Paul C.

2004-07-01

This issue of the “European Physical Journal Applied Physics” contains the papers presented at the Tenth International Conference on Defects: Recognition, Imaging and Physics in Semiconductors (DRIP X), held in Batz-sur-Mer, France, from 29th September to 2nd October, 2003. The conference gathered 150 scientists from academic institutions and industry of 20 countries from around the world, showing the pertinence of the biennial series of DRIP conferences. A much appreciated aspect of DRIP X was the variety of the different backgrounds of the participants, leading to much fruitful exchange and stimulating discussion. Following the spirit of previous DRIP conferences, the main concern of DRIP X was the methodology and the physics of measurement procedures, together with specific developments in instrumentation, and their relationship with the structural, optical and electrical properties of semiconductor defects. The topics covered related to the different methods and techniques used for the recognition and imaging of defects in semiconductor materials (Si, III-V's including nitrides, SiC, IV-IV's, II-VI's, organic compounds, ...) and in semiconductor devices ranging from defects in the raw materials at the wafer level, through process-induced defects and defects that appear during operation (burn-in, aging tests, ...). One of the highlights of the social events of DRIP X was the awards ceremony as part of the celebrations for the Tenth meeting of DRIP. The founders of the DRIP series, Professor Jean-Pierre Fillard and Professor Tomoya Ogawa were both invited to be permanent members of the International Steering Committee and awarded with appropriately engraved trophies to mark the occasion. With help form Tomoya Ogawa, Jean-Pierre Fillard organized the first DRIP conference in 1985 in La Grande Motte, France. The amusing and thought provoking slide presentation by Jean-Pierre Fillard went a great way to remind us of the history of this conference series and to fill with enthusiasm the young and the not-so-young researchers alike to face up to the ever present challenges of defect analysis in semiconductors. We were reminded that with the large variety of imaging techniques available and the vast improvements in technology, there lies ahead tremendous potential for gaining a better understanding of defects in semiconductors by applying image processing techniques. DRIP X was arranged into 13 oral sessions, consisting of 12 invited talks and 59 contributed papers, and two poster sessions made up from 76 contributed papers. The Proceeding chapters reflect the oral sessions with the poster papers being added to the relevant sessions. The sessions covered the following topics: Sessions 1 and 2 were on nanostructures and near field probe techniques, with invited papers from F. Priolo on the luminescence properties of Si nanocrystals and L.K. Orlov on quantum wires in GaAs/GaInAs materials systems prepared by electrochemical etching. Session 3 was on defects in silicon, with an invited paper by Y. Mochizuki on the characterization of process induced defects in deep sub-micron transistors by electrically detected magnetic resonance and transmission electron microscopy. Session 4 was on electrical properties, with an invited paper by D. Roy on the electrical characteristics of advanced MOS structures with ultra-thin oxides. Sessions 5 and 6 were on defects in wide bandgap materials, with invited papers by S. Müller on the current status of the quality of SiC substrates and epitaxial layers, and by J.L Weyher on the characterization of defects in wide band gap semiconductors (mainly GaN) by defect-selective etching in combination with other standard methods (transmission electron microscopy, photo-luminescence, micro-Raman). Session 7 was on spectroscopic techniques, with an invited paper by V. Higgs on the use of photo-luminescence wafer mapping in the context of the production of Si or SiGe materials. Session 8 was on electron beam methods, with an invited paper by R. Balboni on strain mapping in deep sub-micron Si devices using convergent beam electron diffraction in STEM. Session 9 was a specific session on the issue of defect mapping over large area wafers, a new idea to the DRIP series, for investigating the possibilities of implementing different kinds of techniques having a potential for high lateral resolution over the very large areas required nowadays for semiconductor substrates and materials. This session was introduced by an invited talk by S. Ostapenko on defect mapping in multi-crystalline Si as well as SiC wafers. Session 10 on multi-techniques investigation, also new to the DRIP series, showed the importance of having access to a wide variety of techniques and managing such a “strategy” in an optimal way for solving certain defect problems present in today's semiconductor materials. The session was introduced by an invited talk by I. De Wolf, showing the importance of this approach to failure analysis in microelectronics. Session 11 was on X-ray based techniques, with an invited paper by U. Zeimer on the use of grazing incidence X-ray diffraction and X-ray spectroscopy (in the scanning or transmission electron microscope) for the study of epitaxial layers grown after lateral patterning at the nanometer scale of underlying layers. Session 12 was on defects in semiconductor lasers and other devices, with an invited paper by J. Jiménez on the use of spectroscopic techniques (cathodo-luminescence, micro-Raman...) for the assessment of defects in relation to aging behavior in high-power AlGaAs/GaAs laser diodes. Session 13, the final session, was on electronic properties through contactless characterization. We would like to thank all those involved in the local Organizing Committee, the International Steering Committee and the Scientific Committee for their hard work in helping with the organization of DRIP X, as well as all those who participated in the conference as delegates, speakers, invited speakers and chairpersons for contributing to such a successful conference. Thanks are also due to colleagues who served as referees for the papers. For its eleventh edition in 2005, DRIP XI will normally be organized by Professor Zhanguo Wang in Peking, China. Details of DRIP XI will be posted on the DRIP X website www.cnrs-imn.fr/dripx.

Analysis of Etched CdZnTe Substrates

NASA Astrophysics Data System (ADS)

Benson, J. D.; Bubulac, L. O.; Jaime-Vasquez, M.; Lennon, C. M.; Arias, J. M.; Smith, P. J.; Jacobs, R. N.; Markunas, J. K.; Almeida, L. A.; Stoltz, A.; Wijewarnasuriya, P. S.; Peterson, J.; Reddy, M.; Jones, K.; Johnson, S. M.; Lofgreen, D. D.

2016-09-01

State-of-the-art as-received (112)B CdZnTe substrates have been examined for surface impurity contamination and polishing residue. Two 4 cm × 4 cm and one 6 cm × 6 cm (112)B state-of-the-art as-received CdZnTe wafers were analyzed. A maximum surface impurity concentration of Al = 1.7 × 1015 atoms cm-2, Si = 3.7 × 1013 atoms cm-2, Cl = 3.12 × 1015 atoms cm-2, S = 1.7 × 1014 atoms cm-2, P = 1.1 × 1014 atoms cm-2, Fe = 1.0 × 1013 atoms cm-2, Br = 1.2 × 1014 atoms cm-2, and Cu = 4 × 1012 atoms cm-2 was observed on the as-received CdZnTe wafers. CdZnTe particulates and residual SiO2 polishing grit were observed on the surface of the as-received (112)B CdZnTe substrates. The polishing grit/CdZnTe particulate density on CdZnTe wafers was observed to vary across a 6 cm × 6 cm wafer from ˜4 × 107 cm-2 to 2.5 × 108 cm-2. The surface impurity and damage layer of the (112)B CdZnTe wafers dictate that a molecular beam epitaxy (MBE) preparation etch is required. The contamination for one 4 cm × 4 cm and one 6 cm × 6 cm CdZnTe wafer after a standard MBE Br:methanol preparation etch procedure was also analyzed. A maximum surface impurity concentration of Al = 2.4 × 1015 atoms cm-2, Si = 4.0 × 1013 atoms cm-2, Cl = 7.5 × 1013 atoms cm-2, S = 4.4 × 1013 atoms cm-2, P = 9.8 × 1013 atoms cm-2, Fe = 1.0 × 1013 atoms cm-2, Br = 2.9 × 1014 atoms cm-2, and Cu = 5.2 × 1012 atoms cm-2 was observed on the MBE preparation-etched CdZnTe wafers. The MBE preparation-etched surface contamination consists of Cd(Zn)Te particles/flakes. No residual SiO2 polishing grit was observed on the (112)B surface.

Semiconductor sensors

NASA Technical Reports Server (NTRS)

Gatos, Harry C. (Inventor); Lagowski, Jacek (Inventor)

1977-01-01

A semiconductor sensor adapted to detect with a high degree of sensitivity small magnitudes of a mechanical force, presence of traces of a gas or light. The sensor includes a high energy gap (i.e., .about. 1.0 electron volts) semiconductor wafer. Mechanical force is measured by employing a non-centrosymmetric material for the semiconductor. Distortion of the semiconductor by the force creates a contact potential difference (cpd) at the semiconductor surface, and this cpd is determined to give a measure of the force. When such a semiconductor is subjected to illumination with an energy less than the energy gap of the semiconductors, such illumination also creates a cpd at the surface. Detection of this cpd is employed to sense the illumination itself or, in a variation of the system, to detect a gas. When either a gas or light is to be detected and a crystal of a non-centrosymmetric material is employed, the presence of gas or light, in appropriate circumstances, results in a strain within the crystal which distorts the same and the distortion provides a mechanism for qualitative and quantitative evaluation of the gas or the light, as the case may be.

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

NASA Astrophysics Data System (ADS)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

Die singulation method

DOEpatents

Swiler, Thomas P.; Garcia, Ernest J.; Francis, Kathryn M.

2013-06-11

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Die singulation method

DOEpatents

Swiler, Thomas P [Albuquerque, NM; Garcia, Ernest J [Albuquerque, NM; Francis, Kathryn M [Rio Rancho, NM

2014-01-07

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with a HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Particle Deposition onto Enclosure Surfaces

DTIC Science & Technology

2009-08-20

Deposition on Semiconductor Wafers," Aerosol Sci. Technol. 6, 215 (1987). 3. S. E. Pratsinis, T. T. Kodas , M. P. Dudukovic, and S. K. Friedlander...29, 511 (1998). 11. T. T. Kodas , "Generation of Complex Metal Oxides by Aerosol Processes: Superconducting Ceramic Particles and Films," Adv. Mater

Automatic classification of blank substrate defects

NASA Astrophysics Data System (ADS)

Boettiger, Tom; Buck, Peter; Paninjath, Sankaranarayanan; Pereira, Mark; Ronald, Rob; Rost, Dan; Samir, Bhamidipati

2014-10-01

Mask preparation stages are crucial in mask manufacturing, since this mask is to later act as a template for considerable number of dies on wafer. Defects on the initial blank substrate, and subsequent cleaned and coated substrates, can have a profound impact on the usability of the finished mask. This emphasizes the need for early and accurate identification of blank substrate defects and the risk they pose to the patterned reticle. While Automatic Defect Classification (ADC) is a well-developed technology for inspection and analysis of defects on patterned wafers and masks in the semiconductors industry, ADC for mask blanks is still in the early stages of adoption and development. Calibre ADC is a powerful analysis tool for fast, accurate, consistent and automatic classification of defects on mask blanks. Accurate, automated classification of mask blanks leads to better usability of blanks by enabling defect avoidance technologies during mask writing. Detailed information on blank defects can help to select appropriate job-decks to be written on the mask by defect avoidance tools [1][4][5]. Smart algorithms separate critical defects from the potentially large number of non-critical defects or false defects detected at various stages during mask blank preparation. Mechanisms used by Calibre ADC to identify and characterize defects include defect location and size, signal polarity (dark, bright) in both transmitted and reflected review images, distinguishing defect signals from background noise in defect images. The Calibre ADC engine then uses a decision tree to translate this information into a defect classification code. Using this automated process improves classification accuracy, repeatability and speed, while avoiding the subjectivity of human judgment compared to the alternative of manual defect classification by trained personnel [2]. This paper focuses on the results from the evaluation of Automatic Defect Classification (ADC) product at MP Mask Technology Center (MPMask). The Calibre ADC tool was qualified on production mask blanks against the manual classification. The classification accuracy of ADC is greater than 95% for critical defects with an overall accuracy of 90%. The sensitivity to weak defect signals and locating the defect in the images is a challenge we are resolving. The performance of the tool has been demonstrated on multiple mask types and is ready for deployment in full volume mask manufacturing production flow. Implementation of Calibre ADC is estimated to reduce the misclassification of critical defects by 60-80%.

Image sensor with motion artifact supression and anti-blooming

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Wrigley, Chris (Inventor); Yang, Guang (Inventor); Yadid-Pecht, Orly (Inventor)

2006-01-01

An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node. The image sensor includes a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node. The imager can operate at high shutter speeds with simultaneous integration of pixels in the array. High quality images can be produced free from motion artifacts. High quantum efficiency, good blooming control, low dark current, low noise and low image lag can be obtained.

High speed CMOS imager with motion artifact supression and anti-blooming

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Wrigley, Chris (Inventor); Yang, Guang (Inventor); Yadid-Pecht, Orly (Inventor)

2001-01-01

An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node. The image sensor includes a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node. The imager can operate at high shutter speeds with simultaneous integration of pixels in the array. High quality images can be produced free from motion artifacts. High quantum efficiency, good blooming control, low dark current, low noise and low image lag can be obtained.

Process tool monitoring and matching using interferometry technique

NASA Astrophysics Data System (ADS)

Anberg, Doug; Owen, David M.; Mileham, Jeffrey; Lee, Byoung-Ho; Bouche, Eric

2016-03-01

The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today's manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield. In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.

Anisotropy-based crystalline oxide-on-semiconductor material

DOEpatents

McKee, Rodney Allen; Walker, Frederick Joseph

2000-01-01

A semiconductor structure and device for use in a semiconductor application utilizes a substrate of semiconductor-based material, such as silicon, and a thin film of a crystalline oxide whose unit cells are capable of exhibiting anisotropic behavior overlying the substrate surface. Within the structure, the unit cells of the crystalline oxide are exposed to an in-plane stain which influences the geometric shape of the unit cells and thereby arranges a directional-dependent quality of the unit cells in a predisposed orientation relative to the substrate. This predisposition of the directional-dependent quality of the unit cells enables the device to take beneficial advantage of characteristics of the structure during operation. For example, in the instance in which the crystalline oxide of the structure is a perovskite, a spinel or an oxide of similarly-related cubic structure, the structure can, within an appropriate semiconductor device, exhibit ferroelectric, piezoelectric, pyroelectric, electro-optic, ferromagnetic, antiferromagnetic, magneto-optic or large dielectric properties that synergistically couple to the underlying semiconductor substrate.

Method for making a monolithic integrated high-T.sub.c superconductor-semiconductor structure

NASA Technical Reports Server (NTRS)

Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Russell, Stephen D. (Inventor); Garcia, Graham A. (Inventor); Barfknecht, Andrew T. (Inventor); Clayton, Stanley R. (Inventor)

2000-01-01

A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Materials for Stretchable Electronics - Electronic Eyeballs, Brain Monitors and Other Applications

ScienceCinema

Rogers, John A. [University of Illinois, Urbana Champaign, Illinois, United States

2017-12-09

Electronic circuits that involve transistors and related components on thin plastic sheets or rubber slabs offer mechanical properties (e.g. bendability, stretchability) and other features (e.g. lightweight, rugged construction) which cannot be easily achieved with technologies that use rigid, fragile semiconductor wafer or glass substrates.  Device examples include personal or structural health monitors and electronic eye imagers, in which the electronics must conform to complex curvilinear shapes or flex/stretch during use.  Our recent work accomplishes these technology outcomes by use of single crystal inorganic nanomaterials in ‘wavy’ buckled configurations on elastomeric supports.  This talk will describe key fundamental materials and mechanics aspects of these approaches, as well as engineering features of their use in individual transistors, photodiodes and integrated circuits.  Cardiac and brain monitoring devices provide examples of application in biomedicine; hemispherical electronic eye cameras illustrate new capacities for bio-inspired device design.

Analytical determination of critical crack size in solar cells

NASA Technical Reports Server (NTRS)

Chen, C. P.

1988-01-01

Although solar cells usually have chips and cracks, no material specifications concerning the allowable crack size on solar cells are available for quality assurance and engineering design usage. Any material specifications that the cell manufacturers use were developed for cosmetic reasons that have no technical basis. Therefore, the Applied Solar Energy Corporation (ASEC) has sponsored a continuing program for the fracture mechanics evaluation of GaAs. Fracture mechanics concepts were utilized to develop an analytical model that can predict the critical crack size of solar cells. This model indicates that the edge cracks of a solar cell are more critical than its surface cracks. In addition, the model suggests that the material specifications on the allowable crack size used for Si solar cells should not be applied to GaAs solar cells. The analytical model was applied to Si and GaAs solar cells, but it would also be applicable to the semiconductor wafers of other materials, such as a GaAs thin film on a Ge substrate, using appropriate input data.

Enhanced capture rate for haze defects in production wafer inspection

NASA Astrophysics Data System (ADS)

Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

2010-03-01

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

Epitaxial thinning process

NASA Technical Reports Server (NTRS)

Siegel, C. M. (Inventor)

1984-01-01

A method is described for thinning an epitaxial layer of a wafer that is to be used in producing diodes having a specified breakdown voltage and which also facilitates the thinning process. Current is passed through the epitaxial layer, by connecting a current source between the substrate of the wafer and an electrolyte in which the wafer is immersed. When the wafer is initially immersed, the voltage across the wafer initially drops and then rises at a steep rate. When light is applied to the wafer the voltage drops, and when the light is interrupted the voltage rises again. These changes in voltage, each indicate the breakdown voltage of a Schottky diode that could be prepared from the wafer at that time. The epitaxial layer is thinned by continuing to apply current through the wafer while it is immersed and light is applied, to form an oxide film and when the oxide film is thick the wafer can then be cleaned of oxide and the testing and thinning continued. Uninterrupted thinning can be achieved by first forming an oxide film, and then using an electrolyte that dissolves the oxide about as fast as it is being formed, to limit the thickness of the oxide layer.

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Reconditioning of semiconductor substrates to remove photoresist during semiconductor device fabrication

DOEpatents

Farino, Anthony J.

2004-01-27

A method for reconditioning the surface of a semiconductor substrate to remove an unwanted (i.e. defective) layer of photoresist is disclosed. The method adapts a conventional automated spinner which is used to rotate the substrate at high speed while a stream of a first solvent (e.g. acetone) is used to dissolve the photoresist. A stream of a second solvent (e.g. methanol) is then used to clean the substrate at a lower speed, with the substrate being allowed to dry with continued rotation. The method of the present invention can be used within a photolithography track so that the substrates need never leave the track for reconditioning.

Sulfur passivation techniques for III-V wafer bonding

NASA Astrophysics Data System (ADS)

Jackson, Michael James

The use of direct wafer bonding in a multijunction III-V solar cell structure requires the formation of a low resistance bonded interface with minimal thermal treatment. A wafer bonded interface behaves as two independent surfaces in close proximity, hence a major source of resistance is Fermi level pinning common in III-V surfaces. This study demonstrates the use of sulfur passivation in III-V wafer bonding to reduce the energy barrier at the interface. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native oxide etch treatments. Through the addition of a sulfur desorption step in vacuum, the UV-S treatment achieves bondable surfaces free of particles contamination or surface roughening. X-ray photoelectron spectroscopy measurements of the sulfur treated GaAs surfaces find lower levels of oxide and the appearance of sulfide species. After 4 hrs of air exposure, the UV-S treated GaAs actually showed an increase in the amount of sulfide bonded to the semiconductor, resulting in less oxidation compared to the aqueous sulfide treatment. Large area bonding is achieved for sulfur treated GaAs / GaAs and InP / InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively, without large compressive forces. The electrical conductivity across a sulfur treated 400 °C bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 minutes) at elevated temperatures (50--600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the observed temperature dependence of zero bias conductance using a model for tunneling through a grain boundary reveals that the addition of sulfur at the interface lowered the interfacial energy barrier by 0.2 eV. The interface resistance for these sulfur-treated structures is less than 0.03 O·cm 2 at room temperature. These results emphasize that sulfur passivation techniques reduce interface states that otherwise limit the implementation of wafer bonding for high efficiency solar cells and other devices.

Wafer-Scale and Wrinkle-Free Epitaxial Growth of Single-Orientated Multilayer Hexagonal Boron Nitride on Sapphire.

PubMed

Jang, A-Rang; Hong, Seokmo; Hyun, Chohee; Yoon, Seong In; Kim, Gwangwoo; Jeong, Hu Young; Shin, Tae Joo; Park, Sung O; Wong, Kester; Kwak, Sang Kyu; Park, Noejung; Yu, Kwangnam; Choi, Eunjip; Mishchenko, Artem; Withers, Freddie; Novoselov, Kostya S; Lim, Hyunseob; Shin, Hyeon Suk

2016-05-11

Large-scale growth of high-quality hexagonal boron nitride has been a challenge in two-dimensional-material-based electronics. Herein, we present wafer-scale and wrinkle-free epitaxial growth of multilayer hexagonal boron nitride on a sapphire substrate by using high-temperature and low-pressure chemical vapor deposition. Microscopic and spectroscopic investigations and theoretical calculations reveal that synthesized hexagonal boron nitride has a single rotational orientation with AA' stacking order. A facile method for transferring hexagonal boron nitride onto other target substrates was developed, which provides the opportunity for using hexagonal boron nitride as a substrate in practical electronic circuits. A graphene field effect transistor fabricated on our hexagonal boron nitride sheets shows clear quantum oscillation and highly improved carrier mobility because the ultraflatness of the hexagonal boron nitride surface can reduce the substrate-induced degradation of the carrier mobility of two-dimensional materials.

Comparing the transient response of a resistive-type sensor with a thin film thermocouple during the post-exposure bake process

NASA Astrophysics Data System (ADS)

Kreider, Kenneth G.; DeWitt, David P.; Fowler, Joel B.; Proctor, James E.; Kimes, William A.; Ripple, Dean C.; Tsai, Benjamin K.

2004-04-01

Recent studies on dynamic temperature profiling and lithographic performance modeling of the post-exposure bake (PEB) process have demonstrated that the rate of heating and cooling may have an important influence on resist lithographic response. Measuring the transient surface temperature during the heating or cooling process with such accuracy can only be assured if the sensors embedded in or attached to the test wafer do not affect the temperature distribution in the bare wafer. In this paper we report on an experimental and analytical study to compare the transient response of embedded platinum resistance thermometer (PRT) sensors with surface-deposited, thin-film thermocouples (TFTC). The TFTCs on silicon wafers have been developed at NIST to measure wafer temperatures in other semiconductor thermal processes. Experiments are performed on a test bed built from a commercial, fab-qualified module with hot and chill plates using wafers that have been instrumented with calibrated type-E (NiCr/CuNi) TFTCs and commercial PRTs. Time constants were determined from an energy-balance analysis fitting the temperature-time derivative to the wafer temperature during the heating and cooling processes. The time constants for instrumented wafers ranged from 4.6 s to 5.1 s on heating for both the TFTC and PRT sensors, with an average difference less than 0.1 s between the TFTCs and PRTs and slightly greater differences on cooling.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y. Simon; Deb, Satyen K.

1990-01-01

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

Design and fabrication of 6.1-.ANG. family semiconductor devices using semi-insulating A1Sb substrate

DOEpatents

Sherohman, John W [Livermore, CA; Coombs, III, Arthur W.; Yee, Jick Hong [Livermore, CA; Wu, Kuang Jen J [Cupertino, CA

2007-05-29

For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-.ANG. family heterostructure devices.

Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate

DOEpatents

Mazur, Eric [Concord, MA; Shen, Mengyan [Arlington, MA

2008-10-28

The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate

DOEpatents

Mazur, Eric; Shen, Mengyan

2015-09-15

The present invention generally provides semiconductor substrates having submicronsized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate

DOEpatents

Mazur, Eric , Shen; Mengyan, [Belmont, MA

2011-02-08

The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

A Fully Integrated Quartz MEMS VHF TCXO.

PubMed

Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

2018-06-01

We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

Laser Vacuum Furnace for Zone Refining

NASA Technical Reports Server (NTRS)

Griner, D. B.; Zurburg, F. W.; Penn, W. M.

1986-01-01

Laser beam scanned to produce moving melt zone. Experimental laser vacuum furnace scans crystalline wafer with high-power CO2-laser beam to generate precise melt zone with precise control of temperature gradients around zone. Intended for zone refining of silicon or other semiconductors in low gravity, apparatus used in normal gravity.

Graphene-on-semiconductor substrates for analog electronics

DOEpatents

Lagally, Max G.; Cavallo, Francesca; Rojas-Delgado, Richard

2016-04-26

Electrically conductive material structures, analog electronic devices incorporating the structures and methods for making the structures are provided. The structures include a layer of graphene on a semiconductor substrate. The graphene layer and the substrate are separated by an interfacial region that promotes transfer of charge carriers from the surface of the substrate to the graphene.

Silicon Carbide High-Temperature Power Rectifiers Fabricated and Characterized

NASA Technical Reports Server (NTRS)

1996-01-01

The High Temperature Integrated Electronics and Sensors (HTIES) team at the NASA Lewis Research Center is developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. Silicon carbide's demonstrated ability to function under extreme high-temperature, high power, and/or high-radiation conditions will enable significant improvements to a far ranging variety of applications and systems. These improvements range from improved high-voltage switching for energy savings in public electric power distribution and electric vehicles, to more powerful microwave electronics for radar and cellular communications, to sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines. In the case of jet engines, uncooled operation of 300 to 600 C SiC power actuator electronics mounted in key high-temperature areas would greatly enhance system performance and reliability. Because silicon cannot function at these elevated temperatures, the semiconductor device circuit components must be made of SiC. Lewis' HTIES group recently fabricated and characterized high-temperature SiC rectifier diodes whose record-breaking characteristics represent significant progress toward the realization of advanced high-temperature actuator control circuits. The first figure illustrates the 600 C probe-testing of a Lewis SiC pn-junction rectifier diode sitting on top of a glowing red-hot heating element. The second figure shows the current-versus voltage rectifying characteristics recorded at 600 C. At this high temperature, the diodes were able to "turn-on" to conduct 4 A of current when forward biased, and yet block the flow of current ($quot;turn-off") when reverse biases as high as 150 V were applied. This device represents a new record for semiconductor device operation, in that no previous semiconductor electronic device has ever simultaneously demonstrated 600 C functionality, and 4-A turn-on and 150-V rectification. The high operating current was achieved despite severe device size limitations imposed by present-day SiC wafer defect densities. Further substantial increases in device performance can be expected when SiC wafer defect densities decrease as SiC wafer production technology matures.

Guided growth of horizontal GaN nanowires on quartz and their transfer to other substrates.

PubMed

Goren-Ruck, Lior; Tsivion, David; Schvartzman, Mark; Popovitz-Biro, Ronit; Joselevich, Ernesto

2014-03-25

The guided growth of horizontal nanowires has so far been demonstrated on a limited number of substrates. In most cases, the nanowires are covalently bonded to the substrate where they grow and cannot be transferred to other substrates. Here we demonstrate the guided growth of well-aligned horizontal GaN nanowires on quartz and their subsequent transfer to silicon wafers by selective etching of the quartz while maintaining their alignment. The guided growth was observed on different planes of quartz with varying degrees of alignment. We characterized the crystallographic orientations of the nanowires and proposed a new mechanism of "dynamic graphoepitaxy" for their guided growth on quartz. The transfer of the guided nanowires enabled the fabrication of back-gated field-effect transistors from aligned nanowire arrays on oxidized silicon wafers and the production of crossbar arrays. The guided growth of transferrable nanowires opens up the possibility of massively parallel integration of nanowires into functional systems on virtually any desired substrate.

Multivariable control of a rapid thermal processor using ultrasonic sensors

NASA Astrophysics Data System (ADS)

Dankoski, Paul C. P.

The semiconductor manufacturing industry faces the need for tighter control of thermal budget and process variations as circuit feature sizes decrease. Strategies to meet this need include supervisory control, run-to-run control, and real-time feedback control. Typically, the level of control chosen depends upon the actuation and sensing available. Rapid Thermal Processing (RTP) is one step of the manufacturing cycle requiring precise temperature control and hence real-time feedback control. At the outset of this research, the primary ingredient lacking from in-situ RTP temperature control was a suitable sensor. This research looks at an alternative to the traditional approach of pyrometry, which is limited by the unknown and possibly time-varying wafer emissivity. The technique is based upon the temperature dependence of the propagation time of an acoustic wave in the wafer. The aim of this thesis is to evaluate the ultrasonic sensors as a potentially viable sensor for control in RTP. To do this, an experimental implementation was developed at the Center for Integrated Systems. Because of the difficulty in applying a known temperature standard in an RTP environment, calibration to absolute temperature is nontrivial. Given reference propagation delays, multivariable model-based feedback control is applied to the system. The modelling and implementation details are described. The control techniques have been applied to a number of research processes including rapid thermal annealing and rapid thermal crystallization of thin silicon films on quartz/glass substrates.

SEMICONDUCTOR TECHNOLOGY: GaAs surface wet cleaning by a novel treatment in revolving ultrasonic atomization solution

NASA Astrophysics Data System (ADS)

Zaijin, Li; Liming, Hu; Ye, Wang; Ye, Yang; Hangyu, Peng; Jinlong, Zhang; Li, Qin; Yun, Liu; Lijun, Wang

2010-03-01

A novel process for the wet cleaning of GaAs surface is presented. It is designed for technological simplicity and minimum damage generated within the GaAs surface. It combines GaAs cleaning with three conditions consisting of (1) removal of thermodynamically unstable species and (2) surface oxide layers must be completely removed after thermal cleaning, and (3) a smooth surface must be provided. Revolving ultrasonic atomization technology is adopted in the cleaning process. At first impurity removal is achieved by organic solvents; second NH4OH:H2O2:H2O = 1:1:10 solution and HCl: H2O2:H2O = 1:1:20 solution in succession to etch a very thin GaAs layer, the goal of the step is removing metallic contaminants and forming a very thin oxidation layer on the GaAs wafer surface; NH4OH:H2O = 1:5 solution is used as the removed oxide layers in the end. The effectiveness of the process is demonstrated by the operation of the GaAs wafer. Characterization of the oxide composition was carried out by X-ray photoelectron spectroscopy. Metal-contamination and surface morphology was observed by a total reflection X-ray fluorescence spectroscopy and atomic force microscope. The research results show that the cleaned surface is without contamination or metal contamination. Also, the GaAs substrates surface is very smooth for epitaxial growth using the rotary ultrasonic atomization technology.

Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor)

2011-01-01

Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.

Graphene and carbon nanotubes: synthesis, characterization and applications for beyond silicon electronics

NASA Astrophysics Data System (ADS)

Gomez de Arco, Lewis Mortimer

Graphene and carbon nanotubes have outstanding electrical and thermal conductivity. These characteristics make them exciting materials with high potential to replace silicon and surpass its performance in the next generation of semiconductors devices, such devices ought to be considerably smaller and faster than the ones used in present technology. Despite of the excellent electrical and thermal conduction properties of graphene and carbon nanotubes, the advance of nanoelectronics based on them has been hampered due to fundamental limitations of the current synthesis and integration technologies of these carbon nanomaterials. Therefore, there is a strong need to do research at fundamental and applicative levels to help find the roadmap that these materials need to follow, in order to become a real alternative for silicon in future technologies. This dissertation present our approach to overcome some of the most critical problems that hinder the implementation of graphene and carbon nanotubes as important components in real-life macro and nanoelectronic devices. Towards this end, we systematically studied synthesis methods for scalable, high quality graphene and evaluated our large-scale synthesized graphene as transparent electrodes in functional energy conversion devices. In addition, we explored scalable methods to obtain carbon nanotube field-effect transistors with only semiconductor nanotube channels and studied the substrate influence on the structure and metal to semiconductor ratio of aligned nanotubes. Although we have successfully tackled some of the most important challenges of the above-mentioned one- and two-dimensional carbon nanostructures, more remains to be done to integrate them as functional components in electronic devices to reach the goal of transferring them from the laboratory to the manufacturing industry, and ultimately to the society. In chapter 1, a general introduction to carbon nanomaterials is presented, followed by a more focused discussion on the structure and properties of graphene and carbon nanotubes. Chapter 2, presents the development of a chemical vapor deposition method for scalable graphene synthesis and the evaluation of its electrical properties as the active channel in field effect transistor and as a transparent conductor. Chapter 3 presents further work on graphene synthesis on single crystal nickel and the influence of the substrate atomic arrangement on the synthesized graphene. Chapter 4 presents the implementation of the highly scalable graphene synthesized by CVD as the transparent electrode in flexible organic photovoltaic cells. Chapter 5 evaluates the influence of substrate/nanotube interactions during align nanotube growth on the Raman signature of the resulting aligned nanotubes, nanotube structure and metal to semiconductor ratio. Chapter 6 presents our findings on a scalable method that can be used at wafer scale to achieve metal to semiconductor conversion of carbon nanotubes by light irradiation and its application to achieve semiconducting CNTFETs. Finally, in chapter 7, future research directions in related areas of science and technology are proposed.

Direct wafer bonding of highly conductive GaSb/GaInAs and GaSb/GaInP heterojunctions prepared by argon-beam surface activation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Predan, Felix, E-mail: felix.predan@ise.fraunhofer.de; Reinwand, Dirk; Cariou, Romain

The authors present a low-temperature wafer bonding process for the formation of electrically conductive n-GaSb/n-Ga{sub 0.79}In{sub 0.21}As and n-GaSb/n-Ga{sub 0.32}In{sub 0.68}P heterojunctions. The surfaces are deoxidized by sputter-etching with an argon-beam and bonded in ultrahigh vacuum. The sputtering behavior was investigated for each material, revealing a distinct selective sputtering characteristic for Ga{sub 0.32}In{sub 0.68}P. According to these findings, the settings for the bonding process were chosen. The mechanical and electrical properties of the wafer bonds were studied. Fully bonded 2 in. wafer pairs were found for both material combinations exhibiting high bond energies, which are comparable to the binding energiesmore » in the semiconductors. Furthermore, bond resistances below 5 mΩ cm{sup 2} could be reached, which are in the range of the lowest resistances that have been reported for wafer bonded heterojunctions. This speaks, together with the high bond energies, for a high amount of covalent bonds at the interfaces. These promising bond characteristics make the integration of antimonides with arsenides or phosphides by wafer bonding attractive for various optoelectronic applications such as multijunction solar cells.« less

Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby

DOEpatents

Atwater, Jr., Harry A.; Zahler, James M.

2006-11-28

Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure good thermal contact, mechanical strength, and to enable the formation of an ohmic contact between the Si substrate and Ge layers. To accomplish this type of bond, hydrophobic wafer bonding is used, because as the invention demonstrates the hydrogen-surface-terminating species that facilitate van der Waals bonding evolves at temperatures above 600.degree. C. into covalent bonding in hydrophobically bound Ge/Si layer transferred systems.

SEMICONDUCTOR TECHNOLOGY: Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

NASA Astrophysics Data System (ADS)

Yuhan, Cao; Le, Luo

2009-08-01

A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.

Near single-crystalline, high-carrier-mobility silicon thin film on a polycrystalline/amorphous substrate

DOEpatents

Findikoglu, Alp T [Los Alamos, NM; Jia, Quanxi [Los Alamos, NM; Arendt, Paul N [Los Alamos, NM; Matias, Vladimir [Santa Fe, NM; Choi, Woong [Los Alamos, NM

2009-10-27

A template article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material; is provided, together with a semiconductor article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material, and, a top-layer of semiconductor material upon the buffer material layer.

Fabrication of terahertz metamaterials using electrohydrodynamic jet printing for sensitive detection of yeast

NASA Astrophysics Data System (ADS)

Pradhipta Tenggara, Ayodya; Park, S. J.; Teguh Yudistira, Hadi; Ahn, Y. H.; Byun, Doyoung

2017-03-01

We demonstrated the fabrication of terahertz metamaterial sensor for the accurate and on-site detection of yeast using electrohydrodynamic jet printing, which is inexpensive, simple, and environmentally friendly. The very small sized pattern up to 5 µm-width of electrical split ring resonator unit structures could be printed on a large area on both a rigid substrate and flexible substrate, i.e. silicon wafer and polyimide film using the drop on demand technique to eject liquid ink containing silver nanoparticles. Experimental characterization and simulation were performed to study their performances in detecting yeast of different weights. It was shown that the metamaterial sensor fabricated on a flexible polyimide film had higher sensitivity by more than six times than the metamaterial sensor fabricated on a silicon wafer, due to the low refractive index of the PI substrate and due to the extremely thin substrate thickness which lowers the effective index further. The resonance frequency shift saturated when the yeast weights were 145 µg and 215 µg for metamaterial structures with gap size 6.5 µm fabricated on the silicon substrate and on the polyimide substrate, respectively.

A novel setup for wafer curvature measurement at very high heating rates.

PubMed

Islam, T; Zechner, J; Bernardoni, M; Nelhiebel, M; Pippan, R

2017-02-01

The curvature evolution of a thin film layer stack containing a top Al layer is measured during temperature cycles with very high heating rates. The temperature cycles are generated by means of programmable electrical power pulses applied to miniaturized polysilicon heater systems embedded inside a semiconductor chip and the curvature is measured by a fast wafer curvature measurement setup. Fast temperature cycles with heating duration of 100 ms are created to heat the specimen up to 270 °C providing an average heating rate of 2500 K/s. As a second approach, curvature measurement utilizing laser scanning Doppler vibrometry is also demonstrated which verifies the results obtained from the fast wafer curvature measurement setup. Film stresses calculated from the measured curvature values compare well to literature results, indicating that the new method can be used to measure curvature during fast temperature cycling.

On-line photolithography modeling using spectrophotometry and Prolith/2

NASA Astrophysics Data System (ADS)

Engstrom, Herbert L.; Beacham, Jeanne E.

1994-05-01

Spectrophotometry has been applied to optimizing photolithography processes in semiconductor manufacturing. For many years thin film measurement systems have been used in manufacturing for controlling film deposition processes. The combination of film thickness mapping with photolithography modeling has expanded the applications of this technology. Experimental measurements of dose-to-clear, the minimum light exposure dose required to fully develop a photoresist, are described. It is shown how dose-to-clear and photoresist contrast may be determined rapidly and conveniently from measurements of a dose exposure matrix on a monitor wafer. Such experimental measurements may underestimate the dose-to- clear because of thickness variations of the photoresist and underlying layers on the product wafer. Online modeling of the photolithographic process together with film thickness maps of the entire wafer can overcome this problem. Such modeling also provides maps of dose-to- clear and resist linewidth that can be used to estimate and optimize yield.

High-efficiency neutron detectors and methods of making same

DOEpatents

McGregor, Douglas S.; Klann, Raymond

2007-01-16

Neutron detectors, advanced detector process techniques and advanced compound film designs have greatly increased neutron-detection efficiency. One embodiment of the detectors utilizes a semiconductor wafer with a matrix of spaced cavities filled with one or more types of neutron reactive material such as ¹⁰B or ⁶LiF. The cavities are etched into both the front and back surfaces of the device such that the cavities from one side surround the cavities from the other side. The cavities may be etched via holes or etched slots or trenches. In another embodiment, the cavities are different-sized and the smaller cavities extend into the wafer from the lower surfaces of the larger cavities. In a third embodiment, multiple layers of different neutron-responsive material are formed on one or more sides of the wafer. The new devices operate at room temperature, are compact, rugged, and reliable in design.

Methods and devices for fabricating and assembling printable semiconductor elements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Methods and devices for fabricating and assembling printable semiconductor elements

DOEpatents

Nuzzo, Ralph G; Rogers, John A; Menard, Etienne; Lee, Keon Jae; Khang, Dahl-Young; Sun, Yugang; Meitl, Matthew; Zhu, Zhengtao

2014-03-04

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

In-cell overlay metrology by using optical metrology tool

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Hong, Minhyung; Kim, Seungyoung; Lee, Jieun; Lee, DongYoung; Oh, Eungryong; Choi, Ahlin; Park, Hyowon; Liang, Waley; Choi, DongSub; Kim, Nakyoon; Lee, Jeongpyo; Pandev, Stilian; Jeon, Sanghuck; Robinson, John C.

2018-03-01

Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced scheme includes an overlay feedback loop based on after litho optical imaging overlay metrology on scribeline targets. The after litho control loop typically involves high frequency sampling: every lot or nearly every lot. An after etch overlay metrology step is often included, at a lower sampling frequency, in order to characterize and compensate for bias. The after etch metrology step often involves CD-SEM metrology, in this case in-cell and ondevice. This work explores an alternative approach using spectroscopic ellipsometry (SE) metrology and a machine learning analysis technique. Advanced 1x nm DRAM wafers were prepared, including both nominal (POR) wafers with mean overlay offsets, as well as DOE wafers with intentional across wafer overlay modulation. After litho metrology was measured using optical imaging metrology, as well as after etch metrology using both SE and CD-SEM for comparison. We investigate 2 types of machine learning techniques with SE data: model-less and model-based, showing excellent performance for after etch in-cell on-device overlay metrology.

SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

NASA Astrophysics Data System (ADS)

Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

2010-02-01

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

Metrology needs for the semiconductor industry over the next decade

NASA Astrophysics Data System (ADS)

Melliar-Smith, Mark; Diebold, Alain C.

1998-11-01

Metrology will continue to be a key enabler for the development and manufacture of future generations of integrated circuits. During 1997, the Semiconductor Industry Association renewed the National Technology Roadmap for Semiconductors (NTRS) through the 50 nm technology generation and for the first time included a Metrology Roadmap (1). Meeting the needs described in the Metrology Roadmap will be both a technological and financial challenge. In an ideal world, metrology capability would be available at the start of process and tool development, and silicon suppliers would have 450 mm wafer capable metrology tools in time for development of that wafer size. Unfortunately, a majority of the metrology suppliers are small companies that typically can't afford the additional two to three year wait for return on R&D investment. Therefore, the success of the semiconductor industry demands that we expand cooperation between NIST, SEMATECH, the National Labs, SRC, and the entire community. In this paper, we will discuss several critical metrology topics including the role of sensor-based process control, in-line microscopy, focused measurements for transistor and interconnect fabrication, and development needs. Improvements in in-line microscopy must extend existing critical dimension measurements up to 100 nm generations and new methods may be required for sub 100 nm generations. Through development, existing metrology dielectric thickness and dopant dose and junction methods can be extended to 100 nm, but new and possibly in-situ methods are needed beyond 100 nm. Interconnect process control will undergo change before 100 nm due to the introduction of copper metallization, low dielectric constant interlevel dielectrics, and Damascene process flows.

Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate

DOEpatents

Mazur, Eric; Shen, Mengyan

2013-12-03

The present invention generally provides a semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Visible wavelength surface-enhanced Raman spectroscopy from In-InP nanopillars for biomolecule detection

NASA Astrophysics Data System (ADS)

Murdoch, B. J.; Portoles, J. F.; Tardio, S.; Barlow, A. J.; Fletcher, I. W.; Cumpson, P. J.

2016-12-01

Visible wavelength surface-enhanced Raman spectroscopy (SERS) has been observed from bovine serum albumin (BSA) using In-InP nanopillars synthesised by Ar gas cluster ion beam sputtering of InP wafers. InP provides a high local refractive index for plasmonic In structures, which increases the wavelength of the In surface plasmon resonance. The Raman scattering signal was determined to be up to 285 times higher for BSA deposited onto In-InP nanopillars when compared with Si wafer substrates. These substrates demonstrate the label-free detection of biomolecules by visible wavelength SERS, without the use of noble metal particles.

Large-roll growth of 25-inch hexagonal BN monolayer film for self-release buffer layer of free-standing GaN wafer

NASA Astrophysics Data System (ADS)

Wu, Chenping; Soomro, Abdul Majid; Sun, Feipeng; Wang, Huachun; Huang, Youyang; Wu, Jiejun; Liu, Chuan; Yang, Xiaodong; Gao, Na; Chen, Xiaohong; Kang, Junyong; Cai, Duanjun

2016-10-01

Hexagonal boron nitride (h-BN) is known as promising 2D material with a wide band-gap (~6 eV). However, the growth size of h-BN film is strongly limited by the size of reaction chamber. Here, we demonstrate the large-roll synthesis of monolayer and controllable sub-monolayer h-BN film on wound Cu foil by low pressure chemical vapor deposition (LPCVD) method. By winding the Cu foil substrate into mainspring shape supported by a multi-prong quartz fork, the reactor size limit could be overcome by extending the substrate area to a continuous 2D curl of plane inward. An extremely large-size monolayer h-BN film has been achieved over 25 inches in a 1.2” tube. The optical band gap of h-BN monolayer was determined to be 6.0 eV. The h-BN film was uniformly transferred onto 2” GaN or 4” Si wafer surfaces as a release buffer layer. By HVPE method, overgrowth of thick GaN wafer over 200 μm has been achieved free of residual strain, which could provide high quality homo-epitaxial substrate.

Plasmon absorption modulator systems and methods

DOEpatents

Kekatpure, Rohan Deodatta; Davids, Paul

2014-07-15

Plasmon absorption modulator systems and methods are disclosed. A plasmon absorption modulator system includes a semiconductor substrate, a plurality of quantum well layers stacked on a top surface of the semiconductor substrate, and a metal layer formed on a top surface of the stack of quantum well layers. A method for modulating plasmonic current includes enabling propagation of the plasmonic current along a metal layer, and applying a voltage across the stack of quantum well layers to cause absorption of a portion of energy of the plasmonic current by the stack of quantum well layers. A metamaterial switching system includes a semiconductor substrate, a plurality of quantum well layers stacked on a top surface of the semiconductor substrate, and at least one metamaterial structure formed on a top surface of the stack of quantum well layers.

MOCVD process technology for affordable, high-yield, high-performance MESFET structures. Phase 3: MIMIC

NASA Astrophysics Data System (ADS)

1993-01-01

Under the MIMIC Program, Spire has pursued improvements in the manufacturing of low cost, high quality gallium arsenide MOCVD wafers for advanced MIMIC FET applications. As a demonstration of such improvements, Spire was tasked to supply MOCVD wafers for comparison to MBE wafers in the fabrication of millimeter and microwave integrated circuits. In this, the final technical report for Spire's two-year MIMIC contract, we report the results of our work. The main objectives of Spire's MIMIC Phase 3 Program, as outlined in the Statement of Work, were as follows: Optimize the MOCVD growth conditions for the best possible electrical and morphological gallium arsenide. Optimization should include substrate and source qualification as well as determination of the optimum reactor growth conditions; Perform all work on 75 millimeter diameter wafers, using a reactor capable of at least three wafers per run; and Evaluate epitaxial layers using electrical, optical, and morphological tests to obtain thickness, carrier concentration, and mobility data across wafers.

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

NASA Astrophysics Data System (ADS)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

Cameras for semiconductor process control

NASA Technical Reports Server (NTRS)

Porter, W. A.; Parker, D. L.

1977-01-01

The application of X-ray topography to semiconductor process control is described, considering the novel features of the high speed camera and the difficulties associated with this technique. The most significant results on the effects of material defects on device performance are presented, including results obtained using wafers processed entirely within this institute. Defects were identified using the X-ray camera and correlations made with probe data. Also included are temperature dependent effects of material defects. Recent applications and improvements of X-ray topographs of silicon-on-sapphire and gallium arsenide are presented with a description of a real time TV system prototype and of the most recent vacuum chuck design. Discussion is included of our promotion of the use of the camera by various semiconductor manufacturers.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

Virtual overlay metrology for fault detection supported with integrated metrology and machine learning

NASA Astrophysics Data System (ADS)

Lee, Hong-Goo; Schmitt-Weaver, Emil; Kim, Min-Suk; Han, Sang-Jun; Kim, Myoung-Soo; Kwon, Won-Taik; Park, Sung-Ki; Ryan, Kevin; Theeuwes, Thomas; Sun, Kyu-Tae; Lim, Young-Wan; Slotboom, Daan; Kubis, Michael; Staecker, Jens

2015-03-01

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn't be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

NASA Astrophysics Data System (ADS)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

NASA Technical Reports Server (NTRS)

Jhabvala, Murzy; Jhabvala, Christine A.; Ewin, Audrey J.; Hess, Larry A.; Hartmann, Thomas M.; La, Anh T.

2012-01-01

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Enhanced light output from the nano-patterned InP semiconductor substrate through the nanoporous alumina mask.

PubMed

Jung, Mi; Kim, Jae Hun; Lee, Seok; Jang, Byung Jin; Lee, Woo Young; Oh, Yoo-Mi; Park, Sun-Woo; Woo, Deokha

2012-07-01

A significant enhancement in the light output from nano-patterned InP substrate covered with a nanoporous alumina mask was observed. A uniform nanohole array on an InP semiconductor substrate was fabricated by inductively coupled plasma reactive ion etching (ICP-RIE), using the nanoporous alumina mask as a shadow mask. The light output property of the semiconductor substrate was investigated via photoluminescence (PL) intensity measurement. The InP substrate with a nanohole array showed a more enhanced PL intensity compared with the raw InP substrate without a nanohole structure. After ICP-RIE etching, the light output from the nanoporous InP substrate covered with a nanoporous alumina mask showed fourfold enhanced PL intensity compared with the raw InP substrate. These results can be used as a prospective method for increasing the light output efficiency of optoelectronic devices.

SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

NASA Astrophysics Data System (ADS)

Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

2010-10-01

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

Thin film photovoltaic device with multilayer substrate

DOEpatents

Catalano, Anthony W.; Bhushan, Manjul

1984-01-01

A thin film photovoltaic device which utilizes at least one compound semiconductor layer chosen from Groups IIB and VA of the Periodic Table is formed on a multilayer substrate The substrate includes a lowermost support layer on which all of the other layers of the device are formed. Additionally, an uppermost carbide or silicon layer is adjacent to the semiconductor layer. Below the carbide or silicon layer is a metal layer of high conductivity and expansion coefficient equal to or slightly greater than that of the semiconductor layer.

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

78 FR 23472 - Amendments to Existing Validated End-User Authorizations: CSMC Technologies Corporation in the...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-19

... of Wuxi CR Semiconductor Wafers & Chips Co., Ltd. and CSMC Technologies Fab 1 Co., Ltd., which is... Validated End-User: CSMC Technologies Corporation. Eligible Destinations: CSMC Technologies Fab 1 Co., Ltd., 14 Liangxi Road, Wuxi, Jiangsu 214061, China. CSMC Technologies Fab 2 Co., Ltd., 8 Xinzhou Rd., Wuxi...

Laser pattern generator challenges in airborne molecular contamination protection

NASA Astrophysics Data System (ADS)

Ekberg, Mats; Skotte, Per-Uno; Utterback, Tomas; Paul, Swaraj; Kishkovich, Oleg P.; Hudzik, James S.

2003-08-01

The introduction of photomask laser pattern generators presents new challenges to system designers and manufacturers. One of the laser pattern generator's environmental operating challenges is Airborne Molecular Contamination (AMC), which affects both chemically amplified resists (CAResist) and laser optics. Similar challenges in CAResist protection have already been addressed in semiconductor wafer lithography with reasonable solutions and experience gained by all those involved. However, photomask and photomask equipment manufacturers have not previously had a comparable experience, and some photomask AMC issues differ from those seen in semiconductor wafer lithography. Culminating years of AMC experience, the authors discuss specific requirements of Photomask AMC. Air sampling and material of construction analysis were performed to understand these particular AMC challenges and used to develop an appropriate filtration specification for different classes of contaminates. The authors portray the importance of cooperation between tool designers and AMC experts early in the design stage to assure goal attainment to maximize both process stability and machine productivity in advanced mask making. In conclusion, the authors provide valuable recommendations to both laser tool users and other equipment manufacturers.

Integrated Arrays on Silicon at Terahertz Frequencies

NASA Technical Reports Server (NTRS)

Chattopadhayay, Goutam; Lee, Choonsup; Jung, Cecil; Lin, Robert; Peralta, Alessandro; Mehdi, Imran; Llombert, Nuria; Thomas, Bertrand

2011-01-01

In this paper we explore various receiver font-end and antenna architecture for use in integrated arrays at terahertz frequencies. Development of wafer-level integrated terahertz receiver front-end by using advanced semiconductor fabrication technologies and use of novel integrated antennas with silicon micromachining are reported. We report novel stacking of micromachined silicon wafers which allows for the 3-dimensional integration of various terahertz receiver components in extremely small packages which easily leads to the development of 2- dimensioanl multi-pixel receiver front-ends in the terahertz frequency range. We also report an integrated micro-lens antenna that goes with the silicon micro-machined front-end. The micro-lens antenna is fed by a waveguide that excites a silicon lens antenna through a leaky-wave or electromagnetic band gap (EBG) resonant cavity. We utilized advanced semiconductor nanofabrication techniques to design, fabricate, and demonstrate a super-compact, low-mass submillimeter-wave heterodyne frontend. When the micro-lens antenna is integrated with the receiver front-end we will be able to assemble integrated heterodyne array receivers for various applications such as multi-pixel high resolution spectrometer and imaging radar at terahertz frequencies.

Future Development of Dense Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.

2001-01-01

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Prolonged menstrual cycles in female workers exposed to ethylene glycol ethers in the semiconductor manufacturing industry.

PubMed

Hsieh, G-Y; Wang, J-D; Cheng, T-J; Chen, P-C

2005-08-01

It has been shown that female workers exposed to ethylene glycol ethers (EGEs) in the semiconductor industry have higher risks of spontaneous abortion, subfertility, and menstrual disturbances, and prolonged waiting time to pregnancy. To examine whether EGEs or other chemicals are associated with long menstrual cycles in female workers in the semiconductor manufacturing industry. Cross-sectional questionnaire survey during the annual health examination at a wafer manufacturing company in Taiwan in 1997. A three tiered exposure-assessment strategy was used to analyse the risk. A short menstrual cycle was defined to be a cycle less than 24 days and a long cycle to be more than 35 days. There were 606 valid questionnaires from 473 workers in fabrication jobs and 133 in non-fabrication areas. Long menstrual cycles were associated with workers in fabrication areas compared to those in non-fabrication areas. Using workers in non-fabrication areas as referents, workers in photolithography and diffusion areas had higher risks for long menstrual cycles. Workers exposed to EGEs and isopropanol, and hydrofluoric acid, isopropanol, and phosphorous compounds also showed increased risks of a long menstrual cycle. Exposure to multiple chemicals, including EGEs in photolithography, might be associated with long menstrual cycles, and may play an important role in a prolonged time to pregnancy in the wafer manufacturing industry; however, the prevalence in the design, possible exposure misclassification, and chance should be considered.

Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1993-01-01

The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

Electron-Beam Deposition of Superconducting Molybdenum Thin Films for the Development of Mo/Au TES X-Ray Microcalorimeter

NASA Technical Reports Server (NTRS)

Finkbeiner, Fred Michael; Adams, Joseph S.; Bandler, Simon R.; Betancour-Martinez, Gabriele L.; Brown, Ari David; Chang, Meng-Ping; Chervenak, James A.; Chiao, Meng P.; Datesman, Aaron; Eckart, Megan E.;

Photoresist substrate having robust adhesion

DOEpatents

Dentinger, Paul M [Sunol, CA

2005-07-26

A substrate material for LIGA applications w hose general composition is Ti/Cu/Ti/SiO.sub.2. The SiO.sub.2 is preferably applied to the Ti/Cu/Ti wafer as a sputtered coating, typically about 100 nm thick. This substrate composition provides improved adhesion for epoxy-based photoresist materials, and particularly the photoresist material SU-8.

Gamma ray detector modules

NASA Technical Reports Server (NTRS)

Capote, M. Albert (Inventor); Lenos, Howard A. (Inventor)

2009-01-01

A radiation detector assembly has a semiconductor detector array substrate of CdZnTe or CdTe, having a plurality of detector cell pads on a first surface thereof, the pads having a contact metallization and a solder barrier metallization. An interposer card has planar dimensions no larger than planar dimensions of the semiconductor detector array substrate, a plurality of interconnect pads on a first surface thereof, at least one readout semiconductor chip and at least one connector on a second surface thereof, each having planar dimensions no larger than the planar dimensions of the interposer card. Solder columns extend from contacts on the interposer first surface to the plurality of pads on the semiconductor detector array substrate first surface, the solder columns having at least one solder having a melting point or liquidus less than 120 degrees C. An encapsulant is disposed between the interposer circuit card first surface and the semiconductor detector array substrate first surface, encapsulating the solder columns, the encapsulant curing at a temperature no greater than 120 degrees C.

Real time quantitative imaging for semiconductor crystal growth, control and characterization

NASA Technical Reports Server (NTRS)

Wargo, Michael J.

1991-01-01

A quantitative real time image processing system has been developed which can be software-reconfigured for semiconductor processing and characterization tasks. In thermal imager mode, 2D temperature distributions of semiconductor melt surfaces (900-1600 C) can be obtained with temperature and spatial resolutions better than 0.5 C and 0.5 mm, respectively, as demonstrated by analysis of melt surface thermal distributions. Temporal and spatial image processing techniques and multitasking computational capabilities convert such thermal imaging into a multimode sensor for crystal growth control. A second configuration of the image processing engine in conjunction with bright and dark field transmission optics is used to nonintrusively determine the microdistribution of free charge carriers and submicron sized crystalline defects in semiconductors. The IR absorption characteristics of wafers are determined with 10-micron spatial resolution and, after calibration, are converted into charge carrier density.

Mask characterization for critical dimension uniformity budget breakdown in advanced extreme ultraviolet lithography

NASA Astrophysics Data System (ADS)

Nikolsky, Peter; Strolenberg, Chris; Nielsen, Rasmus; Nooitgedacht, Tjitte; Davydova, Natalia; Yang, Greg; Lee, Shawn; Park, Chang-Min; Kim, Insung; Yeo, Jeong-Ho

2013-04-01

As the International Technology Roadmap for Semiconductors critical dimension uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. We will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for advanced extreme ultraviolet (EUV) lithography with 1D (dense lines) and 2D (dense contacts) feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CDs and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples. Mask stack reflectivity variations should also be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We also observed mask error enhancement factor (MEEF) through field fingerprints in the studied EUV cases. Variations of MEEF may play a role towards the total intrafield CDU and may need to be taken into account for EUV lithography. We characterized MEEF-through-field for the reviewed features, with results herein, but further analysis of this phenomenon is required. This comprehensive approach to quantifying the mask part of the overall EUV CDU contribution helps deliver an accurate and integral CDU BB per product/process and litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps extend the limits of Moore's Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y.S.; Deb, S.K.

1990-10-02

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

Solar cells with low cost substrates and process of making same

DOEpatents

Mitchell, Kim W.

1984-01-01

A solar cell having a substrate and an intermediate recrystallized film and a semiconductor material capable of absorbing light with the substrate being selected from one of a synthetic organic resin, graphite, glass and a crystalline material having a grain size less than about 1 micron.sup.2. The intermediate recrystallized film has a grain size in the range of from about 10 microns.sup.2 to about 10,000 microns.sup.2 and a lattice mismatch with the semiconductor material not greater than about 4%. The semiconductor material has a grain size not less than about 10 microns.sup.2. An anti-reflective layer and electrical contact means are provided. Also disclosed is a subcombination of substrate, intermediate recrystallized film and semiconductor material. Also, methods of formulating the solar cell and subcombination are disclosed.

Solar cells with low cost substrates, process of making same and article of manufacture

DOEpatents

Mitchell, K.W.

A solar cell is disclosed having a substrate and an intermediate recrystallized film and a semiconductor material capable of absorbing light with the substrate being selected from one of a synthetic organic resin, graphite, glass and a crystalline material having a grain size less than about 1 micron/sup 2/. The intermediate recrystallized film has a grain size in the range of from about 10 microns/sup 2/ to about 10,000 microns/sup 2/ and a lattice mismatch with the semiconductor material not greater than about 4%. The semiconductor material has a grain size not less than about 10 microns/sup 2/. An anti-reflective layer and electrical contact means are provided. Also disclosed is a subcombination of substrate, intermediate recrystallized film and semiconductor material. Also, methods of formulating the solar cell and subcombination are disclosed.

Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

PubMed

Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

2013-01-02

Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

X-ray lithography using holographic images

DOEpatents

Howells, M.S.; Jacobsen, C.

1997-03-18

Methods for forming X-ray images having 0.25 {micro}m minimum line widths on X-ray sensitive material are presented. A holographic image of a desired circuit pattern is projected onto a wafer or other image-receiving substrate to allow recording of the desired image in photoresist material. In one embodiment, the method uses on-axis transmission and provides a high flux X-ray source having modest monochromaticity and coherence requirements. A layer of light-sensitive photoresist material on a wafer with a selected surface is provided to receive the image(s). The hologram has variable optical thickness and variable associated optical phase angle and amplitude attenuation for transmission of the X-rays. A second embodiment uses off-axis holography. The wafer receives the holographic image by grazing incidence reflection from a hologram printed on a flat metal or other highly reflecting surface or substrate. In this second embodiment, an X-ray beam with a high degree of monochromaticity and spatial coherence is required. 15 figs.

X-ray lithography using holographic images

DOEpatents

Howells, Malcolm S.; Jacobsen, Chris

1997-01-01

Methods for forming X-ray images having 0.25 .mu.m minimum line widths on X-ray sensitive material are presented. A holgraphic image of a desired circuit pattern is projected onto a wafer or other image-receiving substrate to allow recording of the desired image in photoresist material. In one embodiment, the method uses on-axis transmission and provides a high flux X-ray source having modest monochromaticity and coherence requirements. A layer of light-sensitive photoresist material on a wafer with a selected surface is provided to receive the image(s). The hologram has variable optical thickness and variable associated optical phase angle and amplitude attenuation for transmission of the X-rays. A second embodiment uses off-axis holography. The wafer receives the holographic image by grazing incidence reflection from a hologram printed on a flat metal or other highly reflecting surface or substrate. In this second embodiment, an X-ray beam with a high degree of monochromaticity and spatial coherence is required.

Enabling Large Focal Plane Arrays through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Costen, Nick; Benford, Dominic J.

2012-01-01

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Method of manufacturing semiconductor having group II-group VI compounds doped with nitrogen

DOEpatents

Compaan, Alvin D.; Price, Kent J.; Ma, Xianda; Makhratchev, Konstantin

2005-02-08

A method of making a semiconductor comprises depositing a group II-group VI compound onto a substrate in the presence of nitrogen using sputtering to produce a nitrogen-doped semiconductor. This method can be used for making a photovoltaic cell using sputtering to apply a back contact layer of group II-group VI compound to a substrate in the presence of nitrogen, the back coating layer being doped with nitrogen. A semiconductor comprising a group II-group VI compound doped with nitrogen, and a photovoltaic cell comprising a substrate on which is deposited a layer of a group II-group VI compound doped with nitrogen, are also included.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

2003-11-04

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D [Fairfield, CA; Theiss, Steven D [Woodbury, MN; Carey, Paul G [Mountain View, CA; Smith, Patrick M [San Ramon, CA; Wickbold, Paul [Walnut Creek, CA

2006-09-26

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

NASA Astrophysics Data System (ADS)

Pa, Pai-Shan

2010-01-01

A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

High throughput nanoimprint lithography for semiconductor memory applications

NASA Astrophysics Data System (ADS)

Ye, Zhengmao; Zhang, Wei; Khusnatdinov, Niyaz; Stachowiak, Tim; Irving, J. W.; Longsine, Whitney; Traub, Matthew; Fletcher, Brian; Liu, Weijun

2017-03-01

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are two critical components to meeting throughput requirements for imprint lithography. Using a similar approach to what is already done for many deposition and etch processes, imprint stations can be clustered to enhance throughput. The FPA-1200NZ2C is a four station cluster system designed for high volume manufacturing. For a single station, throughput includes overhead, resist dispense, resist fill time (or spread time), exposure and separation. Resist exposure time and mask/wafer separation are well understood processing steps with typical durations on the order of 0.10 to 0.20 seconds. To achieve a total process throughput of 17 wafers per hour (wph) for a single station, it is necessary to complete the fluid fill step in 1.2 seconds. For a throughput of 20 wph, fill time must be reduced to only one 1.1 seconds. There are several parameters that can impact resist filling. Key parameters include resist drop volume (smaller is better), system controls (which address drop spreading after jetting), Design for Imprint or DFI (to accelerate drop spreading) and material engineering (to promote wetting between the resist and underlying adhesion layer). In addition, it is mandatory to maintain fast filling, even for edge field imprinting. In this paper, we address the improvements made in all of these parameters to first enable a 1.20 second filling process for a device like pattern and have demonstrated this capability for both full fields and edge fields. Non-fill defectivity is well under 1.0 defects/cm2 for both field types. Next, by further reducing drop volume and optimizing drop patterns, a fill time of 1.1 seconds was demonstrated.

Apparatus for making photovoltaic devices

DOEpatents

Foote, James B.; Kaake, Steven A. F.; Meyers, Peter V.; Nolan, James F.

1994-12-13

A process and apparatus (70) for making a large area photovoltaic device (22) that is capable of generating low cost electrical power. The apparatus (70) for performing the process includes an enclosure (126) providing a controlled environment in which an oven (156) is located. At least one and preferably a plurality of deposition stations (74,76,78) provide heated vapors of semiconductor material within the oven (156) for continuous elevated temperature deposition of semiconductor material on a sheet substrate (24) including a glass sheet (26) conveyed within the oven. The sheet substrate (24) is conveyed on a roller conveyor (184) within the oven (156) and the semiconductor material whose main layer (82) is cadmium telluride is deposited on an upwardly facing surface (28) of the substrate by each deposition station from a location within the oven above the roller conveyor. A cooling station (86) rapidly cools the substrate (24) after deposition of the semiconductor material thereon to strengthen the glass sheet of the substrate.

Epitaxial growth of CoO films on semiconductor and metal substrates by constructing a complex heterostructure

NASA Astrophysics Data System (ADS)

Entani, S.; Kiguchi, M.; Saiki, K.; Koma, A.

2003-01-01

Epitaxial growth of CoO films was studied using reflection high-energy electron diffraction (RHEED), electron energy loss spectroscopy (EELS), ultraviolet photoelectron spectroscopy (UPS) and Auger electron spectroscopy (AES). The RHEED results indicated that an epitaxial CoO film grew on semiconductor and metal substrates (CoO (0 0 1)∥GaAs (0 0 1), Cu (0 0 1), Ag (0 0 1) and [1 0 0]CoO∥[1 0 0] substrates) by constructing a complex heterostructure with two alkali halide buffer layers. The AES, EELS and UPS results showed that the grown CoO film had almost the same electronic structure as bulk CoO. We could show that use of alkali halide buffer layers was a good way to grow metal oxide films on semiconductor and metal substrates in an O 2 atmosphere. The alkali halide layers not only works as glue to connect very dissimilar materials but also prevents oxidation of metal and semiconductor substrates.

Process for making photovoltaic devices and resultant product

DOEpatents

Foote, James B.; Kaake, Steven A. F.; Meyers, Peter V.; Nolan, James F.

1996-07-16

A process and apparatus (70) for making a large area photovoltaic device (22) that is capable of generating low cost electrical power. The apparatus (70) for performing the process includes an enclosure (126) providing a controlled environment in which an oven (156) is located. At least one and preferably a plurality of deposition stations (74,76,78) provide heated vapors of semiconductor material within the oven (156) for continuous elevated temperature deposition of semiconductor material on a sheet substrate (24) including a glass sheet (26) conveyed within the oven. The sheet substrate (24) is conveyed on a roller conveyor (184) within the oven (156) and the semiconductor material whose main layer (82) is cadmium telluride is deposited on an upwardly facing surface (28) of the substrate by each deposition station from a location within the oven above the roller conveyor. A cooling station (86) rapidly cools the substrate (24) after deposition of the semiconductor material thereon to strengthen the glass sheet of the substrate.

Process for making photovoltaic devices and resultant product

DOEpatents

Foote, James B.; Kaake, Steven A. F.; Meyers, Peter V.; Nolan, James F.

1995-11-28

A process and apparatus (70) for making a large area photovoltaic device (22) that is capable of generating low cost electrical power. The apparatus (70) for performing the process includes an enclosure (126) providing a controlled environment in which an oven (156) is located. At least one and preferably a plurality of deposition stations (74,76,78) provide heated vapors of semiconductor material within the oven (156) for continuous elevated temperature deposition of semiconductor material on a sheet substrate (24) including a glass sheet (26) conveyed within the oven. The sheet substrate (24) is conveyed on a roller conveyor (184) within the oven (156) and the semiconductor material whose main layer (82) is cadmium telluride is deposited on an upwardly facing surface (28) of the substrate by each deposition station from a location within the oven above the roller conveyor. A cooling station (86) rapidly cools the substrate (24) after deposition of the semiconductor material thereon to strengthen the glass sheet of the substrate.

Process for making photovoltaic devices and resultant product

DOEpatents

Foote, James B.; Kaake, Steven A. F.; Meyers, Peter V.; Nolan, James F.

1993-09-28

A process and apparatus (70) for making a large area photovoltaic device (22) that is capable of generating low cost electrical power. The apparatus (70) for performing the process includes an enclosure (126) providing a controlled environment in which an oven (156) is located. At least one and preferably a plurality of deposition stations (74,76,78) provide heated vapors of semiconductor material within the oven (156) for continuous elevated temperature deposition of semiconductor material on a sheet substrate (24) including a glass sheet (26) conveyed within the oven. The sheet substrate (24) is conveyed on a roller conveyor (184) within the oven (156) and the semiconductor material whose main layer (82) is cadmium telluride is deposited on an upwardly facing surface (28) of the substrate by each deposition station from a location within the oven above the roller conveyor. A cooling station (86) rapidly cools the substrate (24) after deposition of the semiconductor material thereon to strengthen the glass sheet of the substrate.

Conductive layer for biaxially oriented semiconductor film growth

DOEpatents

Findikoglu, Alp T.; Matias, Vladimir

2007-10-30

A conductive layer for biaxially oriented semiconductor film growth and a thin film semiconductor structure such as, for example, a photodetector, a photovoltaic cell, or a light emitting diode (LED) that includes a crystallographically oriented semiconducting film disposed on the conductive layer. The thin film semiconductor structure includes: a substrate; a first electrode deposited on the substrate; and a semiconducting layer epitaxially deposited on the first electrode. The first electrode includes a template layer deposited on the substrate and a buffer layer epitaxially deposited on the template layer. The template layer includes a first metal nitride that is electrically conductive and has a rock salt crystal structure, and the buffer layer includes a second metal nitride that is electrically conductive. The semiconducting layer is epitaxially deposited on the buffer layer. A method of making such a thin film semiconductor structure is also described.

Implementation of activity-based costing (ABC) to drive cost reduction efforts in a semiconductor manufacturing operation

NASA Astrophysics Data System (ADS)

Naguib, Hussein; Bol, Igor I.; Lora, J.; Chowdhry, R.

1994-09-01

This paper presents a case study on the implementation of ABC to calculate the cost per wafer and to drive cost reduction efforts for a new IC product line. The cost reduction activities were conducted through the efforts of 11 cross-functional teams which included members of the finance, purchasing, technology development, process engineering, equipment engineering, production control, and facility groups. The activities of these cross functional teams were coordinated by a cost council. It will be shown that these activities have resulted in a 57% reduction in the wafer manufacturing cost of the new product line. Factors contributed to successful implementation of an ABC management system are discussed.

Graphene-Si heterogeneous nanotechnology

NASA Astrophysics Data System (ADS)

Akinwande, Deji; Tao, Li

2013-05-01

It is widely envisioned that graphene, an atomic sheet of carbon that has generated very broad interest has the largest prospects for flexible smart systems and for integrated graphene-silicon (G-Si) heterogeneous very large-scale integrated (VLSI) nanoelectronics. In this work, we focus on the latter and elucidate the research progress that has been achieved for integration of graphene with Si-CMOS including: wafer-scale graphene growth by chemical vapor deposition on Cu/SiO2/Si substrates, wafer-scale graphene transfer that afforded the fabrication of over 10,000 devices, wafer-scalable mitigation strategies to restore graphene's device characteristics via fluoropolymer interaction, and demonstrations of graphene integrated with commercial Si- CMOS chips for hybrid nanoelectronics and sensors. Metrology at the wafer-scale has led to the development of custom Raman processing software (GRISP) now available on the nanohub portal. The metrology reveals that graphene grown on 4-in substrates have monolayer quality comparable to exfoliated flakes. At room temperature, the high-performance passivated graphene devices on SiO2/Si can afford average mobilities 3000cm2/V-s and gate modulation that exceeds an order of magnitude. The latest growth research has yielded graphene with high mobilities greater than 10,000cm2/V-s on oxidized silicon. Further progress requires track compatible graphene-Si integration via wafer bonding in order to translate graphene research from basic to applied research in commercial R and D laboratories to ultimately yield a viable nanotechnology.

Improved field emission properties of carbon nanotubes grown on stainless steel substrate and its application in ionization gauge

NASA Astrophysics Data System (ADS)

Li, Detian; Cheng, Yongjun; Wang, Yongjun; Zhang, Huzhong; Dong, Changkun; Li, Da

2016-03-01

Vertically aligned carbon nanotube (CNT) arrays were fabricated by chemical vapor deposition (CVD) technique on different substrates. Microstructures and field emission characteristics of the as-grown CNT arrays were investigated systematically, and its application in ionization gauge was also evaluated preliminarily. The results indicate that the as-grown CNT arrays are vertically well-aligned relating to the substrate surfaces, but the CNTs grown on stainless steel substrate are longer and more crystalline than the ones grown on silicon wafer substrate. The field emission behaviors of the as-grown CNT arrays are strongly dependent upon substrate properties. Namely, the CNT array grown on stainless steel substrate has better field emission properties, including lower turn on and threshold fields, better emission stability and repeatability, compared with the one grown on silicon wafer substrate. The superior field emission properties of the CNT array grown on stainless steel substrate are mainly attributed to low contact resistance, high thermal conductivity, good adhesion strength, etc. In addition, the metrological behaviors of ionization gauge with the CNT array grown on stainless steel substrate as an electron source were investigated, and this novel cathode ionization gauge extends the lower limit of linear pressure measurement to 10-8 Pa, which is one order of magnitude lower than the result reported for the same of gauge with CNT cathode.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Large-area, laterally-grown epitaxial semiconductor layers

DOEpatents

Han, Jung; Song, Jie; Chen, Danti

2017-07-18

Structures and methods for confined lateral-guided growth of a large-area semiconductor layer on an insulating layer are described. The semiconductor layer may be formed by heteroepitaxial growth from a selective growth area in a vertically-confined, lateral-growth guiding structure. Lateral-growth guiding structures may be formed in arrays over a region of a substrate, so as to cover a majority of the substrate region with laterally-grown epitaxial semiconductor tiles. Quality regions of low-defect, stress-free GaN may be grown on silicon.

Optical devices featuring textured semiconductor layers

DOEpatents

Moustakas, Theodore D [Dover, MA; Cabalu, Jasper S [Cary, NC

2011-10-11

A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor.

Optical devices featuring textured semiconductor layers

DOEpatents

Moustakas, Theodore D [Dover, MA; Cabalu, Jasper S [Cary, NC

2012-08-07

A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor.

Tunnel barrier schottky

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chu, Rongming; Cao, Yu; Li, Zijian

2018-02-20

A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.

ArF scanner performance improvement by using track integrated CD optimization

NASA Astrophysics Data System (ADS)

Huang, Jacky; Yu, Shinn-Sheng; Ke, Chih-Ming; Wu, Timothy; Wang, Yu-Hsi; Gau, Tsai-Sheng; Wang, Dennis; Li, Allen; Yang, Wenge; Kaoru, Araki

2006-03-01

In advanced semiconductor processing, shrinking CD is one of the main objectives when moving to the next generation technology. Improving CD uniformity (CDU) with shrinking CD is one of the biggest challenges. From ArF lithography CD error budget analysis, PEB (post exposure bake) contributes more than 40% CD variations. It turns out that hot plate performance such as CD matching and within-plate temperature control play key roles in litho cell wafer per hour (WPH). Traditionally wired or wireless thermal sensor wafers were used to match and optimize hot plates. However, sensor-to-sensor matching and sensor data quality vs. sensor lifetime or sensor thermal history are still unknown. These concerns make sensor wafers more suitable for coarse mean-temperature adjustment. For precise temperature adjustment, especially within-hot-plate temperature uniformity, using CD instead of sensor wafer temperature is a better and more straightforward metrology to calibrate hot plates. In this study, we evaluated TEL clean track integrated optical CD metrology (IM) combined with TEL CD Optimizer (CDO) software to improve 193-nm resist within-wafer and wafer-to-wafer CD uniformity. Within-wafer CD uniformity is mainly affected by the temperature non-uniformity on the PEB hot plate. Based on CD and PEB sensitivity of photo resists, a physical model has been established to control the CD uniformity through fine-tuning PEB temperature settings. CD data collected by track integrated CD metrology was fed into this model, and the adjustment of PEB setting was calculated and executed through track internal APC system. This auto measurement, auto feed forward, auto calibration and auto adjustment system can reduce the engineer key-in error and improve the hot plate calibration cycle time. And this PEB auto calibration system can easily bring hot-plate-to-hot-plate CD matching to within 0.5nm and within-wafer CDU (3σ) to less than 1.5nm.

Formation of Au nano-patterns on various substrates using simplified nano-transfer printing method

NASA Astrophysics Data System (ADS)

Kim, Jong-Woo; Yang, Ki-Yeon; Hong, Sung-Hoon; Lee, Heon

2008-06-01

For future device applications, fabrication of the metal nano-patterns on various substrates, such as Si wafer, non-planar glass lens and flexible plastic films become important. Among various nano-patterning technologies, nano-transfer print method is one of the simplest techniques to fabricate metal nano-patterns. In nano-transfer printing process, thin Au layer is deposited on flexible PDMS mold, containing surface protrusion patterns, and the Au layer is transferred from PDMS mold to various substrates due to the difference of bonding strength of Au layer to PDMS mold and to the substrate. For effective transfer of Au layer, self-assembled monolayer, which has strong bonding to Au, is deposited on the substrate as a glue layer. In this study, complicated SAM layer coating process was replaced to simple UV/ozone treatment, which can activates the surface and form the -OH radicals. Using simple UV/ozone treatments on both Au and substrate, Au nano-pattern can be successfully transferred to as large as 6 in. diameter Si wafer, without SAM coating process. High fidelity transfer of Au nano-patterns to non-planar glass lens and flexible PET film was also demonstrated.

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

NASA Astrophysics Data System (ADS)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by employing broadband quartz rod-transducer assembles). Experimental results, as predicted by prior rigorous simulations, prove that the temperature measurement accuracy obtained through several dynamic runs using the above specified approach, is better than +/-2°C. Furthermore, these results are highly repeatable and independent of wafer treatment conditions, thereby extolling the versatility and immunity of the new method from environmental conditions.

Soft liquid phase adsorption for fabrication of organic semiconductor films on wettability patterned surfaces.

PubMed

Watanabe, Satoshi; Akiyoshi, Yuri; Matsumoto, Mutsuyoshi

2014-01-01

We report a soft liquid-phase adsorption (SLPA) technique for the fabrication of organic semiconductor films on wettability-patterned substrates using toluene/water emulsions. Wettability-patterned substrates were obtained by the UV-ozone treatment of self-assembled monolayers of silane coupling agents on glass plates using a metal mask. Organic semiconductor polymer films were formed selectively on the hydrophobic part of the wettability-patterned substrates. The thickness of the films fabricated by the SLPA technique is significantly larger than that of the films fabricated by dip-coating and spin-coating techniques. The film thickness can be controlled by adjusting the volume ratio of toluene to water, immersion angle, immersion temperature, and immersion time. The SLPA technique allows for the direct production of organic semiconductor films on wettability-patterned substrates with minimized material consumption and reduced number of fabrication steps.

Power MEMS Development

DTIC Science & Technology

2011-05-01

wafer pair through further processing. Initial cracking issues were identified due to liquid penetration between the wafers during wet processing...free-standing MCD films we needed to address crack formation in the diamond and the Si substrate, which we observed during our initial growths due to...NCD film grown using the heated stage, and finally the thick MCD film grown on the cooled stage. We also found that the control of cracking in the

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

PubMed Central

Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

2016-01-01

High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

A 45° saw-dicing process applied to a glass substrate for wafer-level optical splitter fabrication for optical coherence tomography

NASA Astrophysics Data System (ADS)

Maciel, M. J.; Costa, C. G.; Silva, M. F.; Gonçalves, S. B.; Peixoto, A. C.; Ribeiro, A. Fernando; Wolffenbuttel, R. F.; Correia, J. H.

2016-08-01

This paper reports on the development of a technology for the wafer-level fabrication of an optical Michelson interferometer, which is an essential component in a micro opto-electromechanical system (MOEMS) for a miniaturized optical coherence tomography (OCT) system. The MOEMS consists on a titanium dioxide/silicon dioxide dielectric beam splitter and chromium/gold micro-mirrors. These optical components are deposited on 45° tilted surfaces to allow the horizontal/vertical separation of the incident beam in the final micro-integrated system. The fabrication process consists of 45° saw dicing of a glass substrate and the subsequent deposition of dielectric multilayers and metal layers. The 45° saw dicing is fully characterized in this paper, which also includes an analysis of the roughness. The optimum process results in surfaces with a roughness of 19.76 nm (rms). The actual saw dicing process for a high-quality final surface results as a compromise between the dicing blade’s grit size (#1200) and the cutting speed (0.3 mm s-1). The proposed wafer-level fabrication allows rapid and low-cost processing, high compactness and the possibility of wafer-level alignment/assembly with other optical micro components for OCT integrated imaging.

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer.

PubMed

Yu, Yang; Fong, Patrick W K; Wang, Shifeng; Surya, Charles

2016-11-29

High quality wafer-scale free-standing WS 2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS 2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS 2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS 2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS 2 , which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS 2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm 2 at -1 V which shows superior performances compared to the directly grown WS 2 /GaN heterojunctions.

Real-Time Plasma Process Condition Sensing and Abnormal Process Detection

PubMed Central

Yang, Ryan; Chen, Rongshun

2010-01-01

The plasma process is often used in the fabrication of semiconductor wafers. However, due to the lack of real-time etching control, this may result in some unacceptable process performances and thus leads to significant waste and lower wafer yield. In order to maximize the product wafer yield, a timely and accurately process fault or abnormal detection in a plasma reactor is needed. Optical emission spectroscopy (OES) is one of the most frequently used metrologies in in-situ process monitoring. Even though OES has the advantage of non-invasiveness, it is required to provide a huge amount of information. As a result, the data analysis of OES becomes a big challenge. To accomplish real-time detection, this work employed the sigma matching method technique, which is the time series of OES full spectrum intensity. First, the response model of a healthy plasma spectrum was developed. Then, we defined a matching rate as an indictor for comparing the difference between the tested wafers response and the health sigma model. The experimental results showed that this proposal method can detect process faults in real-time, even in plasma etching tools. PMID:22219683

Diodes of nanocrystalline SiC on n-/n+-type epitaxial crystalline 6H-SiC

NASA Astrophysics Data System (ADS)

Zheng, Junding; Wei, Wensheng; Zhang, Chunxi; He, Mingchang; Li, Chang

2018-03-01

The diodes of nanocrystalline SiC on epitaxial crystalline (n-/n+)6H-SiC wafers were investigated, where the (n+)6H-SiC layer was treated as cathode. For the first unit, a heavily boron doped SiC film as anode was directly deposited by plasma enhanced chemical vapor deposition method on the wafer. As to the second one, an intrinsic SiC film was fabricated to insert between the wafer and the SiC anode. The third one included the SiC anode, an intrinsic SiC layer and a lightly phosphorus doped SiC film besides the wafer. Nanocrystallization in the yielded films was illustrated by means of X-ray diffraction, transmission electronic microscope and Raman spectrum respectively. Current vs. voltage traces of the obtained devices were checked to show as rectifying behaviors of semiconductor diodes, the conduction mechanisms were studied. Reverse recovery current waveforms were detected to analyze the recovery performance. The nanocrystalline SiC films in base region of the fabricated diodes are demonstrated as local regions for lifetime control of minority carriers to improve the reverse recovery properties.

Wafer-scale micro-optics fabrication

NASA Astrophysics Data System (ADS)

Voelkel, Reinhard

2012-07-01

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Ultraclean and Direct Transfer of a Wafer-Scale MoS2 Thin Film onto a Plastic Substrate.

PubMed

Phan, Hoang Danh; Kim, Youngchan; Lee, Jinhwan; Liu, Renlong; Choi, Yongsuk; Cho, Jeong Ho; Lee, Changgu

2017-02-01

An ultraclean method to directly transfer a large-area MoS 2 film from the original growth substrate to a flexible substrate by using epoxy glue is developed. The transferred film is observed to be free of wrinkles and cracks and to be as smooth as the film synthesized on the original substrate. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Photovoltaic devices comprising cadmium stannate transparent conducting films and method for making

DOEpatents

Wu, Xuanzhi; Coutts, Timothy J.; Sheldon, Peter; Rose, Douglas H.

1999-01-01

A photovoltaic device having a substrate, a layer of Cd.sub.2 SnO.sub.4 disposed on said substrate as a front contact, a thin film comprising two or more layers of semiconductor materials disposed on said layer of Cd.sub.2 SnO.sub.4, and an electrically conductive film disposed on said thin film of semiconductor materials to form a rear electrical contact to said thin film. The device is formed by RF sputter coating a Cd.sub.2 SnO.sub.4 layer onto a substrate, depositing a thin film of semiconductor materials onto the layer of Cd.sub.2 SnO.sub.4, and depositing an electrically conductive film onto the thin film of semiconductor materials.

Single closed contact for 0.18-micron photolithography process

NASA Astrophysics Data System (ADS)

Cheung, Cristina; Phan, Khoi A.; Chiu, Robert J.

2000-06-01

With the rapid advances of deep submicron semiconductor technology, identifying defects is converted into a challenge for different modules in the fabrication of chips. Yield engineers often do bitmap on a memory circuit array (SRAM) to identify the failure bits. This is followed by a wafer stripback to look for visual defects at each deprocessed layer for feedback to the Fab. However, to identify the root cause of a problem, Fab engineers must be able to detect similar defects either on the product wafers in process or some short loop test wafers. In the photolithography process, we recognize that the detection of defects is becoming as important as satisfying the critical dimension (CD) of the device. For a multi-level metallization chemically mechanical polish backend process, it is very difficult to detect missing contacts or via at the masking steps due to metal grain roughness, film color variation and/or previous layer defects. Often, photolithography engineer must depend on Photo Cell Monitor (PCM) and short loop experiments for controlling baseline defects and improvement. In this paper, we discuss the findings on the Poly mask PCM and the Contact mask PCM. We present the comparison between the Poly mask and the Contact mask of the I-line Phase Shifted Via mask and DUV mask process for a 0.18 micron process technology. The correlation and the different type of defects between the Contact PCM and the Poly Mask are discussed. The Contact PCM was found to be more sensitive and correlated to contact failure at sort yield better. We also dedicate to study the root cause of a single closed contact hole in the Contact mask short loop experiment for a 0.18 micron process technology. A single closed contact defect was often caused by the developer process, such as bubbles in the line, resist residue left behind, and the rinse mechanism. We also found surfactant solution helps to improve the surface tension of the wafer for the developer process and this prevents/eliminates a single closed contact hole defects. The applications and effects of using different substrates like SiON, different thicknesses of Oxides, and Poly in the Contact Photo Mask is shown. Finally, some defect troubleshooting techniques and the root cause analysis are also discussed.

Dry texturing of solar cells

DOEpatents

Sopori, B.L.

1994-10-25

A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer. The result is a textured backside on an optically reflective, low resistivity alloy interface between the semiconductor substrate and the metal electrical contact layer. 9 figs.

Dry texturing of solar cells

DOEpatents

Sopori, Bhushan L.

1994-01-01

A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer. The result is a textured backside an optically reflective, low resistivity alloy interface between the semiconductor substrate and the metal electrical contact layer.

Method of Manufacturing a Light Emitting, Photovoltaic or Other Electronic Apparatus and System

NASA Technical Reports Server (NTRS)

Blanchard, Richard A. (Inventor); Lewandowski, Mark Allan (Inventor); Frazier, Donald Odell (Inventor); Ray, William Johnstone (Inventor); Fuller, Kirk A. (Inventor); Lowenthal, Mark David (Inventor); Shotton, Neil O. (Inventor)

2014-01-01

The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

Method of manufacturing a light emitting, photovoltaic or other electronic apparatus and system

NASA Technical Reports Server (NTRS)

Fuller, Kirk A. (Inventor); Frazier, Donald Odell (Inventor); Blanchard, Richard A. (Inventor); Lowenthal, Mark D. (Inventor); Lewandowski, Mark Allan (Inventor); Ray, William Johnstone (Inventor); Shotton, Neil O. (Inventor)

2012-01-01

The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

450mm wafer patterning with jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

High efficiency, low cost, thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

2001-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

1999-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

Substrate for thin silicon solar cells

DOEpatents

Ciszek, Theodore F.

1995-01-01

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1.times.10.sup.-3 ohm-cm.

Method of fabricating bifacial tandem solar cells

DOEpatents

Wojtczuk, Steven J; Chiu, Philip T; Zhang, Xuebing; Gagnon, Edward; Timmons, Michael

2014-10-07

A method of fabricating on a semiconductor substrate bifacial tandem solar cells with semiconductor subcells having a lower bandgap than the substrate bandgap on one side of the substrate and with subcells having a higher bandgap than the substrate on the other including, first, growing a lower bandgap subcell on one substrate side that uses only the same periodic table group V material in the dislocation-reducing grading layers and bottom subcells as is present in the substrate and after the initial growth is complete and then flipping the substrate and growing the higher bandgap subcells on the opposite substrate side which can be of different group V material.

Bifacial tandem solar cells

DOEpatents

Wojtczuk, Steven J.; Chiu, Philip T.; Zhang, Xuebing; Gagnon, Edward; Timmons, Michael

2016-06-14

A method of fabricating on a semiconductor substrate bifacial tandem solar cells with semiconductor subcells having a lower bandgap than the substrate bandgap on one side of the substrate and with subcells having a higher bandgap than the substrate on the other including, first, growing a lower bandgap subcell on one substrate side that uses only the same periodic table group V material in the dislocation-reducing grading layers and bottom subcells as is present in the substrate and after the initial growth is complete and then flipping the substrate and growing the higher bandgap subcells on the opposite substrate side which can be of different group V material.

Manufacturing of High-Efficiency Bi-Facial Tandem Concentrator Solar Cells: February 20, 2009--August 20, 2010

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojtczuk , S.

2011-06-01

Spire Semiconductor made concentrator photovoltaic (CPV) cells using a new bi-facial growth process and met both main program goals: a) 42.5% efficiency 500X (AM1.5D, 25C, 100mW/cm2); and b) Ready to supply at least 3MW/year of such cells at end of program. We explored a unique simple fabrication process to make a N/P 3-junction InGaP/GaAs/InGaAs tandem cells . First, the InGaAs bottom cell is grown on the back of a GaAs wafer. The wafers are then loaded into a cassette, spin-rinsed to remove particles, dipped in dilute NH4OH and spin-dried. The wafers are then removed from the cassette loaded the reactormore » for GaAs middle and InGaP top cell growth on the opposite wafer face (bi-facial growth). By making the epitaxial growth process a bit more complex, we are able to avoid more complex processing (such as large area wafer bonding or epitaxial liftoff) used in the inverted metamorphic (IMM) approach to make similar tandem stacks. We believe the yield is improved compared to an IMM process. After bi-facial epigrowth, standard III-V cell steps (back metal, photolithography for front grid, cap etch, AR coat, dice) are used in the remainder of the process.« less

Radiation-tolerant imaging device

DOEpatents

Colella, N.J.; Kimbrough, J.R.

1996-11-19

A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO{sub 2} insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron`s generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO{sub 2} layer. 7 figs.

Radiation-tolerant imaging device

DOEpatents

Colella, Nicholas J.; Kimbrough, Joseph R.

1996-01-01

A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO.sub.2 insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron's generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO.sub.2 layer.

Large scale integration of graphene transistors for potential applications in the back end of the line

NASA Astrophysics Data System (ADS)

Smith, A. D.; Vaziri, S.; Rodriguez, S.; Östling, M.; Lemme, M. C.

2015-06-01

A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm2 V-1 s-1. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Investigation of hyper-NA scanner emulation for photomask CDU performance

NASA Astrophysics Data System (ADS)

Poortinga, Eric; Scheruebl, Thomas; Conley, Will; Sundermann, Frank

2007-02-01

As the semiconductor industry moves toward immersion lithography using numerical apertures above 1.0 the quality of the photomask becomes even more crucial. Photomask specifications are driven by the critical dimension (CD) metrology within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately, tolerances of device electrical properties drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process, and photomask quality. Tightening of photomask specifications is one mechanism for meeting the wafer CD targets. The challenge lies in determining how photomask level metrology results influence wafer level imaging performance. Can it be inferred that photomask level CD performance is the direct contributor to wafer level CD performance? With respect to phase shift masks, criteria such as phase and transmission control are generally tightened with each technology node. Are there other photomask relevant influences that effect wafer CD performance? A comprehensive study is presented supporting the use of scanner emulation based photomask CD metrology to predict wafer level within chip CD uniformity (CDU). Using scanner emulation with the photomask can provide more accurate wafer level prediction because it inherently includes all contributors to image formation related to the 3D topography such as the physical CD, phase, transmission, sidewall angle, surface roughness, and other material properties. Emulated images from different photomask types were captured to provide CD values across chip. Emulated scanner image measurements were completed using an AIMS TM45-193i with its hyper-NA, through-pellicle data acquisition capability including the Global CDU Map TM software option for AIMS TM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CDU data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using scanner emulation based photomask CD metrology.

Inspection of imprint lithography patterns for semiconductor and patterned media

NASA Astrophysics Data System (ADS)

Resnick, Douglas J.; Haase, Gaddi; Singh, Lovejeet; Curran, David; Schmid, Gerard M.; Luo, Kang; Brooks, Cindy; Selinidis, Kosta; Fretwell, John; Sreenivasan, S. V.

2010-03-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This work summarizes the results of defect inspections of semiconductor masks, wafers and hard disks patterned using Jet and Flash Imprint Lithography (J-FILTM). Inspections were performed with optical and e-beam based automated inspection tools. For the semiconductor market, a test mask was designed which included dense features (with half pitches ranging between 32 nm and 48 nm) containing an extensive array of programmed defects. For this work, both e-beam inspection and optical inspection were used to detect both random defects and the programmed defects. Analytical SEMs were then used to review the defects detected by the inspection. Defect trends over the course of many wafers were observed with another test mask using a KLA-T 2132 optical inspection tool. The primary source of defects over 2000 imprints were particle related. For the hard drive market, it is important to understand the defectivity of both the template and the imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity, scattered light, phase shift, etc. Defects that have been identified in this manner are further characterized according to the morphology

Photoresist removal using gaseous sulfur trioxide cleaning technology

NASA Astrophysics Data System (ADS)

Del Puppo, Helene; Bocian, Paul B.; Waleh, Ahmad

1999-06-01

A novel cleaning method for removing photoresists and organic polymers from semiconductor wafers is described. This non-plasma method uses anhydrous sulfur trioxide gas in a two-step process, during which, the substrate is first exposed to SO3 vapor at relatively low temperatures and then is rinsed with de-ionized water. The process is radically different from conventional plasma-ashing methods in that the photoresist is not etched or removed during the exposure to SO3. Rather, the removal of the modified photoresist takes place during the subsequent DI-water rinse step. The SO3 process completely removes photoresist and polymer residues in many post-etch applications. Additional advantages of the process are absence of halogen gases and elimination of the need for other solvents and wet chemicals. The process also enjoys a very low cost of ownership and has minimal environmental impact. The SEM and SIMS surface analysis results are presented to show the effectiveness of gaseous SO3 process after polysilicon, metal an oxide etch applications. The effects of both chlorine- and fluorine-based plasma chemistries on resist removal are described.

CMOS-Compatible Fabrication for Photonic Crystal-Based Nanofluidic Structure.

PubMed

Peng, Wang; Chen, Youping; Ai, Wu; Zhang, Dailin; Song, Han; Xiong, Hui; Huang, Pengcheng

2017-12-01

Photonic crystal (PC)-based devices have been widely used since 1990s, while PC has just stepped into the research area of nanofluidic. In this paper, photonic crystal had been used as a complementary metal oxide semiconductors (CMOS) compatible part to create a nanofluidic structure. A nanofluidic structure prototype had been fabricated with CMOS-compatible techniques. The nanofluidic channels were sealed by direct bonding polydimethylsiloxane (PDMS) and the periodic gratings on photonic crystal structure. The PC was fabricated on a 4-in. Si wafer with Si 3 N 4 as the guided mode layer and SiO 2 film as substrate layer. The higher order mode resonance wavelength of PC-based nanofluidic structure had been selected, which can confine the enhanced electrical field located inside the nanochannel area. A design flow chart was used to guide the fabrication process. By optimizing the fabrication device parameters, the periodic grating of PC-based nanofluidic structure had a high-fidelity profile with fill factor at 0.5. The enhanced electric field was optimized and located within the channel area, and it can be used for PC-based nanofluidic applications with high performance.

Uncovering the Physical Basis Connecting Environment and Tribological Performance of Ultrananocrystalline Diamond

DTIC Science & Technology

2014-04-17

measured with an infrared pyrometer (550-3200°C). The substrates were coated with diamond nanoparticles (ITC Inc.) which serve as nucleation sites...wafers were seeded with nano-diamond particles prior to film growth to provide nucleation sites for diamond growth. To study the effect of surface...wafers are appropriate to generate uniform seeding. AFM tips were seeded with nano-diamond particles prior to coating with NCD to provide nucleation

A study of doping influences on transmission of large-diameter gallium antimonide substrates for long-wave (LWIR) to very long wavelength (VLWIR) infra-red applications

NASA Astrophysics Data System (ADS)

Martinez, Rebecca; Tybjerg, Marius; Smith, Brian; Mowbray, Andrew; Furlong, Mark J.

2015-06-01

Gallium antimonide (GaSb) is an important Group III-V compound semiconductor for infra-red (IR) photodetectors used in sensing and imaging applications. Operating in the mid (3-5 μm) to long wavelength region (8-12 μm) of the IR spectrum, the application of GaSb detectors is extensive, encompassing military, industrial, medical and environmental uses. A significant developing technology for GaSb based detectors are those effective in the very long wavelength (VLWIR) infra-red region (13 μm and beyond) which are advantageous in space and stealth based applications which necessitate high operating temperatures. In this study different doping levels of GaSb are considered and the IR transmission spectra examined by Fourier Transform IR analysis. GaSb n-type doped material consistent in delivering long to very long wavelength transmission is demonstrated which is preferable to p-type material which requires backside thinning for IR transmission. Czochralski (Cz) grown GaSb wafers are assessed for electrical quality and uniformity results, on Hall mobility, resistivity and carrier level reported. Results of this work will establish the carrier concentration that ultimately results in high transparency substrates. In summary enhancements in IR transmission will be shown to be achieved in GaSb bulk crystals by tellurium (Te) compensation.

Mg2Sn heterostructures on Si(111) substrate

NASA Astrophysics Data System (ADS)

Dózsa, L.; Galkin, N. G.; Pécz, B.; Osváth, Z.; Zolnai, Zs.; Németh, A.; Galkin, K. N.; Chernev, I. M.; Dotsenko, S. A.

2017-05-01

Thin un-doped and Al doped polycrystalline Mg-stannide films consisting mainly of Mg2Sn semiconductor phase have been grown by deposition of Sn-Mg multilayers on Si(111) p-type wafers at room temperature and annealing at 150 °C. Rutherford backscattering measurement spectroscopy (RBS) were used to determine the amount of Mg and Sn in the structures. Raman spectroscopy has shown the layers contain Mg2Sn phase. Cross sectional transmission electron microscopy (XTEM) measurements have identified Mg2Sn nanocrystallites in hexagonal and cubic phases without epitaxial orientation with respect to the Si(111) substrate. Significant oxygen concentration was found in the layer both by RBS and TEM. The electrical measurements have shown laterally homogeneous conductivity in the grown layer. The undoped Mg2Sn layers show increasing resistivity with increasing temperature indicating the scattering process dominates the resistance of the layers, i.e. large concentration of point defects was generated in the layer during the growth process. The Al doped layer shows increase of the resistance at low temperature caused by freeze out of free carriers in the Al doped Mg2Sn layer. The measurements indicate the necessity of protective layer grown over the Mg2Sn layers, and a short time delay between sample preparation and cross sectionalTEM analysis, since the unprotected layer is degraded by the interaction with the ambient.

Electrochemical Deposition of Conformal and Functional Layers on High Aspect Ratio Silicon Micro/Nanowires.

PubMed

Ozel, Tuncay; Zhang, Benjamin A; Gao, Ruixuan; Day, Robert W; Lieber, Charles M; Nocera, Daniel G

2017-07-12

Development of new synthetic methods for the modification of nanostructures has accelerated materials design advances to furnish complex architectures. Structures based on one-dimensional (1D) silicon (Si) structures synthesized using top-down and bottom-up methods are especially prominent for diverse applications in chemistry, physics, and medicine. Yet further elaboration of these structures with distinct metal-based and polymeric materials, which could open up new opportunities, has been difficult. We present a general electrochemical method for the deposition of conformal layers of various materials onto high aspect ratio Si micro- and nanowire arrays. The electrochemical deposition of a library of coaxial layers comprising metals, metal oxides, and organic/inorganic semiconductors demonstrate the materials generality of the synthesis technique. Depositions may be performed on wire arrays with varying diameter (70 nm to 4 μm), pitch (5 μ to 15 μ), aspect ratio (4:1 to 75:1), shape (cylindrical, conical, hourglass), resistivity (0.001-0.01 to 1-10 ohm/cm 2 ), and substrate orientation. Anisotropic physical etching of wires with one or more coaxial shells yields 1D structures with exposed tips that can be further site-specifically modified by an electrochemical deposition approach. The electrochemical deposition methodology described herein features a wafer-scale synthesis platform for the preparation of multifunctional nanoscale devices based on a 1D Si substrate.